From 34d3a1dbb6628b61c08396f2b7d4a5511289e125 Mon Sep 17 00:00:00 2001 From: ivanovborislav <81085106+ivanovborislav@users.noreply.github.com> Date: Sun, 21 Nov 2021 14:45:32 +0200 Subject: [PATCH] Add files via upload --- hal/phydm/txbf/halcomtxbf.c | 520 ++++++++++ hal/phydm/txbf/halcomtxbf.h | 183 ++++ hal/phydm/txbf/haltxbf8192e.c | 384 +++++++ hal/phydm/txbf/haltxbf8192e.h | 71 ++ hal/phydm/txbf/haltxbf8814a.c | 675 ++++++++++++ hal/phydm/txbf/haltxbf8814a.h | 77 ++ hal/phydm/txbf/haltxbf8822b.c | 1088 ++++++++++++++++++++ hal/phydm/txbf/haltxbf8822b.h | 78 ++ hal/phydm/txbf/haltxbfinterface.c | 1484 +++++++++++++++++++++++++++ hal/phydm/txbf/haltxbfinterface.h | 167 +++ hal/phydm/txbf/haltxbfjaguar.c | 509 +++++++++ hal/phydm/txbf/haltxbfjaguar.h | 78 ++ hal/phydm/txbf/phydm_hal_txbf_api.c | 759 ++++++++++++++ hal/phydm/txbf/phydm_hal_txbf_api.h | 89 ++ 14 files changed, 6162 insertions(+) create mode 100644 hal/phydm/txbf/halcomtxbf.c create mode 100644 hal/phydm/txbf/halcomtxbf.h create mode 100644 hal/phydm/txbf/haltxbf8192e.c create mode 100644 hal/phydm/txbf/haltxbf8192e.h create mode 100644 hal/phydm/txbf/haltxbf8814a.c create mode 100644 hal/phydm/txbf/haltxbf8814a.h create mode 100644 hal/phydm/txbf/haltxbf8822b.c create mode 100644 hal/phydm/txbf/haltxbf8822b.h create mode 100644 hal/phydm/txbf/haltxbfinterface.c create mode 100644 hal/phydm/txbf/haltxbfinterface.h create mode 100644 hal/phydm/txbf/haltxbfjaguar.c create mode 100644 hal/phydm/txbf/haltxbfjaguar.h create mode 100644 hal/phydm/txbf/phydm_hal_txbf_api.c create mode 100644 hal/phydm/txbf/phydm_hal_txbf_api.h diff --git a/hal/phydm/txbf/halcomtxbf.c b/hal/phydm/txbf/halcomtxbf.c new file mode 100644 index 0000000..ae45a5b --- /dev/null +++ b/hal/phydm/txbf/halcomtxbf.c @@ -0,0 +1,520 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/*@************************************************************ + * Description: + * + * This file is for TXBF mechanism + * + ************************************************************/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef PHYDM_BEAMFORMING_SUPPORT +/*@Beamforming halcomtxbf API create by YuChen 2015/05*/ + +void hal_com_txbf_beamform_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_iqgen_setting_ok = false; + + if (dm->support_ic_type & ODM_RTL8814A) { + is_iqgen_setting_ok = phydm_beamforming_set_iqgen_8814A(dm); + PHYDM_DBG(dm, DBG_TXBF, "[%s] is_iqgen_setting_ok = %d\n", + __func__, is_iqgen_setting_ok); + } +} + +/*Only used for MU BFer Entry when get GID management frame (self as MU STA)*/ +void hal_com_txbf_config_gtab( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_config_gtab(dm); +} + +void phydm_beamform_set_sounding_enter( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_enter_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_enter_work_item); +#else + hal_com_txbf_enter_work_item_callback(dm); +#endif +} + +void phydm_beamform_set_sounding_leave( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_leave_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_leave_work_item); +#else + hal_com_txbf_leave_work_item_callback(dm); +#endif +} + +void phydm_beamform_set_sounding_rate( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_rate_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_rate_work_item); +#else + hal_com_txbf_rate_work_item_callback(dm); +#endif +} + +void phydm_beamform_set_sounding_status( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_status_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_status_work_item); +#else + hal_com_txbf_status_work_item_callback(dm); +#endif +} + +void phydm_beamform_set_sounding_fw_ndpa( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + if (*dm->is_fw_dw_rsvd_page_in_progress) + odm_set_timer(dm, &p_txbf_info->txbf_fw_ndpa_timer, 5); + else + odm_schedule_work_item(&p_txbf_info->txbf_fw_ndpa_work_item); +#else + hal_com_txbf_fw_ndpa_work_item_callback(dm); +#endif +} + +void phydm_beamform_set_sounding_clk( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + if (!odm_is_work_item_scheduled(&p_txbf_info->txbf_clk_work_item)) + odm_schedule_work_item(&p_txbf_info->txbf_clk_work_item); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + phydm_run_in_thread_cmd(dm, hal_com_txbf_clk_work_item_callback, dm); +#else + hal_com_txbf_clk_work_item_callback(dm); +#endif +} + +void phydm_beamform_set_reset_tx_path( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_reset_tx_path_work_item; + + if (!odm_is_work_item_scheduled(pwi)) + odm_schedule_work_item(pwi); +#else + hal_com_txbf_reset_tx_path_work_item_callback(dm); +#endif +} + +void phydm_beamform_set_get_tx_rate( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + struct _RT_WORK_ITEM *pwi = &p_txbf_info->txbf_get_tx_rate_work_item; + + if (!odm_is_work_item_scheduled(pwi)) + odm_schedule_work_item(pwi); +#else + hal_com_txbf_get_tx_rate_work_item_callback(dm); +#endif +} + +void hal_com_txbf_enter_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + u8 idx = p_txbf_info->txbf_idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_enter(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_enter(dm, idx); +} + +void hal_com_txbf_leave_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + u8 idx = p_txbf_info->txbf_idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_leave(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_leave(dm, idx); +} + +void hal_com_txbf_fw_ndpa_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + u8 idx = p_txbf_info->ndpa_idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_fw_txbf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_fw_tx_bf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_fw_txbf(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_fw_txbf(dm, idx); +} + +void hal_com_txbf_clk_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & ODM_RTL8812) + hal_txbf_jaguar_clk_8812a(dm); +} + +void hal_com_txbf_rate_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + u8 BW = p_txbf_info->BW; + u8 rate = p_txbf_info->rate; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & ODM_RTL8812) + hal_txbf_8812a_set_ndpa_rate(dm, BW, rate); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_set_ndpa_rate(dm, BW, rate); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_set_ndpa_rate(dm, BW, rate); +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void hal_com_txbf_fw_ndpa_timer_callback( + struct phydm_timer_list *timer) +{ + void *adapter = (void *)timer->Adapter; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (*dm->is_fw_dw_rsvd_page_in_progress) + odm_set_timer(dm, &(p_txbf_info->txbf_fw_ndpa_timer), 5); + else + odm_schedule_work_item(&(p_txbf_info->txbf_fw_ndpa_work_item)); +} +#endif + +void hal_com_txbf_status_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + u8 idx = p_txbf_info->txbf_idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) + hal_txbf_jaguar_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8192E) + hal_txbf_8192e_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_status(dm, idx); + else if (dm->support_ic_type & ODM_RTL8822B) + hal_txbf_8822b_status(dm, idx); +} + +void hal_com_txbf_reset_tx_path_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + u8 idx = p_txbf_info->txbf_idx; + + if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_reset_tx_path(dm, idx); +} + +void hal_com_txbf_get_tx_rate_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; +#else + struct dm_struct *dm = (struct dm_struct *)dm_void; +#endif + + if (dm->support_ic_type & ODM_RTL8814A) + hal_txbf_8814a_get_tx_rate(dm); +} + +boolean +hal_com_txbf_set( + void *dm_void, + u8 set_type, + void *p_in_buf) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 *p_u1_tmp = (u8 *)p_in_buf; + struct _HAL_TXBF_INFO *p_txbf_info = &dm->beamforming_info.txbf_info; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] set_type = 0x%X\n", __func__, set_type); + + switch (set_type) { + case TXBF_SET_SOUNDING_ENTER: + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_sounding_enter(dm); + break; + + case TXBF_SET_SOUNDING_LEAVE: + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_sounding_leave(dm); + break; + + case TXBF_SET_SOUNDING_RATE: + p_txbf_info->BW = p_u1_tmp[0]; + p_txbf_info->rate = p_u1_tmp[1]; + phydm_beamform_set_sounding_rate(dm); + break; + + case TXBF_SET_SOUNDING_STATUS: + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_sounding_status(dm); + break; + + case TXBF_SET_SOUNDING_FW_NDPA: + p_txbf_info->ndpa_idx = *p_u1_tmp; + phydm_beamform_set_sounding_fw_ndpa(dm); + break; + + case TXBF_SET_SOUNDING_CLK: + phydm_beamform_set_sounding_clk(dm); + break; + + case TXBF_SET_TX_PATH_RESET: + p_txbf_info->txbf_idx = *p_u1_tmp; + phydm_beamform_set_reset_tx_path(dm); + break; + + case TXBF_SET_GET_TX_RATE: + phydm_beamform_set_get_tx_rate(dm); + break; + } + + return true; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +boolean +hal_com_txbf_get( + void *adapter, + u8 get_type, + void *p_out_buf) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + boolean *p_boolean = (boolean *)p_out_buf; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (get_type == TXBF_GET_EXPLICIT_BEAMFORMEE) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter)) + *p_boolean = false; + else if (/*@IS_HARDWARE_TYPE_8822B(adapter) ||*/ + IS_HARDWARE_TYPE_8821B(adapter) || + IS_HARDWARE_TYPE_8192E(adapter) || + IS_HARDWARE_TYPE_8192F(adapter) || + IS_HARDWARE_TYPE_JAGUAR(adapter) || + IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) || + IS_HARDWARE_TYPE_JAGUAR3(adapter)) + *p_boolean = true; + else + *p_boolean = false; + } else if (get_type == TXBF_GET_EXPLICIT_BEAMFORMER) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(adapter)) + *p_boolean = false; + else if (/*@IS_HARDWARE_TYPE_8822B(adapter) ||*/ + IS_HARDWARE_TYPE_8821B(adapter) || + IS_HARDWARE_TYPE_8192E(adapter) || + IS_HARDWARE_TYPE_8192F(adapter) || + IS_HARDWARE_TYPE_JAGUAR(adapter) || + IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter) || + IS_HARDWARE_TYPE_JAGUAR3(adapter)) { + if (hal_data->RF_Type == RF_2T2R || + hal_data->RF_Type == RF_3T3R || + hal_data->RF_Type == RF_4T4R) + *p_boolean = true; + else + *p_boolean = false; + } else + *p_boolean = false; + } else if (get_type == TXBF_GET_MU_MIMO_STA) { +#if ((RTL8822B_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) ||\ + (RTL8822C_SUPPORT == 1)) + if (IS_HARDWARE_TYPE_8822B(adapter) || + IS_HARDWARE_TYPE_8821C(adapter) || + IS_HARDWARE_TYPE_JAGUAR3(adapter)) + *p_boolean = true; + else +#endif + *p_boolean = false; + + } else if (get_type == TXBF_GET_MU_MIMO_AP) { +#if ((RTL8822B_SUPPORT == 1) || (RTL8822C_SUPPORT == 1)) + if (IS_HARDWARE_TYPE_8822B(adapter) || + IS_HARDWARE_TYPE_JAGUAR3(adapter)) + *p_boolean = true; + else +#endif + *p_boolean = false; + } + + return true; +} +#endif + +#endif diff --git a/hal/phydm/txbf/halcomtxbf.h b/hal/phydm/txbf/halcomtxbf.h new file mode 100644 index 0000000..5ad3033 --- /dev/null +++ b/hal/phydm/txbf/halcomtxbf.h @@ -0,0 +1,183 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HAL_COM_TXBF_H__ +#define __HAL_COM_TXBF_H__ + +#if 0 +typedef bool +(*TXBF_GET)( + void* adapter, + u8 get_type, + void* p_out_buf + ); + +typedef bool +(*TXBF_SET)( + void* adapter, + u8 set_type, + void* p_in_buf + ); +#endif + +enum txbf_set_type { + TXBF_SET_SOUNDING_ENTER, + TXBF_SET_SOUNDING_LEAVE, + TXBF_SET_SOUNDING_RATE, + TXBF_SET_SOUNDING_STATUS, + TXBF_SET_SOUNDING_FW_NDPA, + TXBF_SET_SOUNDING_CLK, + TXBF_SET_TX_PATH_RESET, + TXBF_SET_GET_TX_RATE +}; + +enum txbf_get_type { + TXBF_GET_EXPLICIT_BEAMFORMEE, + TXBF_GET_EXPLICIT_BEAMFORMER, + TXBF_GET_MU_MIMO_STA, + TXBF_GET_MU_MIMO_AP +}; + +/* @2 HAL TXBF related */ +struct _HAL_TXBF_INFO { + u8 txbf_idx; + u8 ndpa_idx; + u8 BW; + u8 rate; + + struct phydm_timer_list txbf_fw_ndpa_timer; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM txbf_enter_work_item; + RT_WORK_ITEM txbf_leave_work_item; + RT_WORK_ITEM txbf_fw_ndpa_work_item; + RT_WORK_ITEM txbf_clk_work_item; + RT_WORK_ITEM txbf_status_work_item; + RT_WORK_ITEM txbf_rate_work_item; + RT_WORK_ITEM txbf_reset_tx_path_work_item; + RT_WORK_ITEM txbf_get_tx_rate_work_item; +#endif +}; + +#ifdef PHYDM_BEAMFORMING_SUPPORT + +void hal_com_txbf_beamform_init( + void *dm_void); + +void hal_com_txbf_config_gtab( + void *dm_void); + +void hal_com_txbf_enter_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +void hal_com_txbf_leave_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +void hal_com_txbf_fw_ndpa_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +void hal_com_txbf_clk_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +void hal_com_txbf_reset_tx_path_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +void hal_com_txbf_get_tx_rate_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +void hal_com_txbf_rate_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +void hal_com_txbf_fw_ndpa_timer_callback( + struct phydm_timer_list *timer); + +void hal_com_txbf_status_work_item_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter +#else + void *dm_void +#endif + ); + +boolean +hal_com_txbf_set( + void *dm_void, + u8 set_type, + void *p_in_buf); + +boolean +hal_com_txbf_get( + void *adapter, + u8 get_type, + void *p_out_buf); + +#else +#define hal_com_txbf_beamform_init(dm_void) NULL +#define hal_com_txbf_config_gtab(dm_void) NULL +#define hal_com_txbf_enter_work_item_callback(_adapter) NULL +#define hal_com_txbf_leave_work_item_callback(_adapter) NULL +#define hal_com_txbf_fw_ndpa_work_item_callback(_adapter) NULL +#define hal_com_txbf_clk_work_item_callback(_adapter) NULL +#define hal_com_txbf_rate_work_item_callback(_adapter) NULL +#define hal_com_txbf_fw_ndpa_timer_callback(_adapter) NULL +#define hal_com_txbf_status_work_item_callback(_adapter) NULL +#define hal_com_txbf_get(_adapter, _get_type, _pout_buf) + +#endif + +#endif /* @#ifndef __HAL_COM_TXBF_H__ */ diff --git a/hal/phydm/txbf/haltxbf8192e.c b/hal/phydm/txbf/haltxbf8192e.c new file mode 100644 index 0000000..daac3e5 --- /dev/null +++ b/hal/phydm/txbf/haltxbf8192e.c @@ -0,0 +1,384 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/************************************************************* + * Description: + * + * This file is for 8192E TXBF mechanism + * + ************************************************************/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (RTL8192E_SUPPORT == 1) + +void hal_txbf_8192e_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW)); +} + +void hal_txbf_8192e_rf_mode( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (dm->rf_type == RF_1T1R) + return; + + odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + + if (beam_info->beamformee_su_cnt > 0) { + /*Path_A*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/ + /*Path_B*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/ + } else { + /*Path_A*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/ + /*Path_B*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/ + } + + odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + + if (beam_info->beamformee_su_cnt > 0) { + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333); + odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1); + } else + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313); +} + +void hal_txbf_8192e_fw_txbf_cmd( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx, period0 = 0, period1 = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (idx == 0) { + if (beam_info->beamformee_entry[idx].is_sound) + PageNum0 = 0xFE; + else + PageNum0 = 0xFF; /* stop sounding */ + period0 = (u8)(beam_info->beamformee_entry[idx].sound_period); + } else if (idx == 1) { + if (beam_info->beamformee_entry[idx].is_sound) + PageNum1 = 0xFE; + else + PageNum1 = 0xFF; /* stop sounding */ + period1 = (u8)(beam_info->beamformee_entry[idx].sound_period); + } + } + } + + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = (period1 << 4) | period0; + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", + __func__, PageNum0, period0, PageNum1, period1); +} + +void hal_txbf_8192e_download_ndpa( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + boolean is_send_beacon = false; + u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; + /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *dm->is_fw_dw_rsvd_page_in_progress = true; +#endif + if (idx == 0) + head_page = 0xFE; + else + head_page = 0xFE; + + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1); + odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0))); + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6))); + + if (tmp_reg422 & BIT(6)) { + PHYDM_DBG(dm, DBG_TXBF, + "%s There is an adapter is sending beacon.\n", + __func__); + is_send_beacon = true; + } + + /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/ + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page); + + do { + /*@Clear beacon valid check bit.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2); + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0))); + + /* @download NDPA rsvd page. */ + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if (dm->support_interface == ODM_ITRF_PCIE) { + u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3); + count = 0; + while ((count < 20) && (u1b_tmp & BIT(4))) { + count++; + ODM_delay_us(10); + u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3); + } + odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4)); + } +#endif + + /*@check rsvd page download OK.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2); + count = 0; + while (!(bcn_valid_reg & BIT(0)) && count < 20) { + count++; + ODM_delay_us(10); + bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2); + } + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); + + if (!(bcn_valid_reg & BIT(0))) + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", + __func__); + + /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/ + odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ + /*the beacon cannot be sent by HW.*/ + /*@2010.06.23. Added by tynli.*/ + if (is_send_beacon) + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422); + + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1); + odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0)))); + + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *dm->is_fw_dw_rsvd_page_in_progress = false; +#endif +} + +void hal_txbf_8192e_enter( + void *dm_void, + u8 bfer_bfee_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u32 csi_param; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + hal_txbf_8192e_rf_mode(dm, beamforming_info); + + if (dm->rf_type == RF_2T2R) + odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/ + + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; + + /*Sounding protocol control*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB); + + /*@MAC address/Partial AID of Beamformer*/ + if (bfer_idx == 0) { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]); + } else { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]); + } + + /*@CSI report parameters of Beamformer Default use nc = 2*/ + csi_param = 0x03090309; + + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param); + + /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50); + } + + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; + + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + sta_id = beamformee_entry.mac_id; + else + sta_id = beamformee_entry.p_aid; + + PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__, + sta_id); + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (bfee_idx == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7)); + } else + odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); + + /*@CSI report parameters of Beamformee*/ + if (bfee_idx == 0) { + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3; + + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9)); + } else { + /*Set BIT25*/ + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200); + } + phydm_beamforming_notify(dm); + } +} + +void hal_txbf_8192e_leave( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + hal_txbf_8192e_rf_mode(dm, beam_info); + + /* @Clear P_AID of Beamformee + * Clear MAC addresss of Beamformer + * Clear Associated Bfmee Sel + */ + if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE) + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8); + + if (idx == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); + } else { + odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000); + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60); + } + + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx); +} + +void hal_txbf_8192e_status( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx]; + + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry.mac_id; + else + beam_ctrl_val = beamform_entry.p_aid; + + if (idx == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8192E; + else { + beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); + } + + if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) { + if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= BIT(10); + } else + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); + + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__, + idx, beam_ctrl_reg, beam_ctrl_val); +} + +void hal_txbf_8192e_fw_tx_bf( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_8192e_download_ndpa(dm, idx); + + hal_txbf_8192e_fw_txbf_cmd(dm); +} + +#endif /* @#if (RTL8192E_SUPPORT == 1)*/ + +#endif diff --git a/hal/phydm/txbf/haltxbf8192e.h b/hal/phydm/txbf/haltxbf8192e.h new file mode 100644 index 0000000..9b0c832 --- /dev/null +++ b/hal/phydm/txbf/haltxbf8192e.h @@ -0,0 +1,71 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HAL_TXBF_8192E_H__ +#define __HAL_TXBF_8192E_H__ + +#if (RTL8192E_SUPPORT == 1) +#ifdef PHYDM_BEAMFORMING_SUPPORT + +void hal_txbf_8192e_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate); + +void hal_txbf_8192e_enter( + void *dm_void, + u8 idx); + +void hal_txbf_8192e_leave( + void *dm_void, + u8 idx); + +void hal_txbf_8192e_status( + void *dm_void, + u8 idx); + +void hal_txbf_8192e_fw_tx_bf( + void *dm_void, + u8 idx); +#else + +#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8192e_enter(dm_void, idx) +#define hal_txbf_8192e_leave(dm_void, idx) +#define hal_txbf_8192e_status(dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(dm_void, idx) + +#endif + +#else + +#define hal_txbf_8192e_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8192e_enter(dm_void, idx) +#define hal_txbf_8192e_leave(dm_void, idx) +#define hal_txbf_8192e_status(dm_void, idx) +#define hal_txbf_8192e_fw_tx_bf(dm_void, idx) + +#endif + +#endif diff --git a/hal/phydm/txbf/haltxbf8814a.c b/hal/phydm/txbf/haltxbf8814a.c new file mode 100644 index 0000000..7ad6ca9 --- /dev/null +++ b/hal/phydm/txbf/haltxbf8814a.c @@ -0,0 +1,675 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * Description: + * + * This file is for 8814A TXBF mechanism + * + * ************************************************************ */ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (RTL8814A_SUPPORT == 1) + +boolean +phydm_beamforming_set_iqgen_8814A(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u16 counter = 0; + u32 rf_mode[4]; + + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/ + + while (1) { + counter++; + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_RCK_OS, 0xfffff, 0x18000); /*Select Rx mode*/ + + ODM_delay_us(2); + + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + rf_mode[i] = odm_get_rf_reg(dm, i, RF_RCK_OS, 0xfffff); + + if (rf_mode[0] == 0x18000 && rf_mode[1] == 0x18000 && rf_mode[2] == 0x18000 && rf_mode[3] == 0x18000) + break; + else if (counter == 100) { + PHYDM_DBG(dm, DBG_TXBF, "iqgen setting fail:8814A\n"); + return false; + } + } + + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) { + odm_set_rf_reg(dm, i, RF_TXPA_G1, 0xfffff, 0xBE77F); /*Set Table data*/ + odm_set_rf_reg(dm, i, RF_TXPA_G2, 0xfffff, 0x226BF); /*@Enable TXIQGEN in Rx mode*/ + } + odm_set_rf_reg(dm, RF_PATH_A, RF_TXPA_G2, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in Rx mode*/ + + for (i = RF_PATH_A; i < MAX_RF_PATH; i++) + odm_set_rf_reg(dm, i, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/ + + return true; +} + +void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8814A, BW); + odm_write_1byte(dm, REG_NDPA_RATE_8814A, (u8)rate); +} +#if 0 +#define PHYDM_MEMORY_MAP_BUF_READ 0x8000 +#define PHYDM_CTRL_INFO_PAGE 0x660 + +void +phydm_data_rate_8814a( + struct dm_struct *dm, + u8 mac_id, + u32 *data, + u8 data_len +) +{ + u8 i = 0; + u16 x_read_data_addr = 0; + + odm_write_2byte(dm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); + x_read_data_addr = PHYDM_MEMORY_MAP_BUF_READ + mac_id * 32; /*@Ctrl Info: 32Bytes for each macid(n)*/ + + if (x_read_data_addr < PHYDM_MEMORY_MAP_BUF_READ || x_read_data_addr > 0x8FFF) { + PHYDM_DBG(dm, DBG_TXBF, + "x_read_data_addr(0x%x) is not correct!\n", + x_read_data_addr); + return; + } + + /* Read data */ + for (i = 0; i < data_len; i++) + *(data + i) = odm_read_2byte(dm, x_read_data_addr + i); +} +#endif + +void hal_txbf_8814a_get_tx_rate(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + u8 data_rate = 0xFF; + u8 macid = 0; + + entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]); + macid = (u8)entry->mac_id; + + sta = dm->phydm_sta_info[macid]; + + if (is_sta_active(sta)) { + data_rate = (sta->ra_info.curr_tx_rate) & 0x7f; /*@Bit7 indicates SGI*/ + beam_info->tx_bf_data_rate = data_rate; + } + + PHYDM_DBG(dm, DBG_TXBF, "[%s] dm->tx_bf_data_rate = 0x%x\n", __func__, + beam_info->tx_bf_data_rate); +} + +void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if DEV_BUS_TYPE == RT_USB_INTERFACE + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + u8 nr_index = 0, tx_ss = 0; + + if (idx < BEAMFORMEE_ENTRY_NUM) + beamformee_entry = beamforming_info->beamformee_entry[idx]; + else + return; + + if (beamforming_info->last_usb_hub != (*dm->hub_usb_mode)) { + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer); + + if (*dm->hub_usb_mode == 2) { + if (dm->rf_type == RF_4T4R) + tx_ss = 0xf; + else if (dm->rf_type == RF_3T3R) + tx_ss = 0xe; + else + tx_ss = 0x6; + } else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + tx_ss = 0x6; + else + tx_ss = 0x6; + + if (tx_ss == 0xf) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + } else if (tx_ss == 0xe) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + } else if (tx_ss == 0x6) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); + } + + if (idx == 0) { + switch (nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + break; + } + } else { + switch (nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + break; + } + } + + beamforming_info->last_usb_hub = *dm->hub_usb_mode; + } else + return; +#endif +} + +u8 hal_txbf_8814a_get_ntx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ntx = 0, tx_ss = 3; + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + tx_ss = *dm->hub_usb_mode; +#endif + if (tx_ss == 3 || tx_ss == 2) { + if (dm->rf_type == RF_4T4R) + ntx = 3; + else if (dm->rf_type == RF_3T3R) + ntx = 2; + else + ntx = 1; + } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ + ntx = 1; + else + ntx = 1; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] ntx = %d\n", __func__, ntx); + return ntx; +} + +u8 hal_txbf_8814a_get_nrx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nrx = 0; + + if (dm->rf_type == RF_4T4R) + nrx = 3; + else if (dm->rf_type == RF_3T3R) + nrx = 2; + else if (dm->rf_type == RF_2T2R) + nrx = 1; + else if (dm->rf_type == RF_2T3R) + nrx = 2; + else if (dm->rf_type == RF_2T4R) + nrx = 3; + else if (dm->rf_type == RF_1T1R) + nrx = 0; + else if (dm->rf_type == RF_1T2R) + nrx = 1; + else + nrx = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] nrx = %d\n", __func__, nrx); + return nrx; +} + +void hal_txbf_8814a_rf_mode(void *dm_void, + struct _RT_BEAMFORMING_INFO *beamforming_info, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nr_index = 0; + u8 tx_ss = 3; /*@default use 3 Tx*/ + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + beamformee_entry = beamforming_info->beamformee_entry[idx]; + else + return; + + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), beamformee_entry.comp_steering_num_of_bfer); + + if (dm->rf_type == RF_1T1R) + return; + + if (beamforming_info->beamformee_su_cnt > 0) { +#if DEV_BUS_TYPE == RT_USB_INTERFACE + beamforming_info->last_usb_hub = *dm->hub_usb_mode; + tx_ss = *dm->hub_usb_mode; +#endif + if (tx_ss == 3 || tx_ss == 2) { + if (dm->rf_type == RF_4T4R) + tx_ss = 0xf; + else if (dm->rf_type == RF_3T3R) + tx_ss = 0xe; + else + tx_ss = 0x6; + } else if (tx_ss == 1) /*USB 2.0 always 2Tx*/ + tx_ss = 0x6; + else + tx_ss = 0x6; + + if (tx_ss == 0xf) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93f); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKDWORD, 0x93f93f0); + } else if (tx_ss == 0xe) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x93e); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e93e0); + } else if (tx_ss == 0x6) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x936); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKLWORD, 0x9360); + } + + /*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/ + + if (idx == 0) { + switch (nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + + break; + } + } else { + switch (nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x9366); /*tx2path, BC*/ + break; + + case 2: /*Nsts = 3 BCD*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93e93ee); /*tx3path, BCD*/ + break; + + default: /*nr>3, same as Case 3*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, MASKBYTE3LOWNIBBLE | MASKL3BYTES, 0x93f93ff); /*tx4path, ABCD*/ + break; + } + } + } + + if (beamforming_info->beamformee_su_cnt == 0 && beamforming_info->beamformer_su_cnt == 0) { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8814A, MASKBYTE3 | MASKBYTE2HIGHNIBBLE, 0x932); /*set tx_path selection for 8814a BFer bug refine*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8814A, MASKDWORD, 0x93e9360); + } +} +#if 0 +void +hal_txbf_8814a_download_ndpa( + void *dm_void, + u8 idx +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + u16 head_page = 0x7FE; + boolean is_send_beacon = false; + u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + void *adapter = dm->adapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *dm->is_fw_dw_rsvd_page_in_progress = true; +#endif + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1); + odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); + + if (tmp_reg422 & BIT(6)) { + PHYDM_DBG(dm, DBG_TXBF, + "%s: There is an adapter is sending beacon.\n", + __func__); + is_send_beacon = true; + } + + /*@0x204[11:0] Beacon Head for TXDMA*/ + odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, head_page); + + do { + /*@Clear beacon valid check bit.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1); + odm_write_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); + + /*@download NDPA rsvd page.*/ + if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); + else + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + + /*@check rsvd page download OK.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 1); + count = 0; + while (!(bcn_valid_reg & BIT(7)) && count < 20) { + count++; + ODM_delay_ms(10); + bcn_valid_reg = odm_read_1byte(dm, REG_FIFOPAGE_CTRL_2_8814A + 2); + } + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5); + + if (!(bcn_valid_reg & BIT(7))) + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", + __func__); + + /*@0x204[11:0] Beacon Head for TXDMA*/ + odm_write_2byte(dm, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /*the beacon cannot be sent by HW.*/ + /*@2010.06.23. Added by tynli.*/ + if (is_send_beacon) + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); + + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8814A + 1); + odm_write_1byte(dm, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); + + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *dm->is_fw_dw_rsvd_page_in_progress = false; +#endif +} + +void +hal_txbf_8814a_fw_txbf_cmd( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx, period = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].is_sound) { + PageNum0 = 0xFE; + PageNum1 = 0x07; + period = (u8)(beam_info->beamformee_entry[idx].sound_period); + } else if (PageNum0 == 0xFF) { + PageNum0 = 0xFF; /*stop sounding*/ + PageNum1 = 0x0F; + } + } + } + + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = period; + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d, PageNum1 = %d period = %d\n", __func__, + PageNum0, PageNum1, period); +} +#endif +void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0, csi_param = 0; + u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] bfer_idx=%d, bfee_idx=%d\n", __func__, + bfer_idx, bfee_idx); + odm_set_mac_reg(dm, REG_SND_PTCL_CTRL_8814A, MASKBYTE1 | MASKBYTE2, 0x0202); + + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; + /*Sounding protocol control*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xDB); + + /*@MAC address/Partial AID of Beamformer*/ + if (bfer_idx == 0) { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), beamformer_entry.mac_addr[i]); + } else { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), beamformer_entry.mac_addr[i]); + } + + /*@CSI report parameters of Beamformer*/ + nc_index = hal_txbf_8814a_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nr_index = beamformer_entry.num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + + grouping = 0; + + /*@for ac = 1, for n = 3*/ + if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) + codebookinfo = 1; + else if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) + codebookinfo = 3; + + coefficientsize = 3; + + csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); + + if (bfer_idx == 0) + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, csi_param); + else + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, csi_param); + /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); + } + + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; + + hal_txbf_8814a_rf_mode(dm, beamforming_info, bfee_idx); + + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + sta_id = beamformee_entry.mac_id; + else + sta_id = beamformee_entry.p_aid; + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (bfee_idx == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); + } else + odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); + + /*@CSI report parameters of Beamformee*/ + if (bfee_idx == 0) { + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; + + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9)); + } else + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/ + + phydm_beamforming_notify(dm); + } +} + +void hal_txbf_8814a_leave(void *dm_void, u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + + if (idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; + } else + return; + + /*@Clear P_AID of Beamformee*/ + /*@Clear MAC address of Beamformer*/ + /*@Clear Associated Bfmee Sel*/ + + if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8814A, 0xD8); + if (idx == 0) { + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A, 0); + } else { + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); + } + } + + if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + hal_txbf_8814a_rf_mode(dm, beamforming_info, idx); + if (idx == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, 0x0); + odm_write_1byte(dm, REG_TXBF_CTRL_8814A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8814A + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); + } else { + odm_write_2byte(dm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); + + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); + } + } +} + +void hal_txbf_8814a_status(void *dm_void, u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val, tmp_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + beamform_entry = beamforming_info->beamformee_entry[idx]; + else + return; + + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry.mac_id; + else + beam_ctrl_val = beamform_entry.p_aid; + + PHYDM_DBG(dm, DBG_TXBF, "@%s, beamform_entry.beamform_entry_state = %d", + __func__, beamform_entry.beamform_entry_state); + + if (idx == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8814A; + else { + beam_ctrl_reg = REG_TXBF_CTRL_8814A + 2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); + } + + if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beamforming_info->apply_v_matrix == true) { + if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= (BIT(9) | BIT(10)); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80) + beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); + } else { + PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", __func__); + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); + } + + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); + /*@disable NDP packet use beamforming */ + tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8814A); + odm_write_2byte(dm, REG_TXBF_CTRL_8814A, tmp_val | BIT(15)); +} + +void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx) +{ +#if 0 + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_8814a_download_ndpa(dm, idx); + + hal_txbf_8814a_fw_txbf_cmd(dm); +#endif +} + +#endif /* @(RTL8814A_SUPPORT == 1)*/ + +#endif diff --git a/hal/phydm/txbf/haltxbf8814a.h b/hal/phydm/txbf/haltxbf8814a.h new file mode 100644 index 0000000..61b33bb --- /dev/null +++ b/hal/phydm/txbf/haltxbf8814a.h @@ -0,0 +1,77 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HAL_TXBF_8814A_H__ +#define __HAL_TXBF_8814A_H__ + +#if (RTL8814A_SUPPORT == 1) +#ifdef PHYDM_BEAMFORMING_SUPPORT + +boolean +phydm_beamforming_set_iqgen_8814A(void *dm_void); + +void hal_txbf_8814a_set_ndpa_rate(void *dm_void, u8 BW, u8 rate); + +u8 hal_txbf_8814a_get_ntx(void *dm_void); + +void hal_txbf_8814a_enter(void *dm_void, u8 idx); + +void hal_txbf_8814a_leave(void *dm_void, u8 idx); + +void hal_txbf_8814a_status(void *dm_void, u8 idx); + +void hal_txbf_8814a_reset_tx_path(void *dm_void, u8 idx); + +void hal_txbf_8814a_get_tx_rate(void *dm_void); + +void hal_txbf_8814a_fw_txbf(void *dm_void, u8 idx); + +#else + +#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(dm_void) 0 +#define hal_txbf_8814a_enter(dm_void, idx) +#define hal_txbf_8814a_leave(dm_void, idx) +#define hal_txbf_8814a_status(dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(dm_void) +#define hal_txbf_8814a_fw_txbf(dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(dm_void) 0 + +#endif + +#else + +#define hal_txbf_8814a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_8814a_get_ntx(dm_void) 0 +#define hal_txbf_8814a_enter(dm_void, idx) +#define hal_txbf_8814a_leave(dm_void, idx) +#define hal_txbf_8814a_status(dm_void, idx) +#define hal_txbf_8814a_reset_tx_path(dm_void, idx) +#define hal_txbf_8814a_get_tx_rate(dm_void) +#define hal_txbf_8814a_fw_txbf(dm_void, idx) +#define phydm_beamforming_set_iqgen_8814A(dm_void) 0 +#endif + +#endif diff --git a/hal/phydm/txbf/haltxbf8822b.c b/hal/phydm/txbf/haltxbf8822b.c new file mode 100644 index 0000000..a1d35c9 --- /dev/null +++ b/hal/phydm/txbf/haltxbf8822b.c @@ -0,0 +1,1088 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/*@============================================================*/ +/* @Description: */ +/* @*/ +/* This file is for 8814A TXBF mechanism */ +/* @*/ +/*@============================================================*/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (RTL8822B_SUPPORT == 1) +#ifdef PHYDM_BEAMFORMING_SUPPORT + +u8 hal_txbf_8822b_get_ntx( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ntx = 0; + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (dm->support_interface == ODM_ITRF_USB) { + if (*dm->hub_usb_mode == 2) { /*USB3.0*/ + if (dm->rf_type == RF_4T4R) + ntx = 3; + else if (dm->rf_type == RF_3T3R) + ntx = 2; + else + ntx = 1; + } else if (*dm->hub_usb_mode == 1) /*USB 2.0 always 2Tx*/ + ntx = 1; + else + ntx = 1; + } else +#endif + { + if (dm->rf_type == RF_4T4R) + ntx = 3; + else if (dm->rf_type == RF_3T3R) + ntx = 2; + else + ntx = 1; + } + + return ntx; +} + +u8 hal_txbf_8822b_get_nrx( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nrx = 0; + + if (dm->rf_type == RF_4T4R) + nrx = 3; + else if (dm->rf_type == RF_3T3R) + nrx = 2; + else if (dm->rf_type == RF_2T2R) + nrx = 1; + else if (dm->rf_type == RF_2T3R) + nrx = 2; + else if (dm->rf_type == RF_2T4R) + nrx = 3; + else if (dm->rf_type == RF_1T1R) + nrx = 0; + else if (dm->rf_type == RF_1T2R) + nrx = 1; + else + nrx = 0; + + return nrx; +} + +/***************SU & MU BFee Entry********************/ +void hal_txbf_8822b_rf_mode( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beamforming_info, + u8 idx) +{ +#if 0 + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i, nr_index = 0; + boolean is_self_beamformer = false; + boolean is_self_beamformee = false; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + beamformee_entry = beamforming_info->beamformee_entry[idx]; + else + return; + + if (dm->rf_type == RF_1T1R) + return; + + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x1); + /*RF mode table write enable*/ + } + + if (beamforming_info->beamformee_su_cnt > 0 || beamforming_info->beamformee_mu_cnt > 0) { + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_addr, 0xfffff, 0x18000); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data0, 0xfffff, 0xBE77F); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, rf_mode_table_data1, 0xfffff, 0x226BF); + /*@Enable TXIQGEN in RX mode*/ + } + odm_set_rf_reg(dm, RF_PATH_A, rf_mode_table_data1, 0xfffff, 0xE26BF); + /*@Enable TXIQGEN in RX mode*/ + } + + for (i = RF_PATH_A; i < RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, rf_welut_jaguar, 0x80000, 0x0); + /*RF mode table write disable*/ + } + + if (beamforming_info->beamformee_su_cnt > 0) { + /*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/ + + if (idx == 0) { + /*Nsts = 2 AB*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430);*/ + + } else {/*@IDX =1*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + /*odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2, MASKLWORD, 0x430;*/ + } + } else { + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/ + } + + if (beamforming_info->beamformee_mu_cnt > 0) { + /*@MU STAs share the common setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + } +#endif +} +#if 0 +void +hal_txbf_8822b_download_ndpa( + void *adapter, + u8 idx +) +{ + u8 u1b_tmp = 0, tmp_reg422 = 0; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + u16 head_page = 0x7FE; + boolean is_send_beacon = false; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u16 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + + hal_data->is_fw_dw_rsvd_page_in_progress = true; + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u16 *)&tx_page_bndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1); + platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp | BIT(0))); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmp_reg422 = platform_efio_read_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2); + platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422 & (~BIT(6))); + + if (tmp_reg422 & BIT(6)) { + RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an adapter is sending beacon.\n")); + is_send_beacon = true; + } + + /*@0x204[11:0] Beacon Head for TXDMA*/ + platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, head_page); + + do { + /*@Clear beacon valid check bit.*/ + bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + platform_efio_write_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (bcn_valid_reg | BIT(7))); + + /*@download NDPA rsvd page.*/ + if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->AID, p_beam_entry->sound_bw, BEACON_QUEUE); + else + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + + /*@check rsvd page download OK.*/ + bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + count = 0; + while (!(bcn_valid_reg & BIT(7)) && count < 20) { + count++; + delay_us(10); + bcn_valid_reg = platform_efio_read_1byte(adapter, REG_FIFOPAGE_CTRL_2_8814A + 2); + } + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(7)) && dl_bcn_count < 5); + + if (!(bcn_valid_reg & BIT(0))) + RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__)); + + /*@0x204[11:0] Beacon Head for TXDMA*/ + platform_efio_write_2byte(adapter, REG_FIFOPAGE_CTRL_2_8814A, tx_page_bndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /*the beacon cannot be sent by HW.*/ + /*@2010.06.23. Added by tynli.*/ + if (is_send_beacon) + platform_efio_write_1byte(adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmp_reg422); + + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1b_tmp = platform_efio_read_1byte(adapter, REG_CR_8814A + 1); + platform_efio_write_1byte(adapter, REG_CR_8814A + 1, (u1b_tmp & (~BIT(0)))); + + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; + + hal_data->is_fw_dw_rsvd_page_in_progress = false; +} + +void +hal_txbf_8822b_fw_txbf_cmd( + void *adapter +) +{ + u8 idx, period = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + + PMGNT_INFO mgnt_info = &(adapter->MgntInfo); + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beam_info->beamformee_entry[idx].is_sound) { + PageNum0 = 0xFE; + PageNum1 = 0x07; + period = (u8)(beam_info->beamformee_entry[idx].sound_period); + } else if (PageNum0 == 0xFF) { + PageNum0 = 0xFF; /*stop sounding*/ + PageNum1 = 0x0F; + } + } + } + + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = period; + fill_h2c_cmd(adapter, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + + RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x period = %d", __func__, PageNum0, PageNum1, period)); +} +#endif + +#if 0 +void +hal_txbf_8822b_init( + void *dm_void +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 u1b_tmp; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + void *adapter = dm->adapter; + + odm_set_bb_reg(dm, R_0x14c0, BIT(16), 1); /*@Enable P1 aggr new packet according to P0 transfer time*/ + odm_set_bb_reg(dm, R_0x14c0, BIT(15) | BIT14 | BIT13 | BIT12, 10); /*@MU Retry Limit*/ + odm_set_bb_reg(dm, R_0x14c0, BIT(7), 0); /*@Disable Tx MU-MIMO until sounding done*/ + odm_set_bb_reg(dm, R_0x14c0, 0x3F, 0); /* @Clear validity of MU STAs */ + odm_write_1byte(dm, 0x167c, 0x70); /*@MU-MIMO Option as default value*/ + odm_write_2byte(dm, 0x1680, 0); /*@MU-MIMO Control as default value*/ + + /* Set MU NDPA rate & BW source */ + /* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1b_tmp = odm_read_1byte(dm, 0x42C); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B, (u1b_tmp | BIT(6))); + /* @0x45F[7:0] = 0x10 (rate=OFDM_6M, BW20) */ + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, 0x10); + + /*Temp Settings*/ + odm_set_bb_reg(dm, R_0x6dc, 0x3F000000, 4); /*STA2's CSI rate is fixed at 6M*/ + odm_set_bb_reg(dm, R_0x1c94, MASKDWORD, 0xAFFFAFFF); /*@Grouping bitmap parameters*/ + + /* @Init HW variable */ + beamforming_info->reg_mu_tx_ctrl = odm_read_4byte(dm, 0x14c0); + + if (dm->rf_type == RF_2T2R) { /*@2T2R*/ + PHYDM_DBG(dm, DBG_TXBF, "%s: rf_type is 2T2R\n", __func__); + config_phydm_trx_mode_8822b(dm, (enum bb_path)3, + (enum bb_path)3, BB_PATH_AB; + } + +#if (OMNIPEEK_SNIFFER_ENABLED == 1) + /* @Config HW to receive packet on the user position from registry for sniffer mode. */ + /* odm_set_bb_reg(dm, R_0xb00, BIT(9), 1);*/ /* For A-cut only. RegB00[9] = 1 (enable PMAC Rx) */ + odm_set_bb_reg(dm, R_0xb54, BIT(30), 1); /* RegB54[30] = 1 (force user position) */ + odm_set_bb_reg(dm, R_0xb54, (BIT(29) | BIT28), adapter->MgntInfo.sniff_user_position); /* RegB54[29:28] = user position (0~3) */ + PHYDM_DBG(dm, DBG_TXBF, + "Set adapter->MgntInfo.sniff_user_position=%#X\n", + adapter->MgntInfo.sniff_user_position); +#endif +} +#endif + +void hal_txbf_8822b_enter( + void *dm_void, + u8 bfer_bfee_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u16 csi_param = 0; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry; + u16 value16, sta_id = 0; + u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + u32 gid_valid, user_position_l, user_position_h; + u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + u8 u1b_tmp; + u32 u4b_tmp; + + RT_DISP(FBEAM, FBEAM_FUN, ("%s: bfer_bfee_idx=%d, bfer_idx=%d, bfee_idx=%d\n", __func__, bfer_bfee_idx, bfer_idx, bfee_idx)); + + /*************SU BFer Entry Init*************/ + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx]; + beamformer_entry->is_mu_ap = false; + /*Sounding protocol control*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + for (i = 0; i < MAX_BEAMFORMER_SU; i++) { + if ((beamforming_info->beamformer_su_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformer_su_reg_maping |= BIT(i); + beamformer_entry->su_reg_index = i; + break; + } + } + + /*@MAC address/Partial AID of Beamformer*/ + if (beamformer_entry->su_reg_index == 0) { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]); + } else { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8822B + i), beamformer_entry->mac_addr[i]); + } + + /*@CSI report parameters of Beamformer*/ + nc_index = hal_txbf_8822b_get_nrx(dm); /*@for 8814A nrx = 3(4 ant), min=0(1 ant)*/ + nr_index = beamformer_entry->num_of_sounding_dim; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + + grouping = 0; + + /*@for ac = 1, for n = 3*/ + if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) + codebookinfo = 1; + else if (beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT) + codebookinfo = 3; + + coefficientsize = 3; + + csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); + + if (bfer_idx == 0) + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param); + else + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, csi_param); + /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B + 3, 0x70); + } + + /*************SU BFee Entry Init*************/ + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx]; + p_beamformee_entry->is_mu_sta = false; + hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx); + + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + sta_id = p_beamformee_entry->mac_id; + else + sta_id = p_beamformee_entry->p_aid; + + for (i = 0; i < MAX_BEAMFORMEE_SU; i++) { + if ((beamforming_info->beamformee_su_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformee_su_reg_maping |= BIT(i); + p_beamformee_entry->su_reg_index = i; + break; + } + } + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (p_beamformee_entry->su_reg_index == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + } else + odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, sta_id | BIT(14) | BIT(15) | BIT(12)); + + /*@CSI report parameters of Beamformee*/ + if (p_beamformee_entry->su_reg_index == 0) { + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3) & 0x3; + + odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, sta_id | BIT(9)); + } else + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, sta_id | 0xE200); /*Set BIT25*/ + + phydm_beamforming_notify(dm); + } + + /*************MU BFer Entry Init*************/ + if (beamforming_info->beamformer_mu_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = &beamforming_info->beamformer_entry[bfer_idx]; + beamforming_info->mu_ap_index = bfer_idx; + beamformer_entry->is_mu_ap = true; + for (i = 0; i < 8; i++) + beamformer_entry->gid_valid[i] = 0; + for (i = 0; i < 16; i++) + beamformer_entry->user_position[i] = 0; + + /*Sounding protocol control*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + /* @MAC address */ + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + i), beamformer_entry->mac_addr[i]); + + /* Set partial AID */ + odm_write_2byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8822B + 6), beamformer_entry->p_aid); + + /* @Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ + u1b_tmp = odm_read_1byte(dm, 0x1680); + u1b_tmp = (beamformer_entry->p_aid) & 0xFFF; + odm_write_1byte(dm, 0x1680, u1b_tmp); + + /* Set 80us for leaving ndp_rx_standby_state */ + odm_write_1byte(dm, 0x71B, 0x50); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp |= 0x40; + odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); + /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP1_8822B); + u1b_tmp |= 0x30; + odm_write_1byte(dm, REG_RXFLTMAP1_8822B, u1b_tmp); + + /*@CSI report parameters of Beamformer*/ + nc_index = hal_txbf_8822b_get_nrx(dm); /* @Depend on RF type */ + nr_index = 1; /*@0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so nr_index don't care*/ + grouping = 0; /*no grouping*/ + codebookinfo = 1; /*@7 bit for psi, 9 bit for phi*/ + coefficientsize = 0; /*This is nothing really matter*/ + csi_param = (u16)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (nr_index << 3) | (nc_index)); + odm_write_2byte(dm, 0x6F4, csi_param); + + /*@for B-cut*/ + odm_set_bb_reg(dm, R_0x6a0, BIT(20), 0); + odm_set_bb_reg(dm, R_0x688, BIT(20), 0); + } + + /*************MU BFee Entry Init*************/ + if (beamforming_info->beamformee_mu_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + p_beamformee_entry = &beamforming_info->beamformee_entry[bfee_idx]; + p_beamformee_entry->is_mu_sta = true; + for (i = 0; i < MAX_BEAMFORMEE_MU; i++) { + if ((beamforming_info->beamformee_mu_reg_maping & BIT(i)) == 0) { + beamforming_info->beamformee_mu_reg_maping |= BIT(i); + p_beamformee_entry->mu_reg_index = i; + break; + } + } + + if (p_beamformee_entry->mu_reg_index == 0xFF) { + /* There is no valid bit in beamformee_mu_reg_maping */ + RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__)); + return; + } + + /*User position table*/ + switch (p_beamformee_entry->mu_reg_index) { + case 0: + gid_valid = 0x7fe; + user_position_l = 0x111110; + user_position_h = 0x0; + break; + case 1: + gid_valid = 0x7f806; + user_position_l = 0x11000004; + user_position_h = 0x11; + break; + case 2: + gid_valid = 0x1f81818; + user_position_l = 0x400040; + user_position_h = 0x11100; + break; + case 3: + gid_valid = 0x1e186060; + user_position_l = 0x4000400; + user_position_h = 0x1100040; + break; + case 4: + gid_valid = 0x66618180; + user_position_l = 0x40004000; + user_position_h = 0x10040400; + break; + case 5: + gid_valid = 0x79860600; + user_position_l = 0x40000; + user_position_h = 0x4404004; + break; + } + + for (i = 0; i < 8; i++) { + if (i < 4) { + p_beamformee_entry->gid_valid[i] = (u8)(gid_valid & 0xFF); + gid_valid = (gid_valid >> 8); + } else + p_beamformee_entry->gid_valid[i] = 0; + } + for (i = 0; i < 16; i++) { + if (i < 4) + p_beamformee_entry->user_position[i] = (u8)((user_position_l >> (i * 8)) & 0xFF); + else if (i < 8) + p_beamformee_entry->user_position[i] = (u8)((user_position_h >> ((i - 4) * 8)) & 0xFF); + else + p_beamformee_entry->user_position[i] = 0; + } + + /*Sounding protocol control*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + /*select MU STA table*/ + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= (p_beamformee_entry->mu_reg_index << 8) & (BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + + odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, 0); /*Reset gid_valid table*/ + odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h); + + /*set validity of MU STAs*/ + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + beamforming_info->reg_mu_tx_ctrl |= beamforming_info->beamformee_mu_reg_maping & 0x3F; + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + + PHYDM_DBG(dm, DBG_TXBF, + "@%s, reg_mu_tx_ctrl = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, beamforming_info->reg_mu_tx_ctrl, + user_position_l, user_position_h); + + value16 = odm_read_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index]); + value16 &= 0xFE00; /*@Clear PAID*/ + value16 |= BIT(9); /*@Enable MU BFee*/ + value16 |= p_beamformee_entry->p_aid; + odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], value16); + + /* @0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1b_tmp = odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3); + u1b_tmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, u1b_tmp); + /* Set NDPA to 6M*/ + odm_write_1byte(dm, REG_NDPA_RATE_8822B, 0x4); + + u1b_tmp = odm_read_1byte(dm, REG_NDPA_OPT_CTRL_8822B); + u1b_tmp &= 0xFC; /* @Clear bit 0, 1*/ + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8822B, u1b_tmp); + + u4b_tmp = odm_read_4byte(dm, REG_SND_PTCL_CTRL_8822B); + u4b_tmp = ((u4b_tmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202*/ + odm_write_4byte(dm, REG_SND_PTCL_CTRL_8822B, u4b_tmp); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + u1b_tmp = odm_read_1byte(dm, REG_RXFLTMAP0_8822B + 1); + u1b_tmp |= 0x40; + odm_write_1byte(dm, REG_RXFLTMAP0_8822B + 1, u1b_tmp); + /* @End of MAC registers setting */ + + hal_txbf_8822b_rf_mode(dm, beamforming_info, bfee_idx); +#if (SUPPORT_MU_BF == 1) + /*Special for plugfest*/ + delay_ms(50); /* wait for 4-way handshake ending*/ + send_sw_vht_gid_mgnt_frame(dm, p_beamformee_entry->mac_addr, bfee_idx); +#endif + + phydm_beamforming_notify(dm); +#if 1 + { + u32 ctrl_info_offset, index; + /*Set Ctrl Info*/ + odm_write_2byte(dm, 0x140, 0x660); + ctrl_info_offset = 0x8000 + 32 * p_beamformee_entry->mac_id; + /*Reset Ctrl Info*/ + for (index = 0; index < 8; index++) + odm_write_4byte(dm, ctrl_info_offset + index * 4, 0); + + odm_write_4byte(dm, ctrl_info_offset, (p_beamformee_entry->mu_reg_index + 1) << 16); + odm_write_1byte(dm, 0x81, 0x80); /*RPTBUF ready*/ + + PHYDM_DBG(dm, DBG_TXBF, + "@%s, mac_id = %d, ctrl_info_offset = 0x%x, mu_reg_index = %x\n", + __func__, p_beamformee_entry->mac_id, + ctrl_info_offset, + p_beamformee_entry->mu_reg_index); + } +#endif + } +} + +void hal_txbf_8822b_leave( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY *p_beamformee_entry; + u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + + if (idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = &beamforming_info->beamformer_entry[idx]; + p_beamformee_entry = &beamforming_info->beamformee_entry[idx]; + } else + return; + + /*@Clear P_AID of Beamformee*/ + /*@Clear MAC address of Beamformer*/ + /*@Clear Associated Bfmee Sel*/ + + if (beamformer_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8822B, 0xD8); + if (beamformer_entry->is_mu_ap == 0) { /*SU BFer */ + if (beamformer_entry->su_reg_index == 0) { + odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8822B + 4, 0); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0); + } else { + odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8822B + 4, 0); + odm_write_2byte(dm, REG_TX_CSI_RPT_PARAM_BW20_8822B + 2, 0); + } + beamforming_info->beamformer_su_reg_maping &= ~(BIT(beamformer_entry->su_reg_index)); + beamformer_entry->su_reg_index = 0xFF; + } else { /*@MU BFer */ + /*set validity of MU STA0 and MU STA1*/ + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + + odm_memory_set(dm, beamformer_entry->gid_valid, 0, 8); + odm_memory_set(dm, beamformer_entry->user_position, 0, 16); + beamformer_entry->is_mu_ap = false; + } + } + + if (p_beamformee_entry->beamform_entry_cap == BEAMFORMING_CAP_NONE) { + hal_txbf_8822b_rf_mode(dm, beamforming_info, idx); + if (p_beamformee_entry->is_mu_sta == 0) { /*SU BFee*/ + if (p_beamformee_entry->su_reg_index == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, 0x0); + odm_write_1byte(dm, REG_TXBF_CTRL_8822B + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8822B + 3) | BIT(4) | BIT(6) | BIT(7)); + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); + } else { + odm_write_2byte(dm, REG_TXBF_CTRL_8822B + 2, 0x0 | BIT(14) | BIT(15) | BIT(12)); + + odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2, + odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8822B + 2) & 0x60); + } + beamforming_info->beamformee_su_reg_maping &= ~(BIT(p_beamformee_entry->su_reg_index)); + p_beamformee_entry->su_reg_index = 0xFF; + } else { /*@MU BFee */ + /*@Disable sending NDPA & BF-rpt-poll to this BFee*/ + odm_write_2byte(dm, mu_reg[p_beamformee_entry->mu_reg_index], 0); + /*set validity of MU STA*/ + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(p_beamformee_entry->mu_reg_index)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + + p_beamformee_entry->is_mu_sta = false; + beamforming_info->beamformee_mu_reg_maping &= ~(BIT(p_beamformee_entry->mu_reg_index)); + p_beamformee_entry->mu_reg_index = 0xFF; + } + } +} + +/***********SU & MU BFee Entry Only when souding done****************/ +void hal_txbf_8822b_status( + void *dm_void, + u8 beamform_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val, tmp_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry; + boolean is_mu_sounding = beamforming_info->is_mu_sounding, is_bitmap_ready = false; + u16 bitmap; + u8 idx, gid, i; + u8 id1, id0; + u32 gid_valid[6] = {0}; + u32 value32; + boolean is_sounding_success[6] = {false}; + + if (beamform_idx < BEAMFORMEE_ENTRY_NUM) + beamform_entry = &beamforming_info->beamformee_entry[beamform_idx]; + else + return; + + /*SU sounding done */ + if (is_mu_sounding == false) { + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry->mac_id; + else + beam_ctrl_val = beamform_entry->p_aid; + + PHYDM_DBG(dm, DBG_TXBF, + "@%s, beamform_entry.beamform_entry_state = %d", + __func__, beamform_entry->beamform_entry_state); + + if (beamform_entry->su_reg_index == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8822B; + else { + beam_ctrl_reg = REG_TXBF_CTRL_8822B + 2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); + } + + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (beamform_entry->sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (beamform_entry->sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= (BIT(9) | BIT(10)); + else if (beamform_entry->sound_bw == CHANNEL_WIDTH_80) + beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); + } else { + PHYDM_DBG(dm, DBG_TXBF, "@%s, Don't apply Vmatrix", + __func__); + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); + } + + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); + /*@disable NDP packet use beamforming */ + tmp_val = odm_read_2byte(dm, REG_TXBF_CTRL_8822B); + odm_write_2byte(dm, REG_TXBF_CTRL_8822B, tmp_val | BIT(15)); + } else { + PHYDM_DBG(dm, DBG_TXBF, "@%s, MU Sounding Done\n", __func__); + /*@MU sounding done */ + if (1) { /* @(beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { */ + PHYDM_DBG(dm, DBG_TXBF, + "@%s, BEAMFORMING_ENTRY_STATE_PROGRESSED\n", + __func__); + + value32 = odm_get_bb_reg(dm, R_0x1684, MASKDWORD); + is_sounding_success[0] = (value32 & BIT(10)) ? 1 : 0; + is_sounding_success[1] = (value32 & BIT(26)) ? 1 : 0; + value32 = odm_get_bb_reg(dm, R_0x1688, MASKDWORD); + is_sounding_success[2] = (value32 & BIT(10)) ? 1 : 0; + is_sounding_success[3] = (value32 & BIT(26)) ? 1 : 0; + value32 = odm_get_bb_reg(dm, R_0x168c, MASKDWORD); + is_sounding_success[4] = (value32 & BIT(10)) ? 1 : 0; + is_sounding_success[5] = (value32 & BIT(26)) ? 1 : 0; + + PHYDM_DBG(dm, DBG_TXBF, + "@%s, is_sounding_success STA1:%d, STA2:%d, STA3:%d, STA4:%d, STA5:%d, STA6:%d\n", + __func__, is_sounding_success[0], + is_sounding_success[1], + is_sounding_success[2], + is_sounding_success[3], + is_sounding_success[4], + is_sounding_success[5]); + + value32 = odm_get_bb_reg(dm, R_0xf4c, 0xFFFF0000); + /* odm_set_bb_reg(dm, R_0x19e0, MASKHWORD, 0xFFFF);Let MAC ignore bitmap */ + + is_bitmap_ready = (boolean)((value32 & BIT(15)) >> 15); + bitmap = (u16)(value32 & 0x3FFF); + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) { /*@bit0~4*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { /*@bit5~8*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { /*@bit9~11*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { /*@bit12~13*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { /*@bit14*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + if (bitmap & BIT(idx)) { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + } else { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + } + } + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + beamform_entry = &beamforming_info->beamformee_entry[i]; + if (beamform_entry->is_mu_sta && beamform_entry->mu_reg_index < 6) { + value32 = gid_valid[beamform_entry->mu_reg_index]; + for (idx = 0; idx < 4; idx++) { + beamform_entry->gid_valid[idx] = (u8)(value32 & 0xFF); + value32 = (value32 >> 8); + } + } + } + + for (idx = 0; idx < 6; idx++) { + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= ((idx << 8) & (BIT(8) | BIT(9) | BIT(10))); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_mac_reg(dm, R_0x14c4, MASKDWORD, gid_valid[idx]); /*set MU STA gid valid table*/ + } + + /*@Enable TxMU PPDU*/ + if (beamforming_info->dbg_disable_mu_tx == false) + beamforming_info->reg_mu_tx_ctrl |= BIT(7); + else + beamforming_info->reg_mu_tx_ctrl &= ~BIT(7); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + } + } +} + +/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ +void hal_txbf_8822b_config_gtab( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; + u32 gid_valid = 0, user_position_l = 0, user_position_h = 0, i; + + if (beamforming_info->mu_ap_index < BEAMFORMER_ENTRY_NUM) + beamformer_entry = &beamforming_info->beamformer_entry[beamforming_info->mu_ap_index]; + else + return; + + PHYDM_DBG(dm, DBG_TXBF, "%s==>\n", __func__); + + /*@For GID 0~31*/ + for (i = 0; i < 4; i++) + gid_valid |= (beamformer_entry->gid_valid[i] << (i << 3)); + for (i = 0; i < 8; i++) { + if (i < 4) + user_position_l |= (beamformer_entry->user_position[i] << (i << 3)); + else + user_position_h |= (beamformer_entry->user_position[i] << ((i - 4) << 3)); + } + /*select MU STA0 table*/ + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h); + + PHYDM_DBG(dm, DBG_TXBF, + "%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h); + + gid_valid = 0; + user_position_l = 0; + user_position_h = 0; + + /*@For GID 32~64*/ + for (i = 4; i < 8; i++) + gid_valid |= (beamformer_entry->gid_valid[i] << ((i - 4) << 3)); + for (i = 8; i < 16; i++) { + if (i < 4) + user_position_l |= (beamformer_entry->user_position[i] << ((i - 8) << 3)); + else + user_position_h |= (beamformer_entry->user_position[i] << ((i - 12) << 3)); + } + /*select MU STA1 table*/ + beamforming_info->reg_mu_tx_ctrl &= ~(BIT(8) | BIT(9) | BIT(10)); + beamforming_info->reg_mu_tx_ctrl |= BIT(8); + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); + odm_set_bb_reg(dm, R_0x14c4, MASKDWORD, gid_valid); + odm_set_bb_reg(dm, R_0x14c8, MASKDWORD, user_position_l); + odm_set_bb_reg(dm, R_0x14cc, MASKDWORD, user_position_h); + + PHYDM_DBG(dm, DBG_TXBF, + "%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h); + + /* Set validity of MU STA0 and MU STA1*/ + beamforming_info->reg_mu_tx_ctrl &= 0xFFFFFFC0; + beamforming_info->reg_mu_tx_ctrl |= 0x3; /* STA0, STA1*/ + odm_write_4byte(dm, 0x14c0, beamforming_info->reg_mu_tx_ctrl); +} + +#if 0 +/*This function translate the bitmap to GTAB*/ +void +haltxbf8822b_gtab_translation( + struct dm_struct *dm +) +{ + u8 idx, gid; + u8 id1, id0; + u32 gid_valid[6] = {0}; + u32 user_position_lsb[6] = {0}; + u32 user_position_msb[6] = {0}; + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) {/*@bit0~4*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { /*@bit5~8*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { /*@bit9~11*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { /*@bit12~13*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { /*@bit14*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (1 << gid); + gid_valid[id1] |= (1 << gid); + if (gid < 16) { + /*user_position_lsb[id0] |= (0 << (gid << 1));*/ + user_position_lsb[id1] |= (1 << (gid << 1)); + } else { + /*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/ + user_position_msb[id1] |= (1 << ((gid - 16) << 1)); + } + + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (1 << gid); + gid_valid[id1] |= (1 << gid); + if (gid < 16) { + user_position_lsb[id0] |= (1 << (gid << 1)); + /*user_position_lsb[id1] |= (0 << (gid << 1));*/ + } else { + user_position_msb[id0] |= (1 << ((gid - 16) << 1)); + /*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/ + } + } + + + for (idx = 0; idx < 6; idx++) { + /*@dbg_print("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); + dbg_print("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/ + } +} +#endif + +void hal_txbf_8822b_fw_txbf( + void *dm_void, + u8 idx) +{ +#if 0 + struct _RT_BEAMFORMING_INFO *beam_info = GET_BEAMFORM_INFO(adapter); + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_8822b_download_ndpa(adapter, idx); + + hal_txbf_8822b_fw_txbf_cmd(adapter); +#endif +} + +#endif + +#if (defined(CONFIG_BB_TXBF_API)) +/*this function is only used for BFer*/ +void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; + + if (dm->rf_type == RF_1T1R) + return; + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + for (i = RF_PATH_A; i <= RF_PATH_B; i++) { + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, 0x00036); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, 0x5AFCE); /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), 0x0); /*RF mode table write disable*/ + } + } + + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(30), 1); /*@if Nsts > Nc, don't apply V matrix*/ + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1); /*@ignore user since 8822B only 2Tx*/ + + /*Nsts = 2 AB*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433); + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043); + + } else { + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28) | BIT29, 0x0); /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 0); /*@ignore user since 8822B only 2Tx*/ + + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /*@1SS by path-A*/ + odm_set_bb_reg(dm, REG_BB_TX_PATH_SEL_2_8822B, MASKLWORD, 0x430); /*@2SS by path-A,B*/ + } +} + +/*this function is for BFer bug workaround*/ +void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer, + u8 nc, u8 nr, u8 ng, u8 CB, u8 BW, + boolean is_vht) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (enable_su_bfer) { + odm_set_bb_reg(dm, R_0x19f8, BIT(22) | BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(dm, R_0x19f8, BIT(25) | BIT(24) | BIT(23), 0x0); + odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x1); + + if (is_vht) + odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x1f); + else + odm_set_bb_reg(dm, R_0x19f0, BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x22); + + odm_set_bb_reg(dm, R_0x19f0, BIT(7) | BIT(6), nc); + odm_set_bb_reg(dm, R_0x19f0, BIT(9) | BIT(8), nr); + odm_set_bb_reg(dm, R_0x19f0, BIT(11) | BIT(10), ng); + odm_set_bb_reg(dm, R_0x19f0, BIT(13) | BIT(12), CB); + + odm_set_bb_reg(dm, R_0xb58, BIT(3) | BIT(2), BW); + odm_set_bb_reg(dm, R_0xb58, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x0); + odm_set_bb_reg(dm, R_0xb58, BIT(9) | BIT(8), BW); + odm_set_bb_reg(dm, R_0xb58, BIT(13) | BIT(12) | BIT(11) | BIT(10), 0x0); + } else { + odm_set_bb_reg(dm, R_0x19f8, BIT(16), 0x0); + } + + PHYDM_DBG(dm, DBG_TXBF, "[%s] enable_su_bfer = %d, is_vht = %d\n", + __func__, enable_su_bfer, is_vht); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] nc = %d, nr = %d, ng = %d, CB = %d, BW = %d\n", + __func__, nc, nr, ng, CB, BW); +} +#endif +#endif /* @(RTL8822B_SUPPORT == 1)*/ diff --git a/hal/phydm/txbf/haltxbf8822b.h b/hal/phydm/txbf/haltxbf8822b.h new file mode 100644 index 0000000..552fba2 --- /dev/null +++ b/hal/phydm/txbf/haltxbf8822b.h @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HAL_TXBF_8822B_H__ +#define __HAL_TXBF_8822B_H__ + +#if (RTL8822B_SUPPORT == 1) +#ifdef PHYDM_BEAMFORMING_SUPPORT + +void hal_txbf_8822b_enter( + void *dm_void, + u8 idx); + +void hal_txbf_8822b_leave( + void *dm_void, + u8 idx); + +void hal_txbf_8822b_status( + void *dm_void, + u8 beamform_idx); + +void hal_txbf_8822b_config_gtab( + void *dm_void); + +void hal_txbf_8822b_fw_txbf( + void *dm_void, + u8 idx); +#else +#define hal_txbf_8822b_enter(dm_void, idx) +#define hal_txbf_8822b_leave(dm_void, idx) +#define hal_txbf_8822b_status(dm_void, idx) +#define hal_txbf_8822b_fw_txbf(dm_void, idx) +#define hal_txbf_8822b_config_gtab(dm_void) + +#endif + +#if (defined(CONFIG_BB_TXBF_API)) +void phydm_8822btxbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt); + +void phydm_8822b_sutxbfer_workaroud(void *dm_void, boolean enable_su_bfer, + u8 nc, u8 nr, u8 ng, u8 CB, u8 BW, + boolean is_vht); + +#else +#define phydm_8822btxbf_rfmode(dm_void, su_bfee_cnt, mu_bfee_cnt) +#define phydm_8822b_sutxbfer_workaroud(dm_void, enable_su_bfer, nc, nr, ng, CB, BW, is_vht) +#endif + +#else +#define hal_txbf_8822b_enter(dm_void, idx) +#define hal_txbf_8822b_leave(dm_void, idx) +#define hal_txbf_8822b_status(dm_void, idx) +#define hal_txbf_8822b_fw_txbf(dm_void, idx) +#define hal_txbf_8822b_config_gtab(dm_void) + +#endif +#endif diff --git a/hal/phydm/txbf/haltxbfinterface.c b/hal/phydm/txbf/haltxbfinterface.c new file mode 100644 index 0000000..c125fec --- /dev/null +++ b/hal/phydm/txbf/haltxbfinterface.c @@ -0,0 +1,1484 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/************************************************************* + * Description: + * + * This file is for TXBF interface mechanism + * + ************************************************************/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void beamforming_gid_paid( + void *adapter, + PRT_TCB tcb) +{ + u8 RA[6] = {0}; + u8 *p_header = GET_FRAME_OF_FIRST_FRAG(adapter, tcb); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + + if (((PADAPTER)adapter)->HardwareType < HARDWARE_TYPE_RTL8192EE) + return; + else if (IS_WIRELESS_MODE_N((PADAPTER)adapter) == false) + return; + +#if (SUPPORT_MU_BF == 1) + if (tcb->tx_bf_pkt_type == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* @MU NDPA */ +#else + if (0) { +#endif + /* @Fill G_ID and P_AID */ + tcb->G_ID = 63; + if (beam_info->first_mu_bfee_index < BEAMFORMEE_ENTRY_NUM) { + tcb->P_AID = beam_info->beamformee_entry[beam_info->first_mu_bfee_index].p_aid; + RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID)); + } + } else { + GET_80211_HDR_ADDRESS1(p_header, &RA); + + /* VHT SU PPDU carrying one or more group addressed MPDUs or */ + /* Transmitting a VHT NDP intended for multiple recipients */ + if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || tcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { + tcb->G_ID = 63; + tcb->P_AID = 0; + } else if (ACTING_AS_AP(adapter)) { + u16 AID = (u16)(MacIdGetOwnerAssociatedClientAID(adapter, tcb->macId) & 0x1ff); /*@AID[0:8]*/ + + /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s tcb->mac_id=0x%X, AID=0x%X\n", __func__, tcb->mac_id, AID));*/ + tcb->G_ID = 63; + + if (AID == 0) /*@A PPDU sent by an AP to a non associated STA*/ + tcb->P_AID = 0; + else { /*Sent by an AP and addressed to a STA associated with that AP*/ + u16 BSSID = 0; + GET_80211_HDR_ADDRESS2(p_header, &RA); + BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*@BSSID[44:47] xor BSSID[40:43]*/ + tcb->P_AID = (AID + BSSID * 32) & 0x1ff; /*@(dec(A) + dec(B)*32) mod 512*/ + } + } else if (ACTING_AS_IBSS(((PADAPTER)adapter))) { + tcb->G_ID = 63; + /*P_AID for infrasturcture mode; MACID for ad-hoc mode. */ + tcb->P_AID = tcb->macId; + } else if (MgntLinkStatusQuery(adapter)) { /*@Addressed to AP*/ + tcb->G_ID = 0; + GET_80211_HDR_ADDRESS1(p_header, &RA); + tcb->P_AID = RA[5]; /*RA[39:47]*/ + tcb->P_AID = (tcb->P_AID << 1) | (RA[4] >> 7); + } else { + tcb->G_ID = 63; + tcb->P_AID = 0; + } + /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, tcb->G_ID, tcb->P_AID));*/ + } +} + +enum rt_status +beamforming_get_report_frame( + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + u8 *p_mimo_ctrl_field, p_csi_matrix; + u8 idx, nc, nr, CH_W; + u16 csi_matrix_len = 0; + + ACT_PKT_TYPE pkt_type = ACT_PKT_TYPE_UNKNOWN; + + /* @Memory comparison to see if CSI report is the same with previous one */ + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, Frame_Addr2(*p_pdu_os), &idx); + + if (beamform_entry == NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Cannot find entry by addr\n", + __func__); + return RT_STATUS_FAILURE; + } + + pkt_type = PacketGetActionFrameType(p_pdu_os); + + /* @-@ Modified by David */ + if (pkt_type == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) { + p_mimo_ctrl_field = p_pdu_os->Octet + 26; + nc = ((*p_mimo_ctrl_field) & 0x7) + 1; + nr = (((*p_mimo_ctrl_field) & 0x38) >> 3) + 1; + CH_W = (((*p_mimo_ctrl_field) & 0xC0) >> 6); + /*p_csi_matrix = p_mimo_ctrl_field + 3 + nc;*/ /* 24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */ + csi_matrix_len = p_pdu_os->Length - 26 - 3 - nc; + } else if (pkt_type == ACT_PKT_HT_COMPRESSED_BEAMFORMING) { + p_mimo_ctrl_field = p_pdu_os->Octet + 26; + nc = ((*p_mimo_ctrl_field) & 0x3) + 1; + nr = (((*p_mimo_ctrl_field) & 0xC) >> 2) + 1; + CH_W = (((*p_mimo_ctrl_field) & 0x10) >> 4); + /*p_csi_matrix = p_mimo_ctrl_field + 6 + nr;*/ /* 24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(nc=2) */ + csi_matrix_len = p_pdu_os->Length - 26 - 6 - nr; + } else + return RT_STATUS_SUCCESS; + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] idx=%d, pkt type=%d, nc=%d, nr=%d, CH_W=%d\n", __func__, + idx, pkt_type, nc, nr, CH_W); + + return RT_STATUS_SUCCESS; +} + +void construct_ht_ndpa_packet( + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? + //void *adapter = dm->adapter; + ADAPTER * adapter, + //void *adapter, + u8 *RA, + u8 *buffer, + u32 *p_length, + enum channel_width BW) +{ + u16 duration = 0; + PMGNT_INFO mgnt_info = &(((PADAPTER)adapter)->MgntInfo); + //PMGNT_INFO mgnt_info = &((MGNT_INFO)(((PADAPTER)adapter)->MgntInfo)); + OCTET_STRING p_ndpa_frame, action_content; + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + + PlatformZeroMemory(buffer, 32); + + SET_80211_HDR_FRAME_CONTROL(buffer, 0); + + SET_80211_HDR_ORDER(buffer, 1); + SET_80211_HDR_TYPE_AND_SUBTYPE(buffer, Type_Action_No_Ack); + + SET_80211_HDR_ADDRESS1(buffer, RA); + SET_80211_HDR_ADDRESS2(buffer, ((PADAPTER)adapter)->CurrentAddress); + SET_80211_HDR_ADDRESS3(buffer, ((PMGNT_INFO)mgnt_info)->Bssid); + + duration = 2 * a_SifsTime + 40; + + if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SET_80211_HDR_DURATION(buffer, duration); + + /* @HT control field */ + SET_HT_CTRL_CSI_STEERING(buffer + sMacHdrLng, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(buffer + sMacHdrLng, 1); + + FillOctetString(p_ndpa_frame, buffer, sMacHdrLng + sHTCLng); + + FillOctetString(action_content, action_hdr, 4); + PacketAppendData(&p_ndpa_frame, action_content); + + *p_length = 32; +} + +boolean +send_fw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u32 buf_len; + u8 *buf_addr; + u8 desc_len = 0, idx = 0, ndp_tx_rate; + void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter)); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (beamform_entry == NULL) + return false; + + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) { +#if (DEV_BUS_TYPE != RT_PCI_INTERFACE) + desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength; +#endif + buf_addr = p_buf->Buffer.VirtualAddress + desc_len; + + construct_ht_ndpa_packet( + adapter, + RA, + buf_addr, + &buf_len, + BW); + + tcb->PacketLength = buf_len + desc_len; + + tcb->bTxEnableSwCalcDur = true; + + tcb->BWOfPacket = BW; + + if (ACTING_AS_IBSS(((PADAPTER)adapter)) || ACTING_AS_AP(((PADAPTER)adapter))) + tcb->G_ID = 63; + + tcb->P_AID = beamform_entry->p_aid; + tcb->DataRate = ndp_tx_rate; /*rate of NDP decide by nr*/ + + ((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(((PADAPTER)adapter), tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +boolean +send_sw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, ndp_tx_rate = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { + construct_ht_ndpa_packet( + adapter, + RA, + p_buf->Buffer.VirtualAddress, + &tcb->PacketLength, + BW); + + tcb->bTxEnableSwCalcDur = true; + + tcb->BWOfPacket = BW; + + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +void construct_vht_ndpa_packet( + struct dm_struct *dm, + u8 *RA, + u16 AID, + u8 *buffer, + u32 *p_length, + enum channel_width BW) +{ + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? + //void *adapter = dm->adapter; + ADAPTER * adapter = (PADAPTER)(dm->adapter); + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + /* @Frame control. */ + SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(p_ndpa_frame, RA); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, beamform_entry->my_mac_addr); + + // 2017/11 MH PHYDM compile. But why need to use windows maco? + // For all linux code, it should be useless? + duration = 2 * a_SifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SET_80211_HDR_DURATION(p_ndpa_frame, duration); + + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); + + if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap) == false) + AID = 0; + + sta_info.aid = AID; + sta_info.feedback_type = 0; + sta_info.nc_index = 0; + + odm_move_memory(dm, p_ndpa_frame + 17, (u8 *)&sta_info, 2); + + *p_length = 19; +} + +boolean +send_fw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u32 buf_len; + u8 *buf_addr; + u8 desc_len = 0, idx = 0, ndp_tx_rate = 0; + void *p_def_adapter = GetDefaultAdapter(((PADAPTER)adapter)); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (beamform_entry == NULL) + return false; + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(p_def_adapter, &tcb, &p_buf)) { +#if (DEV_BUS_TYPE != RT_PCI_INTERFACE) + desc_len = ((PADAPTER)adapter)->HWDescHeadLength - hal_data->USBALLDummyLength; +#endif + buf_addr = p_buf->Buffer.VirtualAddress + desc_len; + + construct_vht_ndpa_packet( + dm, + RA, + AID, + buf_addr, + &buf_len, + BW); + + tcb->PacketLength = buf_len + desc_len; + + tcb->bTxEnableSwCalcDur = true; + + tcb->BWOfPacket = BW; + + if (phydm_acting_determine(dm, phydm_acting_as_ibss) || phydm_acting_determine(dm, phydm_acting_as_ap)) + tcb->G_ID = 63; + + tcb->P_AID = beamform_entry->p_aid; + tcb->DataRate = ndp_tx_rate; /*@decide by nr*/ + + ((PADAPTER)adapter)->HalFunc.CmdSendPacketHandler(adapter, tcb, p_buf, tcb->PacketLength, DESC_PACKET_TYPE_NORMAL, false); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] End, ret=%d\n", __func__, ret); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +boolean +send_sw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, ndp_tx_rate = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { + construct_vht_ndpa_packet( + dm, + RA, + AID, + p_buf->Buffer.VirtualAddress, + &tcb->PacketLength, + BW); + + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; + + /*rate of NDP decide by nr*/ + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) +/*@ + * Description: On VHT GID management frame by an MU beamformee. + * + * 2015.05.20. Created by tynli. + */ +enum rt_status +beamforming_get_vht_gid_mgnt_frame( + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + enum rt_status rt_status = RT_STATUS_SUCCESS; + u8 *p_buffer = NULL; + u8 *p_raddr = NULL; + u8 mem_status[8] = {0}, user_pos[16] = {0}; + u8 idx; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMER_ENTRY *beamform_entry = &beam_info->beamformer_entry[beam_info->mu_ap_index]; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] On VHT GID mgnt frame!\n", __func__); + + /* @Check length*/ + if (p_pdu_os->length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY + 16)) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Invalid length (%d)\n", __func__, + p_pdu_os->length); + return RT_STATUS_INVALID_LENGTH; + } + + /* @Check RA*/ + p_raddr = (u8 *)(p_pdu_os->Octet) + 4; + if (!eq_mac_addr(p_raddr, adapter->CurrentAddress)) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Drop because of RA error.\n", + __func__); + return RT_STATUS_PKT_DROP; + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", p_pdu_os->Octet, p_pdu_os->length); + + /*Parsing Membership status array*/ + p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; + for (idx = 0; idx < 8; idx++) { + mem_status[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); + beamform_entry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(p_buffer + idx); + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "mem_status: ", mem_status, 8); + + /* Parsing User Position array*/ + p_buffer = p_pdu_os->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; + for (idx = 0; idx < 16; idx++) { + user_pos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); + beamform_entry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(p_buffer + idx); + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "user_pos: ", user_pos, 16); + + /* @Group ID detail printed*/ + { + u8 i, j; + u8 tmp_val; + u16 tmp_val2; + + for (i = 0; i < 8; i++) { + tmp_val = mem_status[i]; + tmp_val2 = ((user_pos[i * 2 + 1] << 8) & 0xFF00) + (user_pos[i * 2] & 0xFF); + for (j = 0; j < 8; j++) { + if ((tmp_val >> j) & BIT(0)) { + PHYDM_DBG(dm, DBG_TXBF, "Use Group ID (%d), User Position (%d)\n", + (i * 8 + j), (tmp_val2 >> 2 * j) & 0x3); + } + } + } + } + + /* @Indicate GID frame to IHV service. */ + { + u8 indibuffer[24] = {0}; + u8 indioffset = 0; + + PlatformMoveMemory(indibuffer + indioffset, beamform_entry->gid_valid, 8); + indioffset += 8; + PlatformMoveMemory(indibuffer + indioffset, beamform_entry->user_position, 16); + indioffset += 16; + + PlatformIndicateCustomStatus( + adapter, + RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME, + RT_CUSTOM_INDI_TARGET_IHV, + indibuffer, + indioffset); + } + + /* @Config HW GID table */ + hal_com_txbf_config_gtab(dm); + + return rt_status; +} + +/*@ + * Description: Construct VHT Group ID (GID) management frame. + * + * 2015.05.20. Created by tynli. + */ +void construct_vht_gid_mgnt_frame( + struct dm_struct *dm, + u8 *RA, + struct _RT_BEAMFORMEE_ENTRY *beamform_entry, + u8 *buffer, + u32 *p_length + + ) +{ + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + OCTET_STRING os_ftm_frame, tmp; + + FillOctetString(os_ftm_frame, buffer, 0); + *p_length = 0; + + ConstructMaFrameHdr( + adapter, + RA, + ACT_CAT_VHT, + ACT_VHT_GROUPID_MANAGEMENT, + &os_ftm_frame); + + /* @Membership status array*/ + FillOctetString(tmp, beamform_entry->gid_valid, 8); + PacketAppendData(&os_ftm_frame, tmp); + + /* User Position array*/ + FillOctetString(tmp, beamform_entry->user_position, 16); + PacketAppendData(&os_ftm_frame, tmp); + + *p_length = os_ftm_frame.length; + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_gid_mgnt_frame():\n", buffer, *p_length); +} + +boolean +send_sw_vht_gid_mgnt_frame( + void *dm_void, + u8 *RA, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 data_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = &beam_info->beamformee_entry[idx]; + void *adapter = beam_info->source_adapter; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { + construct_vht_gid_mgnt_frame( + dm, + RA, + beamform_entry, + p_buf->Buffer.VirtualAddress, + &tcb->PacketLength); + + tcb->bw_of_packet = CHANNEL_WIDTH_20; + data_rate = MGN_6M; + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +/*@ + * Description: Construct VHT beamforming report poll. + * + * 2015.05.20. Created by tynli. + */ +void construct_vht_bf_report_poll( + struct dm_struct *dm, + u8 *RA, + u8 *buffer, + u32 *p_length) +{ + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + u8 *p_bf_rpt_poll = buffer; + + /* @Frame control*/ + SET_80211_HDR_FRAME_CONTROL(p_bf_rpt_poll, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_bf_rpt_poll, Type_Beamforming_Report_Poll); + + /* @duration*/ + SET_80211_HDR_DURATION(p_bf_rpt_poll, 100); + + /* RA*/ + SET_VHT_BF_REPORT_POLL_RA(p_bf_rpt_poll, RA); + + /* TA*/ + SET_VHT_BF_REPORT_POLL_TA(p_bf_rpt_poll, adapter->CurrentAddress); + + /* @Feedback Segment Retransmission Bitmap*/ + SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(p_bf_rpt_poll, 0xFF); + + *p_length = 17; + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "construct_vht_bf_report_poll():\n", buffer, *p_length); +} + +boolean +send_sw_vht_bf_report_poll( + void *dm_void, + u8 *RA, + boolean is_final_poll) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 idx = 0, data_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + void *adapter = beam_info->source_adapter; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { + construct_vht_bf_report_poll( + dm, + RA, + p_buf->Buffer.VirtualAddress, + &tcb->PacketLength); + + tcb->bTxEnableSwCalcDur = true; /* @ need?*/ + tcb->BWOfPacket = CHANNEL_WIDTH_20; + + if (is_final_poll) + tcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; + else + tcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; + + data_rate = MGN_6M; /* @Legacy OFDM rate*/ + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, data_rate); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "send_sw_vht_bf_report_poll:\n", + p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +/*@ + * Description: Construct VHT MU NDPA packet. + * We should combine this function with construct_vht_ndpa_packet() in the future. + * + * 2015.05.21. Created by tynli. + */ +void construct_vht_mu_ndpa_packet( + struct dm_struct *dm, + enum channel_width BW, + u8 *buffer, + u32 *p_length) +{ + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + u8 idx; + u8 dest_addr[6] = {0}; + struct _RT_BEAMFORMEE_ENTRY *entry = NULL; + + /* @Fill the first MU BFee entry (STA1) MAC addr to destination address then + HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { + cp_mac_addr(dest_addr, entry->mac_addr); + break; + } + } + if (entry == NULL) + return; + + /* @Frame control.*/ + SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, entry->my_mac_addr); + + /*@--------------------------------------------*/ + /* @ Need to modify "duration" to MU consideration. */ + duration = 2 * a_SifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + /*@--------------------------------------------*/ + + SET_80211_HDR_DURATION(p_ndpa_frame, duration); + + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); + + *p_length = 17; + + /* @Construct STA info. for multiple STAs*/ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { + sta_info.aid = entry->AID; + sta_info.feedback_type = 1; /* @1'b1: MU*/ + sta_info.nc_index = 0; + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Get beamformee_entry idx(%d), AID =%d\n", + __func__, idx, entry->AID); + + odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + *p_length += 2; + } + } +} + +boolean +send_sw_vht_mu_ndpa_packet( + void *dm_void, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + + ndp_tx_rate = MGN_VHT2SS_MCS0; + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { + construct_vht_mu_ndpa_packet( + dm, + BW, + p_buf->Buffer.VirtualAddress, + &tcb->PacketLength); + + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; + tcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; + + /*rate of NDP decide by nr*/ + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +void dbg_construct_vht_mundpa_packet( + struct dm_struct *dm, + enum channel_width BW, + u8 *buffer, + u32 *p_length) +{ + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + u16 duration = 0; + u8 sequence = 0; + u8 *p_ndpa_frame = buffer; + struct _RT_NDPA_STA_INFO sta_info; + u8 idx; + u8 dest_addr[6] = {0}; + struct _RT_BEAMFORMEE_ENTRY *entry = NULL; + + boolean is_STA1 = false; + + /* @Fill the first MU BFee entry (STA1) MAC addr to destination address then + HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + entry = &(beam_info->beamformee_entry[idx]); + if (entry->is_mu_sta) { + if (is_STA1 == false) { + is_STA1 = true; + continue; + } else { + cp_mac_addr(dest_addr, entry->mac_addr); + break; + } + } + } + + /* @Frame control.*/ + SET_80211_HDR_FRAME_CONTROL(p_ndpa_frame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(p_ndpa_frame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(p_ndpa_frame, dest_addr); + SET_80211_HDR_ADDRESS2(p_ndpa_frame, dm->CurrentAddress); + + /*@--------------------------------------------*/ + /* @ Need to modify "duration" to MU consideration. */ + duration = 2 * a_SifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + /*@--------------------------------------------*/ + + SET_80211_HDR_DURATION(p_ndpa_frame, duration); + + sequence = *(dm->sounding_seq) << 2; + odm_move_memory(dm, p_ndpa_frame + 16, &sequence, 1); + + *p_length = 17; + + /*STA2's STA Info*/ + sta_info.aid = entry->aid; + sta_info.feedback_type = 1; /* @1'b1: MU */ + sta_info.nc_index = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Get beamformee_entry idx(%d), AID =%d\n", + __func__, idx, entry->aid); + + odm_move_memory(dm, p_ndpa_frame + (*p_length), (u8 *)&sta_info, 2); + *p_length += 2; +} + +boolean +dbg_send_sw_vht_mundpa_packet( + void *dm_void, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + PRT_TCB tcb; + PRT_TX_LOCAL_BUFFER p_buf; + boolean ret = true; + u8 ndp_tx_rate = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + void *adapter = beam_info->source_adapter; + + ndp_tx_rate = MGN_VHT2SS_MCS0; + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + + PlatformAcquireSpinLock(adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(adapter, &tcb, &p_buf)) { + dbg_construct_vht_mundpa_packet( + dm, + BW, + p_buf->Buffer.VirtualAddress, + &tcb->PacketLength); + + tcb->bTxEnableSwCalcDur = true; + tcb->BWOfPacket = BW; + tcb->TxBFPktType = RT_BF_PKT_TYPE_UNICAST_NDPA; + + /*rate of NDP decide by nr*/ + MgntSendPacket(adapter, tcb, p_buf, tcb->PacketLength, NORMAL_QUEUE, ndp_tx_rate); + } else + ret = false; + + PlatformReleaseSpinLock(adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", p_buf->Buffer.VirtualAddress, tcb->PacketLength); + + return ret; +} + +#endif /*@#if (SUPPORT_MU_BF == 1)*/ +#endif /*@#ifdef SUPPORT_MU_BF*/ + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +u32 beamforming_get_report_frame( + void *dm_void, + union recv_frame *precv_frame) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ret = _SUCCESS; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + u8 *pframe = precv_frame->u.hdr.rx_data; + u32 frame_len = precv_frame->u.hdr.len; + u8 *TA; + u8 idx, offset; + + /*@Memory comparison to see if CSI report is the same with previous one*/ + TA = get_addr2_ptr(pframe); + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, TA, &idx); + if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + offset = 31; /*@24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ + else if (beamform_entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + offset = 34; /*@24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(nc=2)*/ + else + return ret; + + return ret; +} + +boolean +send_fw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; + } + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + + pattrib->qsel = QSLT_BEACON; + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + pattrib->rate = ndp_tx_rate; + pattrib->bwmode = BW; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + set_order_bit(pframe); + set_frame_sub_type(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if (pmlmeext->cur_wireless_mode == WIRELESS_11B) + a_sifs_time = 10; + else + a_sifs_time = 16; + + duration = 2 * a_sifs_time + 40; + + if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + set_duration(pframe, duration); + + /* @HT control field */ + SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1); + + _rtw_memcpy(pframe + 28, action_hdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + + return true; +} + +boolean +send_sw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 action_hdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + ndp_tx_rate = beamforming_get_htndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; + } + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = ndp_tx_rate; + pattrib->bwmode = BW; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + set_order_bit(pframe); + set_frame_sub_type(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if (pmlmeext->cur_wireless_mode == WIRELESS_11B) + a_sifs_time = 10; + else + a_sifs_time = 16; + + duration = 2 * a_sifs_time + 40; + + if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + set_duration(pframe, duration); + + /*@HT control field*/ + SET_HT_CTRL_CSI_STEERING(pframe + 24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe + 24, 1); + + _rtw_memcpy(pframe + 28, action_hdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + + return true; +} + +boolean +send_fw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 sequence = 0, a_sifs_time = 0, ndp_tx_rate = 0, idx = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + struct _RT_NDPA_STA_INFO sta_info; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; + } + + /* update attribute */ + pattrib = &pmgntframe->attrib; + _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); + update_mgntframe_attrib(adapter, pattrib); + + pattrib->qsel = QSLT_BEACON; + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + pattrib->rate = ndp_tx_rate; + pattrib->bwmode = BW; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + set_frame_sub_type(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); + + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + a_sifs_time = 16; + else + a_sifs_time = 10; + + duration = 2 * a_sifs_time + 44; + + if (BW == CHANNEL_WIDTH_80) + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + set_duration(pframe, duration); + + sequence = beam_info->sounding_sequence << 2; + if (beam_info->sounding_sequence >= 0x3f) + beam_info->sounding_sequence = 0; + else + beam_info->sounding_sequence++; + + _rtw_memcpy(pframe + 16, &sequence, 1); + + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) + AID = 0; + + sta_info.aid = AID; + sta_info.feedback_type = 0; + sta_info.nc_index = 0; + + _rtw_memcpy(pframe + 17, (u8 *)&sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + + return true; +} + +boolean +send_sw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ADAPTER *adapter = dm->adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct _RT_NDPA_STA_INFO ndpa_sta_info; + u8 ndp_tx_rate = 0, sequence = 0, a_sifs_time = 0, idx = 0; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + ndp_tx_rate = beamforming_get_vht_ndp_tx_rate(dm, beamform_entry->comp_steering_num_of_bfer); + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndp_tx_rate =%d\n", __func__, + ndp_tx_rate); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, alloc mgnt frame fail\n", + __func__); + return false; + } + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); + update_mgntframe_attrib(adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = ndp_tx_rate; + pattrib->bwmode = BW; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + set_frame_sub_type(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, beamform_entry->my_mac_addr, ETH_ALEN); + + if (is_supported_5g(pmlmeext->cur_wireless_mode) || is_supported_ht(pmlmeext->cur_wireless_mode)) + a_sifs_time = 16; + else + a_sifs_time = 10; + + duration = 2 * a_sifs_time + 44; + + if (BW == CHANNEL_WIDTH_80) + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + set_duration(pframe, duration); + + sequence = beam_info->sounding_sequence << 2; + if (beam_info->sounding_sequence >= 0x3f) + beam_info->sounding_sequence = 0; + else + beam_info->sounding_sequence++; + + _rtw_memcpy(pframe + 16, &sequence, 1); + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) + AID = 0; + + ndpa_sta_info.aid = AID; + ndpa_sta_info.feedback_type = 0; + ndpa_sta_info.nc_index = 0; + + _rtw_memcpy(pframe + 17, (u8 *)&ndpa_sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(adapter, pmgntframe); + PHYDM_DBG(dm, DBG_TXBF, "[%s] [%d]\n", __func__, __LINE__); + + return true; +} + +#endif + +void beamforming_get_ndpa_frame( + void *dm_void, +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + OCTET_STRING pdu_os +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + union recv_frame *precv_frame +#endif + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 *TA; + u8 idx, sequence; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 *p_ndpa_frame = pdu_os.Octet; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + u8 *p_ndpa_frame = precv_frame->u.hdr.rx_data; +#endif + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; /*@Modified By Jeffery @2014-10-29*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "beamforming_get_ndpa_frame\n", + pdu_os.Octet, pdu_os.Length); + if (IsCtrlNDPA(p_ndpa_frame) == false) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (get_frame_sub_type(p_ndpa_frame) != WIFI_NDPA) +#endif + return; + else if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821))) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] not 8812 or 8821A, return\n", + __func__); + return; + } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + TA = Frame_Addr2(pdu_os); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + TA = get_addr2_ptr(p_ndpa_frame); +#endif + /*Remove signaling TA. */ + TA[0] = TA[0] & 0xFE; + + beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, TA, &idx); /* @Modified By Jeffery @2014-10-29 */ + + /*@Break options for Clock Reset*/ + if (beamformer_entry == NULL) + return; + else if (!(beamformer_entry->beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU)) + return; + /*@log_success: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ + /*@clock_reset_times: While BFer entry always doesn't receive our CSI, clock will reset again and again.So clock_reset_times is limited to 5 times.2015-04-13, Jeffery*/ + else if ((beamformer_entry->log_success == 1) || (beamformer_entry->clock_reset_times == 5)) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, log_success=%d, clock_reset_times=%d, clock reset is no longer needed.\n", + __func__, beamformer_entry->log_seq, + beamformer_entry->pre_log_seq, + beamformer_entry->log_retry_cnt, + beamformer_entry->log_success, + beamformer_entry->clock_reset_times); + + return; + } + + sequence = (p_ndpa_frame[16]) >> 2; + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Start, sequence=%d, log_seq=%d, pre_log_seq=%d, log_retry_cnt=%d, clock_reset_times=%d, log_success=%d\n", + __func__, sequence, beamformer_entry->log_seq, + beamformer_entry->pre_log_seq, + beamformer_entry->log_retry_cnt, + beamformer_entry->clock_reset_times, + beamformer_entry->log_success); + + if (beamformer_entry->log_seq != 0 && beamformer_entry->pre_log_seq != 0) { + /*Success condition*/ + if (beamformer_entry->log_seq != sequence && beamformer_entry->pre_log_seq != beamformer_entry->log_seq) { + /* @break option for clcok reset, 2015-03-30, Jeffery */ + beamformer_entry->log_retry_cnt = 0; + /*@As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ + /*That is, log_success is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ + beamformer_entry->log_success = 1; + + } else { /*@Fail condition*/ + + if (beamformer_entry->log_retry_cnt == 5) { + beamformer_entry->clock_reset_times++; + beamformer_entry->log_retry_cnt = 0; + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Clock Reset!!! clock_reset_times=%d\n", + __func__, + beamformer_entry->clock_reset_times); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_CLK, NULL); + + } else + beamformer_entry->log_retry_cnt++; + } + } + + /*Update log_seq & pre_log_seq*/ + beamformer_entry->pre_log_seq = beamformer_entry->log_seq; + beamformer_entry->log_seq = sequence; +} + +#endif diff --git a/hal/phydm/txbf/haltxbfinterface.h b/hal/phydm/txbf/haltxbfinterface.h new file mode 100644 index 0000000..b97aa34 --- /dev/null +++ b/hal/phydm/txbf/haltxbfinterface.h @@ -0,0 +1,167 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HAL_TXBF_INTERFACE_H__ +#define __HAL_TXBF_INTERFACE_H__ + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define a_SifsTime ((IS_WIRELESS_MODE_5G(adapter) || IS_WIRELESS_MODE_N_24G(adapter)) ? 16 : 10) + +void beamforming_gid_paid( + void *adapter, + PRT_TCB tcb); + +enum rt_status +beamforming_get_report_frame( + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os); + +void beamforming_get_ndpa_frame( + void *dm_void, + OCTET_STRING pdu_os); + +boolean +send_fw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW); + +boolean +send_fw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); + +boolean +send_sw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); + +boolean +send_sw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW); + +#if (SUPPORT_MU_BF == 1) +enum rt_status +beamforming_get_vht_gid_mgnt_frame( + void *adapter, + PRT_RFD rfd, + POCTET_STRING p_pdu_os); + +boolean +send_sw_vht_gid_mgnt_frame( + void *dm_void, + u8 *RA, + u8 idx); + +boolean +send_sw_vht_bf_report_poll( + void *dm_void, + u8 *RA, + boolean is_final_poll); + +boolean +send_sw_vht_mu_ndpa_packet( + void *dm_void, + enum channel_width BW); +#else +#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE +#define send_sw_vht_gid_mgnt_frame(dm_void, RA) +#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(dm_void, BW) +#endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +u32 beamforming_get_report_frame( + void *dm_void, + union recv_frame *precv_frame); + +boolean +send_fw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW); + +boolean +send_sw_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW); + +boolean +send_fw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); + +boolean +send_sw_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW); +#endif + +void beamforming_get_ndpa_frame( + void *dm_void, +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + OCTET_STRING pdu_os +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + union recv_frame *precv_frame +#endif + ); + +boolean +dbg_send_sw_vht_mundpa_packet( + void *dm_void, + enum channel_width BW); + +#else +#define beamforming_get_ndpa_frame(dm, _pdu_os) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define beamforming_get_report_frame(adapter, precv_frame) RT_STATUS_FAILURE +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define beamforming_get_report_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE +#define beamforming_get_vht_gid_mgnt_frame(adapter, rfd, p_pdu_os) RT_STATUS_FAILURE +#endif +#define send_fw_ht_ndpa_packet(dm_void, RA, BW) +#define send_sw_ht_ndpa_packet(dm_void, RA, BW) +#define send_fw_vht_ndpa_packet(dm_void, RA, AID, BW) +#define send_sw_vht_ndpa_packet(dm_void, RA, AID, BW) +#define send_sw_vht_gid_mgnt_frame(dm_void, RA, idx) +#define send_sw_vht_bf_report_poll(dm_void, RA, is_final_poll) +#define send_sw_vht_mu_ndpa_packet(dm_void, BW) +#endif + +#endif diff --git a/hal/phydm/txbf/haltxbfjaguar.c b/hal/phydm/txbf/haltxbfjaguar.c new file mode 100644 index 0000000..6f18928 --- /dev/null +++ b/hal/phydm/txbf/haltxbfjaguar.c @@ -0,0 +1,509 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/************************************************************* + * Description: + * + * This file is for 8812/8821/8811 TXBF mechanism + * + ************************************************************/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) +void hal_txbf_8812a_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8812A, (rate << 2 | BW)); +} + +void hal_txbf_jaguar_rf_mode( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->rf_type == RF_1T1R) + return; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] set TxIQGen\n", __func__); + + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); /*RF mode table write enable*/ + + if (beam_info->beamformee_su_cnt > 0) { + /* Paath_A */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/ + /* Path_B */ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xE26BF); /*@Enable TXIQGEN in RX mode*/ + } else { + /* Paath_A */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/ + /* Path_B */ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0x78000, 0x3); /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x3F7FF); /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0xC26BF); /*@Disable TXIQGEN in RX mode*/ + } + + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); /*RF mode table write disable*/ + + if (beam_info->beamformee_su_cnt > 0) + odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x33); + else + odm_set_bb_reg(dm, R_0x80c, MASKBYTE1, 0x11); +} + +void hal_txbf_jaguar_download_ndpa( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 u1b_tmp = 0, tmp_reg422 = 0, head_page; + u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0; + boolean is_send_beacon = false; + u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*@default reseved 1 page for the IC type which is undefined.*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + void *adapter = dm->adapter; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *dm->is_fw_dw_rsvd_page_in_progress = true; +#endif + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + /* if (idx == 0) head_page = 0xFE; */ + /* else head_page = 0xFE;*/ + head_page = 0xFE; + + phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1); + odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp | BIT(0))); + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2); + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422 & (~BIT(6))); + + if (tmp_reg422 & BIT(6)) { + PHYDM_DBG(dm, DBG_TXBF, + "SetBeamformDownloadNDPA_8812(): There is an adapter is sending beacon.\n"); + is_send_beacon = true; + } + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + odm_write_1byte(dm, REG_TDECTRL_8812A + 1, head_page); + + do { + /*@Clear beacon valid check bit.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); + odm_write_1byte(dm, REG_TDECTRL_8812A + 2, (bcn_valid_reg | BIT(0))); + + /*@download NDPA rsvd page.*/ + if (p_beam_entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + beamforming_send_vht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->aid, p_beam_entry->sound_bw, BEACON_QUEUE); + else + beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE); + + /*@check rsvd page download OK.*/ + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); + count = 0; + while (!(bcn_valid_reg & BIT(0)) && count < 20) { + count++; + ODM_delay_ms(10); + bcn_valid_reg = odm_read_1byte(dm, REG_TDECTRL_8812A + 2); + } + dl_bcn_count++; + } while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5); + + if (!(bcn_valid_reg & BIT(0))) + PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n", + __func__); + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + odm_write_1byte(dm, REG_TDECTRL_8812A + 1, tx_page_bndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ + /*the beacon cannot be sent by HW.*/ + /*@2010.06.23. Added by tynli.*/ + if (is_send_beacon) + odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8812A + 2, tmp_reg422); + + /*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1b_tmp = odm_read_1byte(dm, REG_CR_8812A + 1); + odm_write_1byte(dm, REG_CR_8812A + 1, (u1b_tmp & (~BIT(0)))); + + p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *dm->is_fw_dw_rsvd_page_in_progress = false; +#endif +} + +void hal_txbf_jaguar_fw_txbf_cmd( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx, period0 = 0, period1 = 0; + u8 PageNum0 = 0xFF, PageNum1 = 0xFF; + u8 u1_tx_bf_parm[3] = {0}; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + /*@Modified by David*/ + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (idx == 0) { + if (beam_info->beamformee_entry[idx].is_sound) + PageNum0 = 0xFE; + else + PageNum0 = 0xFF; /*stop sounding*/ + period0 = (u8)(beam_info->beamformee_entry[idx].sound_period); + } else if (idx == 1) { + if (beam_info->beamformee_entry[idx].is_sound) + PageNum1 = 0xFE; + else + PageNum1 = 0xFF; /*stop sounding*/ + period1 = (u8)(beam_info->beamformee_entry[idx].sound_period); + } + } + } + + u1_tx_bf_parm[0] = PageNum0; + u1_tx_bf_parm[1] = PageNum1; + u1_tx_bf_parm[2] = (period1 << 4) | period0; + odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm); + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n", + __func__, PageNum0, period0, PageNum1, period1); +} + +void hal_txbf_jaguar_enter( + void *dm_void, + u8 bfer_bfee_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4; + u8 bfee_idx = (bfer_bfee_idx & 0xF); + u32 csi_param; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + u16 sta_id = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!\n", __func__); + + hal_txbf_jaguar_rf_mode(dm, beamforming_info); + + if (dm->rf_type == RF_2T2R) + odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x00000000); /*nc =2*/ + else + odm_set_bb_reg(dm, ODM_REG_CSI_CONTENT_VALUE, MASKDWORD, 0x01081008); /*nc =1*/ + + if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[bfer_idx]; + + /*Sounding protocol control*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB); + + /*@MAC address/Partial AID of Beamformer*/ + if (bfer_idx == 0) { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_BFMER0_INFO_8812A + i), beamformer_entry.mac_addr[i]); + /*@CSI report use legacy ofdm so don't need to fill P_AID. */ + /*platform_efio_write_2byte(adapter, REG_BFMER0_INFO_8812A+6, beamform_entry.P_AID); */ + } else { + for (i = 0; i < 6; i++) + odm_write_1byte(dm, (REG_BFMER1_INFO_8812A + i), beamformer_entry.mac_addr[i]); + /*@CSI report use legacy ofdm so don't need to fill P_AID.*/ + /*platform_efio_write_2byte(adapter, REG_BFMER1_INFO_8812A+6, beamform_entry.P_AID);*/ + } + + /*@CSI report parameters of Beamformee*/ + if (beamformer_entry.beamform_entry_cap & BEAMFORMEE_CAP_VHT_SU) { + if (dm->rf_type == RF_2T2R) + csi_param = 0x01090109; + else + csi_param = 0x01080108; + } else { + if (dm->rf_type == RF_2T2R) + csi_param = 0x03090309; + else + csi_param = 0x03080308; + } + + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, csi_param); + odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, csi_param); + + /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); + } + + if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) { + beamformee_entry = beamforming_info->beamformee_entry[bfee_idx]; + + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + sta_id = beamformee_entry.mac_id; + else + sta_id = beamformee_entry.p_aid; + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (bfee_idx == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8812A, sta_id); + odm_write_1byte(dm, REG_TXBF_CTRL_8812A + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8812A + 3) | BIT(4) | BIT(6) | BIT(7)); + } else + odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, sta_id | BIT(12) | BIT(14) | BIT(15)); + + /*@CSI report parameters of Beamformee*/ + if (bfee_idx == 0) { + /*@Get BIT24 & BIT25*/ + u8 tmp = odm_read_1byte(dm, REG_BFMEE_SEL_8812A + 3) & 0x3; + + odm_write_1byte(dm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A, sta_id | BIT(9)); + } else { + /*Set BIT25*/ + odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, sta_id | 0xE200); + } + phydm_beamforming_notify(dm); + } +} + +void hal_txbf_jaguar_leave( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + + if (idx < BEAMFORMER_ENTRY_NUM) { + beamformer_entry = beamforming_info->beamformer_entry[idx]; + beamformee_entry = beamforming_info->beamformee_entry[idx]; + } else + return; + + PHYDM_DBG(dm, DBG_TXBF, "[%s]Start!, IDx = %d\n", __func__, idx); + + /*@Clear P_AID of Beamformee*/ + /*@Clear MAC address of Beamformer*/ + /*@Clear Associated Bfmee Sel*/ + + if (beamformer_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8); + if (idx == 0) { + odm_write_4byte(dm, REG_BFMER0_INFO_8812A, 0); + odm_write_2byte(dm, REG_BFMER0_INFO_8812A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + } else { + odm_write_4byte(dm, REG_BFMER1_INFO_8812A, 0); + odm_write_2byte(dm, REG_BFMER1_INFO_8812A + 4, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + odm_write_2byte(dm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + } + } + + if (beamformee_entry.beamform_entry_cap == BEAMFORMING_CAP_NONE) { + hal_txbf_jaguar_rf_mode(dm, beamforming_info); + if (idx == 0) { + odm_write_2byte(dm, REG_TXBF_CTRL_8812A, 0x0); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A, 0); + } else { + odm_write_2byte(dm, REG_TXBF_CTRL_8812A + 2, odm_read_2byte(dm, REG_TXBF_CTRL_8812A + 2) & 0xF000); + odm_write_2byte(dm, REG_BFMEE_SEL_8812A + 2, odm_read_2byte(dm, REG_BFMEE_SEL_8812A + 2) & 0x60); + } + } +} + +void hal_txbf_jaguar_status( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 beam_ctrl_val; + u32 beam_ctrl_reg; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx]; + + if (phydm_acting_determine(dm, phydm_acting_as_ibss)) + beam_ctrl_val = beamform_entry.mac_id; + else + beam_ctrl_val = beamform_entry.p_aid; + + if (idx == 0) + beam_ctrl_reg = REG_TXBF_CTRL_8812A; + else { + beam_ctrl_reg = REG_TXBF_CTRL_8812A + 2; + beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15); + } + + if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) { + if (beamform_entry.sound_bw == CHANNEL_WIDTH_20) + beam_ctrl_val |= BIT(9); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40) + beam_ctrl_val |= (BIT(9) | BIT(10)); + else if (beamform_entry.sound_bw == CHANNEL_WIDTH_80) + beam_ctrl_val |= (BIT(9) | BIT(10) | BIT(11)); + } else + beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11)); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] beam_ctrl_val = 0x%x!\n", __func__, + beam_ctrl_val); + + odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val); +} + +void hal_txbf_jaguar_fw_txbf( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + hal_txbf_jaguar_download_ndpa(dm, idx); + + hal_txbf_jaguar_fw_txbf_cmd(dm); +} + +void hal_txbf_jaguar_patch( + void *dm_void, + u8 operation) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE) + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (operation == SCAN_OPT_BACKUP_BAND0) + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xC8); + else if (operation == SCAN_OPT_RESTORE) + odm_write_1byte(dm, REG_SND_PTCL_CTRL_8812A, 0xCB); +#endif +} + +void hal_txbf_jaguar_clk_8812a( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 u2btmp; + u8 count = 0, u1btmp; + void *adapter = dm->adapter; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + if (*dm->is_scan_in_process) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] return by Scan\n", __func__); + return; + } +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + /*Stop PCIe TxDMA*/ + if (dm->support_interface == ODM_ITRF_PCIE) + odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); +#endif + +/*Stop Usb TxDMA*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISABLE_FUNC((PADAPTER)adapter, DF_TX_BIT); + PlatformReturnAllPendingTxPackets(adapter); +#else + rtw_write_port_cancel(adapter); +#endif + + /*Wait TXFF empty*/ + for (count = 0; count < 100; count++) { + u2btmp = odm_read_2byte(dm, REG_TXPKT_EMPTY_8812A); + u2btmp = u2btmp & 0xfff; + if (u2btmp != 0xfff) { + ODM_delay_ms(10); + continue; + } else + break; + } + + /*TX pause*/ + odm_write_1byte(dm, REG_TXPAUSE_8812A, 0xFF); + + /*Wait TX state Machine OK*/ + for (count = 0; count < 100; count++) { + if (odm_read_4byte(dm, REG_SCH_TXCMD_8812A) != 0) + continue; + else + break; + } + + /*Stop RX DMA path*/ + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT(2)); + + for (count = 0; count < 100; count++) { + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); + if (u1btmp & BIT(1)) + break; + else + ODM_delay_ms(10); + } + + /*@Disable clock*/ + odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xf0); + /*@Disable 320M*/ + odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); + /*@Enable 320M*/ + odm_write_1byte(dm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); + /*@Enable clock*/ + odm_write_1byte(dm, REG_SYS_CLKR_8812A + 1, 0xfc); + + /*Release Tx pause*/ + odm_write_1byte(dm, REG_TXPAUSE_8812A, 0); + + /*@Enable RX DMA path*/ + u1btmp = odm_read_1byte(dm, REG_RXDMA_CONTROL_8812A); + odm_write_1byte(dm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT(2))); +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + /*@Enable PCIe TxDMA*/ + if (dm->support_interface == ODM_ITRF_PCIE) + odm_write_1byte(dm, REG_PCIE_CTRL_REG_8812A + 1, 0); +#endif + /*Start Usb TxDMA*/ + RT_ENABLE_FUNC((PADAPTER)adapter, DF_TX_BIT); +} + +#endif + +#endif diff --git a/hal/phydm/txbf/haltxbfjaguar.h b/hal/phydm/txbf/haltxbfjaguar.h new file mode 100644 index 0000000..2c9a623 --- /dev/null +++ b/hal/phydm/txbf/haltxbfjaguar.h @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __HAL_TXBF_JAGUAR_H__ +#define __HAL_TXBF_JAGUAR_H__ +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) +#ifdef PHYDM_BEAMFORMING_SUPPORT + +void hal_txbf_8812a_set_ndpa_rate( + void *dm_void, + u8 BW, + u8 rate); + +void hal_txbf_jaguar_enter( + void *dm_void, + u8 idx); + +void hal_txbf_jaguar_leave( + void *dm_void, + u8 idx); + +void hal_txbf_jaguar_status( + void *dm_void, + u8 idx); + +void hal_txbf_jaguar_fw_txbf( + void *dm_void, + u8 idx); + +void hal_txbf_jaguar_patch( + void *dm_void, + u8 operation); + +void hal_txbf_jaguar_clk_8812a( + void *dm_void); +#else + +#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_jaguar_enter(dm_void, idx) +#define hal_txbf_jaguar_leave(dm_void, idx) +#define hal_txbf_jaguar_status(dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(dm_void, idx) +#define hal_txbf_jaguar_patch(dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(dm_void) +#endif +#else + +#define hal_txbf_8812a_set_ndpa_rate(dm_void, BW, rate) +#define hal_txbf_jaguar_enter(dm_void, idx) +#define hal_txbf_jaguar_leave(dm_void, idx) +#define hal_txbf_jaguar_status(dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(dm_void, idx) +#define hal_txbf_jaguar_patch(dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(dm_void) +#endif + +#endif /* @#ifndef __HAL_TXBF_JAGUAR_H__ */ diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.c b/hal/phydm/txbf/phydm_hal_txbf_api.c new file mode 100644 index 0000000..33a7e71 --- /dev/null +++ b/hal/phydm/txbf/phydm_hal_txbf_api.c @@ -0,0 +1,759 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (defined(CONFIG_BB_TXBF_API)) +#if (RTL8822B_SUPPORT == 1 || RTL8192F_SUPPORT == 1 || RTL8812F_SUPPORT == 1 ||\ + RTL8822C_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8814B_SUPPORT == 1) +/*@Add by YuChen for 8822B MU-MIMO API*/ + +/*this function is only used for BFer*/ +u8 phydm_get_ndpa_rate(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ndpa_rate = ODM_RATE6M; + + if (dm->rssi_min >= 30) /*@link RSSI > 30%*/ + ndpa_rate = ODM_RATE24M; + else if (dm->rssi_min <= 25) + ndpa_rate = ODM_RATE6M; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] ndpa_rate = 0x%x\n", __func__, ndpa_rate); + + return ndpa_rate; +} + +/*this function is only used for BFer*/ +u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput, + u8 total_bfee_num, u8 *tx_rate) +{ + u8 idx = 0; + u8 snddecision = 0xff; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + for (idx = 0; idx < total_bfee_num; idx++) { + if (dm->support_ic_type & (ODM_RTL8814A)) { + if ((tx_rate[idx] >= ODM_RATEVHTSS3MCS7 && + tx_rate[idx] <= ODM_RATEVHTSS3MCS9)) + snddecision = snddecision & ~(1 << idx); + } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C | + ODM_RTL8812 | ODM_RTL8192F)) { + if ((tx_rate[idx] >= ODM_RATEVHTSS2MCS7 && + tx_rate[idx] <= ODM_RATEVHTSS2MCS9)) + snddecision = snddecision & ~(1 << idx); + } else if (dm->support_ic_type & (ODM_RTL8814B)) { + if ((tx_rate[idx] >= ODM_RATEVHTSS4MCS7 && + tx_rate[idx] <= ODM_RATEVHTSS4MCS9)) + snddecision = snddecision & ~(1 << idx); + } + } + + for (idx = 0; idx < total_bfee_num; idx++) { + if (throughput[idx] <= 10) + snddecision = snddecision & ~(1 << idx); + } + + PHYDM_DBG(dm, DBG_TXBF, "[%s] soundingdecision = 0x%x\n", __func__, + snddecision); + + return snddecision; +} + +/*this function is only used for BFer*/ +u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput) +{ + u8 snding_score = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*throughput unit is Mbps*/ + if (throughput >= 500) + snding_score = 100; + else if (throughput >= 450) + snding_score = 90; + else if (throughput >= 400) + snding_score = 80; + else if (throughput >= 350) + snding_score = 70; + else if (throughput >= 300) + snding_score = 60; + else if (throughput >= 250) + snding_score = 50; + else if (throughput >= 200) + snding_score = 40; + else if (throughput >= 150) + snding_score = 30; + else if (throughput >= 100) + snding_score = 20; + else if (throughput >= 50) + snding_score = 10; + else + snding_score = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] snding_score = 0x%x\n", __func__, + snding_score); + + return snding_score; +} + +#endif +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nr_index = 0; + u8 ndp_tx_rate; +/*@Find nr*/ +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num); + else + nr_index = tx_bf_nr(1, bfer_str_num); + + switch (nr_index) { + case 1: + ndp_tx_rate = ODM_MGN_MCS8; + break; + + case 2: + ndp_tx_rate = ODM_MGN_MCS16; + break; + + case 3: + ndp_tx_rate = ODM_MGN_MCS24; + break; + + default: + ndp_tx_rate = ODM_MGN_MCS8; + break; + } +#else + ndp_tx_rate = ODM_MGN_MCS8; +#endif + + return ndp_tx_rate; +} + +u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 nr_index = 0; + u8 ndp_tx_rate; +/*@Find nr*/ +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & ODM_RTL8814A) + nr_index = tx_bf_nr(hal_txbf_8814a_get_ntx(dm), bfer_str_num); + else + nr_index = tx_bf_nr(1, bfer_str_num); + + switch (nr_index) { + case 1: + ndp_tx_rate = ODM_MGN_VHT2SS_MCS0; + break; + + case 2: + ndp_tx_rate = ODM_MGN_VHT3SS_MCS0; + break; + + case 3: + ndp_tx_rate = ODM_MGN_VHT4SS_MCS0; + break; + + default: + ndp_tx_rate = ODM_MGN_VHT2SS_MCS0; + break; + } +#else + ndp_tx_rate = ODM_MGN_VHT2SS_MCS0; +#endif + + return ndp_tx_rate; +} +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +/*this function is only used for BFer*/ +void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; + + if (dm->rf_type == RF_1T1R) + return; +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822C) { + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*Path A ==================*/ + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x2); + /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff, + 0x65AFF); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0); + + /*Path B ==================*/ + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff, + 0x996BF); + /*Select Standby mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 1); + /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff, + 0x99230); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0); + } + + /*@if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1); + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2); + odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1); + + /* logic mapping */ + /* TX BF logic map and TX path en for Nsts = 1~2 */ + odm_set_bb_reg(dm, R_0x820, 0xff, 0x33); + odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404); + odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33); + odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404); + } else { + /*@Disable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0); + odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0); + /*@1SS~2ss A, AB*/ + odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); + odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400); + } + } +#endif +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812F) { + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*Path A ==================*/ + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, 0x3, 0x3); + /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, 0xfffff, + 0x61AFE); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0); + + /*Path B ==================*/ + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x3f, 0xfffff, + 0xD86BF); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0); + } + + /*@if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1); + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2); + odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1); + + /* logic mapping */ + /* TX BF logic map and TX path en for Nsts = 1~2 */ + odm_set_bb_reg(dm, R_0x820, 0xff, 0x33); + odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404); + odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33); + odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404); + } else { + /*@Disable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0); + odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0); + /*@1SS~2ss A, AB*/ + odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); + odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400); + } + } +#endif +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8814B) { + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + for (i = RF_PATH_A; i <= RF_PATH_D; i++) { + /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, + BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, + 0xF, 2); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, + 0xfffff, 0x3fc); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, + 0xfffff, 0x280f7); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, + 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, + 0xfffff, 0x365); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, + 0xfffff, 0xafcf7); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, + BIT(19), 0x0); + } + } + /*@if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1); + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2); + odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1); + + /* logic mapping */ + /* TX BF logic map and TX path en for Nsts = 1~4 */ + //odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff); + /*verification path-AC*/ + //odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4); + } else { + /*@Disable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0); + odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0); + /*@1SS~4ss A, AB, ABC, ABCD*/ + //odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731); + //odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400); + } + } +#endif +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8198F) { + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + for (i = RF_PATH_A; i <= RF_PATH_D; i++) { + /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, + BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x30, + 0xfffff, 0x18000); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x31, + 0xfffff, 0x4f); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x32, + 0xfffff, 0x71fc0); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, + BIT(19), 0x0); + } + } + /*@if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1); + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2); + odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1); + + /* logic mapping */ + /* TX BF logic map and TX path en for Nsts = 1~4 */ + odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0xffff); + odm_set_bb_reg(dm, R_0x1e30, 0xffffffff, 0xe4e4e4e4); + } else { + /*@Disable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0); + odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0); + /*@1SS~4ss A, AB, ABC, ABCD*/ + odm_set_bb_reg(dm, R_0x820, 0xffff, 0xf731); + odm_set_bb_reg(dm, R_0x1e2c, 0xffffffff, 0xe4240400); + } + } +#endif +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type == ODM_RTL8197G) { + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*Path A ==================*/ + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x1); + /*Set RF Rx mode table*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, + 0x18000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, + 0x000cf); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, + 0x71fc2); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(19), 0x0); + + /*Path B ==================*/ + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x1); + /*Set RF Rx mode table*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, + 0x18000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, + 0x000cf); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, + 0x71fc2); + /*Set RF Standby mode table*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, + 0x18000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, + 0x000ef); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, + 0x01042); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, BIT(19), 0x0); + } + + /*@if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1); + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2); + odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1); + + /* logic mapping */ + /* TX BF logic map and TX path en for Nsts = 1~2 */ + odm_set_bb_reg(dm, R_0x820, 0xff, 0x33); + odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x404); + odm_set_bb_reg(dm, R_0x820, 0xffff0000, 0x33); + odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0x404); + } else { + /*@Disable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0); + odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0); + /*@1SS~2ss A, AB*/ + odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); + odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0x400); + } + } +#endif +} + +void phydm_mu_rsoml_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3; + + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s cnt reset\n", __func__); + + odm_memory_set(dm, &rateinfo->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2); + odm_memory_set(dm, &rateinfo->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2); +} + +void phydm_mu_rsoml_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3; + u32 val = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s\n", __func__); + + /*OFDM Tx*/ + val = odm_get_bb_reg(dm, R_0x820, MASKDWORD); + rateinfo->tx_path_en_ofdm_2sts = (u8)((val & 0xf0) >> 4); + rateinfo->tx_path_en_ofdm_1sts = (u8)(val & 0xf); + /*OFDM Rx*/ + rateinfo->rx_path_en_ofdm = (u8)odm_get_bb_reg(dm, R_0x824, 0xf0000); + + rateinfo->enable = 1; + rateinfo->mu_ratio_th = 30; + rateinfo->pre_mu_ratio = 0; + rateinfo->mu_set_trxpath = 0; + rateinfo->mu_been_iot = 0; + + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] %s tx1ss=%d, tx2ss=%d, rx=%d\n", + __func__, rateinfo->tx_path_en_ofdm_1sts, + rateinfo->tx_path_en_ofdm_2sts, rateinfo->rx_path_en_ofdm); + + phydm_mu_rsoml_reset(dm); +} + +void phydm_mu_rsoml_decision(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bf_rate_info_jgr3 *rateinfo = &dm->bf_rate_info_jgr3; + struct phydm_iot_center *iot_table = &dm->iot_table; + u8 offset = 0; + u32 mu_ratio = 0; + u32 su_pkt = 0; + u32 mu_pkt = 0; + u32 total_pkt = 0; + + if (rateinfo->tx_path_en_ofdm_2sts != 3 || + rateinfo->rx_path_en_ofdm != 3) { + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] Init Not 2T2R 22CE\n"); + return; + } + + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML Decision eanble: %d\n", + rateinfo->enable); + + if (!rateinfo->enable) + return; + + for (offset = 0; offset < VHT_RATE_NUM; offset++) { + mu_pkt += rateinfo->num_mu_vht_pkt[offset]; + su_pkt += rateinfo->num_qry_vht_pkt[offset]; + } + total_pkt = su_pkt + mu_pkt; + + if (total_pkt == 0) + mu_ratio = 0; + else + mu_ratio = (mu_pkt * 100) / total_pkt; // unit:% + + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] MU rx ratio: %d, total pkt: %d\n", + mu_ratio, total_pkt); + + if (mu_ratio > rateinfo->mu_ratio_th && + rateinfo->pre_mu_ratio > rateinfo->mu_ratio_th) { + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n"); + } else if (mu_ratio <= rateinfo->mu_ratio_th && + rateinfo->pre_mu_ratio <= rateinfo->mu_ratio_th) { + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML status remain\n"); + } else if (mu_ratio > rateinfo->mu_ratio_th) { + odm_set_bb_reg(dm, R_0xc00, BIT(26), 0); + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML OFF\n"); + } else { + odm_set_bb_reg(dm, R_0xc00, BIT(26), 1); + PHYDM_DBG(dm, DBG_TXBF, "[MU RSOML] RSOML ON\n"); + } + + PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] set_trxpath=%d, patch_10120200=%d\n", + rateinfo->mu_set_trxpath, iot_table->patch_id_10120200); + if (rateinfo->mu_set_trxpath && iot_table->patch_id_10120200) { + if (mu_ratio > rateinfo->mu_ratio_th) { + phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_A, + BB_PATH_AUTO); + PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T1R\n"); + rateinfo->mu_been_iot = 1; + } else { + phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, + BB_PATH_AUTO); + PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT 2T2R\n"); + rateinfo->mu_been_iot = 0; + } + } else if (rateinfo->mu_been_iot == 1) { + if (odm_get_bb_reg(dm, R_0x824, 0xf0000) == 1) { + phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, + BB_PATH_AUTO); + PHYDM_DBG(dm, DBG_TXBF, "[MU IOT] 22C IOT Restore\n"); + rateinfo->mu_been_iot = 0; + } + } + + rateinfo->pre_mu_ratio = mu_ratio; + phydm_mu_rsoml_reset(dm); +} + + +#if (RTL8814B_SUPPORT == 1) +void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; + + if (dm->rf_type == RF_1T1R) + return; + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + for (i = RF_PATH_A; i <= RF_PATH_D; i += 3) { + /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), + 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, + 0x3fc); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, + 0x280f7); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, + 0x365); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, + 0xafcf7); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), + 0x0); + } + for (i = RF_PATH_B; i <= RF_PATH_C; i++) { + /*RF mode table write enable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), + 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 2); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, + 0x280c7); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, + 0x280c7); + /*Select RX mode*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3e, 0xfffff, + 0x365); + /*Set Table data*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0x3f, 0xfffff, + 0xafcc7); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, (enum rf_path)i, RF_0xef, BIT(19), + 0x0); + } + } + /*@if Nsts > Nc, don't apply V matrix*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(11), 1); + + if (su_bfee_cnt > 0 || mu_bfee_cnt > 0) { + /*@enable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x2); + odm_set_bb_reg(dm, R_0x1e24, BIT(30), 1); + + /* logic mapping */ + /* TX BF logic map and TX path en for Nsts = 1~2 */ + odm_set_bb_reg(dm, R_0x820, 0xff0000, 0x33); /*seg0*/ + odm_set_bb_reg(dm, R_0x824, 0xff00, 0xcc); /*seg1*/ + odm_set_bb_reg(dm, R_0x1e30, 0xffff, 0xe4e4); + + } else { + /*@Disable BB TxBF ant mapping register*/ + odm_set_bb_reg(dm, R_0x1e24, BIT(28) | BIT29, 0x0); + odm_set_bb_reg(dm, R_0x1e24, BIT(31), 0); + /*@1SS~2ss A, AB*/ + odm_set_bb_reg(dm, R_0x820, 0xff, 0x31); /*seg0*/ + odm_set_bb_reg(dm, R_0x824, 0xff, 0xc8); /*seg1*/ + odm_set_bb_reg(dm, R_0x1e2c, 0xffff, 0xe420); + } +} +#endif +#endif /*PHYSTS_3RD_TYPE_IC*/ + +void phydm_txbf_avoid_hang(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /* avoid CCK CCA hang when the BF mode */ +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + odm_set_bb_reg(dm, R_0x1e6c, 0x100000, 0x1); +#endif + + /* avoid CCK CCA hang when the BFee mode for 92F */ +#if (RTL8192F_SUPPORT == 1) + odm_set_bb_reg(dm, R_0xa70, 0xffff0000, 0x80ff); +#endif +} + +void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[3] = {0}; + u32 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{BF ver1 :0}, {NO applyV:0; applyV:1; default:2}\n"); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{MU RSOML:1}, {MU enable:1/0}, {MU Ratio:40}\n"); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "{MU TRxPath:2}, {TRxPath enable:1/0}\n"); + return; + } + for (i = 0; i < 3; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + if (var1[0] == 0) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #ifdef PHYDM_BEAMFORMING_SUPPORT + struct _RT_BEAMFORMING_INFO *beamforming_info = NULL; + + beamforming_info = &dm->beamforming_info; + + if (var1[1] == 0) { + beamforming_info->apply_v_matrix = false; + beamforming_info->snding3ss = true; + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "\r\n dont apply V matrix and 3SS 789 snding\n"); + } else if (var1[1] == 1) { + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = true; + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "\r\n apply V matrix and 3SS 789 snding\n"); + } else if (var1[1] == 2) { + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = false; + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "\r\n default txbf setting\n"); + } else { + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "\r\n unknown cmd!!\n"); + } + #endif + #endif + } else if (var1[0] == 1) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3; + + bfinfo->enable = (u8)var1[1]; + bfinfo->mu_ratio_th = (u8)var1[2]; + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[MU RSOML] enable= %d, MU ratio TH= %d\n", + bfinfo->enable, bfinfo->mu_ratio_th); + #endif + } else if (var1[0] == 2) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bf_rate_info_jgr3 *bfinfo = &dm->bf_rate_info_jgr3; + + bfinfo->mu_set_trxpath = (u8)var1[1]; + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[MU TRxPath] mu_set_trxpath = %d\n", + bfinfo->mu_set_trxpath); + #endif + } +} + +#endif /*CONFIG_BB_TXBF_API*/ diff --git a/hal/phydm/txbf/phydm_hal_txbf_api.h b/hal/phydm/txbf/phydm_hal_txbf_api.h new file mode 100644 index 0000000..15659cc --- /dev/null +++ b/hal/phydm/txbf/phydm_hal_txbf_api.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __PHYDM_HAL_TXBF_API_H__ +#define __PHYDM_HAL_TXBF_API_H__ + +#if (defined(CONFIG_BB_TXBF_API)) + +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if defined(DM_ODM_CE_MAC80211) +#define tx_bf_nr(a, b) ({ \ + u8 __tx_bf_nr_a = (a); \ + u8 __tx_bf_nr_b = (b); \ + ((__tx_bf_nr_a > __tx_bf_nr_b) ? (__tx_bf_nr_b) : (__tx_bf_nr_a)); }) +#else +#define tx_bf_nr(a, b) ((a > b) ? (b) : (a)) +#endif + +u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num); + +u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num); + +#endif + +#if (RTL8822B_SUPPORT == 1 || RTL8822C_SUPPORT == 1 || RTL8192F_SUPPORT == 1 ||\ + RTL8814B_SUPPORT == 1 || RTL8198F_SUPPORT == 1 || RTL8812F_SUPPORT == 1) +u8 phydm_get_beamforming_sounding_info(void *dm_void, u16 *throughput, + u8 total_bfee_num, u8 *tx_rate); +u8 phydm_get_ndpa_rate(void *dm_void); + +u8 phydm_get_mu_bfee_snding_decision(void *dm_void, u16 throughput); + +#else +#define phydm_get_beamforming_sounding_info(dm, tp, bfee_num, rate) 0 +#define phydm_get_ndpa_rate(dm) +#define phydm_get_mu_bfee_snding_decision(dm, tp) + +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +struct phydm_bf_rate_info_jgr3 { + u8 enable; + u8 mu_ratio_th; + u32 pre_mu_ratio; + u16 num_mu_vht_pkt[VHT_RATE_NUM]; + u16 num_qry_vht_pkt[VHT_RATE_NUM]; + boolean mu_set_trxpath; + u8 tx_path_en_ofdm_1sts; + u8 tx_path_en_ofdm_2sts; + u8 rx_path_en_ofdm; + boolean mu_been_iot; +}; + +/*this function is only used for BFer*/ +void phydm_txbf_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt); +void phydm_txbf_avoid_hang(void *dm_void); +void phydm_mu_rsoml_init(void *dm_void); +void phydm_mu_rsoml_decision(void *dm_void); + +#if (RTL8814B_SUPPORT == 1) +void phydm_txbf_80p80_rfmode(void *dm_void, u8 su_bfee_cnt, u8 mu_bfee_cnt); +#endif + +#endif /*#PHYDM_IC_JGR3_SERIES_SUPPORT*/ +void phydm_bf_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); +#endif +#endif