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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __INC_HAL8188EPHYCFG_H__
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#define __INC_HAL8188EPHYCFG_H__
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 /* us */
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#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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#ifdef CONFIG_PCI_HCI
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#define MAX_AGGR_NUM 0x0B
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#else
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#define MAX_AGGR_NUM 0x07
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#endif /* CONFIG_PCI_HCI */
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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#define MAX_TX_COUNT_8188E 1
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/* BB/RF related */
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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/*
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* BB and RF register read/write
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* */
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u32 PHY_QueryBBReg8188E(PADAPTER Adapter,
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u32 RegAddr,
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u32 BitMask);
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void PHY_SetBBReg8188E(PADAPTER Adapter,
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u32 RegAddr,
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u32 BitMask,
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u32 Data);
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u32 PHY_QueryRFReg8188E(PADAPTER Adapter,
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enum rf_path eRFPath,
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u32 RegAddr,
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u32 BitMask);
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void PHY_SetRFReg8188E(PADAPTER Adapter,
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enum rf_path eRFPath,
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u32 RegAddr,
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u32 BitMask,
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u32 Data);
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/*
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* Initialization related function
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*/
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/* MAC/BB/RF HAL config */
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int PHY_MACConfig8188E(PADAPTER Adapter);
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int PHY_BBConfig8188E(PADAPTER Adapter);
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int PHY_RFConfig8188E(PADAPTER Adapter);
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/* RF config */
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int rtl8188e_PHY_ConfigRFWithParaFile( PADAPTER Adapter, u8 *pFileName, enum rf_path eRFPath);
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/*
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* RF Power setting
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*/
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/* extern BOOLEAN PHY_SetRFPowerState(PADAPTER Adapter,
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* RT_RF_POWER_STATE eRFPowerState); */
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/*
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* BB TX Power R/W
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* */
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void PHY_SetTxPowerLevel8188E(PADAPTER Adapter,
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u8 channel);
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void
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PHY_SetTxPowerIndex_8188E(
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PADAPTER Adapter,
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u32 PowerIndex,
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enum rf_path RFPath,
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u8 Rate
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);
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s8 phy_get_txpwr_target_extra_bias_8188e(_adapter *adapter, enum rf_path rfpath
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, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
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/*
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* Switch bandwidth for 8192S
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*/
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/* extern void PHY_SetBWModeCallback8192C(PRT_TIMER pTimer ); */
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void PHY_SetBWMode8188E(PADAPTER pAdapter,
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enum channel_width ChnlWidth,
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unsigned char Offset);
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/*
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* Set FW CMD IO for 8192S.
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*/
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/* extern BOOLEAN HalSetIO8192C(PADAPTER Adapter,
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* IO_TYPE IOType); */
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/*
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* Set A2 entry to fw for 8192S
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* */
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extern void FillA2Entry8192C(PADAPTER Adapter,
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u8 index,
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u8 *val);
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/*
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* channel switch related funciton
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*/
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/* extern void PHY_SwChnlCallback8192C(PRT_TIMER pTimer ); */
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void PHY_SwChnl8188E(PADAPTER pAdapter,
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u8 channel);
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void
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PHY_SetSwChnlBWMode8188E(
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PADAPTER Adapter,
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u8 channel,
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enum channel_width Bandwidth,
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u8 Offset40,
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u8 Offset80
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);
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void
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PHY_SetRFEReg_8188E(
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PADAPTER Adapter
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);
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/*
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* BB/MAC/RF other monitor API
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* */
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void phy_set_rf_path_switch_8188e(struct dm_struct *phydm, bool bMain);
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extern void
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PHY_SwitchEphyParameter(
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PADAPTER Adapter
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);
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extern void
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PHY_EnableHostClkReq(
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PADAPTER Adapter
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);
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BOOLEAN
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SetAntennaConfig92C(
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PADAPTER Adapter,
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u8 DefaultAnt
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);
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/*--------------------------Exported Function prototype---------------------*/
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/*
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* Initialization related function
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*
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* MAC/BB/RF HAL config */
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/* extern s32 PHY_MACConfig8723(PADAPTER padapter);
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* s32 PHY_BBConfig8723(PADAPTER padapter);
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* s32 PHY_RFConfig8723(PADAPTER padapter); */
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/* ******************************************************************
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* Note: If SIC_ENABLE under PCIE, because of the slow operation
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* you should
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* 2) "#define RTL8723_FPGA_VERIFICATION 1" in Precomp.h.WlanE.Windows
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* 3) "#define RTL8190_Download_Firmware_From_Header 0" in Precomp.h.WlanE.Windows if needed.
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* */
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#if (RTL8188E_SUPPORT == 1) && (RTL8188E_FPGA_TRUE_PHY_VERIFICATION == 1)
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#define SIC_ENABLE 1
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#define SIC_HW_SUPPORT 1
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#else
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#define SIC_ENABLE 0
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#define SIC_HW_SUPPORT 0
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#endif
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/* ****************************************************************** */
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#define SIC_MAX_POLL_CNT 5
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#if (SIC_HW_SUPPORT == 1)
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#define SIC_CMD_READY 0
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#define SIC_CMD_PREWRITE 0x1
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#if (RTL8188E_SUPPORT == 1)
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#define SIC_CMD_WRITE 0x40
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#define SIC_CMD_PREREAD 0x2
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#define SIC_CMD_READ 0x80
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#define SIC_CMD_INIT 0xf0
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#define SIC_INIT_VAL 0xff
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#define SIC_INIT_REG 0x1b7
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#define SIC_CMD_REG 0x1EB /* 1byte */
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#define SIC_ADDR_REG 0x1E8 /* 1b4~1b5, 2 bytes */
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#define SIC_DATA_REG 0x1EC /* 1b0~1b3 */
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#else
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#define SIC_CMD_WRITE 0x11
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#define SIC_CMD_PREREAD 0x2
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#define SIC_CMD_READ 0x12
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#define SIC_CMD_INIT 0x1f
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#define SIC_INIT_VAL 0xff
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#define SIC_INIT_REG 0x1b7
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#define SIC_CMD_REG 0x1b6 /* 1byte */
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#define SIC_ADDR_REG 0x1b4 /* 1b4~1b5, 2 bytes */
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#define SIC_DATA_REG 0x1b0 /* 1b0~1b3 */
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#endif
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#else
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#define SIC_CMD_READY 0
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#define SIC_CMD_WRITE 1
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#define SIC_CMD_READ 2
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#if (RTL8188E_SUPPORT == 1)
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#define SIC_CMD_REG 0x1EB /* 1byte */
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#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
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#define SIC_DATA_REG 0x1EC /* 1bc~1bf */
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#else
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#define SIC_CMD_REG 0x1b8 /* 1byte */
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#define SIC_ADDR_REG 0x1b9 /* 1b9~1ba, 2 bytes */
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#define SIC_DATA_REG 0x1bc /* 1bc~1bf */
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#endif
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#endif
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#if (SIC_ENABLE == 1)
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void SIC_Init( PADAPTER Adapter);
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#endif
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#endif /* __INC_HAL8192CPHYCFG_H */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,170 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __HAL8188EPWRSEQ_H__
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#define __HAL8188EPWRSEQ_H__
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#include "HalPwrSeqCmd.h"
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/*
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Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
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There are 6 HW Power States:
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0: POFF--Power Off
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1: PDN--Power Down
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2: CARDEMU--Card Emulation
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3: ACT--Active Mode
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4: LPS--Low Power State
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5: SUS--Suspend
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The transision from different states are defined below
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TRANS_CARDEMU_TO_ACT
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TRANS_ACT_TO_CARDEMU
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TRANS_CARDEMU_TO_SUS
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TRANS_SUS_TO_CARDEMU
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TRANS_CARDEMU_TO_PDN
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TRANS_ACT_TO_LPS
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TRANS_LPS_TO_ACT
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TRANS_END
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PWR SEQ Version: rtl8188E_PwrSeq_V09.h
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*/
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#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
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#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
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#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
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#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
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#define RTL8188E_TRANS_END_STEPS 1
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#define RTL8188E_TRANS_CARDEMU_TO_ACT \
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/* format */ \
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \
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#define RTL8188E_TRANS_ACT_TO_CARDEMU \
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/* format */ \
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
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{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
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#define RTL8188E_TRANS_CARDEMU_TO_SUS \
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/* format */ \
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
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{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
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#define RTL8188E_TRANS_SUS_TO_CARDEMU \
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/* format */ \
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
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/* format */ \
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
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{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
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{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
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#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
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/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
|
||||
#define RTL8188E_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8188E_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8188E_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
|
||||
|
||||
#endif /* __HAL8188EPWRSEQ_H__ */
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8188FPHYCFG_H__
|
||||
#define __INC_HAL8188FPHYCFG_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters End-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure End----------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_QueryBBReg_8188F(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBBReg_8188F(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_QueryRFReg_8188F(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFReg_8188F(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8188F(PADAPTER Adapter);
|
||||
|
||||
int PHY_RFConfig8188F(PADAPTER Adapter);
|
||||
|
||||
s32 PHY_MACConfig8188F(PADAPTER padapter);
|
||||
|
||||
int
|
||||
PHY_ConfigRFWithParaFile_8188F(
|
||||
PADAPTER Adapter,
|
||||
u8 *pFileName,
|
||||
enum rf_path eRFPath
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8188F(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8188F(
|
||||
PADAPTER Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void rtl8188f_set_txpwr_done(_adapter *adapter);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8188F(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
void phy_set_rf_path_switch_8188f(
|
||||
struct dm_struct *phydm,
|
||||
bool bMain
|
||||
);
|
||||
|
||||
void BBTurnOnBlock_8188F(_adapter *adapter);
|
||||
|
||||
/*--------------------------Exported Function prototype End---------------------*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,212 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8188F
|
||||
#define REALTEK_POWER_SEQUENCE_8188F
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20130815-JackieLau-RTL8188F_Power_Architecture v08.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS 13
|
||||
#define RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS 14
|
||||
#define RTL8188F_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8188F_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8188F_TRANS_ACT_TO_LPS_STEPS 11
|
||||
#define RTL8188F_TRANS_LPS_TO_ACT_STEPS 13
|
||||
#define RTL8188F_TRANS_ACT_TO_SWLPS_STEPS 21
|
||||
#define RTL8188F_TRANS_SWLPS_TO_ACT_STEPS 14
|
||||
#define RTL8188F_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8188F_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3), 0},/* 0x4[11]=1'b0 disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* 0x4[8]=1 polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35}, /*0x27<=35 to reduce RF noise*/
|
||||
|
||||
#define RTL8188F_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
|
||||
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34}, /*0x27 <= 34, xtal_qsel = 0 to xtal bring up*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
|
||||
#define RTL8188F_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
|
||||
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
|
||||
|
||||
#define RTL8188F_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
|
||||
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
|
||||
|
||||
#define RTL8188F_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07 = 0x00 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \
|
||||
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
|
||||
|
||||
#define RTL8188F_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
|
||||
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/
|
||||
|
||||
|
||||
#define RTL8188F_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8188F_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8188F_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
|
||||
|
||||
|
||||
#define RTL8188F_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35},/*xtal_qsel = 1 for low noise*/ \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x002B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1c, 0x1c}, /*. 0x2b[4:2] = 3b'111 to enable BB, AFE clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
|
||||
#define RTL8188F_TRANS_ACT_TO_SWLPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
{0x002b, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1C, 0x00},/*0x2b[4:2]<=0 to gated BB, AFE clock*/ \
|
||||
{0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34},/*xtal_qsel = 0 for bring up*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x00},/* sdio LPS option*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x83},/* usb LPS option, open bandgap, xtal*/ \
|
||||
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /* 0xC4[5]<=0, digital LDO no standby mode*/ \
|
||||
{0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /* 0xC4[7]<=1, on domain voltage adjust*/ \
|
||||
{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe0}, /* low power LPS enable for sdio*/ \
|
||||
{0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe4}, /* low power LPS enable for usb*/ \
|
||||
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* enable WL_LPS_EN*/
|
||||
|
||||
|
||||
#define RTL8188F_TRANS_SWLPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\
|
||||
{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8188F_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS];
|
||||
#endif
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8192EPHYCFG_H__
|
||||
#define __INC_HAL8192EPHYCFG_H__
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/* BB/RF related */
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
/*
|
||||
* BB and RF register read/write
|
||||
* */
|
||||
u32 PHY_QueryBBReg8192E(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
void PHY_SetBBReg8192E(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
u32 PHY_QueryRFReg8192E(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
void PHY_SetRFReg8192E(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
|
||||
/*
|
||||
* Initialization related function
|
||||
*
|
||||
* MAC/BB/RF HAL config */
|
||||
int PHY_MACConfig8192E(PADAPTER Adapter);
|
||||
int PHY_BBConfig8192E(PADAPTER Adapter);
|
||||
int PHY_RFConfig8192E(PADAPTER Adapter);
|
||||
|
||||
/* RF config */
|
||||
|
||||
|
||||
/*
|
||||
* BB TX Power R/W
|
||||
* */
|
||||
void PHY_SetTxPowerLevel8192E(PADAPTER Adapter, u8 channel);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8192E(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
/*
|
||||
* channel switch related funciton
|
||||
* */
|
||||
void
|
||||
PHY_SetSwChnlBWMode8192E(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFEReg_8192E(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
void
|
||||
phy_SpurCalibration_8192E(
|
||||
PADAPTER Adapter,
|
||||
enum spur_cal_method method
|
||||
);
|
||||
void PHY_SpurCalibration_8192E( PADAPTER Adapter);
|
||||
|
||||
#ifdef CONFIG_SPUR_CAL_NBI
|
||||
void
|
||||
phy_SpurCalibration_8192E_NBI(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
#endif
|
||||
/*
|
||||
* BB/MAC/RF other monitor API
|
||||
* */
|
||||
|
||||
void
|
||||
phy_set_rf_path_switch_8192e(
|
||||
struct dm_struct *phydm,
|
||||
bool bMain
|
||||
);
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
#endif /* __INC_HAL8192CPHYCFG_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,169 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8192E
|
||||
#define REALTEK_POWER_SEQUENCE_8192E
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
/*
|
||||
Check document WM-20110607-Paul-RTL8192E_Power_Architecture-R02.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS 18
|
||||
#define RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS 18
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS 18
|
||||
#define RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS 18
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS 18
|
||||
#define RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS 18
|
||||
#define RTL8192E_TRANS_ACT_TO_LPS_STEPS 23
|
||||
#define RTL8192E_TRANS_LPS_TO_ACT_STEPS 23
|
||||
#define RTL8192E_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
|
||||
|
||||
#define RTL8192E_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8192E_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*Unlock small LDO Register*/ \
|
||||
{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*Disable small LDO*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8192E_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0011, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*Enable small LDO*/ \
|
||||
{0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*Lock small LDO Register*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
|
||||
|
||||
#define RTL8192E_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8192E_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8192E_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8192E_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM, For Repeatly In and out, Taggle bit should be changed*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/\
|
||||
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*Clear ISR*/
|
||||
|
||||
#define RTL8192E_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8192E_power_on_flow[RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_radio_off_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_card_disable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_card_enable_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_suspend_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_resume_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_hwpdn_flow[RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_enter_lps_flow[RTL8192E_TRANS_ACT_TO_LPS_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192E_leave_lps_flow[RTL8192E_TRANS_LPS_TO_ACT_STEPS + RTL8192E_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8192FPHYCFG_H__
|
||||
#define __INC_HAL8192FPHYCFG_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters End-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure End----------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_QueryBBReg_8192F(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBBReg_8192F(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_QueryRFReg_8192F(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFReg_8192F(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8192F(PADAPTER Adapter );
|
||||
|
||||
int PHY_RFConfig8192F(PADAPTER Adapter);
|
||||
|
||||
s32 PHY_MACConfig8192F(PADAPTER padapter);
|
||||
|
||||
int
|
||||
PHY_ConfigRFWithParaFile_8192F(
|
||||
PADAPTER Adapter,
|
||||
u8 *pFileName,
|
||||
enum rf_path eRFPath
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8192F(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8192F(
|
||||
PADAPTER Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8192F(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
void phy_set_rf_path_switch_8192f(
|
||||
PADAPTER pAdapter,
|
||||
bool bMain
|
||||
);
|
||||
/*--------------------------Exported Function prototype End---------------------*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,220 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8192F
|
||||
#define REALTEK_POWER_SEQUENCE_8192F
|
||||
#define POWER_SEQUENCE_8192F_VER 04
|
||||
/* #include "PwrSeqCmd.h" */
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transition from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS 38
|
||||
#define RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS 8
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS 7
|
||||
#define RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS 5
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS 8
|
||||
#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS 8
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS 4
|
||||
#define RTL8192F_TRANS_PDN_TO_CARDEMU_STEPS 1
|
||||
#define RTL8192F_TRANS_ACT_TO_LPS_STEPS 13
|
||||
#define RTL8192F_TRANS_LPS_TO_ACT_STEPS 11
|
||||
#define RTL8192F_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, (BIT1|BIT0), 0}, \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* SWR OCP enable 0x10[18]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x007f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x7c[31]=1,LDO has max output capability*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 data mode*/\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
|
||||
{0x0068, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/*RF HW ON/OFF Enable*/\
|
||||
{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*Register Lock Disable*/\
|
||||
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
|
||||
{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
|
||||
{0x007B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
|
||||
{0x0097, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*AFE_Ctrl*/\
|
||||
{0x00DC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xCC},/*AFE_Ctrl*/\
|
||||
{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x18, 0x00},/*AFE_Ctrl 0x24[4:3]=00 for xtal gmn*/\
|
||||
{0x1050, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[7:0] Pull down software register*/\
|
||||
{0x1051, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[15:8] Pull down software register*/\
|
||||
{0x1052, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[23:16] Pull down software register*/\
|
||||
{0x1053, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_A[31:24] Pull down software register*/\
|
||||
{0x105B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*GPIO_B[7:0] Pull down software register*/\
|
||||
{0x001C, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*Register Lock Enable*/\
|
||||
{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT7|BIT6), 0x3},/*set HCI Power sequence state delay time:0*/
|
||||
|
||||
|
||||
#define RTL8192F_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x2[0]=0 Reset BB,RF enter Power Down mode*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x10[18] = 0 to disable ocp*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
|
||||
|
||||
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 USB|SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8192F_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8192F_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x10[18] = 1 to enable ocp*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8192F_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8192F_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8192F_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8192F_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8192F_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8192F_power_on_flow[RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_radio_off_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_card_disable_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_CARDDIS_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_card_enable_flow[RTL8192F_TRANS_CARDDIS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_suspend_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_resume_flow[RTL8192F_TRANS_SUS_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_hwpdn_flow[RTL8192F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8192F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_enter_lps_flow[RTL8192F_TRANS_ACT_TO_LPS_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8192F_leave_lps_flow[RTL8192F_TRANS_LPS_TO_ACT_STEPS+RTL8192F_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8703BPHYCFG_H__
|
||||
#define __INC_HAL8703BPHYCFG_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters End-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure End----------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_QueryBBReg_8703B(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBBReg_8703B(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_QueryRFReg_8703B(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFReg_8703B(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8703B(PADAPTER Adapter);
|
||||
|
||||
int PHY_RFConfig8703B(PADAPTER Adapter);
|
||||
|
||||
s32 PHY_MACConfig8703B(PADAPTER padapter);
|
||||
|
||||
int
|
||||
PHY_ConfigRFWithParaFile_8703B(
|
||||
PADAPTER Adapter,
|
||||
u8 *pFileName,
|
||||
enum rf_path eRFPath
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8703B(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8703B(
|
||||
PADAPTER Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8703B(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
void phy_set_rf_path_switch_8703b(
|
||||
struct dm_struct *phydm,
|
||||
bool bMain
|
||||
);
|
||||
|
||||
/*--------------------------Exported Function prototype End---------------------*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,198 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8703B
|
||||
#define REALTEK_POWER_SEQUENCE_8703B
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20140402-JackieLau-RTL8703B_Power_Architecture v09.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS 23
|
||||
#define RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8703B_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8703B_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8703B_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8703B_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8703B_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8703B_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
|
||||
{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , BIT3},/* enabled usb resume */ \
|
||||
{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 , 0},/* disable usb resume */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
|
||||
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
|
||||
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
|
||||
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
|
||||
|
||||
|
||||
#define RTL8703B_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
|
||||
|
||||
|
||||
#define RTL8703B_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8703B_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8703B_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8703B_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8703B_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8703B_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8703B_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8703B_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8703B_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8703B_power_on_flow[RTL8703B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_radio_off_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_card_disable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_card_enable_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_suspend_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_resume_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_hwpdn_flow[RTL8703B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8703B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_enter_lps_flow[RTL8703B_TRANS_ACT_TO_LPS_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8703B_leave_lps_flow[RTL8703B_TRANS_LPS_TO_ACT_STEPS + RTL8703B_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8710BPHYCFG_H__
|
||||
#define __INC_HAL8710BPHYCFG_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters End-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure End----------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_QueryBBReg_8710B(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBBReg_8710B(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_QueryRFReg_8710B(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFReg_8710B(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8710B(PADAPTER Adapter);
|
||||
|
||||
int PHY_RFConfig8710B(PADAPTER Adapter);
|
||||
|
||||
s32 PHY_MACConfig8710B(PADAPTER padapter);
|
||||
|
||||
int
|
||||
PHY_ConfigRFWithParaFile_8710B(
|
||||
PADAPTER Adapter,
|
||||
u8 *pFileName,
|
||||
enum rf_path eRFPath
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8710B(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8710B(
|
||||
PADAPTER Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8710B(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
/*--------------------------Exported Function prototype End---------------------*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,167 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8710B
|
||||
#define REALTEK_POWER_SEQUENCE_8710B
|
||||
|
||||
/* #include "PwrSeqCmd.h" */
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transition from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS 5
|
||||
#define RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS 4
|
||||
#define RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS 7
|
||||
#define RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8710B_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8710B_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8710B_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8710B_TRANS_ACT_TO_SWLPS_STEPS 22
|
||||
#define RTL8710B_TRANS_SWLPS_TO_ACT_STEPS 15
|
||||
#define RTL8710B_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8710B_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x005D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*AFE power mode selection:1: LDO mode ,0: Power-cut mode*/\
|
||||
{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
|
||||
{0x0056, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x0E},\
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/
|
||||
|
||||
|
||||
#define RTL8710B_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \
|
||||
|
||||
|
||||
#define RTL8710B_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8710B_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
|
||||
#define RTL8710B_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
|
||||
#define RTL8710B_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
|
||||
|
||||
#define RTL8710B_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8710B_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8710B_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
|
||||
|
||||
|
||||
#define RTL8710B_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8710B_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8710B_power_on_flow[RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_radio_off_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_card_disable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_card_enable_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_suspend_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_SUS_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_resume_flow[RTL8710B_TRANS_SUS_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_hwpdn_flow[RTL8710B_TRANS_ACT_TO_CARDEMU_STEPS+RTL8710B_TRANS_CARDEMU_TO_PDN_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_enter_lps_flow[RTL8710B_TRANS_ACT_TO_LPS_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8710B_leave_lps_flow[RTL8710B_TRANS_LPS_TO_ACT_STEPS+RTL8710B_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8723BPHYCFG_H__
|
||||
#define __INC_HAL8723BPHYCFG_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters End-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure End----------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_QueryBBReg_8723B(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBBReg_8723B(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_QueryRFReg_8723B(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFReg_8723B(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8723B(PADAPTER Adapter);
|
||||
|
||||
int PHY_RFConfig8723B(PADAPTER Adapter);
|
||||
|
||||
s32 PHY_MACConfig8723B(PADAPTER padapter);
|
||||
|
||||
int
|
||||
PHY_ConfigRFWithParaFile_8723B(
|
||||
PADAPTER Adapter,
|
||||
u8 *pFileName,
|
||||
enum rf_path eRFPath
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8723B(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8723B(
|
||||
PADAPTER Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8723B(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
void phy_set_rf_path_switch_8723b(
|
||||
struct dm_struct *phydm,
|
||||
bool bMain
|
||||
);
|
||||
|
||||
/*--------------------------Exported Function prototype End---------------------*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,246 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8723B
|
||||
#define REALTEK_POWER_SEQUENCE_8723B
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20130815-JackieLau-RTL8723B_Power_Architecture v08.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 26
|
||||
#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8723B_TRANS_ACT_TO_SWLPS_STEPS 22
|
||||
#define RTL8723B_TRANS_SWLPS_TO_ACT_STEPS 15
|
||||
#define RTL8723B_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
|
||||
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
|
||||
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
|
||||
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/\
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/\
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723B_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8723B_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8723B_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_ACT_TO_SWLPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \
|
||||
{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \
|
||||
{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \
|
||||
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
|
||||
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
|
||||
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \
|
||||
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
|
||||
|
||||
|
||||
#define RTL8723B_TRANS_SWLPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\
|
||||
{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
|
||||
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8723B_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8723B_power_on_flow[RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_radio_off_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_card_disable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_card_enable_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_suspend_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_resume_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_hwpdn_flow[RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_enter_lps_flow[RTL8723B_TRANS_ACT_TO_LPS_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_leave_lps_flow[RTL8723B_TRANS_LPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_enter_swlps_flow[RTL8723B_TRANS_ACT_TO_SWLPS_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723B_leave_swlps_flow[RTL8723B_TRANS_SWLPS_TO_ACT_STEPS + RTL8723B_TRANS_END_STEPS];
|
||||
#endif
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8723DPHYCFG_H__
|
||||
#define __INC_HAL8723DPHYCFG_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters End-------------------------------*/
|
||||
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
/*------------------------------Define structure End----------------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_QueryBBReg_8723D(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetBBReg_8723D(
|
||||
PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_QueryRFReg_8723D(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFReg_8723D(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
/* MAC/BB/RF HAL config */
|
||||
int PHY_BBConfig8723D(PADAPTER Adapter);
|
||||
|
||||
int PHY_RFConfig8723D(PADAPTER Adapter);
|
||||
|
||||
s32 PHY_MACConfig8723D(PADAPTER padapter);
|
||||
|
||||
int
|
||||
PHY_ConfigRFWithParaFile_8723D(
|
||||
PADAPTER Adapter,
|
||||
u8 *pFileName,
|
||||
enum rf_path eRFPath
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8723D(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8723D(
|
||||
PADAPTER Adapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8723D(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
void phy_set_rf_path_switch_8723d(
|
||||
struct dm_struct *phydm,
|
||||
bool bMain
|
||||
);
|
||||
/*--------------------------Exported Function prototype End---------------------*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,206 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8723D
|
||||
#define REALTEK_POWER_SEQUENCE_8723D
|
||||
|
||||
/* #include "PwrSeqCmd.h" */
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20110607-Paul-RTL8192e_Power_Architecture-R02.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transition from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS 27
|
||||
#define RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS 8
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS 7
|
||||
#define RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS 5
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS 8
|
||||
#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS 7
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS 4
|
||||
#define RTL8723D_TRANS_PDN_TO_CARDEMU_STEPS 1
|
||||
#define RTL8723D_TRANS_ACT_TO_LPS_STEPS 13
|
||||
#define RTL8723D_TRANS_LPS_TO_ACT_STEPS 11
|
||||
#define RTL8723D_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)},/* Disable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0},/* Enable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0},/**/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/* Enable WL control XTAL setting*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable falling edge triggering interrupt*/\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable GPIO9 interrupt mode*/\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable GPIO9 input mode*/\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/*Enable HSISR GPIO[C:0] interrupt*/\
|
||||
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)},/*Enable HSISR GPIO9 interrupt*/\
|
||||
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)},/*For GPIO9 internal pull high setting by test chip*/\
|
||||
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},/*For GPIO9 internal pull high setting*/\
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S1*/\
|
||||
{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*reset RF path S0*/\
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enable RF path S1*/\
|
||||
{0x0077, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/*enalbe RF path S0*/\
|
||||
|
||||
|
||||
#define RTL8723D_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, */ /*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x2[0]=0 Reset BB, RF enter Power Down mode*/ \
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Enable rising edge triggering interrupt*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0},/* Enable BT control XTAL setting*/\
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/\
|
||||
|
||||
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723D_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723D_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8723D_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8723D_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8723D_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8723D_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8723D_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, / comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8723D_power_on_flow[RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_radio_off_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_card_disable_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_CARDDIS_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_card_enable_flow[RTL8723D_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_suspend_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_resume_flow[RTL8723D_TRANS_SUS_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_hwpdn_flow[RTL8723D_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723D_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_enter_lps_flow[RTL8723D_TRANS_ACT_TO_LPS_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723D_leave_lps_flow[RTL8723D_TRANS_LPS_TO_ACT_STEPS + RTL8723D_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL8723PWRSEQ_H__
|
||||
#define __HAL8723PWRSEQ_H__
|
||||
/*
|
||||
Check document WM-20110607-Paul-RTL8723A_Power_Architecture-R02.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS 15
|
||||
#define RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8723A_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8723A_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8723A_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 1},/*0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */\
|
||||
|
||||
#define RTL8723A_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723A_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8723A_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8723A_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8723A_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8723A_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8723A_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS + RTL8723A_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8812PHYCFG_H__
|
||||
#define __INC_HAL8812PHYCFG_H__
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/* BB/RF related */
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
/*
|
||||
* BB and RF register read/write
|
||||
* */
|
||||
u32 PHY_QueryBBReg8812(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
void PHY_SetBBReg8812(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
u32 PHY_QueryRFReg8812(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
void PHY_SetRFReg8812(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
|
||||
/*
|
||||
* Initialization related function
|
||||
*
|
||||
* MAC/BB/RF HAL config */
|
||||
int PHY_MACConfig8812(PADAPTER Adapter);
|
||||
int PHY_BBConfig8812(PADAPTER Adapter);
|
||||
void PHY_BB8812_Config_1T(PADAPTER Adapter);
|
||||
int PHY_RFConfig8812(PADAPTER Adapter);
|
||||
|
||||
/* RF config */
|
||||
|
||||
s32
|
||||
PHY_SwitchWirelessBand8812(
|
||||
PADAPTER Adapter,
|
||||
u8 Band
|
||||
);
|
||||
|
||||
/*
|
||||
* BB TX Power R/W
|
||||
* */
|
||||
void PHY_SetTxPowerLevel8812(PADAPTER Adapter, u8 Channel);
|
||||
|
||||
bool phy_get_txpwr_target_skip_by_rate_8812a(_adapter *adapter, enum MGN_RATE rate);
|
||||
|
||||
u32 phy_get_tx_bb_swing_8812a(
|
||||
PADAPTER Adapter,
|
||||
BAND_TYPE Band,
|
||||
enum rf_path RFPath
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8812A(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
/*
|
||||
* channel switch related funciton
|
||||
* */
|
||||
void
|
||||
PHY_SetSwChnlBWMode8812(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
/*
|
||||
* BB/MAC/RF other monitor API
|
||||
* */
|
||||
|
||||
void
|
||||
phy_set_rf_path_switch_8812a(
|
||||
struct dm_struct *phydm,
|
||||
bool bMain
|
||||
);
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
#endif /* __INC_HAL8192CPHYCFG_H */
|
||||
|
|
@ -0,0 +1,735 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8812PHYREG_H__
|
||||
#define __INC_HAL8812PHYREG_H__
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
/*
|
||||
* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
|
||||
* 3. RF register 0x00-2E
|
||||
* 4. Bit Mask for BB/RF register
|
||||
* 5. Other defintion for BB/RF R/W
|
||||
* */
|
||||
|
||||
|
||||
/* BB Register Definition */
|
||||
|
||||
#define rCCAonSec_Jaguar 0x838
|
||||
#define rPwed_TH_Jaguar 0x830
|
||||
|
||||
/* BW and sideband setting */
|
||||
#define rBWIndication_Jaguar 0x834
|
||||
#define rL1PeakTH_Jaguar 0x848
|
||||
#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
|
||||
#define rRFMOD_Jaguar 0x8ac /* RF mode */
|
||||
#define rADC_Buf_Clk_Jaguar 0x8c4
|
||||
#define rRFECTRL_Jaguar 0x900
|
||||
#define bRFMOD_Jaguar 0xc3
|
||||
#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
|
||||
#define bCCK_System_Jaguar 0x10
|
||||
|
||||
/* Block & Path enable */
|
||||
#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
|
||||
#define bOFDMEN_Jaguar 0x20000000
|
||||
#define bCCKEN_Jaguar 0x10000000
|
||||
#define rRxPath_Jaguar 0x808 /* Rx antenna */
|
||||
#define bRxPath_Jaguar 0xff
|
||||
#define rTxPath_Jaguar 0x80c /* Tx antenna */
|
||||
#define bTxPath_Jaguar 0x0fffffff
|
||||
#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
|
||||
#define bCCK_RX_Jaguar 0x0c000000
|
||||
#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
|
||||
|
||||
/* RF read/write-related */
|
||||
#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
|
||||
#define bHSSIRead_addr_Jaguar 0xff
|
||||
#define bHSSIRead_trigger_Jaguar 0x100
|
||||
#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
|
||||
#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
|
||||
#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
|
||||
#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
|
||||
#define rRead_data_Jaguar 0xfffff
|
||||
#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
|
||||
#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
|
||||
#define bLSSIWrite_data_Jaguar 0x000fffff
|
||||
#define bLSSIWrite_addr_Jaguar 0x0ff00000
|
||||
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily */
|
||||
#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
|
||||
#define rFPGA0_XB_RFInterfaceOE 0x864
|
||||
|
||||
#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
|
||||
#define rFPGA0_XCD_RFInterfaceSW 0x874
|
||||
|
||||
/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
|
||||
* #define rFPGA0_XCD_RFParameter 0x87c */
|
||||
|
||||
/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
|
||||
* #define rFPGA0_AnalogParameter2 0x884
|
||||
* #define rFPGA0_AnalogParameter3 0x888
|
||||
* #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
|
||||
* #define rFPGA0_AnalogParameter4 0x88c */
|
||||
|
||||
|
||||
/* CCK TX scaling */
|
||||
#define rCCK_TxFilter1_Jaguar 0xa20
|
||||
#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter1_C1_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter2_Jaguar 0xa24
|
||||
#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
|
||||
#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter2_C5_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter3_Jaguar 0xa28
|
||||
#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily
|
||||
* #define rPdp_AntA 0xb00
|
||||
* #define rPdp_AntA_4 0xb04
|
||||
* #define rConfig_Pmpd_AntA 0xb28
|
||||
* #define rConfig_AntA 0xb68
|
||||
* #define rConfig_AntB 0xb6c
|
||||
* #define rPdp_AntB 0xb70
|
||||
* #define rPdp_AntB_4 0xb74
|
||||
* #define rConfig_Pmpd_AntB 0xb98
|
||||
* #define rAPK 0xbd8 */
|
||||
|
||||
/* RXIQC */
|
||||
#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
|
||||
#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
|
||||
#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
|
||||
#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
|
||||
|
||||
|
||||
/* DIG-related */
|
||||
#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
|
||||
#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
|
||||
#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
|
||||
#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
|
||||
#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
|
||||
#define b_FalseAlarm_Jaguar 0xffff
|
||||
#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
|
||||
#define bCCK_CCA_Jaguar 0x00ff0000
|
||||
|
||||
/* Tx Power Ttraining-related */
|
||||
#define rA_TxPwrTraing_Jaguar 0xc54
|
||||
#define rB_TxPwrTraing_Jaguar 0xe54
|
||||
|
||||
/* Report-related */
|
||||
#define rOFDM_ShortCFOAB_Jaguar 0xf60
|
||||
#define rOFDM_LongCFOAB_Jaguar 0xf64
|
||||
#define rOFDM_EndCFOAB_Jaguar 0xf70
|
||||
#define rOFDM_AGCReport_Jaguar 0xf84
|
||||
#define rOFDM_RxSNR_Jaguar 0xf88
|
||||
#define rOFDM_RxEVMCSI_Jaguar 0xf8c
|
||||
#define rOFDM_SIGReport_Jaguar 0xf90
|
||||
|
||||
/* Misc functions */
|
||||
#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
|
||||
#define bEDCCA_Jaguar 0xffff
|
||||
#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
|
||||
#define bAGC_table_Jaguar 0x3
|
||||
#define b_sel5g_Jaguar 0x1000 /* sel5g */
|
||||
#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
|
||||
#define rFc_area_Jaguar 0x860 /* fc_area */
|
||||
#define bFc_area_Jaguar 0x1ffe000
|
||||
#define rSingleTone_ContTx_Jaguar 0x914
|
||||
|
||||
/* RFE */
|
||||
#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
|
||||
#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
|
||||
#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
|
||||
#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
|
||||
#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
|
||||
#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
|
||||
#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
|
||||
#define bMask_RFEInv_Jaguar 0x3ff00000
|
||||
#define bMask_AntselPathFollow_Jaguar 0x00030000
|
||||
|
||||
/* TX AGC */
|
||||
#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
|
||||
#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
|
||||
#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
|
||||
#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
|
||||
#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
|
||||
#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
|
||||
#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
|
||||
#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
|
||||
#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
|
||||
#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
|
||||
#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
|
||||
#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
|
||||
#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
|
||||
#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
|
||||
#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
|
||||
#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
|
||||
#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
|
||||
#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
|
||||
#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
|
||||
#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
|
||||
#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
|
||||
#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
|
||||
#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
|
||||
#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
|
||||
#define bTxAGC_byte0_Jaguar 0xff
|
||||
#define bTxAGC_byte1_Jaguar 0xff00
|
||||
#define bTxAGC_byte2_Jaguar 0xff0000
|
||||
#define bTxAGC_byte3_Jaguar 0xff000000
|
||||
|
||||
/* IQK YN: temporaily mask this part
|
||||
* #define rFPGA0_IQK 0xe28
|
||||
* #define rTx_IQK_Tone_A 0xe30
|
||||
* #define rRx_IQK_Tone_A 0xe34
|
||||
* #define rTx_IQK_PI_A 0xe38
|
||||
* #define rRx_IQK_PI_A 0xe3c */
|
||||
|
||||
/* #define rTx_IQK 0xe40 */
|
||||
/* #define rRx_IQK 0xe44 */
|
||||
/* #define rIQK_AGC_Pts 0xe48 */
|
||||
/* #define rIQK_AGC_Rsp 0xe4c */
|
||||
/* #define rTx_IQK_Tone_B 0xe50 */
|
||||
/* #define rRx_IQK_Tone_B 0xe54 */
|
||||
/* #define rTx_IQK_PI_B 0xe58 */
|
||||
/* #define rRx_IQK_PI_B 0xe5c */
|
||||
/* #define rIQK_AGC_Cont 0xe60 */
|
||||
|
||||
|
||||
/* AFE-related */
|
||||
#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
|
||||
#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
|
||||
#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
|
||||
#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
|
||||
#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
|
||||
#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
|
||||
#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
|
||||
#define rA_Rx2Rx_BT_Jaguar 0xc7c
|
||||
#define rA_sleep_nav_Jaguar 0xc80
|
||||
#define rA_pmpd_Jaguar 0xc84
|
||||
#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
|
||||
#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
|
||||
#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
|
||||
#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
|
||||
#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
|
||||
#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
|
||||
#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
|
||||
#define rB_Rx2Rx_BT_Jaguar 0xe7c
|
||||
#define rB_sleep_nav_Jaguar 0xe80
|
||||
#define rB_pmpd_Jaguar 0xe84
|
||||
|
||||
|
||||
/* YN: mask these registers temporaily
|
||||
* #define rTx_Power_Before_IQK_A 0xe94
|
||||
* #define rTx_Power_After_IQK_A 0xe9c */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_A 0xea0 */
|
||||
/* #define rRx_Power_Before_IQK_A_2 0xea4 */
|
||||
/* #define rRx_Power_After_IQK_A 0xea8 */
|
||||
/* #define rRx_Power_After_IQK_A_2 0xeac */
|
||||
|
||||
/* #define rTx_Power_Before_IQK_B 0xeb4 */
|
||||
/* #define rTx_Power_After_IQK_B 0xebc */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_B 0xec0 */
|
||||
/* #define rRx_Power_Before_IQK_B_2 0xec4 */
|
||||
/* #define rRx_Power_After_IQK_B 0xec8 */
|
||||
/* #define rRx_Power_After_IQK_B_2 0xecc */
|
||||
|
||||
|
||||
/* RSSI Dump */
|
||||
#define rA_RSSIDump_Jaguar 0xBF0
|
||||
#define rB_RSSIDump_Jaguar 0xBF1
|
||||
#define rS1_RXevmDump_Jaguar 0xBF4
|
||||
#define rS2_RXevmDump_Jaguar 0xBF5
|
||||
#define rA_RXsnrDump_Jaguar 0xBF6
|
||||
#define rB_RXsnrDump_Jaguar 0xBF7
|
||||
#define rA_CfoShortDump_Jaguar 0xBF8
|
||||
#define rB_CfoShortDump_Jaguar 0xBFA
|
||||
#define rA_CfoLongDump_Jaguar 0xBEC
|
||||
#define rB_CfoLongDump_Jaguar 0xBEE
|
||||
|
||||
|
||||
/* RF Register
|
||||
* */
|
||||
#define RF_AC_Jaguar 0x00 /* */
|
||||
#define RF_RF_Top_Jaguar 0x07 /* */
|
||||
#define RF_TXLOK_Jaguar 0x08 /* */
|
||||
#define RF_TXAPK_Jaguar 0x0B
|
||||
#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK1_Jaguar 0x1c /* */
|
||||
#define RF_RCK2_Jaguar 0x1d
|
||||
#define RF_RCK3_Jaguar 0x1e
|
||||
#define RF_ModeTableAddr 0x30
|
||||
#define RF_ModeTableData0 0x31
|
||||
#define RF_ModeTableData1 0x32
|
||||
#define RF_TxLCTank_Jaguar 0x54
|
||||
#define RF_APK_Jaguar 0x63
|
||||
#define RF_LCK 0xB4
|
||||
#define RF_WeLut_Jaguar 0xEF
|
||||
|
||||
#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
|
||||
#define bRF_CHNLBW_BW 0xc00
|
||||
|
||||
|
||||
/*
|
||||
* RL6052 Register definition
|
||||
* */
|
||||
#define RF_AC 0x00 /* */
|
||||
#define RF_IPA_A 0x0C /* */
|
||||
#define RF_TXBIAS_A 0x0D
|
||||
#define RF_BS_PA_APSET_G9_G11 0x0E
|
||||
#define RF_MODE1 0x10 /* */
|
||||
#define RF_MODE2 0x11 /* */
|
||||
#define RF_CHNLBW 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK_OS 0x30 /* RF TX PA control */
|
||||
#define RF_TXPA_G1 0x31 /* RF TX PA control */
|
||||
#define RF_TXPA_G2 0x32 /* RF TX PA control */
|
||||
#define RF_TXPA_G3 0x33 /* RF TX PA control */
|
||||
#define RF_0x52 0x52
|
||||
#define RF_WE_LUT 0xEF
|
||||
|
||||
#define RF_TX_GAIN_OFFSET_8812A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
|
||||
#define RF_TX_GAIN_OFFSET_8821A(_val) ((abs((_val)) << 1) | (((_val) > 0) ? BIT0 : 0))
|
||||
|
||||
/*
|
||||
* Bit Mask
|
||||
*
|
||||
* 1. Page1(0x100) */
|
||||
#define bBBResetB 0x100 /* Useless now? */
|
||||
#define bGlobalResetB 0x200
|
||||
#define bOFDMTxStart 0x4
|
||||
#define bCCKTxStart 0x8
|
||||
#define bCRC32Debug 0x100
|
||||
#define bPMACLoopback 0x10
|
||||
#define bTxLSIG 0xffffff
|
||||
#define bOFDMTxRate 0xf
|
||||
#define bOFDMTxReserved 0x10
|
||||
#define bOFDMTxLength 0x1ffe0
|
||||
#define bOFDMTxParity 0x20000
|
||||
#define bTxHTSIG1 0xffffff
|
||||
#define bTxHTMCSRate 0x7f
|
||||
#define bTxHTBW 0x80
|
||||
#define bTxHTLength 0xffff00
|
||||
#define bTxHTSIG2 0xffffff
|
||||
#define bTxHTSmoothing 0x1
|
||||
#define bTxHTSounding 0x2
|
||||
#define bTxHTReserved 0x4
|
||||
#define bTxHTAggreation 0x8
|
||||
#define bTxHTSTBC 0x30
|
||||
#define bTxHTAdvanceCoding 0x40
|
||||
#define bTxHTShortGI 0x80
|
||||
#define bTxHTNumberHT_LTF 0x300
|
||||
#define bTxHTCRC8 0x3fc00
|
||||
#define bCounterReset 0x10000
|
||||
#define bNumOfOFDMTx 0xffff
|
||||
#define bNumOfCCKTx 0xffff0000
|
||||
#define bTxIdleInterval 0xffff
|
||||
#define bOFDMService 0xffff0000
|
||||
#define bTxMACHeader 0xffffffff
|
||||
#define bTxDataInit 0xff
|
||||
#define bTxHTMode 0x100
|
||||
#define bTxDataType 0x30000
|
||||
#define bTxRandomSeed 0xffffffff
|
||||
#define bCCKTxPreamble 0x1
|
||||
#define bCCKTxSFD 0xffff0000
|
||||
#define bCCKTxSIG 0xff
|
||||
#define bCCKTxService 0xff00
|
||||
#define bCCKLengthExt 0x8000
|
||||
#define bCCKTxLength 0xffff0000
|
||||
#define bCCKTxCRC16 0xffff
|
||||
#define bCCKTxStatus 0x1
|
||||
#define bOFDMTxStatus 0x2
|
||||
|
||||
|
||||
/*
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 1. Page1(0x100)
|
||||
* */
|
||||
#define rPMAC_Reset 0x100
|
||||
#define rPMAC_TxStart 0x104
|
||||
#define rPMAC_TxLegacySIG 0x108
|
||||
#define rPMAC_TxHTSIG1 0x10c
|
||||
#define rPMAC_TxHTSIG2 0x110
|
||||
#define rPMAC_PHYDebug 0x114
|
||||
#define rPMAC_TxPacketNum 0x118
|
||||
#define rPMAC_TxIdle 0x11c
|
||||
#define rPMAC_TxMACHeader0 0x120
|
||||
#define rPMAC_TxMACHeader1 0x124
|
||||
#define rPMAC_TxMACHeader2 0x128
|
||||
#define rPMAC_TxMACHeader3 0x12c
|
||||
#define rPMAC_TxMACHeader4 0x130
|
||||
#define rPMAC_TxMACHeader5 0x134
|
||||
#define rPMAC_TxDataType 0x138
|
||||
#define rPMAC_TxRandomSeed 0x13c
|
||||
#define rPMAC_CCKPLCPPreamble 0x140
|
||||
#define rPMAC_CCKPLCPHeader 0x144
|
||||
#define rPMAC_CCKCRC16 0x148
|
||||
#define rPMAC_OFDMRxCRC32OK 0x170
|
||||
#define rPMAC_OFDMRxCRC32Er 0x174
|
||||
#define rPMAC_OFDMRxParityEr 0x178
|
||||
#define rPMAC_OFDMRxCRC8Er 0x17c
|
||||
#define rPMAC_CCKCRxRC16Er 0x180
|
||||
#define rPMAC_CCKCRxRC32Er 0x184
|
||||
#define rPMAC_CCKCRxRC32OK 0x188
|
||||
#define rPMAC_TxStatus 0x18c
|
||||
|
||||
/*
|
||||
* 3. Page8(0x800)
|
||||
* */
|
||||
#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
|
||||
|
||||
#define rFPGA0_TxInfo 0x804 /* Status report?? */
|
||||
#define rFPGA0_PSDFunction 0x808
|
||||
#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
|
||||
|
||||
#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
|
||||
#define rFPGA0_XA_HSSIParameter2 0x824
|
||||
#define rFPGA0_XB_HSSIParameter1 0x828
|
||||
#define rFPGA0_XB_HSSIParameter2 0x82c
|
||||
|
||||
#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
|
||||
#define rFPGA0_XCD_SwitchControl 0x85c
|
||||
|
||||
#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
|
||||
#define rFPGA0_XCD_RFParameter 0x87c
|
||||
|
||||
#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
|
||||
#define rFPGA0_AnalogParameter2 0x884
|
||||
#define rFPGA0_AnalogParameter3 0x888
|
||||
#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
|
||||
#define rFPGA0_AnalogParameter4 0x88c
|
||||
#define rFPGA0_XB_LSSIReadBack 0x8a4
|
||||
#define rFPGA0_XCD_RFPara 0x8b4
|
||||
|
||||
/*
|
||||
* 4. Page9(0x900)
|
||||
* */
|
||||
#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
|
||||
|
||||
#define rFPGA1_TxBlock 0x904 /* Useless now */
|
||||
#define rFPGA1_DebugSelect 0x908 /* Useless now */
|
||||
#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
|
||||
|
||||
/*
|
||||
* PageA(0xA00)
|
||||
* */
|
||||
#define rCCK0_System 0xa00
|
||||
#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
|
||||
#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
|
||||
#define rCCK0_TxFilter1 0xa20
|
||||
#define rCCK0_TxFilter2 0xa24
|
||||
#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
|
||||
#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
|
||||
|
||||
/*
|
||||
* PageB(0xB00)
|
||||
* */
|
||||
#define rPdp_AntA 0xb00
|
||||
#define rPdp_AntA_4 0xb04
|
||||
#define rConfig_Pmpd_AntA 0xb28
|
||||
#define rConfig_AntA 0xb68
|
||||
#define rConfig_AntB 0xb6c
|
||||
#define rPdp_AntB 0xb70
|
||||
#define rPdp_AntB_4 0xb74
|
||||
#define rConfig_Pmpd_AntB 0xb98
|
||||
#define rAPK 0xbd8
|
||||
|
||||
/*
|
||||
* 6. PageC(0xC00)
|
||||
* */
|
||||
#define rOFDM0_LSTF 0xc00
|
||||
|
||||
#define rOFDM0_TRxPathEnable 0xc04
|
||||
#define rOFDM0_TRMuxPar 0xc08
|
||||
#define rOFDM0_TRSWIsolation 0xc0c
|
||||
|
||||
#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
|
||||
#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
|
||||
#define rOFDM0_XBRxAFE 0xc18
|
||||
#define rOFDM0_XBRxIQImbalance 0xc1c
|
||||
#define rOFDM0_XCRxAFE 0xc20
|
||||
#define rOFDM0_XCRxIQImbalance 0xc24
|
||||
#define rOFDM0_XDRxAFE 0xc28
|
||||
#define rOFDM0_XDRxIQImbalance 0xc2c
|
||||
|
||||
#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
|
||||
#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
|
||||
#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
|
||||
#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
|
||||
|
||||
#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
|
||||
#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
|
||||
#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
|
||||
#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
|
||||
|
||||
#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
|
||||
#define rOFDM0_XAAGCCore2 0xc54
|
||||
#define rOFDM0_XBAGCCore1 0xc58
|
||||
#define rOFDM0_XBAGCCore2 0xc5c
|
||||
#define rOFDM0_XCAGCCore1 0xc60
|
||||
#define rOFDM0_XCAGCCore2 0xc64
|
||||
#define rOFDM0_XDAGCCore1 0xc68
|
||||
#define rOFDM0_XDAGCCore2 0xc6c
|
||||
|
||||
#define rOFDM0_AGCParameter1 0xc70
|
||||
#define rOFDM0_AGCParameter2 0xc74
|
||||
#define rOFDM0_AGCRSSITable 0xc78
|
||||
#define rOFDM0_HTSTFAGC 0xc7c
|
||||
|
||||
#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
|
||||
#define rOFDM0_XATxAFE 0xc84
|
||||
#define rOFDM0_XBTxIQImbalance 0xc88
|
||||
#define rOFDM0_XBTxAFE 0xc8c
|
||||
#define rOFDM0_XCTxIQImbalance 0xc90
|
||||
#define rOFDM0_XCTxAFE 0xc94
|
||||
#define rOFDM0_XDTxIQImbalance 0xc98
|
||||
#define rOFDM0_XDTxAFE 0xc9c
|
||||
|
||||
#define rOFDM0_RxIQExtAnta 0xca0
|
||||
#define rOFDM0_TxCoeff1 0xca4
|
||||
#define rOFDM0_TxCoeff2 0xca8
|
||||
#define rOFDM0_TxCoeff3 0xcac
|
||||
#define rOFDM0_TxCoeff4 0xcb0
|
||||
#define rOFDM0_TxCoeff5 0xcb4
|
||||
#define rOFDM0_TxCoeff6 0xcb8
|
||||
#define rOFDM0_RxHPParameter 0xce0
|
||||
#define rOFDM0_TxPseudoNoiseWgt 0xce4
|
||||
#define rOFDM0_FrameSync 0xcf0
|
||||
#define rOFDM0_DFSReport 0xcf4
|
||||
|
||||
/*
|
||||
* 7. PageD(0xD00)
|
||||
* */
|
||||
#define rOFDM1_LSTF 0xd00
|
||||
#define rOFDM1_TRxPathEnable 0xd04
|
||||
|
||||
/*
|
||||
* 8. PageE(0xE00)
|
||||
* */
|
||||
#define rTxAGC_A_Rate18_06 0xe00
|
||||
#define rTxAGC_A_Rate54_24 0xe04
|
||||
#define rTxAGC_A_CCK1_Mcs32 0xe08
|
||||
#define rTxAGC_A_Mcs03_Mcs00 0xe10
|
||||
#define rTxAGC_A_Mcs07_Mcs04 0xe14
|
||||
#define rTxAGC_A_Mcs11_Mcs08 0xe18
|
||||
#define rTxAGC_A_Mcs15_Mcs12 0xe1c
|
||||
|
||||
#define rTxAGC_B_Rate18_06 0x830
|
||||
#define rTxAGC_B_Rate54_24 0x834
|
||||
#define rTxAGC_B_CCK1_55_Mcs32 0x838
|
||||
#define rTxAGC_B_Mcs03_Mcs00 0x83c
|
||||
#define rTxAGC_B_Mcs07_Mcs04 0x848
|
||||
#define rTxAGC_B_Mcs11_Mcs08 0x84c
|
||||
#define rTxAGC_B_Mcs15_Mcs12 0x868
|
||||
#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
|
||||
|
||||
#define rFPGA0_IQK 0xe28
|
||||
#define rTx_IQK_Tone_A 0xe30
|
||||
#define rRx_IQK_Tone_A 0xe34
|
||||
#define rTx_IQK_PI_A 0xe38
|
||||
#define rRx_IQK_PI_A 0xe3c
|
||||
|
||||
#define rTx_IQK 0xe40
|
||||
#define rRx_IQK 0xe44
|
||||
#define rIQK_AGC_Pts 0xe48
|
||||
#define rIQK_AGC_Rsp 0xe4c
|
||||
#define rTx_IQK_Tone_B 0xe50
|
||||
#define rRx_IQK_Tone_B 0xe54
|
||||
#define rTx_IQK_PI_B 0xe58
|
||||
#define rRx_IQK_PI_B 0xe5c
|
||||
#define rIQK_AGC_Cont 0xe60
|
||||
|
||||
#define rBlue_Tooth 0xe6c
|
||||
#define rRx_Wait_CCA 0xe70
|
||||
#define rTx_CCK_RFON 0xe74
|
||||
#define rTx_CCK_BBON 0xe78
|
||||
#define rTx_OFDM_RFON 0xe7c
|
||||
#define rTx_OFDM_BBON 0xe80
|
||||
#define rTx_To_Rx 0xe84
|
||||
#define rTx_To_Tx 0xe88
|
||||
#define rRx_CCK 0xe8c
|
||||
|
||||
#define rTx_Power_Before_IQK_A 0xe94
|
||||
#define rTx_Power_After_IQK_A 0xe9c
|
||||
|
||||
#define rRx_Power_Before_IQK_A 0xea0
|
||||
#define rRx_Power_Before_IQK_A_2 0xea4
|
||||
#define rRx_Power_After_IQK_A 0xea8
|
||||
#define rRx_Power_After_IQK_A_2 0xeac
|
||||
|
||||
#define rTx_Power_Before_IQK_B 0xeb4
|
||||
#define rTx_Power_After_IQK_B 0xebc
|
||||
|
||||
#define rRx_Power_Before_IQK_B 0xec0
|
||||
#define rRx_Power_Before_IQK_B_2 0xec4
|
||||
#define rRx_Power_After_IQK_B 0xec8
|
||||
#define rRx_Power_After_IQK_B_2 0xecc
|
||||
|
||||
#define rRx_OFDM 0xed0
|
||||
#define rRx_Wait_RIFS 0xed4
|
||||
#define rRx_TO_Rx 0xed8
|
||||
#define rStandby 0xedc
|
||||
#define rSleep 0xee0
|
||||
#define rPMPD_ANAEN 0xeec
|
||||
|
||||
|
||||
/* 2. Page8(0x800) */
|
||||
#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
|
||||
#define bJapanMode 0x2
|
||||
#define bCCKTxSC 0x30
|
||||
#define bCCKEn 0x1000000
|
||||
#define bOFDMEn 0x2000000
|
||||
#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
|
||||
#define bXCTxAGC 0xf000
|
||||
#define bXDTxAGC 0xf0000
|
||||
|
||||
/* 4. PageA(0xA00) */
|
||||
#define bCCKBBMode 0x3 /* Useless */
|
||||
#define bCCKTxPowerSaving 0x80
|
||||
#define bCCKRxPowerSaving 0x40
|
||||
|
||||
#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
|
||||
|
||||
#define bCCKScramble 0x8 /* Useless */
|
||||
#define bCCKAntDiversity 0x8000
|
||||
#define bCCKCarrierRecovery 0x4000
|
||||
#define bCCKTxRate 0x3000
|
||||
#define bCCKDCCancel 0x0800
|
||||
#define bCCKISICancel 0x0400
|
||||
#define bCCKMatchFilter 0x0200
|
||||
#define bCCKEqualizer 0x0100
|
||||
#define bCCKPreambleDetect 0x800000
|
||||
#define bCCKFastFalseCCA 0x400000
|
||||
#define bCCKChEstStart 0x300000
|
||||
#define bCCKCCACount 0x080000
|
||||
#define bCCKcs_lim 0x070000
|
||||
#define bCCKBistMode 0x80000000
|
||||
#define bCCKCCAMask 0x40000000
|
||||
#define bCCKTxDACPhase 0x4
|
||||
#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
|
||||
#define bCCKr_cp_mode0 0x0100
|
||||
#define bCCKTxDCOffset 0xf0
|
||||
#define bCCKRxDCOffset 0xf
|
||||
#define bCCKCCAMode 0xc000
|
||||
#define bCCKFalseCS_lim 0x3f00
|
||||
#define bCCKCS_ratio 0xc00000
|
||||
#define bCCKCorgBit_sel 0x300000
|
||||
#define bCCKPD_lim 0x0f0000
|
||||
#define bCCKNewCCA 0x80000000
|
||||
#define bCCKRxHPofIG 0x8000
|
||||
#define bCCKRxIG 0x7f00
|
||||
#define bCCKLNAPolarity 0x800000
|
||||
#define bCCKRx1stGain 0x7f0000
|
||||
#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
|
||||
#define bCCKRxAGCSatLevel 0x1f000000
|
||||
#define bCCKRxAGCSatCount 0xe0
|
||||
#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
|
||||
#define bCCKFixedRxAGC 0x8000
|
||||
/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
|
||||
#define bCCKAntennaPolarity 0x2000
|
||||
#define bCCKTxFilterType 0x0c00
|
||||
#define bCCKRxAGCReportType 0x0300
|
||||
#define bCCKRxDAGCEn 0x80000000
|
||||
#define bCCKRxDAGCPeriod 0x20000000
|
||||
#define bCCKRxDAGCSatLevel 0x1f000000
|
||||
#define bCCKTimingRecovery 0x800000
|
||||
#define bCCKTxC0 0x3f0000
|
||||
#define bCCKTxC1 0x3f000000
|
||||
#define bCCKTxC2 0x3f
|
||||
#define bCCKTxC3 0x3f00
|
||||
#define bCCKTxC4 0x3f0000
|
||||
#define bCCKTxC5 0x3f000000
|
||||
#define bCCKTxC6 0x3f
|
||||
#define bCCKTxC7 0x3f00
|
||||
#define bCCKDebugPort 0xff0000
|
||||
#define bCCKDACDebug 0x0f000000
|
||||
#define bCCKFalseAlarmEnable 0x8000
|
||||
#define bCCKFalseAlarmRead 0x4000
|
||||
#define bCCKTRSSI 0x7f
|
||||
#define bCCKRxAGCReport 0xfe
|
||||
#define bCCKRxReport_AntSel 0x80000000
|
||||
#define bCCKRxReport_MFOff 0x40000000
|
||||
#define bCCKRxRxReport_SQLoss 0x20000000
|
||||
#define bCCKRxReport_Pktloss 0x10000000
|
||||
#define bCCKRxReport_Lockedbit 0x08000000
|
||||
#define bCCKRxReport_RateError 0x04000000
|
||||
#define bCCKRxReport_RxRate 0x03000000
|
||||
#define bCCKRxFACounterLower 0xff
|
||||
#define bCCKRxFACounterUpper 0xff000000
|
||||
#define bCCKRxHPAGCStart 0xe000
|
||||
#define bCCKRxHPAGCFinal 0x1c00
|
||||
#define bCCKRxFalseAlarmEnable 0x8000
|
||||
#define bCCKFACounterFreeze 0x4000
|
||||
#define bCCKTxPathSel 0x10000000
|
||||
#define bCCKDefaultRxPath 0xc000000
|
||||
#define bCCKOptionRxPath 0x3000000
|
||||
|
||||
/* 6. PageE(0xE00) */
|
||||
#define bSTBCEn 0x4 /* Useless */
|
||||
#define bAntennaMapping 0x10
|
||||
#define bNss 0x20
|
||||
#define bCFOAntSumD 0x200
|
||||
#define bPHYCounterReset 0x8000000
|
||||
#define bCFOReportGet 0x4000000
|
||||
#define bOFDMContinueTx 0x10000000
|
||||
#define bOFDMSingleCarrier 0x20000000
|
||||
#define bOFDMSingleTone 0x40000000
|
||||
|
||||
|
||||
/*
|
||||
* Other Definition
|
||||
* */
|
||||
|
||||
#define bEnable 0x1 /* Useless */
|
||||
#define bDisable 0x0
|
||||
|
||||
/* byte endable for srwrite */
|
||||
#define bByte0 0x1 /* Useless */
|
||||
#define bByte1 0x2
|
||||
#define bByte2 0x4
|
||||
#define bByte3 0x8
|
||||
#define bWord0 0x3
|
||||
#define bWord1 0xc
|
||||
#define bDWord 0xf
|
||||
|
||||
/* for PutRegsetting & GetRegSetting BitMask */
|
||||
#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
|
||||
#define bMaskByte1 0xff00
|
||||
#define bMaskByte2 0xff0000
|
||||
#define bMaskByte3 0xff000000
|
||||
#define bMaskHWord 0xffff0000
|
||||
#define bMaskLWord 0x0000ffff
|
||||
#define bMaskDWord 0xffffffff
|
||||
#define bMaskH3Bytes 0xffffff00
|
||||
#define bMask12Bits 0xfff
|
||||
#define bMaskH4Bits 0xf0000000
|
||||
#define bMaskOFDM_D 0xffc00000
|
||||
#define bMaskCCK 0x3f3f3f3f
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
#ifndef __HAL8812PWRSEQ_H__
|
||||
#define __HAL8812PWRSEQ_H__
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
|
||||
#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8812_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* 0x24[1] Choose the type of buffer after xosc: nand*/ \
|
||||
{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /* 0x28[33] Choose the type of buffer after xosc: nand*/
|
||||
|
||||
#define RTL8812_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \
|
||||
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
|
||||
|
||||
#define RTL8812_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
|
||||
/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},\
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},\
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \
|
||||
{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
|
||||
|
||||
#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \
|
||||
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
|
||||
{0x0024, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /* 0x24[1] Choose the type of buffer after xosc: schmitt trigger*/ \
|
||||
{0x0028, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /* 0x28[33] Choose the type of buffer after xosc: schmitt trigger*/
|
||||
|
||||
|
||||
#define RTL8812_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8812_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8812_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
|
||||
|
||||
|
||||
#define RTL8812_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8812_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_SUS_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS + RTL8812_TRANS_CARDEMU_TO_PDN_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS + RTL8812_TRANS_END_STEPS];
|
||||
|
||||
#endif /* __HAL8812PWRSEQ_H__ */
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8814PHYCFG_H__
|
||||
#define __INC_HAL8814PHYCFG_H__
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define LOOP_LIMIT 5
|
||||
#define MAX_STALL_TIME 50 /* us */
|
||||
#define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */
|
||||
#define MAX_TXPWR_IDX_NMODE_92S 63
|
||||
#define Reset_Cnt_Limit 3
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define MAX_AGGR_NUM 0x0B
|
||||
#else
|
||||
#define MAX_AGGR_NUM 0x07
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/* BB/RF related */
|
||||
|
||||
#define SIC_ENABLE 0
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
/*------------------------Export global variable----------------------------*/
|
||||
|
||||
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
/*------------------------Export Marco Definition---------------------------*/
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
/* 1. BB register R/W API */
|
||||
|
||||
extern u32
|
||||
PHY_QueryBBReg8814A(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
|
||||
|
||||
void
|
||||
PHY_SetBBReg8814A(PADAPTER Adapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
|
||||
|
||||
extern u32
|
||||
PHY_QueryRFReg8814A(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask);
|
||||
|
||||
|
||||
void
|
||||
PHY_SetRFReg8814A(PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data);
|
||||
|
||||
/* 1 3. Initial BB/RF config by reading MAC/BB/RF txt. */
|
||||
s32
|
||||
phy_BB8814A_Config_ParaFile(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
void
|
||||
PHY_ConfigBB_8814A(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
phy_ADC_CLK_8814A(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
s32
|
||||
PHY_RFConfig8814A(
|
||||
PADAPTER Adapter
|
||||
);
|
||||
|
||||
/*
|
||||
* RF Power setting
|
||||
*
|
||||
* BOOLEAN PHY_SetRFPowerState8814A(PADAPTER Adapter, rt_rf_power_state eRFPowerState); */
|
||||
|
||||
/* 1 5. Tx Power setting API */
|
||||
|
||||
void
|
||||
PHY_SetTxPowerLevel8814(
|
||||
PADAPTER Adapter,
|
||||
u8 Channel
|
||||
);
|
||||
|
||||
u8
|
||||
phy_get_tx_power_index_8814a(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate,
|
||||
enum channel_width BandWidth,
|
||||
u8 Channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex_8814A(
|
||||
PADAPTER Adapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
u32
|
||||
PHY_GetTxBBSwing_8814A(
|
||||
PADAPTER Adapter,
|
||||
BAND_TYPE Band,
|
||||
enum rf_path RFPath
|
||||
);
|
||||
|
||||
|
||||
|
||||
/* 1 6. Channel setting API */
|
||||
#if 0
|
||||
void
|
||||
PHY_SwChnlTimerCallback8814A(
|
||||
struct timer_list *p_timer
|
||||
);
|
||||
#endif
|
||||
void
|
||||
PHY_SwChnlWorkItemCallback8814A(
|
||||
void *pContext
|
||||
);
|
||||
|
||||
|
||||
void
|
||||
HAL_HandleSwChnl8814A(
|
||||
PADAPTER pAdapter,
|
||||
u8 channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SwChnlSynchronously8814A(PADAPTER pAdapter,
|
||||
u8 channel);
|
||||
|
||||
void
|
||||
PHY_HandleSwChnlAndSetBW8814A(
|
||||
PADAPTER Adapter,
|
||||
BOOLEAN bSwitchChannel,
|
||||
BOOLEAN bSetBandWidth,
|
||||
u8 ChannelNum,
|
||||
enum channel_width ChnlWidth,
|
||||
u8 ChnlOffsetOf40MHz,
|
||||
u8 ChnlOffsetOf80MHz,
|
||||
u8 CenterFrequencyIndex1
|
||||
);
|
||||
|
||||
|
||||
BOOLEAN
|
||||
PHY_QueryRFPathSwitch_8814A(PADAPTER pAdapter);
|
||||
|
||||
|
||||
|
||||
#if (USE_WORKITEM)
|
||||
void
|
||||
RtCheckForHangWorkItemCallback8814A(
|
||||
void *pContext
|
||||
);
|
||||
#endif
|
||||
|
||||
BOOLEAN
|
||||
SetAntennaConfig8814A(
|
||||
PADAPTER Adapter,
|
||||
u8 DefaultAnt
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetRFEReg8814A(
|
||||
PADAPTER Adapter,
|
||||
BOOLEAN bInit,
|
||||
u8 Band
|
||||
);
|
||||
|
||||
|
||||
s32
|
||||
PHY_SwitchWirelessBand8814A(
|
||||
PADAPTER Adapter,
|
||||
u8 Band
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetIO_8814A(
|
||||
PADAPTER pAdapter
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetSwChnlBWMode8814(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
enum channel_width Bandwidth,
|
||||
u8 Offset40,
|
||||
u8 Offset80
|
||||
);
|
||||
|
||||
s32 PHY_MACConfig8814(PADAPTER Adapter);
|
||||
int PHY_BBConfig8814(PADAPTER Adapter);
|
||||
void PHY_Set_SecCCATH_by_RXANT_8814A(PADAPTER pAdapter, u32 ulAntennaRx);
|
||||
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
#endif /* __INC_HAL8192CPHYCFG_H */
|
||||
|
|
@ -0,0 +1,863 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __INC_HAL8814PHYREG_H__
|
||||
#define __INC_HAL8814PHYREG_H__
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
/*
|
||||
* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
|
||||
* 3. RF register 0x00-2E
|
||||
* 4. Bit Mask for BB/RF register
|
||||
* 5. Other defintion for BB/RF R/W
|
||||
* */
|
||||
|
||||
|
||||
/* BB Register Definition */
|
||||
|
||||
#define rCCAonSec_Jaguar 0x838
|
||||
#define rPwed_TH_Jaguar 0x830
|
||||
#define rL1_Weight_Jaguar 0x840
|
||||
#define r_L1_SBD_start_time 0x844
|
||||
|
||||
/* BW and sideband setting */
|
||||
#define rBWIndication_Jaguar 0x834
|
||||
#define rL1PeakTH_Jaguar 0x848
|
||||
#define rRFMOD_Jaguar 0x8ac /* RF mode */
|
||||
#define rADC_Buf_Clk_Jaguar 0x8c4
|
||||
#define rADC_Buf_40_Clk_Jaguar2 0x8c8
|
||||
#define rRFECTRL_Jaguar 0x900
|
||||
#define bRFMOD_Jaguar 0xc3
|
||||
#define rCCK_System_Jaguar 0xa00 /* for cck sideband */
|
||||
#define bCCK_System_Jaguar 0x10
|
||||
|
||||
/* Block & Path enable */
|
||||
#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
|
||||
#define bOFDMEN_Jaguar 0x20000000
|
||||
#define bCCKEN_Jaguar 0x10000000
|
||||
#define rRxPath_Jaguar 0x808 /* Rx antenna */
|
||||
#define bRxPath_Jaguar 0xff
|
||||
#define rTxPath_Jaguar 0x80c /* Tx antenna */
|
||||
#define bTxPath_Jaguar 0x0fffffff
|
||||
#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
|
||||
#define bCCK_RX_Jaguar 0x0c000000
|
||||
#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
|
||||
|
||||
#define rRxPath_Jaguar2 0xa04 /* Rx antenna */
|
||||
#define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */
|
||||
#define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */
|
||||
|
||||
|
||||
/* RF read/write-related */
|
||||
#define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
|
||||
#define bHSSIRead_addr_Jaguar 0xff
|
||||
#define bHSSIRead_trigger_Jaguar 0x100
|
||||
#define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
|
||||
#define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
|
||||
#define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
|
||||
#define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
|
||||
#define rRead_data_Jaguar 0xfffff
|
||||
#define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
|
||||
#define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
|
||||
#define bLSSIWrite_data_Jaguar 0x000fffff
|
||||
#define bLSSIWrite_addr_Jaguar 0x0ff00000
|
||||
|
||||
#define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */
|
||||
#define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */
|
||||
#define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */
|
||||
#define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */
|
||||
#define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */
|
||||
#define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily */
|
||||
#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
|
||||
#define rFPGA0_XB_RFInterfaceOE 0x864
|
||||
|
||||
#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
|
||||
#define rFPGA0_XCD_RFInterfaceSW 0x874
|
||||
|
||||
/* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
|
||||
* #define rFPGA0_XCD_RFParameter 0x87c */
|
||||
|
||||
/* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
|
||||
* #define rFPGA0_AnalogParameter2 0x884
|
||||
* #define rFPGA0_AnalogParameter3 0x888
|
||||
* #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
|
||||
* #define rFPGA0_AnalogParameter4 0x88c */
|
||||
|
||||
|
||||
/* CCK TX scaling */
|
||||
#define rCCK_TxFilter1_Jaguar 0xa20
|
||||
#define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter1_C1_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter2_Jaguar 0xa24
|
||||
#define bCCK_TxFilter2_C2_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
|
||||
#define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
|
||||
#define bCCK_TxFilter2_C5_Jaguar 0xff000000
|
||||
#define rCCK_TxFilter3_Jaguar 0xa28
|
||||
#define bCCK_TxFilter3_C6_Jaguar 0x000000ff
|
||||
#define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
|
||||
/* NBI & CSI Mask setting */
|
||||
#define rCSI_Mask_Setting1_Jaguar 0x874
|
||||
#define rCSI_Fix_Mask0_Jaguar 0x880
|
||||
#define rCSI_Fix_Mask1_Jaguar 0x884
|
||||
#define rCSI_Fix_Mask2_Jaguar 0x888
|
||||
#define rCSI_Fix_Mask3_Jaguar 0x88c
|
||||
#define rCSI_Fix_Mask4_Jaguar 0x890
|
||||
#define rCSI_Fix_Mask5_Jaguar 0x894
|
||||
#define rCSI_Fix_Mask6_Jaguar 0x898
|
||||
#define rCSI_Fix_Mask7_Jaguar 0x89c
|
||||
#define rNBI_Setting_Jaguar 0x87c
|
||||
|
||||
|
||||
/* YN: mask the following register definition temporarily
|
||||
* #define rPdp_AntA 0xb00
|
||||
* #define rPdp_AntA_4 0xb04
|
||||
* #define rConfig_Pmpd_AntA 0xb28
|
||||
* #define rConfig_AntA 0xb68
|
||||
* #define rConfig_AntB 0xb6c
|
||||
* #define rPdp_AntB 0xb70
|
||||
* #define rPdp_AntB_4 0xb74
|
||||
* #define rConfig_Pmpd_AntB 0xb98
|
||||
* #define rAPK 0xbd8 */
|
||||
|
||||
/* RXIQC */
|
||||
#define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
|
||||
#define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
|
||||
#define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
|
||||
#define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
|
||||
#define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
|
||||
#define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
|
||||
|
||||
#define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */
|
||||
#define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */
|
||||
#define rRF_TxGainOffset 0x55
|
||||
|
||||
/* DIG-related */
|
||||
#define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
|
||||
#define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
|
||||
#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */
|
||||
#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */
|
||||
|
||||
#define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
|
||||
#define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
|
||||
#define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
|
||||
#define b_FalseAlarm_Jaguar 0xffff
|
||||
#define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
|
||||
#define bCCK_CCA_Jaguar 0x00ff0000
|
||||
|
||||
/* Tx Power Ttraining-related */
|
||||
#define rA_TxPwrTraing_Jaguar 0xc54
|
||||
#define rB_TxPwrTraing_Jaguar 0xe54
|
||||
|
||||
/* Report-related */
|
||||
#define rOFDM_ShortCFOAB_Jaguar 0xf60
|
||||
#define rOFDM_LongCFOAB_Jaguar 0xf64
|
||||
#define rOFDM_EndCFOAB_Jaguar 0xf70
|
||||
#define rOFDM_AGCReport_Jaguar 0xf84
|
||||
#define rOFDM_RxSNR_Jaguar 0xf88
|
||||
#define rOFDM_RxEVMCSI_Jaguar 0xf8c
|
||||
#define rOFDM_SIGReport_Jaguar 0xf90
|
||||
|
||||
/* Misc functions */
|
||||
#define rEDCCA_Jaguar 0x8a4 /* EDCCA */
|
||||
#define bEDCCA_Jaguar 0xffff
|
||||
#define rAGC_table_Jaguar 0x82c /* AGC tabel select */
|
||||
#define bAGC_table_Jaguar 0x3
|
||||
#define b_sel5g_Jaguar 0x1000 /* sel5g */
|
||||
#define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
|
||||
#define rFc_area_Jaguar 0x860 /* fc_area */
|
||||
#define bFc_area_Jaguar 0x1ffe000
|
||||
#define rSingleTone_ContTx_Jaguar 0x914
|
||||
|
||||
#define rAGC_table_Jaguar2 0x958 /* AGC tabel select */
|
||||
#define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */
|
||||
|
||||
|
||||
/* RFE */
|
||||
#define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
|
||||
#define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
|
||||
#define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
|
||||
#define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
|
||||
#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
|
||||
#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
|
||||
#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
|
||||
#define bMask_RFEInv_Jaguar 0x3ff00000
|
||||
#define bMask_AntselPathFollow_Jaguar 0x00030000
|
||||
|
||||
#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */
|
||||
#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */
|
||||
#define rA_RFE_Sel_Jaguar2 0x1990
|
||||
|
||||
|
||||
|
||||
/* TX AGC */
|
||||
#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
|
||||
#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
|
||||
#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
|
||||
#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
|
||||
#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
|
||||
#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
|
||||
#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
|
||||
#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
|
||||
#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
|
||||
#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
|
||||
#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
|
||||
#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
|
||||
#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
|
||||
#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
|
||||
#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
|
||||
#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
|
||||
#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
|
||||
#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
|
||||
#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
|
||||
#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
|
||||
#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
|
||||
#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
|
||||
#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
|
||||
#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
|
||||
#define bTxAGC_byte0_Jaguar 0xff
|
||||
#define bTxAGC_byte1_Jaguar 0xff00
|
||||
#define bTxAGC_byte2_Jaguar 0xff0000
|
||||
#define bTxAGC_byte3_Jaguar 0xff000000
|
||||
|
||||
|
||||
/* TX AGC */
|
||||
#define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20
|
||||
#define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24
|
||||
#define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28
|
||||
#define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c
|
||||
#define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30
|
||||
#define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34
|
||||
#define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38
|
||||
#define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8
|
||||
#define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc
|
||||
#define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c
|
||||
#define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40
|
||||
#define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44
|
||||
#define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48
|
||||
#define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c
|
||||
#define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0
|
||||
#define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4
|
||||
#define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8
|
||||
#define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20
|
||||
#define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24
|
||||
#define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28
|
||||
#define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c
|
||||
#define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30
|
||||
#define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34
|
||||
#define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38
|
||||
#define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8
|
||||
#define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc
|
||||
#define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c
|
||||
#define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40
|
||||
#define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44
|
||||
#define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48
|
||||
#define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c
|
||||
#define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0
|
||||
#define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4
|
||||
#define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8
|
||||
#define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820
|
||||
#define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824
|
||||
#define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828
|
||||
#define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c
|
||||
#define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830
|
||||
#define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834
|
||||
#define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838
|
||||
#define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8
|
||||
#define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc
|
||||
#define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c
|
||||
#define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840
|
||||
#define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844
|
||||
#define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848
|
||||
#define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c
|
||||
#define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0
|
||||
#define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4
|
||||
#define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8
|
||||
#define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20
|
||||
#define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24
|
||||
#define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28
|
||||
#define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c
|
||||
#define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30
|
||||
#define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34
|
||||
#define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38
|
||||
#define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8
|
||||
#define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc
|
||||
#define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c
|
||||
#define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40
|
||||
#define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44
|
||||
#define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48
|
||||
#define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c
|
||||
#define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0
|
||||
#define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4
|
||||
#define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8
|
||||
/* IQK YN: temporaily mask this part
|
||||
* #define rFPGA0_IQK 0xe28
|
||||
* #define rTx_IQK_Tone_A 0xe30
|
||||
* #define rRx_IQK_Tone_A 0xe34
|
||||
* #define rTx_IQK_PI_A 0xe38
|
||||
* #define rRx_IQK_PI_A 0xe3c */
|
||||
|
||||
/* #define rTx_IQK 0xe40 */
|
||||
/* #define rRx_IQK 0xe44 */
|
||||
/* #define rIQK_AGC_Pts 0xe48 */
|
||||
/* #define rIQK_AGC_Rsp 0xe4c */
|
||||
/* #define rTx_IQK_Tone_B 0xe50 */
|
||||
/* #define rRx_IQK_Tone_B 0xe54 */
|
||||
/* #define rTx_IQK_PI_B 0xe58 */
|
||||
/* #define rRx_IQK_PI_B 0xe5c */
|
||||
/* #define rIQK_AGC_Cont 0xe60 */
|
||||
|
||||
|
||||
/* AFE-related */
|
||||
#define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
|
||||
#define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
|
||||
#define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
|
||||
#define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
|
||||
#define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
|
||||
#define rA_Tx2Tx_RXCCK_Jaguar 0xc74
|
||||
#define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
|
||||
#define rA_Rx2Rx_BT_Jaguar 0xc7c
|
||||
#define rA_sleep_nav_Jaguar 0xc80
|
||||
#define rA_pmpd_Jaguar 0xc84
|
||||
#define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
|
||||
#define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
|
||||
#define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
|
||||
#define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
|
||||
#define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
|
||||
#define rB_Tx2Tx_RXCCK_Jaguar 0xe74
|
||||
#define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
|
||||
#define rB_Rx2Rx_BT_Jaguar 0xe7c
|
||||
#define rB_sleep_nav_Jaguar 0xe80
|
||||
#define rB_pmpd_Jaguar 0xe84
|
||||
|
||||
|
||||
/* YN: mask these registers temporaily
|
||||
* #define rTx_Power_Before_IQK_A 0xe94
|
||||
* #define rTx_Power_After_IQK_A 0xe9c */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_A 0xea0 */
|
||||
/* #define rRx_Power_Before_IQK_A_2 0xea4 */
|
||||
/* #define rRx_Power_After_IQK_A 0xea8 */
|
||||
/* #define rRx_Power_After_IQK_A_2 0xeac */
|
||||
|
||||
/* #define rTx_Power_Before_IQK_B 0xeb4 */
|
||||
/* #define rTx_Power_After_IQK_B 0xebc */
|
||||
|
||||
/* #define rRx_Power_Before_IQK_B 0xec0 */
|
||||
/* #define rRx_Power_Before_IQK_B_2 0xec4 */
|
||||
/* #define rRx_Power_After_IQK_B 0xec8 */
|
||||
/* #define rRx_Power_After_IQK_B_2 0xecc */
|
||||
|
||||
|
||||
/* RSSI Dump */
|
||||
#define rA_RSSIDump_Jaguar 0xBF0
|
||||
#define rB_RSSIDump_Jaguar 0xBF1
|
||||
#define rS1_RXevmDump_Jaguar 0xBF4
|
||||
#define rS2_RXevmDump_Jaguar 0xBF5
|
||||
#define rA_RXsnrDump_Jaguar 0xBF6
|
||||
#define rB_RXsnrDump_Jaguar 0xBF7
|
||||
#define rA_CfoShortDump_Jaguar 0xBF8
|
||||
#define rB_CfoShortDump_Jaguar 0xBFA
|
||||
#define rA_CfoLongDump_Jaguar 0xBEC
|
||||
#define rB_CfoLongDump_Jaguar 0xBEE
|
||||
|
||||
|
||||
/* RF Register
|
||||
* */
|
||||
#define RF_AC_Jaguar 0x00 /* */
|
||||
#define RF_RF_Top_Jaguar 0x07 /* */
|
||||
#define RF_TXLOK_Jaguar 0x08 /* */
|
||||
#define RF_TXAPK_Jaguar 0x0B
|
||||
#define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK1_Jaguar 0x1c /* */
|
||||
#define RF_RCK2_Jaguar 0x1d
|
||||
#define RF_RCK3_Jaguar 0x1e
|
||||
#define RF_ModeTableAddr 0x30
|
||||
#define RF_ModeTableData0 0x31
|
||||
#define RF_ModeTableData1 0x32
|
||||
#define RF_TxLCTank_Jaguar 0x54
|
||||
#define RF_APK_Jaguar 0x63
|
||||
#define RF_LCK 0xB4
|
||||
#define RF_WeLut_Jaguar 0xEF
|
||||
|
||||
#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
|
||||
#define bRF_CHNLBW_BW 0xc00
|
||||
|
||||
|
||||
/*
|
||||
* RL6052 Register definition
|
||||
* */
|
||||
#define RF_AC 0x00 /* */
|
||||
#define RF_IPA_A 0x0C /* */
|
||||
#define RF_TXBIAS_A 0x0D
|
||||
#define RF_BS_PA_APSET_G9_G11 0x0E
|
||||
#define RF_MODE1 0x10 /* */
|
||||
#define RF_MODE2 0x11 /* */
|
||||
#define RF_CHNLBW 0x18 /* RF channel and BW switch */
|
||||
#define RF_RCK_OS 0x30 /* RF TX PA control */
|
||||
#define RF_TXPA_G1 0x31 /* RF TX PA control */
|
||||
#define RF_TXPA_G2 0x32 /* RF TX PA control */
|
||||
#define RF_TXPA_G3 0x33 /* RF TX PA control */
|
||||
#define RF_0x52 0x52
|
||||
#define RF_WE_LUT 0xEF
|
||||
|
||||
/*
|
||||
* Bit Mask
|
||||
*
|
||||
* 1. Page1(0x100) */
|
||||
#define bBBResetB 0x100 /* Useless now? */
|
||||
#define bGlobalResetB 0x200
|
||||
#define bOFDMTxStart 0x4
|
||||
#define bCCKTxStart 0x8
|
||||
#define bCRC32Debug 0x100
|
||||
#define bPMACLoopback 0x10
|
||||
#define bTxLSIG 0xffffff
|
||||
#define bOFDMTxRate 0xf
|
||||
#define bOFDMTxReserved 0x10
|
||||
#define bOFDMTxLength 0x1ffe0
|
||||
#define bOFDMTxParity 0x20000
|
||||
#define bTxHTSIG1 0xffffff
|
||||
#define bTxHTMCSRate 0x7f
|
||||
#define bTxHTBW 0x80
|
||||
#define bTxHTLength 0xffff00
|
||||
#define bTxHTSIG2 0xffffff
|
||||
#define bTxHTSmoothing 0x1
|
||||
#define bTxHTSounding 0x2
|
||||
#define bTxHTReserved 0x4
|
||||
#define bTxHTAggreation 0x8
|
||||
#define bTxHTSTBC 0x30
|
||||
#define bTxHTAdvanceCoding 0x40
|
||||
#define bTxHTShortGI 0x80
|
||||
#define bTxHTNumberHT_LTF 0x300
|
||||
#define bTxHTCRC8 0x3fc00
|
||||
#define bCounterReset 0x10000
|
||||
#define bNumOfOFDMTx 0xffff
|
||||
#define bNumOfCCKTx 0xffff0000
|
||||
#define bTxIdleInterval 0xffff
|
||||
#define bOFDMService 0xffff0000
|
||||
#define bTxMACHeader 0xffffffff
|
||||
#define bTxDataInit 0xff
|
||||
#define bTxHTMode 0x100
|
||||
#define bTxDataType 0x30000
|
||||
#define bTxRandomSeed 0xffffffff
|
||||
#define bCCKTxPreamble 0x1
|
||||
#define bCCKTxSFD 0xffff0000
|
||||
#define bCCKTxSIG 0xff
|
||||
#define bCCKTxService 0xff00
|
||||
#define bCCKLengthExt 0x8000
|
||||
#define bCCKTxLength 0xffff0000
|
||||
#define bCCKTxCRC16 0xffff
|
||||
#define bCCKTxStatus 0x1
|
||||
#define bOFDMTxStatus 0x2
|
||||
|
||||
|
||||
/*
|
||||
* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
|
||||
* 1. Page1(0x100)
|
||||
* */
|
||||
#define rPMAC_Reset 0x100
|
||||
#define rPMAC_TxStart 0x104
|
||||
#define rPMAC_TxLegacySIG 0x108
|
||||
#define rPMAC_TxHTSIG1 0x10c
|
||||
#define rPMAC_TxHTSIG2 0x110
|
||||
#define rPMAC_PHYDebug 0x114
|
||||
#define rPMAC_TxPacketNum 0x118
|
||||
#define rPMAC_TxIdle 0x11c
|
||||
#define rPMAC_TxMACHeader0 0x120
|
||||
#define rPMAC_TxMACHeader1 0x124
|
||||
#define rPMAC_TxMACHeader2 0x128
|
||||
#define rPMAC_TxMACHeader3 0x12c
|
||||
#define rPMAC_TxMACHeader4 0x130
|
||||
#define rPMAC_TxMACHeader5 0x134
|
||||
#define rPMAC_TxDataType 0x138
|
||||
#define rPMAC_TxRandomSeed 0x13c
|
||||
#define rPMAC_CCKPLCPPreamble 0x140
|
||||
#define rPMAC_CCKPLCPHeader 0x144
|
||||
#define rPMAC_CCKCRC16 0x148
|
||||
#define rPMAC_OFDMRxCRC32OK 0x170
|
||||
#define rPMAC_OFDMRxCRC32Er 0x174
|
||||
#define rPMAC_OFDMRxParityEr 0x178
|
||||
#define rPMAC_OFDMRxCRC8Er 0x17c
|
||||
#define rPMAC_CCKCRxRC16Er 0x180
|
||||
#define rPMAC_CCKCRxRC32Er 0x184
|
||||
#define rPMAC_CCKCRxRC32OK 0x188
|
||||
#define rPMAC_TxStatus 0x18c
|
||||
|
||||
/*
|
||||
* 3. Page8(0x800)
|
||||
* */
|
||||
#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
|
||||
|
||||
#define rFPGA0_TxInfo 0x804 /* Status report?? */
|
||||
#define rFPGA0_PSDFunction 0x808
|
||||
#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
|
||||
|
||||
#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
|
||||
#define rFPGA0_XA_HSSIParameter2 0x824
|
||||
#define rFPGA0_XB_HSSIParameter1 0x828
|
||||
#define rFPGA0_XB_HSSIParameter2 0x82c
|
||||
|
||||
#define rFPGA0_XA_LSSIParameter 0x840
|
||||
#define rFPGA0_XB_LSSIParameter 0x844
|
||||
|
||||
#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
|
||||
#define rFPGA0_XCD_SwitchControl 0x85c
|
||||
|
||||
#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
|
||||
#define rFPGA0_XCD_RFParameter 0x87c
|
||||
|
||||
#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
|
||||
#define rFPGA0_AnalogParameter2 0x884
|
||||
#define rFPGA0_AnalogParameter3 0x888
|
||||
#define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
|
||||
#define rFPGA0_AnalogParameter4 0x88c
|
||||
|
||||
#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
|
||||
#define rFPGA0_XB_LSSIReadBack 0x8a4
|
||||
#define rFPGA0_XC_LSSIReadBack 0x8a8
|
||||
#define rFPGA0_XD_LSSIReadBack 0x8ac
|
||||
|
||||
#define rFPGA0_XCD_RFPara 0x8b4
|
||||
#define rFPGA0_PSDReport 0x8b4 /* Useless now */
|
||||
#define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
|
||||
#define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
|
||||
#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */
|
||||
#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
|
||||
|
||||
/*
|
||||
* 4. Page9(0x900)
|
||||
* */
|
||||
#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
|
||||
#define REG_BB_TX_PATH_SEL_1_8814A 0x93c
|
||||
#define REG_BB_TX_PATH_SEL_2_8814A 0x940
|
||||
#define rFPGA1_TxBlock 0x904 /* Useless now */
|
||||
#define rFPGA1_DebugSelect 0x908 /* Useless now */
|
||||
#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
|
||||
/*Page 19 for TxBF*/
|
||||
#define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac
|
||||
#define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4
|
||||
/*
|
||||
* PageA(0xA00)
|
||||
* */
|
||||
#define rCCK0_System 0xa00
|
||||
#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
|
||||
#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
|
||||
#define rCCK0_TxFilter1 0xa20
|
||||
#define rCCK0_TxFilter2 0xa24
|
||||
#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
|
||||
#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
|
||||
|
||||
/*
|
||||
* PageB(0xB00)
|
||||
* */
|
||||
#define rPdp_AntA 0xb00
|
||||
#define rPdp_AntA_4 0xb04
|
||||
#define rConfig_Pmpd_AntA 0xb28
|
||||
#define rConfig_AntA 0xb68
|
||||
#define rConfig_AntB 0xb6c
|
||||
#define rPdp_AntB 0xb70
|
||||
#define rPdp_AntB_4 0xb74
|
||||
#define rConfig_Pmpd_AntB 0xb98
|
||||
#define rAPK 0xbd8
|
||||
|
||||
/*
|
||||
* 6. PageC(0xC00)
|
||||
* */
|
||||
#define rOFDM0_LSTF 0xc00
|
||||
|
||||
#define rOFDM0_TRxPathEnable 0xc04
|
||||
#define rOFDM0_TRMuxPar 0xc08
|
||||
#define rOFDM0_TRSWIsolation 0xc0c
|
||||
|
||||
#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
|
||||
#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
|
||||
#define rOFDM0_XBRxAFE 0xc18
|
||||
#define rOFDM0_XBRxIQImbalance 0xc1c
|
||||
#define rOFDM0_XCRxAFE 0xc20
|
||||
#define rOFDM0_XCRxIQImbalance 0xc24
|
||||
#define rOFDM0_XDRxAFE 0xc28
|
||||
#define rOFDM0_XDRxIQImbalance 0xc2c
|
||||
|
||||
#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
|
||||
#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
|
||||
#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
|
||||
#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
|
||||
|
||||
#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
|
||||
#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
|
||||
#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
|
||||
#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
|
||||
|
||||
#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
|
||||
#define rOFDM0_XAAGCCore2 0xc54
|
||||
#define rOFDM0_XBAGCCore1 0xc58
|
||||
#define rOFDM0_XBAGCCore2 0xc5c
|
||||
#define rOFDM0_XCAGCCore1 0xc60
|
||||
#define rOFDM0_XCAGCCore2 0xc64
|
||||
#define rOFDM0_XDAGCCore1 0xc68
|
||||
#define rOFDM0_XDAGCCore2 0xc6c
|
||||
|
||||
#define rOFDM0_AGCParameter1 0xc70
|
||||
#define rOFDM0_AGCParameter2 0xc74
|
||||
#define rOFDM0_AGCRSSITable 0xc78
|
||||
#define rOFDM0_HTSTFAGC 0xc7c
|
||||
|
||||
#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
|
||||
#define rOFDM0_XATxAFE 0xc84
|
||||
#define rOFDM0_XBTxIQImbalance 0xc88
|
||||
#define rOFDM0_XBTxAFE 0xc8c
|
||||
#define rOFDM0_XCTxIQImbalance 0xc90
|
||||
#define rOFDM0_XCTxAFE 0xc94
|
||||
#define rOFDM0_XDTxIQImbalance 0xc98
|
||||
#define rOFDM0_XDTxAFE 0xc9c
|
||||
|
||||
#define rOFDM0_RxIQExtAnta 0xca0
|
||||
#define rOFDM0_TxCoeff1 0xca4
|
||||
#define rOFDM0_TxCoeff2 0xca8
|
||||
#define rOFDM0_TxCoeff3 0xcac
|
||||
#define rOFDM0_TxCoeff4 0xcb0
|
||||
#define rOFDM0_TxCoeff5 0xcb4
|
||||
#define rOFDM0_TxCoeff6 0xcb8
|
||||
#define rOFDM0_RxHPParameter 0xce0
|
||||
#define rOFDM0_TxPseudoNoiseWgt 0xce4
|
||||
#define rOFDM0_FrameSync 0xcf0
|
||||
#define rOFDM0_DFSReport 0xcf4
|
||||
|
||||
/*
|
||||
* 7. PageD(0xD00)
|
||||
* */
|
||||
#define rOFDM1_LSTF 0xd00
|
||||
#define rOFDM1_TRxPathEnable 0xd04
|
||||
|
||||
/*
|
||||
* 8. PageE(0xE00)
|
||||
* */
|
||||
#define rTxAGC_A_Rate18_06 0xe00
|
||||
#define rTxAGC_A_Rate54_24 0xe04
|
||||
#define rTxAGC_A_CCK1_Mcs32 0xe08
|
||||
#define rTxAGC_A_Mcs03_Mcs00 0xe10
|
||||
#define rTxAGC_A_Mcs07_Mcs04 0xe14
|
||||
#define rTxAGC_A_Mcs11_Mcs08 0xe18
|
||||
#define rTxAGC_A_Mcs15_Mcs12 0xe1c
|
||||
|
||||
#define rTxAGC_B_Rate18_06 0x830
|
||||
#define rTxAGC_B_Rate54_24 0x834
|
||||
#define rTxAGC_B_CCK1_55_Mcs32 0x838
|
||||
#define rTxAGC_B_Mcs03_Mcs00 0x83c
|
||||
#define rTxAGC_B_Mcs07_Mcs04 0x848
|
||||
#define rTxAGC_B_Mcs11_Mcs08 0x84c
|
||||
#define rTxAGC_B_Mcs15_Mcs12 0x868
|
||||
#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
|
||||
|
||||
#define rFPGA0_IQK 0xe28
|
||||
#define rTx_IQK_Tone_A 0xe30
|
||||
#define rRx_IQK_Tone_A 0xe34
|
||||
#define rTx_IQK_PI_A 0xe38
|
||||
#define rRx_IQK_PI_A 0xe3c
|
||||
|
||||
#define rTx_IQK 0xe40
|
||||
#define rRx_IQK 0xe44
|
||||
#define rIQK_AGC_Pts 0xe48
|
||||
#define rIQK_AGC_Rsp 0xe4c
|
||||
#define rTx_IQK_Tone_B 0xe50
|
||||
#define rRx_IQK_Tone_B 0xe54
|
||||
#define rTx_IQK_PI_B 0xe58
|
||||
#define rRx_IQK_PI_B 0xe5c
|
||||
#define rIQK_AGC_Cont 0xe60
|
||||
|
||||
#define rBlue_Tooth 0xe6c
|
||||
#define rRx_Wait_CCA 0xe70
|
||||
#define rTx_CCK_RFON 0xe74
|
||||
#define rTx_CCK_BBON 0xe78
|
||||
#define rTx_OFDM_RFON 0xe7c
|
||||
#define rTx_OFDM_BBON 0xe80
|
||||
#define rTx_To_Rx 0xe84
|
||||
#define rTx_To_Tx 0xe88
|
||||
#define rRx_CCK 0xe8c
|
||||
|
||||
#define rTx_Power_Before_IQK_A 0xe94
|
||||
#define rTx_Power_After_IQK_A 0xe9c
|
||||
|
||||
#define rRx_Power_Before_IQK_A 0xea0
|
||||
#define rRx_Power_Before_IQK_A_2 0xea4
|
||||
#define rRx_Power_After_IQK_A 0xea8
|
||||
#define rRx_Power_After_IQK_A_2 0xeac
|
||||
|
||||
#define rTx_Power_Before_IQK_B 0xeb4
|
||||
#define rTx_Power_After_IQK_B 0xebc
|
||||
|
||||
#define rRx_Power_Before_IQK_B 0xec0
|
||||
#define rRx_Power_Before_IQK_B_2 0xec4
|
||||
#define rRx_Power_After_IQK_B 0xec8
|
||||
#define rRx_Power_After_IQK_B_2 0xecc
|
||||
|
||||
#define rRx_OFDM 0xed0
|
||||
#define rRx_Wait_RIFS 0xed4
|
||||
#define rRx_TO_Rx 0xed8
|
||||
#define rStandby 0xedc
|
||||
#define rSleep 0xee0
|
||||
#define rPMPD_ANAEN 0xeec
|
||||
|
||||
|
||||
/* 2. Page8(0x800) */
|
||||
#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
|
||||
#define bJapanMode 0x2
|
||||
#define bCCKTxSC 0x30
|
||||
#define bCCKEn 0x1000000
|
||||
#define bOFDMEn 0x2000000
|
||||
#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
|
||||
#define bXCTxAGC 0xf000
|
||||
#define bXDTxAGC 0xf0000
|
||||
|
||||
/* 4. PageA(0xA00) */
|
||||
#define bCCKBBMode 0x3 /* Useless */
|
||||
#define bCCKTxPowerSaving 0x80
|
||||
#define bCCKRxPowerSaving 0x40
|
||||
|
||||
#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
|
||||
|
||||
#define bCCKScramble 0x8 /* Useless */
|
||||
#define bCCKAntDiversity 0x8000
|
||||
#define bCCKCarrierRecovery 0x4000
|
||||
#define bCCKTxRate 0x3000
|
||||
#define bCCKDCCancel 0x0800
|
||||
#define bCCKISICancel 0x0400
|
||||
#define bCCKMatchFilter 0x0200
|
||||
#define bCCKEqualizer 0x0100
|
||||
#define bCCKPreambleDetect 0x800000
|
||||
#define bCCKFastFalseCCA 0x400000
|
||||
#define bCCKChEstStart 0x300000
|
||||
#define bCCKCCACount 0x080000
|
||||
#define bCCKcs_lim 0x070000
|
||||
#define bCCKBistMode 0x80000000
|
||||
#define bCCKCCAMask 0x40000000
|
||||
#define bCCKTxDACPhase 0x4
|
||||
#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
|
||||
#define bCCKr_cp_mode0 0x0100
|
||||
#define bCCKTxDCOffset 0xf0
|
||||
#define bCCKRxDCOffset 0xf
|
||||
#define bCCKCCAMode 0xc000
|
||||
#define bCCKFalseCS_lim 0x3f00
|
||||
#define bCCKCS_ratio 0xc00000
|
||||
#define bCCKCorgBit_sel 0x300000
|
||||
#define bCCKPD_lim 0x0f0000
|
||||
#define bCCKNewCCA 0x80000000
|
||||
#define bCCKRxHPofIG 0x8000
|
||||
#define bCCKRxIG 0x7f00
|
||||
#define bCCKLNAPolarity 0x800000
|
||||
#define bCCKRx1stGain 0x7f0000
|
||||
#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
|
||||
#define bCCKRxAGCSatLevel 0x1f000000
|
||||
#define bCCKRxAGCSatCount 0xe0
|
||||
#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
|
||||
#define bCCKFixedRxAGC 0x8000
|
||||
/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
|
||||
#define bCCKAntennaPolarity 0x2000
|
||||
#define bCCKTxFilterType 0x0c00
|
||||
#define bCCKRxAGCReportType 0x0300
|
||||
#define bCCKRxDAGCEn 0x80000000
|
||||
#define bCCKRxDAGCPeriod 0x20000000
|
||||
#define bCCKRxDAGCSatLevel 0x1f000000
|
||||
#define bCCKTimingRecovery 0x800000
|
||||
#define bCCKTxC0 0x3f0000
|
||||
#define bCCKTxC1 0x3f000000
|
||||
#define bCCKTxC2 0x3f
|
||||
#define bCCKTxC3 0x3f00
|
||||
#define bCCKTxC4 0x3f0000
|
||||
#define bCCKTxC5 0x3f000000
|
||||
#define bCCKTxC6 0x3f
|
||||
#define bCCKTxC7 0x3f00
|
||||
#define bCCKDebugPort 0xff0000
|
||||
#define bCCKDACDebug 0x0f000000
|
||||
#define bCCKFalseAlarmEnable 0x8000
|
||||
#define bCCKFalseAlarmRead 0x4000
|
||||
#define bCCKTRSSI 0x7f
|
||||
#define bCCKRxAGCReport 0xfe
|
||||
#define bCCKRxReport_AntSel 0x80000000
|
||||
#define bCCKRxReport_MFOff 0x40000000
|
||||
#define bCCKRxRxReport_SQLoss 0x20000000
|
||||
#define bCCKRxReport_Pktloss 0x10000000
|
||||
#define bCCKRxReport_Lockedbit 0x08000000
|
||||
#define bCCKRxReport_RateError 0x04000000
|
||||
#define bCCKRxReport_RxRate 0x03000000
|
||||
#define bCCKRxFACounterLower 0xff
|
||||
#define bCCKRxFACounterUpper 0xff000000
|
||||
#define bCCKRxHPAGCStart 0xe000
|
||||
#define bCCKRxHPAGCFinal 0x1c00
|
||||
#define bCCKRxFalseAlarmEnable 0x8000
|
||||
#define bCCKFACounterFreeze 0x4000
|
||||
#define bCCKTxPathSel 0x10000000
|
||||
#define bCCKDefaultRxPath 0xc000000
|
||||
#define bCCKOptionRxPath 0x3000000
|
||||
|
||||
#define RF_T_METER_88E 0x42
|
||||
|
||||
/* 6. PageE(0xE00) */
|
||||
#define bSTBCEn 0x4 /* Useless */
|
||||
#define bAntennaMapping 0x10
|
||||
#define bNss 0x20
|
||||
#define bCFOAntSumD 0x200
|
||||
#define bPHYCounterReset 0x8000000
|
||||
#define bCFOReportGet 0x4000000
|
||||
#define bOFDMContinueTx 0x10000000
|
||||
#define bOFDMSingleCarrier 0x20000000
|
||||
#define bOFDMSingleTone 0x40000000
|
||||
|
||||
|
||||
/*
|
||||
* Other Definition
|
||||
* */
|
||||
|
||||
#define bEnable 0x1 /* Useless */
|
||||
#define bDisable 0x0
|
||||
|
||||
/* byte endable for srwrite */
|
||||
#define bByte0 0x1 /* Useless */
|
||||
#define bByte1 0x2
|
||||
#define bByte2 0x4
|
||||
#define bByte3 0x8
|
||||
#define bWord0 0x3
|
||||
#define bWord1 0xc
|
||||
#define bDWord 0xf
|
||||
|
||||
/* for PutRegsetting & GetRegSetting BitMask */
|
||||
#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
|
||||
#define bMaskByte1 0xff00
|
||||
#define bMaskByte2 0xff0000
|
||||
#define bMaskByte3 0xff000000
|
||||
#define bMaskHWord 0xffff0000
|
||||
#define bMaskLWord 0x0000ffff
|
||||
#define bMaskDWord 0xffffffff
|
||||
#define bMaskH3Bytes 0xffffff00
|
||||
#define bMask12Bits 0xfff
|
||||
#define bMaskH4Bits 0xf0000000
|
||||
#define bMaskOFDM_D 0xffc00000
|
||||
#define bMaskCCK 0x3f3f3f3f
|
||||
#define bMask7bits 0x7f
|
||||
#define bMaskByte2HighNibble 0x00f00000
|
||||
#define bMaskByte3LowNibble 0x0f000000
|
||||
#define bMaskL3Bytes 0x00ffffff
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
#ifndef __HAL8814PWRSEQ_H__
|
||||
#define __HAL8814PWRSEQ_H__
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WB-110628-DZ-RTL8195 (Jaguar) Power Architecture-R04.pdf
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS 16
|
||||
#define RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS 20
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS 17
|
||||
#define RTL8814A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS 17
|
||||
#define RTL8814A_TRANS_PDN_TO_CARDEMU_STEPS 16
|
||||
#define RTL8814A_TRANS_ACT_TO_LPS_STEPS 20
|
||||
#define RTL8814A_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8814A_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x002B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* ??0x28[24]=1, enable pll phase select*/ \
|
||||
{0x0015, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT3 | BIT2 | BIT1), (BIT3 | BIT2 | BIT1)},/* 0x14[11:9]=3'b111, OCP current threshold = 1.5A */ \
|
||||
{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0E, 0x08},/* 0x2C[11:9]=3'b100, select lpf R3 */ \
|
||||
{0x002D, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x70, 0x50},/* 0x2C[14:12]=3'b101, select lpf Rs*/ \
|
||||
{0x007B, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x78[30]=1'b1, SDM order select*/ \
|
||||
/*{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, */ /* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
|
||||
{0x00F0, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* */ \
|
||||
{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x30, 0x20},/* */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/
|
||||
|
||||
#define RTL8814A_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
|
||||
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \
|
||||
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0}, /*0x8[1] = 0 ANA clk = 500k */ \
|
||||
/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 | BIT1, 0},*/ /* 0x02[1:0] = 0 reset BB */ \
|
||||
{0x0066, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /*0x66[7]=0, disable ckreq for gpio7 output SUS */ \
|
||||
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x41[4]=0, disable sic for gpio7 output SUS */ \
|
||||
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /*0x42[1]=0, disable ckout for gpio7 output SUS */ \
|
||||
{0x004e, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x4E[5]=1, disable LED2 for gpio7 output SUS */ \
|
||||
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x41[0]=0, disable uart for gpio7 output SUS */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0c},\
|
||||
{0x0061, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x0E},\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x0F, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x14[13] = 1 turn on ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x14[14] =1 trun on ZCD */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
|
||||
{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend */
|
||||
|
||||
#define RTL8814A_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x14[14] =0 trun off ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x14[13] = 0 turn off ZCD */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
|
||||
/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x94}, //0x93 = 0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
|
||||
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 3081*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x01}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
|
||||
{0x0081, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x30}, /*0x80 = 05h if reload fw, fill the default value of host_CPU handshake field*/ \
|
||||
/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc},*/ \
|
||||
/*{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC},*/ \
|
||||
/*{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07},*/ /* gpio11 input mode, gpio10~8 output mode */ \
|
||||
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
|
||||
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/* 0x15[6] =1 trun on ZCD output */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*0x15[5] = 1 turn on ZCD */ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*0x12[6] = 0 force PFM mode */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*0x8[1] = 0 ANA clk = 500k */ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8814A */ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x020[1]=0 , disable RFC_1 control REG_RF_CTRL_8814A */ \
|
||||
{0x0021, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x021[1]=0 , disable RFC_2 control REG_RF_CTRL_8814A */ \
|
||||
{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* 0x076[1]=0 , disable RFC_3 control REG_OPT_CTRL_8814A +2 */ \
|
||||
{0x0091, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xA0, 0xA0}, /* 0x91[7]=1 0x91[5]=1 , disable sps, ldo sleep mode */ \
|
||||
{0x0070, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /* 0x70[3]=1 enable mainbias polling */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 1 enable WL suspend*/
|
||||
|
||||
#define RTL8814A_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, BIT6},/*0x12[6] = 1 force PWM mode */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0},/*0x15[5] = 0 turn off ZCD */ \
|
||||
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/* 0x15[6] =0 trun off ZCD output */ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
|
||||
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, /* gpio11 input mode, gpio10~8 input mode */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 0, enable WL suspend*/ \
|
||||
/*{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},*/ /*0x03[2] = 1, enable 3081*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/ \
|
||||
{0x0071, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*0x70[10] = 0, CPHY_MBIAS_EN disable*/
|
||||
|
||||
|
||||
#define RTL8814A_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8814A_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8814A_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
|
||||
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
|
||||
|
||||
|
||||
#define RTL8814A_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /* Delay*/ \
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /* Polling 0x109[7]=0 TSF in 40M*/ \
|
||||
/*{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, */ /*. ??0x29[7:6] = 2b'00 enable BB clock*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
|
||||
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
|
||||
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8814A_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS + RTL8814A_TRANS_END_STEPS];
|
||||
|
||||
#endif /* __HAL8814PWRSEQ_H__ */
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef REALTEK_POWER_SEQUENCE_8821
|
||||
#define REALTEK_POWER_SEQUENCE_8821
|
||||
|
||||
#include "HalPwrSeqCmd.h"
|
||||
|
||||
/*
|
||||
Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
|
||||
There are 6 HW Power States:
|
||||
0: POFF--Power Off
|
||||
1: PDN--Power Down
|
||||
2: CARDEMU--Card Emulation
|
||||
3: ACT--Active Mode
|
||||
4: LPS--Low Power State
|
||||
5: SUS--Suspend
|
||||
|
||||
The transision from different states are defined below
|
||||
TRANS_CARDEMU_TO_ACT
|
||||
TRANS_ACT_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_SUS
|
||||
TRANS_SUS_TO_CARDEMU
|
||||
TRANS_CARDEMU_TO_PDN
|
||||
TRANS_ACT_TO_LPS
|
||||
TRANS_LPS_TO_ACT
|
||||
|
||||
TRANS_END
|
||||
*/
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
|
||||
#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
|
||||
#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
|
||||
#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
|
||||
#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
|
||||
#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
|
||||
#define RTL8821A_TRANS_END_STEPS 1
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
|
||||
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3 | BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
|
||||
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4 | BIT3), 0},/* disable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
|
||||
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
|
||||
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
|
||||
{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
|
||||
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
|
||||
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
|
||||
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
|
||||
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
|
||||
{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
|
||||
{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
|
||||
{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP新增對於0x2C的控制權，須把0x10[6]設為1才能讓WLAN控制 */ \
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
|
||||
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
|
||||
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4 | BIT3, (BIT4 | BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3 | BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8821A_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07 = 0x20 , SOP option to disable BG/MB*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8821A_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
#define RTL8821A_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8821A_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 | BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8821A_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, PWR_CMD_END, 0, 0},
|
||||
|
||||
|
||||
extern WLAN_PWR_CFG rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_card_enable_flow[RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS + RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
extern WLAN_PWR_CFG rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS + RTL8821A_TRANS_END_STEPS];
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALPWRSEQCMD_H__
|
||||
#define __HALPWRSEQCMD_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cmd: 4 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_CMD_READ 0x00
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the read value
|
||||
* value: N/A, left by 0
|
||||
* note: dirver shall implement this function by read & msk */
|
||||
|
||||
#define PWR_CMD_WRITE 0x01
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the write bits
|
||||
* value: write value
|
||||
* note: driver shall implement this cmd by read & msk after write */
|
||||
|
||||
#define PWR_CMD_POLLING 0x02
|
||||
/* offset: the read register offset
|
||||
* msk: the mask of the polled value
|
||||
* value: the value to be polled, masked by the msd field.
|
||||
* note: driver shall implement this cmd by
|
||||
* do {
|
||||
* if( (Read(offset) & msk) == (value & msk) )
|
||||
* break;
|
||||
* } while(not timeout); */
|
||||
|
||||
#define PWR_CMD_DELAY 0x03
|
||||
/* offset: the value to delay
|
||||
* msk: N/A
|
||||
* value: the unit of delay, 0: us, 1: ms */
|
||||
|
||||
#define PWR_CMD_END 0x04
|
||||
/* offset: N/A
|
||||
* msk: N/A
|
||||
* value: N/A */
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of base: 4 bits
|
||||
*---------------------------------------------
|
||||
* define the base address of each block */
|
||||
#define PWR_BASEADDR_MAC 0x00
|
||||
#define PWR_BASEADDR_USB 0x01
|
||||
#define PWR_BASEADDR_PCIE 0x02
|
||||
#define PWR_BASEADDR_SDIO 0x03
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of interface_msk: 4 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_INTF_SDIO_MSK BIT(0)
|
||||
#define PWR_INTF_USB_MSK BIT(1)
|
||||
#define PWR_INTF_PCI_MSK BIT(2)
|
||||
#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of fab_msk: 4 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_FAB_TSMC_MSK BIT(0)
|
||||
#define PWR_FAB_UMC_MSK BIT(1)
|
||||
#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cut_msk: 8 bits
|
||||
*---------------------------------------------*/
|
||||
#define PWR_CUT_TESTCHIP_MSK BIT(0)
|
||||
#define PWR_CUT_A_MSK BIT(1)
|
||||
#define PWR_CUT_B_MSK BIT(2)
|
||||
#define PWR_CUT_C_MSK BIT(3)
|
||||
#define PWR_CUT_D_MSK BIT(4)
|
||||
#define PWR_CUT_E_MSK BIT(5)
|
||||
#define PWR_CUT_F_MSK BIT(6)
|
||||
#define PWR_CUT_G_MSK BIT(7)
|
||||
#define PWR_CUT_ALL_MSK 0xFF
|
||||
|
||||
|
||||
typedef enum _PWRSEQ_CMD_DELAY_UNIT_ {
|
||||
PWRSEQ_DELAY_US,
|
||||
PWRSEQ_DELAY_MS,
|
||||
} PWRSEQ_DELAY_UNIT;
|
||||
|
||||
typedef struct _WL_PWR_CFG_ {
|
||||
u16 offset;
|
||||
u8 cut_msk;
|
||||
u8 fab_msk:4;
|
||||
u8 interface_msk:4;
|
||||
u8 base:4;
|
||||
u8 cmd:4;
|
||||
u8 msk;
|
||||
u8 value;
|
||||
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
|
||||
|
||||
|
||||
#define GET_PWR_CFG_OFFSET(__PWR_CMD) ((__PWR_CMD).offset)
|
||||
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) ((__PWR_CMD).cut_msk)
|
||||
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) ((__PWR_CMD).fab_msk)
|
||||
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) ((__PWR_CMD).interface_msk)
|
||||
#define GET_PWR_CFG_BASE(__PWR_CMD) ((__PWR_CMD).base)
|
||||
#define GET_PWR_CFG_CMD(__PWR_CMD) ((__PWR_CMD).cmd)
|
||||
#define GET_PWR_CFG_MASK(__PWR_CMD) ((__PWR_CMD).msk)
|
||||
#define GET_PWR_CFG_VALUE(__PWR_CMD) ((__PWR_CMD).value)
|
||||
|
||||
|
||||
/* ********************************************************************************
|
||||
* Prototype of protected function.
|
||||
* ******************************************************************************** */
|
||||
u8 HalPwrSeqCmdParsing(
|
||||
PADAPTER padapter,
|
||||
u8 CutVersion,
|
||||
u8 FabVersion,
|
||||
u8 InterfaceType,
|
||||
WLAN_PWR_CFG PwrCfgCmd[]);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_VERSION_DEF_H__
|
||||
#define __HAL_VERSION_DEF_H__
|
||||
|
||||
#define TRUE _TRUE
|
||||
#define FALSE _FALSE
|
||||
|
||||
/* HAL_IC_TYPE_E */
|
||||
typedef enum tag_HAL_IC_Type_Definition {
|
||||
CHIP_8192S = 0,
|
||||
CHIP_8188C = 1,
|
||||
CHIP_8192C = 2,
|
||||
CHIP_8192D = 3,
|
||||
CHIP_8723A = 4,
|
||||
CHIP_8188E = 5,
|
||||
CHIP_8812 = 6,
|
||||
CHIP_8821 = 7,
|
||||
CHIP_8723B = 8,
|
||||
CHIP_8192E = 9,
|
||||
CHIP_8814A = 10,
|
||||
CHIP_8703B = 11,
|
||||
CHIP_8188F = 12,
|
||||
CHIP_8822B = 13,
|
||||
CHIP_8723D = 14,
|
||||
CHIP_8821C = 15,
|
||||
CHIP_8710B = 16,
|
||||
CHIP_8192F = 17,
|
||||
CHIP_8188GTV = 18,
|
||||
CHIP_8822C = 19,
|
||||
CHIP_8814B = 20,
|
||||
CHIP_8723F = 21,
|
||||
} HAL_IC_TYPE_E;
|
||||
|
||||
/* HAL_CHIP_TYPE_E */
|
||||
typedef enum tag_HAL_CHIP_Type_Definition {
|
||||
TEST_CHIP = 0,
|
||||
NORMAL_CHIP = 1,
|
||||
FPGA = 2,
|
||||
} HAL_CHIP_TYPE_E;
|
||||
|
||||
/* HAL_CUT_VERSION_E */
|
||||
typedef enum tag_HAL_Cut_Version_Definition {
|
||||
A_CUT_VERSION = 0,
|
||||
B_CUT_VERSION = 1,
|
||||
C_CUT_VERSION = 2,
|
||||
D_CUT_VERSION = 3,
|
||||
E_CUT_VERSION = 4,
|
||||
F_CUT_VERSION = 5,
|
||||
G_CUT_VERSION = 6,
|
||||
H_CUT_VERSION = 7,
|
||||
I_CUT_VERSION = 8,
|
||||
J_CUT_VERSION = 9,
|
||||
K_CUT_VERSION = 10,
|
||||
} HAL_CUT_VERSION_E;
|
||||
|
||||
/* HAL_Manufacturer */
|
||||
typedef enum tag_HAL_Manufacturer_Version_Definition {
|
||||
CHIP_VENDOR_TSMC = 0,
|
||||
CHIP_VENDOR_UMC = 1,
|
||||
CHIP_VENDOR_SMIC = 2,
|
||||
} HAL_VENDOR_E;
|
||||
|
||||
typedef enum tag_HAL_RF_Type_Definition {
|
||||
RF_TYPE_1T1R = 0,
|
||||
RF_TYPE_1T2R = 1,
|
||||
RF_TYPE_2T2R = 2,
|
||||
RF_TYPE_2T3R = 3,
|
||||
RF_TYPE_2T4R = 4,
|
||||
RF_TYPE_3T3R = 5,
|
||||
RF_TYPE_3T4R = 6,
|
||||
RF_TYPE_4T4R = 7,
|
||||
} HAL_RF_TYPE_E;
|
||||
|
||||
typedef struct tag_HAL_VERSION {
|
||||
HAL_IC_TYPE_E ICType;
|
||||
HAL_CHIP_TYPE_E ChipType;
|
||||
HAL_CUT_VERSION_E CUTVersion;
|
||||
HAL_VENDOR_E VendorType;
|
||||
HAL_RF_TYPE_E RFType;
|
||||
u8 ROMVer;
|
||||
} HAL_VERSION, *PHAL_VERSION;
|
||||
|
||||
/* VERSION_8192C VersionID;
|
||||
* HAL_VERSION VersionID; */
|
||||
|
||||
/* Get element */
|
||||
#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType))
|
||||
#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType))
|
||||
#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType))
|
||||
#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType))
|
||||
#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion))
|
||||
#define GET_CVID_ROM_VERSION(version) ((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK)
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* Common Macro. --
|
||||
* ----------------------------------------------------------------------------
|
||||
* HAL_VERSION VersionID */
|
||||
|
||||
/* HAL_IC_TYPE_E */
|
||||
#if 0
|
||||
#define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C) || (GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? TRUE : FALSE)
|
||||
#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? TRUE : FALSE)
|
||||
#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? TRUE : FALSE)
|
||||
#endif
|
||||
|
||||
#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE)
|
||||
#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE)
|
||||
#define IS_8188GTV(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188GTV) ? TRUE : FALSE)
|
||||
#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE)
|
||||
#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE)
|
||||
#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE)
|
||||
#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE)
|
||||
#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE)
|
||||
#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE)
|
||||
#define IS_8822B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE)
|
||||
#define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE)
|
||||
#define IS_8723D_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE)
|
||||
#define IS_8710B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8710B) ? TRUE : FALSE)
|
||||
#define IS_8822C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822C) ? TRUE : FALSE)
|
||||
#define IS_8814B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814B) ? TRUE : FALSE)
|
||||
#define IS_8723F_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723F) ? TRUE : FALSE)
|
||||
|
||||
#define IS_8192F_SERIES(version)\
|
||||
((GET_CVID_IC_TYPE(version) == CHIP_8192F) ? TRUE : FALSE)
|
||||
/* HAL_CHIP_TYPE_E */
|
||||
#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE)
|
||||
#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE)
|
||||
|
||||
/* HAL_CUT_VERSION_E */
|
||||
#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE)
|
||||
#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE)
|
||||
|
||||
/* HAL_VENDOR_E */
|
||||
#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE)
|
||||
#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE)
|
||||
#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE)
|
||||
|
||||
/* HAL_RF_TYPE_E */
|
||||
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE)
|
||||
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE)
|
||||
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE)
|
||||
#define IS_2T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T3R) ? TRUE : FALSE)
|
||||
#define IS_2T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T4R) ? TRUE : FALSE)
|
||||
#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE)
|
||||
#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE)
|
||||
#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE)
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* Chip version Macro. --
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#if 0
|
||||
#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? TRUE : FALSE)
|
||||
|
||||
#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE)
|
||||
#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
|
||||
#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
|
||||
#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) : FALSE)
|
||||
|
||||
#define IS_NORMAL_CHIP92D(version) ((IS_92D(version)) ? ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_92D_C_CUT(version) ((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_92D_D_CUT(version) ((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_92D_E_CUT(version) ((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE)
|
||||
#endif
|
||||
#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE)
|
||||
|
||||
#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE)
|
||||
#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/* ***** temporarily flag ******* */
|
||||
#define CONFIG_SINGLE_IMG
|
||||
|
||||
/* #define CONFIG_DISABLE_ODM */
|
||||
/* for FPGA VERIFICATION config */
|
||||
#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0
|
||||
|
||||
/* ***** temporarily flag ******* */
|
||||
/*
|
||||
* Public General Config
|
||||
*/
|
||||
#define AUTOCONF_INCLUDED
|
||||
#define RTL871X_MODULE_NAME "88EU"
|
||||
#define DRV_NAME "rtl8188eu"
|
||||
|
||||
#define CONFIG_USB_HCI
|
||||
|
||||
#define PLATFORM_LINUX
|
||||
|
||||
/* #define CONFIG_IOCTL_CFG80211 */
|
||||
|
||||
#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X)
|
||||
#ifndef CONFIG_IOCTL_CFG80211
|
||||
#define CONFIG_IOCTL_CFG80211
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IOCTL_CFG80211
|
||||
/* #define RTW_USE_CFG80211_STA_EVENT */ /* Indecate new sta asoc through cfg80211_new_sta */
|
||||
#define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER
|
||||
/* #define CONFIG_DEBUG_CFG80211 */
|
||||
/* #define CONFIG_DRV_ISSUE_PROV_REQ */ /* IOT FOR S2 */
|
||||
#define CONFIG_SET_SCAN_DENY_TIMER
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal General Config
|
||||
*/
|
||||
|
||||
/* #define CONFIG_H2CLBK */
|
||||
|
||||
#define CONFIG_EMBEDDED_FWIMG
|
||||
|
||||
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
#define LOAD_FW_HEADER_FROM_DRIVER
|
||||
#endif
|
||||
/* #define CONFIG_FILE_FWIMG */
|
||||
|
||||
#define CONFIG_XMIT_ACK
|
||||
#ifdef CONFIG_XMIT_ACK
|
||||
#define CONFIG_ACTIVE_KEEP_ALIVE_CHECK
|
||||
#endif
|
||||
#define CONFIG_80211N_HT
|
||||
|
||||
#define CONFIG_RECV_REORDERING_CTRL
|
||||
|
||||
#define CONFIG_SUPPORT_USB_INT
|
||||
#ifdef CONFIG_SUPPORT_USB_INT
|
||||
/* #define CONFIG_USB_INTERRUPT_IN_PIPE */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POWER_SAVING
|
||||
#define CONFIG_IPS
|
||||
#ifdef CONFIG_IPS
|
||||
/* #define CONFIG_IPS_LEVEL_2 */ /* enable this to set default IPS mode to IPS_LEVEL_2 */
|
||||
#endif
|
||||
#define SUPPORT_HW_RFOFF_DETECTED
|
||||
|
||||
#define CONFIG_LPS
|
||||
#if defined(CONFIG_LPS) && defined(CONFIG_SUPPORT_USB_INT)
|
||||
|
||||
|
||||
/* #define CONFIG_LPS_LCLK */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPS_LCLK
|
||||
/* #define CONFIG_XMIT_THREAD_MODE */
|
||||
#endif
|
||||
#endif /* CONFIG_POWER_SAVING */
|
||||
|
||||
/*#define CONFIG_ANTENNA_DIVERSITY*/
|
||||
|
||||
|
||||
|
||||
/* #define CONFIG_CONCURRENT_MODE */
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
#define CONFIG_RUNTIME_PORT_SWITCH
|
||||
|
||||
#define CONFIG_TSF_RESET_OFFLOAD /* For 2 PORT TSF SYNC. */
|
||||
#endif
|
||||
|
||||
#define CONFIG_IOL
|
||||
/* #else */ /* #ifndef CONFIG_MP_INCLUDED */
|
||||
|
||||
/* #endif */ /* #ifndef CONFIG_MP_INCLUDED */
|
||||
|
||||
#ifdef CONFIG_AP_MODE
|
||||
|
||||
/* #define CONFIG_INTERRUPT_BASED_TXBCN */ /* Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs */
|
||||
#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN)
|
||||
#undef CONFIG_INTERRUPT_BASED_TXBCN
|
||||
#endif
|
||||
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
|
||||
/* #define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
|
||||
#define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
|
||||
#endif
|
||||
|
||||
#define CONFIG_NATIVEAP_MLME
|
||||
#ifndef CONFIG_NATIVEAP_MLME
|
||||
#define CONFIG_HOSTAPD_MLME
|
||||
#endif
|
||||
#define CONFIG_FIND_BEST_CHANNEL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_P2P
|
||||
/* The CONFIG_WFD is for supporting the Wi-Fi display */
|
||||
#define CONFIG_WFD
|
||||
|
||||
#define CONFIG_P2P_REMOVE_GROUP_INFO
|
||||
|
||||
/* #define CONFIG_DBG_P2P */
|
||||
|
||||
#define CONFIG_P2P_PS
|
||||
#define CONFIG_P2P_OP_CHK_SOCIAL_CH
|
||||
#define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */
|
||||
/*#define CONFIG_P2P_INVITE_IOT*/
|
||||
#endif
|
||||
|
||||
/* Added by Kurt 20110511 */
|
||||
#ifdef CONFIG_TDLS
|
||||
#define CONFIG_TDLS_DRIVER_SETUP
|
||||
/* #ifndef CONFIG_WFD */
|
||||
/* #define CONFIG_WFD */
|
||||
/* #endif */
|
||||
/* #define CONFIG_TDLS_AUTOSETUP */
|
||||
#define CONFIG_TDLS_AUTOCHECKALIVE
|
||||
/* #define CONFIG_TDLS_CH_SW */ /* Enable this flag only when we confirm that TDLS CH SW is supported in FW */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_SKB_COPY /* for amsdu */
|
||||
|
||||
#define CONFIG_RTW_LED
|
||||
#ifdef CONFIG_RTW_LED
|
||||
#define CONFIG_RTW_SW_LED
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* #define CONFIG_RTW_LED_HANDLED_BY_CMD_THREAD */
|
||||
#endif
|
||||
#endif /* CONFIG_RTW_LED */
|
||||
|
||||
#ifdef CONFIG_IOL
|
||||
#define CONFIG_IOL_NEW_GENERATION
|
||||
#define CONFIG_IOL_READ_EFUSE_MAP
|
||||
/* #define DBG_IOL_READ_EFUSE_MAP */
|
||||
/* #define CONFIG_IOL_LLT */
|
||||
#define CONFIG_IOL_EFUSE_PATCH
|
||||
/* #define CONFIG_IOL_IOREG_CFG */
|
||||
/* #define CONFIG_IOL_IOREG_CFG_DBG */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_GLOBAL_UI_PID
|
||||
|
||||
/* #define CONFIG_ADAPTOR_INFO_CACHING_FILE */ /* now just applied on 8192cu only, should make it general... */
|
||||
/* #define CONFIG_RESUME_IN_WORKQUEUE */
|
||||
/* #define CONFIG_SET_SCAN_DENY_TIMER */
|
||||
#define CONFIG_LONG_DELAY_ISSUE
|
||||
#define CONFIG_NEW_SIGNAL_STAT_PROCESS
|
||||
/* #define CONFIG_SIGNAL_DISPLAY_DBM */ /* display RX signal with dbm */
|
||||
#ifdef CONFIG_SIGNAL_DISPLAY_DBM
|
||||
/* #define CONFIG_BACKGROUND_NOISE_MONITOR */
|
||||
#endif
|
||||
#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */
|
||||
|
||||
/*
|
||||
* Interface Related Config
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
#define CONFIG_USB_TX_AGGREGATION
|
||||
#define CONFIG_USB_RX_AGGREGATION
|
||||
#endif
|
||||
|
||||
/* #define CONFIG_REDUCE_USB_TX_INT */ /* Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms. */
|
||||
/* #define CONFIG_EASY_REPLACEMENT */
|
||||
|
||||
/*
|
||||
* CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now!
|
||||
*/
|
||||
/* #define CONFIG_USE_USB_BUFFER_ALLOC_TX */ /* Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms. */
|
||||
/* #define CONFIG_USE_USB_BUFFER_ALLOC_RX */ /* For RX path */
|
||||
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
|
||||
|
||||
#else
|
||||
#define CONFIG_PREALLOC_RECV_SKB
|
||||
#ifdef CONFIG_PREALLOC_RECV_SKB
|
||||
#define CONFIG_FIX_NR_BULKIN_BUFFER /* only use PREALLOC_RECV_SKB buffer, don't alloc skb at runtime */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB VENDOR REQ BUFFER ALLOCATION METHOD
|
||||
* if not set we'll use function local variable (stack memory)
|
||||
*/
|
||||
/* #define CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE */
|
||||
#define CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
|
||||
|
||||
#define CONFIG_USB_VENDOR_REQ_MUTEX
|
||||
#define CONFIG_VENDOR_REQ_RETRY
|
||||
|
||||
/* #define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */
|
||||
|
||||
|
||||
/*
|
||||
* HAL Related Config
|
||||
*/
|
||||
|
||||
#define RTL8188E_RX_PACKET_INCLUDE_CRC 0
|
||||
#define CONFIG_RX_PACKET_APPEND_FCS
|
||||
|
||||
#define SUPPORTED_BLOCK_IO
|
||||
|
||||
|
||||
/* #define CONFIG_ONLY_ONE_OUT_EP_TO_LOW 0 */
|
||||
|
||||
#define CONFIG_OUT_EP_WIFI_MODE 0
|
||||
|
||||
#define ENABLE_USB_DROP_INCORRECT_OUT
|
||||
|
||||
|
||||
#define DISABLE_BB_RF 0
|
||||
|
||||
/* #define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0 */
|
||||
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
#define MP_DRIVER 1
|
||||
#define CONFIG_MP_IWPRIV_SUPPORT
|
||||
/* #undef CONFIG_USB_TX_AGGREGATION */
|
||||
/* #undef CONFIG_USB_RX_AGGREGATION */
|
||||
#else
|
||||
#define MP_DRIVER 0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Platform Related Config
|
||||
*/
|
||||
#if defined(CONFIG_PLATFORM_ACTIONS_ATM702X)
|
||||
#ifdef CONFIG_USB_TX_AGGREGATION
|
||||
#undef CONFIG_USB_TX_AGGREGATION
|
||||
#endif
|
||||
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX
|
||||
#define CONFIG_USE_USB_BUFFER_ALLOC_TX
|
||||
#endif
|
||||
#ifndef CONFIG_USE_USB_BUFFER_ALLOC_RX
|
||||
#define CONFIG_USE_USB_BUFFER_ALLOC_RX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_USB_TX_AGGREGATION
|
||||
/* #define CONFIG_TX_EARLY_MODE */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TX_EARLY_MODE
|
||||
#define RTL8188E_EARLY_MODE_PKT_NUM_10 0
|
||||
#endif
|
||||
|
||||
/*#define CONFIG_RF_POWER_TRIM */
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
#ifndef WAKEUP_GPIO_IDX
|
||||
#define WAKEUP_GPIO_IDX 7
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Debug Related Config
|
||||
*/
|
||||
#define DBG 1
|
||||
|
||||
#define DBG_CONFIG_ERROR_DETECT
|
||||
/* #define DBG_CONFIG_ERROR_DETECT_INT */
|
||||
#define DBG_CONFIG_ERROR_RESET
|
||||
|
||||
/* #define DBG_IO */
|
||||
/* #define DBG_DELAY_OS */
|
||||
/* #define DBG_MEM_ALLOC */
|
||||
/* #define DBG_IOCTL */
|
||||
|
||||
/* #define DBG_TX */
|
||||
/* #define DBG_XMIT_BUF */
|
||||
/* #define DBG_XMIT_BUF_EXT */
|
||||
/* #define DBG_TX_DROP_FRAME */
|
||||
|
||||
/* #define DBG_RX_DROP_FRAME */
|
||||
/* #define DBG_RX_SEQ */
|
||||
/* #define DBG_RX_SIGNAL_DISPLAY_PROCESSING */
|
||||
/* #define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap" */
|
||||
|
||||
|
||||
|
||||
/* #define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE */
|
||||
/* #define DBG_ROAMING_TEST */
|
||||
|
||||
/* #define DBG_HAL_INIT_PROFILING */
|
||||
|
||||
/* #define DBG_MEMORY_LEAK */
|
||||
|
||||
/* TX use 1 urb */
|
||||
/* #define CONFIG_SINGLE_XMIT_BUF */
|
||||
/* RX use 1 urb */
|
||||
/* #define CONFIG_SINGLE_RECV_BUF */
|
||||
#define DBG_RX_DFRAME_RAW_DATA
|
||||
|
|
@ -0,0 +1,357 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __BASIC_TYPES_H__
|
||||
#define __BASIC_TYPES_H__
|
||||
|
||||
|
||||
#define SUCCESS 0
|
||||
#define FAIL (-1)
|
||||
|
||||
#ifndef TRUE
|
||||
#define _TRUE 1
|
||||
#else
|
||||
#define _TRUE TRUE
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define _FALSE 0
|
||||
#else
|
||||
#define _FALSE FALSE
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_WINDOWS
|
||||
|
||||
typedef signed char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef signed short s16;
|
||||
typedef unsigned short u16;
|
||||
|
||||
typedef signed long s32;
|
||||
typedef unsigned long u32;
|
||||
|
||||
typedef unsigned int uint;
|
||||
typedef signed int sint;
|
||||
|
||||
|
||||
typedef signed long long s64;
|
||||
typedef unsigned long long u64;
|
||||
|
||||
#ifdef NDIS50_MINIPORT
|
||||
|
||||
#define NDIS_MAJOR_VERSION 5
|
||||
#define NDIS_MINOR_VERSION 0
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef NDIS51_MINIPORT
|
||||
|
||||
#define NDIS_MAJOR_VERSION 5
|
||||
#define NDIS_MINOR_VERSION 1
|
||||
|
||||
#endif
|
||||
|
||||
typedef NDIS_PROC proc_t;
|
||||
|
||||
typedef LONG atomic_t;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <linux/version.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/utsname.h>
|
||||
|
||||
typedef signed int sint;
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19))
|
||||
typedef _Bool bool;
|
||||
|
||||
enum {
|
||||
false = 0,
|
||||
true = 1
|
||||
};
|
||||
#endif
|
||||
|
||||
typedef void (*proc_t)(void *);
|
||||
|
||||
typedef __kernel_size_t SIZE_T;
|
||||
typedef __kernel_ssize_t SSIZE_T;
|
||||
#define FIELD_OFFSET(s, field) ((SSIZE_T)&((s *)(0))->field)
|
||||
|
||||
#define NDIS_OID uint
|
||||
#endif /*PLATFORM_LINUX*/
|
||||
|
||||
|
||||
#ifdef PLATFORM_FREEBSD
|
||||
|
||||
typedef signed char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef signed short s16;
|
||||
typedef unsigned short u16;
|
||||
|
||||
typedef signed int s32;
|
||||
typedef unsigned int u32;
|
||||
|
||||
typedef unsigned int uint;
|
||||
typedef signed int sint;
|
||||
typedef long atomic_t;
|
||||
|
||||
typedef signed long long s64;
|
||||
typedef unsigned long long u64;
|
||||
|
||||
typedef u32 dma_addr_t;
|
||||
|
||||
typedef void (*proc_t)(void *);
|
||||
|
||||
typedef unsigned int __kernel_size_t;
|
||||
typedef int __kernel_ssize_t;
|
||||
|
||||
typedef __kernel_size_t SIZE_T;
|
||||
typedef __kernel_ssize_t SSIZE_T;
|
||||
#define FIELD_OFFSET(s, field) ((SSIZE_T)&((s *)(0))->field)
|
||||
|
||||
#endif
|
||||
|
||||
#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
|
||||
#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1)
|
||||
|
||||
#define SIZE_PTR SIZE_T
|
||||
#define SSIZE_PTR SSIZE_T
|
||||
|
||||
/*
|
||||
* Continuous bits starting from least significant bit
|
||||
* Example:
|
||||
* BIT_LEN_MASK_32(0) => 0x00000000
|
||||
* BIT_LEN_MASK_32(1) => 0x00000001
|
||||
* BIT_LEN_MASK_32(2) => 0x00000003
|
||||
* BIT_LEN_MASK_32(32) => 0xFFFFFFFF
|
||||
*/
|
||||
#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen))))
|
||||
#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen))))
|
||||
#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen))))
|
||||
|
||||
/*
|
||||
* Continuous bits starting from least significant bit
|
||||
* Example:
|
||||
* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
|
||||
* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
|
||||
*/
|
||||
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset)))
|
||||
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset)))
|
||||
#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset)))
|
||||
|
||||
/*
|
||||
* Convert LE data to host byte order
|
||||
*/
|
||||
#define EF1Byte (u8)
|
||||
#define EF2Byte le16_to_cpu
|
||||
#define EF4Byte le32_to_cpu
|
||||
|
||||
/*
|
||||
* Read LE data from memory to host byte order
|
||||
*/
|
||||
#define ReadLE4Byte(_ptr) le32_to_cpu(*((u32 *)(_ptr)))
|
||||
#define ReadLE2Byte(_ptr) le16_to_cpu(*((u16 *)(_ptr)))
|
||||
#define ReadLE1Byte(_ptr) (*((u8 *)(_ptr)))
|
||||
|
||||
/*
|
||||
* Read BE data from memory to host byte order
|
||||
*/
|
||||
#define ReadBEE4Byte(_ptr) be32_to_cpu(*((u32 *)(_ptr)))
|
||||
#define ReadBE2Byte(_ptr) be16_to_cpu(*((u16 *)(_ptr)))
|
||||
#define ReadBE1Byte(_ptr) (*((u8 *)(_ptr)))
|
||||
|
||||
/*
|
||||
* Write host byte order data to memory in LE order
|
||||
*/
|
||||
#define WriteLE4Byte(_ptr, _val) ((*((u32 *)(_ptr))) = cpu_to_le32(_val))
|
||||
#define WriteLE2Byte(_ptr, _val) ((*((u16 *)(_ptr))) = cpu_to_le16(_val))
|
||||
#define WriteLE1Byte(_ptr, _val) ((*((u8 *)(_ptr))) = ((u8)(_val)))
|
||||
|
||||
/*
|
||||
* Write host byte order data to memory in BE order
|
||||
*/
|
||||
#define WriteBE4Byte(_ptr, _val) ((*((u32 *)(_ptr))) = cpu_to_be32(_val))
|
||||
#define WriteBE2Byte(_ptr, _val) ((*((u16 *)(_ptr))) = cpu_to_be16(_val))
|
||||
#define WriteBE1Byte(_ptr, _val) ((*((u8 *)(_ptr))) = ((u8)(_val)))
|
||||
|
||||
/*
|
||||
* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system.
|
||||
*/
|
||||
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart))))
|
||||
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart))))
|
||||
#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
|
||||
|
||||
/*
|
||||
* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system.
|
||||
*/
|
||||
#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart))))
|
||||
#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart))))
|
||||
#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart))))
|
||||
|
||||
/*
|
||||
* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to
|
||||
* 4-byte value in host byte ordering.
|
||||
*/
|
||||
#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
|
||||
|
||||
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
|
||||
|
||||
#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
|
||||
|
||||
/*
|
||||
* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to
|
||||
* 4-byte value in host byte ordering.
|
||||
*/
|
||||
#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen))
|
||||
|
||||
#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen))
|
||||
|
||||
#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen))
|
||||
|
||||
/*
|
||||
* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering
|
||||
* and return the result in 4-byte value in host byte ordering.
|
||||
*/
|
||||
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
(LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
|
||||
|
||||
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
(LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
|
||||
|
||||
#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
(LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))))
|
||||
|
||||
/*
|
||||
* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering
|
||||
* and return the result in 4-byte value in host byte ordering.
|
||||
*/
|
||||
#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
(BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)))
|
||||
|
||||
#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
(BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen)))
|
||||
|
||||
#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
(BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))
|
||||
|
||||
/*
|
||||
* Set subfield of little-endian 4-byte value to specified value.
|
||||
*/
|
||||
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
|
||||
do { \
|
||||
if (__BitOffset == 0 && __BitLen == 32) \
|
||||
WriteLE4Byte(__pStart, __Value); \
|
||||
else { \
|
||||
WriteLE4Byte(__pStart, \
|
||||
LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
| \
|
||||
((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
|
||||
); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
|
||||
do { \
|
||||
if (__BitOffset == 0 && __BitLen == 16) \
|
||||
WriteLE2Byte(__pStart, __Value); \
|
||||
else { \
|
||||
WriteLE2Byte(__pStart, \
|
||||
LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
| \
|
||||
((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
|
||||
); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
|
||||
do { \
|
||||
if (__BitOffset == 0 && __BitLen == 8) \
|
||||
WriteLE1Byte(__pStart, __Value); \
|
||||
else { \
|
||||
WriteLE1Byte(__pStart, \
|
||||
LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
| \
|
||||
((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
|
||||
); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* Set subfield of big-endian 4-byte value to specified value.
|
||||
*/
|
||||
#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
|
||||
do { \
|
||||
if (__BitOffset == 0 && __BitLen == 32) \
|
||||
WriteBE4Byte(__pStart, __Value); \
|
||||
else { \
|
||||
WriteBE4Byte(__pStart, \
|
||||
BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
| \
|
||||
((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
|
||||
); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
|
||||
do { \
|
||||
if (__BitOffset == 0 && __BitLen == 16) \
|
||||
WriteBE2Byte(__pStart, __Value); \
|
||||
else { \
|
||||
WriteBE2Byte(__pStart, \
|
||||
BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
| \
|
||||
((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \
|
||||
); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
|
||||
do { \
|
||||
if (__BitOffset == 0 && __BitLen == 8) \
|
||||
WriteBE1Byte(__pStart, __Value); \
|
||||
else { \
|
||||
WriteBE1Byte(__pStart, \
|
||||
BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
|
||||
| \
|
||||
((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \
|
||||
); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* Get the N-bytes aligment offset from the current length */
|
||||
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
|
||||
|
||||
typedef unsigned char BOOLEAN, *PBOOLEAN, boolean;
|
||||
|
||||
#define TEST_FLAG(__Flag, __testFlag) (((__Flag) & (__testFlag)) != 0)
|
||||
#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag)
|
||||
#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag))
|
||||
#define CLEAR_FLAGS(__Flag) ((__Flag) = 0)
|
||||
#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags))
|
||||
|
||||
#endif /* __BASIC_TYPES_H__ */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __CIRC_BUF_H_
|
||||
#define __CIRC_BUF_H_ 1
|
||||
|
||||
#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1))
|
||||
|
||||
#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size))
|
||||
|
||||
#endif //_CIRC_BUF_H_
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __CMD_OSDEP_H_
|
||||
#define __CMD_OSDEP_H_
|
||||
|
||||
|
||||
extern sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv);
|
||||
extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv);
|
||||
extern void _rtw_free_evt_priv(struct evt_priv *pevtpriv);
|
||||
extern void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv);
|
||||
extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head);
|
||||
extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __CUSTOM_GPIO_H__
|
||||
#define __CUSTOM_GPIO_H___
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
|
||||
typedef enum cust_gpio_modes {
|
||||
WLAN_PWDN_ON,
|
||||
WLAN_PWDN_OFF,
|
||||
WLAN_POWER_ON,
|
||||
WLAN_POWER_OFF,
|
||||
WLAN_BT_PWDN_ON,
|
||||
WLAN_BT_PWDN_OFF
|
||||
} cust_gpio_modes_t;
|
||||
|
||||
extern int rtw_wifi_gpio_init(void);
|
||||
extern int rtw_wifi_gpio_deinit(void);
|
||||
extern void rtw_wifi_gpio_wlan_ctrl(int onoff);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,812 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __DRV_CONF_H__
|
||||
#define __DRV_CONF_H__
|
||||
#include "autoconf.h"
|
||||
#include "hal_ic_cfg.h"
|
||||
|
||||
#define CONFIG_RSSI_PRIORITY
|
||||
|
||||
/*
|
||||
* RTW_BUSY_DENY_SCAN control if scan would be denied by busy traffic.
|
||||
* When this defined, BUSY_TRAFFIC_SCAN_DENY_PERIOD would be used to judge if
|
||||
* scan request coming from scan UI. Scan request from scan UI would be
|
||||
* exception and never be denied by busy traffic.
|
||||
*/
|
||||
#define RTW_BUSY_DENY_SCAN
|
||||
|
||||
#ifdef CONFIG_RTW_REPEATER_SON
|
||||
#ifndef CONFIG_AP
|
||||
#define CONFIG_AP
|
||||
#endif
|
||||
#ifndef CONFIG_CONCURRENT_MODE
|
||||
#define CONFIG_CONCURRENT_MODE
|
||||
#endif
|
||||
#ifndef CONFIG_BR_EXT
|
||||
#define CONFIG_BR_EXT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_REPEATER_SON_ID
|
||||
#define CONFIG_RTW_REPEATER_SON_ID 0x02040608
|
||||
#endif
|
||||
//#define CONFIG_RTW_REPEATER_SON_ROOT
|
||||
#ifndef CONFIG_RTW_REPEATER_SON_ROOT
|
||||
#undef CONFIG_ROAMING_FLAG
|
||||
#define CONFIG_ROAMING_FLAG 0x7
|
||||
#endif
|
||||
#undef CONFIG_POWER_SAVING
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MCC_MODE) && (!defined(CONFIG_CONCURRENT_MODE))
|
||||
|
||||
#error "Enable CONCURRENT_MODE before enable MCC MODE\n"
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MCC_MODE) && defined(CONFIG_BT_COEXIST)
|
||||
|
||||
#error "Disable BT COEXIST before enable MCC MODE\n"
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MCC_MODE) && defined(CONFIG_TDLS)
|
||||
|
||||
#error "Disable TDLS before enable MCC MODE\n"
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTW_80211R) && !defined(CONFIG_LAYER2_ROAMING)
|
||||
|
||||
#error "Enable CONFIG_LAYER2_ROAMING before enable CONFIG_RTW_80211R\n"
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LAYER2_ROAMING
|
||||
/*#define CONFIG_RTW_ROAM_QUICKSCAN */ /* active_roaming is required. i.e CONFIG_ROAMING_FLAG[bit2] MUST be enabled */
|
||||
/*#define CONFIG_RTW_ROAM_QUICKSCAN_TH 60*/
|
||||
#endif
|
||||
|
||||
/* Default enable single wiphy if driver ver >= 5.9 */
|
||||
#define RTW_SINGLE_WIPHY
|
||||
|
||||
#ifdef CONFIG_RTW_ANDROID
|
||||
|
||||
#include <linux/version.h>
|
||||
|
||||
#ifndef CONFIG_IOCTL_CFG80211
|
||||
#define CONFIG_IOCTL_CFG80211
|
||||
#endif
|
||||
|
||||
#ifndef RTW_USE_CFG80211_STA_EVENT
|
||||
#define RTW_USE_CFG80211_STA_EVENT
|
||||
#endif
|
||||
|
||||
#if (CONFIG_RTW_ANDROID > 4)
|
||||
#ifndef CONFIG_RADIO_WORK
|
||||
#define CONFIG_RADIO_WORK
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_RTW_ANDROID <= 7)
|
||||
#ifdef RTW_SINGLE_WIPHY
|
||||
#undef RTW_SINGLE_WIPHY
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_RTW_ANDROID >= 8)
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0))
|
||||
#ifndef CONFIG_RTW_WIFI_HAL
|
||||
#define CONFIG_RTW_WIFI_HAL
|
||||
#endif
|
||||
#else
|
||||
#error "Linux kernel version is too old\n"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTW_WIFI_HAL
|
||||
#ifndef CONFIG_RTW_WIFI_HAL_DEBUG
|
||||
//#define CONFIG_RTW_WIFI_HAL_DEBUG
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_CFGVENDOR_LLSTATS
|
||||
#define CONFIG_RTW_CFGVENDOR_LLSTATS
|
||||
#endif
|
||||
#if (CONFIG_RTW_ANDROID < 11)
|
||||
#ifndef CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
|
||||
#define CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI
|
||||
#endif
|
||||
#else
|
||||
#ifndef CONFIG_RTW_SCAN_RAND
|
||||
#define CONFIG_RTW_SCAN_RAND
|
||||
#endif
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_CFGVENDOR_RSSIMONITOR
|
||||
#define CONFIG_RTW_CFGVENDOR_RSSIMONITOR
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
|
||||
#define CONFIG_RTW_CFGVENDOR_WIFI_LOGGER
|
||||
#endif
|
||||
#if (CONFIG_RTW_ANDROID >= 10)
|
||||
#ifndef CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
|
||||
//#define CONFIG_RTW_CFGVENDOR_WIFI_OFFLOAD
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_HOSTAPD_ACS
|
||||
#define CONFIG_RTW_HOSTAPD_ACS
|
||||
#endif
|
||||
#ifndef CONFIG_KERNEL_PATCH_EXTERNAL_AUTH
|
||||
#define CONFIG_KERNEL_PATCH_EXTERNAL_AUTH
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_ABORT_SCAN
|
||||
#define CONFIG_RTW_ABORT_SCAN
|
||||
#endif
|
||||
#endif
|
||||
#endif // CONFIG_RTW_WIFI_HAL
|
||||
|
||||
|
||||
/* Some Android build will restart the UI while non-printable ascii is passed
|
||||
* between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID
|
||||
* for Android here. If you are sure there is no risk on your system about this,
|
||||
* mask this macro define to support non-printable ascii ssid.
|
||||
* #define CONFIG_VALIDATE_SSID */
|
||||
|
||||
/* Android expect dbm as the rx signal strength unit */
|
||||
#define CONFIG_SIGNAL_DISPLAY_DBM
|
||||
#endif // CONFIG_RTW_ANDROID
|
||||
|
||||
/*
|
||||
#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(CONFIG_RESUME_IN_WORKQUEUE)
|
||||
#warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
|
||||
#undef CONFIG_RESUME_IN_WORKQUEUE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ANDROID_POWER) && defined(CONFIG_RESUME_IN_WORKQUEUE)
|
||||
#warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically"
|
||||
#undef CONFIG_RESUME_IN_WORKQUEUE
|
||||
#endif
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_RESUME_IN_WORKQUEUE /* this can be removed, because there is no case for this... */
|
||||
#if !defined(CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER)
|
||||
#error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..."
|
||||
#error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* About USB VENDOR REQ */
|
||||
#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
|
||||
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically"
|
||||
#define CONFIG_USB_VENDOR_REQ_MUTEX
|
||||
#endif
|
||||
#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX)
|
||||
#warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically"
|
||||
#define CONFIG_USB_VENDOR_REQ_MUTEX
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WIFI_MONITOR
|
||||
#define CONFIG_MONITOR_MODE_XMIT
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CUSTOMER_ALIBABA_GENERAL
|
||||
#ifndef CONFIG_WIFI_MONITOR
|
||||
#define CONFIG_WIFI_MONITOR
|
||||
#endif
|
||||
#ifdef CONFIG_POWER_SAVING
|
||||
#undef CONFIG_POWER_SAVING
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
|
||||
#ifdef CONFIG_POWER_SAVING
|
||||
#undef CONFIG_POWER_SAVING
|
||||
#endif
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#undef CONFIG_BEAMFORMING
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_DATA_BMC_TO_UC
|
||||
#define CONFIG_RTW_DATA_BMC_TO_UC 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_MODE
|
||||
#define CONFIG_LIMITED_AP_NUM 1
|
||||
|
||||
#ifndef CONFIG_RTW_AP_DATA_BMC_TO_UC
|
||||
#define CONFIG_RTW_AP_DATA_BMC_TO_UC 1
|
||||
#endif
|
||||
#if CONFIG_RTW_AP_DATA_BMC_TO_UC
|
||||
#undef CONFIG_RTW_DATA_BMC_TO_UC
|
||||
#define CONFIG_RTW_DATA_BMC_TO_UC 1
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_AP_SRC_B2U_FLAGS
|
||||
#define CONFIG_RTW_AP_SRC_B2U_FLAGS 0x8 /* see RTW_AP_B2U_XXX */
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_AP_FWD_B2U_FLAGS
|
||||
#define CONFIG_RTW_AP_FWD_B2U_FLAGS 0x8 /* see RTW_AP_B2U_XXX */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTW_MULTI_AP
|
||||
#ifndef CONFIG_AP_MODE
|
||||
#error "enable CONFIG_RTW_MULTI_AP without CONFIG_AP_MODE"
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_WDS
|
||||
#define CONFIG_RTW_WDS
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_UNASOC_STA_MODE_OF_STYPE
|
||||
#define CONFIG_RTW_UNASOC_STA_MODE_OF_STYPE {2, 1} /* BMC:2 for all, NMY_UC:1 for interested target */
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_NLRTW
|
||||
#define CONFIG_RTW_NLRTW
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_WNM
|
||||
#define CONFIG_RTW_WNM
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_80211K
|
||||
#define CONFIG_RTW_80211K
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTW_MESH
|
||||
#ifndef CONFIG_RTW_MESH_ACNODE_PREVENT
|
||||
#define CONFIG_RTW_MESH_ACNODE_PREVENT 1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_MESH_OFFCH_CAND
|
||||
#define CONFIG_RTW_MESH_OFFCH_CAND 1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_MESH_PEER_BLACKLIST
|
||||
#define CONFIG_RTW_MESH_PEER_BLACKLIST 1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
|
||||
#define CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST 1
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MESH_CTO_MGATE_CARRIER
|
||||
#define CONFIG_RTW_MESH_CTO_MGATE_CARRIER CONFIG_RTW_MESH_CTO_MGATE_BLACKLIST
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_MPM_TX_IES_SYNC_BSS
|
||||
#define CONFIG_RTW_MPM_TX_IES_SYNC_BSS 1
|
||||
#endif
|
||||
#if CONFIG_RTW_MPM_TX_IES_SYNC_BSS
|
||||
#ifndef CONFIG_RTW_MESH_AEK
|
||||
#define CONFIG_RTW_MESH_AEK
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_MESH_DATA_BMC_TO_UC
|
||||
#define CONFIG_RTW_MESH_DATA_BMC_TO_UC 1
|
||||
#endif
|
||||
#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
|
||||
#undef CONFIG_RTW_DATA_BMC_TO_UC
|
||||
#define CONFIG_RTW_DATA_BMC_TO_UC 1
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MSRC_B2U_FLAGS
|
||||
#define CONFIG_RTW_MSRC_B2U_FLAGS 0x0 /* see RTW_MESH_B2U_XXX */
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MFWD_B2U_FLAGS
|
||||
#define CONFIG_RTW_MFWD_B2U_FLAGS 0x2 /* see RTW_MESH_B2U_XXX */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SCAN_BACKOP) && defined(CONFIG_AP_MODE)
|
||||
#define CONFIG_SCAN_BACKOP
|
||||
#endif
|
||||
|
||||
#define RTW_SCAN_SPARSE_MIRACAST 1
|
||||
#define RTW_SCAN_SPARSE_BG 0
|
||||
|
||||
#ifndef CONFIG_TX_AC_LIFETIME
|
||||
#define CONFIG_TX_AC_LIFETIME 1
|
||||
#endif
|
||||
#ifndef CONFIG_TX_ACLT_FLAGS
|
||||
#define CONFIG_TX_ACLT_FLAGS 0x00
|
||||
#endif
|
||||
#ifndef CONFIG_TX_ACLT_CONF_DEFAULT
|
||||
#define CONFIG_TX_ACLT_CONF_DEFAULT {0x0, 1024 * 1000, 1024 * 1000}
|
||||
#endif
|
||||
#ifndef CONFIG_TX_ACLT_CONF_AP_M2U
|
||||
#define CONFIG_TX_ACLT_CONF_AP_M2U {0xF, 256 * 1000, 256 * 1000}
|
||||
#endif
|
||||
#ifndef CONFIG_TX_ACLT_CONF_MESH
|
||||
#define CONFIG_TX_ACLT_CONF_MESH {0xF, 256 * 1000, 256 * 1000}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_HIQ_FILTER
|
||||
#define CONFIG_RTW_HIQ_FILTER 1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_ADAPTIVITY_EN
|
||||
#define CONFIG_RTW_ADAPTIVITY_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_ADAPTIVITY_MODE
|
||||
#define CONFIG_RTW_ADAPTIVITY_MODE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI
|
||||
#define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF
|
||||
#define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_EXCL_CHS
|
||||
#define CONFIG_RTW_EXCL_CHS {0}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IEEE80211_BAND_5GHZ
|
||||
#if defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8821C) \
|
||||
|| defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) \
|
||||
|| defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8814B) || defined(CONFIG_RTL8723F)
|
||||
#define CONFIG_IEEE80211_BAND_5GHZ 1
|
||||
#else
|
||||
#define CONFIG_IEEE80211_BAND_5GHZ 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DFS
|
||||
#define CONFIG_DFS 1
|
||||
#endif
|
||||
|
||||
#if CONFIG_IEEE80211_BAND_5GHZ && CONFIG_DFS && defined(CONFIG_AP_MODE)
|
||||
#if !defined(CONFIG_DFS_SLAVE_WITH_RADAR_DETECT)
|
||||
#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
|
||||
#endif
|
||||
#if !defined(CONFIG_DFS_MASTER) || CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
|
||||
#define CONFIG_DFS_MASTER
|
||||
#endif
|
||||
#if defined(CONFIG_DFS_MASTER) && !defined(CONFIG_RTW_DFS_REGION_DOMAIN)
|
||||
#define CONFIG_RTW_DFS_REGION_DOMAIN 0
|
||||
#endif
|
||||
#else
|
||||
#undef CONFIG_DFS_MASTER
|
||||
#undef CONFIG_RTW_DFS_REGION_DOMAIN
|
||||
#define CONFIG_RTW_DFS_REGION_DOMAIN 0
|
||||
#undef CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
|
||||
#define CONFIG_DFS_SLAVE_WITH_RADAR_DETECT 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TXPWR_BY_RATE_EN
|
||||
#define CONFIG_TXPWR_BY_RATE_EN 2 /* by efuse */
|
||||
#endif
|
||||
#ifndef CONFIG_TXPWR_LIMIT_EN
|
||||
#define CONFIG_TXPWR_LIMIT_EN 2 /* by efuse */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_CHPLAN
|
||||
#define CONFIG_RTW_CHPLAN 0xFF /* RTW_CHPLAN_UNSPECIFIED */
|
||||
#endif
|
||||
|
||||
/* compatible with old fashion configuration */
|
||||
#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY)
|
||||
#undef CONFIG_TXPWR_BY_RATE_EN
|
||||
#undef CONFIG_TXPWR_LIMIT_EN
|
||||
#define CONFIG_TXPWR_BY_RATE_EN 1
|
||||
#define CONFIG_TXPWR_LIMIT_EN 1
|
||||
#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX)
|
||||
#undef CONFIG_TXPWR_BY_RATE_EN
|
||||
#undef CONFIG_TXPWR_LIMIT_EN
|
||||
#define CONFIG_TXPWR_BY_RATE_EN 1
|
||||
#define CONFIG_TXPWR_LIMIT_EN 0
|
||||
#endif
|
||||
|
||||
#ifndef RTW_DEF_MODULE_REGULATORY_CERT
|
||||
#define RTW_DEF_MODULE_REGULATORY_CERT 0
|
||||
#endif
|
||||
|
||||
#if RTW_DEF_MODULE_REGULATORY_CERT
|
||||
#ifdef CONFIG_REGD_SRC_FROM_OS
|
||||
#error "CONFIG_REGD_SRC_FROM_OS is not supported when enable RTW_DEF_MODULE_REGULATORY_CERT"
|
||||
#endif
|
||||
/* force enable TX power by rate and TX power limit */
|
||||
#undef CONFIG_TXPWR_BY_RATE_EN
|
||||
#undef CONFIG_TXPWR_LIMIT_EN
|
||||
#define CONFIG_TXPWR_BY_RATE_EN 1
|
||||
#define CONFIG_TXPWR_LIMIT_EN 1
|
||||
#endif
|
||||
|
||||
#if !CONFIG_TXPWR_LIMIT && CONFIG_TXPWR_LIMIT_EN
|
||||
#undef CONFIG_TXPWR_LIMIT
|
||||
#define CONFIG_TXPWR_LIMIT 1
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_REGD_SRC
|
||||
#define CONFIG_RTW_REGD_SRC 1 /* 0:RTK_PRIV, 1:OS */
|
||||
#endif
|
||||
|
||||
#define CONFIG_IOCTL_WEXT
|
||||
|
||||
#ifdef CONFIG_RTW_IPCAM_APPLICATION
|
||||
#undef CONFIG_TXPWR_BY_RATE_EN
|
||||
#define CONFIG_TXPWR_BY_RATE_EN 1
|
||||
#define CONFIG_RTW_CUSTOMIZE_BEEDCA 0x0000431C
|
||||
#define CONFIG_RTW_CUSTOMIZE_BWMODE 0x00
|
||||
#define CONFIG_RTW_CUSTOMIZE_RLSTA 0x30
|
||||
#define CONFIG_CHECK_SPECIFIC_IE_CONTENT
|
||||
#ifdef CONFIG_CUSTOMER_EZVIZ_CHIME2
|
||||
#undef CONFIG_ACTIVE_KEEP_ALIVE_CHECK
|
||||
#endif
|
||||
#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8822B)
|
||||
#define CONFIG_RTW_TX_NPATH_EN /* mutually incompatible with STBC_TX & Beamformer */
|
||||
#endif
|
||||
#endif
|
||||
/* #define CONFIG_RTW_TOKEN_BASED_XMIT */
|
||||
#ifdef CONFIG_RTW_TOKEN_BASED_XMIT
|
||||
#define NR_TBTX_SLOT 4
|
||||
#define NR_MAXSTA_INSLOT 5
|
||||
#define TBTX_TX_DURATION 30
|
||||
|
||||
#define MAX_TXPAUSE_DURATION (TBTX_TX_DURATION*NR_TBTX_SLOT)
|
||||
#endif
|
||||
|
||||
/*#define CONFIG_EXTEND_LOWRATE_TXOP */
|
||||
|
||||
#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS
|
||||
#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF}
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS
|
||||
#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS {0xFF, 0xFF, 0xFF, 0xFF}
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS
|
||||
#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS {0xFF, 0xFF, 0xFF, 0xFF}
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS
|
||||
#define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS {0xFF, 0xFF, 0xFF, 0xFF}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D
|
||||
#define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_ANTENNA_GAIN
|
||||
#define CONFIG_RTW_ANTENNA_GAIN 0x7FFF /* == UNSPECIFIED_MBM */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G
|
||||
#define CONFIG_RTW_AMPLIFIER_TYPE_2G 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G
|
||||
#define CONFIG_RTW_AMPLIFIER_TYPE_5G 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_RFE_TYPE
|
||||
#define CONFIG_RTW_RFE_TYPE 64
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_GLNA_TYPE
|
||||
#define CONFIG_RTW_GLNA_TYPE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_PLL_REF_CLK_SEL
|
||||
#define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_IFACE_NUMBER
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
#define CONFIG_IFACE_NUMBER 2
|
||||
#else
|
||||
#define CONFIG_IFACE_NUMBER 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CONCURRENT_MODE
|
||||
#if (CONFIG_IFACE_NUMBER > 1)
|
||||
#error "CONFIG_IFACE_NUMBER over 1,but CONFIG_CONCURRENT_MODE not defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_IFACE_NUMBER == 0)
|
||||
#error "CONFIG_IFACE_NUMBER cound not be 0 !!"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8188F) || \
|
||||
defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8192F) || \
|
||||
defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8710B) || \
|
||||
defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8723D)
|
||||
#define CONFIG_HWMPCAP_GEN1
|
||||
#elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || \
|
||||
defined(CONFIG_RTL8723F) /*|| defined(CONFIG_RTL8814A)*/
|
||||
#define CONFIG_HWMPCAP_GEN2
|
||||
#elif defined(CONFIG_RTL8814B) /*Address CAM - 128*/
|
||||
#define CONFIG_HWMPCAP_GEN3
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 2)
|
||||
#ifdef CONFIG_POWER_SAVING
|
||||
/*#warning "Disable PS when CONFIG_IFACE_NUMBER > 2"*/
|
||||
#undef CONFIG_POWER_SAVING
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#error "This IC can't support MI and WoWLan at the same time"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HWMPCAP_GEN1) && (CONFIG_IFACE_NUMBER > 3)
|
||||
#error " This IC can't support over 3 interfaces !!"
|
||||
#endif
|
||||
|
||||
#if (CONFIG_IFACE_NUMBER > 4)
|
||||
#error "Not support over 4 interfaces yet !!"
|
||||
#endif
|
||||
|
||||
#if (CONFIG_IFACE_NUMBER > 8) /*IFACE_ID_MAX*/
|
||||
#error "HW count not support over 8 interfaces !!"
|
||||
#endif
|
||||
|
||||
#if (CONFIG_IFACE_NUMBER > 2)
|
||||
#ifndef CONFIG_HWMPCAP_GEN3
|
||||
#define CONFIG_MI_WITH_MBSSID_CAM
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MI_WITH_MBSSID_CAM
|
||||
#define CONFIG_MBSSID_CAM
|
||||
#if defined(CONFIG_RUNTIME_PORT_SWITCH)
|
||||
#undef CONFIG_RUNTIME_PORT_SWITCH
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_MODE
|
||||
#undef CONFIG_LIMITED_AP_NUM
|
||||
#define CONFIG_LIMITED_AP_NUM 2
|
||||
|
||||
#define CONFIG_SUPPORT_MULTI_BCN
|
||||
|
||||
#define CONFIG_SWTIMER_BASED_TXBCN
|
||||
|
||||
#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
|
||||
#define CONFIG_FW_HANDLE_TXBCN
|
||||
|
||||
#ifdef CONFIG_FW_HANDLE_TXBCN
|
||||
#ifdef CONFIG_SWTIMER_BASED_TXBCN
|
||||
#undef CONFIG_SWTIMER_BASED_TXBCN
|
||||
#endif
|
||||
#undef CONFIG_LIMITED_AP_NUM
|
||||
#define CONFIG_LIMITED_AP_NUM 4
|
||||
#endif
|
||||
|
||||
#endif /*CONFIG_HWMPCAP_GEN2*/
|
||||
|
||||
#ifdef CONFIG_HWMPCAP_GEN3
|
||||
#define CONFIG_PORT_BASED_TXBCN
|
||||
#undef CONFIG_SUPPORT_MULTI_BCN
|
||||
#undef CONFIG_SWTIMER_BASED_TXBCN
|
||||
#undef CONFIG_LIMITED_AP_NUM
|
||||
#define CONFIG_LIMITED_AP_NUM 4
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define CONFIG_PORT_BASED_HIQ /* 8814BU doesn't support */
|
||||
#endif
|
||||
#endif
|
||||
#endif /*CONFIG_AP_MODE*/
|
||||
|
||||
#ifdef CONFIG_HWMPCAP_GEN2 /*CONFIG_RTL8822B/CONFIG_RTL8821C/CONFIG_RTL8822C*/
|
||||
#define CONFIG_CLIENT_PORT_CFG
|
||||
#define CONFIG_NEW_NETDEV_HDL
|
||||
#endif/*CONFIG_HWMPCAP_GEN2*/
|
||||
#endif/*(CONFIG_IFACE_NUMBER > 2)*/
|
||||
|
||||
#if defined(CONFIG_MI_UNIQUE_MACADDR_BIT)
|
||||
#if !defined(CONFIG_MI_WITH_MBSSID_CAM)
|
||||
#error "CONFIG_MI_UNIQUE_MACADDR_BIT should not be used without multiple interface !!"
|
||||
#endif
|
||||
#if (CONFIG_MI_UNIQUE_MACADDR_BIT < 24) || ( 47 < CONFIG_MI_UNIQUE_MACADDR_BIT)
|
||||
#error "CONFIG_MI_UNIQUE_MACADDR_BIT should be the bit in NIC specific mac address(BIT[24:47] !!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define MACID_NUM_SW_LIMIT 32
|
||||
#define SEC_CAM_ENT_NUM_SW_LIMIT 32
|
||||
|
||||
#ifdef SEC_DEFAULT_KEY_SEARCH
|
||||
#if (CONFIG_IFACE_NUMBER >= 2)
|
||||
#error "Default Key Search only work with only one interface case!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_WOWLAN) && (defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B))
|
||||
#define CONFIG_WOW_PATTERN_HW_CAM
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TSF_UPDATE_PAUSE_FACTOR
|
||||
#define CONFIG_TSF_UPDATE_PAUSE_FACTOR 200
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TSF_UPDATE_RESTORE_FACTOR
|
||||
#define CONFIG_TSF_UPDATE_RESTORE_FACTOR 5
|
||||
#endif
|
||||
|
||||
/*
|
||||
Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20
|
||||
If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle,
|
||||
power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP.
|
||||
*/
|
||||
/*#define CONFIG_DEAUTH_BEFORE_CONNECT */
|
||||
|
||||
/*#define CONFIG_WEXT_DONT_JOIN_BYSSID */
|
||||
/* #include <rtl871x_byteorder.h> */
|
||||
|
||||
|
||||
/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */
|
||||
/*#define CONFIG_PHDYM_FW_FIXRATE */ /* Another way to fix tx rate */
|
||||
|
||||
/*Don't release SDIO irq in suspend/resume procedure*/
|
||||
#define CONFIG_RTW_SDIO_KEEP_IRQ 0
|
||||
|
||||
/*
|
||||
* Add by Lucas@2016/02/15
|
||||
* For RX Aggregation
|
||||
*/
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_RX_AGGREGATION)
|
||||
#define RTW_RX_AGGREGATION
|
||||
#endif /* CONFIG_SDIO_HCI || CONFIG_USB_RX_AGGREGATION */
|
||||
|
||||
#ifdef CONFIG_RTW_HOSTAPD_ACS
|
||||
#ifndef CONFIG_RTW_ACS
|
||||
#define CONFIG_RTW_ACS
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTW_80211K
|
||||
#ifndef CONFIG_RTW_ACS
|
||||
#define CONFIG_RTW_ACS
|
||||
#endif
|
||||
#endif /*CONFIG_RTW_80211K*/
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_RESET
|
||||
#ifndef CONFIG_IPS
|
||||
#define CONFIG_IPS
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IPS */
|
||||
#ifndef RTW_IPS_MODE
|
||||
#if defined(CONFIG_IPS)
|
||||
#define RTW_IPS_MODE 1
|
||||
#else
|
||||
#define RTW_IPS_MODE 0
|
||||
#endif
|
||||
#endif /* !RTW_IPS_MODE */
|
||||
|
||||
#if (RTW_IPS_MODE > 1 || RTW_IPS_MODE < 0)
|
||||
#error "The CONFIG_IPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
|
||||
#endif
|
||||
|
||||
/* LPS */
|
||||
#ifndef RTW_LPS_MODE
|
||||
#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
|
||||
#define RTW_LPS_MODE 3
|
||||
#elif defined(CONFIG_LPS_LCLK)
|
||||
#define RTW_LPS_MODE 2
|
||||
#elif defined(CONFIG_LPS)
|
||||
#define RTW_LPS_MODE 1
|
||||
#else
|
||||
#define RTW_LPS_MODE 0
|
||||
#endif
|
||||
#endif /* !RTW_LPS_MODE */
|
||||
|
||||
#if (RTW_LPS_MODE > 3 || RTW_LPS_MODE < 0)
|
||||
#error "The CONFIG_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
|
||||
#endif
|
||||
|
||||
#ifndef RTW_LPS_1T1R
|
||||
#define RTW_LPS_1T1R 0
|
||||
#endif
|
||||
|
||||
#ifndef RTW_WOW_LPS_1T1R
|
||||
#define RTW_WOW_LPS_1T1R 0
|
||||
#endif
|
||||
|
||||
/* WOW LPS */
|
||||
#ifndef RTW_WOW_LPS_MODE
|
||||
#if defined(CONFIG_LPS_PG) || defined(CONFIG_LPS_PG_DDMA)
|
||||
#define RTW_WOW_LPS_MODE 3
|
||||
#elif defined(CONFIG_LPS_LCLK)
|
||||
#define RTW_WOW_LPS_MODE 2
|
||||
#elif defined(CONFIG_LPS)
|
||||
#define RTW_WOW_LPS_MODE 1
|
||||
#else
|
||||
#define RTW_WOW_LPS_MODE 0
|
||||
#endif
|
||||
#endif /* !RTW_WOW_LPS_MODE */
|
||||
|
||||
#if (RTW_WOW_LPS_MODE > 3 || RTW_WOW_LPS_MODE < 0)
|
||||
#error "The RTW_WOW_LPS_MODE value is wrong. Please follow HowTo_enable_the_power_saving_functionality.pdf.\n"
|
||||
#endif
|
||||
|
||||
#ifdef RTW_REDUCE_SCAN_SWITCH_CH_TIME
|
||||
#ifndef CONFIG_RTL8822B
|
||||
#error "Only 8822B support RTW_REDUCE_SCAN_SWITCH_CH_TIME"
|
||||
#endif
|
||||
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#define RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WAR_OFFLOAD
|
||||
#ifndef CONFIG_WOWLAN
|
||||
#error "WAR OFFLOAD is part of WOWLAN"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
|
||||
#ifndef CONFIG_WOWLAN
|
||||
#error "mDNS OFFLOAD is part of WOWLAN"
|
||||
#endif
|
||||
#ifndef CONFIG_WAR_OFFLOAD
|
||||
#define CONFIG_WAR_OFFLOAD
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_RTW_TPT_MODE
|
||||
|
||||
#ifdef CONFIG_PCI_BCN_POLLING
|
||||
#define CONFIG_BCN_ICF
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RTW_MGMT_QUEUE
|
||||
#define CONFIG_RTW_MGMT_QUEUE
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PCI_MSI
|
||||
#define CONFIG_RTW_PCI_MSI_DISABLE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY) || \
|
||||
defined(CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL)
|
||||
#define CONFIG_PCI_DYNAMIC_ASPM
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
/* Debug related compiler flags */
|
||||
#define DBG_THREAD_PID /* Add thread pid to debug message prefix */
|
||||
#define DBG_CPU_INFO /* Add CPU info to debug message prefix */
|
||||
#endif
|
||||
|
||||
#ifndef RTW_AMSDU_MODE
|
||||
#define RTW_AMSDU_MODE 0 /* 0:non-SPP, 1:spp mode, 2:All drop */
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_CONF_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,86 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __DRV_TYPES_CE_H__
|
||||
#define __DRV_TYPES_CE_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
|
||||
#include <Sdcardddk.h>
|
||||
|
||||
#define MAX_ACTIVE_REG_PATH 256
|
||||
|
||||
#define MAX_MCAST_LIST_NUM 32
|
||||
|
||||
|
||||
|
||||
/* for ioctl */
|
||||
#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
|
||||
|
||||
#define NIC_HEADER_SIZE 14 /* !< can be moved to typedef.h */
|
||||
#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
|
||||
#define NIC_MAX_SEND_PACKETS 10 /* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
|
||||
#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0, 001) /* !< can be moved to typedef.h */
|
||||
#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
|
||||
|
||||
typedef struct _MP_REG_ENTRY {
|
||||
|
||||
NDIS_STRING RegName; /* variable name text */
|
||||
BOOLEAN bRequired; /* 1->required, 0->optional */
|
||||
|
||||
u8 Type; /* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
|
||||
uint FieldOffset; /* offset to MP_ADAPTER field */
|
||||
uint FieldSize; /* size (in bytes) of the field */
|
||||
|
||||
#ifdef UNDER_AMD64
|
||||
u64 Default;
|
||||
#else
|
||||
u32 Default; /* default value to use */
|
||||
#endif
|
||||
|
||||
u32 Min; /* minimum value allowed */
|
||||
u32 Max; /* maximum value allowed */
|
||||
} MP_REG_ENTRY, *PMP_REG_ENTRY;
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
typedef struct _USB_EXTENSION {
|
||||
LPCUSB_FUNCS _lpUsbFuncs;
|
||||
USB_HANDLE _hDevice;
|
||||
PVOID pAdapter;
|
||||
|
||||
#if 0
|
||||
USB_ENDPOINT_DESCRIPTOR _endpACLIn;
|
||||
USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh;
|
||||
USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal;
|
||||
|
||||
USB_PIPE pPipeIn;
|
||||
USB_PIPE pPipeOutNormal;
|
||||
USB_PIPE pPipeOutHigh;
|
||||
#endif
|
||||
|
||||
} USB_EXTENSION, *PUSB_EXTENSION;
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct _OCTET_STRING {
|
||||
u8 *Octet;
|
||||
u16 Length;
|
||||
} OCTET_STRING, *POCTET_STRING;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __DRV_TYPES_GSPI_H__
|
||||
#define __DRV_TYPES_GSPI_H__
|
||||
|
||||
/* SPI Header Files */
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/gpio.h>
|
||||
/* #include <mach/ldo.h> */
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <custom_gpio.h>
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct gspi_data {
|
||||
u8 func_number;
|
||||
|
||||
u8 tx_block_mode;
|
||||
u8 rx_block_mode;
|
||||
u32 block_transfer_len;
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
struct spi_device *func;
|
||||
|
||||
struct workqueue_struct *priv_wq;
|
||||
struct delayed_work irq_work;
|
||||
#endif
|
||||
} GSPI_DATA, *PGSPI_DATA;
|
||||
|
||||
#endif /* #ifndef __DRV_TYPES_GSPI_H__ */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __DRV_TYPES_LINUX_H__
|
||||
#define __DRV_TYPES_LINUX_H__
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __DRV_TYPES_PCI_H__
|
||||
#define __DRV_TYPES_PCI_H__
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <linux/pci.h>
|
||||
#endif
|
||||
|
||||
#define INTEL_VENDOR_ID 0x8086
|
||||
#define SIS_VENDOR_ID 0x1039
|
||||
#define ATI_VENDOR_ID 0x1002
|
||||
#define ATI_DEVICE_ID 0x7914
|
||||
#define AMD_VENDOR_ID 0x1022
|
||||
|
||||
#define PCI_VENDER_ID_REALTEK 0x10ec
|
||||
|
||||
enum aspm_mode {
|
||||
ASPM_MODE_UND,
|
||||
ASPM_MODE_PERF,
|
||||
ASPM_MODE_PS,
|
||||
ASPM_MODE_DEF,
|
||||
};
|
||||
|
||||
struct pci_priv {
|
||||
BOOLEAN pci_clk_req;
|
||||
|
||||
u8 pciehdr_offset;
|
||||
|
||||
u8 linkctrl_reg;
|
||||
u8 pcibridge_linkctrlreg;
|
||||
|
||||
u8 amd_l1_patch;
|
||||
|
||||
#ifdef CONFIG_PCI_DYNAMIC_ASPM
|
||||
u8 aspm_mode;
|
||||
#endif
|
||||
};
|
||||
|
||||
typedef struct _RT_ISR_CONTENT {
|
||||
union {
|
||||
u32 IntArray[2];
|
||||
u32 IntReg4Byte;
|
||||
u16 IntReg2Byte;
|
||||
};
|
||||
} RT_ISR_CONTENT, *PRT_ISR_CONTENT;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __DRV_TYPES_SDIO_H__
|
||||
#define __DRV_TYPES_SDIO_H__
|
||||
|
||||
/* SDIO Header Files */
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <linux/mmc/sdio_func.h>
|
||||
#include <linux/mmc/sdio_ids.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/mmc/card.h>
|
||||
|
||||
#ifdef CONFIG_PLATFORM_SPRD
|
||||
#include <linux/gpio.h>
|
||||
#include <custom_gpio.h>
|
||||
#endif /* CONFIG_PLATFORM_SPRD */
|
||||
#endif
|
||||
|
||||
#define RTW_SDIO_CLK_33M 33000000
|
||||
#define RTW_SDIO_CLK_40M 40000000
|
||||
#define RTW_SDIO_CLK_80M 80000000
|
||||
#define RTW_SDIO_CLK_160M 160000000
|
||||
|
||||
typedef struct sdio_data {
|
||||
u8 func_number;
|
||||
|
||||
u8 tx_block_mode;
|
||||
u8 rx_block_mode;
|
||||
u32 block_transfer_len;
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
struct mmc_card *card;
|
||||
struct sdio_func *func;
|
||||
_thread_hdl_ sys_sdio_irq_thd;
|
||||
unsigned int clock;
|
||||
unsigned int timing;
|
||||
u8 sd3_bus_mode;
|
||||
#endif
|
||||
|
||||
#ifdef DBG_SDIO
|
||||
#ifdef PLATFORM_LINUX
|
||||
struct proc_dir_entry *proc_sdio_dbg;
|
||||
#endif /* PLATFORM_LINUX */
|
||||
|
||||
u32 cmd52_err_cnt; /* CMD52 I/O error count */
|
||||
u32 cmd53_err_cnt; /* CMD53 I/O error count */
|
||||
|
||||
#if (DBG_SDIO >= 1)
|
||||
u32 reg_dump_mark; /* reg dump at specific error count */
|
||||
#endif /* DBG_SDIO >= 1 */
|
||||
|
||||
#if (DBG_SDIO >= 2)
|
||||
u8 *dbg_msg; /* Messages for debug */
|
||||
u8 dbg_msg_size;
|
||||
u8 *reg_mac; /* Device MAC register, 0x0~0x800 */
|
||||
u8 *reg_mac_ext; /* Device MAC extend register, 0x1000~0x1800 */
|
||||
u8 *reg_local; /* Device SDIO local register, 0x0~0xFF */
|
||||
u8 *reg_cia; /* SDIO CIA(CCCR, FBR and etc.), 0x0~0x1FF */
|
||||
#endif /* DBG_SDIO >= 2 */
|
||||
|
||||
#if (DBG_SDIO >= 3)
|
||||
u8 dbg_enable; /* 0/1: disable/enable debug mode */
|
||||
u8 err_stop; /* Stop(surprise remove) when I/O error happen */
|
||||
u8 err_test; /* Simulate error happen */
|
||||
u8 err_test_triggered; /* Simulate error already triggered */
|
||||
#endif /* DBG_SDIO >= 3 */
|
||||
#endif /* DBG_SDIO */
|
||||
} SDIO_DATA, *PSDIO_DATA;
|
||||
|
||||
#define dvobj_to_sdio_func(d) ((d)->intf_data.func)
|
||||
|
||||
#define RTW_SDIO_ADDR_CMD52_BIT (1<<17)
|
||||
#define RTW_SDIO_ADDR_CMD52_GEN(a) (a | RTW_SDIO_ADDR_CMD52_BIT)
|
||||
#define RTW_SDIO_ADDR_CMD52_CLR(a) (a&~RTW_SDIO_ADDR_CMD52_BIT)
|
||||
#define RTW_SDIO_ADDR_CMD52_CHK(a) (a&RTW_SDIO_ADDR_CMD52_BIT ? 1 : 0)
|
||||
|
||||
#define RTW_SDIO_ADDR_F0_BIT (1<<18)
|
||||
#define RTW_SDIO_ADDR_F0_GEN(a) (a | RTW_SDIO_ADDR_F0_BIT)
|
||||
#define RTW_SDIO_ADDR_F0_CLR(a) (a&~RTW_SDIO_ADDR_F0_BIT)
|
||||
#define RTW_SDIO_ADDR_F0_CHK(a) (a&RTW_SDIO_ADDR_F0_BIT ? 1 : 0)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __DRV_TYPES_XP_H__
|
||||
#define __DRV_TYPES_XP_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
|
||||
|
||||
|
||||
#define MAX_MCAST_LIST_NUM 32
|
||||
|
||||
|
||||
|
||||
/* for ioctl */
|
||||
#define MAKE_DRIVER_VERSION(_MainVer, _MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer)
|
||||
|
||||
#define NIC_HEADER_SIZE 14 /* !< can be moved to typedef.h */
|
||||
#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
|
||||
#define NIC_MAX_SEND_PACKETS 10 /* max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h */
|
||||
#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0, 001) /* !< can be moved to typedef.h */
|
||||
#define NIC_MAX_PACKET_SIZE 1514 /* !< can be moved to typedef.h */
|
||||
|
||||
|
||||
#undef ON_VISTA
|
||||
/* added by Jackson */
|
||||
#ifndef ON_VISTA
|
||||
/*
|
||||
* Bus driver versions
|
||||
* */
|
||||
|
||||
#define SDBUS_DRIVER_VERSION_1 0x100
|
||||
#define SDBUS_DRIVER_VERSION_2 0x200
|
||||
|
||||
#define SDP_FUNCTION_TYPE 4
|
||||
#define SDP_BUS_DRIVER_VERSION 5
|
||||
#define SDP_BUS_WIDTH 6
|
||||
#define SDP_BUS_CLOCK 7
|
||||
#define SDP_BUS_INTERFACE_CONTROL 8
|
||||
#define SDP_HOST_BLOCK_LENGTH 9
|
||||
#define SDP_FUNCTION_BLOCK_LENGTH 10
|
||||
#define SDP_FN0_BLOCK_LENGTH 11
|
||||
#define SDP_FUNCTION_INT_ENABLE 12
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct _MP_REG_ENTRY {
|
||||
|
||||
NDIS_STRING RegName; /* variable name text */
|
||||
BOOLEAN bRequired; /* 1->required, 0->optional */
|
||||
|
||||
u8 Type; /* NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString */
|
||||
uint FieldOffset; /* offset to MP_ADAPTER field */
|
||||
uint FieldSize; /* size (in bytes) of the field */
|
||||
|
||||
#ifdef UNDER_AMD64
|
||||
u64 Default;
|
||||
#else
|
||||
u32 Default; /* default value to use */
|
||||
#endif
|
||||
|
||||
u32 Min; /* minimum value allowed */
|
||||
u32 Max; /* maximum value allowed */
|
||||
} MP_REG_ENTRY, *PMP_REG_ENTRY;
|
||||
|
||||
|
||||
typedef struct _OCTET_STRING {
|
||||
u8 *Octet;
|
||||
u16 Length;
|
||||
} OCTET_STRING, *POCTET_STRING;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
/*! \file */
|
||||
#ifndef __INC_ETHERNET_H
|
||||
#define __INC_ETHERNET_H
|
||||
|
||||
#define ETHERNET_ADDRESS_LENGTH 6 /* !< Ethernet Address Length */
|
||||
#define ETHERNET_HEADER_SIZE 14 /* !< Ethernet Header Length */
|
||||
#define LLC_HEADER_SIZE 6 /* !< LLC Header Length */
|
||||
#define TYPE_LENGTH_FIELD_SIZE 2 /* !< Type/Length Size */
|
||||
#define MINIMUM_ETHERNET_PACKET_SIZE 60 /* !< Minimum Ethernet Packet Size */
|
||||
#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 /* !< Maximum Ethernet Packet Size */
|
||||
|
||||
#define RT_ETH_IS_MULTICAST(_pAddr) ((((u8 *)(_pAddr))[0]&0x01) != 0) /* !< Is Multicast Address? */
|
||||
#define RT_ETH_IS_BROADCAST(_pAddr) (\
|
||||
((u8 *)(_pAddr))[0] == 0xff && \
|
||||
((u8 *)(_pAddr))[1] == 0xff && \
|
||||
((u8 *)(_pAddr))[2] == 0xff && \
|
||||
((u8 *)(_pAddr))[3] == 0xff && \
|
||||
((u8 *)(_pAddr))[4] == 0xff && \
|
||||
((u8 *)(_pAddr))[5] == 0xff) /* !< Is Broadcast Address? */
|
||||
|
||||
|
||||
#endif /* #ifndef __INC_ETHERNET_H */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __GSPI_HAL_H__
|
||||
#define __GSPI_HAL_H__
|
||||
|
||||
|
||||
void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr);
|
||||
u8 rtw_set_hal_ops(_adapter *padapter);
|
||||
|
||||
#ifdef CONFIG_RTL8188E
|
||||
void rtl8188es_set_hal_ops(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723B
|
||||
void rtl8723bs_set_hal_ops(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif /* __GSPI_HAL_H__ */
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __GSPI_OPS_H__
|
||||
#define __GSPI_OPS_H__
|
||||
|
||||
/* follwing defination is based on
|
||||
* GSPI spec of RTL8723, we temp
|
||||
* suppose that it will be the same
|
||||
* for diff chips of GSPI, if not
|
||||
* we should move it to HAL folder */
|
||||
#define SPI_LOCAL_DOMAIN 0x0
|
||||
#define WLAN_IOREG_DOMAIN 0x8
|
||||
#define FW_FIFO_DOMAIN 0x4
|
||||
#define TX_HIQ_DOMAIN 0xc
|
||||
#define TX_MIQ_DOMAIN 0xd
|
||||
#define TX_LOQ_DOMAIN 0xe
|
||||
#define RX_RXFIFO_DOMAIN 0x1f
|
||||
|
||||
/* IO Bus domain address mapping */
|
||||
#define DEFUALT_OFFSET 0x0
|
||||
#define SPI_LOCAL_OFFSET 0x10250000
|
||||
#define WLAN_IOREG_OFFSET 0x10260000
|
||||
#define FW_FIFO_OFFSET 0x10270000
|
||||
#define TX_HIQ_OFFSET 0x10310000
|
||||
#define TX_MIQ_OFFSET 0x1032000
|
||||
#define TX_LOQ_OFFSET 0x10330000
|
||||
#define RX_RXOFF_OFFSET 0x10340000
|
||||
|
||||
/* SPI Local registers */
|
||||
#define SPI_REG_TX_CTRL 0x0000 /* SPI Tx Control */
|
||||
#define SPI_REG_STATUS_RECOVERY 0x0004
|
||||
#define SPI_REG_INT_TIMEOUT 0x0006
|
||||
#define SPI_REG_HIMR 0x0014 /* SPI Host Interrupt Mask */
|
||||
#define SPI_REG_HISR 0x0018 /* SPI Host Interrupt Service Routine */
|
||||
#define SPI_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */
|
||||
#define SPI_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */
|
||||
#define SPI_REG_HCPWM1 0x0024 /* HCI Current Power Mode 1 */
|
||||
#define SPI_REG_HCPWM2 0x0026 /* HCI Current Power Mode 2 */
|
||||
#define SPI_REG_HTSFR_INFO 0x0030 /* HTSF Informaion */
|
||||
#define SPI_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */
|
||||
#define SPI_REG_HRPWM2 0x0082 /* HCI Request Power Mode 2 */
|
||||
#define SPI_REG_HPS_CLKR 0x0084 /* HCI Power Save Clock */
|
||||
#define SPI_REG_HSUS_CTRL 0x0086 /* SPI HCI Suspend Control */
|
||||
#define SPI_REG_HIMR_ON 0x0090 /* SPI Host Extension Interrupt Mask Always */
|
||||
#define SPI_REG_HISR_ON 0x0091 /* SPI Host Extension Interrupt Status Always */
|
||||
#define SPI_REG_CFG 0x00F0 /* SPI Configuration Register */
|
||||
|
||||
#define SPI_TX_CTRL (SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET)
|
||||
#define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET)
|
||||
#define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET)
|
||||
#define SPI_HIMR (SPI_REG_HIMR | SPI_LOCAL_OFFSET)
|
||||
#define SPI_HISR (SPI_REG_HISR | SPI_LOCAL_OFFSET)
|
||||
#define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET)
|
||||
#define SPI_FREE_TXPG (SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET)
|
||||
|
||||
#define SPI_HIMR_DISABLED 0
|
||||
|
||||
/* SPI HIMR MASK diff with SDIO */
|
||||
#define SPI_HISR_RX_REQUEST BIT(0)
|
||||
#define SPI_HISR_AVAL BIT(1)
|
||||
#define SPI_HISR_TXERR BIT(2)
|
||||
#define SPI_HISR_RXERR BIT(3)
|
||||
#define SPI_HISR_TXFOVW BIT(4)
|
||||
#define SPI_HISR_RXFOVW BIT(5)
|
||||
#define SPI_HISR_TXBCNOK BIT(6)
|
||||
#define SPI_HISR_TXBCNERR BIT(7)
|
||||
#define SPI_HISR_BCNERLY_INT BIT(16)
|
||||
#define SPI_HISR_ATIMEND BIT(17)
|
||||
#define SPI_HISR_ATIMEND_E BIT(18)
|
||||
#define SPI_HISR_CTWEND BIT(19)
|
||||
#define SPI_HISR_C2HCMD BIT(20)
|
||||
#define SPI_HISR_CPWM1 BIT(21)
|
||||
#define SPI_HISR_CPWM2 BIT(22)
|
||||
#define SPI_HISR_HSISR_IND BIT(23)
|
||||
#define SPI_HISR_GTINT3_IND BIT(24)
|
||||
#define SPI_HISR_GTINT4_IND BIT(25)
|
||||
#define SPI_HISR_PSTIMEOUT BIT(26)
|
||||
#define SPI_HISR_OCPINT BIT(27)
|
||||
#define SPI_HISR_TSF_BIT32_TOGGLE BIT(29)
|
||||
|
||||
#define MASK_SPI_HISR_CLEAR (SPI_HISR_TXERR |\
|
||||
SPI_HISR_RXERR |\
|
||||
SPI_HISR_TXFOVW |\
|
||||
SPI_HISR_RXFOVW |\
|
||||
SPI_HISR_TXBCNOK |\
|
||||
SPI_HISR_TXBCNERR |\
|
||||
SPI_HISR_C2HCMD |\
|
||||
SPI_HISR_CPWM1 |\
|
||||
SPI_HISR_CPWM2 |\
|
||||
SPI_HISR_HSISR_IND |\
|
||||
SPI_HISR_GTINT3_IND |\
|
||||
SPI_HISR_GTINT4_IND |\
|
||||
SPI_HISR_PSTIMEOUT |\
|
||||
SPI_HISR_OCPINT)
|
||||
|
||||
#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */
|
||||
#define REG_ADDR_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */
|
||||
#define REG_DOMAIN_ID_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
|
||||
#define REG_FUN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
|
||||
#define REG_RW_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
|
||||
|
||||
#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24)
|
||||
* #define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */
|
||||
#define FIFO_DOMAIN_ID_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
|
||||
#define FIFO_FUN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
|
||||
#define FIFO_RW_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
|
||||
|
||||
|
||||
/* get status dword0 */
|
||||
#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8)
|
||||
#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6)
|
||||
#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6)
|
||||
#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6)
|
||||
#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6)
|
||||
|
||||
/* get status dword1 */
|
||||
#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8)
|
||||
#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8)
|
||||
#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1)
|
||||
#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1)
|
||||
#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16)
|
||||
|
||||
|
||||
#define RXDESC_SIZE 24
|
||||
|
||||
|
||||
struct spi_more_data {
|
||||
unsigned long more_data;
|
||||
unsigned long len;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_RTL8188E
|
||||
void rtl8188es_set_hal_ops(PADAPTER padapter);
|
||||
#define set_hal_ops rtl8188es_set_hal_ops
|
||||
#endif
|
||||
extern void spi_set_chip_endian(PADAPTER padapter);
|
||||
extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big);
|
||||
extern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
|
||||
extern void spi_set_chip_endian(PADAPTER padapter);
|
||||
extern void InitInterrupt8723ASdio(PADAPTER padapter);
|
||||
extern void InitSysInterrupt8723ASdio(PADAPTER padapter);
|
||||
extern void EnableInterrupt8723ASdio(PADAPTER padapter);
|
||||
extern void DisableInterrupt8723ASdio(PADAPTER padapter);
|
||||
extern void spi_int_hdl(PADAPTER padapter);
|
||||
extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);
|
||||
#ifdef CONFIG_RTL8723B
|
||||
extern void InitInterrupt8723BSdio(PADAPTER padapter);
|
||||
extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
|
||||
extern void EnableInterrupt8723BSdio(PADAPTER padapter);
|
||||
extern void DisableInterrupt8723BSdio(PADAPTER padapter);
|
||||
extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8188E
|
||||
extern void InitInterrupt8188EGspi(PADAPTER padapter);
|
||||
extern void EnableInterrupt8188EGspi(PADAPTER padapter);
|
||||
extern void DisableInterrupt8188EGspi(PADAPTER padapter);
|
||||
extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
|
||||
extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter);
|
||||
extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter);
|
||||
extern void ClearInterrupt8188EGspi(PADAPTER padapter);
|
||||
extern u8 CheckIPSStatus(PADAPTER padapter);
|
||||
#endif /* CONFIG_RTL8188E */
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
extern u8 RecvOnePkt(PADAPTER padapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
#endif /* __GSPI_OPS_H__ */
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __SDIO_OPS_LINUX_H__
|
||||
#define __SDIO_OPS_LINUX_H__
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __SDIO_OSINTF_H__
|
||||
#define __SDIO_OSINTF_H__
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
#define _H2CLBK_H_
|
||||
|
||||
|
||||
void _lbk_cmd(PADAPTER Adapter);
|
||||
|
||||
void _lbk_rsp(PADAPTER Adapter);
|
||||
|
||||
void _lbk_evt(PADAPTER Adapter);
|
||||
|
||||
void h2c_event_callback(unsigned char *dev, unsigned char *pbuf);
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2013 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_BTCOEX_H__
|
||||
#define __HAL_BTCOEX_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
/* Some variables can't get from outsrc BT-Coex,
|
||||
* so we need to save here */
|
||||
typedef struct _BT_COEXIST {
|
||||
u8 bBtExist;
|
||||
u8 btTotalAntNum;
|
||||
u8 btChipType;
|
||||
u8 bInitlized;
|
||||
u8 btAntisolation;
|
||||
} BT_COEXIST, *PBT_COEXIST;
|
||||
|
||||
void DBG_BT_INFO(u8 *dbgmsg);
|
||||
|
||||
void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist);
|
||||
u8 hal_btcoex_IsBtExist(PADAPTER padapter);
|
||||
u8 hal_btcoex_IsBtDisabled(PADAPTER);
|
||||
void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType);
|
||||
void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum);
|
||||
|
||||
u8 hal_btcoex_Initialize(PADAPTER padapter);
|
||||
void hal_btcoex_PowerOnSetting(PADAPTER padapter);
|
||||
void hal_btcoex_AntInfoSetting(PADAPTER padapter);
|
||||
void hal_btcoex_PowerOffSetting(PADAPTER padapter);
|
||||
void hal_btcoex_PreLoadFirmware(PADAPTER padapter);
|
||||
void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly);
|
||||
|
||||
void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type);
|
||||
void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type);
|
||||
void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type);
|
||||
void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action);
|
||||
void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus);
|
||||
void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType);
|
||||
void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state);
|
||||
void hal_btcoex_WLRFKNotify(PADAPTER padapter, u8 path, u8 type, u8 state);
|
||||
void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
|
||||
void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf);
|
||||
void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state);
|
||||
void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt);
|
||||
void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter);
|
||||
|
||||
void hal_btcoex_Hanlder(PADAPTER padapter);
|
||||
|
||||
s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter);
|
||||
s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter);
|
||||
u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter);
|
||||
void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual);
|
||||
void hal_btcoex_set_policy_control(PADAPTER padapter, u8 btc_policy);
|
||||
u8 hal_btcoex_1Ant(PADAPTER padapter);
|
||||
u8 hal_btcoex_IsBtControlLps(PADAPTER);
|
||||
u8 hal_btcoex_IsLpsOn(PADAPTER);
|
||||
u8 hal_btcoex_RpwmVal(PADAPTER);
|
||||
u8 hal_btcoex_LpsVal(PADAPTER);
|
||||
u32 hal_btcoex_GetRaMask(PADAPTER);
|
||||
u8 hal_btcoex_query_reduced_wl_pwr_lvl(PADAPTER padapter);
|
||||
void hal_btcoex_set_reduced_wl_pwr_lvl(PADAPTER padapter, u8 val);
|
||||
void hal_btcoex_do_reduce_wl_pwr_lvl(PADAPTER padapter);
|
||||
void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen);
|
||||
void hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize);
|
||||
void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule);
|
||||
u32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize);
|
||||
u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER);
|
||||
u8 hal_btcoex_IsBtLinkExist(PADAPTER);
|
||||
void hal_btcoex_SetBtPatchVersion(PADAPTER, u16 btHciVer, u16 btPatchVer);
|
||||
void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion);
|
||||
void hal_btcoex_SendScanNotify(PADAPTER, u8 type);
|
||||
void hal_btcoex_StackUpdateProfileInfo(void);
|
||||
void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON);
|
||||
void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype);
|
||||
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
|
||||
int hal_btcoex_AntIsolationConfig_ParaFile(PADAPTER Adapter, char *pFileName);
|
||||
int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char *buffer);
|
||||
#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
|
||||
u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data);
|
||||
u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val);
|
||||
void hal_btcoex_set_rfe_type(u8 type);
|
||||
void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type);
|
||||
void hal_btcoex_WlFwDbgInfoNotify(PADAPTER padapter, u8* tmpBuf, u8 length);
|
||||
void hal_btcoex_rx_rate_change_notify(PADAPTER padapter, u8 is_data_frame, u8 rate_id);
|
||||
u16 hal_btcoex_btset_testode(PADAPTER padapter, u8 type);
|
||||
|
||||
#ifdef CONFIG_RF4CE_COEXIST
|
||||
void hal_btcoex_set_rf4ce_link_state(u8 state);
|
||||
u8 hal_btcoex_get_rf4ce_link_state(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#include <hal_sdio_coex.h> /* sdio multi coex */
|
||||
#endif
|
||||
|
||||
#endif /* !__HAL_BTCOEX_H__ */
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2016 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HALBTC_WIFIONLY_H__
|
||||
#define __HALBTC_WIFIONLY_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
#include <hal_data.h>
|
||||
|
||||
/* Define the ICs that support wifi only cfg in coex. codes */
|
||||
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
|
||||
|| defined(CONFIG_RTL8723F)
|
||||
#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 1
|
||||
#else
|
||||
#define CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG 0
|
||||
#endif
|
||||
|
||||
/* Define the ICs that support hal btc common file structure */
|
||||
#if defined(CONFIG_RTL8822C) || (defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723F)&& defined(CONFIG_BT_COEXIST))
|
||||
#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 1
|
||||
#else
|
||||
#define CONFIG_BTCOEX_SUPPORT_BTC_CMN 0
|
||||
#endif
|
||||
|
||||
#if (CONFIG_BTCOEX_SUPPORT_WIFI_ONLY_CFG == 1)
|
||||
|
||||
typedef enum _WIFIONLY_CHIP_INTERFACE {
|
||||
WIFIONLY_INTF_UNKNOWN = 0,
|
||||
WIFIONLY_INTF_PCI = 1,
|
||||
WIFIONLY_INTF_USB = 2,
|
||||
WIFIONLY_INTF_SDIO = 3,
|
||||
WIFIONLY_INTF_MAX
|
||||
} WIFIONLY_CHIP_INTERFACE, *PWIFIONLY_CHIP_INTERFACE;
|
||||
|
||||
typedef enum _WIFIONLY_CUSTOMER_ID {
|
||||
CUSTOMER_NORMAL = 0,
|
||||
CUSTOMER_HP_1 = 1
|
||||
} WIFIONLY_CUSTOMER_ID, *PWIFIONLY_CUSTOMER_ID;
|
||||
|
||||
struct wifi_only_haldata {
|
||||
u16 customer_id;
|
||||
u8 efuse_pg_antnum;
|
||||
u8 efuse_pg_antpath;
|
||||
u8 rfe_type;
|
||||
u8 ant_div_cfg;
|
||||
};
|
||||
|
||||
struct wifi_only_cfg {
|
||||
void *Adapter;
|
||||
struct wifi_only_haldata haldata_info;
|
||||
WIFIONLY_CHIP_INTERFACE chip_interface;
|
||||
};
|
||||
|
||||
void halwifionly_write1byte(void *pwifionlyContext, u32 RegAddr, u8 Data);
|
||||
void halwifionly_write2byte(void *pwifionlyContext, u32 RegAddr, u16 Data);
|
||||
void halwifionly_write4byte(void *pwifionlyContext, u32 RegAddr, u32 Data);
|
||||
u8 halwifionly_read1byte(void *pwifionlyContext, u32 RegAddr);
|
||||
u16 halwifionly_read2byte(void *pwifionlyContext, u32 RegAddr);
|
||||
u32 halwifionly_read4byte(void *pwifionlyContext, u32 RegAddr);
|
||||
void halwifionly_bitmaskwrite1byte(void *pwifionlyContext, u32 regAddr, u8 bitMask, u8 data);
|
||||
void halwifionly_phy_set_rf_reg(void *pwifionlyContext, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
void halwifionly_phy_set_bb_reg(void *pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter);
|
||||
void hal_btcoex_wifionly_scan_notify(PADAPTER padapter);
|
||||
void hal_btcoex_wifionly_connect_notify(PADAPTER padapter);
|
||||
void hal_btcoex_wifionly_hw_config(PADAPTER padapter);
|
||||
void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter);
|
||||
void hal_btcoex_wifionly_AntInfoSetting(PADAPTER padapter);
|
||||
#else
|
||||
#define hal_btcoex_wifionly_switchband_notify(padapter)
|
||||
#define hal_btcoex_wifionly_scan_notify(padapter)
|
||||
#define hal_btcoex_wifionly_connect_notify(padapter)
|
||||
#define hal_btcoex_wifionly_hw_config(padapter)
|
||||
#define hal_btcoex_wifionly_initlizevariables(padapter)
|
||||
#define hal_btcoex_wifionly_AntInfoSetting(padapter)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,736 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_COMMON_H__
|
||||
#define __HAL_COMMON_H__
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_pg.h"
|
||||
#include "hal_phy.h"
|
||||
#include "hal_phy_reg.h"
|
||||
#include "hal_com_reg.h"
|
||||
#include "hal_com_phycfg.h"
|
||||
#include "../hal/hal_com_c2h.h"
|
||||
|
||||
/*------------------------------ Tx Desc definition Macro ------------------------*/
|
||||
/* #pragma mark -- Tx Desc related definition. -- */
|
||||
/* ----------------------------------------------------------------------------
|
||||
* -----------------------------------------------------------
|
||||
* Rate
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC_RATE1M 0x00
|
||||
#define DESC_RATE2M 0x01
|
||||
#define DESC_RATE5_5M 0x02
|
||||
#define DESC_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC_RATE6M 0x04
|
||||
#define DESC_RATE9M 0x05
|
||||
#define DESC_RATE12M 0x06
|
||||
#define DESC_RATE18M 0x07
|
||||
#define DESC_RATE24M 0x08
|
||||
#define DESC_RATE36M 0x09
|
||||
#define DESC_RATE48M 0x0a
|
||||
#define DESC_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC_RATEMCS0 0x0c
|
||||
#define DESC_RATEMCS1 0x0d
|
||||
#define DESC_RATEMCS2 0x0e
|
||||
#define DESC_RATEMCS3 0x0f
|
||||
#define DESC_RATEMCS4 0x10
|
||||
#define DESC_RATEMCS5 0x11
|
||||
#define DESC_RATEMCS6 0x12
|
||||
#define DESC_RATEMCS7 0x13
|
||||
#define DESC_RATEMCS8 0x14
|
||||
#define DESC_RATEMCS9 0x15
|
||||
#define DESC_RATEMCS10 0x16
|
||||
#define DESC_RATEMCS11 0x17
|
||||
#define DESC_RATEMCS12 0x18
|
||||
#define DESC_RATEMCS13 0x19
|
||||
#define DESC_RATEMCS14 0x1a
|
||||
#define DESC_RATEMCS15 0x1b
|
||||
#define DESC_RATEMCS16 0x1C
|
||||
#define DESC_RATEMCS17 0x1D
|
||||
#define DESC_RATEMCS18 0x1E
|
||||
#define DESC_RATEMCS19 0x1F
|
||||
#define DESC_RATEMCS20 0x20
|
||||
#define DESC_RATEMCS21 0x21
|
||||
#define DESC_RATEMCS22 0x22
|
||||
#define DESC_RATEMCS23 0x23
|
||||
#define DESC_RATEMCS24 0x24
|
||||
#define DESC_RATEMCS25 0x25
|
||||
#define DESC_RATEMCS26 0x26
|
||||
#define DESC_RATEMCS27 0x27
|
||||
#define DESC_RATEMCS28 0x28
|
||||
#define DESC_RATEMCS29 0x29
|
||||
#define DESC_RATEMCS30 0x2A
|
||||
#define DESC_RATEMCS31 0x2B
|
||||
#define DESC_RATEVHTSS1MCS0 0x2C
|
||||
#define DESC_RATEVHTSS1MCS1 0x2D
|
||||
#define DESC_RATEVHTSS1MCS2 0x2E
|
||||
#define DESC_RATEVHTSS1MCS3 0x2F
|
||||
#define DESC_RATEVHTSS1MCS4 0x30
|
||||
#define DESC_RATEVHTSS1MCS5 0x31
|
||||
#define DESC_RATEVHTSS1MCS6 0x32
|
||||
#define DESC_RATEVHTSS1MCS7 0x33
|
||||
#define DESC_RATEVHTSS1MCS8 0x34
|
||||
#define DESC_RATEVHTSS1MCS9 0x35
|
||||
#define DESC_RATEVHTSS2MCS0 0x36
|
||||
#define DESC_RATEVHTSS2MCS1 0x37
|
||||
#define DESC_RATEVHTSS2MCS2 0x38
|
||||
#define DESC_RATEVHTSS2MCS3 0x39
|
||||
#define DESC_RATEVHTSS2MCS4 0x3A
|
||||
#define DESC_RATEVHTSS2MCS5 0x3B
|
||||
#define DESC_RATEVHTSS2MCS6 0x3C
|
||||
#define DESC_RATEVHTSS2MCS7 0x3D
|
||||
#define DESC_RATEVHTSS2MCS8 0x3E
|
||||
#define DESC_RATEVHTSS2MCS9 0x3F
|
||||
#define DESC_RATEVHTSS3MCS0 0x40
|
||||
#define DESC_RATEVHTSS3MCS1 0x41
|
||||
#define DESC_RATEVHTSS3MCS2 0x42
|
||||
#define DESC_RATEVHTSS3MCS3 0x43
|
||||
#define DESC_RATEVHTSS3MCS4 0x44
|
||||
#define DESC_RATEVHTSS3MCS5 0x45
|
||||
#define DESC_RATEVHTSS3MCS6 0x46
|
||||
#define DESC_RATEVHTSS3MCS7 0x47
|
||||
#define DESC_RATEVHTSS3MCS8 0x48
|
||||
#define DESC_RATEVHTSS3MCS9 0x49
|
||||
#define DESC_RATEVHTSS4MCS0 0x4A
|
||||
#define DESC_RATEVHTSS4MCS1 0x4B
|
||||
#define DESC_RATEVHTSS4MCS2 0x4C
|
||||
#define DESC_RATEVHTSS4MCS3 0x4D
|
||||
#define DESC_RATEVHTSS4MCS4 0x4E
|
||||
#define DESC_RATEVHTSS4MCS5 0x4F
|
||||
#define DESC_RATEVHTSS4MCS6 0x50
|
||||
#define DESC_RATEVHTSS4MCS7 0x51
|
||||
#define DESC_RATEVHTSS4MCS8 0x52
|
||||
#define DESC_RATEVHTSS4MCS9 0x53
|
||||
#define DESC_RATE_NUM 0x54
|
||||
|
||||
#define IS_CCK_HRATE(_rate) ((_rate) <= DESC_RATE11M)
|
||||
#define IS_OFDM_HRATE(_rate) ((_rate) >= DESC_RATE6M && (_rate) <= DESC_RATE54M)
|
||||
#define IS_LEGACY_HRATE(_rate) ((_rate) <= DESC_RATE54M)
|
||||
#define IS_HT_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS31)
|
||||
#define IS_VHT_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
|
||||
|
||||
#define IS_HT1SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS0 && (_rate) <= DESC_RATEMCS7)
|
||||
#define IS_HT2SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS8 && (_rate) <= DESC_RATEMCS15)
|
||||
#define IS_HT3SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS16 && (_rate) <= DESC_RATEMCS23)
|
||||
#define IS_HT4SS_HRATE(_rate) ((_rate) >= DESC_RATEMCS24 && (_rate) <= DESC_RATEMCS31)
|
||||
|
||||
#define IS_VHT1SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS1MCS0 && (_rate) <= DESC_RATEVHTSS1MCS9)
|
||||
#define IS_VHT2SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS2MCS0 && (_rate) <= DESC_RATEVHTSS2MCS9)
|
||||
#define IS_VHT3SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS3MCS0 && (_rate) <= DESC_RATEVHTSS3MCS9)
|
||||
#define IS_VHT4SS_HRATE(_rate) ((_rate) >= DESC_RATEVHTSS4MCS0 && (_rate) <= DESC_RATEVHTSS4MCS9)
|
||||
|
||||
#define IS_1SS_HRATE(_rate) (IS_CCK_HRATE((_rate)) || IS_OFDM_HRATE((_rate)) || IS_HT1SS_HRATE((_rate)) || IS_VHT1SS_HRATE((_rate)))
|
||||
#define IS_2SS_HRATE(_rate) (IS_HT2SS_HRATE((_rate)) || IS_VHT2SS_HRATE((_rate)))
|
||||
#define IS_3SS_HRATE(_rate) (IS_HT3SS_HRATE((_rate)) || IS_VHT3SS_HRATE((_rate)))
|
||||
#define IS_4SS_HRATE(_rate) (IS_HT4SS_HRATE((_rate)) || IS_VHT4SS_HRATE((_rate)))
|
||||
|
||||
#define HRARE_SS_NUM(_rate) (IS_1SS_HRATE(_rate) ? 1 : (IS_2SS_HRATE(_rate) ? 2 : (IS_3SS_HRATE(_rate) ? 3 : (IS_4SS_HRATE(_rate) ? 4 : 0))))
|
||||
|
||||
extern const char * const _HDATA_RATE[];
|
||||
#define HDATA_RATE(rate) ((rate) >= DESC_RATE_NUM ? _HDATA_RATE[DESC_RATE_NUM] : _HDATA_RATE[rate])
|
||||
|
||||
enum {
|
||||
UP_LINK,
|
||||
DOWN_LINK,
|
||||
};
|
||||
typedef enum _RT_MEDIA_STATUS {
|
||||
RT_MEDIA_DISCONNECT = 0,
|
||||
RT_MEDIA_CONNECT = 1
|
||||
} RT_MEDIA_STATUS;
|
||||
|
||||
#define MAX_DLFW_PAGE_SIZE 4096 /* @ page : 4k bytes */
|
||||
typedef enum _FIRMWARE_SOURCE {
|
||||
FW_SOURCE_IMG_FILE = 0,
|
||||
FW_SOURCE_HEADER_FILE = 1, /* from header file */
|
||||
} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
|
||||
|
||||
typedef enum _CH_SW_USE_CASE {
|
||||
CH_SW_USE_CASE_TDLS = 0,
|
||||
CH_SW_USE_CASE_MCC = 1
|
||||
} CH_SW_USE_CASE;
|
||||
|
||||
typedef enum _WAKEUP_REASON{
|
||||
RX_PAIRWISEKEY = 0x01,
|
||||
RX_GTK = 0x02,
|
||||
RX_FOURWAY_HANDSHAKE = 0x03,
|
||||
RX_DISASSOC = 0x04,
|
||||
RX_DEAUTH = 0x08,
|
||||
RX_ARP_REQUEST = 0x09,
|
||||
FW_DECISION_DISCONNECT = 0x10,
|
||||
RX_MAGIC_PKT = 0x21,
|
||||
RX_UNICAST_PKT = 0x22,
|
||||
RX_PATTERN_PKT = 0x23,
|
||||
RTD3_SSID_MATCH = 0x24,
|
||||
RX_REALWOW_V2_WAKEUP_PKT = 0x30,
|
||||
RX_REALWOW_V2_ACK_LOST = 0x31,
|
||||
ENABLE_FAIL_DMA_IDLE = 0x40,
|
||||
ENABLE_FAIL_DMA_PAUSE = 0x41,
|
||||
RTIME_FAIL_DMA_IDLE = 0x42,
|
||||
RTIME_FAIL_DMA_PAUSE = 0x43,
|
||||
RX_PNO = 0x55,
|
||||
#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
|
||||
WOW_KEEPALIVE_ACK_TIMEOUT = 0x60,
|
||||
WOW_KEEPALIVE_WAKE = 0x61,
|
||||
#endif/*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
|
||||
AP_OFFLOAD_WAKEUP = 0x66,
|
||||
CLK_32K_UNLOCK = 0xFD,
|
||||
CLK_32K_LOCK = 0xFE
|
||||
}WAKEUP_REASON;
|
||||
|
||||
typedef enum _BCN_EARLY_INT_CASE{
|
||||
TDLS_BCN_ERLY_ON,
|
||||
TDLS_BCN_ERLY_OFF
|
||||
}BCN_EARLY_INT_CASE;
|
||||
|
||||
/*
|
||||
* Queue Select Value in TxDesc
|
||||
* */
|
||||
#define QSLT_BK 0x2/* 0x01 */
|
||||
#define QSLT_BE 0x0
|
||||
#define QSLT_VI 0x5/* 0x4 */
|
||||
#define QSLT_VO 0x7/* 0x6 */
|
||||
#define QSLT_BEACON 0x10
|
||||
#define QSLT_HIGH 0x11
|
||||
#define QSLT_MGNT 0x12
|
||||
#define QSLT_CMD 0x13
|
||||
|
||||
/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
|
||||
* #define MAX_TX_QUEUE 9 */
|
||||
|
||||
#define TX_SELE_HQ BIT(0) /* High Queue */
|
||||
#define TX_SELE_LQ BIT(1) /* Low Queue */
|
||||
#define TX_SELE_NQ BIT(2) /* Normal Queue */
|
||||
#define TX_SELE_EQ BIT(3) /* Extern Queue */
|
||||
|
||||
#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
|
||||
#define PageNum_256(_Len) (u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0))
|
||||
#define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0))
|
||||
#define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0))
|
||||
|
||||
struct dbg_rx_counter {
|
||||
u32 rx_pkt_ok;
|
||||
u32 rx_pkt_crc_error;
|
||||
u32 rx_pkt_drop;
|
||||
u32 rx_ofdm_fa;
|
||||
u32 rx_cck_fa;
|
||||
u32 rx_ht_fa;
|
||||
};
|
||||
|
||||
u8 rtw_hal_get_port(_adapter *adapter);
|
||||
|
||||
#ifdef CONFIG_MBSSID_CAM
|
||||
/*#define DBG_MBID_CAM_DUMP*/
|
||||
|
||||
void rtw_mbid_cam_init(struct dvobj_priv *dvobj);
|
||||
void rtw_mbid_cam_deinit(struct dvobj_priv *dvobj);
|
||||
void rtw_mbid_cam_reset(_adapter *adapter);
|
||||
u8 rtw_get_max_mbid_cam_id(_adapter *adapter);
|
||||
u8 rtw_get_mbid_cam_entry_num(_adapter *adapter);
|
||||
int rtw_mbid_cam_cache_dump(void *sel, const char *fun_name , _adapter *adapter);
|
||||
int rtw_mbid_cam_dump(void *sel, const char *fun_name, _adapter *adapter);
|
||||
void rtw_mi_set_mbid_cam(_adapter *adapter);
|
||||
u8 rtw_mbid_camid_alloc(_adapter *adapter, u8 *mac_addr);
|
||||
void rtw_ap_set_mbid_num(_adapter *adapter, u8 ap_num);
|
||||
void rtw_mbid_cam_enable(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MI_WITH_MBSSID_CAM
|
||||
void rtw_hal_set_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
|
||||
void rtw_hal_change_macaddr_mbid(_adapter *adapter, u8 *mac_addr);
|
||||
#ifdef CONFIG_SWTIMER_BASED_TXBCN
|
||||
u16 rtw_hal_bcn_interval_adjust(_adapter *adapter, u16 bcn_interval);
|
||||
#endif
|
||||
void hw_var_set_opmode_mbid(_adapter *Adapter, u8 mode);
|
||||
#endif
|
||||
|
||||
void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
|
||||
void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter);
|
||||
void rtw_reset_mac_rx_counters(_adapter *padapter);
|
||||
void rtw_reset_phy_rx_counters(_adapter *padapter);
|
||||
void rtw_reset_phy_trx_ok_counters(_adapter *padapter);
|
||||
|
||||
#ifdef DBG_RX_COUNTER_DUMP
|
||||
#define DUMP_DRV_RX_COUNTER BIT0
|
||||
#define DUMP_MAC_RX_COUNTER BIT1
|
||||
#define DUMP_PHY_RX_COUNTER BIT2
|
||||
#define DUMP_DRV_TRX_COUNTER_DATA BIT3
|
||||
|
||||
void rtw_dump_phy_rxcnts_preprocess(_adapter *padapter, u8 rx_cnt_mode);
|
||||
void rtw_dump_rx_counters(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
void dump_chip_info(HAL_VERSION ChipVersion);
|
||||
|
||||
#define BAND_CAP_2G BIT0
|
||||
#define BAND_CAP_5G BIT1
|
||||
#define BAND_CAP_BIT_NUM 2
|
||||
|
||||
#define BW_CAP_5M BIT0
|
||||
#define BW_CAP_10M BIT1
|
||||
#define BW_CAP_20M BIT2
|
||||
#define BW_CAP_40M BIT3
|
||||
#define BW_CAP_80M BIT4
|
||||
#define BW_CAP_160M BIT5
|
||||
#define BW_CAP_80_80M BIT6
|
||||
#define BW_CAP_BIT_NUM 7
|
||||
|
||||
#define PROTO_CAP_11B BIT0
|
||||
#define PROTO_CAP_11G BIT1
|
||||
#define PROTO_CAP_11N BIT2
|
||||
#define PROTO_CAP_11AC BIT3
|
||||
#define PROTO_CAP_BIT_NUM 4
|
||||
|
||||
#define WL_FUNC_P2P BIT0
|
||||
#define WL_FUNC_MIRACAST BIT1
|
||||
#define WL_FUNC_TDLS BIT2
|
||||
#define WL_FUNC_FTM BIT3
|
||||
#define WL_FUNC_BIT_NUM 4
|
||||
|
||||
#define TBTT_PROHIBIT_SETUP_TIME 0x04 /* 128us, unit is 32us */
|
||||
#define TBTT_PROHIBIT_HOLD_TIME 0x80 /* 4ms, unit is 32us*/
|
||||
#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 /* 3.2ms unit is 32us*/
|
||||
|
||||
int hal_spec_init(_adapter *adapter);
|
||||
void dump_hal_spec(void *sel, _adapter *adapter);
|
||||
|
||||
bool hal_chk_band_cap(_adapter *adapter, u8 cap);
|
||||
bool hal_chk_bw_cap(_adapter *adapter, u8 cap);
|
||||
bool hal_chk_proto_cap(_adapter *adapter, u8 cap);
|
||||
bool hal_is_band_support(_adapter *adapter, u8 band);
|
||||
bool hal_is_bw_support(_adapter *adapter, u8 bw);
|
||||
bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode);
|
||||
bool hal_is_mimo_support(_adapter *adapter);
|
||||
u8 hal_largest_bw(_adapter *adapter, u8 in_bw);
|
||||
|
||||
bool hal_chk_wl_func(_adapter *adapter, u8 func);
|
||||
|
||||
void hal_com_config_channel_plan(
|
||||
PADAPTER padapter,
|
||||
char *hw_alpha2,
|
||||
u8 hw_chplan,
|
||||
char *sw_alpha2,
|
||||
u8 sw_chplan,
|
||||
BOOLEAN AutoLoadFail
|
||||
);
|
||||
|
||||
int hal_config_macaddr(_adapter *adapter, bool autoload_fail);
|
||||
#ifdef RTW_HALMAC
|
||||
void rtw_hal_hw_port_enable(_adapter *adapter);
|
||||
void rtw_hal_hw_port_disable(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
BOOLEAN
|
||||
HAL_IsLegalChannel(
|
||||
PADAPTER Adapter,
|
||||
u32 Channel
|
||||
);
|
||||
|
||||
u8 MRateToHwRate(enum MGN_RATE rate);
|
||||
|
||||
u8 hw_rate_to_m_rate(u8 hw_rate);
|
||||
#ifdef CONFIG_RTW_DEBUG
|
||||
void dump_hw_rate_map_test(void *sel);
|
||||
#endif
|
||||
|
||||
void HalSetBrateCfg(
|
||||
PADAPTER Adapter,
|
||||
u8 *mBratesOS,
|
||||
u16 *pBrateCfg);
|
||||
|
||||
BOOLEAN
|
||||
Hal_MappingOutPipe(
|
||||
PADAPTER pAdapter,
|
||||
u8 NumOutPipe
|
||||
);
|
||||
|
||||
void rtw_dump_fw_info(void *sel, _adapter *adapter);
|
||||
void rtw_restore_hw_port_cfg(_adapter *adapter);
|
||||
void rtw_mi_set_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/
|
||||
void rtw_hal_dump_macaddr(void *sel, _adapter *adapter);
|
||||
|
||||
void rtw_init_hal_com_default_value(PADAPTER Adapter);
|
||||
|
||||
#ifdef CONFIG_FW_C2H_REG
|
||||
void c2h_evt_clear(_adapter *adapter);
|
||||
s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_PKT
|
||||
void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len);
|
||||
void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len);
|
||||
#endif
|
||||
|
||||
u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type);
|
||||
|
||||
void rtw_hal_update_sta_wset(_adapter *adapter, struct sta_info *psta);
|
||||
s8 rtw_get_sta_rx_nss(_adapter *adapter, struct sta_info *psta);
|
||||
s8 rtw_get_sta_tx_nss(_adapter *adapter, struct sta_info *psta);
|
||||
void rtw_hal_update_sta_ra_info(PADAPTER padapter, struct sta_info *psta);
|
||||
|
||||
/* access HW only */
|
||||
u32 rtw_sec_read_cam(_adapter *adapter, u8 addr);
|
||||
void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata);
|
||||
void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key);
|
||||
void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key);
|
||||
void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id);
|
||||
bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id);
|
||||
|
||||
u8 rtw_hal_rcr_check(_adapter *adapter, u32 check_bit);
|
||||
|
||||
u8 rtw_hal_rcr_add(_adapter *adapter, u32 add);
|
||||
u8 rtw_hal_rcr_clear(_adapter *adapter, u32 clear);
|
||||
void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action);
|
||||
void rtw_hal_rcr_set_chk_bssid_act_non(_adapter *adapter);
|
||||
|
||||
void rtw_iface_enable_tsf_update(_adapter *adapter);
|
||||
void rtw_iface_disable_tsf_update(_adapter *adapter);
|
||||
void rtw_hal_periodic_tsf_update_chk(_adapter *adapter);
|
||||
void rtw_hal_periodic_tsf_update_end_timer_hdl(void *ctx);
|
||||
|
||||
#if CONFIG_TX_AC_LIFETIME
|
||||
#define TX_ACLT_CONF_DEFAULT 0
|
||||
#define TX_ACLT_CONF_AP_M2U 1
|
||||
#define TX_ACLT_CONF_MESH 2
|
||||
#define TX_ACLT_CONF_NUM 3
|
||||
|
||||
extern const char *const _tx_aclt_conf_str[];
|
||||
#define tx_aclt_conf_str(conf) (((conf) >= TX_ACLT_CONF_NUM) ? _tx_aclt_conf_str[TX_ACLT_CONF_NUM] : _tx_aclt_conf_str[(conf)])
|
||||
|
||||
struct tx_aclt_conf_t {
|
||||
u8 en;
|
||||
u32 vo_vi;
|
||||
u32 be_bk;
|
||||
};
|
||||
|
||||
void dump_tx_aclt_force_val(void *sel, struct dvobj_priv *dvobj);
|
||||
void rtw_hal_set_tx_aclt_force_val(_adapter *adapter, struct tx_aclt_conf_t *input, u8 arg_num);
|
||||
void dump_tx_aclt_confs(void *sel, struct dvobj_priv *dvobj);
|
||||
void rtw_hal_set_tx_aclt_conf(_adapter *adapter, u8 conf_idx, struct tx_aclt_conf_t *input, u8 arg_num);
|
||||
void rtw_hal_update_tx_aclt(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
void hw_var_port_switch(_adapter *adapter);
|
||||
void rtw_var_set_basic_rate(PADAPTER padapter, u8 *val);
|
||||
u8 SetHwReg(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void rtw_hal_check_rxfifo_full(_adapter *adapter);
|
||||
void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid);
|
||||
|
||||
u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
|
||||
u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value);
|
||||
|
||||
u32
|
||||
MapCharToHexDigit(
|
||||
char chTmp
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
GetHexValueFromString(
|
||||
char *szStr,
|
||||
u32 *pu4bVal,
|
||||
u32 *pu4bMove
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
GetFractionValueFromString(
|
||||
char *szStr,
|
||||
u8 *pInteger,
|
||||
u8 *pFraction,
|
||||
u32 *pu4bMove
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
IsCommentString(
|
||||
char *szStr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
ParseQualifiedString(
|
||||
char *In,
|
||||
u32 *Start,
|
||||
char *Out,
|
||||
char LeftQualifier,
|
||||
char RightQualifier
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
GetU1ByteIntegerFromStringInDecimal(
|
||||
char *Str,
|
||||
u8 *pInt
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
isAllSpaceOrTab(
|
||||
u8 *data,
|
||||
u8 size
|
||||
);
|
||||
|
||||
void linked_info_dump(_adapter *padapter, u8 benable);
|
||||
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
|
||||
void rtw_get_raw_rssi_info(void *sel, _adapter *padapter);
|
||||
void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel);
|
||||
#endif
|
||||
|
||||
#ifdef DBG_RX_DFRAME_RAW_DATA
|
||||
void rtw_dump_rx_dframe_info(_adapter *padapter, void *sel);
|
||||
#endif
|
||||
void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe);
|
||||
#define HWSET_MAX_SIZE 1024
|
||||
|
||||
#ifdef CONFIG_EFUSE_CONFIG_FILE
|
||||
u32 Hal_readPGDataFromConfigFile(PADAPTER padapter);
|
||||
u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr);
|
||||
#endif /* CONFIG_EFUSE_CONFIG_FILE */
|
||||
|
||||
int hal_efuse_macaddr_offset(_adapter *adapter);
|
||||
int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr);
|
||||
void rtw_dump_cur_efuse(PADAPTER padapter);
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
void rtw_bb_rf_gain_offset(_adapter *padapter);
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer);
|
||||
u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel);
|
||||
|
||||
u8 rtw_get_current_tx_rate(_adapter *padapter, struct sta_info *psta);
|
||||
u8 rtw_get_current_tx_sgi(_adapter *padapter, struct sta_info *psta);
|
||||
#ifdef CONFIG_CUSTOMER01_SMART_ANTENNA
|
||||
void rtw_hal_set_pathb_phase(_adapter *adapter, u8 phase_idx);
|
||||
#endif
|
||||
void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished);
|
||||
u8 rtw_hal_get_rsvd_page_num(struct _ADAPTER *adapter);
|
||||
|
||||
#ifdef CONFIG_TSF_RESET_OFFLOAD
|
||||
int rtw_hal_reset_tsf(_adapter *adapter, u8 reset_port);
|
||||
#endif
|
||||
u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port);
|
||||
|
||||
#ifdef CONFIG_TDLS
|
||||
#ifdef CONFIG_TDLS_CH_SW
|
||||
s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode);
|
||||
#endif
|
||||
#endif
|
||||
#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
|
||||
s32 rtw_hal_set_wifi_btc_port_id_cmd(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
void rtw_lps_state_chk(_adapter *adapter, u8 ps_mode);
|
||||
|
||||
#ifdef CONFIG_GPIO_API
|
||||
u8 rtw_hal_get_gpio(_adapter *adapter, u8 gpio_num);
|
||||
int rtw_hal_set_gpio_output_value(_adapter *adapter, u8 gpio_num, bool isHigh);
|
||||
int rtw_hal_config_gpio(_adapter *adapter, u8 gpio_num, bool isOutput);
|
||||
int rtw_hal_register_gpio_interrupt(_adapter *adapter, int gpio_num, void(*callback)(u8 level));
|
||||
int rtw_hal_disable_gpio_interrupt(_adapter *adapter, int gpio_num);
|
||||
#endif
|
||||
|
||||
s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode);
|
||||
void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter);
|
||||
void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case);
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable);
|
||||
void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval);
|
||||
void rtw_hal_set_input_gpio(_adapter *padapter, u8 index);
|
||||
#define GPIO_OUTPUT_LOW 0
|
||||
#define GPIO_OUTPUT_HIGH 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
|
||||
extern char *rtw_phy_file_path;
|
||||
extern char rtw_phy_para_file_path[PATH_LENGTH_MAX];
|
||||
#define GetLineFromBuffer(buffer) strsep(&buffer, "\r\n")
|
||||
#endif
|
||||
|
||||
void update_IOT_info(_adapter *padapter);
|
||||
#ifdef CONFIG_RTS_FULL_BW
|
||||
void rtw_set_rts_bw(_adapter *padapter);
|
||||
#endif/*CONFIG_RTS_FULL_BW*/
|
||||
|
||||
void ResumeTxBeacon(_adapter *padapter);
|
||||
void StopTxBeacon(_adapter *padapter);
|
||||
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
u8 rtw_hal_antdiv_before_linked(_adapter *padapter);
|
||||
void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src);
|
||||
#endif
|
||||
|
||||
#ifdef DBG_SEC_CAM_MOVE
|
||||
void rtw_hal_move_sta_gk_to_dk(_adapter *adapter);
|
||||
void rtw_hal_read_sta_dk_key(_adapter *adapter, u8 key_id);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPS_PG
|
||||
#define LPSPG_RSVD_PAGE_SET_MACID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 0, 8, _value)/*used macid*/
|
||||
#define LPSPG_RSVD_PAGE_SET_MBSSCAMID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 8, 8, _value)/*used BSSID CAM entry*/
|
||||
#define LPSPG_RSVD_PAGE_SET_PMC_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 16, 8, _value)/*Max used Pattern Match CAM entry*/
|
||||
#define LPSPG_RSVD_PAGE_SET_MU_RAID_GID(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x00, 24, 8, _value)/*Max MU rate table Group ID*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 0, 8, _value)/*used Security CAM entry number*/
|
||||
#define LPSPG_RSVD_PAGE_SET_DRV_RSVDPAGE_NUM(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x04, 8, 8, _value)/*Txbuf used page number for fw offload*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID1(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 0, 8, _value)/*used Security CAM entry -1*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID2(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 8, 8, _value)/*used Security CAM entry -2*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID3(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 16, 8, _value)/*used Security CAM entry -3*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID4(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x08, 24, 8, _value)/*used Security CAM entry -4*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID5(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 0, 8, _value)/*used Security CAM entry -5*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID6(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 8, 8, _value)/*used Security CAM entry -6*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID7(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 16, 8, _value)/*used Security CAM entry -7*/
|
||||
#define LPSPG_RSVD_PAGE_SET_SEC_CAM_ID8(_rsvd_pag, _value) SET_BITS_TO_LE_4BYTE(_rsvd_pag+0x0C, 24, 8, _value)/*used Security CAM entry -8*/
|
||||
enum lps_pg_hdl_id {
|
||||
LPS_PG_INFO_CFG = 0,
|
||||
LPS_PG_REDLEMEM,
|
||||
LPS_PG_PHYDM_DIS,
|
||||
LPS_PG_PHYDM_EN,
|
||||
};
|
||||
|
||||
u8 rtw_hal_set_lps_pg_info_cmd(_adapter *adapter);
|
||||
u8 rtw_hal_set_lps_pg_info(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size);
|
||||
void rtw_hal_construct_beacon(_adapter *padapter, u8 *pframe, u32 *pLength);
|
||||
void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength,
|
||||
u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave);
|
||||
|
||||
bool _rtw_wow_chk_cap(_adapter *adapter, u8 cap);
|
||||
#ifdef CONFIG_WOWLAN
|
||||
struct rtl_wow_pattern {
|
||||
u16 crc;
|
||||
u8 type;
|
||||
u32 mask[4];
|
||||
};
|
||||
void rtw_wow_pattern_cam_dump(_adapter *adapter);
|
||||
|
||||
void rtw_dump_wow_pattern(void *sel, struct rtl_wow_pattern *pwow_pattern, u8 idx);
|
||||
#ifdef CONFIG_WOW_PATTERN_HW_CAM
|
||||
void rtw_wow_pattern_read_cam_ent(_adapter *adapter, u8 id, struct rtl_wow_pattern *context);
|
||||
#endif
|
||||
|
||||
struct rtw_ndp_info {
|
||||
u8 enable:1;
|
||||
u8 check_remote_ip:1; /* Need to Check Sender IP or not */
|
||||
u8 rsvd:6;
|
||||
u8 num_of_target_ip; /* Number of Check IP which NA query IP */
|
||||
u8 target_link_addr[6]; /* DUT's MAC address */
|
||||
u8 remote_ipv6_addr[16]; /* Just respond IP */
|
||||
u8 target_ipv6_addr[16]; /* target IP */
|
||||
};
|
||||
#define REMOTE_INFO_CTRL_SET_VALD_EN(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 0, 0, 8, _value)
|
||||
#define REMOTE_INFO_CTRL_SET_PTK_EN(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 1, 0, 1, _value)
|
||||
#define REMOTE_INFO_CTRL_SET_GTK_EN(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 1, 1, 1, _value)
|
||||
#define REMOTE_INFO_CTRL_SET_GTK_IDX(target, _value) \
|
||||
SET_BITS_TO_LE_4BYTE(target + 2, 0, 8, _value)
|
||||
#endif /*CONFIG_WOWLAN*/
|
||||
|
||||
#ifdef CONFIG_PROC_DEBUG
|
||||
void rtw_dump_phy_cap(void *sel, _adapter *adapter);
|
||||
#endif
|
||||
void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num);
|
||||
#ifdef CONFIG_SUPPORT_FIFO_DUMP
|
||||
void rtw_dump_fifo(void *sel, _adapter *adapter, u8 fifo_sel, u32 fifo_addr, u32 fifo_size);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
s32 rtw_hal_set_default_port_id_cmd(_adapter *adapter, u8 mac_id);
|
||||
s32 rtw_set_default_port_id(_adapter *adapter);
|
||||
s32 rtw_set_ps_rsvd_page(_adapter *adapter);
|
||||
|
||||
#define get_dft_portid(adapter) (adapter_to_dvobj(adapter)->dft.port_id)
|
||||
#define get_dft_macid(adapter) (adapter_to_dvobj(adapter)->dft.mac_id)
|
||||
|
||||
/*void rtw_search_default_port(_adapter *adapter);*/
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#ifdef RTW_HALMAC
|
||||
void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
void rtw_hal_switch_chnl_and_set_bw_offload(_adapter *adapter, u8 central_ch, u8 pri_ch_idx, u8 bw);
|
||||
#endif
|
||||
|
||||
s16 translate_dbm_to_percentage(s16 signal);
|
||||
|
||||
#ifdef CONFIG_SUPPORT_MULTI_BCN
|
||||
void rtw_ap_multi_bcn_cfg(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SWTIMER_BASED_TXBCN
|
||||
#ifdef CONFIG_BCN_RECOVERY
|
||||
u8 rtw_ap_bcn_recovery(_adapter *padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_BCN_XMIT_PROTECT
|
||||
u8 rtw_ap_bcn_queue_empty_check(_adapter *padapter, u32 txbcn_timer_ms);
|
||||
#endif
|
||||
#endif /*CONFIG_SWTIMER_BASED_TXBCN*/
|
||||
|
||||
#ifdef CONFIG_FW_HANDLE_TXBCN
|
||||
void rtw_ap_mbid_bcn_en(_adapter *adapter, u8 mbcn_id);
|
||||
void rtw_ap_mbid_bcn_dis(_adapter *adapter, u8 mbcn_id);
|
||||
#endif
|
||||
|
||||
void rtw_hal_get_trx_path(struct dvobj_priv *d, enum rf_type *type,
|
||||
enum bb_path *tx, enum bb_path *rx);
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#ifdef RTW_BEAMFORMING_VERSION_2
|
||||
void rtw_hal_beamforming_config_csirate(PADAPTER adapter);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
u8 phy_get_capable_tx_num(_adapter *adapter, enum MGN_RATE rate);
|
||||
u8 phy_get_current_tx_num(_adapter *adapter, enum MGN_RATE rate);
|
||||
|
||||
#ifdef CONFIG_RTL8812A
|
||||
u8 * rtw_hal_set_8812a_vendor_ie(_adapter *padapter , u8 *pframe ,uint *frlen );
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PROTSEL_PORT
|
||||
void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel);
|
||||
bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len);
|
||||
void rtw_leave_protsel_port(_adapter *padapter);
|
||||
#else
|
||||
static inline void rtw_enter_protsel_port(_adapter *padapter, u8 port_sel) {}
|
||||
static inline bool rtw_assert_protsel_port(_adapter *padapter, u32 addr, u8 len) {return true; }
|
||||
static inline void rtw_leave_protsel_port(_adapter *padapter) {}
|
||||
#endif
|
||||
#ifdef CONFIG_PROTSEL_ATIMDTIM
|
||||
void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel);
|
||||
bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len);
|
||||
void rtw_leave_protsel_atimdtim(_adapter *padapter);
|
||||
#else
|
||||
static inline void rtw_enter_protsel_atimdtim(_adapter *padapter, u8 port_sel) {}
|
||||
static inline bool rtw_assert_protsel_atimdtim(_adapter *padapter, u32 addr, u8 len) {return true; }
|
||||
static inline void rtw_leave_protsel_atimdtim(_adapter *padapter) {}
|
||||
#endif
|
||||
#ifdef CONFIG_PROTSEL_MACSLEEP
|
||||
void rtw_enter_protsel_macsleep(_adapter *padapter, u8 sel);
|
||||
bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len);
|
||||
void rtw_leave_protsel_macsleep(_adapter *padapter);
|
||||
#else
|
||||
static inline void rtw_enter_protsel_macsleep(_adapter *padapter, u8 port_sel) {}
|
||||
static inline bool rtw_assert_protsel_macsleep(_adapter *padapter, u32 addr, u8 len) {return true; }
|
||||
static inline void rtw_leave_protsel_macsleep(_adapter *padapter) {}
|
||||
#endif
|
||||
#endif /* __HAL_COMMON_H__ */
|
||||
|
|
@ -0,0 +1,817 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __COMMON_H2C_H__
|
||||
#define __COMMON_H2C_H__
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
|
||||
* ---------------------------------------------------------------------------------------------------------
|
||||
* 88e, 8723b, 8812, 8821, 92e use the same FW code base */
|
||||
enum h2c_cmd {
|
||||
/* Common Class: 000 */
|
||||
H2C_RSVD_PAGE = 0x00,
|
||||
H2C_MEDIA_STATUS_RPT = 0x01,
|
||||
H2C_SCAN_ENABLE = 0x02,
|
||||
H2C_KEEP_ALIVE = 0x03,
|
||||
H2C_DISCON_DECISION = 0x04,
|
||||
H2C_PSD_OFFLOAD = 0x05,
|
||||
H2C_CUSTOMER_STR_REQ = 0x06,
|
||||
H2C_TXPWR_IDX_OFFLOAD = 0x07,
|
||||
H2C_AP_OFFLOAD = 0x08,
|
||||
H2C_BCN_RSVDPAGE = 0x09,
|
||||
H2C_PROBERSP_RSVDPAGE = 0x0A,
|
||||
H2C_FCS_RSVDPAGE = 0x10,
|
||||
H2C_FCS_INFO = 0x11,
|
||||
H2C_AP_WOW_GPIO_CTRL = 0x13,
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
H2C_MCC_RQT_TSF = 0x15,
|
||||
H2C_MCC_MACID_BITMAP = 0x16,
|
||||
H2C_MCC_LOCATION = 0x10,
|
||||
H2C_MCC_CTRL_V2 = 0x17,
|
||||
H2C_MCC_CTRL = 0x18,
|
||||
H2C_MCC_TIME_SETTING = 0x19,
|
||||
H2C_MCC_IQK_PARAM = 0x1A,
|
||||
#endif /* CONFIG_MCC_MODE */
|
||||
H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C,
|
||||
H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D,
|
||||
|
||||
/* PoweSave Class: 001 */
|
||||
H2C_SET_PWR_MODE = 0x20,
|
||||
H2C_PS_TUNING_PARA = 0x21,
|
||||
H2C_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_P2P_LPS_PARAM = 0x23,
|
||||
H2C_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_PS_SCAN_ENABLE = 0x25,
|
||||
H2C_SAP_PS_ = 0x26,
|
||||
H2C_INACTIVE_PS_ = 0x27, /* Inactive_PS */
|
||||
H2C_FWLPS_IN_IPS_ = 0x28,
|
||||
#ifdef CONFIG_LPS_POFF
|
||||
H2C_LPS_POFF_CTRL = 0x29,
|
||||
H2C_LPS_POFF_PARAM = 0x2A,
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_PG
|
||||
H2C_LPS_PG_INFO = 0x2B,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
H2C_DEFAULT_PORT_ID = 0x2C,
|
||||
#endif
|
||||
/* Dynamic Mechanism Class: 010 */
|
||||
H2C_MACID_CFG = 0x40,
|
||||
H2C_TXBF = 0x41,
|
||||
H2C_RSSI_SETTING = 0x42,
|
||||
H2C_AP_REQ_TXRPT = 0x43,
|
||||
H2C_INIT_RATE_COLLECT = 0x44,
|
||||
H2C_IQ_CALIBRATION = 0x45,
|
||||
|
||||
H2C_RA_MASK_3SS = 0x46,/* for 8814A */
|
||||
H2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */
|
||||
H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */
|
||||
|
||||
H2C_FW_TRACE_EN = 0x49,
|
||||
#ifdef RTW_PER_CMD_SUPPORT_FW
|
||||
H2C_REQ_PER_RPT = 0x4e,
|
||||
#endif
|
||||
/* BT Class: 011 */
|
||||
H2C_B_TYPE_TDMA = 0x60,
|
||||
H2C_BT_INFO = 0x61,
|
||||
H2C_FORCE_BT_TXPWR = 0x62,
|
||||
H2C_BT_IGNORE_WLANACT = 0x63,
|
||||
H2C_DAC_SWING_VALUE = 0x64,
|
||||
H2C_ANT_SEL_RSV = 0x65,
|
||||
H2C_WL_OPMODE = 0x66,
|
||||
H2C_BT_MP_OPER = 0x67,
|
||||
H2C_BT_CONTROL = 0x68,
|
||||
H2C_BT_WIFI_CTRL = 0x69,
|
||||
H2C_BT_FW_PATCH = 0x6A,
|
||||
#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
|
||||
H2C_BTC_WL_PORT_ID = 0x71,
|
||||
#endif
|
||||
/* WOWLAN Class: 100 */
|
||||
H2C_WOWLAN = 0x80,
|
||||
H2C_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_AOAC_RSVD_PAGE = 0x83,
|
||||
H2C_AOAC_RSVD_PAGE2 = 0x84,
|
||||
H2C_D0_SCAN_OFFLOAD_CTRL = 0x85,
|
||||
H2C_D0_SCAN_OFFLOAD_INFO = 0x86,
|
||||
H2C_CHNL_SWITCH_OFFLOAD = 0x87,
|
||||
H2C_AOAC_RSVDPAGE3 = 0x88,
|
||||
H2C_GPIO_CUSTOM = 0x89,
|
||||
H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
|
||||
H2C_P2P_OFFLOAD = 0x8B,
|
||||
H2C_WAR_OFFLOAD = 0x8D,
|
||||
H2C_WAROFLD_RSVDPAGE1 = 0x8E,
|
||||
#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
|
||||
H2C_UDP_KEEPALIVE = 0x90,
|
||||
#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
|
||||
#ifdef CONFIG_FW_HANDLE_TXBCN
|
||||
H2C_FW_BCN_OFFLOAD = 0xBA,
|
||||
#endif
|
||||
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
|
||||
H2C_FW_CRC5_SEARCH = 0xBB,
|
||||
#endif
|
||||
H2C_RESET_TSF = 0xC0,
|
||||
#ifdef CONFIG_FW_CORRECT_BCN
|
||||
H2C_BCNHWSEQ = 0xC5,
|
||||
#endif
|
||||
H2C_CUSTOMER_STR_W1 = 0xC6,
|
||||
H2C_CUSTOMER_STR_W2 = 0xC7,
|
||||
H2C_CUSTOMER_STR_W3 = 0xC8,
|
||||
H2C_BT_UNKNOWN_DEVICE_WA = 0xD1,
|
||||
#ifdef DBG_FW_DEBUG_MSG_PKT
|
||||
H2C_FW_DBG_MSG_PKT = 0xE1,
|
||||
#endif /*DBG_FW_DEBUG_MSG_PKT*/
|
||||
H2C_MAXID,
|
||||
};
|
||||
|
||||
#define H2C_INACTIVE_PS_LEN 4
|
||||
#define H2C_RSVDPAGE_LOC_LEN 5
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
#define H2C_DEFAULT_PORT_ID_LEN 2
|
||||
#define H2C_MEDIA_STATUS_RPT_LEN 4
|
||||
#else
|
||||
#define H2C_MEDIA_STATUS_RPT_LEN 3
|
||||
#endif
|
||||
#define H2C_GPIO_CUSTOM_LEN 3
|
||||
#define H2C_KEEP_ALIVE_CTRL_LEN 2
|
||||
#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
|
||||
#define H2C_KEEP_ALIVE_PATTERN_LEN 7
|
||||
#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
|
||||
#define H2C_DISCON_DECISION_LEN 3
|
||||
#define H2C_AP_OFFLOAD_LEN 3
|
||||
#define H2C_AP_WOW_GPIO_CTRL_LEN 4
|
||||
#define H2C_AP_PS_LEN 2
|
||||
#define H2C_PWRMODE_LEN 7
|
||||
#define H2C_PSTUNEPARAM_LEN 4
|
||||
#define H2C_MACID_CFG_LEN 7
|
||||
#define H2C_BTMP_OPER_LEN 5
|
||||
#define H2C_WOWLAN_LEN 7
|
||||
#define H2C_REMOTE_WAKE_CTRL_LEN 3
|
||||
#define H2C_AOAC_GLOBAL_INFO_LEN 2
|
||||
#define H2C_AOAC_RSVDPAGE_LOC_LEN 7
|
||||
#define H2C_SCAN_OFFLOAD_CTRL_LEN 4
|
||||
#define H2C_BT_FW_PATCH_LEN 6
|
||||
#define H2C_RSSI_SETTING_LEN 4
|
||||
#define H2C_AP_REQ_TXRPT_LEN 3
|
||||
#define H2C_FORCE_BT_TXPWR_LEN 3
|
||||
#define H2C_BCN_RSVDPAGE_LEN 5
|
||||
#define H2C_PROBERSP_RSVDPAGE_LEN 5
|
||||
#define H2C_P2PRSVDPAGE_LOC_LEN 5
|
||||
#define H2C_P2P_OFFLOAD_LEN 3
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
#define H2C_MCC_CTRL_LEN 7
|
||||
#ifdef CONFIG_MCC_MODE_V2
|
||||
#define H2C_MCC_LOCATION_LEN 7
|
||||
#else
|
||||
#define H2C_MCC_LOCATION_LEN 3
|
||||
#endif
|
||||
#define H2C_MCC_MACID_BITMAP_LEN 6
|
||||
#define H2C_MCC_RQT_TSF_LEN 1
|
||||
#define H2C_MCC_TIME_SETTING_LEN 6
|
||||
#define H2C_MCC_IQK_PARAM_LEN 7
|
||||
#endif /* CONFIG_MCC_MODE */
|
||||
#ifdef CONFIG_LPS_PG
|
||||
#ifdef CONFIG_RTL8822C
|
||||
#define H2C_LPS_PG_INFO_LEN 4
|
||||
#else
|
||||
#define H2C_LPS_PG_INFO_LEN 2
|
||||
#endif
|
||||
#define H2C_LPSPG_LEN 16
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_POFF
|
||||
#define H2C_LPS_POFF_CTRL_LEN 1
|
||||
#define H2C_LPS_POFF_PARAM_LEN 5
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
|
||||
#define H2C_BTC_WL_PORT_ID_LEN 1
|
||||
#endif
|
||||
|
||||
#ifdef DBG_FW_DEBUG_MSG_PKT
|
||||
#define H2C_FW_DBG_MSG_PKT_LEN 2
|
||||
#endif /*DBG_FW_DEBUG_MSG_PKT*/
|
||||
|
||||
#define H2C_SINGLE_CHANNELSWITCH_V2_LEN 3
|
||||
#define H2C_BT_UNKNOWN_DEVICE_WA_LEN 1
|
||||
|
||||
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
|
||||
#define H2C_FW_CRC5_SEARCH_LEN 7
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WAR_OFFLOAD
|
||||
#define H2C_WAR_OFFLOAD_LEN 3
|
||||
#define H2C_WAROFLD_RSVDPAGE1_LEN 6
|
||||
#endif /* CONFIG_WAR_OFFLOAD */
|
||||
|
||||
|
||||
#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
|
||||
#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
|
||||
#define cpIpAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3])
|
||||
#define cpIpv6Addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5], (des)[6] = (src)[6], (des)[7] = (src)[7], (des)[8] = (src)[8], (des)[9] = (src)[9], (des)[10] = (src)[10], (des)[11] = (src)[11], (des)[12] = (src)[12], (des)[13] = (src)[13], (des)[14] = (src)[14], (des)[15] = (src)[15])
|
||||
|
||||
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
#define FW_WOWLAN_FUN_EN BIT(0)
|
||||
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
|
||||
#define FW_WOWLAN_MAGIC_PKT BIT(2)
|
||||
#define FW_WOWLAN_UNICAST BIT(3)
|
||||
#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
|
||||
#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
|
||||
#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
|
||||
#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
|
||||
|
||||
#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
|
||||
#define FW_FW_PARSE_MAGIC_PKT BIT(1)
|
||||
|
||||
#define FW_REMOTE_WAKE_CTRL_EN BIT(0)
|
||||
#define FW_REALWOWLAN_EN BIT(5)
|
||||
|
||||
#define FW_WOWLAN_KEEP_ALIVE_EN BIT(0)
|
||||
#define FW_ADOPT_USER BIT(1)
|
||||
#define FW_WOWLAN_KEEP_ALIVE_PKT_TYPE BIT(2)
|
||||
|
||||
#define FW_REMOTE_WAKE_CTRL_EN BIT(0)
|
||||
#define FW_ARP_EN BIT(1)
|
||||
#define FW_REALWOWLAN_EN BIT(5)
|
||||
#define FW_WOW_FW_UNICAST_EN BIT(7)
|
||||
|
||||
#define FW_IPS_DISABLE_BBRF BIT(0)
|
||||
#define FW_IPS_WRC BIT(1)
|
||||
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
/* _RSVDPAGE_LOC_CMD_0x00 */
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */
|
||||
#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value))
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value))
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value))
|
||||
#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value))
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
|
||||
#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value))
|
||||
#define SET_H2CCMD_MSRRPT_PARM_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 3, 0, 3, (__Value))
|
||||
|
||||
#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1)
|
||||
#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1)
|
||||
#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1)
|
||||
#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4)
|
||||
|
||||
#ifdef CONFIG_WAR_OFFLOAD
|
||||
#define SET_IPHDR_VERSION(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 0, __Value)
|
||||
#define SET_IPHDR_DSCP(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 1, __Value)
|
||||
#define SET_IPHDR_TOTAL_LEN(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value)
|
||||
#define SET_IPHDR_IDENTIFIER(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 4, __Value)
|
||||
#define SET_IPHDR_FLAGS(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 6, __Value)
|
||||
#define SET_IPHDR_FRAG_OFFSET(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 7, __Value)
|
||||
#define SET_IPHDR_TTL(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 8, __Value)
|
||||
#define SET_IPHDR_PROTOCOL(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 9, __Value)
|
||||
#define SET_IPHDR_HDR_CHECKSUM(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 10, __Value)
|
||||
#define SET_IPHDR_SRC_IP_ADDR(__pHeader, __Value) cpIpAddr(((u8 *)(__pHeader))+12, (u8 *)(__Value))
|
||||
#define SET_IPHDR_DST_IP_ADDR(__pHeader, __Value) cpIpAddr(((u8 *)(__pHeader))+16, (u8 *)(__Value))
|
||||
#define SET_UDP_SRC_PORT(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 0, __Value)
|
||||
#define SET_UDP_DST_PORT(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 2, __Value)
|
||||
#define SET_UDP_LEN(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 4, __Value)
|
||||
#define SET_UDP_CHECKSUM(__pHeader, __Value) WriteLE2Byte(((u8 *)(__pHeader)) + 6, __Value)
|
||||
|
||||
#define SET_MDNS_HDR_FLAG(__pHeader, __Value) WriteLE1Byte(((u8 *)(__pHeader)) + 2, __Value)
|
||||
|
||||
#endif /* CONFIG_WAR_OFFLOAD */
|
||||
|
||||
#ifdef CONFIG_OFFLOAD_MDNS_V6
|
||||
#define SET_IPHDRV6_VERSION(__pHeader, __Value) SET_BITS_TO_LE_1BYTE(__pHeader, 4, 4, __Value)
|
||||
#define SET_IPHDRV6_TRAFFIC_CLASS(__pHeader, __Value) SET_BITS_TO_LE_2BYTE(__pHeader, 4, 8, __Value)
|
||||
#define SET_IPHDRV6_FLOW_LABEL(__pHeader, __Value) SET_BITS_TO_LE_4BYTE(__pHeader, 12, 20, __Value)
|
||||
#define SET_IPHDRV6_PAYLOAD_LENGTH(__pHeader, __Value) SET_BITS_TO_LE_2BYTE(((u8 *)(__pHeader)) + 4, 0, 16, __Value)
|
||||
#define SET_IPHDRV6_NEXT_HEADER(__pHeader, __Value) SET_BITS_TO_LE_1BYTE((__pHeader) + 6, 0, 8, __Value)
|
||||
#define SET_IPHDRV6_HOP_LIMIT(__pHeader, __Value) SET_BITS_TO_LE_1BYTE((__pHeader) + 7, 0, 8, __Value)
|
||||
#define SET_IPHDRV6_SRC_IP_ADDR(__pHeader, __Value) cpIpv6Addr((u8 *)(__pHeader) + 8, (u8 *)(__Value))
|
||||
#define SET_IPHDRV6_DST_IP_ADDR(__pHeader, __Value) cpIpv6Addr((u8 *)(__pHeader) + 24, (u8 *)(__Value))
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#define H2C_MSR_ROLE_RSVD 0
|
||||
#define H2C_MSR_ROLE_STA 1
|
||||
#define H2C_MSR_ROLE_AP 2
|
||||
#define H2C_MSR_ROLE_GC 3
|
||||
#define H2C_MSR_ROLE_GO 4
|
||||
#define H2C_MSR_ROLE_TDLS 5
|
||||
#define H2C_MSR_ROLE_ADHOC 6
|
||||
#define H2C_MSR_ROLE_MESH 7
|
||||
#define H2C_MSR_ROLE_MAX 8
|
||||
|
||||
extern const char *const _h2c_msr_role_str[];
|
||||
#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)])
|
||||
|
||||
#define H2C_MSR_FMT "%s %s%s"
|
||||
#define H2C_MSR_ARG(h2c_msr) \
|
||||
GET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? " C" : "", \
|
||||
h2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \
|
||||
GET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? " MSINK" : " MSRC") : ""
|
||||
|
||||
s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end);
|
||||
s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid);
|
||||
s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end);
|
||||
|
||||
/* _KEEP_ALIVE_CMD_0x03 */
|
||||
#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 3, __Value)
|
||||
#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _DISCONNECT_DECISION_CMD_0x04 */
|
||||
#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_BCN_FAIL_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_DISCONDECISION_PARM_DISCONNECT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value)
|
||||
#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_DISCONDECISION_PARM_TRY_OK_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/*UDP_KEEP_ALIVE 0x90*/
|
||||
#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
|
||||
/*data 0*/
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value);
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_PACKET_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value);
|
||||
/*data 1*/
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value);
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_ACK_PATTERN_idx(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 7, __Value);
|
||||
/*data 2*/
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value);
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_WAKE_PATTERN_idx(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value);
|
||||
/*data3*/
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_PERIOD_LOW_BIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value);
|
||||
/*data4*/
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_PERIOD_HI_BIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value);
|
||||
/*data5*/
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value);
|
||||
/*data6*/
|
||||
#define SET_H2CCMD_UDP_KEEP_ALIVE_RETRY_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value);
|
||||
#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
|
||||
#ifdef CONFIG_RTW_CUSTOMER_STR
|
||||
#define RTW_CUSTOMER_STR_LEN 16
|
||||
#define RTW_CUSTOMER_STR_FMT "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x"
|
||||
#define RTW_CUSTOMER_STR_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
|
||||
((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
|
||||
((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
|
||||
|
||||
/* H2C_CUSTOMER_STR_REQ 0x06 */
|
||||
#define H2C_CUSTOMER_STR_REQ_LEN 1
|
||||
#define SET_H2CCMD_CUSTOMER_STR_REQ_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
|
||||
s32 rtw_hal_h2c_customer_str_req(_adapter *adapter);
|
||||
s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs);
|
||||
|
||||
/* H2C_CUSTOMER_STR_W1 0xC6 */
|
||||
#define H2C_CUSTOMER_STR_W1_LEN 7
|
||||
#define SET_H2CCMD_CUSTOMER_STR_W1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
|
||||
#define H2CCMD_CUSTOMER_STR_W1_BYTE0(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1)
|
||||
|
||||
/* H2C_CUSTOMER_STR_W2 0xC7 */
|
||||
#define H2C_CUSTOMER_STR_W2_LEN 7
|
||||
#define SET_H2CCMD_CUSTOMER_STR_W2_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
|
||||
#define H2CCMD_CUSTOMER_STR_W2_BYTE6(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1)
|
||||
|
||||
/* H2C_CUSTOMER_STR_W3 0xC8 */
|
||||
#define H2C_CUSTOMER_STR_W3_LEN 5
|
||||
#define SET_H2CCMD_CUSTOMER_STR_W3_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value))
|
||||
#define H2CCMD_CUSTOMER_STR_W3_BYTE12(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1)
|
||||
s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs);
|
||||
s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs);
|
||||
#endif /* CONFIG_RTW_CUSTOMER_STR */
|
||||
|
||||
#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
|
||||
#define H2C_TXPWR_IDX_OFFLOAD_LEN 4
|
||||
#define SET_H2CCMD_TXPWR_IDX_CCK(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_TXPWR_IDX_OFDM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_TXPWR_IDX_HT1SS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd + 2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_TXPWR_IDX_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd + 3, 0, 1, __Value)
|
||||
#endif
|
||||
|
||||
/* _AP_Offload 0x08 */
|
||||
#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
/* _BCN_RsvdPage 0x09 */
|
||||
#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
/* _Probersp_RsvdPage 0x0a */
|
||||
#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
/* _Probersp_RsvdPage 0x13 */
|
||||
|
||||
#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
/* _PWR_MOD_CMD_0x20 */
|
||||
|
||||
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
/* _AP_PS 0x26 */
|
||||
#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
|
||||
/* INACTIVE_PS 0x27, duration unit is TBTT */
|
||||
#define SET_H2CCMD_INACTIVE_PS_EN(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_INACTIVE_IGNORE_PS(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_INACTIVE_PERIOD_SCAN_EN(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_INACTIVE_DISBBRF(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
#define SET_H2CCMD_INACTIVE_PORT_NUM(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 3, __Value)
|
||||
#define SET_H2CCMD_INACTIVE_PS_FREQ(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd + 1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_INACTIVE_PS_DURATION(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd + 2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_INACTIVE_PS_PERIOD_SCAN_TIME(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd + 3, 0, 8, __Value)
|
||||
|
||||
#ifdef CONFIG_LPS_POFF
|
||||
/*PARTIAL OFF Control 0x29*/
|
||||
#define SET_H2CCMD_LPS_POFF_CTRL_EN(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
/*PARTIAL OFF PARAM 0x2A*/
|
||||
#define SET_H2CCMD_LPS_POFF_PARAM_RDVLD(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_LPS_POFF_PARAM_WRVLD(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDL(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_LPS_POFF_PARAM_STARTADDH(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDL(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_LPS_POFF_PARAM_ENDADDH(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
/* DEFAULT PORT ID 0x2C*/
|
||||
#define SET_H2CCMD_DFTPID_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 8, (__Value))
|
||||
#define SET_H2CCMD_DFTPID_MAC_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
/* MCC LOC CMD 0x10 */
|
||||
#define SET_H2CCMD_MCC_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_PWRIDX_OFFLOAD_RFNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 4, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_PWRIDX_RSVDPAGE_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 4, 0, 8, __Value)
|
||||
|
||||
/* MCC RQT TSF 0x15 */
|
||||
#define SET_H2CCMD_MCC_RQT_TSFX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_RQT_TSFY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
|
||||
/* MCC MAC ID CMD 0x16 */
|
||||
#define SET_H2CCMD_MCC_MACID_BITMAP_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_MACID_BITMAP_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
|
||||
/* NEW MCC CTRL CMD 0x17 */
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_CENTRAL_CH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_PRIMARY_CH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_INCURCH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_DIS_SW_RETRY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_DISTXNULL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 6, 2, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_TSFX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_NULL_EARLY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 4, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_V2_UPDATE_PARM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
|
||||
|
||||
|
||||
/* MCC CTRL CMD 0x18 */
|
||||
#define SET_H2CCMD_MCC_CTRL_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_TOTALNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_CHIDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_BW40SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 3, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_BW80SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 5, 3, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 3, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_INCURCH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_RSVD0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_RSVD1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_RFETYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_DISTXNULL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 4, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_C2HRPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 5, 2, __Value)
|
||||
#define SET_H2CCMD_MCC_CTRL_CHSCAN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 7, 1, __Value)
|
||||
|
||||
/* MCC Time CMD 0x19 */
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_FW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_TSF_SYNC_OFFSET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 7, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_START_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_INTERVAL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_EARLY_SWITCH_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_ORDER_BASE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_ORDER_SYNC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_TIME_SETTING_ORDER0_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 1, 7, __Value)
|
||||
|
||||
/* MCC IQK CMD 0x1A */
|
||||
#define SET_H2CCMD_MCC_IQK_READY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_ORDER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_PATH(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 2, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_RX_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_RX_M1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_RX_M2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 6, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_RX_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 4, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_TX_L(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_TX_M1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 3, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_TX_M2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 3, 5, __Value)
|
||||
#define SET_H2CCMD_MCC_IQK_TX_H(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 6, __Value)
|
||||
#endif /* CONFIG_MCC_MODE */
|
||||
|
||||
/* CHNL SWITCH OPER OFFLOAD 0x1C */
|
||||
#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 2, __Value)
|
||||
#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 2, 3, __Value)
|
||||
#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value)
|
||||
#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value)
|
||||
|
||||
/* H2C_SINGLE_CHANNELSWITCH_V2 = 0x1D */
|
||||
#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CENTRAL_CH_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PRIMARY_CH_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 4, __Value)
|
||||
#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 4, 4, __Value)
|
||||
#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_PWR_IDX_UPDATE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 1, __Value)
|
||||
#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_IQK_UPDATE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 1, 1, __Value)
|
||||
#define SET_H2CCMD_SINGLE_CH_SWITCH_V2_CH_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 4, 4, __Value)
|
||||
|
||||
#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
|
||||
#define SET_H2CCMD_BTC_WL_PORT_ID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#endif
|
||||
|
||||
/* _WoWLAN PARAM_CMD_0x80 */
|
||||
#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_DISABLE_UPHY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_HST2DEV_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 1, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_GPIO_DURATION_MS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_DEV2HST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 7, 1, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_TIME_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
#define SET_H2CCMD_WOWLAN_RISE_HST2DEV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 2, 1, __Value)
|
||||
|
||||
/* _REMOTE_WAKEUP_CMD_0x81 */
|
||||
#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 3, 1, __Value)
|
||||
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
|
||||
#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value)
|
||||
|
||||
/* AOAC_GLOBAL_INFO_0x82 */
|
||||
#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
|
||||
/* AOAC_RSVDPAGE_LOC_0x83 */
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#ifdef CONFIG_GTK_OL
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
#endif /* CONFIG_GTK_OL */
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NDP_INFO(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value)
|
||||
|
||||
/* AOAC_RSVDPAGE_2_0x84 */
|
||||
|
||||
/* AOAC_RSVDPAGE_3_0x88 */
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
|
||||
#endif
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 8, __Value)
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
/* D0_Scan_Offload_Info_0x86 */
|
||||
#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value)
|
||||
#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value)
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#endif /* CONFIG_PNO_SUPPORT */
|
||||
|
||||
/* _GPIO_CUSTOM_CMD_0x89 */
|
||||
#define SET_H2CCMD_CUSTOMERID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_SPECIAL_WAKE_REASON(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_CUSTOM_WAKE_REASON(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value)
|
||||
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
/* P2P_RsvdPage_0x8a */
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_NEGO_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_INVITE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_P2P_PD_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#endif /* CONFIG_P2P_WOWLAN */
|
||||
|
||||
#ifdef CONFIG_LPS_PG
|
||||
#define SET_H2CCMD_LPSPG_SEC_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*SecurityCAM_En*/
|
||||
#define SET_H2CCMD_LPSPG_MBID_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)/*BSSIDCAM_En*/
|
||||
#define SET_H2CCMD_LPSPG_PMC_CAM_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)/*PatternMatchCAM_En*/
|
||||
#define SET_H2CCMD_LPSPG_MACID_SEARCH_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)/*MACIDSearch_En*/
|
||||
#define SET_H2CCMD_LPSPG_TXSC_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)/*TXSC_En*/
|
||||
#define SET_H2CCMD_LPSPG_MU_RATE_TB_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)/*MURateTable_En*/
|
||||
#define SET_H2CCMD_LPSPG_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)/*Loc_LPS_PG*/
|
||||
#define SET_H2CCMD_LPSPG_DPK_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)/*Loc_LPS_PG_DPK_info*/
|
||||
#define SET_H2CCMD_LPSPG_IQK_INFO_LOC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 3, 0, 8, __Value)/*Loc_IQK_result*/
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8822C) && defined(CONFIG_SUPPORT_DYNAMIC_TXPWR)
|
||||
#define SET_H2CCMD_FW_CRC5_SEARCH_EN(cmd, v) \
|
||||
SET_BITS_TO_LE_1BYTE((cmd), 0, 1, (v));
|
||||
#define SET_H2CCMD_FW_CRC5_SEARCH_MACID(cmd, v) \
|
||||
SET_BITS_TO_LE_1BYTE((cmd), 1, 7, (v));
|
||||
#define SET_H2CCMD_FW_CRC5_SEARCH_MAC(cmd, mac) \
|
||||
do { \
|
||||
int __offset = 0; \
|
||||
for (__offset = 0; __offset < ETH_ALEN; __offset++) \
|
||||
SET_BITS_TO_LE_1BYTE((u8 *)(cmd + __offset), 0, 8, *((u8 *)(mac + __offset))); \
|
||||
} while(0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WAR_OFFLOAD
|
||||
/* WarOffload_Info_0x8D */
|
||||
#define SET_H2CCMD_WAR_CFG_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_WAR_CFG_ARP_RSP_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_WAR_CFG_MDNSV4_RSP_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 2, 1, __Value)
|
||||
#define SET_H2CCMD_WAR_CFG_MDNSV6_RSP_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 3, 1, __Value)
|
||||
#define SET_H2CCMD_WAR_CFG_MDNSV4_WAKE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 6, 1, __Value)
|
||||
#define SET_H2CCMD_WAR_CFG_MDNSV6_WAKE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 7, 1, __Value)
|
||||
|
||||
/* H2C_WAROFLD_RSVDPAGE1 */
|
||||
#define SET_H2CCMD_WAROFLD_RSVDPAGE1_LOC_PARM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
|
||||
#endif /* CONFIG_WAR_OFFLOAD */
|
||||
|
||||
|
||||
/* BT_UNKNOWN_DEVICE_WA_0xD1 */
|
||||
#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_HANG_CHK_EN(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_FORCE_IB_EN(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_HWID_CHK_EN(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_H2CCMD_BT_UNKNOWN_DEVICE_WA_ONE_TIME_CHK(__pH2CCmd, __Value) \
|
||||
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
|
||||
#ifdef DBG_FW_DEBUG_MSG_PKT
|
||||
#define SET_H2CCMD_FW_DBG_MSG_PKT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)/*sniffer_dbg_en*/
|
||||
#define SET_H2CCMD_RSVDPAGE_LOC_FW_DBG_MSG_PKT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) /*loc_debug_packet*/
|
||||
#endif /*DBG_FW_DEBUG_MSG_PKT*/
|
||||
|
||||
#ifdef DBG_RSVD_PAGE_CFG
|
||||
#define RSVD_PAGE_CFG(ops, v1, v2, v3) \
|
||||
RTW_INFO("=== [RSVD][%s]-NeedPage:%d, TotalPageNum:%d TotalPacketLen:%d ===\n", \
|
||||
ops, v1, v2, v3)
|
||||
#else
|
||||
#define RSVD_PAGE_CFG(ops, v1, v2, v3) do {} while (0)
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ------------------------------------------- Structure --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
typedef struct _RSVDPAGE_LOC {
|
||||
u8 LocProbeRsp;
|
||||
u8 LocPsPoll;
|
||||
u8 LocNullData;
|
||||
u8 LocQosNull;
|
||||
u8 LocBTQosNull;
|
||||
#ifdef CONFIG_WOWLAN
|
||||
u8 LocRemoteCtrlInfo;
|
||||
u8 LocArpRsp;
|
||||
u8 LocNbrAdv;
|
||||
u8 LocGTKRsp;
|
||||
u8 LocGTKInfo;
|
||||
u8 LocProbeReq;
|
||||
u8 LocNetList;
|
||||
#ifdef CONFIG_GTK_OL
|
||||
u8 LocGTKEXTMEM;
|
||||
#endif /* CONFIG_GTK_OL */
|
||||
u8 LocNDPInfo;
|
||||
u8 LocAOACReport;
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
u8 LocPNOInfo;
|
||||
u8 LocScanInfo;
|
||||
u8 LocSSIDInfo;
|
||||
u8 LocProbePacket;
|
||||
#endif /* CONFIG_PNO_SUPPORT */
|
||||
#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
|
||||
u8 LocKeepAlive;
|
||||
#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
|
||||
#ifdef CONFIG_WAR_OFFLOAD
|
||||
u8 LocIpParm;
|
||||
#if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
|
||||
u8 LocMdnsPara;
|
||||
u8 LocMdnsv4;
|
||||
u8 LocMdnsv6;
|
||||
#endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
|
||||
#endif /* CONFIG_WAR_OFFLOAD */
|
||||
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
u8 LocApOffloadBCN;
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
u8 LocP2PBeacon;
|
||||
u8 LocP2PProbeRsp;
|
||||
u8 LocNegoRsp;
|
||||
u8 LocInviteRsp;
|
||||
u8 LocPDRsp;
|
||||
#endif /* CONFIG_P2P_WOWLAN */
|
||||
#ifdef DBG_FW_DEBUG_MSG_PKT
|
||||
u8 loc_fw_dbg_msg_pkt;
|
||||
#endif /*DBG_FW_DEBUG_MSG_PKT*/
|
||||
} RSVDPAGE_LOC, *PRSVDPAGE_LOC;
|
||||
|
||||
struct rsvd_page_cache_t {
|
||||
char *name;
|
||||
u8 loc;
|
||||
u8 page_num;
|
||||
u8 *data;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
bool rsvd_page_cache_update_all(struct rsvd_page_cache_t *cache, u8 loc
|
||||
, u8 txdesc_len, u32 page_size, u8 *info, u32 info_len);
|
||||
bool rsvd_page_cache_update_data(struct rsvd_page_cache_t *cache, u8 *info
|
||||
, u32 info_len);
|
||||
void rsvd_page_cache_free_data(struct rsvd_page_cache_t *cache);
|
||||
void rsvd_page_cache_free(struct rsvd_page_cache_t *cache);
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_WOWLAN
|
||||
void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size);
|
||||
#endif
|
||||
u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid);
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
/* WOW command function */
|
||||
void rtw_hal_set_fw_wow_related_cmd(_adapter *padapter, u8 enable);
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
/* H2C 0x8A */
|
||||
u8 rtw_hal_set_FwP2PRsvdPage_cmd(_adapter *adapter, PRSVDPAGE_LOC rsvdpageloc);
|
||||
/* H2C 0x8B */
|
||||
u8 rtw_hal_set_p2p_wowlan_offload_cmd(_adapter *adapter);
|
||||
#endif /* CONFIG_P2P_WOWLAN */
|
||||
#endif
|
||||
|
||||
#ifdef RTW_PER_CMD_SUPPORT_FW
|
||||
u8 rtw_hal_set_req_per_rpt_cmd(_adapter *adapter, u8 group_macid,
|
||||
u8 rpt_type, u32 macid_bitmap);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,437 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_COMMON_LED_H_
|
||||
#define __HAL_COMMON_LED_H_
|
||||
|
||||
#define NO_LED 0
|
||||
#define HW_LED 1
|
||||
|
||||
#ifdef CONFIG_RTW_LED
|
||||
#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000)
|
||||
|
||||
/* ********************************************************************************
|
||||
* LED Behavior Constant.
|
||||
* ********************************************************************************
|
||||
* Default LED behavior.
|
||||
* */
|
||||
#define LED_BLINK_NORMAL_INTERVAL 100
|
||||
#define LED_BLINK_SLOWLY_INTERVAL 200
|
||||
#define LED_BLINK_LONG_INTERVAL 400
|
||||
#define LED_INITIAL_INTERVAL 1800
|
||||
|
||||
/* LED Customerization */
|
||||
|
||||
/* NETTRONIX */
|
||||
#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100
|
||||
#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000
|
||||
|
||||
/* PORNET */
|
||||
#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000
|
||||
#define LED_BLINK_NORMAL_INTERVAL_PORNET 100
|
||||
#define LED_BLINK_FAST_INTERVAL_BITLAND 30
|
||||
|
||||
/* AzWave. */
|
||||
#define LED_CM2_BLINK_ON_INTERVAL 250
|
||||
#define LED_CM2_BLINK_OFF_INTERVAL 4750
|
||||
#define LED_CM8_BLINK_OFF_INTERVAL 3750 /* for QMI */
|
||||
|
||||
/* RunTop */
|
||||
#define LED_RunTop_BLINK_INTERVAL 300
|
||||
|
||||
/* ALPHA */
|
||||
#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000
|
||||
#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 /* add by ylb 20121012 for customer led for alpha */
|
||||
#define LED_BLINK_LINK_INTERVAL_ALPHA 500 /* 500 */
|
||||
#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 /* 150 */
|
||||
#define LED_BLINK_FASTER_INTERVAL_ALPHA 50
|
||||
#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000
|
||||
|
||||
/* 111122 by hpfan: Customized for Xavi */
|
||||
#define LED_CM11_BLINK_INTERVAL 300
|
||||
#define LED_CM11_LINK_ON_INTERVEL 3000
|
||||
|
||||
/* Netgear */
|
||||
#define LED_BLINK_LINK_INTERVAL_NETGEAR 500
|
||||
#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR 1000
|
||||
|
||||
#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR 100
|
||||
#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR 500
|
||||
|
||||
/* Belkin AC950 */
|
||||
#define LED_BLINK_LINK_INTERVAL_ON_BELKIN 200
|
||||
#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN 100
|
||||
#define LED_BLINK_ERROR_INTERVAL_BELKIN 100
|
||||
|
||||
/* by chiyokolin for Azurewave */
|
||||
#define LED_CM12_BLINK_INTERVAL_5Mbps 160
|
||||
#define LED_CM12_BLINK_INTERVAL_10Mbps 80
|
||||
#define LED_CM12_BLINK_INTERVAL_20Mbps 50
|
||||
#define LED_CM12_BLINK_INTERVAL_40Mbps 40
|
||||
#define LED_CM12_BLINK_INTERVAL_80Mbps 30
|
||||
#define LED_CM12_BLINK_INTERVAL_MAXMbps 25
|
||||
|
||||
/* Dlink */
|
||||
#define LED_BLINK_NO_LINK_INTERVAL 1000
|
||||
#define LED_BLINK_LINK_IDEL_INTERVAL 100
|
||||
|
||||
#define LED_BLINK_SCAN_ON_INTERVAL 30
|
||||
#define LED_BLINK_SCAN_OFF_INTERVAL 300
|
||||
|
||||
#define LED_WPS_BLINK_ON_INTERVAL_DLINK 30
|
||||
#define LED_WPS_BLINK_OFF_INTERVAL_DLINK 300
|
||||
#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK 5000
|
||||
|
||||
/* ********************************************************************************
|
||||
* LED object.
|
||||
* ******************************************************************************** */
|
||||
|
||||
typedef enum _LED_CTL_MODE {
|
||||
LED_CTL_POWER_ON = 1,
|
||||
LED_CTL_LINK = 2,
|
||||
LED_CTL_NO_LINK = 3,
|
||||
LED_CTL_TX = 4, /* unspecific data TX, including single & group addressed */
|
||||
LED_CTL_RX = 5, /* unspecific data RX, including single & group addressed */
|
||||
LED_CTL_UC_TX = 6, /* single addressed data TX */
|
||||
LED_CTL_UC_RX = 7, /* single addressed data RX */
|
||||
LED_CTL_BMC_TX = 8, /* group addressed data TX */
|
||||
LED_CTL_BMC_RX = 9, /* group addressed data RX */
|
||||
LED_CTL_SITE_SURVEY = 10,
|
||||
LED_CTL_POWER_OFF = 11,
|
||||
LED_CTL_START_TO_LINK = 12,
|
||||
LED_CTL_START_WPS = 13,
|
||||
LED_CTL_STOP_WPS = 14,
|
||||
LED_CTL_START_WPS_BOTTON = 15, /* added for runtop */
|
||||
LED_CTL_STOP_WPS_FAIL = 16, /* added for ALPHA */
|
||||
LED_CTL_STOP_WPS_FAIL_OVERLAP = 17, /* added for BELKIN */
|
||||
LED_CTL_CONNECTION_NO_TRANSFER = 18,
|
||||
} LED_CTL_MODE;
|
||||
|
||||
typedef enum _LED_STATE {
|
||||
LED_UNKNOWN = 0,
|
||||
RTW_LED_ON = 1,
|
||||
RTW_LED_OFF = 2,
|
||||
LED_BLINK_NORMAL = 3,
|
||||
LED_BLINK_SLOWLY = 4,
|
||||
LED_BLINK_POWER_ON = 5,
|
||||
LED_BLINK_SCAN = 6, /* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */
|
||||
LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */
|
||||
LED_BLINK_StartToBlink = 8, /* Customzied for Sercomm Printer Server case */
|
||||
LED_BLINK_TXRX = 9,
|
||||
LED_BLINK_WPS = 10, /* LED is blinkg during WPS communication */
|
||||
LED_BLINK_WPS_STOP = 11, /* for ALPHA */
|
||||
LED_BLINK_WPS_STOP_OVERLAP = 12, /* for BELKIN */
|
||||
LED_BLINK_RUNTOP = 13, /* Customized for RunTop */
|
||||
LED_BLINK_CAMEO = 14,
|
||||
LED_BLINK_XAVI = 15,
|
||||
LED_BLINK_ALWAYS_ON = 16,
|
||||
LED_BLINK_LINK_IN_PROCESS = 17, /* Customized for Belkin AC950 */
|
||||
LED_BLINK_AUTH_ERROR = 18, /* Customized for Belkin AC950 */
|
||||
LED_BLINK_Azurewave_5Mbps = 19,
|
||||
LED_BLINK_Azurewave_10Mbps = 20,
|
||||
LED_BLINK_Azurewave_20Mbps = 21,
|
||||
LED_BLINK_Azurewave_40Mbps = 22,
|
||||
LED_BLINK_Azurewave_80Mbps = 23,
|
||||
LED_BLINK_Azurewave_MAXMbps = 24,
|
||||
LED_BLINK_LINK_IDEL = 25,
|
||||
LED_BLINK_WPS_LINKED = 26,
|
||||
} LED_STATE;
|
||||
|
||||
typedef enum _LED_PIN {
|
||||
LED_PIN_GPIO0,
|
||||
LED_PIN_LED0,
|
||||
LED_PIN_LED1,
|
||||
LED_PIN_LED2
|
||||
} LED_PIN;
|
||||
|
||||
|
||||
/* ********************************************************************************
|
||||
* PCIE LED Definition.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
typedef enum _LED_STRATEGY_PCIE {
|
||||
/* start from 2 */
|
||||
SW_LED_MODE_UC_TRX_ONLY = 2,
|
||||
SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
|
||||
SW_LED_MODE1, /* SW control for PCI Express */
|
||||
SW_LED_MODE2, /* SW control for Cameo. */
|
||||
SW_LED_MODE3, /* SW contorl for RunTop. */
|
||||
SW_LED_MODE4, /* SW control for Netcore */
|
||||
SW_LED_MODE5, /* added by vivi, for led new mode, DLINK */
|
||||
SW_LED_MODE6, /* added by vivi, for led new mode, PRONET */
|
||||
SW_LED_MODE7, /* added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec */
|
||||
SW_LED_MODE8, /* added by chiyokolin, for QMI */
|
||||
SW_LED_MODE9, /* added by chiyokolin, for BITLAND-LENOVO, PCI Express Minicard Spec Rev.1.1 */
|
||||
SW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */
|
||||
SW_LED_MODE11, /* added by hpfan, for Xavi */
|
||||
SW_LED_MODE12, /* added by chiyokolin, for Azurewave */
|
||||
} LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE;
|
||||
|
||||
typedef struct _LED_PCIE {
|
||||
PADAPTER padapter;
|
||||
|
||||
LED_PIN LedPin; /* Identify how to implement this SW led. */
|
||||
|
||||
LED_STATE CurrLedState; /* Current LED state. */
|
||||
BOOLEAN bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
|
||||
|
||||
BOOLEAN bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
|
||||
BOOLEAN bLedWPSBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
|
||||
|
||||
BOOLEAN bLedSlowBlinkInProgress;/* added by vivi, for led new mode */
|
||||
u32 BlinkTimes; /* Number of times to toggle led state for blinking. */
|
||||
LED_STATE BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
|
||||
|
||||
_timer BlinkTimer; /* Timer object for led blinking. */
|
||||
} LED_PCIE, *PLED_PCIE;
|
||||
|
||||
typedef struct _LED_PCIE LED_DATA, *PLED_DATA;
|
||||
typedef enum _LED_STRATEGY_PCIE LED_STRATEGY, *PLED_STRATEGY;
|
||||
|
||||
void
|
||||
LedControlPCIE(
|
||||
PADAPTER Adapter,
|
||||
LED_CTL_MODE LedAction
|
||||
);
|
||||
|
||||
void
|
||||
gen_RefreshLedState(
|
||||
PADAPTER Adapter);
|
||||
|
||||
/* ********************************************************************************
|
||||
* USB LED Definition.
|
||||
* ******************************************************************************** */
|
||||
#elif defined(CONFIG_USB_HCI)
|
||||
|
||||
#define IS_LED_WPS_BLINKING(_LED_USB) (((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS \
|
||||
|| ((PLED_USB)_LED_USB)->CurrLedState == LED_BLINK_WPS_STOP \
|
||||
|| ((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress)
|
||||
|
||||
#define IS_LED_BLINKING(_LED_USB) (((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress \
|
||||
|| ((PLED_USB)_LED_USB)->bLedScanBlinkInProgress)
|
||||
|
||||
|
||||
typedef enum _LED_STRATEGY_USB {
|
||||
/* start from 2 */
|
||||
SW_LED_MODE_UC_TRX_ONLY = 2,
|
||||
SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
|
||||
SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
|
||||
SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
|
||||
SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
|
||||
SW_LED_MODE4, /* for Edimax / Belkin */
|
||||
SW_LED_MODE5, /* for Sercomm / Belkin */
|
||||
SW_LED_MODE6, /* for 88CU minicard, porting from ce SW_LED_MODE7 */
|
||||
SW_LED_MODE7, /* for Netgear special requirement */
|
||||
SW_LED_MODE8, /* for LC */
|
||||
SW_LED_MODE9, /* for Belkin AC950 */
|
||||
SW_LED_MODE10, /* for Netgear A6200V2 */
|
||||
SW_LED_MODE11, /* for Edimax / ASUS */
|
||||
SW_LED_MODE12, /* for WNC/NEC */
|
||||
SW_LED_MODE13, /* for Netgear A6100, 8811Au */
|
||||
SW_LED_MODE14, /* for Buffalo, DNI, 8811Au */
|
||||
SW_LED_MODE15, /* for DLINK, 8811Au/8812AU */
|
||||
} LED_STRATEGY_USB, *PLED_STRATEGY_USB;
|
||||
|
||||
|
||||
typedef struct _LED_USB {
|
||||
PADAPTER padapter;
|
||||
|
||||
LED_PIN LedPin; /* Identify how to implement this SW led. */
|
||||
|
||||
LED_STATE CurrLedState; /* Current LED state. */
|
||||
BOOLEAN bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
|
||||
|
||||
BOOLEAN bSWLedCtrl;
|
||||
|
||||
BOOLEAN bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
|
||||
/* ALPHA, added by chiyoko, 20090106 */
|
||||
BOOLEAN bLedNoLinkBlinkInProgress;
|
||||
BOOLEAN bLedLinkBlinkInProgress;
|
||||
BOOLEAN bLedStartToLinkBlinkInProgress;
|
||||
BOOLEAN bLedScanBlinkInProgress;
|
||||
BOOLEAN bLedWPSBlinkInProgress;
|
||||
|
||||
u32 BlinkTimes; /* Number of times to toggle led state for blinking. */
|
||||
u8 BlinkCounter; /* Added for turn off overlap led after blinking a while, by page, 20120821 */
|
||||
LED_STATE BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
|
||||
|
||||
_timer BlinkTimer; /* Timer object for led blinking. */
|
||||
|
||||
_workitem BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED.' */
|
||||
} LED_USB, *PLED_USB;
|
||||
|
||||
typedef struct _LED_USB LED_DATA, *PLED_DATA;
|
||||
typedef enum _LED_STRATEGY_USB LED_STRATEGY, *PLED_STRATEGY;
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
void
|
||||
LedControlUSB(
|
||||
PADAPTER Adapter,
|
||||
LED_CTL_MODE LedAction
|
||||
);
|
||||
#endif
|
||||
|
||||
|
||||
/* ********************************************************************************
|
||||
* SDIO LED Definition.
|
||||
* ******************************************************************************** */
|
||||
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
|
||||
#define IS_LED_WPS_BLINKING(_LED_SDIO) (((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS \
|
||||
|| ((PLED_SDIO)_LED_SDIO)->CurrLedState == LED_BLINK_WPS_STOP \
|
||||
|| ((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress)
|
||||
|
||||
#define IS_LED_BLINKING(_LED_SDIO) (((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress \
|
||||
|| ((PLED_SDIO)_LED_SDIO)->bLedScanBlinkInProgress)
|
||||
|
||||
|
||||
typedef enum _LED_STRATEGY_SDIO {
|
||||
/* start from 2 */
|
||||
SW_LED_MODE_UC_TRX_ONLY = 2,
|
||||
SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
|
||||
SW_LED_MODE1, /* 2 LEDs, through LED0 and LED1. For ALPHA. */
|
||||
SW_LED_MODE2, /* SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. */
|
||||
SW_LED_MODE3, /* SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. */
|
||||
SW_LED_MODE4, /* for Edimax / Belkin */
|
||||
SW_LED_MODE5, /* for Sercomm / Belkin */
|
||||
SW_LED_MODE6, /* for 88CU minicard, porting from ce SW_LED_MODE7 */
|
||||
} LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO;
|
||||
|
||||
typedef struct _LED_SDIO {
|
||||
PADAPTER padapter;
|
||||
|
||||
LED_PIN LedPin; /* Identify how to implement this SW led. */
|
||||
|
||||
LED_STATE CurrLedState; /* Current LED state. */
|
||||
BOOLEAN bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */
|
||||
|
||||
BOOLEAN bSWLedCtrl;
|
||||
|
||||
BOOLEAN bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */
|
||||
/* ALPHA, added by chiyoko, 20090106 */
|
||||
BOOLEAN bLedNoLinkBlinkInProgress;
|
||||
BOOLEAN bLedLinkBlinkInProgress;
|
||||
BOOLEAN bLedStartToLinkBlinkInProgress;
|
||||
BOOLEAN bLedScanBlinkInProgress;
|
||||
BOOLEAN bLedWPSBlinkInProgress;
|
||||
|
||||
u32 BlinkTimes; /* Number of times to toggle led state for blinking. */
|
||||
LED_STATE BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */
|
||||
|
||||
_timer BlinkTimer; /* Timer object for led blinking. */
|
||||
|
||||
_workitem BlinkWorkItem; /* Workitem used by BlinkTimer to manipulate H/W to blink LED. */
|
||||
} LED_SDIO, *PLED_SDIO;
|
||||
|
||||
typedef struct _LED_SDIO LED_DATA, *PLED_DATA;
|
||||
typedef enum _LED_STRATEGY_SDIO LED_STRATEGY, *PLED_STRATEGY;
|
||||
|
||||
void
|
||||
LedControlSDIO(
|
||||
PADAPTER Adapter,
|
||||
LED_CTL_MODE LedAction
|
||||
);
|
||||
|
||||
#endif
|
||||
|
||||
struct led_priv {
|
||||
LED_STRATEGY LedStrategy;
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
LED_DATA SwLed0;
|
||||
LED_DATA SwLed1;
|
||||
LED_DATA SwLed2;
|
||||
u8 bRegUseLed;
|
||||
u8 iface_en_mask;
|
||||
u32 ctl_en_mask[CONFIG_IFACE_NUMBER];
|
||||
void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction);
|
||||
void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed);
|
||||
void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed);
|
||||
#endif
|
||||
};
|
||||
|
||||
#define SwLedOn(adapter, pLed) \
|
||||
do { \
|
||||
if (adapter_to_led(adapter)->SwLedOn) \
|
||||
adapter_to_led(adapter)->SwLedOn((adapter), (pLed)); \
|
||||
} while (0)
|
||||
|
||||
#define SwLedOff(adapter, pLed) \
|
||||
do { \
|
||||
if (adapter_to_led(adapter)->SwLedOff) \
|
||||
adapter_to_led(adapter)->SwLedOff((adapter), (pLed)); \
|
||||
} while (0)
|
||||
|
||||
void BlinkTimerCallback(void *data);
|
||||
void BlinkWorkItemCallback(_workitem *work);
|
||||
|
||||
void ResetLedStatus(PLED_DATA pLed);
|
||||
|
||||
void
|
||||
InitLed(
|
||||
_adapter *padapter,
|
||||
PLED_DATA pLed,
|
||||
LED_PIN LedPin
|
||||
);
|
||||
|
||||
void
|
||||
DeInitLed(
|
||||
PLED_DATA pLed
|
||||
);
|
||||
|
||||
/* hal... */
|
||||
extern void BlinkHandler(PLED_DATA pLed);
|
||||
void dump_led_config(void *sel, _adapter *adapter);
|
||||
void rtw_led_set_strategy(_adapter *adapter, u8 strategy);
|
||||
#endif /* CONFIG_RTW_LED */
|
||||
|
||||
#if defined(CONFIG_RTW_LED)
|
||||
#define rtw_led_get_strategy(adapter) (adapter_to_led(adapter)->LedStrategy)
|
||||
#else
|
||||
#define rtw_led_get_strategy(adapter) NO_LED
|
||||
#endif
|
||||
|
||||
#define IS_NO_LED_STRATEGY(s) ((s) == NO_LED)
|
||||
#define IS_HW_LED_STRATEGY(s) ((s) == HW_LED)
|
||||
#define IS_SW_LED_STRATEGY(s) ((s) != NO_LED && (s) != HW_LED)
|
||||
|
||||
#if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED)
|
||||
|
||||
#ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
|
||||
#define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0
|
||||
#endif
|
||||
|
||||
#if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
|
||||
void rtw_sw_led_blink_uc_trx_only(LED_DATA *led);
|
||||
void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl);
|
||||
#endif
|
||||
void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl);
|
||||
void rtw_led_tx_control(_adapter *adapter, const u8 *da);
|
||||
void rtw_led_rx_control(_adapter *adapter, const u8 *da);
|
||||
void rtw_led_set_iface_en(_adapter *adapter, u8 en);
|
||||
void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask);
|
||||
void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask);
|
||||
void rtw_led_set_ctl_en_mask_primary(_adapter *adapter);
|
||||
void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter);
|
||||
#else
|
||||
#define rtw_led_control(adapter, ctl) do {} while (0)
|
||||
#define rtw_led_tx_control(adapter, da) do {} while (0)
|
||||
#define rtw_led_rx_control(adapter, da) do {} while (0)
|
||||
#define rtw_led_set_iface_en(adapter, en) do {} while (0)
|
||||
#define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0)
|
||||
#define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0)
|
||||
#define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0)
|
||||
#define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0)
|
||||
#endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */
|
||||
|
||||
#endif /*__HAL_COMMON_LED_H_*/
|
||||
|
||||
|
|
@ -0,0 +1,341 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_COM_PHYCFG_H__
|
||||
#define __HAL_COM_PHYCFG_H__
|
||||
|
||||
#ifndef DBG_TX_POWER_IDX
|
||||
#define DBG_TX_POWER_IDX 0
|
||||
#endif
|
||||
|
||||
#define PathA 0x0 /* Useless */
|
||||
#define PathB 0x1
|
||||
#define PathC 0x2
|
||||
#define PathD 0x3
|
||||
|
||||
typedef enum _RF_TX_NUM {
|
||||
RF_1TX = 0,
|
||||
RF_2TX,
|
||||
RF_3TX,
|
||||
RF_4TX,
|
||||
RF_MAX_TX_NUM,
|
||||
RF_TX_NUM_NONIMPLEMENT,
|
||||
} RF_TX_NUM;
|
||||
|
||||
enum txpwr_pg_mode {
|
||||
TXPWR_PG_WITH_PWR_IDX,
|
||||
TXPWR_PG_WITH_TSSI_OFFSET,
|
||||
TXPWR_PG_UNKNOWN, /* keep last */
|
||||
};
|
||||
|
||||
/*------------------------------Define structure----------------------------*/
|
||||
typedef struct _BB_REGISTER_DEFINITION {
|
||||
u32 rfintfs; /* set software control: */
|
||||
/* 0x870~0x877[8 bytes] */
|
||||
|
||||
u32 rfintfo; /* output data: */
|
||||
/* 0x860~0x86f [16 bytes] */
|
||||
|
||||
u32 rfintfe; /* output enable: */
|
||||
/* 0x860~0x86f [16 bytes] */
|
||||
|
||||
u32 rf3wireOffset; /* LSSI data: */
|
||||
/* 0x840~0x84f [16 bytes] */
|
||||
|
||||
u32 rfHSSIPara2; /* wire parameter control2 : */
|
||||
/* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
|
||||
|
||||
u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
|
||||
/* 0x8a0~0x8af [16 bytes] */
|
||||
|
||||
u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
|
||||
|
||||
} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------- */
|
||||
|
||||
extern const char *const _txpwr_pg_mode_str[];
|
||||
#define txpwr_pg_mode_str(_mode) (((_mode) >= TXPWR_PG_UNKNOWN) ? _txpwr_pg_mode_str[TXPWR_PG_UNKNOWN] : _txpwr_pg_mode_str[(_mode)])
|
||||
|
||||
u8 phy_get_target_txpwr(
|
||||
PADAPTER Adapter,
|
||||
u8 Band,
|
||||
u8 RfPath,
|
||||
RATE_SECTION RateSection
|
||||
);
|
||||
|
||||
void
|
||||
PHY_GetRateValuesOfTxPowerByRate(
|
||||
PADAPTER pAdapter,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Value,
|
||||
u8 *Rate,
|
||||
s8 *PwrByRateVal,
|
||||
u8 *RateNum
|
||||
);
|
||||
|
||||
u8 phy_get_rate_idx_of_txpwr_by_rate(enum MGN_RATE rate);
|
||||
|
||||
void
|
||||
phy_set_tx_power_index_by_rate_section(
|
||||
PADAPTER pAdapter,
|
||||
enum rf_path RFPath,
|
||||
u8 Channel,
|
||||
u8 RateSection
|
||||
);
|
||||
|
||||
s8 phy_get_txpwr_by_rate(_adapter *adapter
|
||||
, BAND_TYPE band, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate);
|
||||
|
||||
s16 phy_get_txpwr_by_rate_single_mbm(_adapter *adapter
|
||||
, BAND_TYPE band, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, bool eirp);
|
||||
s16 phy_get_txpwr_by_rate_total_mbm(_adapter *adapter
|
||||
, BAND_TYPE band, RATE_SECTION rs, enum MGN_RATE rate, bool cap, bool eirp);
|
||||
|
||||
s16 phy_get_txpwr_by_rate_single_max_mbm(_adapter *adapter, BAND_TYPE band, enum rf_path rfpath, bool eirp);
|
||||
s16 phy_get_txpwr_by_rate_total_max_mbm(_adapter *adapter, BAND_TYPE band, bool cap, bool eirp);
|
||||
|
||||
void
|
||||
phy_set_tx_power_level_by_path(
|
||||
PADAPTER Adapter,
|
||||
u8 channel,
|
||||
u8 path
|
||||
);
|
||||
|
||||
void
|
||||
PHY_InitTxPowerByRate(
|
||||
PADAPTER pAdapter
|
||||
);
|
||||
|
||||
void
|
||||
phy_store_tx_power_by_rate(
|
||||
PADAPTER pAdapter,
|
||||
u32 Band,
|
||||
u32 RfPath,
|
||||
u32 TxNum,
|
||||
u32 RegAddr,
|
||||
u32 BitMask,
|
||||
u32 Data
|
||||
);
|
||||
|
||||
void
|
||||
PHY_TxPowerByRateConfiguration(
|
||||
PADAPTER pAdapter
|
||||
);
|
||||
|
||||
bool phy_chk_ch_setting_consistency(_adapter *adapter, u8 ch);
|
||||
|
||||
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
u8 phy_get_pg_txpwr_idx(_adapter *pAdapter
|
||||
, enum rf_path RFPath, RATE_SECTION rs, u8 ntx_idx
|
||||
, enum channel_width BandWidth, u8 band, u8 Channel);
|
||||
#endif
|
||||
|
||||
#if CONFIG_TXPWR_LIMIT
|
||||
s8 phy_get_txpwr_lmt(_adapter *adapter
|
||||
, const char *regd_name
|
||||
, BAND_TYPE band, enum channel_width bw
|
||||
, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
|
||||
);
|
||||
|
||||
s8 phy_get_txpwr_lmt_diff(_adapter *adapter
|
||||
, const char *regd_name
|
||||
, BAND_TYPE band, enum channel_width bw
|
||||
, u8 rfpath, u8 rs, u8 tlrs, u8 ntx_idx, u8 cch, u8 lock
|
||||
);
|
||||
|
||||
s8 phy_get_txpwr_lmt_sub_chs(_adapter *adapter
|
||||
, const char *regd_name
|
||||
, BAND_TYPE band, enum channel_width bw
|
||||
, u8 rfpath, u8 rate, u8 ntx_idx, u8 cch, u8 opch, bool reg_max
|
||||
);
|
||||
#else
|
||||
#define phy_get_txpwr_lmt(adapter, regd_name, band, bw, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
|
||||
#define phy_get_txpwr_lmt_diff(adapter, regd_name, band, bw, rfpath, rs, tlrs, ntx_idx, cch, lock) (GET_HAL_SPEC(adapter)->txgi_max)
|
||||
#define phy_get_txpwr_lmt_sub_chs(adapter, regd_name, band, bw, rfpath, rate, ntx_idx, cch, opch, reg_max) (GET_HAL_SPEC(adapter)->txgi_max)
|
||||
#endif /* CONFIG_TXPWR_LIMIT */
|
||||
|
||||
void dump_txpwr_tpc_settings(void *sel, _adapter *adapter);
|
||||
void dump_txpwr_antenna_gain(void *sel, _adapter *adapter);
|
||||
|
||||
s8 phy_get_txpwr_target(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
|
||||
, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, bool reg_max, struct txpwr_idx_comp *tic);
|
||||
s8 phy_get_txpwr_amends(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate, u8 ntx_idx
|
||||
, enum channel_width bw, BAND_TYPE band, u8 cch, struct txpwr_idx_comp *tic);
|
||||
#ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
|
||||
s8 phy_get_tssi_txpwr_by_rate_ref(_adapter *adapter, enum rf_path path
|
||||
, enum channel_width bw, u8 cch, u8 opch);
|
||||
#endif
|
||||
u8 hal_com_get_txpwr_idx(_adapter *adapter, enum rf_path rfpath
|
||||
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
|
||||
, struct txpwr_idx_comp *tic);
|
||||
|
||||
s16 phy_get_txpwr_single_mbm(_adapter *adapter, u8 rfpath, RATE_SECTION rs, u8 rate
|
||||
, enum channel_width bw, u8 cch, u8 opch, bool reg_max, bool eirp, struct txpwr_idx_comp *tic);
|
||||
s16 phy_get_txpwr_total_mbm(_adapter *adapter, RATE_SECTION rs, u8 rate
|
||||
, enum channel_width bw, u8 cch, u8 opch, bool reg_max, bool eirp, struct txpwr_idx_comp *tic);
|
||||
|
||||
s16 phy_get_txpwr_single_max_mbm(_adapter *adapter, u8 rfpath
|
||||
, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht, bool reg_max, bool eirp);
|
||||
s16 phy_get_txpwr_total_max_mbm(_adapter *adapter
|
||||
, enum channel_width bw, u8 cch, u8 opch, u16 bmp_cck_ofdm, u32 bmp_ht, u64 bmp_vht, bool reg_max, bool eirp);
|
||||
|
||||
s8
|
||||
phy_get_tx_power_final_absolute_value(_adapter *adapter, u8 rfpath, u8 rate,
|
||||
enum channel_width bw, u8 channel);
|
||||
|
||||
s8
|
||||
PHY_GetTxPowerTrackingOffset(
|
||||
PADAPTER pAdapter,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
struct txpwr_idx_comp {
|
||||
u8 ntx_idx;
|
||||
s8 target;
|
||||
s8 base;
|
||||
|
||||
/* for target */
|
||||
s8 by_rate;
|
||||
s8 btc;
|
||||
s8 extra;
|
||||
s8 utarget;
|
||||
s8 rlimit; /* regulatory limit w/o HAL consideration */
|
||||
s8 limit; /* limit from RTK private (regulatory limit w/ HAL consideration) */
|
||||
s8 ulimit; /* user limit */
|
||||
s8 tpc;
|
||||
|
||||
/* for amends */
|
||||
s8 tpt;
|
||||
s8 dpd;
|
||||
};
|
||||
|
||||
u8 phy_get_tx_power_index_ex(_adapter *adapter
|
||||
, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
|
||||
, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch);
|
||||
|
||||
u8
|
||||
phy_get_tx_power_index(
|
||||
PADAPTER pAdapter,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate,
|
||||
enum channel_width BandWidth,
|
||||
u8 Channel
|
||||
);
|
||||
|
||||
void
|
||||
PHY_SetTxPowerIndex(
|
||||
PADAPTER pAdapter,
|
||||
u32 PowerIndex,
|
||||
enum rf_path RFPath,
|
||||
u8 Rate
|
||||
);
|
||||
|
||||
bool phy_is_txpwr_user_mbm_valid(_adapter *adapter, s16 mbm);
|
||||
bool phy_is_txpwr_user_target_specified(_adapter *adapter);
|
||||
|
||||
void dump_tx_power_index_inline(void *sel, _adapter *adapter, u8 rfpath
|
||||
, enum channel_width bw, u8 cch, enum MGN_RATE rate, u8 pwr_idx, struct txpwr_idx_comp *tic);
|
||||
#ifdef CONFIG_PROC_DEBUG
|
||||
void dump_tx_power_idx_title(void *sel, _adapter *adapter
|
||||
, enum channel_width bw, u8 cch, u8 opch);
|
||||
void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath
|
||||
, RATE_SECTION rs, enum channel_width bw, u8 cch, u8 opch);
|
||||
void dump_tx_power_idx(void *sel, _adapter *adapter
|
||||
, enum channel_width bw, u8 cch, u8 opch);
|
||||
void dump_txpwr_total_dbm_title(void *sel, _adapter *adapter
|
||||
, enum channel_width bw, u8 cch, u8 opch);
|
||||
void dump_txpwr_total_dbm_by_rs(void *sel, _adapter *adapter, u8 rs
|
||||
, enum channel_width bw, u8 cch, u8 opch);
|
||||
void dump_txpwr_total_dbm(void *sel, _adapter *adapter
|
||||
, enum channel_width bw, u8 cch, u8 opch);
|
||||
#endif
|
||||
|
||||
bool phy_is_tx_power_limit_needed(_adapter *adapter);
|
||||
bool phy_is_tx_power_by_rate_needed(_adapter *adapter);
|
||||
int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file);
|
||||
#if CONFIG_TXPWR_LIMIT
|
||||
int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file);
|
||||
#endif
|
||||
void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file);
|
||||
void phy_reload_tx_power_ext_info(_adapter *adapter);
|
||||
void phy_reload_default_tx_power_ext_info(_adapter *adapter);
|
||||
|
||||
const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter);
|
||||
|
||||
#ifdef CONFIG_EFUSE_CONFIG_FILE
|
||||
int check_phy_efuse_tx_power_info_valid(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
|
||||
void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt);
|
||||
|
||||
void hal_load_txpwr_info(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PROC_DEBUG
|
||||
void dump_tx_power_ext_info(void *sel, _adapter *adapter);
|
||||
void dump_target_tx_power(void *sel, _adapter *adapter);
|
||||
void dump_tx_power_by_rate(void *sel, _adapter *adapter);
|
||||
#endif
|
||||
|
||||
int rtw_get_phy_file_path(_adapter *adapter, const char *file_name);
|
||||
|
||||
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
|
||||
#define MAC_FILE_FW_NIC "FW_NIC.bin"
|
||||
#define MAC_FILE_FW_WW_IMG "FW_WoWLAN.bin"
|
||||
#define PHY_FILE_MAC_REG "MAC_REG.txt"
|
||||
|
||||
#define PHY_FILE_AGC_TAB "AGC_TAB.txt"
|
||||
#define PHY_FILE_PHY_REG "PHY_REG.txt"
|
||||
#define PHY_FILE_PHY_REG_MP "PHY_REG_MP.txt"
|
||||
#define PHY_FILE_PHY_REG_PG "PHY_REG_PG.txt"
|
||||
|
||||
#define PHY_FILE_RADIO_A "RadioA.txt"
|
||||
#define PHY_FILE_RADIO_B "RadioB.txt"
|
||||
#define PHY_FILE_RADIO_C "RadioC.txt"
|
||||
#define PHY_FILE_RADIO_D "RadioD.txt"
|
||||
#define PHY_FILE_TXPWR_TRACK "TxPowerTrack.txt"
|
||||
#define PHY_FILE_TXPWR_LMT "TXPWR_LMT.txt"
|
||||
|
||||
#define PHY_FILE_WIFI_ANT_ISOLATION "wifi_ant_isolation.txt"
|
||||
|
||||
#define MAX_PARA_FILE_BUF_LEN 32768 /* 32k */
|
||||
|
||||
#define LOAD_MAC_PARA_FILE BIT0
|
||||
#define LOAD_BB_PARA_FILE BIT1
|
||||
#define LOAD_BB_PG_PARA_FILE BIT2
|
||||
#define LOAD_BB_MP_PARA_FILE BIT3
|
||||
#define LOAD_RF_PARA_FILE BIT4
|
||||
#define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5
|
||||
#define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6
|
||||
|
||||
int phy_ConfigMACWithParaFile(PADAPTER Adapter, char *pFileName);
|
||||
int phy_ConfigBBWithParaFile(PADAPTER Adapter, char *pFileName, u32 ConfigType);
|
||||
int phy_ConfigBBWithPgParaFile(PADAPTER Adapter, const char *pFileName);
|
||||
int phy_ConfigBBWithMpParaFile(PADAPTER Adapter, char *pFileName);
|
||||
int PHY_ConfigRFWithParaFile(PADAPTER Adapter, char *pFileName, enum rf_path eRFPath);
|
||||
int PHY_ConfigRFWithTxPwrTrackParaFile(PADAPTER Adapter, char *pFileName);
|
||||
#if CONFIG_TXPWR_LIMIT
|
||||
int PHY_ConfigRFWithPowerLimitTableParaFile(PADAPTER Adapter, const char *pFileName);
|
||||
#endif
|
||||
void phy_free_filebuf_mask(_adapter *padapter, u8 mask);
|
||||
void phy_free_filebuf(_adapter *padapter);
|
||||
#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
|
||||
u8 phy_check_under_survey_ch(_adapter *adapter);
|
||||
#endif /* __HAL_COMMON_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,881 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_DATA_H__
|
||||
#define __HAL_DATA_H__
|
||||
|
||||
#if 1/* def CONFIG_SINGLE_IMG */
|
||||
|
||||
#include "../hal/phydm/phydm_precomp.h"
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
#include <hal_btcoex.h>
|
||||
#endif
|
||||
#include <hal_btcoex_wifionly.h>
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#include <hal_sdio.h>
|
||||
#endif
|
||||
#ifdef CONFIG_GSPI_HCI
|
||||
#include <hal_gspi.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTW_ACS) || defined(CONFIG_BACKGROUND_NOISE_MONITOR)
|
||||
#include "../hal/hal_dm_acs.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
|
||||
* */
|
||||
typedef enum _RT_MULTI_FUNC {
|
||||
RT_MULTI_FUNC_NONE = 0x00,
|
||||
RT_MULTI_FUNC_WIFI = 0x01,
|
||||
RT_MULTI_FUNC_BT = 0x02,
|
||||
RT_MULTI_FUNC_GPS = 0x04,
|
||||
} RT_MULTI_FUNC, *PRT_MULTI_FUNC;
|
||||
/*
|
||||
* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
|
||||
* */
|
||||
typedef enum _RT_POLARITY_CTL {
|
||||
RT_POLARITY_LOW_ACT = 0,
|
||||
RT_POLARITY_HIGH_ACT = 1,
|
||||
} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
|
||||
|
||||
/* For RTL8723 regulator mode. by tynli. 2011.01.14. */
|
||||
typedef enum _RT_REGULATOR_MODE {
|
||||
RT_SWITCHING_REGULATOR = 0,
|
||||
RT_LDO_REGULATOR = 1,
|
||||
} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
|
||||
|
||||
/*
|
||||
* Interface type.
|
||||
* */
|
||||
typedef enum _INTERFACE_SELECT_PCIE {
|
||||
INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */
|
||||
INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */
|
||||
INTF_SEL2_PCIe = 2, /* PCIe Card */
|
||||
} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE;
|
||||
|
||||
|
||||
typedef enum _INTERFACE_SELECT_USB {
|
||||
INTF_SEL0_USB = 0, /* USB */
|
||||
INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */
|
||||
INTF_SEL2_MINICARD = 2, /* Minicard */
|
||||
INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */
|
||||
INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */
|
||||
INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */
|
||||
} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
|
||||
|
||||
typedef enum _RT_AMPDU_BRUST_MODE {
|
||||
RT_AMPDU_BRUST_NONE = 0,
|
||||
RT_AMPDU_BRUST_92D = 1,
|
||||
RT_AMPDU_BRUST_88E = 2,
|
||||
RT_AMPDU_BRUST_8812_4 = 3,
|
||||
RT_AMPDU_BRUST_8812_8 = 4,
|
||||
RT_AMPDU_BRUST_8812_12 = 5,
|
||||
RT_AMPDU_BRUST_8812_15 = 6,
|
||||
RT_AMPDU_BRUST_8723B = 7,
|
||||
} RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE;
|
||||
|
||||
/* Tx Power Limit Table Size */
|
||||
#define MAX_REGULATION_NUM 4
|
||||
#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4
|
||||
#define MAX_2_4G_BANDWIDTH_NUM 2
|
||||
#define MAX_RATE_SECTION_NUM 10
|
||||
#define MAX_5G_BANDWIDTH_NUM 4
|
||||
|
||||
#define NUM_OF_TARGET_TXPWR_2G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
|
||||
#define NUM_OF_TARGET_TXPWR_5G 9 /* OFDM:1, HT:4, VHT:4 */
|
||||
|
||||
#ifdef RTW_RX_AGGREGATION
|
||||
typedef enum _RX_AGG_MODE {
|
||||
RX_AGG_DISABLE,
|
||||
RX_AGG_DMA,
|
||||
RX_AGG_USB,
|
||||
RX_AGG_MIX
|
||||
} RX_AGG_MODE;
|
||||
|
||||
/* #define MAX_RX_DMA_BUFFER_SIZE 10240 */ /* 10K for 8192C RX DMA buffer */
|
||||
|
||||
#endif /* RTW_RX_AGGREGATION */
|
||||
|
||||
/* E-Fuse */
|
||||
#ifdef CONFIG_RTL8188E
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8192E
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8723B
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8814A
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8703B
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8723D
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8188F
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8188GTV
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8710B
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8192F
|
||||
#define EFUSE_MAP_SIZE 512
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8814B)
|
||||
#define EFUSE_MAX_SIZE 1024
|
||||
#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8710B)
|
||||
#define EFUSE_MAX_SIZE 256
|
||||
#else
|
||||
#define EFUSE_MAX_SIZE 512
|
||||
#endif
|
||||
/* end of E-Fuse */
|
||||
|
||||
#define Mac_OFDM_OK 0x00000000
|
||||
#define Mac_OFDM_Fail 0x10000000
|
||||
#define Mac_OFDM_FasleAlarm 0x20000000
|
||||
#define Mac_CCK_OK 0x30000000
|
||||
#define Mac_CCK_Fail 0x40000000
|
||||
#define Mac_CCK_FasleAlarm 0x50000000
|
||||
#define Mac_HT_OK 0x60000000
|
||||
#define Mac_HT_Fail 0x70000000
|
||||
#define Mac_HT_FasleAlarm 0x90000000
|
||||
#define Mac_DropPacket 0xA0000000
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
#if defined(CONFIG_RTL8723B)
|
||||
#define REG_RF_BB_GAIN_OFFSET 0x7f
|
||||
#define RF_GAIN_OFFSET_MASK 0xfffff
|
||||
#elif defined(CONFIG_RTL8188E)
|
||||
#define REG_RF_BB_GAIN_OFFSET 0x55
|
||||
#define RF_GAIN_OFFSET_MASK 0xfffff
|
||||
#else
|
||||
#define REG_RF_BB_GAIN_OFFSET 0x55
|
||||
#define RF_GAIN_OFFSET_MASK 0xfffff
|
||||
#endif /* CONFIG_RTL8723B */
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
/* For store initial value of BB register */
|
||||
typedef struct _BB_INIT_REGISTER {
|
||||
u16 offset;
|
||||
u32 value;
|
||||
|
||||
} BB_INIT_REGISTER, *PBB_INIT_REGISTER;
|
||||
|
||||
#define PAGE_SIZE_128 128
|
||||
#define PAGE_SIZE_256 256
|
||||
#define PAGE_SIZE_512 512
|
||||
|
||||
#define HCI_SUS_ENTER 0
|
||||
#define HCI_SUS_LEAVING 1
|
||||
#define HCI_SUS_LEAVE 2
|
||||
#define HCI_SUS_ENTERING 3
|
||||
#define HCI_SUS_ERR 4
|
||||
|
||||
#define EFUSE_FILE_UNUSED 0
|
||||
#define EFUSE_FILE_FAILED 1
|
||||
#define EFUSE_FILE_LOADED 2
|
||||
|
||||
#define MACADDR_FILE_UNUSED 0
|
||||
#define MACADDR_FILE_FAILED 1
|
||||
#define MACADDR_FILE_LOADED 2
|
||||
|
||||
#define MAX_IQK_INFO_BACKUP_CHNL_NUM 5
|
||||
#define MAX_IQK_INFO_BACKUP_REG_NUM 10
|
||||
|
||||
struct kfree_data_t {
|
||||
u8 flag;
|
||||
s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
|
||||
|
||||
#if CONFIG_IEEE80211_BAND_5GHZ
|
||||
s8 pa_bias_5g[RF_PATH_MAX];
|
||||
s8 pad_bias_5g[RF_PATH_MAX];
|
||||
#endif
|
||||
s8 thermal;
|
||||
};
|
||||
|
||||
bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data);
|
||||
|
||||
struct hal_spec_t {
|
||||
char *ic_name;
|
||||
u8 macid_num;
|
||||
|
||||
u8 sec_cam_ent_num;
|
||||
u8 sec_cap;
|
||||
u8 wow_cap;
|
||||
u8 macid_cap;
|
||||
u16 macid_txrpt;
|
||||
u8 macid_txrpt_pgsz;
|
||||
|
||||
u8 rfpath_num_2g:4; /* used for tx power index path */
|
||||
u8 rfpath_num_5g:4; /* used for tx power index path */
|
||||
u8 rf_reg_path_num;
|
||||
u8 rf_reg_path_avail_num;
|
||||
u8 rf_reg_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */
|
||||
u8 max_tx_cnt;
|
||||
|
||||
u8 tx_nss_num:4;
|
||||
u8 rx_nss_num:4;
|
||||
|
||||
u8 band_cap; /* value of BAND_CAP_XXX */
|
||||
u8 bw_cap; /* value of BW_CAP_XXX */
|
||||
u8 port_num;
|
||||
u8 proto_cap; /* value of PROTO_CAP_XXX */
|
||||
|
||||
u8 txgi_max; /* maximum tx power gain index */
|
||||
u8 txgi_pdbm; /* tx power gain index per dBm */
|
||||
|
||||
u8 wl_func; /* value of WL_FUNC_XXX */
|
||||
|
||||
u8 tx_aclt_unit_factor; /* how many 32us */
|
||||
|
||||
u8 rx_tsf_filter:1;
|
||||
|
||||
u8 pg_txpwr_saddr; /* starting address of PG tx power info */
|
||||
u8 pg_txgi_diff_factor; /* PG tx power gain index diff to tx power gain index */
|
||||
|
||||
u8 hci_type; /* value of HCI Type */
|
||||
};
|
||||
|
||||
#define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path))
|
||||
#define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path))
|
||||
#define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \
|
||||
_band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \
|
||||
_band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0)
|
||||
|
||||
#ifdef CONFIG_PHY_CAPABILITY_QUERY
|
||||
struct phy_spec_t {
|
||||
u32 trx_cap;
|
||||
u32 stbc_cap;
|
||||
u32 ldpc_cap;
|
||||
u32 txbf_param;
|
||||
u32 txbf_cap;
|
||||
};
|
||||
#endif
|
||||
struct hal_iqk_reg_backup {
|
||||
u8 central_chnl;
|
||||
u8 bw_mode;
|
||||
u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM];
|
||||
};
|
||||
|
||||
|
||||
typedef struct hal_p2p_ps_para {
|
||||
/*DW0*/
|
||||
u8 offload_en:1;
|
||||
u8 role:1;
|
||||
u8 ctwindow_en:1;
|
||||
u8 noa_en:1;
|
||||
u8 noa_sel:1;
|
||||
u8 all_sta_sleep:1;
|
||||
u8 discovery:1;
|
||||
u8 disable_close_rf:1;
|
||||
u8 p2p_port_id;
|
||||
u8 p2p_group;
|
||||
u8 p2p_macid;
|
||||
|
||||
/*DW1*/
|
||||
u8 ctwindow_length;
|
||||
u8 rsvd3;
|
||||
u8 rsvd4;
|
||||
u8 rsvd5;
|
||||
|
||||
/*DW2*/
|
||||
u32 noa_duration_para;
|
||||
|
||||
/*DW3*/
|
||||
u32 noa_interval_para;
|
||||
|
||||
/*DW4*/
|
||||
u32 noa_start_time_para;
|
||||
|
||||
/*DW5*/
|
||||
u32 noa_count_para;
|
||||
} HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA;
|
||||
|
||||
#define TXPWR_LMT_RS_CCK 0
|
||||
#define TXPWR_LMT_RS_OFDM 1
|
||||
#define TXPWR_LMT_RS_HT 2
|
||||
#define TXPWR_LMT_RS_VHT 3
|
||||
#define TXPWR_LMT_RS_NUM 4
|
||||
|
||||
#define TXPWR_LMT_RS_NUM_2G 4 /* CCK, OFDM, HT, VHT */
|
||||
#define TXPWR_LMT_RS_NUM_5G 3 /* OFDM, HT, VHT */
|
||||
|
||||
#if CONFIG_TXPWR_LIMIT
|
||||
extern const char *const _txpwr_lmt_rs_str[];
|
||||
#define txpwr_lmt_rs_str(rs) (((rs) >= TXPWR_LMT_RS_NUM) ? _txpwr_lmt_rs_str[TXPWR_LMT_RS_NUM] : _txpwr_lmt_rs_str[(rs)])
|
||||
|
||||
struct txpwr_lmt_ent {
|
||||
_list list;
|
||||
|
||||
s8 lmt_2g[MAX_2_4G_BANDWIDTH_NUM]
|
||||
[TXPWR_LMT_RS_NUM_2G]
|
||||
[CENTER_CH_2G_NUM]
|
||||
[MAX_TX_COUNT];
|
||||
|
||||
#if CONFIG_IEEE80211_BAND_5GHZ
|
||||
s8 lmt_5g[MAX_5G_BANDWIDTH_NUM]
|
||||
[TXPWR_LMT_RS_NUM_5G]
|
||||
[CENTER_CH_5G_ALL_NUM]
|
||||
[MAX_TX_COUNT];
|
||||
#endif
|
||||
|
||||
char regd_name[0];
|
||||
};
|
||||
#endif /* CONFIG_TXPWR_LIMIT */
|
||||
|
||||
typedef struct hal_com_data {
|
||||
HAL_VERSION version_id;
|
||||
RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */
|
||||
RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */
|
||||
RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */
|
||||
u8 hw_init_completed;
|
||||
/****** FW related ******/
|
||||
u32 firmware_size;
|
||||
u16 firmware_version;
|
||||
u16 FirmwareVersionRev;
|
||||
u16 firmware_sub_version;
|
||||
u16 FirmwareSignature;
|
||||
u8 RegFWOffload;
|
||||
u8 bFWReady;
|
||||
u8 bBTFWReady;
|
||||
u8 fw_ractrl;
|
||||
u8 LastHMEBoxNum; /* H2C - for host message to fw */
|
||||
#ifdef CONFIG_LPS_1T1R
|
||||
u8 lps_1t1r;
|
||||
#endif
|
||||
|
||||
/****** current WIFI_PHY values ******/
|
||||
WIRELESS_MODE CurrentWirelessMode;
|
||||
enum channel_width current_channel_bw;
|
||||
BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */
|
||||
u8 current_channel;
|
||||
u8 cch_20;
|
||||
u8 cch_40;
|
||||
u8 cch_80;
|
||||
u8 CurrentCenterFrequencyIndex1;
|
||||
u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */
|
||||
u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */
|
||||
BOOLEAN bSwChnlAndSetBWInProgress;
|
||||
u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */
|
||||
u16 BasicRateSet;
|
||||
u32 ReceiveConfig;
|
||||
#ifdef CONFIG_WIFI_MONITOR
|
||||
struct mon_reg_backup mon_backup; /* used for switching back from monitor mode */
|
||||
#endif /* CONFIG_WIFI_MONITOR */
|
||||
u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */
|
||||
BOOLEAN bSwChnl;
|
||||
BOOLEAN bSetChnlBW;
|
||||
BOOLEAN bSWToBW40M;
|
||||
BOOLEAN bSWToBW80M;
|
||||
BOOLEAN bChnlBWInitialized;
|
||||
|
||||
#ifdef CONFIG_RTW_ACS
|
||||
struct auto_chan_sel acs;
|
||||
#endif
|
||||
#ifdef CONFIG_BCN_RECOVERY
|
||||
u8 issue_bcn_fail;
|
||||
#endif /*CONFIG_BCN_RECOVERY*/
|
||||
|
||||
/****** rf_ctrl *****/
|
||||
u8 rf_chip;
|
||||
|
||||
u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp */
|
||||
u8 rf_type; /*enum rf_type , is RF_PATH - GET_HAL_RFPATH*/
|
||||
u8 NumTotalRFPath; /*GET_HAL_RFPATH_NUM*/
|
||||
u8 max_tx_cnt;
|
||||
u8 tx_nss; /*tx Spatial Streams - GET_HAL_TX_NSS*/
|
||||
u8 rx_nss; /*rx Spatial Streams - GET_HAL_RX_NSS*/
|
||||
u8 txpath_cap_num_nss[4]; /* capable path num for NSS TX, [0] for 1SS, [3] for 4SS */
|
||||
|
||||
u8 PackageType;
|
||||
u8 antenna_test;
|
||||
|
||||
/* runtime TRX path setting */
|
||||
enum bb_path txpath; /* TX path bmp */
|
||||
enum bb_path rxpath; /* RX path bmp */
|
||||
enum bb_path txpath_nss[4]; /* path bmp for NSS TX, [0] for 1SS, [3] for 4SS */
|
||||
u8 txpath_num_nss[4]; /* path num for NSS TX, [0] for 1SS, [3] for 4SS */
|
||||
|
||||
/****** Debug ******/
|
||||
u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
|
||||
u8 bDumpRxPkt;
|
||||
u8 bDumpTxPkt;
|
||||
u8 dis_turboedca; /* 1: disable turboedca,
|
||||
2: disable turboedca and setting EDCA parameter based on the input parameter*/
|
||||
u32 edca_param_mode;
|
||||
|
||||
/****** EEPROM setting.******/
|
||||
u8 bautoload_fail_flag;
|
||||
u8 efuse_file_status;
|
||||
u8 macaddr_file_status;
|
||||
u8 EepromOrEfuse;
|
||||
u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/
|
||||
u8 InterfaceSel; /* board type kept in eFuse */
|
||||
u16 CustomerID;
|
||||
|
||||
u16 EEPROMVID;
|
||||
u16 EEPROMSVID;
|
||||
#ifdef CONFIG_USB_HCI
|
||||
u8 EEPROMUsbSwitch;
|
||||
u16 EEPROMPID;
|
||||
u16 EEPROMSDID;
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
u16 EEPROMDID;
|
||||
u16 EEPROMSMID;
|
||||
#endif
|
||||
|
||||
u8 EEPROMCustomerID;
|
||||
u8 EEPROMSubCustomerID;
|
||||
u8 EEPROMVersion;
|
||||
u8 EEPROMRegulatory;
|
||||
u8 eeprom_thermal_meter;
|
||||
u8 EEPROMBluetoothCoexist;
|
||||
u8 EEPROMBluetoothType;
|
||||
u8 EEPROMBluetoothAntNum;
|
||||
u8 EEPROMBluetoothAntIsolation;
|
||||
u8 EEPROMBluetoothRadioShared;
|
||||
u8 EEPROMMACAddr[ETH_ALEN];
|
||||
|
||||
u8 eeprom_trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp. 0x00:not specified */
|
||||
u8 eeprom_max_tx_cnt; /* 0: not specified */
|
||||
|
||||
u8 tx_bbswing_24G;
|
||||
u8 tx_bbswing_5G;
|
||||
u8 efuse0x3d7; /* efuse[0x3D7] */
|
||||
u8 efuse0x3d8; /* efuse[0x3D8] */
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
u8 EEPROMRFGainOffset;
|
||||
u8 EEPROMRFGainVal;
|
||||
struct kfree_data_t kfree_data;
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
#ifdef CONFIG_RTL8814A
|
||||
u32 BackUp_BB_REG_4_2nd_CCA[3];
|
||||
#endif
|
||||
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || \
|
||||
defined(CONFIG_RTL8723D) || \
|
||||
defined(CONFIG_RTL8192F)
|
||||
|
||||
u8 adjuseVoltageVal;
|
||||
u8 need_restore;
|
||||
#endif
|
||||
u8 EfuseUsedPercentage;
|
||||
u16 EfuseUsedBytes;
|
||||
/*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/
|
||||
EFUSE_HAL EfuseHal;
|
||||
|
||||
u8 txpwr_pg_mode; /* enum txpwr_pg_mode */
|
||||
|
||||
/*---------------------------------------------------------------------------------*/
|
||||
#ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
/* 2.4G TX power info for target TX power*/
|
||||
u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
|
||||
u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM];
|
||||
s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
|
||||
/* 5G TX power info for target TX power*/
|
||||
#if CONFIG_IEEE80211_BAND_5GHZ
|
||||
u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM];
|
||||
u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM];
|
||||
s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
|
||||
#endif
|
||||
#endif /* CONFIG_TXPWR_PG_WITH_PWR_IDX */
|
||||
|
||||
u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND]
|
||||
[TX_PWR_BY_RATE_NUM_RF];
|
||||
|
||||
s8 TxPwrByRate[TX_PWR_BY_RATE_NUM_BAND]
|
||||
[TX_PWR_BY_RATE_NUM_RF]
|
||||
[TX_PWR_BY_RATE_NUM_RATE];
|
||||
|
||||
/* Store the target power for each rate section and rf path */
|
||||
u8 target_txpwr_2g[TX_PWR_BY_RATE_NUM_RF]
|
||||
[NUM_OF_TARGET_TXPWR_2G];
|
||||
u8 target_txpwr_5g[TX_PWR_BY_RATE_NUM_RF]
|
||||
[NUM_OF_TARGET_TXPWR_5G];
|
||||
|
||||
bool set_entire_txpwr;
|
||||
|
||||
#if defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C) || defined(CONFIG_RTL8814B) \
|
||||
|| defined(CONFIG_RTL8723F)
|
||||
u32 txagc_set_buf;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
|
||||
u8 txpwr_idx_offload_buf[3]; /* for CCK, OFDM, HT1SS */
|
||||
struct submit_ctx txpwr_idx_offload_sctx;
|
||||
#endif
|
||||
|
||||
u8 txpwr_by_rate_loaded:1;
|
||||
u8 txpwr_by_rate_from_file:1;
|
||||
u8 txpwr_limit_loaded:1;
|
||||
u8 txpwr_limit_from_file:1;
|
||||
|
||||
/* Read/write are allow for following hardware information variables */
|
||||
u8 crystal_cap;
|
||||
|
||||
u8 PAType_2G;
|
||||
u8 PAType_5G;
|
||||
u8 LNAType_2G;
|
||||
u8 LNAType_5G;
|
||||
u8 ExternalPA_2G;
|
||||
u8 ExternalLNA_2G;
|
||||
u8 external_pa_5g;
|
||||
u8 external_lna_5g;
|
||||
u16 TypeGLNA;
|
||||
u16 TypeGPA;
|
||||
u16 TypeALNA;
|
||||
u16 TypeAPA;
|
||||
u16 rfe_type;
|
||||
|
||||
u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
|
||||
u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */
|
||||
u8 is_turbo_edca;
|
||||
u8 prv_traffic_idx;
|
||||
BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */
|
||||
|
||||
u32 RfRegChnlVal[MAX_RF_PATH];
|
||||
|
||||
/* RDG enable */
|
||||
BOOLEAN bRDGEnable;
|
||||
|
||||
#if defined (CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
|
||||
u32 RegRRSR;
|
||||
#endif
|
||||
|
||||
/****** antenna diversity ******/
|
||||
u8 AntDivCfg;
|
||||
u8 with_extenal_ant_switch;
|
||||
u8 b_fix_tx_ant;
|
||||
u8 AntDetection;
|
||||
u8 TRxAntDivType;
|
||||
u8 ant_path; /* for 8723B s0/s1 selection */
|
||||
u32 antenna_tx_path; /* Antenna path Tx */
|
||||
u32 AntennaRxPath; /* Antenna path Rx */
|
||||
u8 sw_antdiv_bl_state;
|
||||
|
||||
/******** PHY DM & DM Section **********/
|
||||
_lock IQKSpinLock;
|
||||
u8 INIDATA_RATE[MACID_NUM_SW_LIMIT];
|
||||
|
||||
struct dm_struct odmpriv;
|
||||
u64 bk_rf_ability;
|
||||
u8 bIQKInitialized;
|
||||
u8 bNeedIQK;
|
||||
u8 neediqk_24g;
|
||||
u8 IQK_MP_Switch;
|
||||
u8 bScanInProcess;
|
||||
u8 phydm_init_result; /*BB and RF para match or not*/
|
||||
/******** PHY DM & DM Section **********/
|
||||
|
||||
|
||||
|
||||
/* 2010/08/09 MH Add CU power down mode. */
|
||||
BOOLEAN pwrdown;
|
||||
|
||||
#ifdef CONFIG_P2P
|
||||
#ifdef CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
|
||||
u16 p2p_ps_offload;
|
||||
#else
|
||||
u8 p2p_ps_offload;
|
||||
#endif
|
||||
#endif
|
||||
/* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
|
||||
u8 bMacPwrCtrlOn;
|
||||
u8 hci_sus_state;
|
||||
|
||||
u8 RegIQKFWOffload;
|
||||
struct submit_ctx iqk_sctx;
|
||||
u8 ch_switch_offload;
|
||||
struct submit_ctx chsw_sctx;
|
||||
|
||||
RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
|
||||
|
||||
u8 OutEpQueueSel;
|
||||
u8 OutEpNumber;
|
||||
|
||||
#ifdef RTW_RX_AGGREGATION
|
||||
RX_AGG_MODE rxagg_mode;
|
||||
|
||||
/* For RX Aggregation DMA Mode */
|
||||
u8 rxagg_dma_size;
|
||||
u8 rxagg_dma_timeout;
|
||||
#endif /* RTW_RX_AGGREGATION */
|
||||
|
||||
bool intf_start;
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
/* */
|
||||
/* For SDIO Interface HAL related */
|
||||
/* */
|
||||
|
||||
/* */
|
||||
/* SDIO ISR Related */
|
||||
/*
|
||||
* u32 IntrMask[1];
|
||||
* u32 IntrMaskToSet[1];
|
||||
* LOG_INTERRUPT InterruptLog; */
|
||||
u32 sdio_himr;
|
||||
u32 sdio_hisr;
|
||||
#ifndef RTW_HALMAC
|
||||
/* */
|
||||
/* SDIO Tx FIFO related. */
|
||||
/* */
|
||||
/* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
|
||||
#ifdef CONFIG_RTL8192F
|
||||
u16 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
|
||||
#else
|
||||
u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
|
||||
#endif/*CONFIG_RTL8192F*/
|
||||
#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
|
||||
u8 sdio_avail_int_en_q;
|
||||
#endif
|
||||
_lock SdioTxFIFOFreePageLock;
|
||||
u8 SdioTxOQTMaxFreeSpace;
|
||||
u8 SdioTxOQTFreeSpace;
|
||||
#else /* RTW_HALMAC */
|
||||
u16 SdioTxOQTFreeSpace;
|
||||
#endif /* RTW_HALMAC */
|
||||
|
||||
/* */
|
||||
/* SDIO Rx FIFO related. */
|
||||
/* */
|
||||
u8 SdioRxFIFOCnt;
|
||||
#if defined (CONFIG_RTL8822C) || defined (CONFIG_RTL8192F)
|
||||
u32 SdioRxFIFOSize;
|
||||
#else
|
||||
u16 SdioRxFIFOSize;
|
||||
#endif
|
||||
|
||||
#ifndef RTW_HALMAC
|
||||
u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
|
||||
#else
|
||||
#ifdef CONFIG_RTL8821C
|
||||
u16 tx_high_page;
|
||||
u16 tx_low_page;
|
||||
u16 tx_normal_page;
|
||||
u16 tx_extra_page;
|
||||
u16 tx_pub_page;
|
||||
u8 max_oqt_size;
|
||||
#ifdef XMIT_BUF_SIZE
|
||||
u32 max_xmit_size_vovi;
|
||||
u32 max_xmit_size_bebk;
|
||||
#endif /*XMIT_BUF_SIZE*/
|
||||
u16 max_xmit_page;
|
||||
u16 max_xmit_page_vo;
|
||||
u16 max_xmit_page_vi;
|
||||
u16 max_xmit_page_be;
|
||||
u16 max_xmit_page_bk;
|
||||
|
||||
#endif /*#ifdef CONFIG_RTL8821C*/
|
||||
#endif /* !RTW_HALMAC */
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
|
||||
/* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
|
||||
BOOLEAN UsbRxHighSpeedMode;
|
||||
BOOLEAN UsbTxVeryHighSpeedMode;
|
||||
u32 UsbBulkOutSize;
|
||||
BOOLEAN bSupportUSB3;
|
||||
u8 usb_intf_start;
|
||||
|
||||
/* Interrupt relatd register information. */
|
||||
u32 IntArray[3];/* HISR0,HISR1,HSISR */
|
||||
u32 IntrMask[3];
|
||||
#ifdef CONFIG_USB_TX_AGGREGATION
|
||||
u8 UsbTxAggMode;
|
||||
u8 UsbTxAggDescNum;
|
||||
#endif /* CONFIG_USB_TX_AGGREGATION */
|
||||
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
u16 HwRxPageSize; /* Hardware setting */
|
||||
|
||||
/* For RX Aggregation USB Mode */
|
||||
u8 rxagg_usb_size;
|
||||
u8 rxagg_usb_timeout;
|
||||
#endif/* CONFIG_USB_RX_AGGREGATION */
|
||||
#endif /* CONFIG_USB_HCI */
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* */
|
||||
/* EEPROM setting. */
|
||||
/* */
|
||||
u32 TransmitConfig;
|
||||
u32 IntrMaskToSet[2];
|
||||
u32 IntArray[4];
|
||||
u32 IntrMask[4];
|
||||
u32 SysIntArray[1];
|
||||
u32 SysIntrMask[1];
|
||||
u32 IntrMaskReg[2];
|
||||
u32 IntrMaskDefault[4];
|
||||
|
||||
u32 pci_backdoor_ctrl;
|
||||
|
||||
u8 bDefaultAntenna;
|
||||
|
||||
u8 bInterruptMigration;
|
||||
u8 bDisableTxInt;
|
||||
|
||||
u16 RxTag;
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
struct sreset_priv srestpriv;
|
||||
#endif /* #ifdef DBG_CONFIG_ERROR_DETECT */
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
/* For bluetooth co-existance */
|
||||
BT_COEXIST bt_coexist;
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
|
||||
#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) \
|
||||
|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D)|| defined(CONFIG_RTL8192F)
|
||||
#ifndef CONFIG_PCI_HCI /* mutual exclusive with PCI -- so they're SDIO and GSPI */
|
||||
/* Interrupt relatd register information. */
|
||||
u32 SysIntrStatus;
|
||||
u32 SysIntrMask;
|
||||
#endif
|
||||
#endif /*endif CONFIG_RTL8723B */
|
||||
|
||||
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
|
||||
char para_file_buf[MAX_PARA_FILE_BUF_LEN];
|
||||
char *mac_reg;
|
||||
u32 mac_reg_len;
|
||||
char *bb_phy_reg;
|
||||
u32 bb_phy_reg_len;
|
||||
char *bb_agc_tab;
|
||||
u32 bb_agc_tab_len;
|
||||
char *bb_phy_reg_pg;
|
||||
u32 bb_phy_reg_pg_len;
|
||||
char *bb_phy_reg_mp;
|
||||
u32 bb_phy_reg_mp_len;
|
||||
char *rf_radio_a;
|
||||
u32 rf_radio_a_len;
|
||||
char *rf_radio_b;
|
||||
u32 rf_radio_b_len;
|
||||
char *rf_tx_pwr_track;
|
||||
u32 rf_tx_pwr_track_len;
|
||||
char *rf_tx_pwr_lmt;
|
||||
u32 rf_tx_pwr_lmt_len;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
|
||||
struct noise_monitor nm;
|
||||
#endif
|
||||
|
||||
struct hal_spec_t hal_spec;
|
||||
#ifdef CONFIG_PHY_CAPABILITY_QUERY
|
||||
struct phy_spec_t phy_spec;
|
||||
#endif
|
||||
u8 RfKFreeEnable;
|
||||
u8 RfKFree_ch_group;
|
||||
BOOLEAN bCCKinCH14;
|
||||
BB_INIT_REGISTER RegForRecover[5];
|
||||
|
||||
#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN)
|
||||
BOOLEAN bCorrectBCN;
|
||||
#endif
|
||||
#ifdef CONFIG_RTL8814A
|
||||
u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/
|
||||
u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/
|
||||
#endif
|
||||
struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM];
|
||||
|
||||
#ifdef RTW_HALMAC
|
||||
u16 drv_rsvd_page_number;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
u8 backup_snd_ptcl_ctrl;
|
||||
#ifdef RTW_BEAMFORMING_VERSION_2
|
||||
struct beamforming_info beamforming_info;
|
||||
#endif /* RTW_BEAMFORMING_VERSION_2 */
|
||||
#endif /* CONFIG_BEAMFORMING */
|
||||
|
||||
u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/
|
||||
u8 phydm_op_mode;
|
||||
|
||||
u8 in_cta_test;
|
||||
|
||||
#ifdef CONFIG_RTW_LED
|
||||
struct led_priv led;
|
||||
#endif
|
||||
/* for multi channel case (ex: MCC/TDLS) */
|
||||
u8 multi_ch_switch_mode;
|
||||
|
||||
#ifdef CONFIG_RTL8814B
|
||||
u8 dma_ch_map[32]; /* TXDESC qsel maximum size */
|
||||
#endif
|
||||
|
||||
} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
|
||||
|
||||
typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
|
||||
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)(((struct _ADAPTER*)__pAdapter)->HalData))
|
||||
#define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec))
|
||||
#define adapter_to_led(adapter) (&(GET_HAL_DATA(adapter)->led))
|
||||
|
||||
#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
|
||||
|
||||
#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data))
|
||||
|
||||
#define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \
|
||||
RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \
|
||||
RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo)
|
||||
|
||||
#define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr)
|
||||
#define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse)
|
||||
#define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed)
|
||||
#define rtw_set_hw_init_completed(adapter, cmp) (GET_HAL_DATA(adapter)->hw_init_completed = cmp)
|
||||
#define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE)
|
||||
|
||||
/* refer to (hal_data->version_id.RFType / registrypriv->rf_path / 8814a from efuse or registrypriv)*/
|
||||
#define GET_HAL_RFPATH(adapter) (GET_HAL_DATA(adapter)->rf_type)
|
||||
#define GET_HAL_RFPATH_NUM(adapter) (GET_HAL_DATA(adapter)->NumTotalRFPath)
|
||||
#define GET_HAL_TX_PATH_BMP(adapter) ((GET_HAL_DATA(adapter)->trx_path_bmp & 0xF0) >> 4)
|
||||
#define GET_HAL_RX_PATH_BMP(adapter) (GET_HAL_DATA(adapter)->trx_path_bmp & 0x0F)
|
||||
|
||||
/* refer to (registrypriv-> tx_nss,rx_nss / hal_spec->tx_nss_num,rx_nss_num)*/
|
||||
#define GET_HAL_TX_NSS(adapter) (GET_HAL_DATA(adapter)->tx_nss)
|
||||
#define GET_HAL_RX_NSS(adapter) (GET_HAL_DATA(adapter)->rx_nss)
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef RTW_HALMAC
|
||||
int rtw_halmac_deinit_adapter(struct dvobj_priv *);
|
||||
#endif /* RTW_HALMAC */
|
||||
|
||||
#endif /* __HAL_DATA_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_GSPI_H_
|
||||
#define __HAL_GSPI_H_
|
||||
|
||||
#define ffaddr2deviceId(pdvobj, addr) (pdvobj->Queue2Pipe[addr])
|
||||
|
||||
u8 rtw_hal_gspi_max_txoqt_free_space(_adapter *padapter);
|
||||
u8 rtw_hal_gspi_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
|
||||
void rtw_hal_gspi_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
|
||||
void rtw_hal_set_gspi_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
|
||||
u32 rtw_hal_get_gspi_tx_max_length(PADAPTER padapter, u8 queue_idx);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,713 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_IC_CFG_H__
|
||||
#define __HAL_IC_CFG_H__
|
||||
|
||||
#define RTL8188E_SUPPORT 0
|
||||
#define RTL8812A_SUPPORT 0
|
||||
#define RTL8821A_SUPPORT 0
|
||||
#define RTL8723B_SUPPORT 0
|
||||
#define RTL8723D_SUPPORT 0
|
||||
#define RTL8723F_SUPPORT 0
|
||||
#define RTL8192E_SUPPORT 0
|
||||
#define RTL8192F_SUPPORT 0
|
||||
#define RTL8814A_SUPPORT 0
|
||||
#define RTL8195A_SUPPORT 0
|
||||
#define RTL8197F_SUPPORT 0
|
||||
#define RTL8703B_SUPPORT 0
|
||||
#define RTL8188F_SUPPORT 0
|
||||
#define RTL8822B_SUPPORT 0
|
||||
#define RTL8821B_SUPPORT 0
|
||||
#define RTL8821C_SUPPORT 0
|
||||
#define RTL8710B_SUPPORT 0
|
||||
#define RTL8814B_SUPPORT 0
|
||||
#define RTL8824B_SUPPORT 0
|
||||
#define RTL8198F_SUPPORT 0
|
||||
#define RTL8195B_SUPPORT 0
|
||||
#define RTL8822C_SUPPORT 0
|
||||
#define RTL8721D_SUPPORT 0
|
||||
#define RTL8812F_SUPPORT 0
|
||||
#define RTL8197G_SUPPORT 0
|
||||
#define RTL8710C_SUPPORT 0
|
||||
|
||||
|
||||
/*#if (RTL8188E_SUPPORT==1)*/
|
||||
#define RATE_ADAPTIVE_SUPPORT 0
|
||||
#define POWER_TRAINING_ACTIVE 0
|
||||
|
||||
#ifdef CONFIG_MULTIDRV
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8188E
|
||||
#undef RTL8188E_SUPPORT
|
||||
#undef RATE_ADAPTIVE_SUPPORT
|
||||
#undef POWER_TRAINING_ACTIVE
|
||||
|
||||
#define RTL8188E_SUPPORT 1
|
||||
#define RATE_ADAPTIVE_SUPPORT 1
|
||||
#define POWER_TRAINING_ACTIVE 1
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8812A
|
||||
#undef RTL8812A_SUPPORT
|
||||
#define RTL8812A_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#define CONFIG_BEAMFORMER_FW_NDPA
|
||||
#define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/
|
||||
#define SUPPORT_MU_BF 0
|
||||
#endif /*CONFIG_BEAMFORMING*/
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8821A
|
||||
#undef RTL8821A_SUPPORT
|
||||
#define RTL8821A_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#define CONFIG_BEAMFORMER_FW_NDPA
|
||||
#define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/
|
||||
#define SUPPORT_MU_BF 0
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192E
|
||||
#undef RTL8192E_SUPPORT
|
||||
#define RTL8192E_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192F
|
||||
#undef RTL8192F_SUPPORT
|
||||
#define RTL8192F_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
/*#define CONFIG_AMPDU_PRETX_CD*/
|
||||
/*#define DBG_LA_MODE*/
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
/* #define CONFIG_NARROWBAND_SUPPORTING */
|
||||
#ifdef CONFIG_NARROWBAND_SUPPORTING
|
||||
#define CONFIG_NB_VALUE RTW_NB_CONFIG_NONE /*RTW_NB_CONFIG_WIDTH_10 or RTW_NB_CONFIG_WIDTH_5 */
|
||||
#endif
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define CONFIG_WOW_PATTERN_IN_TXFIFO
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#define CONFIG_STOP_RESUME_BCN_BY_TXPAUSE /*to fixed no bcn issue*/
|
||||
#define CONFIG_TSF_SYNC
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723B
|
||||
#undef RTL8723B_SUPPORT
|
||||
#define RTL8723B_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723D
|
||||
#undef RTL8723D_SUPPORT
|
||||
#define RTL8723D_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_CUSTOMER_STR
|
||||
#define CONFIG_RTW_CUSTOMER_STR
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8814A
|
||||
#undef RTL8814A_SUPPORT
|
||||
#define RTL8814A_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#define CONFIG_FW_CORRECT_BCN
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/
|
||||
#define SUPPORT_MU_BF 0
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8703B
|
||||
#undef RTL8703B_SUPPORT
|
||||
#define RTL8703B_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8188F
|
||||
#undef RTL8188F_SUPPORT
|
||||
#define RTL8188F_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_CUSTOMER_STR
|
||||
#define CONFIG_RTW_CUSTOMER_STR
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8188GTV
|
||||
#undef RTL8188F_SUPPORT
|
||||
#define RTL8188F_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#ifndef CONFIG_RTW_CUSTOMER_STR
|
||||
#define CONFIG_RTW_CUSTOMER_STR
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_HCI) && !defined(CONFIG_FW_OFFLOAD_SET_TXPWR_IDX)
|
||||
#define CONFIG_FW_OFFLOAD_SET_TXPWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8822B
|
||||
#undef RTL8822B_SUPPORT
|
||||
#define RTL8822B_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif /* CONFIG_FW_C2H_PKT */
|
||||
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
|
||||
#define RTW_AMPDU_AGG_RETRY_AND_NEW
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define CONFIG_GTK_OL
|
||||
/*#define CONFIG_ARP_KEEP_ALIVE*/
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
#ifndef WAKEUP_GPIO_IDX
|
||||
#define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */
|
||||
#endif /* !WAKEUP_GPIO_IDX */
|
||||
#endif /* CONFIG_GPIO_WAKEUP */
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
#define CONFIG_AP_PORT_SWAP
|
||||
#define CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
#endif /* CONFIG_CONCURRENT_MODE */
|
||||
|
||||
/*
|
||||
* Beamforming related definition
|
||||
*/
|
||||
/* Only support new beamforming mechanism */
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#define RTW_BEAMFORMING_VERSION_2
|
||||
#endif /* CONFIG_BEAMFORMING */
|
||||
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif /* CONFIG_RTW_MAC_HIDDEN_RPT */
|
||||
|
||||
#ifndef DBG_RX_DFRAME_RAW_DATA
|
||||
#define DBG_RX_DFRAME_RAW_DATA
|
||||
#endif /* DBG_RX_DFRAME_RAW_DATA */
|
||||
|
||||
#ifndef RTW_IQK_FW_OFFLOAD
|
||||
#define RTW_IQK_FW_OFFLOAD
|
||||
#endif /* RTW_IQK_FW_OFFLOAD */
|
||||
|
||||
/* Checksum offload feature */
|
||||
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
|
||||
#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
|
||||
#define CONFIG_RTW_NETIF_SG
|
||||
#endif
|
||||
#define CONFIG_TCP_CSUM_OFFLOAD_RX
|
||||
|
||||
#define CONFIG_ADVANCE_OTA
|
||||
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
#define CONFIG_MCC_MODE_V2
|
||||
#define CONFIG_MCC_PHYDM_OFFLOAD
|
||||
#endif /* CONFIG_MCC_MODE */
|
||||
|
||||
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
|
||||
#define CONFIG_TDLS_CH_SW_V2
|
||||
#endif
|
||||
|
||||
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#ifdef CONFIG_TDLS_CH_SW_V2
|
||||
#define RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#endif
|
||||
#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
|
||||
|
||||
#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
|
||||
/* Supported since fw v22.1 */
|
||||
#define RTW_PER_CMD_SUPPORT_FW
|
||||
#endif /* RTW_PER_CMD_SUPPORT_FW */
|
||||
#define CONFIG_SUPPORT_FIFO_DUMP
|
||||
#define CONFIG_HW_P0_TSF_SYNC
|
||||
#define CONFIG_BCN_RECV_TIME
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifdef CONFIG_LPS
|
||||
#define CONFIG_LPS_ACK /* Supported after FW v30 & v27.9 */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif /* CONFIG_RTL8822B */
|
||||
|
||||
#ifdef CONFIG_RTL8822C
|
||||
#undef RTL8822C_SUPPORT
|
||||
#define RTL8822C_SUPPORT 1
|
||||
/*#define DBG_LA_MODE*/
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif /* CONFIG_FW_C2H_PKT */
|
||||
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define CONFIG_GTK_OL
|
||||
/*#define CONFIG_ARP_KEEP_ALIVE*/
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
#ifndef WAKEUP_GPIO_IDX
|
||||
#define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */
|
||||
#endif /* !WAKEUP_GPIO_IDX */
|
||||
#endif /* CONFIG_GPIO_WAKEUP */
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
#define CONFIG_AP_PORT_SWAP
|
||||
#define CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
#endif /* CONFIG_CONCURRENT_MODE */
|
||||
|
||||
/*
|
||||
* Beamforming related definition
|
||||
*/
|
||||
/* Only support new beamforming mechanism */
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#define RTW_BEAMFORMING_VERSION_2
|
||||
#endif /* CONFIG_BEAMFORMING */
|
||||
|
||||
#ifdef CONFIG_NO_FW
|
||||
#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#undef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#else
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef DBG_RX_DFRAME_RAW_DATA
|
||||
#define DBG_RX_DFRAME_RAW_DATA
|
||||
#endif /* DBG_RX_DFRAME_RAW_DATA */
|
||||
|
||||
#ifndef RTW_IQK_FW_OFFLOAD
|
||||
/* #define RTW_IQK_FW_OFFLOAD */
|
||||
#endif /* RTW_IQK_FW_OFFLOAD */
|
||||
#define CONFIG_ADVANCE_OTA
|
||||
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
#define CONFIG_MCC_MODE_V2
|
||||
#define CONFIG_MCC_PHYDM_OFFLOAD
|
||||
#endif /* CONFIG_MCC_MODE */
|
||||
|
||||
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
|
||||
#define CONFIG_TDLS_CH_SW_V2
|
||||
#endif
|
||||
|
||||
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#ifdef CONFIG_TDLS_CH_SW_V2
|
||||
#define RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#endif
|
||||
#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
|
||||
|
||||
#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
|
||||
/* Supported since fw v22.1 */
|
||||
#define RTW_PER_CMD_SUPPORT_FW
|
||||
#endif /* RTW_PER_CMD_SUPPORT_FW */
|
||||
#define CONFIG_SUPPORT_FIFO_DUMP
|
||||
#define CONFIG_HW_P0_TSF_SYNC
|
||||
#define CONFIG_BCN_RECV_TIME
|
||||
|
||||
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
|
||||
#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
|
||||
#define CONFIG_RTW_NETIF_SG
|
||||
#endif
|
||||
#define CONFIG_TCP_CSUM_OFFLOAD_RX
|
||||
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifdef CONFIG_LPS
|
||||
#define CONFIG_LPS_ACK /* Supported after FW v07 */
|
||||
#define CONFIG_LPS_1T1R /* Supported after FW v07 */
|
||||
#endif
|
||||
|
||||
#define CONFIG_BT_EFUSE_MASK
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
|
||||
#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
|
||||
#endif
|
||||
|
||||
#define CONFIG_RTL8822C_XCAP_NEW_POLICY
|
||||
|
||||
#define CONFIG_SUPPORT_DYNAMIC_TXPWR
|
||||
#endif /* CONFIG_RTL8822C */
|
||||
|
||||
#ifdef CONFIG_RTL8821C
|
||||
#undef RTL8821C_SUPPORT
|
||||
#define RTL8821C_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#ifdef CONFIG_NO_FW
|
||||
#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#undef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#else
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#endif
|
||||
#define LOAD_FW_HEADER_FROM_DRIVER
|
||||
#define CONFIG_PHY_CAPABILITY_QUERY
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
#define CONFIG_AP_PORT_SWAP
|
||||
#define CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
#endif
|
||||
#define CONFIG_SUPPORT_FIFO_DUMP
|
||||
#ifndef RTW_IQK_FW_OFFLOAD
|
||||
#define RTW_IQK_FW_OFFLOAD
|
||||
#endif /* RTW_IQK_FW_OFFLOAD */
|
||||
/*#define CONFIG_AMPDU_PRETX_CD*/
|
||||
/*#define DBG_PRE_TX_HANG*/
|
||||
|
||||
/* Beamforming related definition */
|
||||
/* Only support new beamforming mechanism */
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#define RTW_BEAMFORMING_VERSION_2
|
||||
#endif /* CONFIG_BEAMFORMING */
|
||||
#define CONFIG_HW_P0_TSF_SYNC
|
||||
#define CONFIG_BCN_RECV_TIME
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifdef CONFIG_LPS
|
||||
/* #define CONFIG_LPS_ACK */ /* Supported after FW v25 */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
|
||||
#define CONFIG_BT_EFUSE_MASK
|
||||
#endif /*CONFIG_RTL8821C*/
|
||||
|
||||
#ifdef CONFIG_RTL8710B
|
||||
#undef RTL8710B_SUPPORT
|
||||
#define RTL8710B_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8814B
|
||||
#undef RTL8814B_SUPPORT
|
||||
#define RTL8814B_SUPPORT 1
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif /* CONFIG_FW_C2H_PKT */
|
||||
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
|
||||
#define RTW_AMPDU_AGG_RETRY_AND_NEW
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define CONFIG_GTK_OL
|
||||
/*#define CONFIG_ARP_KEEP_ALIVE*/
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
#ifndef WAKEUP_GPIO_IDX
|
||||
#define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */
|
||||
#endif /* !WAKEUP_GPIO_IDX */
|
||||
#endif /* CONFIG_GPIO_WAKEUP */
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
/*#define CONFIG_AP_PORT_SWAP*/
|
||||
#define CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
#endif /* CONFIG_CONCURRENT_MODE */
|
||||
|
||||
/*
|
||||
* Beamforming related definition
|
||||
*/
|
||||
/* Only support new beamforming mechanism */
|
||||
#ifdef CONFIG_BEAMFORMING
|
||||
#define RTW_BEAMFORMING_VERSION_2
|
||||
#endif /* CONFIG_BEAMFORMING */
|
||||
|
||||
#ifndef DBG_RX_DFRAME_RAW_DATA
|
||||
#define DBG_RX_DFRAME_RAW_DATA
|
||||
#endif /* DBG_RX_DFRAME_RAW_DATA */
|
||||
|
||||
#ifndef RTW_IQK_FW_OFFLOAD
|
||||
#define RTW_IQK_FW_OFFLOAD
|
||||
#endif /* RTW_IQK_FW_OFFLOAD */
|
||||
|
||||
/* Checksum offload feature */
|
||||
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */
|
||||
#define CONFIG_TCP_CSUM_OFFLOAD_RX
|
||||
|
||||
#define CONFIG_ADVANCE_OTA
|
||||
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
#define CONFIG_MCC_MODE_V2
|
||||
#define CONFIG_MCC_PHYDM_OFFLOAD
|
||||
#endif /* CONFIG_MCC_MODE */
|
||||
|
||||
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
|
||||
#define CONFIG_TDLS_CH_SW_V2
|
||||
#endif
|
||||
|
||||
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#ifdef CONFIG_TDLS_CH_SW_V2
|
||||
#define RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#endif
|
||||
#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
|
||||
|
||||
#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
|
||||
/* Supported since fw v22.1 */
|
||||
#define RTW_PER_CMD_SUPPORT_FW
|
||||
#endif /* RTW_PER_CMD_SUPPORT_FW */
|
||||
#define CONFIG_SUPPORT_FIFO_DUMP
|
||||
#define CONFIG_HW_P0_TSF_SYNC
|
||||
#define CONFIG_BCN_RECV_TIME
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
|
||||
#endif
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#define CONFIG_PROTSEL_PORT
|
||||
#define CONFIG_PROTSEL_ATIMDTIM
|
||||
#define CONFIG_PROTSEL_MACSLEEP
|
||||
|
||||
#define CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR
|
||||
#define CONFIG_HAS_HW_VAR_BCN_FUNC
|
||||
#define CONFIG_HAS_HW_VAR_MLME_DISCONNECT
|
||||
#define CONFIG_HAS_HW_VAR_MLME_JOIN
|
||||
#define CONFIG_HAS_HW_VAR_CORRECT_TSF
|
||||
#define CONFIG_HAS_TX_BEACON_PAUSE
|
||||
|
||||
#define CONFIG_RTW_TX_NPATH_EN /* 8814B is always 4TX */
|
||||
|
||||
#ifdef CONFIG_LPS
|
||||
#define CONFIG_LPS_ACK /* Supported after FW v04 */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
|
||||
#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
|
||||
#endif
|
||||
#endif /* CONFIG_RTL8814B */
|
||||
#ifdef CONFIG_RTL8723F
|
||||
#undef RTL8723F_SUPPORT
|
||||
#define RTL8723F_SUPPORT 1
|
||||
|
||||
/* Use HALMAC architecture, necessary for 8723F */
|
||||
#define RTW_HALMAC
|
||||
|
||||
/*#define DBG_LA_MODE*/
|
||||
|
||||
#ifndef CONFIG_FW_C2H_PKT
|
||||
#define CONFIG_FW_C2H_PKT
|
||||
#endif /* CONFIG_FW_C2H_PKT */
|
||||
|
||||
#define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define CONFIG_WOW_PATTERN_IN_TXFIFO
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define CONFIG_GTK_OL
|
||||
/*#define CONFIG_ARP_KEEP_ALIVE*/
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
#ifndef WAKEUP_GPIO_IDX
|
||||
#define WAKEUP_GPIO_IDX 12 /* WIFI Chip Side */
|
||||
#endif /* !WAKEUP_GPIO_IDX */
|
||||
#endif /* CONFIG_GPIO_WAKEUP */
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
#define CONFIG_AP_PORT_SWAP
|
||||
#define CONFIG_FW_MULTI_PORT_SUPPORT
|
||||
#endif /* CONFIG_CONCURRENT_MODE */
|
||||
|
||||
#ifdef CONFIG_NO_FW
|
||||
#ifdef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#undef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#else
|
||||
#ifndef CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#define CONFIG_RTW_MAC_HIDDEN_RPT
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef DBG_RX_DFRAME_RAW_DATA
|
||||
#define DBG_RX_DFRAME_RAW_DATA
|
||||
#endif /* DBG_RX_DFRAME_RAW_DATA */
|
||||
|
||||
/*#define RTW_IQK_FW_OFFLOAD*/
|
||||
#define CONFIG_ADVANCE_OTA
|
||||
|
||||
#ifdef CONFIG_MCC_MODE
|
||||
#define CONFIG_MCC_MODE_V2
|
||||
#define CONFIG_MCC_PHYDM_OFFLOAD
|
||||
#endif /* CONFIG_MCC_MODE */
|
||||
|
||||
#if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)
|
||||
#define CONFIG_TDLS_CH_SW_V2
|
||||
#endif
|
||||
|
||||
#ifndef RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#ifdef CONFIG_TDLS_CH_SW_V2
|
||||
#define RTW_CHANNEL_SWITCH_OFFLOAD
|
||||
#endif
|
||||
#endif /* RTW_CHANNEL_SWITCH_OFFLOAD */
|
||||
|
||||
#if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW)
|
||||
/* Supported since fw v22.1 */
|
||||
#define RTW_PER_CMD_SUPPORT_FW
|
||||
#endif /* RTW_PER_CMD_SUPPORT_FW */
|
||||
#define CONFIG_SUPPORT_FIFO_DUMP
|
||||
#define CONFIG_HW_P0_TSF_SYNC
|
||||
#define CONFIG_BCN_RECV_TIME
|
||||
|
||||
/*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/
|
||||
#if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG)
|
||||
#define CONFIG_RTW_NETIF_SG
|
||||
#endif
|
||||
#define CONFIG_TCP_CSUM_OFFLOAD_RX
|
||||
|
||||
#ifdef CONFIG_P2P_PS
|
||||
#define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP
|
||||
#endif
|
||||
|
||||
#define CONFIG_RTS_FULL_BW
|
||||
|
||||
#ifdef CONFIG_LPS
|
||||
#define CONFIG_LPS_ACK
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#define CONFIG_TXPWR_PG_WITH_PWR_IDX
|
||||
#endif
|
||||
#ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
|
||||
#define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
|
||||
#endif
|
||||
|
||||
#define CONFIG_BT_EFUSE_MASK
|
||||
|
||||
#define CONFIG_WRITE_BCN_LEN_TO_FW
|
||||
#endif /* CONFIG_RTL8723F */
|
||||
#endif /*__HAL_IC_CFG_H__*/
|
||||
|
|
@ -0,0 +1,912 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_INTF_H__
|
||||
#define __HAL_INTF_H__
|
||||
|
||||
|
||||
enum RTL871X_HCI_TYPE {
|
||||
RTW_PCIE = BIT0,
|
||||
RTW_USB = BIT1,
|
||||
RTW_SDIO = BIT2,
|
||||
RTW_GSPI = BIT3,
|
||||
};
|
||||
|
||||
enum _CHIP_TYPE {
|
||||
|
||||
NULL_CHIP_TYPE,
|
||||
RTL8188E,
|
||||
RTL8192E,
|
||||
RTL8812,
|
||||
RTL8821, /* RTL8811 */
|
||||
RTL8723B,
|
||||
RTL8814A,
|
||||
RTL8703B,
|
||||
RTL8188F,
|
||||
RTL8188GTV,
|
||||
RTL8822B,
|
||||
RTL8723D,
|
||||
RTL8821C,
|
||||
RTL8710B,
|
||||
RTL8192F,
|
||||
RTL8822C,
|
||||
RTL8814B,
|
||||
RTL8723F,
|
||||
MAX_CHIP_TYPE
|
||||
};
|
||||
|
||||
#ifdef RTW_HALMAC
|
||||
enum fw_mem {
|
||||
FW_EMEM,
|
||||
FW_IMEM,
|
||||
FW_DMEM,
|
||||
};
|
||||
#endif
|
||||
|
||||
extern const u32 _chip_type_to_odm_ic_type[];
|
||||
#define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)])
|
||||
|
||||
typedef enum _HAL_HW_TIMER_TYPE {
|
||||
HAL_TIMER_NONE = 0,
|
||||
HAL_TIMER_TXBF = 1,
|
||||
HAL_TIMER_EARLYMODE = 2,
|
||||
} HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE;
|
||||
|
||||
|
||||
typedef enum _HW_VARIABLES {
|
||||
HW_VAR_MEDIA_STATUS,
|
||||
HW_VAR_SET_OPMODE,
|
||||
HW_VAR_MAC_ADDR,
|
||||
HW_VAR_BSSID,
|
||||
HW_VAR_INIT_RTS_RATE,
|
||||
HW_VAR_BASIC_RATE,
|
||||
HW_VAR_TXPAUSE,
|
||||
HW_VAR_BCN_FUNC,
|
||||
HW_VAR_BCN_CTRL_ADDR,
|
||||
HW_VAR_CORRECT_TSF,
|
||||
HW_VAR_RCR,
|
||||
HW_VAR_MLME_DISCONNECT,
|
||||
HW_VAR_MLME_SITESURVEY,
|
||||
HW_VAR_MLME_JOIN,
|
||||
HW_VAR_ON_RCR_AM,
|
||||
HW_VAR_OFF_RCR_AM,
|
||||
HW_VAR_BEACON_INTERVAL,
|
||||
HW_VAR_SLOT_TIME,
|
||||
HW_VAR_RESP_SIFS,
|
||||
HW_VAR_ACK_PREAMBLE,
|
||||
HW_VAR_SEC_CFG,
|
||||
HW_VAR_SEC_DK_CFG,
|
||||
HW_VAR_BCN_VALID,
|
||||
HW_VAR_FREECNT,
|
||||
|
||||
/* PHYDM odm->SupportAbility */
|
||||
HW_VAR_CAM_EMPTY_ENTRY,
|
||||
HW_VAR_CAM_INVALID_ALL,
|
||||
HW_VAR_AC_PARAM_VO,
|
||||
HW_VAR_AC_PARAM_VI,
|
||||
HW_VAR_AC_PARAM_BE,
|
||||
HW_VAR_AC_PARAM_BK,
|
||||
HW_VAR_ACM_CTRL,
|
||||
#ifdef CONFIG_WMMPS_STA
|
||||
HW_VAR_UAPSD_TID,
|
||||
#endif /* CONFIG_WMMPS_STA */
|
||||
HW_VAR_AMPDU_MIN_SPACE,
|
||||
#ifdef CONFIG_80211N_HT
|
||||
HW_VAR_AMPDU_FACTOR,
|
||||
#endif /* CONFIG_80211N_HT */
|
||||
HW_VAR_RXDMA_AGG_PG_TH,
|
||||
HW_VAR_SET_RPWM,
|
||||
HW_VAR_CPWM,
|
||||
HW_VAR_H2C_FW_PWRMODE,
|
||||
HW_VAR_H2C_FW_PWRMODE_RFON_CTRL,
|
||||
HW_VAR_H2C_INACTIVE_IPS,
|
||||
HW_VAR_H2C_PS_TUNE_PARAM,
|
||||
HW_VAR_H2C_FW_JOINBSSRPT,
|
||||
HW_VAR_FWLPS_RF_ON,
|
||||
HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
|
||||
#ifdef CONFIG_LPS_POFF
|
||||
HW_VAR_LPS_POFF_INIT,
|
||||
HW_VAR_LPS_POFF_DEINIT,
|
||||
HW_VAR_LPS_POFF_SET_MODE,
|
||||
HW_VAR_LPS_POFF_WOW_EN,
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_PG
|
||||
HW_VAR_LPS_PG_HANDLE,
|
||||
#endif
|
||||
HW_VAR_TRIGGER_GPIO_0,
|
||||
HW_VAR_BT_SET_COEXIST,
|
||||
HW_VAR_BT_ISSUE_DELBA,
|
||||
HW_VAR_SWITCH_EPHY_WoWLAN,
|
||||
HW_VAR_EFUSE_USAGE,
|
||||
HW_VAR_EFUSE_BYTES,
|
||||
HW_VAR_EFUSE_BT_USAGE,
|
||||
HW_VAR_EFUSE_BT_BYTES,
|
||||
HW_VAR_FIFO_CLEARN_UP,
|
||||
HW_VAR_RESTORE_HW_SEQ,
|
||||
HW_VAR_CHECK_TXBUF,
|
||||
HW_VAR_PCIE_STOP_TX_DMA,
|
||||
HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
|
||||
HW_VAR_HCI_SUS_STATE,
|
||||
/* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
|
||||
/* Unit in microsecond. 0 means disable this function. */
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
HW_VAR_WOWLAN,
|
||||
HW_VAR_WAKEUP_REASON,
|
||||
#endif
|
||||
HW_VAR_RPWM_TOG,
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
HW_VAR_WOW_OUTPUT_GPIO,
|
||||
HW_VAR_WOW_INPUT_GPIO,
|
||||
HW_SET_GPIO_WL_CTRL,
|
||||
#endif
|
||||
HW_VAR_SYS_CLKR,
|
||||
HW_VAR_NAV_UPPER,
|
||||
HW_VAR_RPT_TIMER_SETTING,
|
||||
HW_VAR_TX_RPT_MAX_MACID,
|
||||
HW_VAR_CHK_HI_QUEUE_EMPTY,
|
||||
HW_VAR_CHK_MGQ_CPU_EMPTY,
|
||||
HW_VAR_DL_BCN_SEL,
|
||||
HW_VAR_AMPDU_MAX_TIME,
|
||||
HW_VAR_WIRELESS_MODE,
|
||||
HW_VAR_USB_MODE,
|
||||
HW_VAR_PORT_SWITCH,
|
||||
HW_VAR_PORT_CFG,
|
||||
HW_VAR_DO_IQK,
|
||||
HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/
|
||||
HW_VAR_SET_REQ_FW_PS,
|
||||
HW_VAR_FW_PS_STATE,
|
||||
HW_VAR_SOUNDING_ENTER,
|
||||
HW_VAR_SOUNDING_LEAVE,
|
||||
HW_VAR_SOUNDING_RATE,
|
||||
HW_VAR_SOUNDING_STATUS,
|
||||
HW_VAR_SOUNDING_FW_NDPA,
|
||||
HW_VAR_SOUNDING_CLK,
|
||||
HW_VAR_SOUNDING_SET_GID_TABLE,
|
||||
HW_VAR_SOUNDING_CSI_REPORT,
|
||||
/*Add by YuChen for TXBF HW timer*/
|
||||
HW_VAR_HW_REG_TIMER_INIT,
|
||||
HW_VAR_HW_REG_TIMER_RESTART,
|
||||
HW_VAR_HW_REG_TIMER_START,
|
||||
HW_VAR_HW_REG_TIMER_STOP,
|
||||
/*Add by YuChen for TXBF HW timer*/
|
||||
HW_VAR_DL_RSVD_PAGE,
|
||||
HW_VAR_MACID_LINK,
|
||||
HW_VAR_MACID_NOLINK,
|
||||
HW_VAR_DUMP_MAC_QUEUE_INFO,
|
||||
HW_VAR_ASIX_IOT,
|
||||
#ifdef CONFIG_MBSSID_CAM
|
||||
HW_VAR_MBSSID_CAM_WRITE,
|
||||
HW_VAR_MBSSID_CAM_CLEAR,
|
||||
HW_VAR_RCR_MBSSID_EN,
|
||||
#endif
|
||||
HW_VAR_EN_HW_UPDATE_TSF,
|
||||
HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,
|
||||
HW_VAR_CH_SW_IQK_INFO_BACKUP,
|
||||
HW_VAR_CH_SW_IQK_INFO_RESTORE,
|
||||
|
||||
HW_VAR_DBI,
|
||||
HW_VAR_MDIO,
|
||||
HW_VAR_L1OFF_CAPABILITY,
|
||||
HW_VAR_L1OFF_NIC_SUPPORT,
|
||||
HW_VAR_BCN_EARLY_C2H_RPT,
|
||||
HW_VAR_SET_DRV_ERLY_INT,
|
||||
HW_VAR_DUMP_MAC_TXFIFO,
|
||||
HW_VAR_PWR_CMD,
|
||||
#ifdef CONFIG_FW_HANDLE_TXBCN
|
||||
HW_VAR_BCN_HEAD_SEL,
|
||||
#endif
|
||||
HW_VAR_SET_SOML_PARAM,
|
||||
HW_VAR_ENABLE_RX_BAR,
|
||||
HW_VAR_TSF_AUTO_SYNC,
|
||||
HW_VAR_LPS_STATE_CHK,
|
||||
HW_VAR_LPS_RFON_CHK,
|
||||
#ifdef CONFIG_RTS_FULL_BW
|
||||
HW_VAR_SET_RTS_BW,
|
||||
#endif
|
||||
#if defined(CONFIG_PCI_HCI)
|
||||
HW_VAR_ENSWBCN,
|
||||
#endif
|
||||
#ifdef CONFIG_WOWLAN
|
||||
HW_VAR_VENDOR_WOW_MODE,
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
} HW_VARIABLES;
|
||||
|
||||
typedef enum _HAL_DEF_VARIABLE {
|
||||
HAL_DEF_UNDERCORATEDSMOOTHEDPWDB,
|
||||
HAL_DEF_IS_SUPPORT_ANT_DIV,
|
||||
HAL_DEF_DRVINFO_SZ,
|
||||
HAL_DEF_MAX_RECVBUF_SZ,
|
||||
HAL_DEF_RX_PACKET_OFFSET,
|
||||
HAL_DEF_RX_DMA_SZ_WOW,
|
||||
HAL_DEF_RX_DMA_SZ,
|
||||
HAL_DEF_RX_PAGE_SIZE,
|
||||
HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
|
||||
HAL_DEF_RA_DECISION_RATE,
|
||||
HAL_DEF_RA_SGI,
|
||||
HAL_DEF_PT_PWR_STATUS,
|
||||
HAL_DEF_TX_LDPC, /* LDPC support */
|
||||
HAL_DEF_RX_LDPC, /* LDPC support */
|
||||
HAL_DEF_TX_STBC, /* TX STBC support */
|
||||
HAL_DEF_RX_STBC, /* RX STBC support */
|
||||
HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit Compressed Steering Capable */
|
||||
HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */
|
||||
HAL_DEF_VHT_MU_BEAMFORMER, /* VHT MU Beamformer support */
|
||||
HAL_DEF_VHT_MU_BEAMFORMEE, /* VHT MU Beamformee support */
|
||||
HAL_DEF_BEAMFORMER_CAP,
|
||||
HAL_DEF_BEAMFORMEE_CAP,
|
||||
HW_VAR_MAX_RX_AMPDU_FACTOR,
|
||||
HW_DEF_RA_INFO_DUMP,
|
||||
HAL_DEF_DBG_DUMP_TXPKT,
|
||||
|
||||
HAL_DEF_TX_PAGE_SIZE,
|
||||
HAL_DEF_TX_PAGE_BOUNDARY,
|
||||
HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN,
|
||||
HAL_DEF_TX_BUFFER_LAST_ENTRY,
|
||||
HAL_DEF_ANT_DETECT,/* to do for 8723a */
|
||||
HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */
|
||||
HAL_DEF_EFUSE_USAGE, /* Get current EFUSE utilization. 2008.12.19. Added by Roger. */
|
||||
HAL_DEF_EFUSE_BYTES,
|
||||
HW_VAR_BEST_AMPDU_DENSITY,
|
||||
} HAL_DEF_VARIABLE;
|
||||
|
||||
typedef enum _HAL_ODM_VARIABLE {
|
||||
HAL_ODM_STA_INFO,
|
||||
HAL_ODM_P2P_STATE,
|
||||
HAL_ODM_WIFI_DISPLAY_STATE,
|
||||
HAL_ODM_REGULATION,
|
||||
HAL_ODM_INITIAL_GAIN,
|
||||
HAL_ODM_RX_INFO_DUMP,
|
||||
HAL_ODM_RX_Dframe_INFO,
|
||||
#ifdef CONFIG_ANTENNA_DIVERSITY
|
||||
HAL_ODM_ANTDIV_SELECT
|
||||
#endif
|
||||
} HAL_ODM_VARIABLE;
|
||||
|
||||
typedef enum _HAL_INTF_PS_FUNC {
|
||||
HAL_USB_SELECT_SUSPEND,
|
||||
HAL_MAX_ID,
|
||||
} HAL_INTF_PS_FUNC;
|
||||
|
||||
typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
|
||||
|
||||
struct txpwr_idx_comp;
|
||||
|
||||
struct hal_ops {
|
||||
/*** initialize section ***/
|
||||
void (*read_chip_version)(_adapter *padapter);
|
||||
void (*init_default_value)(_adapter *padapter);
|
||||
void (*intf_chip_configure)(_adapter *padapter);
|
||||
u8 (*read_adapter_info)(_adapter *padapter);
|
||||
u32(*hal_power_on)(_adapter *padapter);
|
||||
void (*hal_power_off)(_adapter *padapter);
|
||||
u32(*hal_init)(_adapter *padapter);
|
||||
u32(*hal_deinit)(_adapter *padapter);
|
||||
void (*dm_init)(_adapter *padapter);
|
||||
void (*dm_deinit)(_adapter *padapter);
|
||||
|
||||
/*** xmit section ***/
|
||||
s32(*init_xmit_priv)(_adapter *padapter);
|
||||
void (*free_xmit_priv)(_adapter *padapter);
|
||||
s32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
/*
|
||||
* mgnt_xmit should be implemented to run in interrupt context
|
||||
*/
|
||||
s32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32(*hal_mgmt_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#if defined (CONFIG_CONCURRENT_MODE) && defined (CONFIG_TSF_SYNC)
|
||||
void(*tsf_sync)(_adapter *Adapter);
|
||||
#endif
|
||||
#ifdef CONFIG_XMIT_THREAD_MODE
|
||||
s32(*xmit_thread_handler)(_adapter *padapter);
|
||||
#endif
|
||||
void (*run_thread)(_adapter *padapter);
|
||||
void (*cancel_thread)(_adapter *padapter);
|
||||
|
||||
/*** recv section ***/
|
||||
s32(*init_recv_priv)(_adapter *padapter);
|
||||
void (*free_recv_priv)(_adapter *padapter);
|
||||
#ifdef CONFIG_RECV_THREAD_MODE
|
||||
s32 (*recv_hdl)(_adapter *adapter);
|
||||
#endif
|
||||
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
|
||||
u32(*inirp_init)(_adapter *padapter);
|
||||
u32(*inirp_deinit)(_adapter *padapter);
|
||||
#endif
|
||||
/*** interrupt hdl section ***/
|
||||
void (*enable_interrupt)(_adapter *padapter);
|
||||
void (*disable_interrupt)(_adapter *padapter);
|
||||
u8(*check_ips_status)(_adapter *padapter);
|
||||
#if defined(CONFIG_PCI_HCI)
|
||||
s32(*interrupt_handler)(_adapter *padapter);
|
||||
void (*unmap_beacon_icf)(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
|
||||
void (*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_HCI)
|
||||
void (*irp_reset)(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
/*** DM section ***/
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
void (*InitSwLeds)(_adapter *padapter);
|
||||
void (*DeInitSwLeds)(_adapter *padapter);
|
||||
#endif
|
||||
void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
|
||||
|
||||
void (*set_tx_power_level_handler)(_adapter *adapter, u8 channel);
|
||||
void (*set_txpwr_done)(_adapter *adapter);
|
||||
void (*set_tx_power_index_handler)(_adapter *adapter, u32 powerindex, enum rf_path rfpath, u8 rate);
|
||||
|
||||
u8 (*get_tx_power_index_handler)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate
|
||||
, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic);
|
||||
s8 (*get_txpwr_target_extra_bias)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
|
||||
|
||||
void (*hal_dm_watchdog)(_adapter *padapter);
|
||||
|
||||
u8 (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val);
|
||||
|
||||
void (*GetHwRegHandler)(_adapter *padapter, u8 variable, u8 *val);
|
||||
|
||||
|
||||
|
||||
u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
|
||||
|
||||
u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
|
||||
|
||||
void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
|
||||
void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
|
||||
|
||||
void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter);
|
||||
|
||||
u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
|
||||
|
||||
u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
|
||||
void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
|
||||
void (*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
#ifdef CONFIG_SYSON_INDIRECT_ACCESS
|
||||
u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask);
|
||||
void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
#endif
|
||||
void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params);
|
||||
|
||||
#ifdef CONFIG_HOSTAPD_MLME
|
||||
s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt);
|
||||
#endif
|
||||
|
||||
void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
|
||||
void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState);
|
||||
void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest);
|
||||
void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest);
|
||||
u16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest);
|
||||
int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest);
|
||||
int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
|
||||
u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
|
||||
BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest);
|
||||
#if defined(CONFIG_RTL8710B)
|
||||
BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value);
|
||||
#endif
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
void (*sreset_init_value)(_adapter *padapter);
|
||||
void (*sreset_reset_value)(_adapter *padapter);
|
||||
void (*silentreset)(_adapter *padapter);
|
||||
void (*sreset_xmit_status_check)(_adapter *padapter);
|
||||
void (*sreset_linked_status_check)(_adapter *padapter);
|
||||
u8(*sreset_get_wifi_status)(_adapter *padapter);
|
||||
bool (*sreset_inprogress)(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IOL
|
||||
int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
|
||||
#endif
|
||||
|
||||
void (*hal_notch_filter)(_adapter *adapter, bool enable);
|
||||
#ifdef RTW_HALMAC
|
||||
void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length);
|
||||
#else
|
||||
s32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
|
||||
#endif
|
||||
void (*reqtxrpt)(_adapter *padapter, u8 macid);
|
||||
s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen,
|
||||
u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
s32(*fw_dl)(_adapter *adapter, u8 wowlan);
|
||||
#ifdef RTW_HALMAC
|
||||
s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)
|
||||
void (*clear_interrupt)(_adapter *padapter);
|
||||
#endif
|
||||
u8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan);
|
||||
#ifdef CONFIG_GPIO_API
|
||||
void (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag);
|
||||
int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num);
|
||||
void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num);
|
||||
#endif
|
||||
#ifdef CONFIG_FW_CORRECT_BCN
|
||||
void (*fw_correct_bcn)(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef RTW_HALMAC
|
||||
u8(*init_mac_register)(PADAPTER);
|
||||
u8(*init_phy)(PADAPTER);
|
||||
#endif /* RTW_HALMAC */
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RFKILL_POLL
|
||||
bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_TX_POLLING
|
||||
void (*tx_poll_handler)(_adapter *adapter);
|
||||
#endif
|
||||
};
|
||||
|
||||
typedef enum _RT_EEPROM_TYPE {
|
||||
EEPROM_93C46,
|
||||
EEPROM_93C56,
|
||||
EEPROM_BOOT_EFUSE,
|
||||
} RT_EEPROM_TYPE, *PRT_EEPROM_TYPE;
|
||||
|
||||
|
||||
|
||||
#define RF_CHANGE_BY_INIT 0
|
||||
#define RF_CHANGE_BY_IPS BIT28
|
||||
#define RF_CHANGE_BY_PS BIT29
|
||||
#define RF_CHANGE_BY_HW BIT30
|
||||
#define RF_CHANGE_BY_SW BIT31
|
||||
|
||||
typedef enum _HARDWARE_TYPE {
|
||||
HARDWARE_TYPE_RTL8188EE,
|
||||
HARDWARE_TYPE_RTL8188EU,
|
||||
HARDWARE_TYPE_RTL8188ES,
|
||||
/* NEW_GENERATION_IC */
|
||||
HARDWARE_TYPE_RTL8192EE,
|
||||
HARDWARE_TYPE_RTL8192EU,
|
||||
HARDWARE_TYPE_RTL8192ES,
|
||||
HARDWARE_TYPE_RTL8812E,
|
||||
HARDWARE_TYPE_RTL8812AU,
|
||||
HARDWARE_TYPE_RTL8811AU,
|
||||
HARDWARE_TYPE_RTL8821E,
|
||||
HARDWARE_TYPE_RTL8821U,
|
||||
HARDWARE_TYPE_RTL8821S,
|
||||
HARDWARE_TYPE_RTL8723BE,
|
||||
HARDWARE_TYPE_RTL8723BU,
|
||||
HARDWARE_TYPE_RTL8723BS,
|
||||
HARDWARE_TYPE_RTL8814AE,
|
||||
HARDWARE_TYPE_RTL8814AU,
|
||||
HARDWARE_TYPE_RTL8814AS,
|
||||
HARDWARE_TYPE_RTL8821BE,
|
||||
HARDWARE_TYPE_RTL8821BU,
|
||||
HARDWARE_TYPE_RTL8821BS,
|
||||
HARDWARE_TYPE_RTL8822BE,
|
||||
HARDWARE_TYPE_RTL8822BU,
|
||||
HARDWARE_TYPE_RTL8822BS,
|
||||
HARDWARE_TYPE_RTL8703BE,
|
||||
HARDWARE_TYPE_RTL8703BU,
|
||||
HARDWARE_TYPE_RTL8703BS,
|
||||
HARDWARE_TYPE_RTL8188FE,
|
||||
HARDWARE_TYPE_RTL8188FU,
|
||||
HARDWARE_TYPE_RTL8188FS,
|
||||
HARDWARE_TYPE_RTL8188GTVU,
|
||||
HARDWARE_TYPE_RTL8188GTVS,
|
||||
HARDWARE_TYPE_RTL8723DE,
|
||||
HARDWARE_TYPE_RTL8723DU,
|
||||
HARDWARE_TYPE_RTL8723DS,
|
||||
HARDWARE_TYPE_RTL8821CE,
|
||||
HARDWARE_TYPE_RTL8821CU,
|
||||
HARDWARE_TYPE_RTL8821CS,
|
||||
HARDWARE_TYPE_RTL8710BU,
|
||||
HARDWARE_TYPE_RTL8192FS,
|
||||
HARDWARE_TYPE_RTL8192FU,
|
||||
HARDWARE_TYPE_RTL8192FE,
|
||||
HARDWARE_TYPE_RTL8822CE,
|
||||
HARDWARE_TYPE_RTL8822CU,
|
||||
HARDWARE_TYPE_RTL8822CS,
|
||||
HARDWARE_TYPE_RTL8814BE,
|
||||
HARDWARE_TYPE_RTL8814BU,
|
||||
HARDWARE_TYPE_RTL8814BS,
|
||||
HARDWARE_TYPE_RTL8723FU,
|
||||
HARDWARE_TYPE_RTL8723FS,
|
||||
HARDWARE_TYPE_MAX,
|
||||
} HARDWARE_TYPE;
|
||||
|
||||
#define IS_NEW_GENERATION_IC(_Adapter) (rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE)
|
||||
/*
|
||||
* RTL8188E Series
|
||||
* */
|
||||
#define IS_HARDWARE_TYPE_8188EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE)
|
||||
#define IS_HARDWARE_TYPE_8188EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU)
|
||||
#define IS_HARDWARE_TYPE_8188ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES)
|
||||
#define IS_HARDWARE_TYPE_8188E(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter))
|
||||
|
||||
/* RTL8812 Series */
|
||||
#define IS_HARDWARE_TYPE_8812E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E)
|
||||
#define IS_HARDWARE_TYPE_8812AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU)
|
||||
#define IS_HARDWARE_TYPE_8812(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter))
|
||||
|
||||
/* RTL8821 Series */
|
||||
#define IS_HARDWARE_TYPE_8821E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E)
|
||||
#define IS_HARDWARE_TYPE_8811AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
|
||||
#define IS_HARDWARE_TYPE_8821U(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \
|
||||
rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU)
|
||||
#define IS_HARDWARE_TYPE_8821S(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S)
|
||||
#define IS_HARDWARE_TYPE_8821(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter))
|
||||
|
||||
/* RTL8192E Series */
|
||||
#define IS_HARDWARE_TYPE_8192EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE)
|
||||
#define IS_HARDWARE_TYPE_8192EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU)
|
||||
#define IS_HARDWARE_TYPE_8192ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8192E(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8723BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE)
|
||||
#define IS_HARDWARE_TYPE_8723BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU)
|
||||
#define IS_HARDWARE_TYPE_8723BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8723B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter))
|
||||
|
||||
/* RTL8814A Series */
|
||||
#define IS_HARDWARE_TYPE_8814AE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE)
|
||||
#define IS_HARDWARE_TYPE_8814AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU)
|
||||
#define IS_HARDWARE_TYPE_8814AS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8814A(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter))
|
||||
|
||||
/* RTL8703B Series */
|
||||
#define IS_HARDWARE_TYPE_8703BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE)
|
||||
#define IS_HARDWARE_TYPE_8703BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS)
|
||||
#define IS_HARDWARE_TYPE_8703BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU)
|
||||
#define IS_HARDWARE_TYPE_8703B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter))
|
||||
|
||||
/* RTL8723D Series */
|
||||
#define IS_HARDWARE_TYPE_8723DE(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE)
|
||||
#define IS_HARDWARE_TYPE_8723DS(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS)
|
||||
#define IS_HARDWARE_TYPE_8723DU(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU)
|
||||
#define IS_HARDWARE_TYPE_8723D(_Adapter)\
|
||||
(IS_HARDWARE_TYPE_8723DE(_Adapter) || \
|
||||
IS_HARDWARE_TYPE_8723DU(_Adapter) || \
|
||||
IS_HARDWARE_TYPE_8723DS(_Adapter))
|
||||
|
||||
/* RTL8192F Series */
|
||||
#define IS_HARDWARE_TYPE_8192FS(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS)
|
||||
#define IS_HARDWARE_TYPE_8192FU(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU)
|
||||
#define IS_HARDWARE_TYPE_8192FE(_Adapter)\
|
||||
(rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE)
|
||||
#define IS_HARDWARE_TYPE_8192F(_Adapter)\
|
||||
(IS_HARDWARE_TYPE_8192FS(_Adapter) ||\
|
||||
IS_HARDWARE_TYPE_8192FU(_Adapter) ||\
|
||||
IS_HARDWARE_TYPE_8192FE(_Adapter))
|
||||
|
||||
/* RTL8188F Series */
|
||||
#define IS_HARDWARE_TYPE_8188FE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE)
|
||||
#define IS_HARDWARE_TYPE_8188FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS)
|
||||
#define IS_HARDWARE_TYPE_8188FU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU)
|
||||
#define IS_HARDWARE_TYPE_8188F(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8188GTVU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU)
|
||||
#define IS_HARDWARE_TYPE_8188GTVS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS)
|
||||
#define IS_HARDWARE_TYPE_8188GTV(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter))
|
||||
|
||||
/* RTL8710B Series */
|
||||
#define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU)
|
||||
#define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8821BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE)
|
||||
#define IS_HARDWARE_TYPE_8821BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU)
|
||||
#define IS_HARDWARE_TYPE_8821BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS)
|
||||
|
||||
#define IS_HARDWARE_TYPE_8821B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8822BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE)
|
||||
#define IS_HARDWARE_TYPE_8822BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU)
|
||||
#define IS_HARDWARE_TYPE_8822BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS)
|
||||
#define IS_HARDWARE_TYPE_8822B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8821CE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE)
|
||||
#define IS_HARDWARE_TYPE_8821CU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU)
|
||||
#define IS_HARDWARE_TYPE_8821CS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS)
|
||||
#define IS_HARDWARE_TYPE_8821C(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8822CE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CE)
|
||||
#define IS_HARDWARE_TYPE_8822CU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CU)
|
||||
#define IS_HARDWARE_TYPE_8822CS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CS)
|
||||
#define IS_HARDWARE_TYPE_8822C(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8822CE(_Adapter) || IS_HARDWARE_TYPE_8822CU(_Adapter) || IS_HARDWARE_TYPE_8822CS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8814BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BE)
|
||||
#define IS_HARDWARE_TYPE_8814BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BU)
|
||||
#define IS_HARDWARE_TYPE_8814BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BS)
|
||||
#define IS_HARDWARE_TYPE_8814B(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8814BE(_Adapter) || IS_HARDWARE_TYPE_8814BU(_Adapter) || IS_HARDWARE_TYPE_8814BS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_8723FU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723FU)
|
||||
#define IS_HARDWARE_TYPE_8723FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723FS)
|
||||
#define IS_HARDWARE_TYPE_8723F(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8723FU(_Adapter) || IS_HARDWARE_TYPE_8723FS(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR3(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8814B(_Adapter) || IS_HARDWARE_TYPE_8822C(_Adapter))
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR3_11N(_Adapter) IS_HARDWARE_TYPE_8723F(_Adapter)
|
||||
|
||||
#define IS_HARDWARE_TYPE_JAGUAR_ALL(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) || IS_HARDWARE_TYPE_JAGUAR3(_Adapter))
|
||||
|
||||
|
||||
typedef enum _wowlan_subcode {
|
||||
WOWLAN_ENABLE = 0,
|
||||
WOWLAN_DISABLE = 1,
|
||||
WOWLAN_AP_ENABLE = 2,
|
||||
WOWLAN_AP_DISABLE = 3,
|
||||
WOWLAN_PATTERN_CLEAN = 4
|
||||
} wowlan_subcode;
|
||||
|
||||
struct wowlan_ioctl_param {
|
||||
unsigned int subcode;
|
||||
unsigned int subcode_value;
|
||||
unsigned int wakeup_reason;
|
||||
};
|
||||
|
||||
u8 rtw_hal_data_init(_adapter *padapter);
|
||||
void rtw_hal_data_deinit(_adapter *padapter);
|
||||
|
||||
void rtw_hal_def_value_init(_adapter *padapter);
|
||||
|
||||
void rtw_hal_free_data(_adapter *padapter);
|
||||
|
||||
void rtw_hal_dm_init(_adapter *padapter);
|
||||
void rtw_hal_dm_deinit(_adapter *padapter);
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
void rtw_hal_sw_led_init(_adapter *padapter);
|
||||
void rtw_hal_sw_led_deinit(_adapter *padapter);
|
||||
#endif
|
||||
u32 rtw_hal_power_on(_adapter *padapter);
|
||||
void rtw_hal_power_off(_adapter *padapter);
|
||||
|
||||
uint rtw_hal_init(_adapter *padapter);
|
||||
#ifdef CONFIG_NEW_NETDEV_HDL
|
||||
uint rtw_hal_iface_init(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit);
|
||||
void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter);
|
||||
void dump_hal_trx_mode(void *sel, _adapter *adapter);
|
||||
u8 rtw_hal_rfpath_init(_adapter *adapter);
|
||||
u8 rtw_hal_trxnss_init(_adapter *adapter);
|
||||
|
||||
uint rtw_hal_deinit(_adapter *padapter);
|
||||
void rtw_hal_stop(_adapter *padapter);
|
||||
u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val);
|
||||
|
||||
void rtw_hal_chip_configure(_adapter *padapter);
|
||||
u8 rtw_hal_read_chip_info(_adapter *padapter);
|
||||
void rtw_hal_read_chip_version(_adapter *padapter);
|
||||
|
||||
u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
|
||||
u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue);
|
||||
|
||||
void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet);
|
||||
void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2);
|
||||
|
||||
void rtw_hal_enable_interrupt(_adapter *padapter);
|
||||
void rtw_hal_disable_interrupt(_adapter *padapter);
|
||||
|
||||
u8 rtw_hal_check_ips_status(_adapter *padapter);
|
||||
|
||||
#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
|
||||
u32 rtw_hal_inirp_init(_adapter *padapter);
|
||||
u32 rtw_hal_inirp_deinit(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI_HCI)
|
||||
void rtw_hal_irp_reset(_adapter *padapter);
|
||||
void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data);
|
||||
u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr);
|
||||
void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data);
|
||||
u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr);
|
||||
u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter);
|
||||
u8 rtw_hal_pci_l1off_capability(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
|
||||
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtw_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
|
||||
|
||||
s32 rtw_hal_init_xmit_priv(_adapter *padapter);
|
||||
void rtw_hal_free_xmit_priv(_adapter *padapter);
|
||||
|
||||
s32 rtw_hal_init_recv_priv(_adapter *padapter);
|
||||
void rtw_hal_free_recv_priv(_adapter *padapter);
|
||||
|
||||
void rtw_hal_update_ra_mask(struct sta_info *psta);
|
||||
|
||||
void rtw_hal_start_thread(_adapter *padapter);
|
||||
void rtw_hal_stop_thread(_adapter *padapter);
|
||||
|
||||
void rtw_hal_bcn_related_reg_setting(_adapter *padapter);
|
||||
|
||||
u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask);
|
||||
void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask);
|
||||
void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
|
||||
|
||||
#define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask))
|
||||
#define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data))
|
||||
#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask))
|
||||
#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
|
||||
|
||||
#ifdef CONFIG_SYSON_INDIRECT_ACCESS
|
||||
u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask);
|
||||
void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data);
|
||||
#define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask))
|
||||
#define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data))
|
||||
#endif
|
||||
|
||||
#define phy_set_mac_reg phy_set_bb_reg
|
||||
#define phy_query_mac_reg phy_query_bb_reg
|
||||
|
||||
#if defined(CONFIG_PCI_HCI)
|
||||
s32 rtw_hal_interrupt_handler(_adapter *padapter);
|
||||
void rtw_hal_unmap_beacon_icf(_adapter *padapter);
|
||||
#endif
|
||||
#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
|
||||
void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf);
|
||||
#endif
|
||||
|
||||
void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80);
|
||||
void rtw_hal_dm_watchdog(_adapter *padapter);
|
||||
void rtw_hal_dm_watchdog_in_lps(_adapter *padapter);
|
||||
|
||||
#ifdef CONFIG_HOSTAPD_MLME
|
||||
s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt);
|
||||
#endif
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
void rtw_hal_sreset_init(_adapter *padapter);
|
||||
void rtw_hal_sreset_reset(_adapter *padapter);
|
||||
void rtw_hal_sreset_reset_value(_adapter *padapter);
|
||||
void rtw_hal_sreset_xmit_status_check(_adapter *padapter);
|
||||
void rtw_hal_sreset_linked_status_check(_adapter *padapter);
|
||||
u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter);
|
||||
bool rtw_hal_sreset_inprogress(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IOL
|
||||
int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_XMIT_THREAD_MODE
|
||||
s32 rtw_hal_xmit_thread_handler(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RECV_THREAD_MODE
|
||||
s32 rtw_hal_recv_hdl(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
void rtw_hal_notch_filter(_adapter *adapter, bool enable);
|
||||
|
||||
#ifdef CONFIG_FW_C2H_REG
|
||||
bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload);
|
||||
bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf);
|
||||
s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_PKT
|
||||
bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload);
|
||||
#endif
|
||||
|
||||
s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
|
||||
#ifndef RTW_HALMAC
|
||||
s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
|
||||
s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
|
||||
#endif
|
||||
|
||||
s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter);
|
||||
|
||||
s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid);
|
||||
s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid);
|
||||
s32 rtw_hal_macid_sleep_all_used(_adapter *adapter);
|
||||
s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter);
|
||||
|
||||
s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid);
|
||||
s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid);
|
||||
|
||||
s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen,
|
||||
u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan);
|
||||
|
||||
#ifdef CONFIG_GPIO_API
|
||||
void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag);
|
||||
int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num);
|
||||
void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num);
|
||||
#endif
|
||||
#ifdef CONFIG_FW_CORRECT_BCN
|
||||
void rtw_hal_fw_correct_bcn(_adapter *padapter);
|
||||
#endif
|
||||
s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan);
|
||||
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
void rtw_hal_clear_interrupt(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel);
|
||||
void rtw_hal_update_txpwr_level(_adapter *adapter);
|
||||
void rtw_hal_set_txpwr_done(_adapter *adapter);
|
||||
void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex
|
||||
, enum rf_path rfpath, u8 rate);
|
||||
|
||||
u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath
|
||||
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch
|
||||
, struct txpwr_idx_comp *tic);
|
||||
s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath
|
||||
, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch);
|
||||
|
||||
u8 rtw_hal_ops_check(_adapter *padapter);
|
||||
|
||||
#ifdef RTW_HALMAC
|
||||
u8 rtw_hal_init_mac_register(PADAPTER);
|
||||
u8 rtw_hal_init_phy(PADAPTER);
|
||||
s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem);
|
||||
#endif /* RTW_HALMAC */
|
||||
|
||||
#ifdef CONFIG_RFKILL_POLL
|
||||
bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid);
|
||||
#endif
|
||||
|
||||
#endif /* __HAL_INTF_H__ */
|
||||
|
|
@ -0,0 +1,997 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __HAL_PG_H__
|
||||
#define __HAL_PG_H__
|
||||
|
||||
#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
|
||||
#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
|
||||
|
||||
#define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
|
||||
#define PPG_THERMAL_OFFSET_MASK 0x1F
|
||||
#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
|
||||
#define KFREE_BB_GAIN_2G_TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg_v) >> 5) : (-((_ppg_v) >> 5))))
|
||||
#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
|
||||
#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 88EE/88EU/88ES
|
||||
* **************************************************** */
|
||||
#define EEPROM_ChannelPlan_88E 0xB8
|
||||
#define EEPROM_XTAL_88E 0xB9
|
||||
#define EEPROM_THERMAL_METER_88E 0xBA
|
||||
#define EEPROM_IQK_LCK_88E 0xBB
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_88E 0xC1
|
||||
#define EEPROM_RF_FEATURE_OPTION_88E 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_88E 0xC3
|
||||
#define EEPROM_VERSION_88E 0xC4
|
||||
#define EEPROM_CustomID_88E 0xC5
|
||||
#define EEPROM_RF_ANTENNA_OPT_88E 0xC9
|
||||
#define EEPROM_COUNTRY_CODE_88E 0xCB
|
||||
|
||||
/* RTL88EE */
|
||||
#define EEPROM_MAC_ADDR_88EE 0xD0
|
||||
#define EEPROM_VID_88EE 0xD6
|
||||
#define EEPROM_DID_88EE 0xD8
|
||||
#define EEPROM_SVID_88EE 0xDA
|
||||
#define EEPROM_SMID_88EE 0xDC
|
||||
|
||||
/* RTL88EU */
|
||||
#define EEPROM_MAC_ADDR_88EU 0xD7
|
||||
#define EEPROM_VID_88EU 0xD0
|
||||
#define EEPROM_PID_88EU 0xD2
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 /* 8188EU, 8192EU, 8812AU is the same */
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104
|
||||
|
||||
/* RTL88ES */
|
||||
#define EEPROM_MAC_ADDR_88ES 0x11A
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES
|
||||
* **************************************************** */
|
||||
#define GET_PG_KFREE_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
|
||||
#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
|
||||
|
||||
#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E 0x1F6
|
||||
#define PPG_THERMAL_OFFSET_8192E 0x1F5
|
||||
|
||||
#define EEPROM_ChannelPlan_8192E 0xB8
|
||||
#define EEPROM_XTAL_8192E 0xB9
|
||||
#define EEPROM_THERMAL_METER_8192E 0xBA
|
||||
#define EEPROM_IQK_LCK_8192E 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8192E 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8192E 0xC1
|
||||
#define EEPROM_RF_FEATURE_OPTION_8192E 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8192E 0xC3
|
||||
#define EEPROM_VERSION_8192E 0xC4
|
||||
#define EEPROM_CustomID_8192E 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8192E 0xC6
|
||||
#define EEPROM_TX_BBSWING_5G_8192E 0xC7
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8192E 0xC9
|
||||
#define EEPROM_RFE_OPTION_8192E 0xCA
|
||||
#define EEPROM_RFE_OPTION_8188E 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8192E 0xCB
|
||||
|
||||
/* RTL8192EE */
|
||||
#define EEPROM_MAC_ADDR_8192EE 0xD0
|
||||
#define EEPROM_VID_8192EE 0xD6
|
||||
#define EEPROM_DID_8192EE 0xD8
|
||||
#define EEPROM_SVID_8192EE 0xDA
|
||||
#define EEPROM_SMID_8192EE 0xDC
|
||||
|
||||
/* RTL8192EU */
|
||||
#define EEPROM_MAC_ADDR_8192EU 0xD7
|
||||
#define EEPROM_VID_8192EU 0xD0
|
||||
#define EEPROM_PID_8192EU 0xD2
|
||||
#define EEPROM_PA_TYPE_8192EU 0xBC
|
||||
#define EEPROM_LNA_TYPE_2G_8192EU 0xBD
|
||||
#define EEPROM_LNA_TYPE_5G_8192EU 0xBF
|
||||
|
||||
/* RTL8192ES */
|
||||
#define EEPROM_MAC_ADDR_8192ES 0x11A
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS
|
||||
* *****************************************************/
|
||||
#define EEPROM_USB_MODE_8812 0x08
|
||||
|
||||
#define EEPROM_ChannelPlan_8812 0xB8
|
||||
#define EEPROM_XTAL_8812 0xB9
|
||||
#define EEPROM_THERMAL_METER_8812 0xBA
|
||||
#define EEPROM_IQK_LCK_8812 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8812 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8812 0xC1
|
||||
#define EEPROM_RF_FEATURE_OPTION_8812 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8812 0xC3
|
||||
#define EEPROM_VERSION_8812 0xC4
|
||||
#define EEPROM_CustomID_8812 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8812 0xC6
|
||||
#define EEPROM_TX_BBSWING_5G_8812 0xC7
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8812 0xC9
|
||||
#define EEPROM_RFE_OPTION_8812 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8812 0xCB
|
||||
|
||||
/* RTL8812AE */
|
||||
#define EEPROM_MAC_ADDR_8812AE 0xD0
|
||||
#define EEPROM_VID_8812AE 0xD6
|
||||
#define EEPROM_DID_8812AE 0xD8
|
||||
#define EEPROM_SVID_8812AE 0xDA
|
||||
#define EEPROM_SMID_8812AE 0xDC
|
||||
|
||||
/* RTL8812AU */
|
||||
#define EEPROM_MAC_ADDR_8812AU 0xD7
|
||||
#define EEPROM_VID_8812AU 0xD0
|
||||
#define EEPROM_PID_8812AU 0xD2
|
||||
#define EEPROM_PA_TYPE_8812AU 0xBC
|
||||
#define EEPROM_LNA_TYPE_2G_8812AU 0xBD
|
||||
#define EEPROM_LNA_TYPE_5G_8812AU 0xBF
|
||||
|
||||
/* RTL8814AU */
|
||||
#define EEPROM_MAC_ADDR_8814AU 0xD8
|
||||
#define EEPROM_VID_8814AU 0xD0
|
||||
#define EEPROM_PID_8814AU 0xD2
|
||||
#define EEPROM_PA_TYPE_8814AU 0xBC
|
||||
#define EEPROM_LNA_TYPE_2G_8814AU 0xBD
|
||||
#define EEPROM_LNA_TYPE_5G_8814AU 0xBF
|
||||
|
||||
/* RTL8814AE */
|
||||
#define EEPROM_MAC_ADDR_8814AE 0xD0
|
||||
#define EEPROM_VID_8814AE 0xD6
|
||||
#define EEPROM_DID_8814AE 0xD8
|
||||
#define EEPROM_SVID_8814AE 0xDA
|
||||
#define EEPROM_SMID_8814AE 0xDC
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8814AU
|
||||
* **************************************************** */
|
||||
#define GET_PG_KFREE_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
|
||||
#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
|
||||
#define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2)
|
||||
|
||||
#define KFREE_GAIN_DATA_LENGTH_8814A 22
|
||||
|
||||
#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A 0x3EE
|
||||
|
||||
#define PPG_THERMAL_OFFSET_8814A 0x3EF
|
||||
|
||||
#define EEPROM_USB_MODE_8814A 0x0E
|
||||
#define EEPROM_ChannelPlan_8814 0xB8
|
||||
#define EEPROM_XTAL_8814 0xB9
|
||||
#define EEPROM_THERMAL_METER_8814 0xBA
|
||||
#define EEPROM_IQK_LCK_8814 0xBB
|
||||
|
||||
|
||||
#define EEPROM_PA_TYPE_8814 0xBC
|
||||
#define EEPROM_LNA_TYPE_AB_2G_8814 0xBD
|
||||
#define EEPROM_LNA_TYPE_CD_2G_8814 0xBE
|
||||
#define EEPROM_LNA_TYPE_AB_5G_8814 0xBF
|
||||
#define EEPROM_LNA_TYPE_CD_5G_8814 0xC0
|
||||
#define EEPROM_RF_BOARD_OPTION_8814 0xC1
|
||||
#define EEPROM_RF_BT_SETTING_8814 0xC3
|
||||
#define EEPROM_VERSION_8814 0xC4
|
||||
#define EEPROM_CustomID_8814 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8814 0xC6
|
||||
#define EEPROM_TX_BBSWING_5G_8814 0xC7
|
||||
#define EEPROM_TRX_ANTENNA_OPTION_8814 0xC9
|
||||
#define EEPROM_RFE_OPTION_8814 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8814 0xCB
|
||||
|
||||
/*Extra Info for 8814A Initial Gain Fine Tune suggested by Willis, JIRA: MP123*/
|
||||
#define EEPROM_IG_OFFSET_4_AB_2G_8814A 0x120
|
||||
#define EEPROM_IG_OFFSET_4_CD_2G_8814A 0x121
|
||||
#define EEPROM_IG_OFFSET_4_AB_5GL_8814A 0x122
|
||||
#define EEPROM_IG_OFFSET_4_CD_5GL_8814A 0x123
|
||||
#define EEPROM_IG_OFFSET_4_AB_5GM_8814A 0x124
|
||||
#define EEPROM_IG_OFFSET_4_CD_5GM_8814A 0x125
|
||||
#define EEPROM_IG_OFFSET_4_AB_5GH_8814A 0x126
|
||||
#define EEPROM_IG_OFFSET_4_CD_5GH_8814A 0x127
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS
|
||||
* **************************************************** */
|
||||
|
||||
#define GET_PG_KFREE_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)
|
||||
#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
|
||||
|
||||
#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A 0x1F6
|
||||
#define PPG_THERMAL_OFFSET_8821A 0x1F5
|
||||
#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A 0x1F4
|
||||
#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A 0x1F3
|
||||
#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A 0x1F2
|
||||
#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1
|
||||
#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0
|
||||
|
||||
#define EEPROM_ChannelPlan_8821 0xB8
|
||||
#define EEPROM_XTAL_8821 0xB9
|
||||
#define EEPROM_THERMAL_METER_8821 0xBA
|
||||
#define EEPROM_IQK_LCK_8821 0xBB
|
||||
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8821 0xC1
|
||||
#define EEPROM_RF_FEATURE_OPTION_8821 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8821 0xC3
|
||||
#define EEPROM_VERSION_8821 0xC4
|
||||
#define EEPROM_CustomID_8821 0xC5
|
||||
#define EEPROM_RF_ANTENNA_OPT_8821 0xC9
|
||||
|
||||
/* RTL8821AE */
|
||||
#define EEPROM_MAC_ADDR_8821AE 0xD0
|
||||
#define EEPROM_VID_8821AE 0xD6
|
||||
#define EEPROM_DID_8821AE 0xD8
|
||||
#define EEPROM_SVID_8821AE 0xDA
|
||||
#define EEPROM_SMID_8821AE 0xDC
|
||||
|
||||
/* RTL8821AU */
|
||||
#define EEPROM_PA_TYPE_8821AU 0xBC
|
||||
#define EEPROM_LNA_TYPE_8821AU 0xBF
|
||||
|
||||
/* RTL8821AS */
|
||||
#define EEPROM_MAC_ADDR_8821AS 0x11A
|
||||
|
||||
/* RTL8821AU */
|
||||
#define EEPROM_MAC_ADDR_8821AU 0x107
|
||||
#define EEPROM_VID_8821AU 0x100
|
||||
#define EEPROM_PID_8821AU 0x102
|
||||
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8192 SE/SU
|
||||
* **************************************************** */
|
||||
#define EEPROM_VID_92SE 0x0A
|
||||
#define EEPROM_DID_92SE 0x0C
|
||||
#define EEPROM_SVID_92SE 0x0E
|
||||
#define EEPROM_SMID_92SE 0x10
|
||||
|
||||
#define EEPROM_MAC_ADDR_92S 0x12
|
||||
|
||||
#define EEPROM_TSSI_A_92SE 0x74
|
||||
#define EEPROM_TSSI_B_92SE 0x75
|
||||
|
||||
#define EEPROM_Version_92SE 0x7C
|
||||
|
||||
|
||||
#define EEPROM_VID_92SU 0x08
|
||||
#define EEPROM_PID_92SU 0x0A
|
||||
|
||||
#define EEPROM_Version_92SU 0x50
|
||||
#define EEPROM_TSSI_A_92SU 0x6b
|
||||
#define EEPROM_TSSI_B_92SU 0x6c
|
||||
|
||||
/* ====================================================
|
||||
EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS
|
||||
====================================================
|
||||
*/
|
||||
|
||||
#define GET_PG_KFREE_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
|
||||
#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
|
||||
|
||||
#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE
|
||||
#define PPG_THERMAL_OFFSET_8188F 0xEF
|
||||
|
||||
#define EEPROM_ChannelPlan_8188F 0xB8
|
||||
#define EEPROM_XTAL_8188F 0xB9
|
||||
#define EEPROM_THERMAL_METER_8188F 0xBA
|
||||
#define EEPROM_IQK_LCK_8188F 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8188F 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8188F 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8188F 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8188F 0xC3
|
||||
#define EEPROM_VERSION_8188F 0xC4
|
||||
#define EEPROM_CustomID_8188F 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8188F 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8188F 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8188F 0xC9
|
||||
#define EEPROM_RFE_OPTION_8188F 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8188F 0xCB
|
||||
#define EEPROM_CUSTOMER_ID_8188F 0x7F
|
||||
#define EEPROM_SUBCUSTOMER_ID_8188F 0x59
|
||||
|
||||
/* RTL8188FU */
|
||||
#define EEPROM_MAC_ADDR_8188FU 0xD7
|
||||
#define EEPROM_VID_8188FU 0xD0
|
||||
#define EEPROM_PID_8188FU 0xD2
|
||||
#define EEPROM_PA_TYPE_8188FU 0xBC
|
||||
#define EEPROM_LNA_TYPE_2G_8188FU 0xBD
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4
|
||||
|
||||
/* RTL8188FS */
|
||||
#define EEPROM_MAC_ADDR_8188FS 0x11A
|
||||
#define EEPROM_Voltage_ADDR_8188F 0x8
|
||||
|
||||
/* ====================================================
|
||||
EEPROM/Efuse PG Offset for 8188GTV/8188GTVS
|
||||
====================================================
|
||||
*/
|
||||
|
||||
#define GET_PG_KFREE_ON_8188GTV(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
|
||||
#define GET_PG_KFREE_THERMAL_K_ON_8188GTV(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
|
||||
|
||||
#define PPG_BB_GAIN_2G_TXA_OFFSET_8188GTV 0xEE
|
||||
#define PPG_THERMAL_OFFSET_8188GTV 0xEF
|
||||
|
||||
#define EEPROM_ChannelPlan_8188GTV 0xB8
|
||||
#define EEPROM_XTAL_8188GTV 0xB9
|
||||
#define EEPROM_THERMAL_METER_8188GTV 0xBA
|
||||
#define EEPROM_IQK_LCK_8188GTV 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8188GTV 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188GTV 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188GTV 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8188GTV 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8188GTV 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8188GTV 0xC3
|
||||
#define EEPROM_VERSION_8188GTV 0xC4
|
||||
#define EEPROM_CustomID_8188GTV 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8188GTV 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8188GTV 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8188GTV 0xC9
|
||||
#define EEPROM_RFE_OPTION_8188GTV 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8188GTV 0xCB
|
||||
#define EEPROM_CUSTOMER_ID_8188GTV 0x7F
|
||||
#define EEPROM_SUBCUSTOMER_ID_8188GTV 0x59
|
||||
|
||||
/* RTL8188GTVU */
|
||||
#define EEPROM_MAC_ADDR_8188GTVU 0xD7
|
||||
#define EEPROM_VID_8188GTVU 0xD0
|
||||
#define EEPROM_PID_8188GTVU 0xD2
|
||||
#define EEPROM_PA_TYPE_8188GTVU 0xBC
|
||||
#define EEPROM_LNA_TYPE_2G_8188GTVU 0xBD
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8188GTVU 0xD4
|
||||
|
||||
/* RTL8188GTVS */
|
||||
#define EEPROM_MAC_ADDR_8188GTVS 0x11A
|
||||
#define EEPROM_Voltage_ADDR_8188GTV 0x8
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS
|
||||
* *****************************************************/
|
||||
#define EEPROM_ChannelPlan_8723B 0xB8
|
||||
#define EEPROM_XTAL_8723B 0xB9
|
||||
#define EEPROM_THERMAL_METER_8723B 0xBA
|
||||
#define EEPROM_IQK_LCK_8723B 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8723B 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8723B 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8723B 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8723B 0xC3
|
||||
#define EEPROM_VERSION_8723B 0xC4
|
||||
#define EEPROM_CustomID_8723B 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8723B 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8723B 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8723B 0xC9
|
||||
#define EEPROM_RFE_OPTION_8723B 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8723B 0xCB
|
||||
|
||||
/* RTL8723BE */
|
||||
#define EEPROM_MAC_ADDR_8723BE 0xD0
|
||||
#define EEPROM_VID_8723BE 0xD6
|
||||
#define EEPROM_DID_8723BE 0xD8
|
||||
#define EEPROM_SVID_8723BE 0xDA
|
||||
#define EEPROM_SMID_8723BE 0xDC
|
||||
|
||||
/* RTL8723BU */
|
||||
#define EEPROM_MAC_ADDR_8723BU 0x107
|
||||
#define EEPROM_VID_8723BU 0x100
|
||||
#define EEPROM_PID_8723BU 0x102
|
||||
#define EEPROM_PA_TYPE_8723BU 0xBC
|
||||
#define EEPROM_LNA_TYPE_2G_8723BU 0xBD
|
||||
|
||||
|
||||
/* RTL8723BS */
|
||||
#define EEPROM_MAC_ADDR_8723BS 0x11A
|
||||
#define EEPROM_Voltage_ADDR_8723B 0x8
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8703B
|
||||
* **************************************************** */
|
||||
#define GET_PG_KFREE_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
|
||||
#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
|
||||
|
||||
#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B 0xEE
|
||||
#define PPG_THERMAL_OFFSET_8703B 0xEF
|
||||
|
||||
#define EEPROM_ChannelPlan_8703B 0xB8
|
||||
#define EEPROM_XTAL_8703B 0xB9
|
||||
#define EEPROM_THERMAL_METER_8703B 0xBA
|
||||
#define EEPROM_IQK_LCK_8703B 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8703B 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8703B 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8703B 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8703B 0xC3
|
||||
#define EEPROM_VERSION_8703B 0xC4
|
||||
#define EEPROM_CustomID_8703B 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8703B 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8703B 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8703B 0xC9
|
||||
#define EEPROM_RFE_OPTION_8703B 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8703B 0xCB
|
||||
|
||||
/* RTL8703BU */
|
||||
#define EEPROM_MAC_ADDR_8703BU 0x107
|
||||
#define EEPROM_VID_8703BU 0x100
|
||||
#define EEPROM_PID_8703BU 0x102
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU 0x104
|
||||
#define EEPROM_PA_TYPE_8703BU 0xBC
|
||||
#define EEPROM_LNA_TYPE_2G_8703BU 0xBD
|
||||
|
||||
/* RTL8703BS */
|
||||
#define EEPROM_MAC_ADDR_8703BS 0x11A
|
||||
#define EEPROM_Voltage_ADDR_8703B 0x8
|
||||
|
||||
/*
|
||||
* ====================================================
|
||||
* EEPROM/Efuse PG Offset for 8822B
|
||||
* ====================================================
|
||||
*/
|
||||
#define EEPROM_ChannelPlan_8822B 0xB8
|
||||
#define EEPROM_XTAL_8822B 0xB9
|
||||
#define EEPROM_THERMAL_METER_8822B 0xBA
|
||||
#define EEPROM_IQK_LCK_8822B 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8822B 0xBC
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBD
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B 0xBE
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBF
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B 0xC0
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8822B 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8822B 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8822B 0xC3
|
||||
#define EEPROM_VERSION_8822B 0xC4
|
||||
#define EEPROM_CustomID_8822B 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8822B 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8822B 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8822B 0xC9
|
||||
#define EEPROM_RFE_OPTION_8822B 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8822B 0xCB
|
||||
|
||||
/* RTL8822BU */
|
||||
#define EEPROM_MAC_ADDR_8822BU 0x107
|
||||
#define EEPROM_VID_8822BU 0x100
|
||||
#define EEPROM_PID_8822BU 0x102
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU 0x104
|
||||
#define EEPROM_USB_MODE_8822BU 0x06
|
||||
|
||||
/* RTL8822BS */
|
||||
#define EEPROM_MAC_ADDR_8822BS 0x11A
|
||||
|
||||
/* RTL8822BE */
|
||||
#define EEPROM_MAC_ADDR_8822BE 0xD0
|
||||
/*
|
||||
* ====================================================
|
||||
* EEPROM/Efuse PG Offset for 8821C
|
||||
* ====================================================
|
||||
*/
|
||||
#define EEPROM_CHANNEL_PLAN_8821C 0xB8
|
||||
#define EEPROM_XTAL_8821C 0xB9
|
||||
#define EEPROM_THERMAL_METER_8821C 0xBA
|
||||
#define EEPROM_IQK_LCK_8821C 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8821C 0xBC
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8821C 0xBD
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8821C 0xBE
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8821C 0xBF
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8821C 0xC0
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8821C 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8821C 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8821C 0xC3
|
||||
#define EEPROM_VERSION_8821C 0xC4
|
||||
#define EEPROM_CUSTOMER_ID_8821C 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8821C 0xC6
|
||||
#define EEPROM_TX_BBSWING_5G_8821C 0xC7
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8821C 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8821C 0xC9
|
||||
#define EEPROM_RFE_OPTION_8821C 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8821C 0xCB
|
||||
|
||||
/* RTL8821CU */
|
||||
#define EEPROM_MAC_ADDR_8821CU 0x107
|
||||
#define EEPROM_VID_8821CU 0x100
|
||||
#define EEPROM_PID_8821CU 0x102
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8821CU 0x104
|
||||
#define EEPROM_USB_MODE_8821CU 0x06
|
||||
|
||||
/* RTL8821CS */
|
||||
#define EEPROM_MAC_ADDR_8821CS 0x11A
|
||||
|
||||
/* RTL8821CE */
|
||||
#define EEPROM_MAC_ADDR_8821CE 0xD0
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8723D
|
||||
* **************************************************** */
|
||||
#define GET_PG_KFREE_ON_8723D(_pg_m) \
|
||||
LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)
|
||||
#define GET_PG_KFREE_THERMAL_K_ON_8723D(_pg_m) \
|
||||
LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)
|
||||
|
||||
#define PPG_8723D_S1 0
|
||||
#define PPG_8723D_S0 1
|
||||
|
||||
#define PPG_BB_GAIN_2G_TXA_OFFSET_8723D 0xEE
|
||||
#define PPG_BB_GAIN_2G_TX_OFFSET_8723D 0x1EE
|
||||
#define PPG_THERMAL_OFFSET_8723D 0xEF
|
||||
|
||||
#define EEPROM_ChannelPlan_8723D 0xB8
|
||||
#define EEPROM_XTAL_8723D 0xB9
|
||||
#define EEPROM_THERMAL_METER_8723D 0xBA
|
||||
#define EEPROM_IQK_LCK_8723D 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8723D 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723D 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723D 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8723D 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8723D 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8723D 0xC3
|
||||
#define EEPROM_VERSION_8723D 0xC4
|
||||
#define EEPROM_CustomID_8723D 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8723D 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8723D 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8723D 0xC9
|
||||
#define EEPROM_RFE_OPTION_8723D 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8723D 0xCB
|
||||
|
||||
/* RTL8723DE */
|
||||
#define EEPROM_MAC_ADDR_8723DE 0xD0
|
||||
#define EEPROM_VID_8723DE 0xD6
|
||||
#define EEPROM_DID_8723DE 0xD8
|
||||
#define EEPROM_SVID_8723DE 0xDA
|
||||
#define EEPROM_SMID_8723DE 0xDC
|
||||
|
||||
/* RTL8723DU */
|
||||
#define EEPROM_MAC_ADDR_8723DU 0x107
|
||||
#define EEPROM_VID_8723DU 0x100
|
||||
#define EEPROM_PID_8723DU 0x102
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8723DU 0x104
|
||||
|
||||
/* RTL8723BS */
|
||||
#define EEPROM_MAC_ADDR_8723DS 0x11A
|
||||
#define EEPROM_Voltage_ADDR_8723D 0x8
|
||||
|
||||
/*
|
||||
* ====================================================
|
||||
* EEPROM/Efuse PG Offset for 8822C
|
||||
* ====================================================
|
||||
*/
|
||||
#define EEPROM_TX_PWR_INX_8822C 0x10
|
||||
#define EEPROM_ChannelPlan_8822C 0xB8
|
||||
#define EEPROM_XTAL_B9_8822C 0xB9
|
||||
#define EEPROM_IQK_LCK_8822C 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8822C 0xBC
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C 0xBD
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822C 0xBE
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C 0xBF
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822C 0xC0
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8822C 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8822C 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8822C 0xC3
|
||||
#define EEPROM_VERSION_8822C 0xC4
|
||||
#define EEPROM_CustomID_8822C 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8822C 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8822C 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8822C 0xC9
|
||||
#define EEPROM_RFE_OPTION_8822C 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8822C 0xCB
|
||||
#define EEPROM_THERMAL_METER_A_8822C 0xD0
|
||||
#define EEPROM_THERMAL_METER_B_8822C 0xD1
|
||||
|
||||
#define EEPROM_XTAL_110_8822C 0x110
|
||||
#define EEPROM_XTAL_111_8822C 0x111
|
||||
|
||||
/* RTL8822CU */
|
||||
#define EEPROM_MAC_ADDR_8822CU 0x157
|
||||
#define EEPROM_VID_8822CU 0x100
|
||||
#define EEPROM_PID_8822CU 0x102
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8822CU 0x104
|
||||
#define EEPROM_USB_MODE_8822CU 0x06
|
||||
|
||||
/* RTL8822CS */
|
||||
#define EEPROM_MAC_ADDR_8822CS 0x16A
|
||||
|
||||
/* RTL8822CE */
|
||||
#define EEPROM_MAC_ADDR_8822CE 0x120
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8192F
|
||||
* **************************************************** */
|
||||
#define EEPROM_ChannelPlan_8192F 0xB8
|
||||
#define EEPROM_XTAL_8192F 0xB9
|
||||
#define EEPROM_THERMAL_METER_8192F 0xBA
|
||||
#define EEPROM_IQK_LCK_8192F 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8192F 0xBC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192F 0xBD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192F 0xBF
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8192F 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8192F 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8192F 0xC3
|
||||
#define EEPROM_VERSION_8192F 0xC4
|
||||
#define EEPROM_CustomID_8192F 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8192F 0xC6
|
||||
#define EEPROM_TX_BBSWING_5G_8192F 0xC7
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8192F 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8192F 0xC9
|
||||
#define EEPROM_RFE_OPTION_8192F 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8192F 0xCB
|
||||
/*RTL8192FS*/
|
||||
#define EEPROM_MAC_ADDR_8192FS 0x11A
|
||||
#define EEPROM_Voltage_ADDR_8192F 0x8
|
||||
/* RTL8192FU */
|
||||
#define EEPROM_MAC_ADDR_8192FU 0x107
|
||||
#define EEPROM_VID_8192FU 0x100
|
||||
#define EEPROM_PID_8192FU 0x102
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8192FU 0x104
|
||||
/* RTL8192FE */
|
||||
#define EEPROM_MAC_ADDR_8192FE 0xD0
|
||||
#define EEPROM_VID_8192FE 0xD6
|
||||
#define EEPROM_DID_8192FE 0xD8
|
||||
#define EEPROM_SVID_8192FE 0xDA
|
||||
#define EEPROM_SMID_8192FE 0xDC
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8710B
|
||||
* **************************************************** */
|
||||
#define RTL_EEPROM_ID_8710B 0x8195
|
||||
#define EEPROM_Default_ThermalMeter_8710B 0x1A
|
||||
|
||||
#define EEPROM_CHANNEL_PLAN_8710B 0xC8
|
||||
#define EEPROM_XTAL_8710B 0xC9
|
||||
#define EEPROM_THERMAL_METER_8710B 0xCA
|
||||
#define EEPROM_IQK_LCK_8710B 0xCB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8710B 0xCC
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8710B 0xCD
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8710B 0xCF
|
||||
#define EEPROM_TX_KFREE_8710B 0xEE //Physical Efuse Address
|
||||
#define EEPROM_THERMAL_8710B 0xEF //Physical Efuse Address
|
||||
#define EEPROM_PACKAGE_TYPE_8710B 0xF8 //Physical Efuse Address
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8710B 0x131
|
||||
#define EEPROM_RF_FEATURE_OPTION_8710B 0x132
|
||||
#define EEPROM_RF_BT_SETTING_8710B 0x133
|
||||
#define EEPROM_VERSION_8710B 0x134
|
||||
#define EEPROM_CUSTOM_ID_8710B 0x135
|
||||
#define EEPROM_TX_BBSWING_2G_8710B 0x136
|
||||
#define EEPROM_TX_BBSWING_5G_8710B 0x137
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8710B 0x138
|
||||
#define EEPROM_RF_ANTENNA_OPT_8710B 0x139
|
||||
#define EEPROM_RFE_OPTION_8710B 0x13A
|
||||
#define EEPROM_COUNTRY_CODE_8710B 0x13B
|
||||
#define EEPROM_COUNTRY_CODE_2_8710B 0x13C
|
||||
|
||||
#define EEPROM_MAC_ADDR_8710B 0x11A
|
||||
#define EEPROM_VID_8710BU 0x1C0
|
||||
#define EEPROM_PID_8710BU 0x1C2
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse PG Offset for 8814B
|
||||
* **************************************************** */
|
||||
|
||||
#define EEPROM_USB_MODE_8814BU 0x06
|
||||
/* 0x10 ~ 0x63 = TX power area. */
|
||||
#define EEPROM_TX_PWR_INX_8814B 0x10
|
||||
#define EEPROM_ChannelPlan_8814B 0xB8
|
||||
#define EEPROM_XTAL_8814B 0xB9
|
||||
#define EEPROM_IQK_LCK_8814B 0xBB
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8814B 0xC1
|
||||
#define EEPROM_RF_FEATURE_OPTION_8814B 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8814B 0xC3
|
||||
#define EEPROM_VERSION_8814B 0xC4
|
||||
#define EEPROM_CustomID_8814B 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8814B 0xC6
|
||||
#define EEPROM_TX_BBSWING_5G_8814B 0xC7
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8814B 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8814B 0xC9
|
||||
#define EEPROM_RFE_OPTION_8814B 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8814B 0xCB
|
||||
|
||||
#define EEPROM_THERMAL_METER_A_8814B 0xD0
|
||||
#define EEPROM_THERMAL_METER_B_8814B 0xD1
|
||||
#define EEPROM_THERMAL_METER_C_8814B 0xD2
|
||||
#define EEPROM_THERMAL_METER_D_8814B 0xD3
|
||||
|
||||
#define EEPROM_MAC_ADDR_8814BE 0x120
|
||||
#define EEPROM_VID_8814B 0x126
|
||||
#define EEPROM_DID_8814B 0x128
|
||||
#define EEPROM_SVID_8814B 0x12A
|
||||
#define EEPROM_SMID_8814B 0x12C
|
||||
|
||||
/* RTL8814BU */
|
||||
#define EEPROM_MAC_ADDR_8814BU 0x157
|
||||
#define EEPROM_VID_8814BU 0x150
|
||||
#define EEPROM_PID_8814BU 0x152
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8814BU 0x154
|
||||
|
||||
/*
|
||||
* ====================================================
|
||||
* EEPROM/Efuse PG Offset for 8723F
|
||||
* ====================================================
|
||||
*/
|
||||
#define EEPROM_TX_PWR_INX_8723F 0x10
|
||||
#define EEPROM_ChannelPlan_8723F 0xB8
|
||||
#define EEPROM_XTAL_B9_8723F 0xB9
|
||||
#define EEPROM_THERMAL_METER_8723F 0xBA
|
||||
#define EEPROM_IQK_LCK_8723F 0xBB
|
||||
#define EEPROM_2G_5G_PA_TYPE_8723F 0xBC
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8723F 0xBD
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8723F 0xBE
|
||||
/* PATH A & PATH B */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8723F 0xBF
|
||||
/* PATH C & PATH D */
|
||||
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8723F 0xC0
|
||||
|
||||
#define EEPROM_RF_BOARD_OPTION_8723F 0xC1
|
||||
#define EEPROM_FEATURE_OPTION_8723F 0xC2
|
||||
#define EEPROM_RF_BT_SETTING_8723F 0xC3
|
||||
#define EEPROM_VERSION_8723F 0xC4
|
||||
#define EEPROM_CustomID_8723F 0xC5
|
||||
#define EEPROM_TX_BBSWING_2G_8723F 0xC6
|
||||
#define EEPROM_TX_PWR_CALIBRATE_RATE_8723F 0xC8
|
||||
#define EEPROM_RF_ANTENNA_OPT_8723F 0xC9
|
||||
#define EEPROM_RFE_OPTION_8723F 0xCA
|
||||
#define EEPROM_COUNTRY_CODE_8723F 0xCB
|
||||
|
||||
/* RTL8723FU */
|
||||
#define EEPROM_MAC_ADDR_8723FU 0x108
|
||||
#define EEPROM_VID_8723FU 0x100
|
||||
#define EEPROM_PID_8723FU 0x102
|
||||
#define EEPROM_USB_OPTIONAL_FUNCTION0_8723FU 0x104
|
||||
#define EEPROM_USB_MODE_8723FU 0x03
|
||||
|
||||
/* RTL8723FS */
|
||||
#define EEPROM_MAC_ADDR_8723FS 0x11A
|
||||
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse Value Type
|
||||
* **************************************************** */
|
||||
#define EETYPE_TX_PWR 0x0
|
||||
#define EETYPE_MAX_RFE_8192F 0x31
|
||||
/* ****************************************************
|
||||
* EEPROM/Efuse Default Value
|
||||
* **************************************************** */
|
||||
#define EEPROM_CID_DEFAULT 0x0
|
||||
#define EEPROM_CID_DEFAULT_EXT 0xFF /* Reserved for Realtek */
|
||||
#define EEPROM_CID_TOSHIBA 0x4
|
||||
#define EEPROM_CID_CCX 0x10
|
||||
#define EEPROM_CID_QMI 0x0D
|
||||
#define EEPROM_CID_WHQL 0xFE
|
||||
|
||||
#define EEPROM_CHANNEL_PLAN_FCC 0x0
|
||||
#define EEPROM_CHANNEL_PLAN_IC 0x1
|
||||
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
|
||||
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
|
||||
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
|
||||
#define EEPROM_CHANNEL_PLAN_MKK 0x5
|
||||
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
|
||||
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
|
||||
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
|
||||
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
|
||||
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
|
||||
#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB
|
||||
#define EEPROM_CHANNEL_PLAN_CHIAN 0XC
|
||||
#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD
|
||||
#define EEPROM_CHANNEL_PLAN_KOREA 0xE
|
||||
#define EEPROM_CHANNEL_PLAN_TURKEY 0xF
|
||||
#define EEPROM_CHANNEL_PLAN_JAPAN 0x10
|
||||
#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11
|
||||
#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12
|
||||
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13
|
||||
#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14
|
||||
|
||||
#define EEPROM_USB_OPTIONAL1 0xE
|
||||
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
|
||||
|
||||
#define RTL_EEPROM_ID 0x8129
|
||||
#define EEPROM_Default_TSSI 0x0
|
||||
#define EEPROM_Default_BoardType 0x02
|
||||
#define EEPROM_Default_ThermalMeter 0x12
|
||||
#define EEPROM_Default_ThermalMeter_92SU 0x7
|
||||
#define EEPROM_Default_ThermalMeter_88E 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8812 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8192E 0x1A
|
||||
#define EEPROM_Default_ThermalMeter_8723B 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8703B 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8723D 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8188F 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8188GTV 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8814A 0x18
|
||||
#define EEPROM_Default_ThermalMeter_8192F 0x1A
|
||||
#define EEPROM_Default_ThermalMeter_8814B 0x20
|
||||
|
||||
#define EEPROM_Default_CrystalCap 0x0
|
||||
#define EEPROM_Default_CrystalCap_8723A 0x20
|
||||
#define EEPROM_Default_CrystalCap_88E 0x20
|
||||
#define EEPROM_Default_CrystalCap_8812 0x20
|
||||
#define EEPROM_Default_CrystalCap_8814 0x20
|
||||
#define EEPROM_Default_CrystalCap_8192E 0x20
|
||||
#define EEPROM_Default_CrystalCap_8723B 0x20
|
||||
#define EEPROM_Default_CrystalCap_8703B 0x20
|
||||
#define EEPROM_Default_CrystalCap_8723D 0x20
|
||||
#define EEPROM_Default_CrystalCap_8723F 0x3F
|
||||
#define EEPROM_Default_CrystalCap_8188F 0x20
|
||||
#define EEPROM_Default_CrystalCap_8188GTV 0x20
|
||||
#define EEPROM_Default_CrystalCap_8192F 0x20
|
||||
#define EEPROM_Default_CrystalCap_B9_8822C 0x3F
|
||||
#define EEPROM_Default_CrystalCap_110_8822C 0x40
|
||||
#define EEPROM_Default_CrystalCap_111_8822C 0x40
|
||||
#define EEPROM_Default_CrystalCap_8814B 0x40
|
||||
#define EEPROM_Default_CrystalFreq 0x0
|
||||
#define EEPROM_Default_TxPowerLevel_92C 0x22
|
||||
#define EEPROM_Default_TxPowerLevel_2G 0x2C
|
||||
#define EEPROM_Default_TxPowerLevel_5G 0x22
|
||||
#define EEPROM_Default_TxPowerLevel 0x22
|
||||
#define EEPROM_Default_HT40_2SDiff 0x0
|
||||
#define EEPROM_Default_HT20_Diff 2
|
||||
#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
|
||||
#define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3
|
||||
#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4
|
||||
#define EEPROM_Default_HT40_PwrMaxOffset 0
|
||||
#define EEPROM_Default_HT20_PwrMaxOffset 0
|
||||
|
||||
#define EEPROM_Default_PID 0x1234
|
||||
#define EEPROM_Default_VID 0x5678
|
||||
#define EEPROM_Default_CustomerID 0xAB
|
||||
#define EEPROM_Default_CustomerID_8188E 0x00
|
||||
#define EEPROM_Default_SubCustomerID 0xCD
|
||||
#define EEPROM_Default_Version 0
|
||||
|
||||
#define EEPROM_Default_externalPA_C9 0x00
|
||||
#define EEPROM_Default_externalPA_CC 0xFF
|
||||
#define EEPROM_Default_internalPA_SP3T_C9 0xAA
|
||||
#define EEPROM_Default_internalPA_SP3T_CC 0xAF
|
||||
#define EEPROM_Default_internalPA_SPDT_C9 0xAA
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define EEPROM_Default_internalPA_SPDT_CC 0xA0
|
||||
#else
|
||||
#define EEPROM_Default_internalPA_SPDT_CC 0xFA
|
||||
#endif
|
||||
#define EEPROM_Default_PAType 0
|
||||
#define EEPROM_Default_LNAType 0
|
||||
|
||||
/* New EFUSE default value */
|
||||
#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F
|
||||
#define EEPROM_DEFAULT_BOARD_OPTION 0x00
|
||||
#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF
|
||||
#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF
|
||||
#define EEPROM_DEFAULT_RFE_OPTION 0x04
|
||||
#define EEPROM_DEFAULT_FEATURE_OPTION 0x00
|
||||
#define EEPROM_DEFAULT_BT_OPTION 0x10
|
||||
|
||||
|
||||
#define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00
|
||||
|
||||
/* PCIe related */
|
||||
#define EEPROM_PCIE_DEV_CAP_01 0xE0 /* Express device capability in PCIe configuration space, i.e., map to offset 0x74 */
|
||||
#define EEPROM_PCIE_DEV_CAP_02 0xE1 /* Express device capability in PCIe configuration space, i.e., map to offset 0x75 */
|
||||
|
||||
|
||||
/*
|
||||
* For VHT series TX power by rate table.
|
||||
* VHT TX power by rate off setArray =
|
||||
* Band:-2G&5G = 0 / 1
|
||||
* RF: at most 4*4 = ABCD=0/1/2/3
|
||||
* CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
|
||||
* */
|
||||
#define TX_PWR_BY_RATE_NUM_BAND 2
|
||||
#define TX_PWR_BY_RATE_NUM_RF 4
|
||||
#define TX_PWR_BY_RATE_NUM_RATE 84
|
||||
|
||||
#define TXPWR_LMT_MAX_RF 4
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* EEPROM/EFUSE data structure definition.
|
||||
* ---------------------------------------------------------------------------- */
|
||||
|
||||
/* For 88E new structure */
|
||||
|
||||
/*
|
||||
2.4G:
|
||||
{
|
||||
{1,2},
|
||||
{3,4,5},
|
||||
{6,7,8},
|
||||
{9,10,11},
|
||||
{12,13},
|
||||
{14}
|
||||
}
|
||||
|
||||
5G:
|
||||
{
|
||||
{36,38,40},
|
||||
{44,46,48},
|
||||
{52,54,56},
|
||||
{60,62,64},
|
||||
{100,102,104},
|
||||
{108,110,112},
|
||||
{116,118,120},
|
||||
{124,126,128},
|
||||
{132,134,136},
|
||||
{140,142,144},
|
||||
{149,151,153},
|
||||
{157,159,161},
|
||||
{173,175,177},
|
||||
}
|
||||
*/
|
||||
#define MAX_RF_PATH 4
|
||||
#define RF_PATH_MAX MAX_RF_PATH
|
||||
#define MAX_CHNL_GROUP_24G 6
|
||||
#define MAX_CHNL_GROUP_5G 14
|
||||
|
||||
/* It must always set to 4, otherwise read efuse table sequence will be wrong. */
|
||||
#define MAX_TX_COUNT 4
|
||||
|
||||
typedef enum _BT_Ant_NUM {
|
||||
Ant_x2 = 0,
|
||||
Ant_x1 = 1
|
||||
} BT_Ant_NUM, *PBT_Ant_NUM;
|
||||
|
||||
typedef enum _BT_CoType {
|
||||
BT_2WIRE = 0,
|
||||
BT_ISSC_3WIRE = 1,
|
||||
BT_ACCEL = 2,
|
||||
BT_CSR_BC4 = 3,
|
||||
BT_CSR_BC8 = 4,
|
||||
BT_RTL8756 = 5,
|
||||
BT_RTL8723A = 6,
|
||||
BT_RTL8821 = 7,
|
||||
BT_RTL8723B = 8,
|
||||
BT_RTL8192E = 9,
|
||||
BT_RTL8814A = 10,
|
||||
BT_RTL8812A = 11,
|
||||
BT_RTL8703B = 12,
|
||||
BT_RTL8822B = 13,
|
||||
BT_RTL8723D = 14,
|
||||
BT_RTL8821C = 15,
|
||||
BT_RTL8192F = 16,
|
||||
BT_RTL8822C = 17,
|
||||
BT_RTL8814B = 18,
|
||||
BT_RTL8723F = 19,
|
||||
} BT_CoType, *PBT_CoType;
|
||||
|
||||
typedef enum _BT_RadioShared {
|
||||
BT_Radio_Shared = 0,
|
||||
BT_Radio_Individual = 1,
|
||||
} BT_RadioShared, *PBT_RadioShared;
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_PHY_H__
|
||||
#define __HAL_PHY_H__
|
||||
|
||||
|
||||
#if DISABLE_BB_RF
|
||||
#define HAL_FW_ENABLE 0
|
||||
#define HAL_MAC_ENABLE 0
|
||||
#define HAL_BB_ENABLE 0
|
||||
#define HAL_RF_ENABLE 0
|
||||
#else /* FPGA_PHY and ASIC */
|
||||
#define HAL_FW_ENABLE 1
|
||||
#define HAL_MAC_ENABLE 1
|
||||
#define HAL_BB_ENABLE 1
|
||||
#define HAL_RF_ENABLE 1
|
||||
#endif
|
||||
|
||||
#define RF6052_MAX_TX_PWR 0x3F
|
||||
#define RF6052_MAX_REG_88E 0xFF
|
||||
#define RF6052_MAX_REG_92C 0x7F
|
||||
|
||||
#define RF6052_MAX_REG \
|
||||
((RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
|
||||
|
||||
#define GET_RF6052_REAL_MAX_REG(_Adapter) \
|
||||
(IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C)
|
||||
|
||||
#define RF6052_MAX_PATH 2
|
||||
|
||||
/*
|
||||
* Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected.
|
||||
* Added by Roger, 2013.05.22.
|
||||
* */
|
||||
#define ANT_DETECT_BY_SINGLE_TONE BIT0
|
||||
#define ANT_DETECT_BY_RSSI BIT1
|
||||
#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE)
|
||||
#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI)
|
||||
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
typedef enum _RF_CHIP {
|
||||
RF_CHIP_MIN = 0, /* 0 */
|
||||
RF_8225 = 1, /* 1 11b/g RF for verification only */
|
||||
RF_8256 = 2, /* 2 11b/g/n */
|
||||
RF_8258 = 3, /* 3 11a/b/g/n RF */
|
||||
RF_6052 = 4, /* 4 11b/g/n RF */
|
||||
RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */
|
||||
RF_CHIP_MAX
|
||||
} RF_CHIP_E, *PRF_CHIP_E;
|
||||
|
||||
typedef enum _ANTENNA_PATH {
|
||||
ANTENNA_NONE = 0,
|
||||
ANTENNA_D = 1,
|
||||
ANTENNA_C = 2,
|
||||
ANTENNA_CD = 3,
|
||||
ANTENNA_B = 4,
|
||||
ANTENNA_BD = 5,
|
||||
ANTENNA_BC = 6,
|
||||
ANTENNA_BCD = 7,
|
||||
ANTENNA_A = 8,
|
||||
ANTENNA_AD = 9,
|
||||
ANTENNA_AC = 10,
|
||||
ANTENNA_ACD = 11,
|
||||
ANTENNA_AB = 12,
|
||||
ANTENNA_ABD = 13,
|
||||
ANTENNA_ABC = 14,
|
||||
ANTENNA_ABCD = 15
|
||||
} ANTENNA_PATH;
|
||||
|
||||
typedef enum _RF_CONTENT {
|
||||
radioa_txt = 0x1000,
|
||||
radiob_txt = 0x1001,
|
||||
radioc_txt = 0x1002,
|
||||
radiod_txt = 0x1003
|
||||
} RF_CONTENT;
|
||||
|
||||
typedef enum _BaseBand_Config_Type {
|
||||
BaseBand_Config_PHY_REG = 0, /* Radio Path A */
|
||||
BaseBand_Config_AGC_TAB = 1, /* Radio Path B */
|
||||
BaseBand_Config_AGC_TAB_2G = 2,
|
||||
BaseBand_Config_AGC_TAB_5G = 3,
|
||||
BaseBand_Config_PHY_REG_PG
|
||||
} BaseBand_Config_Type, *PBaseBand_Config_Type;
|
||||
|
||||
typedef enum _HW_BLOCK {
|
||||
HW_BLOCK_MAC = 0,
|
||||
HW_BLOCK_PHY0 = 1,
|
||||
HW_BLOCK_PHY1 = 2,
|
||||
HW_BLOCK_RF = 3,
|
||||
HW_BLOCK_MAXIMUM = 4, /* Never use this */
|
||||
} HW_BLOCK_E, *PHW_BLOCK_E;
|
||||
|
||||
typedef enum _WIRELESS_MODE {
|
||||
WIRELESS_MODE_UNKNOWN = 0x00,
|
||||
WIRELESS_MODE_A = 0x01,
|
||||
WIRELESS_MODE_B = 0x02,
|
||||
WIRELESS_MODE_G = 0x04,
|
||||
WIRELESS_MODE_AUTO = 0x08,
|
||||
WIRELESS_MODE_N_24G = 0x10,
|
||||
WIRELESS_MODE_N_5G = 0x20,
|
||||
WIRELESS_MODE_AC_5G = 0x40,
|
||||
WIRELESS_MODE_AC_24G = 0x80,
|
||||
WIRELESS_MODE_AC_ONLY = 0x100,
|
||||
} WIRELESS_MODE;
|
||||
|
||||
typedef enum _SwChnlCmdID {
|
||||
CmdID_End,
|
||||
CmdID_SetTxPowerLevel,
|
||||
CmdID_BBRegWrite10,
|
||||
CmdID_WritePortUlong,
|
||||
CmdID_WritePortUshort,
|
||||
CmdID_WritePortUchar,
|
||||
CmdID_RF_WriteReg,
|
||||
} SwChnlCmdID;
|
||||
|
||||
typedef struct _SwChnlCmd {
|
||||
SwChnlCmdID CmdID;
|
||||
u32 Para1;
|
||||
u32 Para2;
|
||||
u32 msDelay;
|
||||
} SwChnlCmd;
|
||||
|
||||
typedef struct _R_ANTENNA_SELECT_OFDM {
|
||||
u32 r_tx_antenna:4;
|
||||
u32 r_ant_l:4;
|
||||
u32 r_ant_non_ht:4;
|
||||
u32 r_ant_ht1:4;
|
||||
u32 r_ant_ht2:4;
|
||||
u32 r_ant_ht_s1:4;
|
||||
u32 r_ant_non_ht_s1:4;
|
||||
u32 OFDM_TXSC:2;
|
||||
u32 Reserved:2;
|
||||
} R_ANTENNA_SELECT_OFDM;
|
||||
|
||||
typedef struct _R_ANTENNA_SELECT_CCK {
|
||||
u8 r_cckrx_enable_2:2;
|
||||
u8 r_cckrx_enable:2;
|
||||
u8 r_ccktx_enable:4;
|
||||
} R_ANTENNA_SELECT_CCK;
|
||||
|
||||
|
||||
/*--------------------------Exported Function prototype---------------------*/
|
||||
u32
|
||||
PHY_CalculateBitShift(
|
||||
u32 BitMask
|
||||
);
|
||||
|
||||
#ifdef CONFIG_RF_SHADOW_RW
|
||||
typedef struct RF_Shadow_Compare_Map {
|
||||
/* Shadow register value */
|
||||
u32 Value;
|
||||
/* Compare or not flag */
|
||||
u8 Compare;
|
||||
/* Record If it had ever modified unpredicted */
|
||||
u8 ErrorOrNot;
|
||||
/* Recorver Flag */
|
||||
u8 Recorver;
|
||||
/* */
|
||||
u8 Driver_Write;
|
||||
} RF_SHADOW_T;
|
||||
|
||||
u32
|
||||
PHY_RFShadowRead(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 Offset);
|
||||
|
||||
void
|
||||
PHY_RFShadowWrite(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 Offset,
|
||||
u32 Data);
|
||||
|
||||
BOOLEAN
|
||||
PHY_RFShadowCompare(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 Offset);
|
||||
|
||||
void
|
||||
PHY_RFShadowRecorver(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 Offset);
|
||||
|
||||
void
|
||||
PHY_RFShadowCompareAll(
|
||||
PADAPTER Adapter);
|
||||
|
||||
void
|
||||
PHY_RFShadowRecorverAll(
|
||||
PADAPTER Adapter);
|
||||
|
||||
void
|
||||
PHY_RFShadowCompareFlagSet(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 Offset,
|
||||
u8 Type);
|
||||
|
||||
void
|
||||
PHY_RFShadowRecorverFlagSet(
|
||||
PADAPTER Adapter,
|
||||
enum rf_path eRFPath,
|
||||
u32 Offset,
|
||||
u8 Type);
|
||||
|
||||
void
|
||||
PHY_RFShadowCompareFlagSetAll(
|
||||
PADAPTER Adapter);
|
||||
|
||||
void
|
||||
PHY_RFShadowRecorverFlagSetAll(
|
||||
PADAPTER Adapter);
|
||||
|
||||
void
|
||||
PHY_RFShadowRefresh(
|
||||
PADAPTER Adapter);
|
||||
#endif /*#CONFIG_RF_SHADOW_RW*/
|
||||
#endif /* __HAL_COMMON_H__ */
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_PHY_REG_H__
|
||||
#define __HAL_PHY_REG_H__
|
||||
|
||||
/* for PutRFRegsetting & GetRFRegSetting BitMask*/
|
||||
#define bRFRegOffsetMask 0xfffff
|
||||
|
||||
/* alias for phydm coding style */
|
||||
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
|
||||
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
|
||||
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
|
||||
#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
|
||||
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
|
||||
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
|
||||
#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
|
||||
#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
|
||||
|
||||
#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
|
||||
#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
|
||||
#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
|
||||
#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
|
||||
#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
|
||||
#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
|
||||
#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
|
||||
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
|
||||
#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
|
||||
#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
|
||||
#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
|
||||
#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
|
||||
#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
|
||||
#define REG_IQK_AGC_CONT rIQK_AGC_Cont
|
||||
#define REG_IQK_AGC_PTS rIQK_AGC_Pts
|
||||
#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
|
||||
#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
|
||||
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
|
||||
#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
|
||||
#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
|
||||
#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
|
||||
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
|
||||
#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
|
||||
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
|
||||
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
|
||||
#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
|
||||
#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
|
||||
#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
|
||||
#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
|
||||
|
||||
/*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/
|
||||
#define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar
|
||||
/*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/
|
||||
#define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar
|
||||
#define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar
|
||||
/*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/
|
||||
#define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar
|
||||
/*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/
|
||||
#define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar
|
||||
/*#define REG_A_TX_AGC rA_TXAGC*/
|
||||
#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
|
||||
#define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar
|
||||
/*#define REG_B_BBSWING rB_BBSWING*/
|
||||
/*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/
|
||||
#define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar
|
||||
/*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/
|
||||
#define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar
|
||||
/*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/
|
||||
#define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar
|
||||
/*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/
|
||||
#define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar
|
||||
/*#define REG_B_TX_AGC rB_TXAGC*/
|
||||
#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
|
||||
#define REG_BLUE_TOOTH rBlue_Tooth
|
||||
#define REG_CCK_0_AFE_SETTING rCCK0_AFESetting
|
||||
/*#define REG_C_BBSWING rC_BBSWING*/
|
||||
/*#define REG_C_TX_AGC rC_TXAGC*/
|
||||
#define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2
|
||||
#define REG_CONFIG_ANT_A rConfig_AntA
|
||||
#define REG_CONFIG_ANT_B rConfig_AntB
|
||||
#define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA
|
||||
#define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB
|
||||
#define REG_DPDT_CONTROL rDPDT_control
|
||||
/*#define REG_D_BBSWING rD_BBSWING*/
|
||||
/*#define REG_D_TX_AGC rD_TXAGC*/
|
||||
#define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2
|
||||
#define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4
|
||||
#define REG_FPGA0_IQK rFPGA0_IQK
|
||||
#define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction
|
||||
#define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport
|
||||
#define REG_FPGA0_RFMOD rFPGA0_RFMOD
|
||||
#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
|
||||
#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
|
||||
#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
|
||||
#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
|
||||
#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
|
||||
#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
|
||||
#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
|
||||
#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
|
||||
#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
|
||||
#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
|
||||
#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
|
||||
#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
|
||||
#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
|
||||
#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
|
||||
#define REG_IQK_AGC_CONT rIQK_AGC_Cont
|
||||
#define REG_IQK_AGC_PTS rIQK_AGC_Pts
|
||||
#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
|
||||
#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
|
||||
#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
|
||||
#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
|
||||
#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
|
||||
#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
|
||||
#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
|
||||
#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
|
||||
#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
|
||||
#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
|
||||
#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
|
||||
#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
|
||||
#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
|
||||
#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
|
||||
#define REG_PMPD_ANAEN rPMPD_ANAEN
|
||||
#define REG_PDP_ANT_A rPdp_AntA
|
||||
#define REG_PDP_ANT_A_4 rPdp_AntA_4
|
||||
#define REG_PDP_ANT_B rPdp_AntB
|
||||
#define REG_PDP_ANT_B_4 rPdp_AntB_4
|
||||
#define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar
|
||||
#define REG_RX_CCK rRx_CCK
|
||||
#define REG_RX_IQK rRx_IQK
|
||||
#define REG_RX_IQK_PI_A rRx_IQK_PI_A
|
||||
#define REG_RX_IQK_PI_B rRx_IQK_PI_B
|
||||
#define REG_RX_IQK_TONE_A rRx_IQK_Tone_A
|
||||
#define REG_RX_IQK_TONE_B rRx_IQK_Tone_B
|
||||
#define REG_RX_OFDM rRx_OFDM
|
||||
#define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2
|
||||
#define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2
|
||||
#define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2
|
||||
#define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2
|
||||
#define REG_RX_TO_RX rRx_TO_Rx
|
||||
#define REG_RX_WAIT_CCA rRx_Wait_CCA
|
||||
#define REG_RX_WAIT_RIFS rRx_Wait_RIFS
|
||||
#define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch
|
||||
/*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/
|
||||
#define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar
|
||||
/*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/
|
||||
#define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar
|
||||
#define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL
|
||||
#define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar
|
||||
#define REG_SLEEP rSleep
|
||||
#define REG_STANDBY rStandby
|
||||
#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar
|
||||
#define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32
|
||||
#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar
|
||||
#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar
|
||||
#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar
|
||||
#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar
|
||||
#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar
|
||||
#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar
|
||||
#define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00
|
||||
#define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04
|
||||
#define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08
|
||||
#define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12
|
||||
#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
|
||||
#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
|
||||
#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
|
||||
#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
|
||||
#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
|
||||
#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
|
||||
#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
|
||||
#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
|
||||
#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar
|
||||
#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar
|
||||
#define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06
|
||||
#define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24
|
||||
#define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11
|
||||
#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar
|
||||
#define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32
|
||||
#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar
|
||||
#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar
|
||||
#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar
|
||||
#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar
|
||||
#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar
|
||||
#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar
|
||||
#define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00
|
||||
#define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04
|
||||
#define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08
|
||||
#define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12
|
||||
#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
|
||||
#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
|
||||
#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
|
||||
#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
|
||||
#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
|
||||
#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
|
||||
#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
|
||||
#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
|
||||
#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar
|
||||
#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar
|
||||
#define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06
|
||||
#define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24
|
||||
#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar
|
||||
#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar
|
||||
#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar
|
||||
#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar
|
||||
#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar
|
||||
#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar
|
||||
#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar
|
||||
#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
|
||||
#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
|
||||
#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
|
||||
#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
|
||||
#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
|
||||
#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
|
||||
#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
|
||||
#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
|
||||
#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar
|
||||
#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar
|
||||
#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar
|
||||
#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar
|
||||
#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar
|
||||
#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar
|
||||
#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar
|
||||
#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar
|
||||
#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar
|
||||
#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
|
||||
#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
|
||||
#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
|
||||
#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
|
||||
#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
|
||||
#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
|
||||
#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
|
||||
#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
|
||||
#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar
|
||||
#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar
|
||||
#define REG_TX_PATH_JAGUAR rTxPath_Jaguar
|
||||
#define REG_TX_CCK_BBON rTx_CCK_BBON
|
||||
#define REG_TX_CCK_RFON rTx_CCK_RFON
|
||||
#define REG_TX_IQK rTx_IQK
|
||||
#define REG_TX_IQK_PI_A rTx_IQK_PI_A
|
||||
#define REG_TX_IQK_PI_B rTx_IQK_PI_B
|
||||
#define REG_TX_IQK_TONE_A rTx_IQK_Tone_A
|
||||
#define REG_TX_IQK_TONE_B rTx_IQK_Tone_B
|
||||
#define REG_TX_OFDM_BBON rTx_OFDM_BBON
|
||||
#define REG_TX_OFDM_RFON rTx_OFDM_RFON
|
||||
#define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A
|
||||
#define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B
|
||||
#define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A
|
||||
#define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B
|
||||
#define REG_TX_TO_RX rTx_To_Rx
|
||||
#define REG_TX_TO_TX rTx_To_Tx
|
||||
#define REG_APK rAPK
|
||||
#define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar
|
||||
|
||||
#define rf_welut_jaguar RF_WeLut_Jaguar
|
||||
#define rf_mode_table_addr RF_ModeTableAddr
|
||||
#define rf_mode_table_data0 RF_ModeTableData0
|
||||
#define rf_mode_table_data1 RF_ModeTableData1
|
||||
|
||||
#define RX_SMOOTH_FACTOR Rx_Smooth_Factor
|
||||
|
||||
#endif /* __HAL_PHY_REG_H__ */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __HAL_SDIO_H_
|
||||
#define __HAL_SDIO_H_
|
||||
|
||||
#define ffaddr2deviceId(pdvobj, addr) (pdvobj->Queue2Pipe[addr])
|
||||
|
||||
#ifndef RTW_HALMAC
|
||||
extern const char *_sdio_tx_queue_str[];
|
||||
#define sdio_tx_queue_str(_page_idx) (_page_idx >= SDIO_MAX_TX_QUEUE ? "UNKNOWN" : _sdio_tx_queue_str[_page_idx])
|
||||
#endif
|
||||
|
||||
u8 rtw_hal_sdio_max_txoqt_free_space(_adapter *padapter);
|
||||
u8 rtw_hal_sdio_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
|
||||
void rtw_hal_sdio_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum);
|
||||
void rtw_hal_set_sdio_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ, u8 div_num);
|
||||
u32 rtw_hal_get_sdio_tx_max_length(PADAPTER padapter, u8 queue_idx);
|
||||
bool sdio_power_on_check(PADAPTER padapter);
|
||||
|
||||
#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
|
||||
#if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) ||defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723D)
|
||||
void rtw_hal_sdio_avail_page_threshold_init(_adapter *adapter);
|
||||
void rtw_hal_sdio_avail_page_threshold_en(_adapter *adapter, u8 qidx, u8 pg_num);
|
||||
#endif
|
||||
#endif /* CONFIG_SDIO_TX_ENABLE_AVAL_INT */
|
||||
|
||||
#ifdef CONFIG_FW_C2H_REG
|
||||
void sd_c2h_hisr_hdl(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8188F) || defined (CONFIG_RTL8188GTV) || defined (CONFIG_RTL8192F) || defined(CONFIG_RTL8723D)
|
||||
#define SDIO_LOCAL_CMD_ADDR(addr) ((SDIO_LOCAL_DEVICE_ID << 13) | ((addr) & SDIO_LOCAL_MSK))
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_CHK_HCI_RESUME
|
||||
bool sdio_chk_hci_resume(struct intf_hdl *pintfhdl);
|
||||
void sdio_chk_hci_suspend(struct intf_hdl *pintfhdl);
|
||||
#else
|
||||
#define sdio_chk_hci_resume(pintfhdl) _FALSE
|
||||
#define sdio_chk_hci_suspend(pintfhdl) do {} while (0)
|
||||
#endif /* CONFIG_SDIO_CHK_HCI_RESUME */
|
||||
|
||||
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
|
||||
/* program indirect access register in sdio local to read/write page0 registers */
|
||||
s32 sdio_iread(PADAPTER padapter, u32 addr, u8 size, u8 *v);
|
||||
s32 sdio_iwrite(PADAPTER padapter, u32 addr, u8 size, u8 *v);
|
||||
u8 sdio_iread8(struct intf_hdl *pintfhdl, u32 addr);
|
||||
u16 sdio_iread16(struct intf_hdl *pintfhdl, u32 addr);
|
||||
u32 sdio_iread32(struct intf_hdl *pintfhdl, u32 addr);
|
||||
s32 sdio_iwrite8(struct intf_hdl *pintfhdl, u32 addr, u8 val);
|
||||
s32 sdio_iwrite16(struct intf_hdl *pintfhdl, u32 addr, u16 val);
|
||||
s32 sdio_iwrite32(struct intf_hdl *pintfhdl, u32 addr, u32 val);
|
||||
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
|
||||
u32 cmd53_4byte_alignment(struct intf_hdl *pintfhdl, u32 addr);
|
||||
|
||||
#ifndef CONFIG_SDIO_TX_TASKLET
|
||||
#ifdef SDIO_FREE_XMIT_BUF_SEMA
|
||||
void _rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit);
|
||||
void _rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit);
|
||||
#ifdef DBG_SDIO_FREE_XMIT_BUF_SEMA
|
||||
void dbg_rtw_sdio_free_xmitbuf_sema_up(struct xmit_priv *xmit, const char *caller);
|
||||
void dbg_rtw_sdio_free_xmitbuf_sema_down(struct xmit_priv *xmit, const char *caller);
|
||||
#define rtw_sdio_free_xmitbuf_sema_up(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_up(_xmit, __func__)
|
||||
#define rtw_sdio_free_xmitbuf_sema_down(_xmit) dbg_rtw_sdio_free_xmitbuf_sema_down(_xmit, __func__)
|
||||
#else
|
||||
#define rtw_sdio_free_xmitbuf_sema_up(_xmit) _rtw_sdio_free_xmitbuf_sema_up(_xmit)
|
||||
#define rtw_sdio_free_xmitbuf_sema_down(_xmit) _rtw_sdio_free_xmitbuf_sema_down(_xmit)
|
||||
#endif /* DBG_SDIO_FREE_XMIT_BUF_SEMA */
|
||||
#endif /* SDIO_FREE_XMIT_BUF_SEMA */
|
||||
#endif /* !CONFIG_SDIO_TX_TASKLET */
|
||||
|
||||
s32 sdio_initrecvbuf(struct recv_buf *recvbuf, _adapter *adapter);
|
||||
void sdio_freerecvbuf(struct recv_buf *recvbuf);
|
||||
|
||||
#ifdef CONFIG_SDIO_RECVBUF_PWAIT
|
||||
void dump_recvbuf_pwait_conf(void *sel, struct recv_priv *recvpriv);
|
||||
#ifdef CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST
|
||||
int recvbuf_pwait_config_req(struct recv_priv *recvpriv, enum rtw_pwait_type type, s32 time, s32 cnt_lmt);
|
||||
int recvbuf_pwait_config_hdl(struct recv_priv *recvpriv, struct recv_buf *rbuf);
|
||||
#endif /* CONFIG_SDIO_RECVBUF_PWAIT_RUNTIME_ADJUST */
|
||||
#endif /* CONFIG_SDIO_RECVBUF_PWAIT */
|
||||
|
||||
#endif /* __HAL_SDIO_H_ */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2013 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __HAL_SDIO_COEX_H__
|
||||
#define __HAL_SDIO_COEX_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
#ifdef CONFIG_SDIO_MULTI_FUNCTION_COEX
|
||||
|
||||
enum { /* for sdio multi-func. coex */
|
||||
SDIO_MULTI_WIFI = 0,
|
||||
SDIO_MULTI_BT,
|
||||
SDIO_MULTI_NUM
|
||||
};
|
||||
|
||||
bool ex_hal_sdio_multi_if_bus_available(PADAPTER adapter);
|
||||
|
||||
#else
|
||||
|
||||
#define ex_hal_sdio_multi_if_bus_available(adapter) TRUE
|
||||
|
||||
#endif /* CONFIG_SDIO_MULTI_FUNCTION_COEX */
|
||||
#endif /* !__HAL_SDIO_COEX_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,312 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __IEEE80211_EXT_H
|
||||
#define __IEEE80211_EXT_H
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
#define WMM_OUI_TYPE 2
|
||||
#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0
|
||||
#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1
|
||||
#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2
|
||||
#define WMM_VERSION 1
|
||||
|
||||
#define WPA_PROTO_WPA BIT(0)
|
||||
#define WPA_PROTO_RSN BIT(1)
|
||||
|
||||
#define WPA_KEY_MGMT_IEEE8021X BIT(0)
|
||||
#define WPA_KEY_MGMT_PSK BIT(1)
|
||||
#define WPA_KEY_MGMT_NONE BIT(2)
|
||||
#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3)
|
||||
#define WPA_KEY_MGMT_WPA_NONE BIT(4)
|
||||
|
||||
|
||||
#define WPA_CAPABILITY_PREAUTH BIT(0)
|
||||
#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6)
|
||||
#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9)
|
||||
|
||||
|
||||
#define PMKID_LEN 16
|
||||
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
struct wpa_ie_hdr {
|
||||
u8 elem_id;
|
||||
u8 len;
|
||||
u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */
|
||||
u8 version[2]; /* little endian */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct rsn_ie_hdr {
|
||||
u8 elem_id; /* WLAN_EID_RSN */
|
||||
u8 len;
|
||||
u8 version[2]; /* little endian */
|
||||
} __attribute__((packed));
|
||||
|
||||
struct wme_ac_parameter {
|
||||
#if defined(CONFIG_LITTLE_ENDIAN)
|
||||
/* byte 1 */
|
||||
u8 aifsn:4,
|
||||
acm:1,
|
||||
aci:2,
|
||||
reserved:1;
|
||||
|
||||
/* byte 2 */
|
||||
u8 eCWmin:4,
|
||||
eCWmax:4;
|
||||
#elif defined(CONFIG_BIG_ENDIAN)
|
||||
/* byte 1 */
|
||||
u8 reserved:1,
|
||||
aci:2,
|
||||
acm:1,
|
||||
aifsn:4;
|
||||
|
||||
/* byte 2 */
|
||||
u8 eCWmax:4,
|
||||
eCWmin:4;
|
||||
#else
|
||||
#error "Please fix <endian.h>"
|
||||
#endif
|
||||
|
||||
/* bytes 3 & 4 */
|
||||
u16 txopLimit;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct wme_parameter_element {
|
||||
/* required fields for WME version 1 */
|
||||
u8 oui[3];
|
||||
u8 oui_type;
|
||||
u8 oui_subtype;
|
||||
u8 version;
|
||||
u8 acInfo;
|
||||
u8 reserved;
|
||||
struct wme_ac_parameter ac[4];
|
||||
|
||||
} __attribute__((packed));
|
||||
|
||||
#endif
|
||||
|
||||
#define WPA_PUT_LE16(a, val) \
|
||||
do { \
|
||||
(a)[1] = ((u16) (val)) >> 8; \
|
||||
(a)[0] = ((u16) (val)) & 0xff; \
|
||||
} while (0)
|
||||
|
||||
#define WPA_PUT_BE32(a, val) \
|
||||
do { \
|
||||
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
|
||||
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
|
||||
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
|
||||
(a)[3] = (u8) (((u32) (val)) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define WPA_PUT_LE32(a, val) \
|
||||
do { \
|
||||
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
|
||||
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
|
||||
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
|
||||
(a)[0] = (u8) (((u32) (val)) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val))
|
||||
/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */
|
||||
|
||||
|
||||
|
||||
/* Action category code */
|
||||
enum ieee80211_category {
|
||||
WLAN_CATEGORY_SPECTRUM_MGMT = 0,
|
||||
WLAN_CATEGORY_QOS = 1,
|
||||
WLAN_CATEGORY_DLS = 2,
|
||||
WLAN_CATEGORY_BACK = 3,
|
||||
WLAN_CATEGORY_HT = 7,
|
||||
WLAN_CATEGORY_WMM = 17,
|
||||
};
|
||||
|
||||
/* SPECTRUM_MGMT action code */
|
||||
enum ieee80211_spectrum_mgmt_actioncode {
|
||||
WLAN_ACTION_SPCT_MSR_REQ = 0,
|
||||
WLAN_ACTION_SPCT_MSR_RPRT = 1,
|
||||
WLAN_ACTION_SPCT_TPC_REQ = 2,
|
||||
WLAN_ACTION_SPCT_TPC_RPRT = 3,
|
||||
WLAN_ACTION_SPCT_CHL_SWITCH = 4,
|
||||
WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5,
|
||||
};
|
||||
|
||||
/* BACK action code */
|
||||
enum ieee80211_back_actioncode {
|
||||
WLAN_ACTION_ADDBA_REQ = 0,
|
||||
WLAN_ACTION_ADDBA_RESP = 1,
|
||||
WLAN_ACTION_DELBA = 2,
|
||||
};
|
||||
|
||||
/* HT features action code */
|
||||
enum ieee80211_ht_actioncode {
|
||||
WLAN_ACTION_NOTIFY_CH_WIDTH = 0,
|
||||
WLAN_ACTION_SM_PS = 1,
|
||||
WLAN_ACTION_PSPM = 2,
|
||||
WLAN_ACTION_PCO_PHASE = 3,
|
||||
WLAN_ACTION_MIMO_CSI_MX = 4,
|
||||
WLAN_ACTION_MIMO_NONCP_BF = 5,
|
||||
WLAN_ACTION_MIMP_CP_BF = 6,
|
||||
WLAN_ACTION_ASEL_INDICATES_FB = 7,
|
||||
WLAN_ACTION_HI_INFO_EXCHG = 8,
|
||||
};
|
||||
|
||||
/* BACK (block-ack) parties */
|
||||
enum ieee80211_back_parties {
|
||||
WLAN_BACK_RECIPIENT = 0,
|
||||
WLAN_BACK_INITIATOR = 1,
|
||||
WLAN_BACK_TIMER = 2,
|
||||
};
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
|
||||
struct ieee80211_mgmt {
|
||||
u16 frame_control;
|
||||
u16 duration;
|
||||
u8 da[6];
|
||||
u8 sa[6];
|
||||
u8 bssid[6];
|
||||
u16 seq_ctrl;
|
||||
union {
|
||||
struct {
|
||||
u16 auth_alg;
|
||||
u16 auth_transaction;
|
||||
u16 status_code;
|
||||
/* possibly followed by Challenge text */
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) auth;
|
||||
struct {
|
||||
u16 reason_code;
|
||||
} __attribute__((packed)) deauth;
|
||||
struct {
|
||||
u16 capab_info;
|
||||
u16 listen_interval;
|
||||
/* followed by SSID and Supported rates */
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) assoc_req;
|
||||
struct {
|
||||
u16 capab_info;
|
||||
u16 status_code;
|
||||
u16 aid;
|
||||
/* followed by Supported rates */
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) assoc_resp, reassoc_resp;
|
||||
struct {
|
||||
u16 capab_info;
|
||||
u16 listen_interval;
|
||||
u8 current_ap[6];
|
||||
/* followed by SSID and Supported rates */
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) reassoc_req;
|
||||
struct {
|
||||
u16 reason_code;
|
||||
} __attribute__((packed)) disassoc;
|
||||
struct {
|
||||
__le64 timestamp;
|
||||
u16 beacon_int;
|
||||
u16 capab_info;
|
||||
/* followed by some of SSID, Supported rates,
|
||||
* FH Params, DS Params, CF Params, IBSS Params, TIM */
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) beacon;
|
||||
struct {
|
||||
/* only variable items: SSID, Supported rates */
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) probe_req;
|
||||
struct {
|
||||
__le64 timestamp;
|
||||
u16 beacon_int;
|
||||
u16 capab_info;
|
||||
/* followed by some of SSID, Supported rates,
|
||||
* FH Params, DS Params, CF Params, IBSS Params */
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) probe_resp;
|
||||
struct {
|
||||
u8 category;
|
||||
union {
|
||||
struct {
|
||||
u8 action_code;
|
||||
u8 dialog_token;
|
||||
u8 status_code;
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) wme_action;
|
||||
#if 0
|
||||
struct {
|
||||
u8 action_code;
|
||||
u8 element_id;
|
||||
u8 length;
|
||||
struct ieee80211_channel_sw_ie sw_elem;
|
||||
} __attribute__((packed)) chan_switch;
|
||||
struct {
|
||||
u8 action_code;
|
||||
u8 dialog_token;
|
||||
u8 element_id;
|
||||
u8 length;
|
||||
struct ieee80211_msrment_ie msr_elem;
|
||||
} __attribute__((packed)) measurement;
|
||||
#endif
|
||||
struct {
|
||||
u8 action_code;
|
||||
u8 dialog_token;
|
||||
u16 capab;
|
||||
u16 timeout;
|
||||
u16 start_seq_num;
|
||||
} __attribute__((packed)) addba_req;
|
||||
struct {
|
||||
u8 action_code;
|
||||
u8 dialog_token;
|
||||
u16 status;
|
||||
u16 capab;
|
||||
u16 timeout;
|
||||
} __attribute__((packed)) addba_resp;
|
||||
struct {
|
||||
u8 action_code;
|
||||
u16 params;
|
||||
u16 reason_code;
|
||||
} __attribute__((packed)) delba;
|
||||
struct {
|
||||
u8 action_code;
|
||||
/* capab_info for open and confirm,
|
||||
* reason for close
|
||||
*/
|
||||
u16 aux;
|
||||
/* Followed in plink_confirm by status
|
||||
* code, AID and supported rates,
|
||||
* and directly by supported rates in
|
||||
* plink_open and plink_close
|
||||
*/
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) plink_action;
|
||||
struct {
|
||||
u8 action_code;
|
||||
u8 variable[0];
|
||||
} __attribute__((packed)) mesh_action;
|
||||
} __attribute__((packed)) u;
|
||||
} __attribute__((packed)) action;
|
||||
} __attribute__((packed)) u;
|
||||
} __attribute__((packed));
|
||||
|
||||
#endif
|
||||
|
||||
/* mgmt header + 1 byte category code */
|
||||
#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u)
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef _LINUX_IF_ETHER_H
|
||||
#define _LINUX_IF_ETHER_H
|
||||
|
||||
/*
|
||||
* IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble
|
||||
* and FCS/CRC (frame check sequence).
|
||||
*/
|
||||
|
||||
#define ETH_ALEN 6 /* Octets in one ethernet addr */
|
||||
#define ETH_HLEN 14 /* Total octets in header. */
|
||||
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
|
||||
#define ETH_DATA_LEN 1500 /* Max. octets in payload */
|
||||
#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */
|
||||
|
||||
/*
|
||||
* These are the defined Ethernet Protocol ID's.
|
||||
*/
|
||||
|
||||
#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */
|
||||
#define ETH_P_PUP 0x0200 /* Xerox PUP packet */
|
||||
#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */
|
||||
#define ETH_P_IP 0x0800 /* Internet Protocol packet */
|
||||
#define ETH_P_X25 0x0805 /* CCITT X.25 */
|
||||
#define ETH_P_ARP 0x0806 /* Address Resolution packet */
|
||||
#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */
|
||||
#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */
|
||||
#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */
|
||||
#define ETH_P_DEC 0x6000 /* DEC Assigned proto */
|
||||
#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */
|
||||
#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */
|
||||
#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */
|
||||
#define ETH_P_LAT 0x6004 /* DEC LAT */
|
||||
#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */
|
||||
#define ETH_P_CUST 0x6006 /* DEC Customer use */
|
||||
#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */
|
||||
#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */
|
||||
#define ETH_P_ATALK 0x809B /* Appletalk DDP */
|
||||
#define ETH_P_AARP 0x80F3 /* Appletalk AARP */
|
||||
#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
|
||||
#define ETH_P_IPX 0x8137 /* IPX over DIX */
|
||||
#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */
|
||||
#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */
|
||||
#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */
|
||||
#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */
|
||||
#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport
|
||||
* over Ethernet
|
||||
*/
|
||||
|
||||
/*
|
||||
* Non DIX types. Won't clash for 1500 types.
|
||||
*/
|
||||
|
||||
#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */
|
||||
#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */
|
||||
#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */
|
||||
#define ETH_P_802_2 0x0004 /* 802.2 frames */
|
||||
#define ETH_P_SNAP 0x0005 /* Internal only */
|
||||
#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */
|
||||
#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/
|
||||
#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */
|
||||
#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */
|
||||
#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/
|
||||
#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */
|
||||
#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */
|
||||
#define ETH_P_CONTROL 0x0016 /* Card specific control frames */
|
||||
#define ETH_P_IRDA 0x0017 /* Linux-IrDA */
|
||||
#define ETH_P_ECONET 0x0018 /* Acorn Econet */
|
||||
|
||||
/*
|
||||
* This is an Ethernet frame header.
|
||||
*/
|
||||
|
||||
struct ethhdr {
|
||||
unsigned char h_dest[ETH_ALEN]; /* destination eth addr */
|
||||
unsigned char h_source[ETH_ALEN]; /* source ether addr */
|
||||
unsigned short h_proto; /* packet type ID field */
|
||||
};
|
||||
|
||||
struct _vlan {
|
||||
unsigned short h_vlan_TCI; /* Encapsulates priority and VLAN ID */
|
||||
unsigned short h_vlan_encapsulated_proto;
|
||||
};
|
||||
|
||||
|
||||
|
||||
#define get_vlan_id(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI)) & 0xfff)
|
||||
#define get_vlan_priority(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI))>>13)
|
||||
#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short)pvlan->h_vlan_encapsulated_proto))
|
||||
|
||||
|
||||
#endif /* _LINUX_IF_ETHER_H */
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _LINUX_IP_H
|
||||
#define _LINUX_IP_H
|
||||
|
||||
/* SOL_IP socket options */
|
||||
|
||||
#define IPTOS_TOS_MASK 0x1E
|
||||
#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK)
|
||||
#define IPTOS_LOWDELAY 0x10
|
||||
#define IPTOS_THROUGHPUT 0x08
|
||||
#define IPTOS_RELIABILITY 0x04
|
||||
#define IPTOS_MINCOST 0x02
|
||||
|
||||
#define IPTOS_PREC_MASK 0xE0
|
||||
#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK)
|
||||
#define IPTOS_PREC_NETCONTROL 0xe0
|
||||
#define IPTOS_PREC_INTERNETCONTROL 0xc0
|
||||
#define IPTOS_PREC_CRITIC_ECP 0xa0
|
||||
#define IPTOS_PREC_FLASHOVERRIDE 0x80
|
||||
#define IPTOS_PREC_FLASH 0x60
|
||||
#define IPTOS_PREC_IMMEDIATE 0x40
|
||||
#define IPTOS_PREC_PRIORITY 0x20
|
||||
#define IPTOS_PREC_ROUTINE 0x00
|
||||
|
||||
|
||||
/* IP options */
|
||||
#define IPOPT_COPY 0x80
|
||||
#define IPOPT_CLASS_MASK 0x60
|
||||
#define IPOPT_NUMBER_MASK 0x1f
|
||||
|
||||
#define IPOPT_COPIED(o) ((o)&IPOPT_COPY)
|
||||
#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK)
|
||||
#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK)
|
||||
|
||||
#define IPOPT_CONTROL 0x00
|
||||
#define IPOPT_RESERVED1 0x20
|
||||
#define IPOPT_MEASUREMENT 0x40
|
||||
#define IPOPT_RESERVED2 0x60
|
||||
|
||||
#define IPOPT_END (0 | IPOPT_CONTROL)
|
||||
#define IPOPT_NOOP (1 | IPOPT_CONTROL)
|
||||
#define IPOPT_SEC (2 | IPOPT_CONTROL | IPOPT_COPY)
|
||||
#define IPOPT_LSRR (3 | IPOPT_CONTROL | IPOPT_COPY)
|
||||
#define IPOPT_TIMESTAMP (4 | IPOPT_MEASUREMENT)
|
||||
#define IPOPT_RR (7 | IPOPT_CONTROL)
|
||||
#define IPOPT_SID (8 | IPOPT_CONTROL | IPOPT_COPY)
|
||||
#define IPOPT_SSRR (9 | IPOPT_CONTROL | IPOPT_COPY)
|
||||
#define IPOPT_RA (20 | IPOPT_CONTROL | IPOPT_COPY)
|
||||
|
||||
#define IPVERSION 4
|
||||
#define MAXTTL 255
|
||||
#define IPDEFTTL 64
|
||||
|
||||
/* struct timestamp, struct route and MAX_ROUTES are removed.
|
||||
|
||||
REASONS: it is clear that nobody used them because:
|
||||
- MAX_ROUTES value was wrong.
|
||||
- "struct route" was wrong.
|
||||
- "struct timestamp" had fatally misaligned bitfields and was completely unusable.
|
||||
*/
|
||||
|
||||
#define IPOPT_OPTVAL 0
|
||||
#define IPOPT_OLEN 1
|
||||
#define IPOPT_OFFSET 2
|
||||
#define IPOPT_MINOFF 4
|
||||
#define MAX_IPOPTLEN 40
|
||||
#define IPOPT_NOP IPOPT_NOOP
|
||||
#define IPOPT_EOL IPOPT_END
|
||||
#define IPOPT_TS IPOPT_TIMESTAMP
|
||||
|
||||
#define IPOPT_TS_TSONLY 0 /* timestamps only */
|
||||
#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */
|
||||
#define IPOPT_TS_PRESPEC 3 /* specified modules only */
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
|
||||
struct ip_options {
|
||||
__u32 faddr; /* Saved first hop address */
|
||||
unsigned char optlen;
|
||||
unsigned char srr;
|
||||
unsigned char rr;
|
||||
unsigned char ts;
|
||||
unsigned char is_setbyuser:1, /* Set by setsockopt? */
|
||||
is_data:1, /* Options in __data, rather than skb */
|
||||
is_strictroute:1, /* Strict source route */
|
||||
srr_is_hit:1, /* Packet destination addr was our one */
|
||||
is_changed:1, /* IP checksum more not valid */
|
||||
rr_needaddr:1, /* Need to record addr of outgoing dev */
|
||||
ts_needtime:1, /* Need to record timestamp */
|
||||
ts_needaddr:1; /* Need to record addr of outgoing dev */
|
||||
unsigned char router_alert;
|
||||
unsigned char __pad1;
|
||||
unsigned char __pad2;
|
||||
unsigned char __data[0];
|
||||
};
|
||||
|
||||
#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
|
||||
#endif
|
||||
|
||||
struct iphdr {
|
||||
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||||
__u8 ihl:4,
|
||||
version:4;
|
||||
#elif defined (__BIG_ENDIAN_BITFIELD)
|
||||
__u8 version:4,
|
||||
ihl:4;
|
||||
#else
|
||||
#error "Please fix <asm/byteorder.h>"
|
||||
#endif
|
||||
__u8 tos;
|
||||
__u16 tot_len;
|
||||
__u16 id;
|
||||
__u16 frag_off;
|
||||
__u8 ttl;
|
||||
__u8 protocol;
|
||||
__u16 check;
|
||||
__u32 saddr;
|
||||
__u32 daddr;
|
||||
/*The options start here. */
|
||||
};
|
||||
|
||||
#endif /* _LINUX_IP_H */
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __MLME_OSDEP_H_
|
||||
#define __MLME_OSDEP_H_
|
||||
|
||||
extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated);
|
||||
extern void rtw_os_indicate_connect(_adapter *adapter);
|
||||
void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted);
|
||||
extern void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie);
|
||||
|
||||
void rtw_reset_securitypriv(_adapter *adapter);
|
||||
|
||||
#endif /* _MLME_OSDEP_H_ */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
#ifndef __NIC_SPEC_H__
|
||||
#define __NIC_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
#define RTL8711_MCTRL_ (0x20000)
|
||||
#define RTL8711_UART_ (0x30000)
|
||||
#define RTL8711_TIMER_ (0x40000)
|
||||
#define RTL8711_FINT_ (0x50000)
|
||||
#define RTL8711_HINT_ (0x50000)
|
||||
#define RTL8711_GPIO_ (0x60000)
|
||||
#define RTL8711_WLANCTRL_ (0x200000)
|
||||
#define RTL8711_WLANFF_ (0xe00000)
|
||||
#define RTL8711_HCICTRL_ (0x600000)
|
||||
#define RTL8711_SYSCFG_ (0x620000)
|
||||
#define RTL8711_SYSCTRL_ (0x620000)
|
||||
#define RTL8711_MCCTRL_ (0x020000)
|
||||
|
||||
|
||||
#include <rtl8711_regdef.h>
|
||||
|
||||
#include <rtl8711_bitdef.h>
|
||||
|
||||
|
||||
#endif /* __RTL8711_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __OSDEP_INTF_H_
|
||||
#define __OSDEP_INTF_H_
|
||||
|
||||
|
||||
struct intf_priv {
|
||||
|
||||
u8 *intf_dev;
|
||||
u32 max_iosz; /* USB2.0: 128, USB1.1: 64, SDIO:64 */
|
||||
u32 max_xmitsz; /* USB2.0: unlimited, SDIO:512 */
|
||||
u32 max_recvsz; /* USB2.0: unlimited, SDIO:512 */
|
||||
|
||||
volatile u8 *io_rwmem;
|
||||
volatile u8 *allocated_io_rwmem;
|
||||
u32 io_wsz; /* unit: 4bytes */
|
||||
u32 io_rsz;/* unit: 4bytes */
|
||||
u8 intf_status;
|
||||
|
||||
void (*_bus_io)(u8 *priv);
|
||||
|
||||
/*
|
||||
Under Sync. IRP (SDIO/USB)
|
||||
A protection mechanism is necessary for the io_rwmem(read/write protocol)
|
||||
|
||||
Under Async. IRP (SDIO/USB)
|
||||
The protection mechanism is through the pending queue.
|
||||
*/
|
||||
|
||||
_mutex ioctl_mutex;
|
||||
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#ifdef CONFIG_USB_HCI
|
||||
/* when in USB, IO is through interrupt in/out endpoints */
|
||||
struct usb_device *udev;
|
||||
PURB piorw_urb;
|
||||
u8 io_irp_cnt;
|
||||
u8 bio_irp_pending;
|
||||
_sema io_retevt;
|
||||
_timer io_timer;
|
||||
u8 bio_irp_timeout;
|
||||
u8 bio_timer_cancel;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
struct dvobj_priv *devobj_init(void);
|
||||
void devobj_deinit(struct dvobj_priv *pdvobj);
|
||||
|
||||
u8 rtw_init_drv_sw(_adapter *padapter);
|
||||
u8 rtw_free_drv_sw(_adapter *padapter);
|
||||
u8 rtw_reset_drv_sw(_adapter *padapter);
|
||||
void rtw_dev_unload(PADAPTER padapter);
|
||||
|
||||
u32 rtw_start_drv_threads(_adapter *padapter);
|
||||
void rtw_stop_drv_threads(_adapter *padapter);
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
void rtw_cancel_dynamic_chk_timer(_adapter *padapter);
|
||||
#endif
|
||||
void rtw_cancel_all_timer(_adapter *padapter);
|
||||
|
||||
uint loadparam(_adapter *adapter);
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
|
||||
|
||||
int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
|
||||
struct net_device *rtw_init_netdev(_adapter *padapter);
|
||||
|
||||
void rtw_os_ndev_free(_adapter *adapter);
|
||||
int rtw_os_ndev_init(_adapter *adapter, const char *name);
|
||||
void rtw_os_ndev_deinit(_adapter *adapter);
|
||||
void rtw_os_ndev_unregister(_adapter *adapter);
|
||||
void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj);
|
||||
int rtw_os_ndevs_init(struct dvobj_priv *dvobj);
|
||||
void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj);
|
||||
|
||||
u16 rtw_os_recv_select_queue(u8 *msdu, enum rtw_rx_llc_hdl llc_hdl);
|
||||
|
||||
int rtw_ndev_notifier_register(void);
|
||||
void rtw_ndev_notifier_unregister(void);
|
||||
void rtw_inetaddr_notifier_register(void);
|
||||
void rtw_inetaddr_notifier_unregister(void);
|
||||
|
||||
#include "../os_dep/linux/rtw_proc.h"
|
||||
#include "../os_dep/linux/nlrtw.h"
|
||||
#ifdef CONFIG_PLATFORM_CMAP_INTFS
|
||||
#include "../os_dep/linux/custom_multiap_intfs/custom_multiap_intfs.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IOCTL_CFG80211
|
||||
#include "../os_dep/linux/ioctl_cfg80211.h"
|
||||
#endif /* CONFIG_IOCTL_CFG80211 */
|
||||
|
||||
u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj);
|
||||
void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl);
|
||||
|
||||
#endif /* PLATFORM_LINUX */
|
||||
|
||||
|
||||
#ifdef PLATFORM_FREEBSD
|
||||
extern int rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
|
||||
#endif
|
||||
|
||||
void rtw_ips_dev_unload(_adapter *padapter);
|
||||
|
||||
#ifdef CONFIG_IPS
|
||||
int rtw_ips_pwr_up(_adapter *padapter);
|
||||
void rtw_ips_pwr_down(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
struct _io_ops;
|
||||
struct dvobj_priv;
|
||||
_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter, struct _io_ops *pops));
|
||||
void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj);
|
||||
void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj);
|
||||
#endif
|
||||
|
||||
void rtw_ndev_destructor(_nic_hdl ndev);
|
||||
#ifdef CONFIG_ARP_KEEP_ALIVE
|
||||
int rtw_gw_addr_query(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
int rtw_suspend_common(_adapter *padapter);
|
||||
int rtw_resume_common(_adapter *padapter);
|
||||
|
||||
#endif /* _OSDEP_INTF_H_ */
|
||||
|
|
@ -0,0 +1,887 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __OSDEP_SERVICE_H_
|
||||
#define __OSDEP_SERVICE_H_
|
||||
|
||||
|
||||
#define _FAIL 0
|
||||
#define _SUCCESS 1
|
||||
#define RTW_RX_HANDLED 2
|
||||
#define RTW_RFRAME_UNAVAIL 3
|
||||
#define RTW_RFRAME_PKT_UNAVAIL 4
|
||||
#define RTW_RBUF_UNAVAIL 5
|
||||
#define RTW_RBUF_PKT_UNAVAIL 6
|
||||
#define RTW_SDIO_READ_PORT_FAIL 7
|
||||
#define RTW_ALREADY 8
|
||||
#define RTW_RA_RESOLVING 9
|
||||
#define RTW_BMC_NO_NEED 10
|
||||
#define RTW_XBUF_UNAVAIL 11
|
||||
#define RTW_TX_BALANCE 12
|
||||
#define RTW_TX_WAIT_MORE_FRAME 13
|
||||
#define RTW_QUEUE_MGMT 14
|
||||
|
||||
/* #define RTW_STATUS_TIMEDOUT -110 */
|
||||
|
||||
#undef _TRUE
|
||||
#define _TRUE 1
|
||||
|
||||
#undef _FALSE
|
||||
#define _FALSE 0
|
||||
|
||||
|
||||
#ifdef PLATFORM_FREEBSD
|
||||
#include <osdep_service_bsd.h>
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#include <linux/version.h>
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0))
|
||||
#include <linux/sched/signal.h>
|
||||
#include <linux/sched/types.h>
|
||||
#endif
|
||||
#include <osdep_service_linux.h>
|
||||
#include <drv_types_linux.h>
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_OS_XP
|
||||
#include <osdep_service_xp.h>
|
||||
#include <drv_types_xp.h>
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_OS_CE
|
||||
#include <osdep_service_ce.h>
|
||||
#include <drv_types_ce.h>
|
||||
#endif
|
||||
|
||||
/* #include <rtw_byteorder.h> */
|
||||
|
||||
#ifndef BIT
|
||||
#define BIT(x) (1 << (x))
|
||||
#endif
|
||||
#ifndef BIT_ULL
|
||||
#define BIT_ULL(x) (1ULL << (x))
|
||||
#endif
|
||||
|
||||
#define CHECK_BIT(a, b) (!!((a) & (b)))
|
||||
|
||||
#define BIT0 0x00000001
|
||||
#define BIT1 0x00000002
|
||||
#define BIT2 0x00000004
|
||||
#define BIT3 0x00000008
|
||||
#define BIT4 0x00000010
|
||||
#define BIT5 0x00000020
|
||||
#define BIT6 0x00000040
|
||||
#define BIT7 0x00000080
|
||||
#define BIT8 0x00000100
|
||||
#define BIT9 0x00000200
|
||||
#define BIT10 0x00000400
|
||||
#define BIT11 0x00000800
|
||||
#define BIT12 0x00001000
|
||||
#define BIT13 0x00002000
|
||||
#define BIT14 0x00004000
|
||||
#define BIT15 0x00008000
|
||||
#define BIT16 0x00010000
|
||||
#define BIT17 0x00020000
|
||||
#define BIT18 0x00040000
|
||||
#define BIT19 0x00080000
|
||||
#define BIT20 0x00100000
|
||||
#define BIT21 0x00200000
|
||||
#define BIT22 0x00400000
|
||||
#define BIT23 0x00800000
|
||||
#define BIT24 0x01000000
|
||||
#define BIT25 0x02000000
|
||||
#define BIT26 0x04000000
|
||||
#define BIT27 0x08000000
|
||||
#define BIT28 0x10000000
|
||||
#define BIT29 0x20000000
|
||||
#define BIT30 0x40000000
|
||||
#define BIT31 0x80000000
|
||||
#define BIT32 0x0100000000
|
||||
#define BIT33 0x0200000000
|
||||
#define BIT34 0x0400000000
|
||||
#define BIT35 0x0800000000
|
||||
#define BIT36 0x1000000000
|
||||
|
||||
#ifndef GENMASK
|
||||
#define GENMASK(h, l) \
|
||||
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
|
||||
#endif
|
||||
|
||||
extern int RTW_STATUS_CODE(int error_code);
|
||||
|
||||
#ifndef RTK_DMP_PLATFORM
|
||||
#define CONFIG_USE_VMALLOC
|
||||
#endif
|
||||
|
||||
/* flags used for rtw_mstat_update() */
|
||||
enum mstat_f {
|
||||
/* type: 0x00ff */
|
||||
MSTAT_TYPE_VIR = 0x00,
|
||||
MSTAT_TYPE_PHY = 0x01,
|
||||
MSTAT_TYPE_SKB = 0x02,
|
||||
MSTAT_TYPE_USB = 0x03,
|
||||
MSTAT_TYPE_MAX = 0x04,
|
||||
|
||||
/* func: 0xff00 */
|
||||
MSTAT_FUNC_UNSPECIFIED = 0x00 << 8,
|
||||
MSTAT_FUNC_IO = 0x01 << 8,
|
||||
MSTAT_FUNC_TX_IO = 0x02 << 8,
|
||||
MSTAT_FUNC_RX_IO = 0x03 << 8,
|
||||
MSTAT_FUNC_TX = 0x04 << 8,
|
||||
MSTAT_FUNC_RX = 0x05 << 8,
|
||||
MSTAT_FUNC_CFG_VENDOR = 0x06 << 8,
|
||||
MSTAT_FUNC_MAX = 0x07 << 8,
|
||||
};
|
||||
|
||||
#define mstat_tf_idx(flags) ((flags) & 0xff)
|
||||
#define mstat_ff_idx(flags) (((flags) & 0xff00) >> 8)
|
||||
|
||||
typedef enum mstat_status {
|
||||
MSTAT_ALLOC_SUCCESS = 0,
|
||||
MSTAT_ALLOC_FAIL,
|
||||
MSTAT_FREE
|
||||
} MSTAT_STATUS;
|
||||
|
||||
#ifdef DBG_MEM_ALLOC
|
||||
void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz);
|
||||
void rtw_mstat_dump(void *sel);
|
||||
bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size);
|
||||
void *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
|
||||
void *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
|
||||
void dbg_rtw_vmfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
|
||||
void *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
|
||||
void *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line);
|
||||
void dbg_rtw_mfree(void *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line);
|
||||
|
||||
struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line);
|
||||
void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
|
||||
struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
|
||||
struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line);
|
||||
int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
|
||||
#ifdef CONFIG_RTW_NAPI
|
||||
int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
|
||||
#ifdef CONFIG_RTW_GRO
|
||||
gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line);
|
||||
#endif
|
||||
#endif /* CONFIG_RTW_NAPI */
|
||||
void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line);
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line);
|
||||
void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line);
|
||||
#endif /* CONFIG_USB_HCI */
|
||||
|
||||
#ifdef CONFIG_USE_VMALLOC
|
||||
#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
|
||||
#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
|
||||
#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
|
||||
#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
|
||||
#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
|
||||
#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__)
|
||||
#else /* CONFIG_USE_VMALLOC */
|
||||
#define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#endif /* CONFIG_USE_VMALLOC */
|
||||
#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__)
|
||||
|
||||
#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#ifdef CONFIG_RTW_NAPI
|
||||
#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#ifdef CONFIG_RTW_GRO
|
||||
#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#endif
|
||||
#endif /* CONFIG_RTW_NAPI */
|
||||
#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__)
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
|
||||
#define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
|
||||
#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
|
||||
#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f) & 0xff00) | MSTAT_TYPE_USB, __FUNCTION__, __LINE__)
|
||||
#endif /* CONFIG_USB_HCI */
|
||||
|
||||
#else /* DBG_MEM_ALLOC */
|
||||
#define rtw_mstat_update(flag, status, sz) do {} while (0)
|
||||
#define rtw_mstat_dump(sel) do {} while (0)
|
||||
#define match_mstat_sniff_rules(flags, size) _FALSE
|
||||
void *_rtw_vmalloc(u32 sz);
|
||||
void *_rtw_zvmalloc(u32 sz);
|
||||
void _rtw_vmfree(void *pbuf, u32 sz);
|
||||
void *_rtw_zmalloc(u32 sz);
|
||||
void *_rtw_malloc(u32 sz);
|
||||
void _rtw_mfree(void *pbuf, u32 sz);
|
||||
|
||||
struct sk_buff *_rtw_skb_alloc(u32 sz);
|
||||
void _rtw_skb_free(struct sk_buff *skb);
|
||||
struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb);
|
||||
struct sk_buff *_rtw_skb_clone(struct sk_buff *skb);
|
||||
int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb);
|
||||
#ifdef CONFIG_RTW_NAPI
|
||||
int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb);
|
||||
#ifdef CONFIG_RTW_GRO
|
||||
gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb);
|
||||
#endif
|
||||
#endif /* CONFIG_RTW_NAPI */
|
||||
void _rtw_skb_queue_purge(struct sk_buff_head *list);
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma);
|
||||
void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma);
|
||||
#endif /* CONFIG_USB_HCI */
|
||||
|
||||
#ifdef CONFIG_USE_VMALLOC
|
||||
#define rtw_vmalloc(sz) _rtw_vmalloc((sz))
|
||||
#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz))
|
||||
#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz))
|
||||
#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz))
|
||||
#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz))
|
||||
#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz))
|
||||
#else /* CONFIG_USE_VMALLOC */
|
||||
#define rtw_vmalloc(sz) _rtw_malloc((sz))
|
||||
#define rtw_zvmalloc(sz) _rtw_zmalloc((sz))
|
||||
#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz))
|
||||
#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz))
|
||||
#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz))
|
||||
#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz))
|
||||
#endif /* CONFIG_USE_VMALLOC */
|
||||
#define rtw_malloc(sz) _rtw_malloc((sz))
|
||||
#define rtw_zmalloc(sz) _rtw_zmalloc((sz))
|
||||
#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz))
|
||||
#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz))
|
||||
#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz))
|
||||
#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz))
|
||||
|
||||
#define rtw_skb_alloc(size) _rtw_skb_alloc((size))
|
||||
#define rtw_skb_free(skb) _rtw_skb_free((skb))
|
||||
#define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size))
|
||||
#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb))
|
||||
#define rtw_skb_copy(skb) _rtw_skb_copy((skb))
|
||||
#define rtw_skb_clone(skb) _rtw_skb_clone((skb))
|
||||
#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb))
|
||||
#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb))
|
||||
#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb)
|
||||
#ifdef CONFIG_RTW_NAPI
|
||||
#define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb)
|
||||
#ifdef CONFIG_RTW_GRO
|
||||
#define rtw_napi_gro_receive(napi, skb) _rtw_napi_gro_receive(napi, skb)
|
||||
#endif
|
||||
#endif /* CONFIG_RTW_NAPI */
|
||||
#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head)
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma))
|
||||
#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
|
||||
#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma))
|
||||
#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma))
|
||||
#endif /* CONFIG_USB_HCI */
|
||||
#endif /* DBG_MEM_ALLOC */
|
||||
|
||||
extern void *rtw_malloc2d(int h, int w, size_t size);
|
||||
extern void rtw_mfree2d(void *pbuf, int h, int w, int size);
|
||||
|
||||
void rtw_os_pkt_free(_pkt *pkt);
|
||||
_pkt *rtw_os_pkt_copy(_pkt *pkt);
|
||||
void *rtw_os_pkt_data(_pkt *pkt);
|
||||
u32 rtw_os_pkt_len(_pkt *pkt);
|
||||
|
||||
extern void _rtw_memcpy(void *dec, const void *sour, u32 sz);
|
||||
extern void _rtw_memmove(void *dst, const void *src, u32 sz);
|
||||
extern int _rtw_memcmp(const void *dst, const void *src, u32 sz);
|
||||
extern int _rtw_memcmp2(const void *dst, const void *src, u32 sz);
|
||||
extern void _rtw_memset(void *pbuf, int c, u32 sz);
|
||||
|
||||
extern void _rtw_init_listhead(_list *list);
|
||||
extern u32 rtw_is_list_empty(_list *phead);
|
||||
extern void rtw_list_insert_head(_list *plist, _list *phead);
|
||||
extern void rtw_list_insert_tail(_list *plist, _list *phead);
|
||||
void rtw_list_splice(_list *list, _list *head);
|
||||
void rtw_list_splice_init(_list *list, _list *head);
|
||||
void rtw_list_splice_tail(_list *list, _list *head);
|
||||
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
extern void rtw_list_delete(_list *plist);
|
||||
#endif /* PLATFORM_FREEBSD */
|
||||
|
||||
void rtw_hlist_head_init(rtw_hlist_head *h);
|
||||
void rtw_hlist_add_head(rtw_hlist_node *n, rtw_hlist_head *h);
|
||||
void rtw_hlist_del(rtw_hlist_node *n);
|
||||
void rtw_hlist_add_head_rcu(rtw_hlist_node *n, rtw_hlist_head *h);
|
||||
void rtw_hlist_del_rcu(rtw_hlist_node *n);
|
||||
|
||||
extern void _rtw_init_sema(_sema *sema, int init_val);
|
||||
extern void _rtw_free_sema(_sema *sema);
|
||||
extern void _rtw_up_sema(_sema *sema);
|
||||
extern u32 _rtw_down_sema(_sema *sema);
|
||||
extern void _rtw_mutex_init(_mutex *pmutex);
|
||||
extern void _rtw_mutex_free(_mutex *pmutex);
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
extern void _rtw_spinlock_init(_lock *plock);
|
||||
#endif /* PLATFORM_FREEBSD */
|
||||
extern void _rtw_spinlock_free(_lock *plock);
|
||||
extern void _rtw_spinlock(_lock *plock);
|
||||
extern void _rtw_spinunlock(_lock *plock);
|
||||
extern void _rtw_spinlock_ex(_lock *plock);
|
||||
extern void _rtw_spinunlock_ex(_lock *plock);
|
||||
|
||||
extern void _rtw_init_queue(_queue *pqueue);
|
||||
extern void _rtw_deinit_queue(_queue *pqueue);
|
||||
extern u32 _rtw_queue_empty(_queue *pqueue);
|
||||
extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement);
|
||||
|
||||
extern systime _rtw_get_current_time(void);
|
||||
extern u32 _rtw_systime_to_ms(systime stime);
|
||||
extern systime _rtw_ms_to_systime(u32 ms);
|
||||
extern systime _rtw_us_to_systime(u32 us);
|
||||
extern s32 _rtw_get_passing_time_ms(systime start);
|
||||
extern s32 _rtw_get_remaining_time_ms(systime end);
|
||||
extern s32 _rtw_get_time_interval_ms(systime start, systime end);
|
||||
extern bool _rtw_time_after(systime a, systime b);
|
||||
|
||||
#ifdef DBG_SYSTIME
|
||||
#define rtw_get_current_time() ({systime __stime = _rtw_get_current_time(); __stime;})
|
||||
#define rtw_systime_to_ms(stime) ({u32 __ms = _rtw_systime_to_ms(stime); typecheck(systime, stime); __ms;})
|
||||
#define rtw_ms_to_systime(ms) ({systime __stime = _rtw_ms_to_systime(ms); __stime;})
|
||||
#define rtw_us_to_systime(us) ({systime __stime = _rtw_us_to_systime(us); __stime;})
|
||||
#define rtw_get_passing_time_ms(start) ({u32 __ms = _rtw_get_passing_time_ms(start); typecheck(systime, start); __ms;})
|
||||
#define rtw_get_remaining_time_ms(end) ({u32 __ms = _rtw_get_remaining_time_ms(end); typecheck(systime, end); __ms;})
|
||||
#define rtw_get_time_interval_ms(start, end) ({u32 __ms = _rtw_get_time_interval_ms(start, end); typecheck(systime, start); typecheck(systime, end); __ms;})
|
||||
#define rtw_time_after(a,b) ({bool __r = _rtw_time_after(a,b); typecheck(systime, a); typecheck(systime, b); __r;})
|
||||
#define rtw_time_before(a,b) ({bool __r = _rtw_time_after(b, a); typecheck(systime, a); typecheck(systime, b); __r;})
|
||||
#else
|
||||
#define rtw_get_current_time() _rtw_get_current_time()
|
||||
#define rtw_systime_to_ms(stime) _rtw_systime_to_ms(stime)
|
||||
#define rtw_ms_to_systime(ms) _rtw_ms_to_systime(ms)
|
||||
#define rtw_us_to_systime(us) _rtw_us_to_systime(us)
|
||||
#define rtw_get_passing_time_ms(start) _rtw_get_passing_time_ms(start)
|
||||
#define rtw_get_remaining_time_ms(end) _rtw_get_remaining_time_ms(end)
|
||||
#define rtw_get_time_interval_ms(start, end) _rtw_get_time_interval_ms(start, end)
|
||||
#define rtw_time_after(a,b) _rtw_time_after(a,b)
|
||||
#define rtw_time_before(a,b) _rtw_time_after(b,a)
|
||||
#endif
|
||||
|
||||
sysptime rtw_sptime_get(void);
|
||||
sysptime rtw_sptime_set(s64 secs, const u32 nsecs);
|
||||
sysptime rtw_sptime_zero(void);
|
||||
|
||||
int rtw_sptime_cmp(const sysptime cmp1, const sysptime cmp2);
|
||||
bool rtw_sptime_eql(const sysptime cmp1, const sysptime cmp2);
|
||||
bool rtw_sptime_is_zero(const sysptime sptime);
|
||||
sysptime rtw_sptime_sub(const sysptime lhs, const sysptime rhs);
|
||||
sysptime rtw_sptime_add(const sysptime lhs, const sysptime rhs);
|
||||
|
||||
s64 rtw_sptime_to_ms(const sysptime sptime);
|
||||
sysptime rtw_ms_to_sptime(u64 ms);
|
||||
s64 rtw_sptime_to_us(const sysptime sptime);
|
||||
sysptime rtw_us_to_sptime(u64 us);
|
||||
s64 rtw_sptime_to_ns(const sysptime sptime);
|
||||
sysptime rtw_ns_to_sptime(u64 ns);
|
||||
|
||||
s64 rtw_sptime_diff_ms(const sysptime start, const sysptime end);
|
||||
s64 rtw_sptime_pass_ms(const sysptime start);
|
||||
s64 rtw_sptime_diff_us(const sysptime start, const sysptime end);
|
||||
s64 rtw_sptime_pass_us(const sysptime start);
|
||||
s64 rtw_sptime_diff_ns(const sysptime start, const sysptime end);
|
||||
s64 rtw_sptime_pass_ns(const sysptime start);
|
||||
|
||||
extern void rtw_sleep_schedulable(int ms);
|
||||
|
||||
extern void rtw_msleep_os(int ms);
|
||||
extern void rtw_usleep_os(int us);
|
||||
|
||||
extern u32 rtw_atoi(u8 *s);
|
||||
|
||||
#ifdef DBG_DELAY_OS
|
||||
#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__)
|
||||
#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__)
|
||||
extern void _rtw_mdelay_os(int ms, const char *func, const int line);
|
||||
extern void _rtw_udelay_os(int us, const char *func, const int line);
|
||||
#else
|
||||
extern void rtw_mdelay_os(int ms);
|
||||
extern void rtw_udelay_os(int us);
|
||||
#endif
|
||||
|
||||
extern void rtw_yield_os(void);
|
||||
|
||||
enum rtw_pwait_type {
|
||||
RTW_PWAIT_TYPE_MSLEEP,
|
||||
RTW_PWAIT_TYPE_USLEEP,
|
||||
RTW_PWAIT_TYPE_YIELD,
|
||||
RTW_PWAIT_TYPE_MDELAY,
|
||||
RTW_PWAIT_TYPE_UDELAY,
|
||||
|
||||
RTW_PWAIT_TYPE_NUM,
|
||||
};
|
||||
|
||||
#define RTW_PWAIT_TYPE_VALID(type) (type < RTW_PWAIT_TYPE_NUM)
|
||||
|
||||
struct rtw_pwait_conf {
|
||||
enum rtw_pwait_type type;
|
||||
s32 wait_time;
|
||||
s32 wait_cnt_lmt;
|
||||
};
|
||||
|
||||
struct rtw_pwait_ctx {
|
||||
struct rtw_pwait_conf conf;
|
||||
s32 wait_cnt;
|
||||
void (*wait_hdl)(int us);
|
||||
};
|
||||
|
||||
extern const char *_rtw_pwait_type_str[];
|
||||
#define rtw_pwait_type_str(type) (RTW_PWAIT_TYPE_VALID(type) ? _rtw_pwait_type_str[type] : _rtw_pwait_type_str[RTW_PWAIT_TYPE_NUM])
|
||||
|
||||
#define rtw_pwctx_reset(pwctx) (pwctx)->wait_cnt = 0
|
||||
#define rtw_pwctx_wait(pwctx) do { (pwctx)->wait_hdl((pwctx)->conf.wait_time); (pwctx)->wait_cnt++; } while(0)
|
||||
#define rtw_pwctx_waited(pwctx) ((pwctx)->wait_cnt)
|
||||
#define rtw_pwctx_exceed(pwctx) ((pwctx)->conf.wait_cnt_lmt >= 0 && (pwctx)->wait_cnt >= (pwctx)->conf.wait_cnt_lmt)
|
||||
|
||||
int rtw_pwctx_config(struct rtw_pwait_ctx *pwctx, enum rtw_pwait_type type, s32 time, s32 cnt_lmt);
|
||||
|
||||
extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx);
|
||||
|
||||
|
||||
__inline static unsigned char _cancel_timer_ex(_timer *ptimer)
|
||||
{
|
||||
u8 bcancelled;
|
||||
|
||||
_cancel_timer(ptimer, &bcancelled);
|
||||
|
||||
return bcancelled;
|
||||
}
|
||||
|
||||
static __inline void thread_enter(char *name)
|
||||
{
|
||||
#ifdef PLATFORM_LINUX
|
||||
allow_signal(SIGTERM);
|
||||
#endif
|
||||
#ifdef PLATFORM_FREEBSD
|
||||
printf("%s", "RTKTHREAD_enter");
|
||||
#endif
|
||||
}
|
||||
void thread_exit(_completion *comp);
|
||||
void _rtw_init_completion(_completion *comp);
|
||||
void _rtw_wait_for_comp_timeout(_completion *comp);
|
||||
void _rtw_wait_for_comp(_completion *comp);
|
||||
|
||||
static inline bool rtw_thread_stop(_thread_hdl_ th)
|
||||
{
|
||||
#ifdef PLATFORM_LINUX
|
||||
return kthread_stop(th);
|
||||
#endif
|
||||
}
|
||||
static inline void rtw_thread_wait_stop(void)
|
||||
{
|
||||
#ifdef PLATFORM_LINUX
|
||||
#if 0
|
||||
while (!kthread_should_stop())
|
||||
rtw_msleep_os(10);
|
||||
#else
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
while (!kthread_should_stop()) {
|
||||
schedule();
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
}
|
||||
__set_current_state(TASK_RUNNING);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
__inline static void flush_signals_thread(void)
|
||||
{
|
||||
#ifdef PLATFORM_LINUX
|
||||
if (signal_pending(current))
|
||||
flush_signals(current);
|
||||
#endif
|
||||
}
|
||||
|
||||
__inline static _OS_STATUS res_to_status(sint res)
|
||||
{
|
||||
|
||||
#if defined(PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD)
|
||||
return res;
|
||||
#endif
|
||||
|
||||
#ifdef PLATFORM_WINDOWS
|
||||
|
||||
if (res == _SUCCESS)
|
||||
return NDIS_STATUS_SUCCESS;
|
||||
else
|
||||
return NDIS_STATUS_FAILURE;
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
__inline static void rtw_dump_stack(void)
|
||||
{
|
||||
#ifdef PLATFORM_LINUX
|
||||
dump_stack();
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#define rtw_warn_on(condition) WARN_ON(condition)
|
||||
#else
|
||||
#define rtw_warn_on(condition) do {} while (0)
|
||||
#endif
|
||||
|
||||
__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4)
|
||||
{
|
||||
int ret = _TRUE;
|
||||
|
||||
#ifdef PLATFORM_WINDOWS
|
||||
if (((uint)parg1) <= 0x7fffffff ||
|
||||
((uint)parg2) <= 0x7fffffff ||
|
||||
((uint)parg3) <= 0x7fffffff ||
|
||||
((uint)parg4) <= 0x7fffffff) {
|
||||
ret = _FALSE;
|
||||
KeBugCheckEx(0x87110000, (ULONG_PTR)parg1, (ULONG_PTR)parg2, (ULONG_PTR)parg3, (ULONG_PTR)parg4);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
#ifdef PLATFORM_LINUX
|
||||
#define RTW_DIV_ROUND_UP(n, d) DIV_ROUND_UP(n, d)
|
||||
#else /* !PLATFORM_LINUX */
|
||||
#define RTW_DIV_ROUND_UP(n, d) (((n) + (d - 1)) / d)
|
||||
#endif /* !PLATFORM_LINUX */
|
||||
|
||||
#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r))
|
||||
#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2)
|
||||
|
||||
__inline static u32 _RND4(u32 sz)
|
||||
{
|
||||
|
||||
u32 val;
|
||||
|
||||
val = ((sz >> 2) + ((sz & 3) ? 1 : 0)) << 2;
|
||||
|
||||
return val;
|
||||
|
||||
}
|
||||
|
||||
__inline static u32 _RND8(u32 sz)
|
||||
{
|
||||
|
||||
u32 val;
|
||||
|
||||
val = ((sz >> 3) + ((sz & 7) ? 1 : 0)) << 3;
|
||||
|
||||
return val;
|
||||
|
||||
}
|
||||
|
||||
__inline static u32 _RND128(u32 sz)
|
||||
{
|
||||
|
||||
u32 val;
|
||||
|
||||
val = ((sz >> 7) + ((sz & 127) ? 1 : 0)) << 7;
|
||||
|
||||
return val;
|
||||
|
||||
}
|
||||
|
||||
__inline static u32 _RND256(u32 sz)
|
||||
{
|
||||
|
||||
u32 val;
|
||||
|
||||
val = ((sz >> 8) + ((sz & 255) ? 1 : 0)) << 8;
|
||||
|
||||
return val;
|
||||
|
||||
}
|
||||
|
||||
__inline static u32 _RND512(u32 sz)
|
||||
{
|
||||
|
||||
u32 val;
|
||||
|
||||
val = ((sz >> 9) + ((sz & 511) ? 1 : 0)) << 9;
|
||||
|
||||
return val;
|
||||
|
||||
}
|
||||
|
||||
__inline static u32 bitshift(u32 bitmask)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i <= 31; i++)
|
||||
if (((bitmask >> i) & 0x1) == 1)
|
||||
break;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static inline int largest_bit(u32 bitmask)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 31; i >= 0; i--)
|
||||
if (bitmask & BIT(i))
|
||||
break;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static inline int largest_bit_64(u64 bitmask)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 63; i >= 0; i--)
|
||||
if (bitmask & BIT_ULL(i))
|
||||
break;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
#define rtw_abs(a) (a < 0 ? -a : a)
|
||||
#define rtw_min(a, b) ((a > b) ? b : a)
|
||||
#define rtw_max(a, b) ((a > b) ? a : b)
|
||||
#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b)))
|
||||
#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b)))
|
||||
|
||||
#ifndef MAC_FMT
|
||||
#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
|
||||
#endif
|
||||
#ifndef MAC_ARG
|
||||
#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
|
||||
#endif
|
||||
|
||||
bool rtw_macaddr_is_larger(const u8 *a, const u8 *b);
|
||||
|
||||
extern void rtw_suspend_lock_init(void);
|
||||
extern void rtw_suspend_lock_uninit(void);
|
||||
extern void rtw_lock_suspend(void);
|
||||
extern void rtw_unlock_suspend(void);
|
||||
extern void rtw_lock_suspend_timeout(u32 timeout_ms);
|
||||
extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms);
|
||||
extern void rtw_resume_lock_suspend(void);
|
||||
extern void rtw_resume_unlock_suspend(void);
|
||||
#ifdef CONFIG_AP_WOWLAN
|
||||
extern void rtw_softap_lock_suspend(void);
|
||||
extern void rtw_softap_unlock_suspend(void);
|
||||
#endif
|
||||
|
||||
extern void rtw_set_bit(int nr, unsigned long *addr);
|
||||
extern void rtw_clear_bit(int nr, unsigned long *addr);
|
||||
extern int rtw_test_and_clear_bit(int nr, unsigned long *addr);
|
||||
|
||||
extern void ATOMIC_SET(ATOMIC_T *v, int i);
|
||||
extern int ATOMIC_READ(ATOMIC_T *v);
|
||||
extern void ATOMIC_ADD(ATOMIC_T *v, int i);
|
||||
extern void ATOMIC_SUB(ATOMIC_T *v, int i);
|
||||
extern void ATOMIC_INC(ATOMIC_T *v);
|
||||
extern void ATOMIC_DEC(ATOMIC_T *v);
|
||||
extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i);
|
||||
extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i);
|
||||
extern int ATOMIC_INC_RETURN(ATOMIC_T *v);
|
||||
extern int ATOMIC_DEC_RETURN(ATOMIC_T *v);
|
||||
extern bool ATOMIC_INC_UNLESS(ATOMIC_T *v, int u);
|
||||
|
||||
/* File operation APIs, just for linux now */
|
||||
extern int rtw_is_dir_readable(const char *path);
|
||||
extern int rtw_is_file_readable(const char *path);
|
||||
extern int rtw_is_file_readable_with_size(const char *path, u32 *sz);
|
||||
extern int rtw_readable_file_sz_chk(const char *path, u32 sz);
|
||||
extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz);
|
||||
extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz);
|
||||
|
||||
|
||||
#ifndef PLATFORM_FREEBSD
|
||||
extern void rtw_free_netdev(struct net_device *netdev);
|
||||
#endif /* PLATFORM_FREEBSD */
|
||||
|
||||
|
||||
extern u64 rtw_modular64(u64 x, u64 y);
|
||||
extern u64 rtw_division64(u64 x, u64 y);
|
||||
extern u32 rtw_random32(void);
|
||||
|
||||
/* Macros for handling unaligned memory accesses */
|
||||
|
||||
#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1]))
|
||||
#define RTW_PUT_BE16(a, val) \
|
||||
do { \
|
||||
(a)[0] = ((u16) (val)) >> 8; \
|
||||
(a)[1] = ((u16) (val)) & 0xff; \
|
||||
} while (0)
|
||||
|
||||
#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0]))
|
||||
#define RTW_PUT_LE16(a, val) \
|
||||
do { \
|
||||
(a)[1] = ((u16) (val)) >> 8; \
|
||||
(a)[0] = ((u16) (val)) & 0xff; \
|
||||
} while (0)
|
||||
|
||||
#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \
|
||||
((u32) (a)[2]))
|
||||
#define RTW_PUT_BE24(a, val) \
|
||||
do { \
|
||||
(a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \
|
||||
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
|
||||
(a)[2] = (u8) (((u32) (val)) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \
|
||||
(((u32) (a)[2]) << 8) | ((u32) (a)[3]))
|
||||
#define RTW_PUT_BE32(a, val) \
|
||||
do { \
|
||||
(a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \
|
||||
(a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \
|
||||
(a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \
|
||||
(a)[3] = (u8) (((u32) (val)) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \
|
||||
(((u32) (a)[1]) << 8) | ((u32) (a)[0]))
|
||||
#define RTW_PUT_LE32(a, val) \
|
||||
do { \
|
||||
(a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \
|
||||
(a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \
|
||||
(a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \
|
||||
(a)[0] = (u8) (((u32) (val)) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \
|
||||
(((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \
|
||||
(((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \
|
||||
(((u64) (a)[6]) << 8) | ((u64) (a)[7]))
|
||||
#define RTW_PUT_BE64(a, val) \
|
||||
do { \
|
||||
(a)[0] = (u8) (((u64) (val)) >> 56); \
|
||||
(a)[1] = (u8) (((u64) (val)) >> 48); \
|
||||
(a)[2] = (u8) (((u64) (val)) >> 40); \
|
||||
(a)[3] = (u8) (((u64) (val)) >> 32); \
|
||||
(a)[4] = (u8) (((u64) (val)) >> 24); \
|
||||
(a)[5] = (u8) (((u64) (val)) >> 16); \
|
||||
(a)[6] = (u8) (((u64) (val)) >> 8); \
|
||||
(a)[7] = (u8) (((u64) (val)) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \
|
||||
(((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \
|
||||
(((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \
|
||||
(((u64) (a)[1]) << 8) | ((u64) (a)[0]))
|
||||
#define RTW_PUT_LE64(a, val) \
|
||||
do { \
|
||||
(a)[7] = (u8) ((((u64) (val)) >> 56) & 0xff); \
|
||||
(a)[6] = (u8) ((((u64) (val)) >> 48) & 0xff); \
|
||||
(a)[5] = (u8) ((((u64) (val)) >> 40) & 0xff); \
|
||||
(a)[4] = (u8) ((((u64) (val)) >> 32) & 0xff); \
|
||||
(a)[3] = (u8) ((((u64) (val)) >> 24) & 0xff); \
|
||||
(a)[2] = (u8) ((((u64) (val)) >> 16) & 0xff); \
|
||||
(a)[1] = (u8) ((((u64) (val)) >> 8) & 0xff); \
|
||||
(a)[0] = (u8) (((u64) (val)) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
void rtw_buf_free(u8 **buf, u32 *buf_len);
|
||||
void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len);
|
||||
|
||||
struct rtw_cbuf {
|
||||
u32 write;
|
||||
u32 read;
|
||||
u32 size;
|
||||
void *bufs[0];
|
||||
};
|
||||
|
||||
bool rtw_cbuf_full(struct rtw_cbuf *cbuf);
|
||||
bool rtw_cbuf_empty(struct rtw_cbuf *cbuf);
|
||||
bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf);
|
||||
void *rtw_cbuf_pop(struct rtw_cbuf *cbuf);
|
||||
struct rtw_cbuf *rtw_cbuf_alloc(u32 size);
|
||||
void rtw_cbuf_free(struct rtw_cbuf *cbuf);
|
||||
|
||||
struct map_seg_t {
|
||||
u16 sa;
|
||||
u16 len;
|
||||
u8 *c;
|
||||
};
|
||||
|
||||
struct map_t {
|
||||
u16 len;
|
||||
u16 seg_num;
|
||||
u8 init_value;
|
||||
struct map_seg_t *segs;
|
||||
};
|
||||
|
||||
#define MAPSEG_ARRAY_ENT(_sa, _len, _c, arg...) \
|
||||
{ .sa = _sa, .len = _len, .c = (u8[_len]){ _c, ##arg}, }
|
||||
|
||||
#define MAPSEG_PTR_ENT(_sa, _len, _p) \
|
||||
{ .sa = _sa, .len = _len, .c = _p, }
|
||||
|
||||
#define MAP_ENT(_len, _seg_num, _init_v, _seg, arg...) \
|
||||
{ .len = _len, .seg_num = _seg_num, .init_value = _init_v, .segs = (struct map_seg_t[_seg_num]){ _seg, ##arg}, }
|
||||
|
||||
int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf);
|
||||
u8 map_read8(const struct map_t *map, u16 offset);
|
||||
|
||||
struct blacklist_ent {
|
||||
_list list;
|
||||
u8 addr[ETH_ALEN];
|
||||
systime exp_time;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_RTW_MESH
|
||||
int rtw_blacklist_add(_queue *blist, const u8 *addr, u32 timeout_ms);
|
||||
int rtw_blacklist_del(_queue *blist, const u8 *addr);
|
||||
int rtw_blacklist_search(_queue *blist, const u8 *addr);
|
||||
void rtw_blacklist_flush(_queue *blist);
|
||||
void dump_blacklist(void *sel, _queue *blist, const char *title);
|
||||
#endif
|
||||
|
||||
/* String handler */
|
||||
|
||||
BOOLEAN is_null(char c);
|
||||
BOOLEAN is_all_null(char *c, int len);
|
||||
BOOLEAN is_eol(char c);
|
||||
BOOLEAN is_space(char c);
|
||||
BOOLEAN IsHexDigit(char chTmp);
|
||||
BOOLEAN is_alpha(char chTmp);
|
||||
char alpha_to_upper(char c);
|
||||
|
||||
int hex2num_i(char c);
|
||||
int hex2byte_i(const char *hex);
|
||||
int hexstr2bin(const char *hex, u8 *buf, size_t len);
|
||||
|
||||
int hwaddr_aton_i(const char *txt, u8 *addr);
|
||||
|
||||
/*
|
||||
* Write formatted output to sized buffer
|
||||
*/
|
||||
#ifdef PLATFORM_LINUX
|
||||
#define rtw_sprintf(buf, size, format, arg...) snprintf(buf, size, format, ##arg)
|
||||
#else /* !PLATFORM_LINUX */
|
||||
#error "NOT DEFINE \"rtw_sprintf\"!!"
|
||||
#endif /* !PLATFORM_LINUX */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,757 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __OSDEP_BSD_SERVICE_H_
|
||||
#define __OSDEP_BSD_SERVICE_H_
|
||||
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/param.h>
|
||||
#include <sys/sockio.h>
|
||||
#include <sys/sysctl.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/mbuf.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/endian.h>
|
||||
#include <sys/kdb.h>
|
||||
#include <sys/kthread.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/time.h>
|
||||
#include <machine/atomic.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/rman.h>
|
||||
|
||||
#include <net/bpf.h>
|
||||
#include <net/if.h>
|
||||
#include <net/if_arp.h>
|
||||
#include <net/ethernet.h>
|
||||
#include <net/if_dl.h>
|
||||
#include <net/if_media.h>
|
||||
#include <net/if_types.h>
|
||||
#include <net/route.h>
|
||||
|
||||
|
||||
#include <netinet/in.h>
|
||||
#include <netinet/in_systm.h>
|
||||
#include <netinet/in_var.h>
|
||||
#include <netinet/if_ether.h>
|
||||
#include <if_ether.h>
|
||||
|
||||
#include <net80211/ieee80211_var.h>
|
||||
#include <net80211/ieee80211_regdomain.h>
|
||||
#include <net80211/ieee80211_radiotap.h>
|
||||
#include <net80211/ieee80211_ratectl.h>
|
||||
|
||||
#include <dev/usb/usb.h>
|
||||
#include <dev/usb/usbdi.h>
|
||||
#include "usbdevs.h"
|
||||
|
||||
#define USB_DEBUG_VAR rum_debug
|
||||
#include <dev/usb/usb_debug.h>
|
||||
|
||||
#if 1 //Baron porting from linux, it's all temp solution, needs to check again
|
||||
#include <sys/sema.h>
|
||||
#include <sys/pcpu.h> /* XXX for PCPU_GET */
|
||||
// typedef struct semaphore _sema;
|
||||
typedef struct sema _sema;
|
||||
// typedef spinlock_t _lock;
|
||||
typedef struct mtx _lock;
|
||||
typedef struct mtx _mutex;
|
||||
typedef struct rtw_timer_list _timer;
|
||||
struct list_head {
|
||||
struct list_head *next, *prev;
|
||||
};
|
||||
struct __queue {
|
||||
struct list_head queue;
|
||||
_lock lock;
|
||||
};
|
||||
|
||||
typedef struct mbuf _pkt;
|
||||
typedef struct mbuf _buffer;
|
||||
|
||||
typedef struct __queue _queue;
|
||||
typedef struct list_head _list;
|
||||
typedef int _OS_STATUS;
|
||||
//typedef u32 _irqL;
|
||||
typedef unsigned long _irqL;
|
||||
typedef struct ifnet * _nic_hdl;
|
||||
|
||||
typedef pid_t _thread_hdl_;
|
||||
// typedef struct thread _thread_hdl_;
|
||||
typedef void thread_return;
|
||||
typedef void* thread_context;
|
||||
|
||||
typedef void timer_hdl_return;
|
||||
typedef void* timer_hdl_context;
|
||||
typedef struct work_struct _workitem;
|
||||
typedef struct task _tasklet;
|
||||
|
||||
#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
|
||||
/* emulate a modern version */
|
||||
#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35)
|
||||
|
||||
#define WIRELESS_EXT -1
|
||||
#define HZ hz
|
||||
#define spin_lock_irqsave mtx_lock_irqsave
|
||||
#define spin_lock_bh mtx_lock_irqsave
|
||||
#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));}
|
||||
//#define IFT_RTW 0xf9 //ifnet allocate type for RTW
|
||||
#define free_netdev if_free
|
||||
#define LIST_CONTAINOR(ptr, type, member) \
|
||||
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
|
||||
#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n))
|
||||
/*
|
||||
* Linux timers are emulated using FreeBSD callout functions
|
||||
* (and taskqueue functionality).
|
||||
*
|
||||
* Currently no timer stats functionality.
|
||||
*
|
||||
* See (linux_compat) processes.c
|
||||
*
|
||||
*/
|
||||
struct rtw_timer_list {
|
||||
struct callout callout;
|
||||
void (*function)(void *);
|
||||
void *arg;
|
||||
};
|
||||
|
||||
struct workqueue_struct;
|
||||
struct work_struct;
|
||||
typedef void (*work_func_t)(struct work_struct *work);
|
||||
/* Values for the state of an item of work (work_struct) */
|
||||
typedef enum work_state {
|
||||
WORK_STATE_UNSET = 0,
|
||||
WORK_STATE_CALLOUT_PENDING = 1,
|
||||
WORK_STATE_TASK_PENDING = 2,
|
||||
WORK_STATE_WORK_CANCELLED = 3
|
||||
} work_state_t;
|
||||
|
||||
struct work_struct {
|
||||
struct task task; /* FreeBSD task */
|
||||
work_state_t state; /* the pending or otherwise state of work. */
|
||||
work_func_t func;
|
||||
};
|
||||
#define spin_unlock_irqrestore mtx_unlock_irqrestore
|
||||
#define spin_unlock_bh mtx_unlock_irqrestore
|
||||
#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock);
|
||||
extern void _rtw_spinlock_init(_lock *plock);
|
||||
|
||||
//modify private structure to match freebsd
|
||||
#define BITS_PER_LONG 32
|
||||
union ktime {
|
||||
s64 tv64;
|
||||
#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR)
|
||||
struct {
|
||||
#ifdef __BIG_ENDIAN
|
||||
s32 sec, nsec;
|
||||
#else
|
||||
s32 nsec, sec;
|
||||
#endif
|
||||
} tv;
|
||||
#endif
|
||||
};
|
||||
#define kmemcheck_bitfield_begin(name)
|
||||
#define kmemcheck_bitfield_end(name)
|
||||
#define CHECKSUM_NONE 0
|
||||
typedef unsigned char *sk_buff_data_t;
|
||||
typedef union ktime ktime_t; /* Kill this */
|
||||
|
||||
void rtw_mtx_lock(_lock *plock);
|
||||
|
||||
void rtw_mtx_unlock(_lock *plock);
|
||||
|
||||
/**
|
||||
* struct sk_buff - socket buffer
|
||||
* @next: Next buffer in list
|
||||
* @prev: Previous buffer in list
|
||||
* @sk: Socket we are owned by
|
||||
* @tstamp: Time we arrived
|
||||
* @dev: Device we arrived on/are leaving by
|
||||
* @transport_header: Transport layer header
|
||||
* @network_header: Network layer header
|
||||
* @mac_header: Link layer header
|
||||
* @_skb_refdst: destination entry (with norefcount bit)
|
||||
* @sp: the security path, used for xfrm
|
||||
* @cb: Control buffer. Free for use by every layer. Put private vars here
|
||||
* @len: Length of actual data
|
||||
* @data_len: Data length
|
||||
* @mac_len: Length of link layer header
|
||||
* @hdr_len: writable header length of cloned skb
|
||||
* @csum: Checksum (must include start/offset pair)
|
||||
* @csum_start: Offset from skb->head where checksumming should start
|
||||
* @csum_offset: Offset from csum_start where checksum should be stored
|
||||
* @local_df: allow local fragmentation
|
||||
* @cloned: Head may be cloned (check refcnt to be sure)
|
||||
* @nohdr: Payload reference only, must not modify header
|
||||
* @pkt_type: Packet class
|
||||
* @fclone: skbuff clone status
|
||||
* @ip_summed: Driver fed us an IP checksum
|
||||
* @priority: Packet queueing priority
|
||||
* @users: User count - see {datagram,tcp}.c
|
||||
* @protocol: Packet protocol from driver
|
||||
* @truesize: Buffer size
|
||||
* @head: Head of buffer
|
||||
* @data: Data head pointer
|
||||
* @tail: Tail pointer
|
||||
* @end: End pointer
|
||||
* @destructor: Destruct function
|
||||
* @mark: Generic packet mark
|
||||
* @nfct: Associated connection, if any
|
||||
* @ipvs_property: skbuff is owned by ipvs
|
||||
* @peeked: this packet has been seen already, so stats have been
|
||||
* done for it, don't do them again
|
||||
* @nf_trace: netfilter packet trace flag
|
||||
* @nfctinfo: Relationship of this skb to the connection
|
||||
* @nfct_reasm: netfilter conntrack re-assembly pointer
|
||||
* @nf_bridge: Saved data about a bridged frame - see br_netfilter.c
|
||||
* @skb_iif: ifindex of device we arrived on
|
||||
* @rxhash: the packet hash computed on receive
|
||||
* @queue_mapping: Queue mapping for multiqueue devices
|
||||
* @tc_index: Traffic control index
|
||||
* @tc_verd: traffic control verdict
|
||||
* @ndisc_nodetype: router type (from link layer)
|
||||
* @dma_cookie: a cookie to one of several possible DMA operations
|
||||
* done by skb DMA functions
|
||||
* @secmark: security marking
|
||||
* @vlan_tci: vlan tag control information
|
||||
*/
|
||||
|
||||
struct sk_buff {
|
||||
/* These two members must be first. */
|
||||
struct sk_buff *next;
|
||||
struct sk_buff *prev;
|
||||
|
||||
ktime_t tstamp;
|
||||
|
||||
struct sock *sk;
|
||||
//struct net_device *dev;
|
||||
struct ifnet *dev;
|
||||
|
||||
/*
|
||||
* This is the control buffer. It is free to use for every
|
||||
* layer. Please put your private variables there. If you
|
||||
* want to keep them across layers you have to do a skb_clone()
|
||||
* first. This is owned by whoever has the skb queued ATM.
|
||||
*/
|
||||
char cb[48] __aligned(8);
|
||||
|
||||
unsigned long _skb_refdst;
|
||||
#ifdef CONFIG_XFRM
|
||||
struct sec_path *sp;
|
||||
#endif
|
||||
unsigned int len,
|
||||
data_len;
|
||||
u16 mac_len,
|
||||
hdr_len;
|
||||
union {
|
||||
u32 csum;
|
||||
struct {
|
||||
u16 csum_start;
|
||||
u16 csum_offset;
|
||||
}smbol2;
|
||||
}smbol1;
|
||||
u32 priority;
|
||||
kmemcheck_bitfield_begin(flags1);
|
||||
u8 local_df:1,
|
||||
cloned:1,
|
||||
ip_summed:2,
|
||||
nohdr:1,
|
||||
nfctinfo:3;
|
||||
u8 pkt_type:3,
|
||||
fclone:2,
|
||||
ipvs_property:1,
|
||||
peeked:1,
|
||||
nf_trace:1;
|
||||
kmemcheck_bitfield_end(flags1);
|
||||
u16 protocol;
|
||||
|
||||
void (*destructor)(struct sk_buff *skb);
|
||||
#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
|
||||
struct nf_conntrack *nfct;
|
||||
struct sk_buff *nfct_reasm;
|
||||
#endif
|
||||
#ifdef CONFIG_BRIDGE_NETFILTER
|
||||
struct nf_bridge_info *nf_bridge;
|
||||
#endif
|
||||
|
||||
int skb_iif;
|
||||
#ifdef CONFIG_NET_SCHED
|
||||
u16 tc_index; /* traffic control index */
|
||||
#ifdef CONFIG_NET_CLS_ACT
|
||||
u16 tc_verd; /* traffic control verdict */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
u32 rxhash;
|
||||
|
||||
kmemcheck_bitfield_begin(flags2);
|
||||
u16 queue_mapping:16;
|
||||
#ifdef CONFIG_IPV6_NDISC_NODETYPE
|
||||
u8 ndisc_nodetype:2,
|
||||
deliver_no_wcard:1;
|
||||
#else
|
||||
u8 deliver_no_wcard:1;
|
||||
#endif
|
||||
kmemcheck_bitfield_end(flags2);
|
||||
|
||||
/* 0/14 bit hole */
|
||||
|
||||
#ifdef CONFIG_NET_DMA
|
||||
dma_cookie_t dma_cookie;
|
||||
#endif
|
||||
#ifdef CONFIG_NETWORK_SECMARK
|
||||
u32 secmark;
|
||||
#endif
|
||||
union {
|
||||
u32 mark;
|
||||
u32 dropcount;
|
||||
}symbol3;
|
||||
|
||||
u16 vlan_tci;
|
||||
|
||||
sk_buff_data_t transport_header;
|
||||
sk_buff_data_t network_header;
|
||||
sk_buff_data_t mac_header;
|
||||
/* These elements must be at the end, see alloc_skb() for details. */
|
||||
sk_buff_data_t tail;
|
||||
sk_buff_data_t end;
|
||||
unsigned char *head,
|
||||
*data;
|
||||
unsigned int truesize;
|
||||
atomic_t users;
|
||||
};
|
||||
struct sk_buff_head {
|
||||
/* These two members must be first. */
|
||||
struct sk_buff *next;
|
||||
struct sk_buff *prev;
|
||||
|
||||
u32 qlen;
|
||||
_lock lock;
|
||||
};
|
||||
#define skb_tail_pointer(skb) skb->tail
|
||||
static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
|
||||
{
|
||||
unsigned char *tmp = skb_tail_pointer(skb);
|
||||
//SKB_LINEAR_ASSERT(skb);
|
||||
skb->tail += len;
|
||||
skb->len += len;
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
|
||||
{
|
||||
skb->len -= len;
|
||||
if(skb->len < skb->data_len)
|
||||
printf("%s(),%d,error!\n",__FUNCTION__,__LINE__);
|
||||
return skb->data += len;
|
||||
}
|
||||
static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len)
|
||||
{
|
||||
#ifdef PLATFORM_FREEBSD
|
||||
return __skb_pull(skb, len);
|
||||
#else
|
||||
return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len);
|
||||
#endif //PLATFORM_FREEBSD
|
||||
}
|
||||
static inline u32 skb_queue_len(const struct sk_buff_head *list_)
|
||||
{
|
||||
return list_->qlen;
|
||||
}
|
||||
static inline void __skb_insert(struct sk_buff *newsk,
|
||||
struct sk_buff *prev, struct sk_buff *next,
|
||||
struct sk_buff_head *list)
|
||||
{
|
||||
newsk->next = next;
|
||||
newsk->prev = prev;
|
||||
next->prev = prev->next = newsk;
|
||||
list->qlen++;
|
||||
}
|
||||
static inline void __skb_queue_before(struct sk_buff_head *list,
|
||||
struct sk_buff *next,
|
||||
struct sk_buff *newsk)
|
||||
{
|
||||
__skb_insert(newsk, next->prev, next, list);
|
||||
}
|
||||
static inline void skb_queue_tail(struct sk_buff_head *list,
|
||||
struct sk_buff *newsk)
|
||||
{
|
||||
mtx_lock(&list->lock);
|
||||
__skb_queue_before(list, (struct sk_buff *)list, newsk);
|
||||
mtx_unlock(&list->lock);
|
||||
}
|
||||
static inline struct sk_buff *skb_peek(struct sk_buff_head *list_)
|
||||
{
|
||||
struct sk_buff *list = ((struct sk_buff *)list_)->next;
|
||||
if (list == (struct sk_buff *)list_)
|
||||
list = NULL;
|
||||
return list;
|
||||
}
|
||||
static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list)
|
||||
{
|
||||
struct sk_buff *next, *prev;
|
||||
|
||||
list->qlen--;
|
||||
next = skb->next;
|
||||
prev = skb->prev;
|
||||
skb->next = skb->prev = NULL;
|
||||
next->prev = prev;
|
||||
prev->next = next;
|
||||
}
|
||||
|
||||
static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list)
|
||||
{
|
||||
mtx_lock(&list->lock);
|
||||
|
||||
struct sk_buff *skb = skb_peek(list);
|
||||
if (skb)
|
||||
__skb_unlink(skb, list);
|
||||
|
||||
mtx_unlock(&list->lock);
|
||||
|
||||
return skb;
|
||||
}
|
||||
static inline void skb_reserve(struct sk_buff *skb, int len)
|
||||
{
|
||||
skb->data += len;
|
||||
skb->tail += len;
|
||||
}
|
||||
static inline void __skb_queue_head_init(struct sk_buff_head *list)
|
||||
{
|
||||
list->prev = list->next = (struct sk_buff *)list;
|
||||
list->qlen = 0;
|
||||
}
|
||||
/*
|
||||
* This function creates a split out lock class for each invocation;
|
||||
* this is needed for now since a whole lot of users of the skb-queue
|
||||
* infrastructure in drivers have different locking usage (in hardirq)
|
||||
* than the networking core (in softirq only). In the long run either the
|
||||
* network layer or drivers should need annotation to consolidate the
|
||||
* main types of usage into 3 classes.
|
||||
*/
|
||||
static inline void skb_queue_head_init(struct sk_buff_head *list)
|
||||
{
|
||||
_rtw_spinlock_init(&list->lock);
|
||||
__skb_queue_head_init(list);
|
||||
}
|
||||
unsigned long copy_from_user(void *to, const void *from, unsigned long n);
|
||||
unsigned long copy_to_user(void *to, const void *from, unsigned long n);
|
||||
struct sk_buff * dev_alloc_skb(unsigned int size);
|
||||
struct sk_buff *skb_clone(const struct sk_buff *skb);
|
||||
void dev_kfree_skb_any(struct sk_buff *skb);
|
||||
#endif //Baron porting from linux, it's all temp solution, needs to check again
|
||||
|
||||
|
||||
#if 1 // kenny add Linux compatibility code for Linux USB driver
|
||||
#include <dev/usb/usb_compat_linux.h>
|
||||
|
||||
#define __init // __attribute ((constructor))
|
||||
#define __exit // __attribute ((destructor))
|
||||
|
||||
/*
|
||||
* Definitions for module_init and module_exit macros.
|
||||
*
|
||||
* These macros will use the SYSINIT framework to call a specified
|
||||
* function (with no arguments) on module loading or unloading.
|
||||
*
|
||||
*/
|
||||
|
||||
void module_init_exit_wrapper(void *arg);
|
||||
|
||||
#define module_init(initfn) \
|
||||
SYSINIT(mod_init_ ## initfn, \
|
||||
SI_SUB_KLD, SI_ORDER_FIRST, \
|
||||
module_init_exit_wrapper, initfn)
|
||||
|
||||
#define module_exit(exitfn) \
|
||||
SYSUNINIT(mod_exit_ ## exitfn, \
|
||||
SI_SUB_KLD, SI_ORDER_ANY, \
|
||||
module_init_exit_wrapper, exitfn)
|
||||
|
||||
/*
|
||||
* The usb_register and usb_deregister functions are used to register
|
||||
* usb drivers with the usb subsystem.
|
||||
*/
|
||||
int usb_register(struct usb_driver *driver);
|
||||
int usb_deregister(struct usb_driver *driver);
|
||||
|
||||
/*
|
||||
* usb_get_dev and usb_put_dev - increment/decrement the reference count
|
||||
* of the usb device structure.
|
||||
*
|
||||
* Original body of usb_get_dev:
|
||||
*
|
||||
* if (dev)
|
||||
* get_device(&dev->dev);
|
||||
* return dev;
|
||||
*
|
||||
* Reference counts are not currently used in this compatibility
|
||||
* layer. So these functions will do nothing.
|
||||
*/
|
||||
static inline struct usb_device *
|
||||
usb_get_dev(struct usb_device *dev)
|
||||
{
|
||||
return dev;
|
||||
}
|
||||
|
||||
static inline void
|
||||
usb_put_dev(struct usb_device *dev)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
// rtw_usb_compat_linux
|
||||
int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags);
|
||||
int rtw_usb_unlink_urb(struct urb *urb);
|
||||
int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe);
|
||||
int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe,
|
||||
uint8_t request, uint8_t requesttype,
|
||||
uint16_t value, uint16_t index, void *data,
|
||||
uint16_t size, usb_timeout_t timeout);
|
||||
int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index);
|
||||
int rtw_usb_setup_endpoint(struct usb_device *dev,
|
||||
struct usb_host_endpoint *uhe, usb_size_t bufsize);
|
||||
struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags);
|
||||
struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep);
|
||||
struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index);
|
||||
struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no);
|
||||
void *rtw_usbd_get_intfdata(struct usb_interface *intf);
|
||||
void rtw_usb_linux_register(void *arg);
|
||||
void rtw_usb_linux_deregister(void *arg);
|
||||
void rtw_usb_linux_free_device(struct usb_device *dev);
|
||||
void rtw_usb_free_urb(struct urb *urb);
|
||||
void rtw_usb_init_urb(struct urb *urb);
|
||||
void rtw_usb_kill_urb(struct urb *urb);
|
||||
void rtw_usb_set_intfdata(struct usb_interface *intf, void *data);
|
||||
void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev,
|
||||
struct usb_host_endpoint *uhe, void *buf,
|
||||
int length, usb_complete_t callback, void *arg);
|
||||
int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe,
|
||||
void *data, int len, uint16_t *pactlen, usb_timeout_t timeout);
|
||||
void *usb_get_intfdata(struct usb_interface *intf);
|
||||
int usb_linux_init_endpoints(struct usb_device *udev);
|
||||
|
||||
|
||||
|
||||
typedef struct urb * PURB;
|
||||
|
||||
typedef unsigned gfp_t;
|
||||
#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */
|
||||
#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */
|
||||
#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */
|
||||
#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */
|
||||
#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */
|
||||
#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */
|
||||
#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */
|
||||
#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */
|
||||
#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */
|
||||
#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */
|
||||
#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */
|
||||
#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */
|
||||
#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */
|
||||
#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */
|
||||
|
||||
/* This equals 0, but use constants in case they ever change */
|
||||
#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH)
|
||||
/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */
|
||||
#define GFP_ATOMIC (__GFP_HIGH)
|
||||
#define GFP_NOIO (__GFP_WAIT)
|
||||
#define GFP_NOFS (__GFP_WAIT | __GFP_IO)
|
||||
#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS)
|
||||
#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL)
|
||||
#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \
|
||||
__GFP_HIGHMEM)
|
||||
|
||||
|
||||
#endif // kenny add Linux compatibility code for Linux USB
|
||||
|
||||
__inline static _list *get_next(_list *list)
|
||||
{
|
||||
return list->next;
|
||||
}
|
||||
|
||||
__inline static _list *get_list_head(_queue *queue)
|
||||
{
|
||||
return (&(queue->queue));
|
||||
}
|
||||
|
||||
|
||||
#define LIST_CONTAINOR(ptr, type, member) \
|
||||
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
|
||||
|
||||
|
||||
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_lock_irqsave(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_unlock_irqrestore(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_lock_irqsave(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_unlock_irqrestore(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_lock_bh(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_unlock_bh(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
|
||||
{
|
||||
|
||||
mtx_lock(pmutex);
|
||||
|
||||
}
|
||||
|
||||
|
||||
__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
|
||||
{
|
||||
|
||||
mtx_unlock(pmutex);
|
||||
|
||||
}
|
||||
static inline void __list_del(struct list_head * prev, struct list_head * next)
|
||||
{
|
||||
next->prev = prev;
|
||||
prev->next = next;
|
||||
}
|
||||
static inline void INIT_LIST_HEAD(struct list_head *list)
|
||||
{
|
||||
list->next = list;
|
||||
list->prev = list;
|
||||
}
|
||||
__inline static void rtw_list_delete(_list *plist)
|
||||
{
|
||||
__list_del(plist->prev, plist->next);
|
||||
INIT_LIST_HEAD(plist);
|
||||
}
|
||||
|
||||
static inline void timer_hdl(void *ctx)
|
||||
{
|
||||
_timer *timer = (_timer *)ctx;
|
||||
|
||||
rtw_mtx_lock(NULL);
|
||||
if (callout_pending(&timer->callout)) {
|
||||
/* callout was reset */
|
||||
rtw_mtx_unlock(NULL);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!callout_active(&timer->callout)) {
|
||||
/* callout was stopped */
|
||||
rtw_mtx_unlock(NULL);
|
||||
return;
|
||||
}
|
||||
|
||||
callout_deactivate(&timer->callout);
|
||||
|
||||
timer->function(timer->arg);
|
||||
|
||||
rtw_mtx_unlock(NULL);
|
||||
}
|
||||
|
||||
static inline void _init_timer(_timer *ptimer, _nic_hdl padapter, void *pfunc, void *cntx)
|
||||
{
|
||||
ptimer->function = pfunc;
|
||||
ptimer->arg = cntx;
|
||||
callout_init(&ptimer->callout, CALLOUT_MPSAFE);
|
||||
}
|
||||
|
||||
__inline static void _set_timer(_timer *ptimer,u32 delay_time)
|
||||
{
|
||||
if (ptimer->function && ptimer->arg) {
|
||||
rtw_mtx_lock(NULL);
|
||||
callout_reset(&ptimer->callout, delay_time, timer_hdl, ptimer);
|
||||
rtw_mtx_unlock(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled)
|
||||
{
|
||||
rtw_mtx_lock(NULL);
|
||||
callout_drain(&ptimer->callout);
|
||||
rtw_mtx_unlock(NULL);
|
||||
*bcancelled = 1; /* assume an pending timer to be canceled */
|
||||
}
|
||||
|
||||
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
|
||||
{
|
||||
printf("%s Not implement yet! \n",__FUNCTION__);
|
||||
}
|
||||
|
||||
__inline static void _set_workitem(_workitem *pwork)
|
||||
{
|
||||
printf("%s Not implement yet! \n",__FUNCTION__);
|
||||
// schedule_work(pwork);
|
||||
}
|
||||
|
||||
//
|
||||
// Global Mutex: can only be used at PASSIVE level.
|
||||
//
|
||||
|
||||
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
}
|
||||
|
||||
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
}
|
||||
|
||||
#define ATOMIC_INIT(i) { (i) }
|
||||
|
||||
static __inline void thread_enter(char *name);
|
||||
|
||||
//Atomic integer operations
|
||||
typedef uint32_t ATOMIC_T ;
|
||||
|
||||
#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc)
|
||||
|
||||
#define rtw_free_netdev(netdev) if_free((netdev))
|
||||
|
||||
#define NDEV_FMT "%s"
|
||||
#define NDEV_ARG(ndev) ""
|
||||
#define ADPT_FMT "%s"
|
||||
#define ADPT_ARG(adapter) ""
|
||||
#define FUNC_NDEV_FMT "%s"
|
||||
#define FUNC_NDEV_ARG(ndev) __func__
|
||||
#define FUNC_ADPT_FMT "%s"
|
||||
#define FUNC_ADPT_ARG(adapter) __func__
|
||||
|
||||
#define STRUCT_PACKED
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __OSDEP_CE_SERVICE_H_
|
||||
#define __OSDEP_CE_SERVICE_H_
|
||||
|
||||
|
||||
#include <ndis.h>
|
||||
#include <ntddndis.h>
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#include "SDCardDDK.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#include <usbdi.h>
|
||||
#endif
|
||||
|
||||
typedef HANDLE _sema;
|
||||
typedef LIST_ENTRY _list;
|
||||
typedef NDIS_STATUS _OS_STATUS;
|
||||
|
||||
typedef NDIS_SPIN_LOCK _lock;
|
||||
|
||||
typedef HANDLE _rwlock; //Mutex
|
||||
|
||||
typedef u32 _irqL;
|
||||
|
||||
typedef NDIS_HANDLE _nic_hdl;
|
||||
|
||||
struct rtw_timer_list {
|
||||
NDIS_MINIPORT_TIMER ndis_timer;
|
||||
void (*function)(void *);
|
||||
void *arg;
|
||||
};
|
||||
|
||||
struct __queue {
|
||||
LIST_ENTRY queue;
|
||||
_lock lock;
|
||||
};
|
||||
|
||||
typedef NDIS_PACKET _pkt;
|
||||
typedef NDIS_BUFFER _buffer;
|
||||
typedef struct __queue _queue;
|
||||
|
||||
typedef HANDLE _thread_hdl_;
|
||||
typedef DWORD thread_return;
|
||||
typedef void* thread_context;
|
||||
typedef NDIS_WORK_ITEM _workitem;
|
||||
|
||||
|
||||
|
||||
#define SEMA_UPBND (0x7FFFFFFF) //8192
|
||||
|
||||
__inline static _list *get_prev(_list *list)
|
||||
{
|
||||
return list->Blink;
|
||||
}
|
||||
|
||||
__inline static _list *get_next(_list *list)
|
||||
{
|
||||
return list->Flink;
|
||||
}
|
||||
|
||||
__inline static _list *get_list_head(_queue *queue)
|
||||
{
|
||||
return (&(queue->queue));
|
||||
}
|
||||
|
||||
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
|
||||
|
||||
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisAcquireSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisReleaseSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisDprAcquireSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisDprReleaseSpinLock(plock);
|
||||
}
|
||||
|
||||
|
||||
__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
|
||||
{
|
||||
WaitForSingleObject(*prwlock, INFINITE );
|
||||
|
||||
}
|
||||
|
||||
__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL)
|
||||
{
|
||||
ReleaseMutex(*prwlock);
|
||||
}
|
||||
|
||||
__inline static void rtw_list_delete(_list *plist)
|
||||
{
|
||||
RemoveEntryList(plist);
|
||||
InitializeListHead(plist);
|
||||
}
|
||||
|
||||
static inline void timer_hdl(
|
||||
IN PVOID SystemSpecific1,
|
||||
IN PVOID FunctionContext,
|
||||
IN PVOID SystemSpecific2,
|
||||
IN PVOID SystemSpecific3)
|
||||
{
|
||||
_timer *timer = (_timer *)FunctionContext;
|
||||
|
||||
timer->function(timer->arg);
|
||||
}
|
||||
|
||||
static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
|
||||
{
|
||||
ptimer->function = pfunc;
|
||||
ptimer->arg = cntx;
|
||||
NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
|
||||
}
|
||||
|
||||
static inline void _set_timer(_timer *ptimer, u32 delay_time)
|
||||
{
|
||||
NdisMSetTimer(ptimer, delay_time);
|
||||
}
|
||||
|
||||
static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
|
||||
{
|
||||
NdisMCancelTimer(ptimer, bcancelled);
|
||||
}
|
||||
|
||||
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
|
||||
{
|
||||
|
||||
NdisInitializeWorkItem(pwork, pfunc, cntx);
|
||||
}
|
||||
|
||||
__inline static void _set_workitem(_workitem *pwork)
|
||||
{
|
||||
NdisScheduleWorkItem(pwork);
|
||||
}
|
||||
|
||||
#define ATOMIC_INIT(i) { (i) }
|
||||
|
||||
//
|
||||
// Global Mutex: can only be used at PASSIVE level.
|
||||
//
|
||||
|
||||
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
|
||||
{ \
|
||||
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
|
||||
NdisMSleep(10000); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
|
||||
}
|
||||
|
||||
// limitation of path length
|
||||
#define PATH_LENGTH_MAX MAX_PATH
|
||||
|
||||
//Atomic integer operations
|
||||
#define ATOMIC_T LONG
|
||||
|
||||
#define NDEV_FMT "%s"
|
||||
#define NDEV_ARG(ndev) ""
|
||||
#define ADPT_FMT "%s"
|
||||
#define ADPT_ARG(adapter) ""
|
||||
#define FUNC_NDEV_FMT "%s"
|
||||
#define FUNC_NDEV_ARG(ndev) __func__
|
||||
#define FUNC_ADPT_FMT "%s"
|
||||
#define FUNC_ADPT_ARG(adapter) __func__
|
||||
|
||||
#define STRUCT_PACKED
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,564 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __OSDEP_LINUX_SERVICE_H_
|
||||
#define __OSDEP_LINUX_SERVICE_H_
|
||||
|
||||
#include <linux/version.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/namei.h>
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 5))
|
||||
#include <linux/kref.h>
|
||||
#endif
|
||||
/* #include <linux/smp_lock.h> */
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/inetdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/circ_buf.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/io.h>
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
|
||||
#include <asm/semaphore.h>
|
||||
#else
|
||||
#include <linux/semaphore.h>
|
||||
#endif
|
||||
#include <linux/sem.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/wireless.h>
|
||||
#include <net/iw_handler.h>
|
||||
#include <net/addrconf.h>
|
||||
#include <linux/if_arp.h>
|
||||
#include <linux/rtnetlink.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h> /* for struct tasklet_struct */
|
||||
#include <linux/ip.h>
|
||||
#include <linux/kthread.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0))
|
||||
#include <uapi/linux/sched/types.h>
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 5, 41))
|
||||
#include <linux/tqueue.h>
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0))
|
||||
#include <uapi/linux/limits.h>
|
||||
#else
|
||||
#include <linux/limits.h>
|
||||
#endif
|
||||
|
||||
#ifdef RTK_DMP_PLATFORM
|
||||
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 12))
|
||||
#include <linux/pageremap.h>
|
||||
#endif
|
||||
#include <asm/io.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NET_RADIO
|
||||
#define CONFIG_WIRELESS_EXT
|
||||
#endif
|
||||
|
||||
/* Monitor mode */
|
||||
#include <net/ieee80211_radiotap.h>
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
|
||||
#include <linux/ieee80211.h>
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25) && \
|
||||
LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29))
|
||||
#define CONFIG_IEEE80211_HT_ADDT_INFO
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IOCTL_CFG80211
|
||||
/* #include <linux/ieee80211.h> */
|
||||
#include <net/cfg80211.h>
|
||||
#else
|
||||
#ifdef CONFIG_REGD_SRC_FROM_OS
|
||||
#error "CONFIG_REGD_SRC_FROM_OS requires CONFIG_IOCTL_CFG80211"
|
||||
#endif
|
||||
#endif /* CONFIG_IOCTL_CFG80211 */
|
||||
|
||||
|
||||
#ifdef CONFIG_HAS_EARLYSUSPEND
|
||||
#include <linux/earlysuspend.h>
|
||||
#endif /* CONFIG_HAS_EARLYSUSPEND */
|
||||
|
||||
#ifdef CONFIG_EFUSE_CONFIG_FILE
|
||||
#include <linux/fs.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#include <linux/usb.h>
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 21))
|
||||
#include <linux/usb_ch9.h>
|
||||
#else
|
||||
#include <linux/usb/ch9.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST_SOCKET_TRX
|
||||
#include <net/sock.h>
|
||||
#include <net/tcp.h>
|
||||
#include <linux/udp.h>
|
||||
#include <linux/in.h>
|
||||
#include <linux/netlink.h>
|
||||
#endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
typedef struct urb *PURB;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTW_GRO) && (!defined(CONFIG_RTW_NAPI))
|
||||
|
||||
#error "Enable NAPI before enable GRO\n"
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if (KERNEL_VERSION(2, 6, 29) > LINUX_VERSION_CODE && defined(CONFIG_RTW_NAPI))
|
||||
|
||||
#undef CONFIG_RTW_NAPI
|
||||
/*#warning "Linux Kernel version too old to support NAPI (should newer than 2.6.29)\n"*/
|
||||
|
||||
#endif
|
||||
|
||||
#if (KERNEL_VERSION(2, 6, 33) > LINUX_VERSION_CODE && defined(CONFIG_RTW_GRO))
|
||||
|
||||
#undef CONFIG_RTW_GRO
|
||||
/*#warning "Linux Kernel version too old to support GRO(should newer than 2.6.33)\n"*/
|
||||
|
||||
#endif
|
||||
|
||||
typedef struct semaphore _sema;
|
||||
typedef spinlock_t _lock;
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
|
||||
typedef struct mutex _mutex;
|
||||
#else
|
||||
typedef struct semaphore _mutex;
|
||||
#endif
|
||||
struct rtw_timer_list {
|
||||
struct timer_list timer;
|
||||
void (*function)(void *);
|
||||
void *arg;
|
||||
};
|
||||
|
||||
typedef struct rtw_timer_list _timer;
|
||||
typedef struct completion _completion;
|
||||
|
||||
struct __queue {
|
||||
struct list_head queue;
|
||||
_lock lock;
|
||||
};
|
||||
|
||||
typedef struct sk_buff _pkt;
|
||||
typedef unsigned char _buffer;
|
||||
|
||||
typedef struct __queue _queue;
|
||||
typedef struct list_head _list;
|
||||
|
||||
/* hlist */
|
||||
typedef struct hlist_head rtw_hlist_head;
|
||||
typedef struct hlist_node rtw_hlist_node;
|
||||
|
||||
/* RCU */
|
||||
typedef struct rcu_head rtw_rcu_head;
|
||||
#define rtw_rcu_dereference(p) rcu_dereference((p))
|
||||
#define rtw_rcu_dereference_protected(p, c) rcu_dereference_protected(p, c)
|
||||
#define rtw_rcu_assign_pointer(p, v) rcu_assign_pointer((p), (v))
|
||||
#define rtw_rcu_read_lock() rcu_read_lock()
|
||||
#define rtw_rcu_read_unlock() rcu_read_unlock()
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 34))
|
||||
#define rtw_rcu_access_pointer(p) rcu_access_pointer(p)
|
||||
#endif
|
||||
|
||||
/* rhashtable */
|
||||
#include "../os_dep/linux/rtw_rhashtable.h"
|
||||
|
||||
typedef int _OS_STATUS;
|
||||
/* typedef u32 _irqL; */
|
||||
typedef unsigned long _irqL;
|
||||
typedef struct net_device *_nic_hdl;
|
||||
|
||||
typedef void *_thread_hdl_;
|
||||
typedef int thread_return;
|
||||
typedef void *thread_context;
|
||||
|
||||
typedef void timer_hdl_return;
|
||||
typedef void *timer_hdl_context;
|
||||
|
||||
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
|
||||
typedef struct work_struct _workitem;
|
||||
#else
|
||||
typedef struct tq_struct _workitem;
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
|
||||
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
|
||||
#endif
|
||||
|
||||
typedef unsigned long systime;
|
||||
typedef ktime_t sysptime;
|
||||
typedef struct tasklet_struct _tasklet;
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22))
|
||||
/* Porting from linux kernel, for compatible with old kernel. */
|
||||
static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb)
|
||||
{
|
||||
return skb->tail;
|
||||
}
|
||||
|
||||
static inline void skb_reset_tail_pointer(struct sk_buff *skb)
|
||||
{
|
||||
skb->tail = skb->data;
|
||||
}
|
||||
|
||||
static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
|
||||
{
|
||||
skb->tail = skb->data + offset;
|
||||
}
|
||||
|
||||
static inline unsigned char *skb_end_pointer(const struct sk_buff *skb)
|
||||
{
|
||||
return skb->end;
|
||||
}
|
||||
#endif
|
||||
|
||||
__inline static void rtw_list_delete(_list *plist)
|
||||
{
|
||||
list_del_init(plist);
|
||||
}
|
||||
|
||||
__inline static _list *get_next(_list *list)
|
||||
{
|
||||
return list->next;
|
||||
}
|
||||
|
||||
#define LIST_CONTAINOR(ptr, type, member) \
|
||||
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
|
||||
|
||||
#define rtw_list_first_entry(ptr, type, member) list_first_entry(ptr, type, member)
|
||||
|
||||
#define rtw_hlist_for_each_entry(pos, head, member) hlist_for_each_entry(pos, head, member)
|
||||
#define rtw_hlist_for_each_safe(pos, n, head) hlist_for_each_safe(pos, n, head)
|
||||
#define rtw_hlist_entry(ptr, type, member) hlist_entry(ptr, type, member)
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))
|
||||
#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, n, head, member)
|
||||
#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, head, member)
|
||||
#else
|
||||
#define rtw_hlist_for_each_entry_safe(pos, np, n, head, member) hlist_for_each_entry_safe(pos, np, n, head, member)
|
||||
#define rtw_hlist_for_each_entry_rcu(pos, node, head, member) hlist_for_each_entry_rcu(pos, node, head, member)
|
||||
#endif
|
||||
|
||||
__inline static void _enter_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_lock_irqsave(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_unlock_irqrestore(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_lock_irqsave(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_unlock_irqrestore(plock, *pirqL);
|
||||
}
|
||||
|
||||
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_lock_bh(plock);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
spin_unlock_bh(plock);
|
||||
}
|
||||
|
||||
__inline static void enter_critical_bh(_lock *plock)
|
||||
{
|
||||
spin_lock_bh(plock);
|
||||
}
|
||||
|
||||
__inline static void exit_critical_bh(_lock *plock)
|
||||
{
|
||||
spin_unlock_bh(plock);
|
||||
}
|
||||
|
||||
__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
|
||||
{
|
||||
int ret = 0;
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
|
||||
/* mutex_lock(pmutex); */
|
||||
ret = mutex_lock_interruptible(pmutex);
|
||||
#else
|
||||
ret = down_interruptible(pmutex);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
__inline static int _enter_critical_mutex_lock(_mutex *pmutex, _irqL *pirqL)
|
||||
{
|
||||
int ret = 0;
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
|
||||
mutex_lock(pmutex);
|
||||
#else
|
||||
down(pmutex);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
|
||||
mutex_unlock(pmutex);
|
||||
#else
|
||||
up(pmutex);
|
||||
#endif
|
||||
}
|
||||
|
||||
__inline static _list *get_list_head(_queue *queue)
|
||||
{
|
||||
return &(queue->queue);
|
||||
}
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
|
||||
static inline void timer_hdl(struct timer_list *in_timer)
|
||||
#else
|
||||
static inline void timer_hdl(unsigned long cntx)
|
||||
#endif
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
|
||||
_timer *ptimer = from_timer(ptimer, in_timer, timer);
|
||||
#else
|
||||
_timer *ptimer = (_timer *)cntx;
|
||||
#endif
|
||||
ptimer->function(ptimer->arg);
|
||||
}
|
||||
|
||||
__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
|
||||
{
|
||||
ptimer->function = pfunc;
|
||||
ptimer->arg = cntx;
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
|
||||
timer_setup(&ptimer->timer, timer_hdl, 0);
|
||||
#else
|
||||
/* setup_timer(ptimer, pfunc,(u32)cntx); */
|
||||
ptimer->timer.function = timer_hdl;
|
||||
ptimer->timer.data = (unsigned long)ptimer;
|
||||
init_timer(&ptimer->timer);
|
||||
#endif
|
||||
}
|
||||
|
||||
__inline static void _set_timer(_timer *ptimer, u32 delay_time)
|
||||
{
|
||||
mod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000)));
|
||||
}
|
||||
|
||||
__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled)
|
||||
{
|
||||
*bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0;
|
||||
}
|
||||
|
||||
__inline static void _cancel_timer_async(_timer *ptimer)
|
||||
{
|
||||
del_timer(&ptimer->timer);
|
||||
}
|
||||
|
||||
static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20))
|
||||
INIT_WORK(pwork, pfunc);
|
||||
#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
|
||||
INIT_WORK(pwork, pfunc, pwork);
|
||||
#else
|
||||
INIT_TQUEUE(pwork, pfunc, pwork);
|
||||
#endif
|
||||
}
|
||||
|
||||
__inline static void _set_workitem(_workitem *pwork)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
|
||||
schedule_work(pwork);
|
||||
#else
|
||||
schedule_task(pwork);
|
||||
#endif
|
||||
}
|
||||
|
||||
__inline static void _cancel_workitem_sync(_workitem *pwork)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22))
|
||||
cancel_work_sync(pwork);
|
||||
#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
|
||||
flush_scheduled_work();
|
||||
#else
|
||||
flush_scheduled_tasks();
|
||||
#endif
|
||||
}
|
||||
/*
|
||||
* Global Mutex: can only be used at PASSIVE level.
|
||||
* */
|
||||
|
||||
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1) { \
|
||||
atomic_dec((atomic_t *)&(_MutexCounter)); \
|
||||
msleep(10); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
atomic_dec((atomic_t *)&(_MutexCounter)); \
|
||||
}
|
||||
|
||||
static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
|
||||
return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) &&
|
||||
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) &&
|
||||
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) &&
|
||||
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)));
|
||||
#else
|
||||
return netif_queue_stopped(pnetdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void rtw_netif_wake_queue(struct net_device *pnetdev)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
|
||||
netif_tx_wake_all_queues(pnetdev);
|
||||
#else
|
||||
netif_wake_queue(pnetdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void rtw_netif_start_queue(struct net_device *pnetdev)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
|
||||
netif_tx_start_all_queues(pnetdev);
|
||||
#else
|
||||
netif_start_queue(pnetdev);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void rtw_netif_stop_queue(struct net_device *pnetdev)
|
||||
{
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35))
|
||||
netif_tx_stop_all_queues(pnetdev);
|
||||
#else
|
||||
netif_stop_queue(pnetdev);
|
||||
#endif
|
||||
}
|
||||
static inline void rtw_netif_device_attach(struct net_device *pnetdev)
|
||||
{
|
||||
netif_device_attach(pnetdev);
|
||||
}
|
||||
static inline void rtw_netif_device_detach(struct net_device *pnetdev)
|
||||
{
|
||||
netif_device_detach(pnetdev);
|
||||
}
|
||||
static inline void rtw_netif_carrier_on(struct net_device *pnetdev)
|
||||
{
|
||||
netif_carrier_on(pnetdev);
|
||||
}
|
||||
static inline void rtw_netif_carrier_off(struct net_device *pnetdev)
|
||||
{
|
||||
netif_carrier_off(pnetdev);
|
||||
}
|
||||
|
||||
static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2)
|
||||
{
|
||||
int len = 0;
|
||||
len += snprintf(dst + len, dst_len - len, "%s", src1);
|
||||
len += snprintf(dst + len, dst_len - len, "%s", src2);
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
|
||||
#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1)
|
||||
#else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
|
||||
#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1)
|
||||
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) */
|
||||
|
||||
|
||||
/* Suspend lock prevent system from going suspend */
|
||||
#ifdef CONFIG_WAKELOCK
|
||||
#include <linux/wakelock.h>
|
||||
#elif defined(CONFIG_ANDROID_POWER)
|
||||
#include <linux/android_power.h>
|
||||
#endif
|
||||
|
||||
/* limitation of path length */
|
||||
#define PATH_LENGTH_MAX PATH_MAX
|
||||
|
||||
/* Atomic integer operations */
|
||||
#define ATOMIC_T atomic_t
|
||||
|
||||
#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv)
|
||||
|
||||
#define NDEV_FMT "%s"
|
||||
#define NDEV_ARG(ndev) ndev->name
|
||||
#define ADPT_FMT "%s"
|
||||
#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL)
|
||||
#define FUNC_NDEV_FMT "%s(%s)"
|
||||
#define FUNC_NDEV_ARG(ndev) __func__, ndev->name
|
||||
#define FUNC_ADPT_FMT "%s(%s)"
|
||||
#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL)
|
||||
|
||||
struct rtw_netdev_priv_indicator {
|
||||
void *priv;
|
||||
u32 sizeof_priv;
|
||||
};
|
||||
struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
|
||||
extern struct net_device *rtw_alloc_etherdev(int sizeof_priv);
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
|
||||
#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(name)
|
||||
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26))
|
||||
#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(ndev->nd_net, name)
|
||||
#else
|
||||
#define rtw_get_same_net_ndev_by_name(ndev, name) dev_get_by_name(dev_net(ndev), name)
|
||||
#endif
|
||||
|
||||
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
|
||||
#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(name)
|
||||
#else
|
||||
#define rtw_get_bridge_ndev_by_name(name) dev_get_by_name(&init_net, name)
|
||||
#endif
|
||||
|
||||
#define STRUCT_PACKED __attribute__ ((packed))
|
||||
|
||||
|
||||
#endif /* __OSDEP_LINUX_SERVICE_H_ */
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __OSDEP_LINUX_SERVICE_H_
|
||||
#define __OSDEP_LINUX_SERVICE_H_
|
||||
|
||||
#include <ndis.h>
|
||||
#include <ntddk.h>
|
||||
#include <ntddndis.h>
|
||||
#include <ntdef.h>
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#include <usb.h>
|
||||
#include <usbioctl.h>
|
||||
#include <usbdlib.h>
|
||||
#endif
|
||||
|
||||
typedef KSEMAPHORE _sema;
|
||||
typedef LIST_ENTRY _list;
|
||||
typedef NDIS_STATUS _OS_STATUS;
|
||||
|
||||
|
||||
typedef NDIS_SPIN_LOCK _lock;
|
||||
|
||||
typedef KMUTEX _mutex;
|
||||
|
||||
typedef KIRQL _irqL;
|
||||
|
||||
// USB_PIPE for WINCE , but handle can be use just integer under windows
|
||||
typedef NDIS_HANDLE _nic_hdl;
|
||||
|
||||
struct rtw_timer_list {
|
||||
NDIS_MINIPORT_TIMER ndis_timer;
|
||||
void (*function)(void *);
|
||||
void *arg;
|
||||
};
|
||||
|
||||
struct __queue {
|
||||
LIST_ENTRY queue;
|
||||
_lock lock;
|
||||
};
|
||||
|
||||
typedef NDIS_PACKET _pkt;
|
||||
typedef NDIS_BUFFER _buffer;
|
||||
typedef struct __queue _queue;
|
||||
|
||||
typedef PKTHREAD _thread_hdl_;
|
||||
typedef void thread_return;
|
||||
typedef void* thread_context;
|
||||
|
||||
typedef NDIS_WORK_ITEM _workitem;
|
||||
|
||||
|
||||
#define HZ 10000000
|
||||
#define SEMA_UPBND (0x7FFFFFFF) //8192
|
||||
|
||||
__inline static _list *get_next(_list *list)
|
||||
{
|
||||
return list->Flink;
|
||||
}
|
||||
|
||||
__inline static _list *get_list_head(_queue *queue)
|
||||
{
|
||||
return (&(queue->queue));
|
||||
}
|
||||
|
||||
|
||||
#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member)
|
||||
|
||||
|
||||
__inline static _enter_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisAcquireSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static _exit_critical(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisReleaseSpinLock(plock);
|
||||
}
|
||||
|
||||
|
||||
__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisDprAcquireSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisDprReleaseSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisDprAcquireSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL)
|
||||
{
|
||||
NdisDprReleaseSpinLock(plock);
|
||||
}
|
||||
|
||||
__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL)
|
||||
{
|
||||
KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL);
|
||||
}
|
||||
|
||||
|
||||
__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL)
|
||||
{
|
||||
KeReleaseMutex(pmutex, FALSE);
|
||||
}
|
||||
|
||||
|
||||
__inline static void rtw_list_delete(_list *plist)
|
||||
{
|
||||
RemoveEntryList(plist);
|
||||
InitializeListHead(plist);
|
||||
}
|
||||
|
||||
static inline void timer_hdl(
|
||||
IN PVOID SystemSpecific1,
|
||||
IN PVOID FunctionContext,
|
||||
IN PVOID SystemSpecific2,
|
||||
IN PVOID SystemSpecific3)
|
||||
{
|
||||
_timer *timer = (_timer *)FunctionContext;
|
||||
|
||||
timer->function(timer->arg);
|
||||
}
|
||||
|
||||
static inline void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
|
||||
{
|
||||
ptimer->function = pfunc;
|
||||
ptimer->arg = cntx;
|
||||
NdisMInitializeTimer(&ptimer->ndis_timer, nic_hdl, timer_hdl, ptimer);
|
||||
}
|
||||
|
||||
static inline void _set_timer(_timer *ptimer, u32 delay_time)
|
||||
{
|
||||
NdisMSetTimer(ptimer, delay_time);
|
||||
}
|
||||
|
||||
static inline void _cancel_timer(_timer *ptimer, u8 *bcancelled)
|
||||
{
|
||||
NdisMCancelTimer(ptimer, bcancelled);
|
||||
}
|
||||
|
||||
__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx)
|
||||
{
|
||||
|
||||
NdisInitializeWorkItem(pwork, pfunc, cntx);
|
||||
}
|
||||
|
||||
__inline static void _set_workitem(_workitem *pwork)
|
||||
{
|
||||
NdisScheduleWorkItem(pwork);
|
||||
}
|
||||
|
||||
|
||||
#define ATOMIC_INIT(i) { (i) }
|
||||
|
||||
//
|
||||
// Global Mutex: can only be used at PASSIVE level.
|
||||
//
|
||||
|
||||
#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\
|
||||
{ \
|
||||
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
|
||||
NdisMSleep(10000); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \
|
||||
{ \
|
||||
NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \
|
||||
}
|
||||
|
||||
// limitation of path length
|
||||
#define PATH_LENGTH_MAX MAX_PATH
|
||||
|
||||
//Atomic integer operations
|
||||
#define ATOMIC_T LONG
|
||||
|
||||
|
||||
#define NDEV_FMT "%s"
|
||||
#define NDEV_ARG(ndev) ""
|
||||
#define ADPT_FMT "%s"
|
||||
#define ADPT_ARG(adapter) ""
|
||||
#define FUNC_NDEV_FMT "%s"
|
||||
#define FUNC_NDEV_ARG(ndev) __func__
|
||||
#define FUNC_ADPT_FMT "%s"
|
||||
#define FUNC_ADPT_ARG(adapter) __func__
|
||||
|
||||
#define STRUCT_PACKED
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __PCI_HAL_H__
|
||||
#define __PCI_HAL_H__
|
||||
|
||||
#ifdef CONFIG_RTL8188E
|
||||
void rtl8188ee_set_hal_ops(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
|
||||
void rtl8812ae_set_hal_ops(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8192E)
|
||||
void rtl8192ee_set_hal_ops(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8192F)
|
||||
void rtl8192fe_set_hal_ops(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723B
|
||||
void rtl8723be_set_hal_ops(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723D
|
||||
void rtl8723de_set_hal_ops(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8814A
|
||||
void rtl8814ae_set_hal_ops(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8822B
|
||||
void rtl8822be_set_hal_ops(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8822C
|
||||
void rtl8822ce_set_hal_ops(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8814B
|
||||
void rtl8814be_set_hal_ops(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
u8 rtw_set_hal_ops(_adapter *padapter);
|
||||
|
||||
#endif /* __PCIE_HAL_H__ */
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __PCI_OPS_H_
|
||||
#define __PCI_OPS_H_
|
||||
|
||||
|
||||
#ifdef CONFIG_RTL8188E
|
||||
u32 rtl8188ee_init_desc_ring(_adapter *padapter);
|
||||
u32 rtl8188ee_free_desc_ring(_adapter *padapter);
|
||||
void rtl8188ee_reset_desc_ring(_adapter *padapter);
|
||||
int rtl8188ee_interrupt(PADAPTER Adapter);
|
||||
void rtl8188ee_xmit_tasklet(void *priv);
|
||||
void rtl8188ee_recv_tasklet(void *priv);
|
||||
void rtl8188ee_prepare_bcn_tasklet(void *priv);
|
||||
void rtl8188ee_set_intf_ops(struct _io_ops *pops);
|
||||
void rtw8188ee_unmap_beacon_icf(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
|
||||
u32 rtl8812ae_init_desc_ring(_adapter *padapter);
|
||||
u32 rtl8812ae_free_desc_ring(_adapter *padapter);
|
||||
void rtl8812ae_reset_desc_ring(_adapter *padapter);
|
||||
int rtl8812ae_interrupt(PADAPTER Adapter);
|
||||
void rtl8812ae_xmit_tasklet(void *priv);
|
||||
void rtl8812ae_recv_tasklet(void *priv);
|
||||
void rtl8812ae_prepare_bcn_tasklet(void *priv);
|
||||
void rtl8812ae_set_intf_ops(struct _io_ops *pops);
|
||||
void rtw8812ae_unmap_beacon_icf(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192E
|
||||
u32 rtl8192ee_init_desc_ring(_adapter *padapter);
|
||||
u32 rtl8192ee_free_desc_ring(_adapter *padapter);
|
||||
void rtl8192ee_reset_desc_ring(_adapter *padapter);
|
||||
void rtl8192ee_recv_tasklet(void *priv);
|
||||
void rtl8192ee_prepare_bcn_tasklet(void *priv);
|
||||
int rtl8192ee_interrupt(PADAPTER Adapter);
|
||||
void rtl8192ee_set_intf_ops(struct _io_ops *pops);
|
||||
void rtw8192ee_unmap_beacon_icf(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8192F
|
||||
u32 rtl8192fe_init_desc_ring(_adapter *padapter);
|
||||
u32 rtl8192fe_free_desc_ring(_adapter *padapter);
|
||||
void rtl8192fe_reset_desc_ring(_adapter *padapter);
|
||||
int rtl8192fe_interrupt(PADAPTER Adapter);
|
||||
void rtl8192fe_recv_tasklet(void *priv);
|
||||
void rtl8192fe_prepare_bcn_tasklet(void *priv);
|
||||
void rtl8192fe_set_intf_ops(struct _io_ops *pops);
|
||||
u8 check_tx_desc_resource(_adapter *padapter, int prio);
|
||||
void rtl8192fe_unmap_beacon_icf(PADAPTER Adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723B
|
||||
u32 rtl8723be_init_desc_ring(_adapter *padapter);
|
||||
u32 rtl8723be_free_desc_ring(_adapter *padapter);
|
||||
void rtl8723be_reset_desc_ring(_adapter *padapter);
|
||||
int rtl8723be_interrupt(PADAPTER Adapter);
|
||||
void rtl8723be_recv_tasklet(void *priv);
|
||||
void rtl8723be_prepare_bcn_tasklet(void *priv);
|
||||
void rtl8723be_set_intf_ops(struct _io_ops *pops);
|
||||
void rtl8723be_unmap_beacon_icf(PADAPTER Adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8723D
|
||||
u32 rtl8723de_init_desc_ring(_adapter *padapter);
|
||||
u32 rtl8723de_free_desc_ring(_adapter *padapter);
|
||||
void rtl8723de_reset_desc_ring(_adapter *padapter);
|
||||
int rtl8723de_interrupt(PADAPTER Adapter);
|
||||
void rtl8723de_recv_tasklet(void *priv);
|
||||
void rtl8723de_prepare_bcn_tasklet(void *priv);
|
||||
void rtl8723de_set_intf_ops(struct _io_ops *pops);
|
||||
u8 check_tx_desc_resource(_adapter *padapter, int prio);
|
||||
void rtl8723de_unmap_beacon_icf(PADAPTER Adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8814A
|
||||
u32 rtl8814ae_init_desc_ring(_adapter *padapter);
|
||||
u32 rtl8814ae_free_desc_ring(_adapter *padapter);
|
||||
void rtl8814ae_reset_desc_ring(_adapter *padapter);
|
||||
int rtl8814ae_interrupt(PADAPTER Adapter);
|
||||
void rtl8814ae_xmit_tasklet(void *priv);
|
||||
void rtl8814ae_recv_tasklet(void *priv);
|
||||
void rtl8814ae_prepare_bcn_tasklet(void *priv);
|
||||
void rtl8814ae_set_intf_ops(struct _io_ops *pops);
|
||||
void rtl8814ae_unmap_beacon_icf(PADAPTER Adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8822B
|
||||
void rtl8822be_set_intf_ops(struct _io_ops *pops);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8821C
|
||||
void rtl8821ce_set_intf_ops(struct _io_ops *pops);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8822C
|
||||
void rtl8822ce_set_intf_ops(struct _io_ops *pops);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RTL8814B
|
||||
void rtl8814be_set_intf_ops(struct _io_ops *pops);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __PCI_OSINTF_H
|
||||
#define __PCI_OSINTF_H
|
||||
|
||||
#ifdef CONFIG_PLATFORM_RTK129X
|
||||
#define PCIE_SLOT1_MEM_START 0x9804F000
|
||||
#define PCIE_SLOT1_MEM_LEN 0x1000
|
||||
#define PCIE_SLOT1_CTRL_START 0x9804EC00
|
||||
|
||||
#define PCIE_SLOT2_MEM_START 0x9803C000
|
||||
#define PCIE_SLOT2_MEM_LEN 0x1000
|
||||
#define PCIE_SLOT2_CTRL_START 0x9803BC00
|
||||
|
||||
#define PCIE_MASK_OFFSET 0x100 /* mask offset from CTRL_START */
|
||||
#define PCIE_TRANSLATE_OFFSET 0x104 /* translate offset from CTRL_START */
|
||||
#endif
|
||||
|
||||
#define PCI_BC_CLK_REQ BIT0
|
||||
#define PCI_BC_ASPM_L0s BIT1
|
||||
#define PCI_BC_ASPM_L1 BIT2
|
||||
#define PCI_BC_ASPM_L1Off BIT3
|
||||
//#define PCI_BC_ASPM_LTR BIT4
|
||||
//#define PCI_BC_ASPM_OBFF BIT5
|
||||
|
||||
void PlatformClearPciPMEStatus(PADAPTER Adapter);
|
||||
void rtw_pci_aspm_config(_adapter *padapter);
|
||||
void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble);
|
||||
#ifdef CONFIG_PCI_DYNAMIC_ASPM
|
||||
void rtw_pci_set_aspm_lnkctl(_adapter *padapter, u8 mode);
|
||||
void rtw_pci_set_l1_latency(_adapter *padapter, u8 mode);
|
||||
|
||||
static inline void rtw_pci_dynamic_aspm_set_mode(_adapter *padapter, u8 mode)
|
||||
{
|
||||
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
|
||||
struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
|
||||
|
||||
if (mode == pcipriv->aspm_mode)
|
||||
return;
|
||||
|
||||
pcipriv->aspm_mode = mode;
|
||||
|
||||
#ifdef CONFIG_PCI_DYNAMIC_ASPM_LINK_CTRL
|
||||
rtw_pci_set_aspm_lnkctl(padapter, mode);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_DYNAMIC_ASPM_L1_LATENCY
|
||||
rtw_pci_set_l1_latency(padapter, mode);
|
||||
#endif
|
||||
}
|
||||
#else
|
||||
#define rtw_pci_dynamic_aspm_set_mode(adapter, mode)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RECV_OSDEP_H_
|
||||
#define __RECV_OSDEP_H_
|
||||
|
||||
|
||||
extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
|
||||
extern void _rtw_free_recv_priv(struct recv_priv *precvpriv);
|
||||
|
||||
|
||||
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
|
||||
void rtw_rframe_set_os_pkt(union recv_frame *rframe);
|
||||
extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
|
||||
extern void rtw_recv_returnpacket(_nic_hdl cnxt, _pkt *preturnedpkt);
|
||||
|
||||
#ifdef CONFIG_WIFI_MONITOR
|
||||
extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame);
|
||||
#endif /* CONFIG_WIFI_MONITOR */
|
||||
|
||||
#ifdef CONFIG_HOSTAPD_MLME
|
||||
extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
|
||||
#endif
|
||||
|
||||
struct sta_info;
|
||||
extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup);
|
||||
|
||||
|
||||
int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);
|
||||
int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);
|
||||
void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
|
||||
|
||||
|
||||
int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb);
|
||||
int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb);
|
||||
void rtw_os_free_recvframe(union recv_frame *precvframe);
|
||||
|
||||
|
||||
int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf, u32 size);
|
||||
int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
|
||||
_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, const u8 *da, const u8 *sa
|
||||
, u8 *msdu ,u16 msdu_len, enum rtw_rx_llc_hdl llc_hdl);
|
||||
void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, union recv_frame *rframe);
|
||||
|
||||
void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
|
||||
#ifdef PLATFORM_LINUX
|
||||
#ifdef CONFIG_RTW_NAPI
|
||||
#include <linux/netdevice.h> /* struct napi_struct */
|
||||
|
||||
int rtw_recv_napi_poll(struct napi_struct *, int budget);
|
||||
#ifdef CONFIG_RTW_NAPI_DYNAMIC
|
||||
void dynamic_napi_th_chk (_adapter *adapter);
|
||||
#endif /* CONFIG_RTW_NAPI_DYNAMIC */
|
||||
#endif /* CONFIG_RTW_NAPI */
|
||||
#endif /* PLATFORM_LINUX */
|
||||
|
||||
#endif /* */
|
||||
Loading…
Reference in New Issue