From e12437bd4c40104081bbc6e7926e5f8bd3877db8 Mon Sep 17 00:00:00 2001 From: ivanovborislav <81085106+ivanovborislav@users.noreply.github.com> Date: Sun, 21 Nov 2021 14:43:29 +0200 Subject: [PATCH] Add files via upload --- hal/phydm/ap_makefile.mk | 237 + hal/phydm/halhwimg.h | 137 + hal/phydm/mp_precomp.h | 24 + hal/phydm/phydm.c | 3826 ++++++++++++ hal/phydm/phydm.h | 1574 +++++ hal/phydm/phydm.mk | 249 + hal/phydm/phydm_adaptivity.c | 845 +++ hal/phydm/phydm_adaptivity.h | 126 + hal/phydm/phydm_adc_sampling.c | 1787 ++++++ hal/phydm/phydm_adc_sampling.h | 172 + hal/phydm/phydm_antdect.c | 888 +++ hal/phydm/phydm_antdect.h | 78 + hal/phydm/phydm_antdiv.c | 6640 +++++++++++++++++++++ hal/phydm/phydm_antdiv.h | 547 ++ hal/phydm/phydm_api.c | 3754 ++++++++++++ hal/phydm/phydm_api.h | 228 + hal/phydm/phydm_auto_dbg.c | 725 +++ hal/phydm/phydm_auto_dbg.h | 115 + hal/phydm/phydm_beamforming.c | 1989 ++++++ hal/phydm/phydm_beamforming.h | 363 ++ hal/phydm/phydm_cck_pd.c | 1918 ++++++ hal/phydm/phydm_cck_pd.h | 202 + hal/phydm/phydm_cck_rx_pathdiv.c | 163 + hal/phydm/phydm_cck_rx_pathdiv.h | 67 + hal/phydm/phydm_ccx.c | 3468 +++++++++++ hal/phydm/phydm_ccx.h | 429 ++ hal/phydm/phydm_cfotracking.c | 623 ++ hal/phydm/phydm_cfotracking.h | 74 + hal/phydm/phydm_debug.c | 6177 +++++++++++++++++++ hal/phydm/phydm_debug.h | 484 ++ hal/phydm/phydm_dfs.c | 2193 +++++++ hal/phydm/phydm_dfs.h | 191 + hal/phydm/phydm_dig.c | 3654 ++++++++++++ hal/phydm/phydm_dig.h | 393 ++ hal/phydm/phydm_direct_bf.c | 366 ++ hal/phydm/phydm_direct_bf.h | 44 + hal/phydm/phydm_dynamictxpower.c | 795 +++ hal/phydm/phydm_dynamictxpower.h | 142 + hal/phydm/phydm_features.h | 82 + hal/phydm/phydm_features_ap.h | 227 + hal/phydm/phydm_features_ce.h | 245 + hal/phydm/phydm_features_ce2_kernel.h | 84 + hal/phydm/phydm_features_iot.h | 177 + hal/phydm/phydm_features_win.h | 215 + hal/phydm/phydm_hwconfig.c | 1681 ++++++ hal/phydm/phydm_hwconfig.h | 79 + hal/phydm/phydm_interface.c | 1480 +++++ hal/phydm/phydm_interface.h | 328 + hal/phydm/phydm_lna_sat.c | 1688 ++++++ hal/phydm/phydm_lna_sat.h | 196 + hal/phydm/phydm_math_lib.c | 290 + hal/phydm/phydm_math_lib.h | 120 + hal/phydm/phydm_mp.c | 408 ++ hal/phydm/phydm_mp.h | 83 + hal/phydm/phydm_noisemonitor.c | 467 ++ hal/phydm/phydm_noisemonitor.h | 48 + hal/phydm/phydm_pathdiv.c | 1113 ++++ hal/phydm/phydm_pathdiv.h | 145 + hal/phydm/phydm_phystatus.c | 3245 ++++++++++ hal/phydm/phydm_phystatus.h | 1250 ++++ hal/phydm/phydm_pmac_tx_setting.c | 584 ++ hal/phydm/phydm_pmac_tx_setting.h | 111 + hal/phydm/phydm_pow_train.c | 171 + hal/phydm/phydm_pow_train.h | 84 + hal/phydm/phydm_pre_define.h | 1020 ++++ hal/phydm/phydm_precomp.h | 652 ++ hal/phydm/phydm_primary_cca.c | 173 + hal/phydm/phydm_primary_cca.h | 76 + hal/phydm/phydm_psd.c | 564 ++ hal/phydm/phydm_psd.h | 68 + hal/phydm/phydm_rainfo.c | 2432 ++++++++ hal/phydm/phydm_rainfo.h | 333 ++ hal/phydm/phydm_reg.h | 243 + hal/phydm/phydm_regdefine11ac.h | 109 + hal/phydm/phydm_regdefine11n.h | 220 + hal/phydm/phydm_regtable.h | 1122 ++++ hal/phydm/phydm_rssi_monitor.c | 189 + hal/phydm/phydm_rssi_monitor.h | 58 + hal/phydm/phydm_smt_ant.c | 2277 +++++++ hal/phydm/phydm_smt_ant.h | 210 + hal/phydm/phydm_soml.c | 1451 +++++ hal/phydm/phydm_soml.h | 199 + hal/phydm/phydm_types.h | 413 ++ hal/phydm/rtl8188e/hal8188erateadaptive.c | 1325 ++++ hal/phydm/rtl8188e/hal8188erateadaptive.h | 86 + hal/phydm/rtl8188e/hal8188ereg.h | 58 + hal/phydm/rtl8188e/halhwimg8188e_bb.c | 1779 ++++++ hal/phydm/rtl8188e/halhwimg8188e_bb.h | 51 + hal/phydm/rtl8188e/halhwimg8188e_mac.c | 283 + hal/phydm/rtl8188e/halhwimg8188e_mac.h | 33 + hal/phydm/rtl8188e/halhwimg8188e_rf.c | 2414 ++++++++ hal/phydm/rtl8188e/halhwimg8188e_rf.h | 118 + hal/phydm/rtl8188e/phydm_regconfig8188e.c | 181 + hal/phydm/rtl8188e/phydm_regconfig8188e.h | 44 + hal/phydm/rtl8188e/phydm_rtl8188e.c | 58 + hal/phydm/rtl8188e/phydm_rtl8188e.h | 21 + hal/phydm/rtl8188e/version_rtl8188e.h | 34 + hal/phydm/sd4_phydm_2_kernel.mk | 188 + 98 files changed, 78770 insertions(+) create mode 100644 hal/phydm/ap_makefile.mk create mode 100644 hal/phydm/halhwimg.h create mode 100644 hal/phydm/mp_precomp.h create mode 100644 hal/phydm/phydm.c create mode 100644 hal/phydm/phydm.h create mode 100644 hal/phydm/phydm.mk create mode 100644 hal/phydm/phydm_adaptivity.c create mode 100644 hal/phydm/phydm_adaptivity.h create mode 100644 hal/phydm/phydm_adc_sampling.c create mode 100644 hal/phydm/phydm_adc_sampling.h create mode 100644 hal/phydm/phydm_antdect.c create mode 100644 hal/phydm/phydm_antdect.h create mode 100644 hal/phydm/phydm_antdiv.c create mode 100644 hal/phydm/phydm_antdiv.h create mode 100644 hal/phydm/phydm_api.c create mode 100644 hal/phydm/phydm_api.h create mode 100644 hal/phydm/phydm_auto_dbg.c create mode 100644 hal/phydm/phydm_auto_dbg.h create mode 100644 hal/phydm/phydm_beamforming.c create mode 100644 hal/phydm/phydm_beamforming.h create mode 100644 hal/phydm/phydm_cck_pd.c create mode 100644 hal/phydm/phydm_cck_pd.h create mode 100644 hal/phydm/phydm_cck_rx_pathdiv.c create mode 100644 hal/phydm/phydm_cck_rx_pathdiv.h create mode 100644 hal/phydm/phydm_ccx.c create mode 100644 hal/phydm/phydm_ccx.h create mode 100644 hal/phydm/phydm_cfotracking.c create mode 100644 hal/phydm/phydm_cfotracking.h create mode 100644 hal/phydm/phydm_debug.c create mode 100644 hal/phydm/phydm_debug.h create mode 100644 hal/phydm/phydm_dfs.c create mode 100644 hal/phydm/phydm_dfs.h create mode 100644 hal/phydm/phydm_dig.c create mode 100644 hal/phydm/phydm_dig.h create mode 100644 hal/phydm/phydm_direct_bf.c create mode 100644 hal/phydm/phydm_direct_bf.h create mode 100644 hal/phydm/phydm_dynamictxpower.c create mode 100644 hal/phydm/phydm_dynamictxpower.h create mode 100644 hal/phydm/phydm_features.h create mode 100644 hal/phydm/phydm_features_ap.h create mode 100644 hal/phydm/phydm_features_ce.h create mode 100644 hal/phydm/phydm_features_ce2_kernel.h create mode 100644 hal/phydm/phydm_features_iot.h create mode 100644 hal/phydm/phydm_features_win.h create mode 100644 hal/phydm/phydm_hwconfig.c create mode 100644 hal/phydm/phydm_hwconfig.h create mode 100644 hal/phydm/phydm_interface.c create mode 100644 hal/phydm/phydm_interface.h create mode 100644 hal/phydm/phydm_lna_sat.c create mode 100644 hal/phydm/phydm_lna_sat.h create mode 100644 hal/phydm/phydm_math_lib.c create mode 100644 hal/phydm/phydm_math_lib.h create mode 100644 hal/phydm/phydm_mp.c create mode 100644 hal/phydm/phydm_mp.h create mode 100644 hal/phydm/phydm_noisemonitor.c create mode 100644 hal/phydm/phydm_noisemonitor.h create mode 100644 hal/phydm/phydm_pathdiv.c create mode 100644 hal/phydm/phydm_pathdiv.h create mode 100644 hal/phydm/phydm_phystatus.c create mode 100644 hal/phydm/phydm_phystatus.h create mode 100644 hal/phydm/phydm_pmac_tx_setting.c create mode 100644 hal/phydm/phydm_pmac_tx_setting.h create mode 100644 hal/phydm/phydm_pow_train.c create mode 100644 hal/phydm/phydm_pow_train.h create mode 100644 hal/phydm/phydm_pre_define.h create mode 100644 hal/phydm/phydm_precomp.h create mode 100644 hal/phydm/phydm_primary_cca.c create mode 100644 hal/phydm/phydm_primary_cca.h create mode 100644 hal/phydm/phydm_psd.c create mode 100644 hal/phydm/phydm_psd.h create mode 100644 hal/phydm/phydm_rainfo.c create mode 100644 hal/phydm/phydm_rainfo.h create mode 100644 hal/phydm/phydm_reg.h create mode 100644 hal/phydm/phydm_regdefine11ac.h create mode 100644 hal/phydm/phydm_regdefine11n.h create mode 100644 hal/phydm/phydm_regtable.h create mode 100644 hal/phydm/phydm_rssi_monitor.c create mode 100644 hal/phydm/phydm_rssi_monitor.h create mode 100644 hal/phydm/phydm_smt_ant.c create mode 100644 hal/phydm/phydm_smt_ant.h create mode 100644 hal/phydm/phydm_soml.c create mode 100644 hal/phydm/phydm_soml.h create mode 100644 hal/phydm/phydm_types.h create mode 100644 hal/phydm/rtl8188e/hal8188erateadaptive.c create mode 100644 hal/phydm/rtl8188e/hal8188erateadaptive.h create mode 100644 hal/phydm/rtl8188e/hal8188ereg.h create mode 100644 hal/phydm/rtl8188e/halhwimg8188e_bb.c create mode 100644 hal/phydm/rtl8188e/halhwimg8188e_bb.h create mode 100644 hal/phydm/rtl8188e/halhwimg8188e_mac.c create mode 100644 hal/phydm/rtl8188e/halhwimg8188e_mac.h create mode 100644 hal/phydm/rtl8188e/halhwimg8188e_rf.c create mode 100644 hal/phydm/rtl8188e/halhwimg8188e_rf.h create mode 100644 hal/phydm/rtl8188e/phydm_regconfig8188e.c create mode 100644 hal/phydm/rtl8188e/phydm_regconfig8188e.h create mode 100644 hal/phydm/rtl8188e/phydm_rtl8188e.c create mode 100644 hal/phydm/rtl8188e/phydm_rtl8188e.h create mode 100644 hal/phydm/rtl8188e/version_rtl8188e.h create mode 100644 hal/phydm/sd4_phydm_2_kernel.mk diff --git a/hal/phydm/ap_makefile.mk b/hal/phydm/ap_makefile.mk new file mode 100644 index 0000000..120fc3d --- /dev/null +++ b/hal/phydm/ap_makefile.mk @@ -0,0 +1,237 @@ + +_PHYDM_FILES :=\ + phydm/phydm.o \ + phydm/phydm_dig.o\ + phydm/phydm_antdiv.o\ + phydm/phydm_soml.o\ + phydm/phydm_smt_ant.o\ + phydm/phydm_pathdiv.o\ + phydm/phydm_rainfo.o\ + phydm/phydm_dynamictxpower.o\ + phydm/phydm_adaptivity.o\ + phydm/phydm_debug.o\ + phydm/phydm_interface.o\ + phydm/phydm_phystatus.o\ + phydm/phydm_hwconfig.o\ + phydm/phydm_dfs.o\ + phydm/phydm_cfotracking.o\ + phydm/phydm_adc_sampling.o\ + phydm/phydm_ccx.o\ + phydm/phydm_primary_cca.o\ + phydm/phydm_cck_pd.o\ + phydm/phydm_rssi_monitor.o\ + phydm/phydm_auto_dbg.o\ + phydm/phydm_math_lib.o\ + phydm/phydm_noisemonitor.o\ + phydm/phydm_api.o\ + phydm/phydm_pow_train.o\ + phydm/phydm_lna_sat.o\ + phydm/phydm_pmac_tx_setting.o\ + phydm/phydm_mp.o\ + phydm/phydm_cck_rx_pathdiv.o\ + phydm/phydm_direct_bf.o\ + phydm/txbf/phydm_hal_txbf_api.o\ + EdcaTurboCheck.o\ + phydm/halrf/halrf.o\ + phydm/halrf/halrf_debug.o\ + phydm/halrf/halphyrf_ap.o\ + phydm/halrf/halrf_powertracking_ap.o\ + phydm/halrf/halrf_powertracking.o\ + phydm/halrf/halrf_kfree.o\ + phydm/halrf/halrf_psd.o + +ifeq ($(CONFIG_RTL_88E_SUPPORT),y) + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8188e/halhwimg8188e_bb.o\ + phydm/rtl8188e/halhwimg8188e_mac.o\ + phydm/rtl8188e/halhwimg8188e_rf.o\ + phydm/rtl8188e/phydm_regconfig8188e.o\ + phydm/rtl8188e/hal8188erateadaptive.o\ + phydm/rtl8188e/phydm_rtl8188e.o\ + phydm/halrf/rtl8188e/halrf_8188e_ap.o + endif +endif + +ifeq ($(CONFIG_RTL_8812_SUPPORT),y) + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o + endif + _PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8881A),y) + _PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8192EE),y) + _PHYDM_FILES += \ + phydm/halrf/rtl8192e/halrf_8192e_ap.o\ + phydm/rtl8192e/phydm_rtl8192e.o +endif + +ifeq ($(CONFIG_WLAN_HAL_8814AE),y) + rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o + rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o + rtl8192cd-objs += phydm/halrf/rtl8814a/halhwimg8814a_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + rtl8192cd-objs += \ + phydm/rtl8814a/halhwimg8814a_bb.o\ + phydm/rtl8814a/halhwimg8814a_mac.o\ + phydm/rtl8814a/phydm_regconfig8814a.o\ + phydm/rtl8814a/phydm_rtl8814a.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8822BE),y) + _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o + _PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o + _PHYDM_FILES += phydm/halrf/rtl8822b/halhwimg8822b_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8822b/halhwimg8822b_bb.o\ + phydm/rtl8822b/halhwimg8822b_mac.o\ + phydm/rtl8822b/phydm_regconfig8822b.o\ + phydm/rtl8822b/phydm_hal_api8822b.o\ + phydm/rtl8822b/phydm_rtl8822b.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8822CE),y) + _PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o + _PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o + _PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o + _PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o + _PHYDM_FILES += phydm/halrf/rtl8822c/halhwimg8822c_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8822c/halhwimg8822c_bb.o\ + phydm/rtl8822c/phydm_regconfig8822c.o\ + phydm/rtl8822c/phydm_hal_api8822c.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8812FE),y) + _PHYDM_FILES += phydm/halrf/rtl8812f/halrf_8812f.o + _PHYDM_FILES += phydm/halrf/rtl8812f/halrf_iqk_8812f.o + _PHYDM_FILES += phydm/halrf/rtl8812f/halrf_dpk_8812f.o + _PHYDM_FILES += phydm/halrf/rtl8812f/halrf_tssi_8812f.o + _PHYDM_FILES += phydm/halrf/rtl8812f/halrf_rfk_init_8812f.o + _PHYDM_FILES += phydm/halrf/rtl8812f/halhwimg8812f_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8812f/halhwimg8812f_bb.o\ + phydm/rtl8812f/phydm_regconfig8812f.o\ + phydm/rtl8812f/phydm_hal_api8812f.o\ + phydm/rtl8812f/phydm_rtl8812f.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8821CE),y) + _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o + _PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o + _PHYDM_FILES += phydm/halrf/rtl8821c/halhwimg8821c_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8821c/halhwimg8821c_bb.o\ + phydm/rtl8821c/halhwimg8821c_mac.o\ + phydm/rtl8821c/phydm_regconfig8821c.o\ + phydm/rtl8821c/phydm_hal_api8821c.o\ + phydm/rtl8821c/phydm_rtl8821c.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8197F),y) + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o + _PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o + _PHYDM_FILES += phydm/halrf/rtl8197f/halhwimg8197f_rf.o + _PHYDM_FILES += efuse_97f/efuse.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8197f/halhwimg8197f_bb.o\ + phydm/rtl8197f/halhwimg8197f_mac.o\ + phydm/rtl8197f/phydm_hal_api8197f.o\ + phydm/rtl8197f/phydm_regconfig8197f.o\ + phydm/rtl8197f/phydm_rtl8197f.o + endif +endif + + +ifeq ($(CONFIG_WLAN_HAL_8192FE),y) + _PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o + _PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o + _PHYDM_FILES += phydm/halrf/rtl8192f/halhwimg8192f_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8192f/halhwimg8192f_bb.o\ + phydm/rtl8192f/halhwimg8192f_mac.o\ + phydm/rtl8192f/phydm_hal_api8192f.o\ + phydm/rtl8192f/phydm_regconfig8192f.o\ + phydm/rtl8192f/phydm_rtl8192f.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8198F),y) + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o + _PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o + _PHYDM_FILES += phydm/halrf/rtl8198f/halhwimg8198f_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8198f/phydm_hal_api8198f.o\ + phydm/rtl8198f/halhwimg8198f_bb.o\ + phydm/rtl8198f/halhwimg8198f_mac.o\ + phydm/rtl8198f/phydm_regconfig8198f.o \ + phydm/halrf/rtl8198f/halrf_8198f.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8814BE),y) + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_txgapk_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o + _PHYDM_FILES += phydm/halrf/rtl8814b/halhwimg8814b_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8814b/phydm_hal_api8814b.o\ + phydm/rtl8814b/halhwimg8814b_bb.o\ + phydm/rtl8814b/phydm_regconfig8814b.o \ + phydm/rtl8814b/phydm_extraagc8814b.o \ + phydm/halrf/rtl8814b/halrf_8814b.o + endif +endif + +ifeq ($(CONFIG_WLAN_HAL_8197G),y) + _PHYDM_FILES += phydm/halrf/rtl8197g/halrf_8197g.o + _PHYDM_FILES += phydm/halrf/rtl8197g/halrf_iqk_8197g.o + _PHYDM_FILES += phydm/halrf/rtl8197g/halrf_dpk_8197g.o + _PHYDM_FILES += phydm/halrf/rtl8197g/halrf_tssi_8197g.o + _PHYDM_FILES += phydm/halrf/rtl8197g/halrf_rfk_init_8197g.o + _PHYDM_FILES += phydm/halrf/rtl8197g/halhwimg8197g_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8197g/phydm_hal_api8197g.o\ + phydm/rtl8197g/halhwimg8197g_bb.o\ + phydm/rtl8197g/halhwimg8197g_mac.o\ + phydm/rtl8197g/phydm_regconfig8197g.o \ + phydm/rtl8197g/phydm_rtl8197g.o \ + phydm/halrf/rtl8197g/halrf_8197g.o + endif +endif +ifeq ($(CONFIG_WLAN_HAL_8723FE),y) + _PHYDM_FILES += phydm/halrf/rtl8723f/halrf_8723f.o + _PHYDM_FILES += phydm/halrf/rtl8723f/halrf_iqk_8723f.o + _PHYDM_FILES += phydm/halrf/rtl8723f/halrf_dpk_8723f.o + _PHYDM_FILES += phydm/halrf/rtl8723f/halrf_rfk_init_8723f.o + _PHYDM_FILES += phydm/halrf/rtl8723f/halhwimg8723f_rf.o + ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y) + _PHYDM_FILES += \ + phydm/rtl8723f/halhwimg8723f_bb.o\ + phydm/rtl8723f/phydm_regconfig8723f.o\ + phydm/rtl8723f/phydm_hal_api8723f.o + endif +endif diff --git a/hal/phydm/halhwimg.h b/hal/phydm/halhwimg.h new file mode 100644 index 0000000..6d658b3 --- /dev/null +++ b/hal/phydm/halhwimg.h @@ -0,0 +1,137 @@ +/****************************************************************************** + * + * Copyright(c) 2016 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#pragma once +#ifndef __INC_HW_IMG_H +#define __INC_HW_IMG_H + +/*@ + * 2011/03/15 MH Add for different IC HW image file selection. code size consideration. + * */ +#if RT_PLATFORM == PLATFORM_LINUX + + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + /* @For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 1 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 0 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + /* @For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 1 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 0 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + /* @For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 0 + + /* @For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_USB_INTERFACE) + /* @For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + /* @For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + /* @For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 0 + + /* @For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + /* @For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + /* @For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + /* @For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + /* @For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + #endif + +#else /* PLATFORM_WINDOWS & MacOSX */ + + /* @For 92C */ + #define RTL8192CE_HWIMG_SUPPORT 1 + #define RTL8192CE_TEST_HWIMG_SUPPORT 1 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 1 + + /* @For 92D */ + #define RTL8192DE_HWIMG_SUPPORT 1 + #define RTL8192DE_TEST_HWIMG_SUPPORT 1 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 1 + + #if defined(UNDER_CE) + /* @For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + /* @For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #else + + /* @For 8723 */ + #define RTL8723E_HWIMG_SUPPORT 1 + /* @#define RTL_8723E_TEST_HWIMG_SUPPORT 1 */ + #define RTL8723U_HWIMG_SUPPORT 1 + /* @#define RTL_8723U_TEST_HWIMG_SUPPORT 1 */ + #define RTL8723S_HWIMG_SUPPORT 1 + /* @#define RTL_8723S_TEST_HWIMG_SUPPORT 1 */ + + /* @For 88E */ + #define RTL8188EE_HWIMG_SUPPORT 1 + #define RTL8188EU_HWIMG_SUPPORT 1 + #define RTL8188ES_HWIMG_SUPPORT 1 + #endif + +#endif + +#endif /* @__INC_HW_IMG_H */ diff --git a/hal/phydm/mp_precomp.h b/hal/phydm/mp_precomp.h new file mode 100644 index 0000000..897adc1 --- /dev/null +++ b/hal/phydm/mp_precomp.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ diff --git a/hal/phydm/phydm.c b/hal/phydm/phydm.c new file mode 100644 index 0000000..a26ec97 --- /dev/null +++ b/hal/phydm/phydm.c @@ -0,0 +1,3826 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +const u16 phy_rate_table[] = { + /*@20M*/ + 1, 2, 5, 11, + 6, 9, 12, 18, 24, 36, 48, 54, + 6, 13, 19, 26, 39, 52, 58, 65, /*@MCS0~7*/ + 13, 26, 39, 52, 78, 104, 117, 130, /*@MCS8~15*/ + 19, 39, 58, 78, 117, 156, 175, 195, /*@MCS16~23*/ + 26, 52, 78, 104, 156, 208, 234, 260, /*@MCS24~31*/ + 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1ss MCS0~9*/ + 13, 26, 39, 52, 78, 104, 117, 130, 156, 180, /*@2ss MCS0~9*/ + 19, 39, 58, 78, 117, 156, 175, 195, 234, 260, /*@3ss MCS0~9*/ + 26, 52, 78, 104, 156, 208, 234, 260, 312, 360 /*@4ss MCS0~9*/ +}; + +void phydm_traffic_load_decision(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 shift = 0; + + /*@---TP & Trafic-load calculation---*/ + + if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast) + dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast; + + if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast) + dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast; + + dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt; + dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt; + dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast; + dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast; + + /*@AP: <<3(8bit), >>20(10^6,M), >>0(1sec)*/ + shift = 17 + (PHYDM_WATCH_DOG_PERIOD - 1); + /*@WIN&CE: <<3(8bit), >>20(10^6,M), >>1(2sec)*/ + + dm->tx_tp = (dm->tx_tp >> 1) + (u32)((dm->cur_tx_ok_cnt >> shift) >> 1); + dm->rx_tp = (dm->rx_tp >> 1) + (u32)((dm->cur_rx_ok_cnt >> shift) >> 1); + + dm->total_tp = dm->tx_tp + dm->rx_tp; + + /*@[Calculate TX/RX state]*/ + if (dm->tx_tp > (dm->rx_tp << 1)) + dm->txrx_state_all = TX_STATE; + else if (dm->rx_tp > (dm->tx_tp << 1)) + dm->txrx_state_all = RX_STATE; + else + dm->txrx_state_all = BI_DIRECTION_STATE; + + /*@[Traffic load decision]*/ + dm->pre_traffic_load = dm->traffic_load; + + if (dm->cur_tx_ok_cnt > 1875000 || dm->cur_rx_ok_cnt > 1875000) { + /* @( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ + dm->traffic_load = TRAFFIC_HIGH; + } else if (dm->cur_tx_ok_cnt > 500000 || dm->cur_rx_ok_cnt > 500000) { + /*@( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ + dm->traffic_load = TRAFFIC_MID; + } else if (dm->cur_tx_ok_cnt > 100000 || dm->cur_rx_ok_cnt > 100000) { + /*@( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ + dm->traffic_load = TRAFFIC_LOW; + } else if (dm->cur_tx_ok_cnt > 25000 || dm->cur_rx_ok_cnt > 25000) { + /*@( 0.025M * 8bit ) / 2sec = 0.1M bits /sec )*/ + dm->traffic_load = TRAFFIC_ULTRA_LOW; + } else { + dm->traffic_load = TRAFFIC_NO_TP; + } + + /*@[Calculate consecutive idlel time]*/ + if (dm->traffic_load == 0) + dm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; + else + dm->consecutive_idlel_time = 0; + + #if 0 + PHYDM_DBG(dm, DBG_COMMON_FLOW, + "cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n", + dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, dm->last_tx_ok_cnt, + dm->last_rx_ok_cnt); + + PHYDM_DBG(dm, DBG_COMMON_FLOW, "tx_tp = %d, rx_tp = %d\n", dm->tx_tp, + dm->rx_tp); + #endif +} + +void phydm_cck_new_agc_chk(struct dm_struct *dm) +{ + u32 new_agc_addr = 0x0; + + dm->cck_new_agc = false; +#if (RTL8723D_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8710B_SUPPORT || RTL8192F_SUPPORT ||\ + RTL8195B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8721D_SUPPORT || RTL8710C_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8821C | + ODM_RTL8197F | ODM_RTL8710B | ODM_RTL8192F | ODM_RTL8195B | + ODM_RTL8721D | ODM_RTL8710C)) { + new_agc_addr = R_0xa9c; + } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | + ODM_RTL8814B | ODM_RTL8197G)) { + new_agc_addr = R_0x1a9c; + } + + /*@1: new agc 0: old agc*/ + dm->cck_new_agc = (boolean)odm_get_bb_reg(dm, new_agc_addr, BIT(17)); +#endif +#if (RTL8723F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8723F)) + dm->cck_new_agc = true; +#endif +} + +/*select 3 or 4 bit LNA */ +void phydm_cck_lna_bit_num_chk(struct dm_struct *dm) +{ + boolean report_type = 0; + #if (RTL8192E_SUPPORT) + u32 value_824, value_82c; + #endif + + #if (RTL8192E_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8192E)) { + /* @0x824[9] = 0x82C[9] = 0xA80[7] those registers setting + * should be equal or CCK RSSI report may be incorrect + */ + value_824 = odm_get_bb_reg(dm, R_0x824, BIT(9)); + value_82c = odm_get_bb_reg(dm, R_0x82c, BIT(9)); + + if (value_824 != value_82c) + odm_set_bb_reg(dm, R_0x82c, BIT(9), value_824); + odm_set_bb_reg(dm, R_0xa80, BIT(7), value_824); + report_type = (boolean)value_824; + } + #endif + + #if (RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8710B_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + report_type = (boolean)odm_get_bb_reg(dm, R_0x950, BIT(11)); + + if (report_type != 1) + pr_debug("[Warning] CCK should be 4bit LNA\n"); + } + #endif + + #if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) { + if (dm->default_rf_set_8821c == SWITCH_TO_BTG) + report_type = 1; + } + #endif + + dm->cck_agc_report_type = report_type; + + PHYDM_DBG(dm, ODM_COMP_INIT, "cck_agc_report_type=((%d))\n", + dm->cck_agc_report_type); +} + +void phydm_init_cck_setting(struct dm_struct *dm) +{ + u32 reg_tmp = 0; + u32 mask_tmp = 0; + + phydm_cck_new_agc_chk(dm); + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + return; + + reg_tmp = ODM_REG(CCK_RPT_FORMAT, dm); + mask_tmp = ODM_BIT(CCK_RPT_FORMAT, dm); + dm->is_cck_high_power = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp); + + PHYDM_DBG(dm, ODM_COMP_INIT, "ext_lna_gain=((%d))\n", dm->ext_lna_gain); + + phydm_config_cck_rx_antenna_init(dm); + + if (dm->support_ic_type & ODM_RTL8192F) + phydm_config_cck_rx_path(dm, BB_PATH_AB); + else if (dm->valid_path_set == BB_PATH_A) + phydm_config_cck_rx_path(dm, BB_PATH_A); + else if (dm->valid_path_set == BB_PATH_B) + phydm_config_cck_rx_path(dm, BB_PATH_B); + + phydm_cck_lna_bit_num_chk(dm); + phydm_get_cck_rssi_table_from_reg(dm); +} + +#ifdef CONFIG_RFE_BY_HW_INFO +void phydm_init_hw_info_by_rfe(struct dm_struct *dm) +{ + #if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) + phydm_init_hw_info_by_rfe_type_8821c(dm); + #endif + #if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + phydm_init_hw_info_by_rfe_type_8197f(dm); + #endif + #if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) + phydm_init_hw_info_by_rfe_type_8197g(dm); + #endif +} +#endif + +void phydm_common_info_self_init(struct dm_struct *dm) +{ + u32 reg_tmp = 0; + u32 mask_tmp = 0; + + dm->run_in_drv_fw = RUN_IN_DRIVER; + + /*@BB IP Generation*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + dm->ic_ip_series = PHYDM_IC_JGR3; + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) + dm->ic_ip_series = PHYDM_IC_AC; + else if (dm->support_ic_type & ODM_IC_11N_SERIES) + dm->ic_ip_series = PHYDM_IC_N; + + /*@BB phy-status Generation*/ + if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) + dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_3; + else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) + dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_2; + else + dm->ic_phy_sts_type = PHYDM_PHYSTS_TYPE_1; + + phydm_init_cck_setting(dm); + + reg_tmp = ODM_REG(BB_RX_PATH, dm); + mask_tmp = ODM_BIT(BB_RX_PATH, dm); + dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, reg_tmp, mask_tmp); +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) + dm->is_net_closed = &dm->BOOLEAN_temp; + + phydm_init_debug_setting(dm); +#endif + phydm_init_soft_ml_setting(dm); + + dm->phydm_sys_up_time = 0; + + if (dm->support_ic_type & ODM_IC_1SS) + dm->num_rf_path = 1; + else if (dm->support_ic_type & ODM_IC_2SS) + dm->num_rf_path = 2; + #if 0 + /* @RTK do not has IC which is equipped with 3 RF paths, + * so ODM_IC_3SS is an enpty macro and result in coverity check errors + */ + else if (dm->support_ic_type & ODM_IC_3SS) + dm->num_rf_path = 3; + #endif + else if (dm->support_ic_type & ODM_IC_4SS) + dm->num_rf_path = 4; + else + dm->num_rf_path = 1; + + phydm_trx_antenna_setting_init(dm, dm->num_rf_path); + + dm->tx_rate = 0xFF; + dm->rssi_min_by_path = 0xFF; + + dm->number_linked_client = 0; + dm->pre_number_linked_client = 0; + dm->number_active_client = 0; + dm->pre_number_active_client = 0; + + dm->last_tx_ok_cnt = 0; + dm->last_rx_ok_cnt = 0; + dm->tx_tp = 0; + dm->rx_tp = 0; + dm->total_tp = 0; + dm->traffic_load = TRAFFIC_LOW; + + dm->nbi_set_result = 0; + dm->is_init_hw_info_by_rfe = false; + dm->pre_dbg_priority = DBGPORT_RELEASE; + dm->tp_active_th = 5; + dm->disable_phydm_watchdog = 0; + + dm->u8_dummy = 0xf; + dm->u16_dummy = 0xffff; + dm->u32_dummy = 0xffffffff; +#if (RTL8814B_SUPPORT) +/*@------------For spur detection Default Mode------------@*/ + dm->dsde_sel = DET_CSI; + dm->csi_wgt = 4; +/*@-------------------------------------------------------@*/ +#endif + dm->pre_is_linked = false; + dm->is_linked = false; +/*dym bw thre and it can config by registry*/ + if (dm->en_auto_bw_th == 0) + dm->en_auto_bw_th = 20; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (!(dm->is_fcs_mode_enable)) { + dm->is_fcs_mode_enable = &dm->boolean_dummy; + pr_debug("[Warning] is_fcs_mode_enable=NULL\n"); + } +#endif + /*init IOT table*/ + odm_memory_set(dm, &dm->iot_table, 0, sizeof(struct phydm_iot_center)); +} + +void phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_iot_center *iot_table = &dm->iot_table; + + PHYDM_DBG(dm, DBG_CMN, "[IOT] 0x%x = %d\n", iot_idx, en); + switch (iot_idx) { + case 0x100f0401: + iot_table->patch_id_100f0401 = en; + PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_100f0401 = %d\n", + iot_table->patch_id_100f0401); + break; + case 0x10120200: + iot_table->patch_id_10120200 = en; + PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_10120200 = %d\n", + iot_table->patch_id_10120200); + break; + case 0x40010700: + iot_table->patch_id_40010700 = en; + PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_40010700 = %d\n", + iot_table->patch_id_40010700); + break; + case 0x021f0800: + iot_table->patch_id_021f0800 = en; + PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_021f0800 = %d\n", + iot_table->patch_id_021f0800); + break; + case 0x011f0500: + iot_table->patch_id_011f0500 = en; + PHYDM_DBG(dm, DBG_CMN, "[IOT] patch_id_011f0500 = %d\n", + iot_table->patch_id_011f0500); + break; + default: + pr_debug("[%s] warning!\n", __func__); + break; + } +} + +void phydm_cmn_sta_info_update(void *dm_void, u8 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid sta_info\n", + __func__); + return; + } + + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA_MASK, "MACID=%d\n", sta->mac_id); + + /*@[Calculate TX/RX state]*/ + if (sta->tx_moving_average_tp > (sta->rx_moving_average_tp << 1)) + ra->txrx_state = TX_STATE; + else if (sta->rx_moving_average_tp > (sta->tx_moving_average_tp << 1)) + ra->txrx_state = RX_STATE; + else + ra->txrx_state = BI_DIRECTION_STATE; + + ra->is_noisy = dm->noisy_decision; +} + +void phydm_common_info_self_update(struct dm_struct *dm) +{ + u8 sta_cnt = 0, num_active_client = 0; + u32 i, one_entry_macid = 0; + u32 ma_rx_tp = 0; + u32 tp_diff = 0; + struct cmn_sta_info *sta; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER adapter = (PADAPTER)dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + + sta = dm->phydm_sta_info[0]; + + /* STA mode is linked to AP */ + if (is_sta_active(sta) && !ACTING_AS_AP(adapter)) + dm->bsta_state = true; + else + dm->bsta_state = false; +#endif + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + if (sta_cnt == 1) + one_entry_macid = i; + + phydm_cmn_sta_info_update(dm, (u8)i); + #ifdef PHYDM_BEAMFORMING_SUPPORT + /*@phydm_get_txbf_device_num(dm, (u8)i);*/ + #endif + + ma_rx_tp = sta->rx_moving_average_tp + + sta->tx_moving_average_tp; + + PHYDM_DBG(dm, DBG_COMMON_FLOW, + "TP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp); + + if (ma_rx_tp > ACTIVE_TP_THRESHOLD) + num_active_client++; + } + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + dm->is_linked = (sta_cnt != 0) ? true : false; +#endif + + if (sta_cnt == 1) { + dm->is_one_entry_only = true; + dm->one_entry_macid = one_entry_macid; + dm->one_entry_tp = ma_rx_tp; + + dm->tp_active_occur = 0; + + PHYDM_DBG(dm, DBG_COMMON_FLOW, + "one_entry_tp=((%d)), pre_one_entry_tp=((%d))\n", + dm->one_entry_tp, dm->pre_one_entry_tp); + + if (dm->one_entry_tp > dm->pre_one_entry_tp && + dm->pre_one_entry_tp <= 2) { + tp_diff = dm->one_entry_tp - dm->pre_one_entry_tp; + + if (tp_diff > dm->tp_active_th) + dm->tp_active_occur = 1; + } + dm->pre_one_entry_tp = dm->one_entry_tp; + } else { + dm->is_one_entry_only = false; + } + + dm->pre_number_linked_client = dm->number_linked_client; + dm->pre_number_active_client = dm->number_active_client; + + dm->number_linked_client = sta_cnt; + dm->number_active_client = num_active_client; + + /*Traffic load information update*/ + phydm_traffic_load_decision(dm); + + dm->phydm_sys_up_time += PHYDM_WATCH_DOG_PERIOD; + + dm->is_dfs_band = phydm_is_dfs_band(dm); + dm->phy_dbg_info.show_phy_sts_cnt = 0; + + /*[Link Status Check]*/ + dm->first_connect = dm->is_linked && !dm->pre_is_linked; + dm->first_disconnect = !dm->is_linked && dm->pre_is_linked; + dm->pre_is_linked = dm->is_linked; +} + +void phydm_common_info_self_reset(struct dm_struct *dm) +{ + struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info; + + dbg_t->beacon_cnt_in_period = dbg_t->num_qry_beacon_pkt; + dbg_t->num_qry_beacon_pkt = 0; + + dm->rxsc_l = 0xff; + dm->rxsc_20 = 0xff; + dm->rxsc_40 = 0xff; + dm->rxsc_80 = 0xff; +} + +void * +phydm_get_structure(struct dm_struct *dm, u8 structure_type) + +{ + void *structure = NULL; + + switch (structure_type) { + case PHYDM_FALSEALMCNT: + structure = &dm->false_alm_cnt; + break; + + case PHYDM_CFOTRACK: + structure = &dm->dm_cfo_track; + break; + + case PHYDM_ADAPTIVITY: + structure = &dm->adaptivity; + break; +#ifdef CONFIG_PHYDM_DFS_MASTER + case PHYDM_DFS: + structure = &dm->dfs; + break; +#endif + default: + break; + } + + return structure; +} + +void phydm_phy_info_update(struct dm_struct *dm) +{ +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) + dm->phy_dbg_info.condi_num = phydm_get_condi_num_8822b(dm); +#endif +} + +void phydm_hw_setting(struct dm_struct *dm) +{ +#if (RTL8821A_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821) + odm_hw_setting_8821a(dm); +#endif + +#if (RTL8814A_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814A) + phydm_hwsetting_8814a(dm); +#endif + +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + phydm_hwsetting_8822b(dm); +#endif + +#if (RTL8812A_SUPPORT) + if (dm->support_ic_type & ODM_RTL8812) + phydm_hwsetting_8812a(dm); +#endif + +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + phydm_hwsetting_8197f(dm); +#endif + +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + phydm_hwsetting_8192f(dm); +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) + phydm_hwsetting_8822c(dm); +#endif + +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) + phydm_hwsetting_8197g(dm); +#endif + +#if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) + phydm_hwsetting_8723f(dm); +#endif + +#if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) + phydm_hwsetting_8821c(dm); +#endif + +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8812F) + phydm_hwsetting_8812f(dm); +#endif + +#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT + phydm_cck_rx_pathdiv_watchdog(dm); +#endif +} + +__odm_func__ +boolean phydm_chk_bb_rf_pkg_set_valid(struct dm_struct *dm) +{ + boolean valid = true; + + if (dm->support_ic_type == ODM_RTL8822C) { + #if (RTL8822C_SUPPORT) + valid = phydm_chk_pkg_set_valid_8822c(dm, + RELEASE_VERSION_8822C, + RF_RELEASE_VERSION_8822C); + #else + valid = true; /*@Just for preventing compile warnings*/ + #endif + #if (RTL8812F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8812F) { + valid = phydm_chk_pkg_set_valid_8812f(dm, + RELEASE_VERSION_8812F, + RF_RELEASE_VERSION_8812F); + #endif + #if (RTL8197G_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8197G) { + valid = phydm_chk_pkg_set_valid_8197g(dm, + RELEASE_VERSION_8197G, + RF_RELEASE_VERSION_8197G); + #endif + #if (RTL8812F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8812F) { + valid = phydm_chk_pkg_set_valid_8812f(dm, + RELEASE_VERSION_8812F, + RF_RELEASE_VERSION_8812F); + #endif + #if (RTL8198F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8198F) { + valid = phydm_chk_pkg_set_valid_8198f(dm, + RELEASE_VERSION_8198F, + RF_RELEASE_VERSION_8198F); + #endif + #if (RTL8814B_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8814B) { + valid = phydm_chk_pkg_set_valid_8814b(dm, + RELEASE_VERSION_8814B, + RF_RELEASE_VERSION_8814B); + #endif + #if (RTL8723F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8723F) { + valid = phydm_chk_pkg_set_valid_8723f(dm, + RELEASE_VERSION_8723F, + RF_RELEASE_VERSION_8723F); + #endif + } + + return valid; +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +u64 phydm_supportability_init_win( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + + switch (dm->support_ic_type) { +/*@---------------N Series--------------------*/ +#if (RTL8188E_SUPPORT) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8192E_SUPPORT) + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8723B_SUPPORT) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8703B_SUPPORT) + case ODM_RTL8703B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8723D_SUPPORT) + case ODM_RTL8723D: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8710B_SUPPORT) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8188F_SUPPORT) + case ODM_RTL8188F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8192F_SUPPORT) + case ODM_RTL8192F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + /*ODM_BB_PATH_DIV |*/ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ADAPTIVE_SOML | + ODM_BB_ENV_MONITOR; + /*ODM_BB_LNA_SAT_CHK |*/ + /*ODM_BB_PRIMARY_CCA*/ + + break; +#endif + +/*@---------------AC Series-------------------*/ + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT) + case ODM_RTL8812: + case ODM_RTL8821: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814A_SUPPORT) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8822B_SUPPORT) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_ADAPTIVE_SOML |*/ + ODM_BB_RATE_ADAPTIVE | + /*ODM_BB_PATH_DIV |*/ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8821C_SUPPORT) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +/*@---------------JGR3 Series-------------------*/ + +#if (RTL8822C_SUPPORT) + case ODM_RTL8822C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_PATH_DIV | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814B_SUPPORT) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING; + /*ODM_BB_ENV_MONITOR;*/ + break; +#endif + +#if (RTL8723F_SUPPORT) + case ODM_RTL8723F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /* ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; + } + + return support_ability; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +u64 phydm_supportability_init_ce(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + + switch (dm->support_ic_type) { +/*@---------------N Series--------------------*/ +#if (RTL8188E_SUPPORT) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8192E_SUPPORT) + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8723B_SUPPORT) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8703B_SUPPORT) + case ODM_RTL8703B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8723D_SUPPORT) + case ODM_RTL8723D: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8710B_SUPPORT) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8188F_SUPPORT) + case ODM_RTL8188F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8192F_SUPPORT) + case ODM_RTL8192F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_PWR_TRAIN | + ODM_BB_RATE_ADAPTIVE | + /*ODM_BB_PATH_DIV |*/ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + /*@ODM_BB_ADAPTIVE_SOML |*/ + ODM_BB_ENV_MONITOR; + /*@ODM_BB_LNA_SAT_CHK |*/ + /*@ODM_BB_PRIMARY_CCA*/ + break; +#endif +/*@---------------AC Series-------------------*/ + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT) + case ODM_RTL8812: + case ODM_RTL8821: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814A_SUPPORT) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8822B_SUPPORT) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + /*ODM_BB_PATH_DIV |*/ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8821C_SUPPORT) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +/*@---------------JGR3 Series-------------------*/ + +#if (RTL8822C_SUPPORT) + case ODM_RTL8822C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_RATE_ADAPTIVE | + /* ODM_BB_PATH_DIV | */ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814B_SUPPORT) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_RATE_ADAPTIVE |*/ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING; + /*ODM_BB_ENV_MONITOR;*/ + break; +#endif +#if (RTL8723F_SUPPORT) + case ODM_RTL8723F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_RATE_ADAPTIVE | + /* ODM_BB_PATH_DIV | */ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*@ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*@ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; + } + + return support_ability; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u64 phydm_supportability_init_ap( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + + switch (dm->support_ic_type) { +/*@---------------N Series--------------------*/ +#if (RTL8188E_SUPPORT) + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8192E_SUPPORT) + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8723B_SUPPORT) + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8198F_SUPPORT || RTL8197F_SUPPORT) + case ODM_RTL8198F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_RATE_ADAPTIVE |*/ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING; + /*ODM_BB_ADAPTIVE_SOML |*/ + /*ODM_BB_ENV_MONITOR |*/ + /*ODM_BB_LNA_SAT_CHK |*/ + /*ODM_BB_PRIMARY_CCA;*/ + break; + case ODM_RTL8197F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ADAPTIVE_SOML | + ODM_BB_ENV_MONITOR | + ODM_BB_LNA_SAT_CHK | + ODM_BB_PRIMARY_CCA; + break; +#endif + +#if (RTL8192F_SUPPORT) + case ODM_RTL8192F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + /*ODM_BB_CFO_TRACKING |*/ + ODM_BB_ADAPTIVE_SOML | + /*ODM_BB_PATH_DIV |*/ + ODM_BB_ENV_MONITOR | + /*ODM_BB_LNA_SAT_CHK |*/ + /*ODM_BB_PRIMARY_CCA |*/ + 0; + break; +#endif + +/*@---------------AC Series-------------------*/ + +#if (RTL8881A_SUPPORT) + case ODM_RTL8881A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8814A_SUPPORT) + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8822B_SUPPORT) + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_ADAPTIVE_SOML |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8821C_SUPPORT) + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + break; +#endif + +/*@---------------JGR3 Series-------------------*/ + +#if (RTL8814B_SUPPORT) + case ODM_RTL8814B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + /*ODM_BB_RATE_ADAPTIVE |*/ + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8197G_SUPPORT) + case ODM_RTL8197G: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8812F_SUPPORT) + case ODM_RTL8812F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + /*ODM_BB_CCK_PD |*/ + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8723F_SUPPORT) + case ODM_RTL8723F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; + } + + return support_ability; +} +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) +u64 phydm_supportability_init_iot( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability = 0; + + switch (dm->support_ic_type) { +#if (RTL8710B_SUPPORT) + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8195A_SUPPORT) + case ODM_RTL8195A: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8195B_SUPPORT) + case ODM_RTL8195B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8721D_SUPPORT) + case ODM_RTL8721D: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + +#if (RTL8710C_SUPPORT) + case ODM_RTL8710C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_ADAPTIVITY | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + break; +#endif + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + /*ODM_BB_DYNAMIC_TXPWR |*/ + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + /*ODM_BB_PWR_TRAIN |*/ + ODM_BB_RATE_ADAPTIVE | + ODM_BB_CFO_TRACKING | + ODM_BB_ENV_MONITOR; + + pr_debug("[Warning] Supportability Init Warning !!!\n"); + break; + } + + return support_ability; +} +#endif + +void phydm_fwoffload_ability_init(struct dm_struct *dm, + enum phydm_offload_ability offload_ability) +{ + switch (offload_ability) { + case PHYDM_PHY_PARAM_OFFLOAD: + if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD) + dm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD; + break; + + case PHYDM_RF_IQK_OFFLOAD: + dm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD; + break; + + case PHYDM_RF_DPK_OFFLOAD: + dm->fw_offload_ability |= PHYDM_RF_DPK_OFFLOAD; + break; + + default: + PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n"); + break; + } + + PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n", + dm->fw_offload_ability); +} + +void phydm_fwoffload_ability_clear(struct dm_struct *dm, + enum phydm_offload_ability offload_ability) +{ + switch (offload_ability) { + case PHYDM_PHY_PARAM_OFFLOAD: + if (dm->support_ic_type & PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD) + dm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD); + break; + + case PHYDM_RF_IQK_OFFLOAD: + dm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD); + break; + + case PHYDM_RF_DPK_OFFLOAD: + dm->fw_offload_ability &= (~PHYDM_RF_DPK_OFFLOAD); + break; + + default: + PHYDM_DBG(dm, ODM_COMP_INIT, "fwofflad, wrong init type!!\n"); + break; + } + + PHYDM_DBG(dm, ODM_COMP_INIT, "fw_offload_ability = %x\n", + dm->fw_offload_ability); +} + +void phydm_supportability_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 support_ability; + + if (dm->manual_supportability && + *dm->manual_supportability != 0xffffffff) { + support_ability = *dm->manual_supportability; + } else if (*dm->mp_mode) { + support_ability = 0; + } else { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + support_ability = phydm_supportability_init_win(dm); + #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + support_ability = phydm_supportability_init_ap(dm); + #elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + support_ability = phydm_supportability_init_ce(dm); + #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + support_ability = phydm_supportability_init_iot(dm); + #endif + + /*@[Config Antenna Diversity]*/ + if (IS_FUNC_EN(dm->enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + + /*@[Config TXpath Diversity]*/ + if (IS_FUNC_EN(dm->enable_pathdiv)) + support_ability |= ODM_BB_PATH_DIV; + + /*@[Config Adaptive SOML]*/ + if (IS_FUNC_EN(dm->en_adap_soml)) + support_ability |= ODM_BB_ADAPTIVE_SOML; + + /*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/ + if(IS_FUNC_EN(&dm->en_tssi_mode) && + (dm->support_ic_type & ODM_RTL8822C)) + support_ability &= ~ODM_BB_DYNAMIC_TXPWR; + /*@[DYNAMIC_TXPWR and TSSI cannot coexist]*/ + if(IS_FUNC_EN(&dm->en_tssi_mode) && + (dm->support_ic_type & ODM_RTL8723F)) + support_ability &= ~ODM_BB_DYNAMIC_TXPWR; + } + dm->support_ability = support_ability; + PHYDM_DBG(dm, ODM_COMP_INIT, "IC=0x%x, mp=%d, Supportability=0x%llx\n", + dm->support_ic_type, *dm->mp_mode, dm->support_ability); +} + +void phydm_rfe_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, ODM_COMP_INIT, "RFE_Init\n"); +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + phydm_rfe_8822b_init(dm); +#endif +} + +#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH +void phydm_tx_collsion_th_init(void *dm_void) +{ + +struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) + phydm_tx_collsion_th_init_8197g(dm); +#endif + +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8812F) + phydm_tx_collsion_th_init_8812f(dm); +#endif + +} + +void phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) + phydm_tx_collsion_th_set_8197g(dm, val_r2t, val_t2r); +#endif + +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8812F) + phydm_tx_collsion_th_set_8812f(dm, val_r2t, val_t2r); +#endif + +} +#endif + +void phydm_dm_early_init(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + phydm_init_debug_setting(dm); +#endif +} + +enum phydm_init_result odm_dm_init(struct dm_struct *dm) +{ + enum phydm_init_result result = PHYDM_INIT_SUCCESS; + + if (!phydm_chk_bb_rf_pkg_set_valid(dm)) { + pr_debug("[Warning][%s] Init fail\n", __func__); + return PHYDM_INIT_FAIL_BBRF_REG_INVALID; + } + + halrf_init(dm); + phydm_supportability_init(dm); + phydm_pause_func_init(dm); + phydm_rfe_init(dm); + phydm_common_info_self_init(dm); + phydm_rx_phy_status_init(dm); +#ifdef PHYDM_AUTO_DEGBUG + phydm_auto_dbg_engine_init(dm); +#endif + phydm_dig_init(dm); +#ifdef PHYDM_SUPPORT_CCKPD +#ifdef PHYDM_DCC_ENHANCE + phydm_dig_cckpd_coex_init(dm); +#endif + phydm_cck_pd_init(dm); +#endif + phydm_env_monitor_init(dm); + phydm_adaptivity_init(dm); + phydm_ra_info_init(dm); + phydm_rssi_monitor_init(dm); + phydm_cfo_tracking_init(dm); + phydm_rf_init(dm); + phydm_dc_cancellation(dm); +#ifdef PHYDM_TXA_CALIBRATION + phydm_txcurrentcalibration(dm); + phydm_get_pa_bias_offset(dm); +#endif +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + odm_antenna_diversity_init(dm); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_init(dm); +#endif +#ifdef CONFIG_PATH_DIVERSITY + phydm_tx_path_diversity_init(dm); +#endif +#ifdef CONFIG_DYNAMIC_TX_TWR + phydm_dynamic_tx_power_init(dm); +#endif +#if (PHYDM_LA_MODE_SUPPORT) + phydm_la_init(dm); +#endif + +#ifdef PHYDM_BEAMFORMING_VERSION1 + phydm_beamforming_init(dm); +#endif + +#if (RTL8188E_SUPPORT) + odm_ra_info_init_all(dm); +#endif +#ifdef PHYDM_PRIMARY_CCA + phydm_primary_cca_init(dm); +#endif +#ifdef CONFIG_PSD_TOOL + phydm_psd_init(dm); +#endif + +#ifdef CONFIG_SMART_ANTENNA + phydm_smt_ant_init(dm); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_check_init(dm); +#endif +#ifdef CONFIG_MCC_DM + phydm_mcc_init(dm); +#endif + +#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT + phydm_cck_rx_pathdiv_init(dm); +#endif + +#ifdef CONFIG_MU_RSOML + phydm_mu_rsoml_init(dm); +#endif + +#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH + phydm_tx_collsion_th_init(dm); +#endif + + return result; +} + +void odm_dm_reset(struct dm_struct *dm) +{ + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + odm_ant_div_reset(dm); + #endif + phydm_set_edcca_threshold_api(dm); +} + +void phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 dm_value[10] = {0}; + u64 pre_support_ability, one = 1; + u64 comp = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + } + + pre_support_ability = dm->support_ability; + comp = dm->support_ability; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n================================\n"); + + if (dm_value[0] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Supportability] PhyDM Selection\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))DIG\n", + ((comp & ODM_BB_DIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RA_MASK\n", + ((comp & ODM_BB_RA_MASK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))DYN_TXPWR\n", + ((comp & ODM_BB_DYNAMIC_TXPWR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))FA_CNT\n", + ((comp & ODM_BB_FA_CNT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))RSSI_MNTR\n", + ((comp & ODM_BB_RSSI_MONITOR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "05. (( %s ))CCK_PD\n", + ((comp & ODM_BB_CCK_PD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "06. (( %s ))ANT_DIV\n", + ((comp & ODM_BB_ANT_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "07. (( %s ))SMT_ANT\n", + ((comp & ODM_BB_SMT_ANT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "08. (( %s ))PWR_TRAIN\n", + ((comp & ODM_BB_PWR_TRAIN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "09. (( %s ))RA\n", + ((comp & ODM_BB_RATE_ADAPTIVE) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "10. (( %s ))PATH_DIV\n", + ((comp & ODM_BB_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "11. (( %s ))DFS\n", + ((comp & ODM_BB_DFS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "12. (( %s ))DYN_ARFR\n", + ((comp & ODM_BB_DYNAMIC_ARFR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "13. (( %s ))ADAPTIVITY\n", + ((comp & ODM_BB_ADAPTIVITY) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "14. (( %s ))CFO_TRACK\n", + ((comp & ODM_BB_CFO_TRACKING) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "15. (( %s ))ENV_MONITOR\n", + ((comp & ODM_BB_ENV_MONITOR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "16. (( %s ))PRI_CCA\n", + ((comp & ODM_BB_PRIMARY_CCA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "17. (( %s ))ADPTV_SOML\n", + ((comp & ODM_BB_ADAPTIVE_SOML) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "18. (( %s ))LNA_SAT_CHK\n", + ((comp & ODM_BB_LNA_SAT_CHK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Supportability] PhyDM offload ability\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))PHY PARAM OFFLOAD\n", + ((dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) ? + ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RF IQK OFFLOAD\n", + ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) ? + ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + } else if (dm_value[0] == 101) { + dm->support_ability = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable all support_ability components\n"); + } else { + if (dm_value[1] == 1) { /* @enable */ + dm->support_ability |= (one << dm_value[0]); + } else if (dm_value[1] == 2) {/* @disable */ + dm->support_ability &= ~(one << dm_value[0]); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Warning!!!] 1:enable, 2:disable\n"); + } + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "pre-supportability = 0x%llx\n", pre_support_ability); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Cur-supportability = 0x%llx\n", dm->support_ability); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + *_used = used; + *_out_len = out_len; +} + +void phydm_watchdog_lps_32k(struct dm_struct *dm) +{ + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); + + phydm_common_info_self_update(dm); + phydm_rssi_monitor_check(dm); + phydm_dig_lps_32k(dm); + phydm_common_info_self_reset(dm); +} + +void phydm_watchdog_lps(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT)) + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); + + phydm_common_info_self_update(dm); + phydm_rssi_monitor_check(dm); + phydm_basic_dbg_message(dm); + phydm_receiver_blocking(dm); + phydm_false_alarm_counter_statistics(dm); + phydm_dig_by_rssi_lps(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + phydm_adaptivity(dm); + #ifdef CONFIG_BW_INDICATION + phydm_dyn_bw_indication(dm); + #endif + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + /*@enable AntDiv in PS mode, request from SD4 Jeff*/ + odm_antenna_diversity(dm); + #endif + #endif + phydm_common_info_self_reset(dm); +#endif +} + +void phydm_watchdog_mp(struct dm_struct *dm) +{ +} + +void phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (pause_type == PHYDM_PAUSE) { + dm->disable_phydm_watchdog = 1; + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Stop\n"); + } else { + dm->disable_phydm_watchdog = 0; + PHYDM_DBG(dm, ODM_COMP_API, "PHYDM Start\n"); + } +} + +void phydm_pause_func_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + dm->pause_lv_table.lv_cckpd = PHYDM_PAUSE_RELEASE; + dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE; + dm->pause_lv_table.lv_antdiv = PHYDM_PAUSE_RELEASE; + dm->pause_lv_table.lv_dig = PHYDM_PAUSE_RELEASE; + dm->pause_lv_table.lv_adapt = PHYDM_PAUSE_RELEASE; + dm->pause_lv_table.lv_adsl = PHYDM_PAUSE_RELEASE; +} + +u8 phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_lv, u8 val_lehgth, + u32 *val_buf) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_func_poiner *func_t = &dm->phydm_func_handler; + s8 *pause_lv_pre = &dm->s8_dummy; + u32 *bkp_val = &dm->u32_dummy; + u32 ori_val[5] = {0}; + u64 pause_func_bitmap = (u64)BIT(pause_func); + u8 i = 0; + u8 en_2rcca = 0; + u8 en_bw40m = 0; + u8 pause_result = PAUSE_FAIL; + + PHYDM_DBG(dm, ODM_COMP_API, "\n"); + PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] LV=%d, Len=%d\n", __func__, + ((pause_type == PHYDM_PAUSE) ? "Pause" : + ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")), + pause_lv, val_lehgth); + + if (pause_lv >= PHYDM_PAUSE_MAX_NUM) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING]Wrong LV=%d\n", pause_lv); + return PAUSE_FAIL; + } + + if (pause_func == F00_DIG) { + PHYDM_DBG(dm, ODM_COMP_API, "[DIG]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(dm->dm_dig_table.cur_ig_value); + pause_lv_pre = &dm->pause_lv_table.lv_dig; + bkp_val = (u32 *)(&dm->dm_dig_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_dig_val; + +#ifdef PHYDM_SUPPORT_CCKPD + } else if (pause_func == F05_CCK_PD) { + PHYDM_DBG(dm, ODM_COMP_API, "[CCK_PD]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)dm->dm_cckpd_table.cck_pd_lv; + pause_lv_pre = &dm->pause_lv_table.lv_cckpd; + bkp_val = (u32 *)(&dm->dm_cckpd_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_cckpd_val; +#endif + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + } else if (pause_func == F06_ANT_DIV) { + PHYDM_DBG(dm, ODM_COMP_API, "[AntDiv]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; + } + /*@default antenna*/ + ori_val[0] = (u32)(dm->dm_fat_table.rx_idle_ant); + pause_lv_pre = &dm->pause_lv_table.lv_antdiv; + bkp_val = (u32 *)(&dm->dm_fat_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_antdiv_val; + +#endif +#ifdef PHYDM_SUPPORT_ADAPTIVITY + } else if (pause_func == F13_ADPTVTY) { + PHYDM_DBG(dm, ODM_COMP_API, "[Adaptivity]\n"); + + if (val_lehgth != 2) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 2\n"); + return PAUSE_FAIL; + } + + ori_val[0] = (u32)(dm->adaptivity.th_l2h); /*th_l2h*/ + ori_val[1] = (u32)(dm->adaptivity.th_h2l); /*th_h2l*/ + pause_lv_pre = &dm->pause_lv_table.lv_adapt; + bkp_val = (u32 *)(&dm->adaptivity.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_edcca_val; + +#endif +#ifdef CONFIG_ADAPTIVE_SOML + } else if (pause_func == F17_ADPTV_SOML) { + PHYDM_DBG(dm, ODM_COMP_API, "[AD-SOML]\n"); + + if (val_lehgth != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] length != 1\n"); + return PAUSE_FAIL; + } + /*SOML_ON/OFF*/ + ori_val[0] = (u32)(dm->dm_soml_table.soml_on_off); + + pause_lv_pre = &dm->pause_lv_table.lv_adsl; + bkp_val = (u32 *)(&dm->dm_soml_table.rvrt_val); + /*@function pointer hook*/ + func_t->pause_phydm_handler = phydm_set_adsl_val; + +#endif + } else { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error func idx\n"); + return PAUSE_FAIL; + } + + PHYDM_DBG(dm, ODM_COMP_API, "Pause_LV{new , pre} = {%d ,%d}\n", + pause_lv, *pause_lv_pre); + + if (pause_type == PHYDM_PAUSE || pause_type == PHYDM_PAUSE_NO_SET) { + if (pause_lv <= *pause_lv_pre) { + PHYDM_DBG(dm, ODM_COMP_API, + "[PAUSE FAIL] Pre_LV >= Curr_LV\n"); + return PAUSE_FAIL; + } + + if (!(dm->pause_ability & pause_func_bitmap)) { + for (i = 0; i < val_lehgth; i++) + bkp_val[i] = ori_val[i]; + } + + dm->pause_ability |= pause_func_bitmap; + PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", + dm->pause_ability); + + if (pause_type == PHYDM_PAUSE) { + for (i = 0; i < val_lehgth; i++) + PHYDM_DBG(dm, ODM_COMP_API, + "[PAUSE SUCCESS] val_idx[%d]{New, Ori}={0x%x, 0x%x}\n", + i, val_buf[i], bkp_val[i]); + func_t->pause_phydm_handler(dm, val_buf, val_lehgth); + } else { + for (i = 0; i < val_lehgth; i++) + PHYDM_DBG(dm, ODM_COMP_API, + "[PAUSE NO Set: SUCCESS] val_idx[%d]{Ori}={0x%x}\n", + i, bkp_val[i]); + } + + *pause_lv_pre = pause_lv; + pause_result = PAUSE_SUCCESS; + + } else if (pause_type == PHYDM_RESUME) { + if (pause_lv < *pause_lv_pre) { + PHYDM_DBG(dm, ODM_COMP_API, + "[Resume FAIL] Pre_LV >= Curr_LV\n"); + return PAUSE_FAIL; + } + + if ((dm->pause_ability & pause_func_bitmap) == 0) { + PHYDM_DBG(dm, ODM_COMP_API, + "[RESUME] No Need to Revert\n"); + return PAUSE_SUCCESS; + } + + dm->pause_ability &= ~pause_func_bitmap; + PHYDM_DBG(dm, ODM_COMP_API, "pause_ability=0x%llx\n", + dm->pause_ability); + + *pause_lv_pre = PHYDM_PAUSE_RELEASE; + + for (i = 0; i < val_lehgth; i++) { + PHYDM_DBG(dm, ODM_COMP_API, + "[RESUME] val_idx[%d]={0x%x}\n", i, + bkp_val[i]); + } + + func_t->pause_phydm_handler(dm, bkp_val, val_lehgth); + + pause_result = PAUSE_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, "[WARNING] error pause_type\n"); + pause_result = PAUSE_FAIL; + } + return pause_result; +} + +void phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + u8 length = 0; + u32 buf[5] = {0}; + u8 set_result = 0; + enum phydm_func_idx func = 0; + enum phydm_pause_type type = 0; + enum phydm_pause_level lv = 0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{Func} {1:pause,2:pause no set 3:Resume} {lv:0~3} Val[5:0]\n"); + + goto out; + } + + for (i = 0; i < 10; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + + func = (enum phydm_func_idx)var1[0]; + type = (enum phydm_pause_type)var1[1]; + lv = (enum phydm_pause_level)var1[2]; + + for (i = 0; i < 5; i++) + buf[i] = var1[3 + i]; + + if (func == F00_DIG) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[DIG]\n"); + length = 1; + + } else if (func == F05_CCK_PD) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[CCK_PD]\n"); + length = 1; + } else if (func == F06_ANT_DIV) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Ant_Div]\n"); + length = 1; + } else if (func == F13_ADPTVTY) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Adaptivity]\n"); + length = 2; + } else if (func == F17_ADPTV_SOML) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ADSL]\n"); + length = 1; + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set Function Error]\n"); + length = 0; + } + + if (length != 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{%s, lv=%d} val = %d, %d}\n", + ((type == PHYDM_PAUSE) ? "Pause" : + ((type == PHYDM_RESUME) ? "Resume" : "Pause no_set")), + lv, var1[3], var1[4]); + + set_result = phydm_pause_func(dm, func, type, lv, length, buf); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "set_result = %d\n", set_result); + +out: + *_used = used; + *_out_len = out_len; +} + +void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm, + enum phydm_pause_type pause_type, u8 rssi) +{ + u32 igi_val = rssi + 10; + u32 th_buf[2]; + + PHYDM_DBG(dm, ODM_COMP_API, "[%s][%s] rssi=%d\n", __func__, + ((pause_type == PHYDM_PAUSE) ? "Pause" : + ((pause_type == PHYDM_RESUME) ? "Resume" : "Pause no_set")), + rssi); + + if (pause_type == PHYDM_RESUME) { + phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, + PHYDM_PAUSE_LEVEL_1, 1, &igi_val); + + phydm_pause_func(dm, F13_ADPTVTY, PHYDM_RESUME, + PHYDM_PAUSE_LEVEL_1, 2, th_buf); + } else { + odm_write_dig(dm, (u8)igi_val); + phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, + PHYDM_PAUSE_LEVEL_1, 1, &igi_val); + + th_buf[0] = 0xff; + th_buf[1] = 0xff; + + phydm_pause_func(dm, F13_ADPTVTY, PHYDM_PAUSE, + PHYDM_PAUSE_LEVEL_1, 2, th_buf); + } +} + +u8 phydm_stop_dm_watchdog_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->disable_phydm_watchdog == 1) { + PHYDM_DBG(dm, DBG_COMMON_FLOW, "Disable phydm\n"); + return true; + } else { + return false; + } +} + +void phydm_watchdog(struct dm_struct *dm) +{ + PHYDM_DBG(dm, DBG_COMMON_FLOW, "%s ======>\n", __func__); + + phydm_common_info_self_update(dm); + phydm_phy_info_update(dm); + phydm_rssi_monitor_check(dm); + phydm_basic_dbg_message(dm); + phydm_dm_summary(dm, FIRST_MACID); +#ifdef PHYDM_AUTO_DEGBUG + phydm_auto_dbg_engine(dm); +#endif + phydm_receiver_blocking(dm); + + if (phydm_stop_dm_watchdog_check(dm) == true) + return; + + phydm_hw_setting(dm); + + phydm_env_mntr_result_watchdog(dm); + +#ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore == 0) { + phydm_tdma_dig_timer_check(dm); + } else +#endif + { + phydm_false_alarm_counter_statistics(dm); + #if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & (ODM_IC_11N_SERIES | + ODM_IC_11AC_SERIES)) + phydm_noisy_detection(dm); + #endif + + #if defined(PHYDM_DCC_ENHANCE) && defined(PHYDM_SUPPORT_CCKPD) + phydm_dig_cckpd_coex(dm); + #else + phydm_dig(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + #endif + } + +#ifdef PHYDM_HW_IGI + phydm_hwigi(dm); +#endif +#ifdef PHYDM_POWER_TRAINING_SUPPORT + phydm_update_power_training_state(dm); +#endif + phydm_adaptivity(dm); + phydm_ra_info_watchdog(dm); +#ifdef CONFIG_PATH_DIVERSITY + phydm_tx_path_diversity(dm); +#endif + phydm_cfo_tracking(dm); +#ifdef CONFIG_DYNAMIC_TX_TWR + phydm_dynamic_tx_power(dm); +#endif +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + odm_antenna_diversity(dm); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml(dm); +#endif + +#ifdef PHYDM_BEAMFORMING_VERSION1 + phydm_beamforming_watchdog(dm); +#endif + + halrf_watchdog(dm); +#ifdef PHYDM_PRIMARY_CCA + phydm_primary_cca(dm); +#endif +#ifdef CONFIG_BW_INDICATION + phydm_dyn_bw_indication(dm); +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + odm_dtc(dm); +#endif + + phydm_env_mntr_set_watchdog(dm); + +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_chk_watchdog(dm); +#endif + +#ifdef CONFIG_MCC_DM + phydm_mcc_switch(dm); +#endif + +#ifdef CONFIG_MU_RSOML + phydm_mu_rsoml_decision(dm); +#endif + + phydm_common_info_self_reset(dm); +} + +void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx, + boolean enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; + u8 para4[4]; /*4 bit*/ + u8 para8[4]; /*8 bit*/ + u8 i = 0; + + for (i = 0; i < 4; i++) { + para4[i] = 0; + para8[i] = 0; + } + + switch (fun_idx) { + case F00_DIG: + phydm_fill_fw_dig_info(dm, &enable, para4, para8); + break; + default: + pr_debug("[Warning] %s\n", __func__); + return; + } + + h2c_val[0] = (u8)((fun_idx & 0x3f) | (enable << 6)); + h2c_val[1] = para8[0]; + h2c_val[2] = para8[1]; + h2c_val[3] = para8[2]; + h2c_val[4] = para8[3]; + h2c_val[5] = (para4[0] & 0xf) | ((para4[1] & 0xf) << 3); + h2c_val[6] = (para4[2] & 0xf) | ((para4[3] & 0xf) << 3); + + PHYDM_DBG(dm, DBG_FW_DM, + "H2C[0x59] fun_idx=%d,en=%d,para8={%x %x %x %x},para4={%x %x %x %x}\n", + fun_idx, enable, + para8[0], para8[1], para8[2], para8[3], + para4[0], para4[1], para4[2], para4[3]); + + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_DM_CTRL, H2C_MAX_LENGTH, h2c_val); +} + +/*@ + * Init /.. Fixed HW value. Only init time. + */ +void odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, + u64 value) +{ + /* This section is used for init value */ + switch (cmn_info) { + /* @Fixed ODM value. */ + case ODM_CMNINFO_ABILITY: + dm->support_ability = (u64)value; + break; + + case ODM_CMNINFO_RF_TYPE: + dm->rf_type = (u8)value; + break; + + case ODM_CMNINFO_PLATFORM: + dm->support_platform = (u8)value; + break; + + case ODM_CMNINFO_INTERFACE: + dm->support_interface = (u8)value; + break; + + case ODM_CMNINFO_MP_TEST_CHIP: + dm->is_mp_chip = (u8)value; + break; + + case ODM_CMNINFO_IC_TYPE: + dm->support_ic_type = (u32)value; + break; + + case ODM_CMNINFO_CUT_VER: + dm->cut_version = (u8)value; + break; + + case ODM_CMNINFO_FAB_VER: + dm->fab_version = (u8)value; + break; + case ODM_CMNINFO_FW_VER: + dm->fw_version = (u8)value; + break; + case ODM_CMNINFO_FW_SUB_VER: + dm->fw_sub_version = (u8)value; + break; + case ODM_CMNINFO_RFE_TYPE: +#if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) + dm->rfe_type_expand = (u8)value; + else +#endif + dm->rfe_type = (u8)value; + +#ifdef CONFIG_RFE_BY_HW_INFO + phydm_init_hw_info_by_rfe(dm); +#endif + break; + + case ODM_CMNINFO_RF_ANTENNA_TYPE: + dm->ant_div_type = (u8)value; + break; + + case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: + dm->with_extenal_ant_switch = (u8)value; + break; + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + case ODM_CMNINFO_BE_FIX_TX_ANT: + dm->dm_fat_table.b_fix_tx_ant = (u8)value; + break; +#endif + + case ODM_CMNINFO_BOARD_TYPE: + if (!dm->is_init_hw_info_by_rfe) + dm->board_type = (u8)value; + break; + + case ODM_CMNINFO_PACKAGE_TYPE: + if (!dm->is_init_hw_info_by_rfe) + dm->package_type = (u8)value; + break; + + case ODM_CMNINFO_EXT_LNA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_lna = (u8)value; + break; + + case ODM_CMNINFO_5G_EXT_LNA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_lna_5g = (u8)value; + break; + + case ODM_CMNINFO_EXT_PA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_pa = (u8)value; + break; + + case ODM_CMNINFO_5G_EXT_PA: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_pa_5g = (u8)value; + break; + + case ODM_CMNINFO_GPA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_gpa = (u16)value; + break; + + case ODM_CMNINFO_APA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_apa = (u16)value; + break; + + case ODM_CMNINFO_GLNA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_glna = (u16)value; + break; + + case ODM_CMNINFO_ALNA: + if (!dm->is_init_hw_info_by_rfe) + dm->type_alna = (u16)value; + break; + + case ODM_CMNINFO_EXT_TRSW: + if (!dm->is_init_hw_info_by_rfe) + dm->ext_trsw = (u8)value; + break; + case ODM_CMNINFO_EXT_LNA_GAIN: + dm->ext_lna_gain = (u8)value; + break; + case ODM_CMNINFO_PATCH_ID: + dm->iot_table.win_patch_id = (u8)value; + break; + case ODM_CMNINFO_BINHCT_TEST: + dm->is_in_hct_test = (boolean)value; + break; + case ODM_CMNINFO_BWIFI_TEST: + dm->wifi_test = (u8)value; + break; + case ODM_CMNINFO_SMART_CONCURRENT: + dm->is_dual_mac_smart_concurrent = (boolean)value; + break; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + case ODM_CMNINFO_CONFIG_BB_RF: + dm->config_bbrf = (boolean)value; + break; +#endif + case ODM_CMNINFO_IQKPAOFF: + dm->rf_calibrate_info.is_iqk_pa_off = (boolean)value; + break; + case ODM_CMNINFO_REGRFKFREEENABLE: + dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value; + break; + case ODM_CMNINFO_RFKFREEENABLE: + dm->rf_calibrate_info.rf_kfree_enable = (u8)value; + break; + case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: + dm->normal_rx_path = (u8)value; + break; + case ODM_CMNINFO_VALID_PATH_SET: + dm->valid_path_set = (u8)value; + break; + case ODM_CMNINFO_EFUSE0X3D8: + dm->efuse0x3d8 = (u8)value; + break; + case ODM_CMNINFO_EFUSE0X3D7: + dm->efuse0x3d7 = (u8)value; + break; + case ODM_CMNINFO_ADVANCE_OTA: + dm->p_advance_ota = (u8)value; + break; + +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_REGION_DOMAIN: + dm->dfs_region_domain = (u8)value; + break; +#endif + case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING: + dm->soft_ap_special_setting = (u32)value; + break; + + case ODM_CMNINFO_X_CAP_SETTING: + dm->dm_cfo_track.crystal_cap_default = (u8)value; + break; + + case ODM_CMNINFO_DPK_EN: + /*@dm->dpk_en = (u1Byte)value;*/ + halrf_cmn_info_set(dm, HALRF_CMNINFO_DPK_EN, (u64)value); + break; + + case ODM_CMNINFO_HP_HWID: + dm->hp_hw_id = (boolean)value; + break; + case ODM_CMNINFO_TSSI_ENABLE: + dm->en_tssi_mode = (u8)value; + break; + case ODM_CMNINFO_DIS_DPD: + dm->en_dis_dpd = (boolean)value; + break; + case ODM_CMNINFO_EN_AUTO_BW_TH: + dm->en_auto_bw_th = (u8)value; + break; +#if (RTL8721D_SUPPORT) + case ODM_CMNINFO_POWER_VOLTAGE: + dm->power_voltage = (u8)value; + break; + case ODM_CMNINFO_ANTDIV_GPIO: + dm->antdiv_gpio = (u8)value; + break; + case ODM_CMNINFO_PEAK_DETECT_MODE: + dm->peak_detect_mode = (u8)value; + break; +#endif + default: + break; + } +} + +void odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, + void *value) +{ + /* @Hook call by reference pointer. */ + switch (cmn_info) { + /* @Dynamic call by reference pointer. */ + case ODM_CMNINFO_TX_UNI: + dm->num_tx_bytes_unicast = (u64 *)value; + break; + + case ODM_CMNINFO_RX_UNI: + dm->num_rx_bytes_unicast = (u64 *)value; + break; + + case ODM_CMNINFO_BAND: + dm->band_type = (u8 *)value; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + dm->sec_ch_offset = (u8 *)value; + break; + + case ODM_CMNINFO_SEC_MODE: + dm->security = (u8 *)value; + break; + + case ODM_CMNINFO_BW: + dm->band_width = (u8 *)value; + break; + + case ODM_CMNINFO_CHNL: + dm->channel = (u8 *)value; + break; + + case ODM_CMNINFO_SCAN: + dm->is_scan_in_process = (boolean *)value; + break; + + case ODM_CMNINFO_POWER_SAVING: + dm->is_power_saving = (boolean *)value; + break; + + case ODM_CMNINFO_TDMA: + dm->is_tdma = (boolean *)value; + break; + + case ODM_CMNINFO_ONE_PATH_CCA: + dm->one_path_cca = (u8 *)value; + break; + + case ODM_CMNINFO_DRV_STOP: + dm->is_driver_stopped = (boolean *)value; + break; + case ODM_CMNINFO_INIT_ON: + dm->pinit_adpt_in_progress = (boolean *)value; + break; + + case ODM_CMNINFO_ANT_TEST: + dm->antenna_test = (u8 *)value; + break; + + case ODM_CMNINFO_NET_CLOSED: + dm->is_net_closed = (boolean *)value; + break; + + case ODM_CMNINFO_FORCED_RATE: + dm->forced_data_rate = (u16 *)value; + break; + case ODM_CMNINFO_ANT_DIV: + dm->enable_antdiv = (u8 *)value; + break; + case ODM_CMNINFO_PATH_DIV: + dm->enable_pathdiv = (u8 *)value; + break; + case ODM_CMNINFO_ADAPTIVE_SOML: + dm->en_adap_soml = (u8 *)value; + break; + case ODM_CMNINFO_ADAPTIVITY: + dm->edcca_mode = (u8 *)value; + break; + + case ODM_CMNINFO_P2P_LINK: + dm->dm_dig_table.is_p2p_in_process = (u8 *)value; + break; + + case ODM_CMNINFO_IS1ANTENNA: + dm->is_1_antenna = (boolean *)value; + break; + + case ODM_CMNINFO_RFDEFAULTPATH: + dm->rf_default_path = (u8 *)value; + break; + + case ODM_CMNINFO_FCS_MODE: /* @fast channel switch (= MCC mode)*/ + dm->is_fcs_mode_enable = (boolean *)value; + break; + + case ODM_CMNINFO_HUBUSBMODE: + dm->hub_usb_mode = (u8 *)value; + break; + case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: + dm->is_fw_dw_rsvd_page_in_progress = (boolean *)value; + break; + case ODM_CMNINFO_TX_TP: + dm->current_tx_tp = (u32 *)value; + break; + case ODM_CMNINFO_RX_TP: + dm->current_rx_tp = (u32 *)value; + break; + case ODM_CMNINFO_SOUNDING_SEQ: + dm->sounding_seq = (u8 *)value; + break; +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_MASTER_ENABLE: + dm->dfs_master_enabled = (u8 *)value; + break; +#endif + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: + dm->dm_fat_table.p_force_tx_by_desc = (u8 *)value; + break; + case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA: + dm->dm_fat_table.p_default_s0_s1 = (u8 *)value; + break; + case ODM_CMNINFO_BF_ANTDIV_DECISION: + dm->dm_fat_table.is_no_csi_feedback = (boolean *)value; + break; +#endif + + case ODM_CMNINFO_SOFT_AP_MODE: + dm->soft_ap_mode = (u32 *)value; + break; + case ODM_CMNINFO_MP_MODE: + dm->mp_mode = (u8 *)value; + break; + case ODM_CMNINFO_INTERRUPT_MASK: + dm->interrupt_mask = (u32 *)value; + break; + case ODM_CMNINFO_BB_OPERATION_MODE: + dm->bb_op_mode = (u8 *)value; + break; + case ODM_CMNINFO_MANUAL_SUPPORTABILITY: + dm->manual_supportability = (u32 *)value; + break; + case ODM_CMNINFO_EN_DYM_BW_INDICATION: + dm->dis_dym_bw_indication = (u8 *)value; + default: + /*do nothing*/ + break; + } +} + +/*@ + * Update band/CHannel/.. The values are dynamic but non-per-packet. + */ +void odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value) +{ + /* This init variable may be changed in run time. */ + switch (cmn_info) { + case ODM_CMNINFO_LINK_IN_PROGRESS: + dm->is_link_in_process = (boolean)value; + break; + + case ODM_CMNINFO_ABILITY: + dm->support_ability = (u64)value; + break; + + case ODM_CMNINFO_RF_TYPE: + dm->rf_type = (u8)value; + break; + + case ODM_CMNINFO_WIFI_DIRECT: + dm->is_wifi_direct = (boolean)value; + break; + + case ODM_CMNINFO_WIFI_DISPLAY: + dm->is_wifi_display = (boolean)value; + break; + + case ODM_CMNINFO_LINK: + dm->is_linked = (boolean)value; + break; + + case ODM_CMNINFO_CMW500LINK: + dm->iot_table.is_linked_cmw500 = (boolean)value; + break; + + case ODM_CMNINFO_STATION_STATE: + dm->bsta_state = (boolean)value; + break; + + case ODM_CMNINFO_RSSI_MIN: +#if 0 + dm->rssi_min = (u8)value; +#endif + break; + + case ODM_CMNINFO_RSSI_MIN_BY_PATH: + dm->rssi_min_by_path = (u8)value; + break; + + case ODM_CMNINFO_DBG_COMP: + dm->debug_components = (u64)value; + break; + +#ifdef ODM_CONFIG_BT_COEXIST + /* The following is for BT HS mode and BT coexist mechanism. */ + case ODM_CMNINFO_BT_ENABLED: + dm->bt_info_table.is_bt_enabled = (boolean)value; + break; + + case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: + dm->bt_info_table.is_bt_connect_process = (boolean)value; + break; + + case ODM_CMNINFO_BT_HS_RSSI: + dm->bt_info_table.bt_hs_rssi = (u8)value; + break; + + case ODM_CMNINFO_BT_OPERATION: + dm->bt_info_table.is_bt_hs_operation = (boolean)value; + break; + + case ODM_CMNINFO_BT_LIMITED_DIG: + dm->bt_info_table.is_bt_limited_dig = (boolean)value; + break; +#endif + + case ODM_CMNINFO_AP_TOTAL_NUM: + dm->ap_total_num = (u8)value; + break; + +#ifdef CONFIG_PHYDM_DFS_MASTER + case ODM_CMNINFO_DFS_REGION_DOMAIN: + dm->dfs_region_domain = (u8)value; + break; +#endif + + case ODM_CMNINFO_BT_CONTINUOUS_TURN: + dm->is_bt_continuous_turn = (boolean)value; + break; + case ODM_CMNINFO_IS_DOWNLOAD_FW: + dm->is_download_fw = (boolean)value; + break; + case ODM_CMNINFO_PHYDM_PATCH_ID: + dm->iot_table.phydm_patch_id = (u32)value; + break; + case ODM_CMNINFO_RRSR_VAL: + dm->dm_ra_table.rrsr_val_init = (u32)value; + break; + case ODM_CMNINFO_LINKED_BF_SUPPORT: + dm->linked_bf_support = (u8)value; + break; + case ODM_CMNINFO_FLATNESS_TYPE: + dm->flatness_type = (u8)value; + break; + case ODM_CMNINFO_TSSI_ENABLE: + dm->en_tssi_mode = (u8)value; + break; + default: + break; + } +} + +u32 phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type) +{ + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + + switch (info_type) { + /*@=== [FA Relative] ===========================================*/ + case PHYDM_INFO_FA_OFDM: + return fa_t->cnt_ofdm_fail; + + case PHYDM_INFO_FA_CCK: + return fa_t->cnt_cck_fail; + + case PHYDM_INFO_FA_TOTAL: + return fa_t->cnt_all; + + case PHYDM_INFO_CCA_OFDM: + return fa_t->cnt_ofdm_cca; + + case PHYDM_INFO_CCA_CCK: + return fa_t->cnt_cck_cca; + + case PHYDM_INFO_CCA_ALL: + return fa_t->cnt_cca_all; + + case PHYDM_INFO_CRC32_OK_VHT: + return fa_t->cnt_vht_crc32_ok; + + case PHYDM_INFO_CRC32_OK_HT: + return fa_t->cnt_ht_crc32_ok; + + case PHYDM_INFO_CRC32_OK_LEGACY: + return fa_t->cnt_ofdm_crc32_ok; + + case PHYDM_INFO_CRC32_OK_CCK: + return fa_t->cnt_cck_crc32_ok; + + case PHYDM_INFO_CRC32_ERROR_VHT: + return fa_t->cnt_vht_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_HT: + return fa_t->cnt_ht_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_LEGACY: + return fa_t->cnt_ofdm_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_CCK: + return fa_t->cnt_cck_crc32_error; + + case PHYDM_INFO_EDCCA_FLAG: + return fa_t->edcca_flag; + + case PHYDM_INFO_OFDM_ENABLE: + return fa_t->ofdm_block_enable; + + case PHYDM_INFO_CCK_ENABLE: + return fa_t->cck_block_enable; + + case PHYDM_INFO_DBG_PORT_0: + return fa_t->dbg_port0; + + case PHYDM_INFO_CRC32_OK_HT_AGG: + return fa_t->cnt_ht_crc32_ok_agg; + + case PHYDM_INFO_CRC32_ERROR_HT_AGG: + return fa_t->cnt_ht_crc32_error_agg; + + /*@=== [DIG] ================================================*/ + + case PHYDM_INFO_CURR_IGI: + return dig_t->cur_ig_value; + + /*@=== [RSSI] ===============================================*/ + case PHYDM_INFO_RSSI_MIN: + return (u32)dm->rssi_min; + + case PHYDM_INFO_RSSI_MAX: + return (u32)dm->rssi_max; + + case PHYDM_INFO_CLM_RATIO: + return (u32)ccx_info->clm_ratio; + case PHYDM_INFO_NHM_RATIO: + return (u32)ccx_info->nhm_ratio; + case PHYDM_INFO_NHM_NOISE_PWR: + return (u32)ccx_info->nhm_level; + case PHYDM_INFO_NHM_PWR: + return (u32)ccx_info->nhm_pwr; + case PHYDM_INFO_NHM_ENV_RATIO: + return (u32)ccx_info->nhm_env_ratio; + case PHYDM_INFO_TXEN_CCK: + return (u32)fa_t->cnt_cck_txen; + case PHYDM_INFO_TXEN_OFDM: + return (u32)fa_t->cnt_ofdm_txen; + default: + return 0xffffffff; + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void odm_init_all_work_items(struct dm_struct *dm) +{ + void *adapter = dm->adapter; +#if USE_WORKITEM + +#ifdef CONFIG_ADAPTIVE_SOML + odm_initialize_work_item(dm, + &dm->dm_soml_table.phydm_adaptive_soml_workitem, + (RT_WORKITEM_CALL_BACK)phydm_adaptive_soml_workitem_callback, + (void *)adapter, + "AdaptiveSOMLWorkitem"); +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_initialize_work_item(dm, + &dm->phydm_evm_antdiv_workitem, + (RT_WORKITEM_CALL_BACK)phydm_evm_antdiv_workitem_callback, + (void *)adapter, + "EvmAntdivWorkitem"); +#endif + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_initialize_work_item(dm, + &dm->dm_swat_table.phydm_sw_antenna_switch_workitem, + (RT_WORKITEM_CALL_BACK)odm_sw_antdiv_workitem_callback, + (void *)adapter, + "AntennaSwitchWorkitem"); +#endif +#if (defined(CONFIG_HL_SMART_ANTENNA)) + odm_initialize_work_item(dm, + &dm->dm_sat_table.hl_smart_antenna_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, + (void *)adapter, + "hl_smart_ant_workitem"); + + odm_initialize_work_item(dm, + &dm->dm_sat_table.hl_smart_antenna_decision_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, + (void *)adapter, + "hl_smart_ant_decision_workitem"); +#endif + + odm_initialize_work_item( + dm, + &dm->ra_rpt_workitem, + (RT_WORKITEM_CALL_BACK)halrf_update_init_rate_work_item_callback, + (void *)adapter, + "ra_rpt_workitem"); + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_initialize_work_item( + dm, + &dm->fast_ant_training_workitem, + (RT_WORKITEM_CALL_BACK)odm_fast_ant_training_work_item_callback, + (void *)adapter, + "fast_ant_training_workitem"); +#endif + +#endif /*#if USE_WORKITEM*/ + +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_enter_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_enter_work_item_callback, + (void *)adapter, + "txbf_enter_work_item"); + + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_leave_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_leave_work_item_callback, + (void *)adapter, + "txbf_leave_work_item"); + + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_fw_ndpa_work_item_callback, + (void *)adapter, + "txbf_fw_ndpa_work_item"); + + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_clk_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_clk_work_item_callback, + (void *)adapter, + "txbf_clk_work_item"); + + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_rate_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_rate_work_item_callback, + (void *)adapter, + "txbf_rate_work_item"); + + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_status_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_status_work_item_callback, + (void *)adapter, + "txbf_status_work_item"); + + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_reset_tx_path_work_item_callback, + (void *)adapter, + "txbf_reset_tx_path_work_item"); + + odm_initialize_work_item( + dm, + &dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item, + (RT_WORKITEM_CALL_BACK)hal_com_txbf_get_tx_rate_work_item_callback, + (void *)adapter, + "txbf_get_tx_rate_work_item"); +#endif + +#if (PHYDM_LA_MODE_SUPPORT == 1) + odm_initialize_work_item( + dm, + &dm->adcsmp.adc_smp_work_item, + (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, + (void *)adapter, + "adc_smp_work_item"); + + odm_initialize_work_item( + dm, + &dm->adcsmp.adc_smp_work_item_1, + (RT_WORKITEM_CALL_BACK)adc_smp_work_item_callback, + (void *)adapter, + "adc_smp_work_item_1"); +#endif +} + +void odm_free_all_work_items(struct dm_struct *dm) +{ +#if USE_WORKITEM + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_free_work_item(&dm->dm_swat_table.phydm_sw_antenna_switch_workitem); +#endif + +#ifdef CONFIG_ADAPTIVE_SOML + odm_free_work_item(&dm->dm_soml_table.phydm_adaptive_soml_workitem); +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_free_work_item(&dm->phydm_evm_antdiv_workitem); +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) + odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_workitem); + odm_free_work_item(&dm->dm_sat_table.hl_smart_antenna_decision_workitem); +#endif + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_free_work_item(&dm->fast_ant_training_workitem); +#endif + odm_free_work_item(&dm->ra_rpt_workitem); +/*odm_free_work_item((&dm->sbdcnt_workitem));*/ +#endif + +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_enter_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_leave_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_fw_ndpa_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_clk_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_rate_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_status_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_reset_tx_path_work_item)); + odm_free_work_item((&dm->beamforming_info.txbf_info.txbf_get_tx_rate_work_item)); +#endif + +#if (PHYDM_LA_MODE_SUPPORT == 1) + odm_free_work_item((&dm->adcsmp.adc_smp_work_item)); + odm_free_work_item((&dm->adcsmp.adc_smp_work_item_1)); +#endif +} +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +void odm_init_all_timers(struct dm_struct *dm) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + odm_ant_div_timers(dm, INIT_ANTDIV_TIMMER); +#endif +#if (defined(PHYDM_TDMA_DIG_SUPPORT)) +#ifdef IS_USE_NEW_TDMA + phydm_tdma_dig_timers(dm, INIT_TDMA_DIG_TIMMER); +#endif +#endif +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_timers(dm, INIT_SOML_TIMMER); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_timers(dm, INIT_LNA_SAT_CHK_TIMMER); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_initialize_timer(dm, &dm->sbdcnt_timer, + (void *)phydm_sbd_callback, NULL, "SbdTimer"); +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_initialize_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer, + (void *)hal_com_txbf_fw_ndpa_timer_callback, NULL, + "txbf_fw_ndpa_timer"); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_initialize_timer(dm, &dm->beamforming_info.beamforming_timer, + (void *)beamforming_sw_timer_callback, NULL, + "beamforming_timer"); +#endif +#endif +} + +void odm_cancel_all_timers(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* @2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in win7*/ + if (dm->adapter == NULL) + return; +#endif + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + odm_ant_div_timers(dm, CANCEL_ANTDIV_TIMMER); +#endif +#ifdef PHYDM_TDMA_DIG_SUPPORT +#ifdef IS_USE_NEW_TDMA + phydm_tdma_dig_timers(dm, CANCEL_TDMA_DIG_TIMMER); +#endif +#endif +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_timers(dm, CANCEL_SOML_TIMMER); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_timers(dm, CANCEL_LNA_SAT_CHK_TIMMER); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_cancel_timer(dm, &dm->sbdcnt_timer); +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_cancel_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_cancel_timer(dm, &dm->beamforming_info.beamforming_timer); +#endif +#endif +} + +void odm_release_all_timers(struct dm_struct *dm) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + odm_ant_div_timers(dm, RELEASE_ANTDIV_TIMMER); +#endif +#ifdef PHYDM_TDMA_DIG_SUPPORT +#ifdef IS_USE_NEW_TDMA + phydm_tdma_dig_timers(dm, RELEASE_TDMA_DIG_TIMMER); +#endif +#endif +#ifdef CONFIG_ADAPTIVE_SOML + phydm_adaptive_soml_timers(dm, RELEASE_SOML_TIMMER); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_timers(dm, RELEASE_LNA_SAT_CHK_TIMMER); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_release_timer(dm, &dm->sbdcnt_timer); +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_release_timer(dm, &dm->beamforming_info.txbf_info.txbf_fw_ndpa_timer); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#ifdef PHYDM_BEAMFORMING_SUPPORT + odm_release_timer(dm, &dm->beamforming_info.beamforming_timer); +#endif +#endif +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void odm_init_all_threads( + struct dm_struct *dm) +{ +#ifdef TPT_THREAD + k_tpt_task_init(dm->priv); +#endif +} + +void odm_stop_all_threads( + struct dm_struct *dm) +{ +#ifdef TPT_THREAD + k_tpt_task_stop(dm->priv); +#endif +} +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/* @Justin: According to the current RRSI to adjust Response Frame TX power, + * 2012/11/05 + */ +void odm_dtc(struct dm_struct *dm) +{ +#ifdef CONFIG_DM_RESP_TXAGC +/* RSSI higher than this value, start to decade TX power */ +#define DTC_BASE 35 + +/* RSSI lower than this value, start to increase TX power */ +#define DTC_DWN_BASE (DTC_BASE - 5) + + /* RSSI vs TX power step mapping: decade TX power */ + static const u8 dtc_table_down[] = { + DTC_BASE, + (DTC_BASE + 5), + (DTC_BASE + 10), + (DTC_BASE + 15), + (DTC_BASE + 20), + (DTC_BASE + 25)}; + + /* RSSI vs TX power step mapping: increase TX power */ + static const u8 dtc_table_up[] = { + DTC_DWN_BASE, + (DTC_DWN_BASE - 5), + (DTC_DWN_BASE - 10), + (DTC_DWN_BASE - 15), + (DTC_DWN_BASE - 15), + (DTC_DWN_BASE - 20), + (DTC_DWN_BASE - 20), + (DTC_DWN_BASE - 25), + (DTC_DWN_BASE - 25), + (DTC_DWN_BASE - 30), + (DTC_DWN_BASE - 35)}; + + u8 i; + u8 dtc_steps = 0; + u8 sign; + u8 resp_txagc = 0; + + if (dm->rssi_min > DTC_BASE) { + /* need to decade the CTS TX power */ + sign = 1; + for (i = 0; i < ARRAY_SIZE(dtc_table_down); i++) { + if (dtc_table_down[i] >= dm->rssi_min || dtc_steps >= 6) + break; + else + dtc_steps++; + } + } +#if 0 + else if (dm->rssi_min > DTC_DWN_BASE) { + /* needs to increase the CTS TX power */ + sign = 0; + dtc_steps = 1; + for (i = 0; i < ARRAY_SIZE(dtc_table_up); i++) { + if (dtc_table_up[i] <= dm->rssi_min || dtc_steps >= 10) + break; + else + dtc_steps++; + } + } +#endif + else { + sign = 0; + dtc_steps = 0; + } + + resp_txagc = dtc_steps | (sign << 4); + resp_txagc = resp_txagc | (resp_txagc << 5); + odm_write_1byte(dm, 0x06d9, resp_txagc); + + PHYDM_DBG(dm, ODM_COMP_PWR_TRAIN, + "%s rssi_min:%u, set RESP_TXAGC to %s %u\n", __func__, + dm->rssi_min, sign ? "minus" : "plus", dtc_steps); +#endif /* @CONFIG_RESP_TXAGC_ADJUST */ +} + +#endif /* @#if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + +/*@<20170126, BB-Kevin>8188F D-CUT DC cancellation and 8821C*/ +void phydm_dc_cancellation(struct dm_struct *dm) +{ +#ifdef PHYDM_DC_CANCELLATION + u32 offset_i_hex[PHYDM_MAX_RF_PATH] = {0}; + u32 offset_q_hex[PHYDM_MAX_RF_PATH] = {0}; + u32 reg_value32[PHYDM_MAX_RF_PATH] = {0}; + u8 path = RF_PATH_A; + u8 set_result; + + if (!(dm->support_ic_type & ODM_DC_CANCELLATION_SUPPORT)) + return; + if ((dm->support_ic_type & ODM_RTL8188F) && + dm->cut_version < ODM_CUT_D) + return; + if ((dm->support_ic_type & ODM_RTL8192F) && + dm->cut_version == ODM_CUT_A) + return; + if (*dm->band_width == CHANNEL_WIDTH_5) + return; + if (*dm->band_width == CHANNEL_WIDTH_10) + return; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); + + /*@DC_Estimation (only for 2x2 ic now) */ + + for (path = RF_PATH_A; path < PHYDM_MAX_RF_PATH; path++) { + if (path > RF_PATH_A && + dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8188F | + ODM_RTL8710B | ODM_RTL8721D | + ODM_RTL8710C | ODM_RTL8723D)) + break; + else if (path > RF_PATH_B && + dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8192F)) + break; + if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) { + PHYDM_DBG(dm, ODM_COMP_API, "STOP_TRX_FAIL\n"); + return; + } + odm_write_dig(dm, 0x7e); + /*@Disable LNA*/ + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D | + ODM_RTL8710C)) + halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE); + /*Turn off 3-wire*/ + phydm_stop_3_wire(dm, PHYDM_SET); + if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D | + ODM_RTL8710B)) { + /*set debug port to 0x235*/ + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) { + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; + } + } else if (dm->support_ic_type & (ODM_RTL8721D | + ODM_RTL8710C)) { + /*set debug port to 0x200*/ + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_2, 0x200)) { + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; + } + } else if (dm->support_ic_type & ODM_RTL8821C) { + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; + } + phydm_bb_dbg_port_header_sel(dm, 0x0); + } else if (dm->support_ic_type & ODM_RTL8822B) { + if (path == RF_PATH_A && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x200)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; + } + if (path == RF_PATH_B && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x202)) { + /*set debug port to 0x200*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; + } + phydm_bb_dbg_port_header_sel(dm, 0x0); + } else if (dm->support_ic_type & ODM_RTL8192F) { + if (path == RF_PATH_A && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x235)) { + /*set debug port to 0x235*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; + } + if (path == RF_PATH_B && + !phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x23d)) { + /*set debug port to 0x23d*/ + PHYDM_DBG(dm, ODM_COMP_API, + "Set Debug port Fail\n"); + return; + } + } + + /*@disable CCK DCNF*/ + odm_set_bb_reg(dm, R_0xa78, MASKBYTE1, 0x0); + + PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation Begin!!!\n"); + + phydm_stop_ck320(dm, true); /*stop ck320*/ + + /* the same debug port both for path-a and path-b*/ + reg_value32[path] = phydm_get_bb_dbg_port_val(dm); + + phydm_stop_ck320(dm, false); /*start ck320*/ + + phydm_release_bb_dbg_port(dm); + /* @Turn on 3-wire*/ + phydm_stop_3_wire(dm, PHYDM_REVERT); + /* @Enable LNA*/ + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D | + ODM_RTL8710C)) + halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE); + + odm_write_dig(dm, 0x20); + + set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT); + + PHYDM_DBG(dm, ODM_COMP_API, "DC cancellation OK!!!\n"); + } + + /*@DC_Cancellation*/ + /*@DC compensation to CCK data path*/ + odm_set_bb_reg(dm, R_0xa9c, BIT(20), 0x1); + if (dm->support_ic_type & (ODM_RTL8188F | ODM_RTL8723D | + ODM_RTL8710B)) { + offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18; + offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? + (0x400 - offset_i_hex[0]) : + (0x1ff - offset_i_hex[0]); + offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? + (0x400 - offset_q_hex[0]) : + (0x1ff - offset_q_hex[0]); + + odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]); + odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]); + } else if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B)) { + /* Path-a */ + offset_i_hex[0] = (reg_value32[0] & 0xffc00) >> 10; + offset_q_hex[0] = reg_value32[0] & 0x3ff; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[0] = 0x400 - offset_i_hex[0]; + offset_q_hex[0] = 0x400 - offset_q_hex[0]; + + odm_set_bb_reg(dm, R_0xc10, 0x3c000000, + (0x3c0 & offset_i_hex[0]) >> 6); + odm_set_bb_reg(dm, R_0xc10, 0xfc00, 0x3f & offset_i_hex[0]); + odm_set_bb_reg(dm, R_0xc14, 0x3c000000, + (0x3c0 & offset_q_hex[0]) >> 6); + odm_set_bb_reg(dm, R_0xc14, 0xfc00, 0x3f & offset_q_hex[0]); + + /* Path-b */ + if (dm->rf_type > RF_1T1R) { + offset_i_hex[1] = (reg_value32[1] & 0xffc00) >> 10; + offset_q_hex[1] = reg_value32[1] & 0x3ff; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[1] = 0x400 - offset_i_hex[1]; + offset_q_hex[1] = 0x400 - offset_q_hex[1]; + + odm_set_bb_reg(dm, R_0xe10, 0x3c000000, + (0x3c0 & offset_i_hex[1]) >> 6); + odm_set_bb_reg(dm, R_0xe10, 0xfc00, + 0x3f & offset_i_hex[1]); + odm_set_bb_reg(dm, R_0xe14, 0x3c000000, + (0x3c0 & offset_q_hex[1]) >> 6); + odm_set_bb_reg(dm, R_0xe14, 0xfc00, + 0x3f & offset_q_hex[1]); + } + } else if (dm->support_ic_type & (ODM_RTL8192F)) { + /* Path-a I:df4[27:18],Q:df4[17:8]*/ + offset_i_hex[0] = (reg_value32[0] & 0xffc0000) >> 18; + offset_q_hex[0] = (reg_value32[0] & 0x3ff00) >> 8; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[0] = (offset_i_hex[0] >= 0x200) ? + (0x400 - offset_i_hex[0]) : + (0xff - offset_i_hex[0]); + offset_q_hex[0] = (offset_q_hex[0] >= 0x200) ? + (0x400 - offset_q_hex[0]) : + (0xff - offset_q_hex[0]); + /*Path-a I:c10[7:0],Q:c10[15:8]*/ + odm_set_bb_reg(dm, R_0xc10, 0xff, offset_i_hex[0]); + odm_set_bb_reg(dm, R_0xc10, 0xff00, offset_q_hex[0]); + + /* Path-b */ + if (dm->rf_type > RF_1T1R) { + /* @I:df4[27:18],Q:df4[17:8]*/ + offset_i_hex[1] = (reg_value32[1] & 0xffc0000) >> 18; + offset_q_hex[1] = (reg_value32[1] & 0x3ff00) >> 8; + + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[1] = (offset_i_hex[1] >= 0x200) ? + (0x400 - offset_i_hex[1]) : + (0xff - offset_i_hex[1]); + offset_q_hex[1] = (offset_q_hex[1] >= 0x200) ? + (0x400 - offset_q_hex[1]) : + (0xff - offset_q_hex[1]); + /*Path-b I:c18[7:0],Q:c18[15:8]*/ + odm_set_bb_reg(dm, R_0xc18, 0xff, offset_i_hex[1]); + odm_set_bb_reg(dm, R_0xc18, 0xff00, offset_q_hex[1]); + } + } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) { + /*judy modified 20180517*/ + offset_i_hex[0] = (reg_value32[0] & 0xff80000) >> 19; + offset_q_hex[0] = (reg_value32[0] & 0x3fe00) >> 9; + + if ((offset_i_hex[0] > 0xF && offset_i_hex[0] < 0x1F1) + || (offset_q_hex[0] > 0xF && offset_q_hex[0] < 0x1F1)) { + /*@Discard outliers*/ + offset_i_hex[0] = 0x0; + offset_q_hex[0] = 0x0; + } else { + /*@Before filling into registers, + *offset should be multiplexed (-1) + */ + offset_i_hex[0] = 0x200 - offset_i_hex[0]; + offset_q_hex[0] = 0x200 - offset_q_hex[0]; + } + odm_set_bb_reg(dm, R_0x950, 0x1ff, offset_i_hex[0]); + odm_set_bb_reg(dm, R_0x950, 0x1ff0000, offset_q_hex[0]); + } +#endif +} + +void phydm_receiver_blocking(void *dm_void) +{ +#ifdef CONFIG_RECEIVER_BLOCKING + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 chnl = *dm->channel; + u8 bw = *dm->band_width; + u32 bb_regf0 = odm_get_bb_reg(dm, R_0xf0, 0xf000); + + if (!(dm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT) || + *dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE) + return; + + if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 < 8) || + dm->support_ic_type & ODM_RTL8192E) { + /*@8188E_T version*/ + if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode) + goto end; + + if (bw == CHANNEL_WIDTH_20 && chnl == 1) { + phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2410, + PHYDM_DONT_CARE); + dm->is_rx_blocking_en = true; + } else if ((bw == CHANNEL_WIDTH_20) && (chnl == 13)) { + phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473, + PHYDM_DONT_CARE); + dm->is_rx_blocking_en = true; + } else if (dm->is_rx_blocking_en && chnl != 1 && chnl != 13) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f); + dm->is_rx_blocking_en = false; + } + return; + } else if ((dm->support_ic_type & ODM_RTL8188E && bb_regf0 >= 8)) { + /*@8188E_S version*/ + if (dm->consecutive_idlel_time <= 10 || *dm->mp_mode) + goto end; + + if (bw == CHANNEL_WIDTH_20 && chnl == 13) { + phydm_nbi_setting(dm, FUNC_ENABLE, chnl, 20, 2473, + PHYDM_DONT_CARE); + dm->is_rx_blocking_en = true; + } else if (dm->is_rx_blocking_en && chnl != 13) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f); + dm->is_rx_blocking_en = false; + } + return; + } + +end: + if (dm->is_rx_blocking_en) { + phydm_nbi_enable(dm, FUNC_DISABLE); + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, 0x1f); + dm->is_rx_blocking_en = false; + } +#endif +} + +void phydm_dyn_bw_indication(void *dm_void) +{ +#ifdef CONFIG_BW_INDICATION + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 en_auto_bw_th = dm->en_auto_bw_th; + + if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT)) + return; + + /*driver decide bw cobime timing*/ + if (dm->dis_dym_bw_indication) { + if (*dm->dis_dym_bw_indication) + return; + } + + /*check for auto bw*/ + if (dm->rssi_min <= en_auto_bw_th && dm->is_linked) { + phydm_bw_fixed_enable(dm, FUNC_DISABLE); + return; + } + + phydm_bw_fixed_setting(dm); +#endif +} + diff --git a/hal/phydm/phydm.h b/hal/phydm/phydm.h new file mode 100644 index 0000000..2f96186 --- /dev/null +++ b/hal/phydm/phydm.h @@ -0,0 +1,1574 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +/*@============================================================*/ +/*@include files*/ +/*@============================================================*/ +/*PHYDM header*/ +#include "phydm_pre_define.h" +#include "phydm_features.h" +#include "phydm_dig.h" +#ifdef CONFIG_PATH_DIVERSITY +#include "phydm_pathdiv.h" +#endif +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY +#include "phydm_antdiv.h" +#endif + +#include "phydm_soml.h" + +#ifdef CONFIG_SMART_ANTENNA +#include "phydm_smt_ant.h" +#endif +#ifdef CONFIG_ANT_DETECTION +#include "phydm_antdect.h" +#endif +#include "phydm_rainfo.h" +#ifdef CONFIG_DYNAMIC_TX_TWR +#include "phydm_dynamictxpower.h" +#endif +#include "phydm_cfotracking.h" +#include "phydm_adaptivity.h" +#include "phydm_dfs.h" +#include "phydm_ccx.h" +#include "txbf/phydm_hal_txbf_api.h" +#if (PHYDM_LA_MODE_SUPPORT) +#include "phydm_adc_sampling.h" +#endif +#ifdef CONFIG_PSD_TOOL +#include "phydm_psd.h" +#endif +#ifdef PHYDM_PRIMARY_CCA +#include "phydm_primary_cca.h" +#endif +#include "phydm_cck_pd.h" +#include "phydm_rssi_monitor.h" +#ifdef PHYDM_AUTO_DEGBUG +#include "phydm_auto_dbg.h" +#endif +#include "phydm_math_lib.h" +#include "phydm_noisemonitor.h" +#include "phydm_api.h" +#ifdef PHYDM_POWER_TRAINING_SUPPORT +#include "phydm_pow_train.h" +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +#include "phydm_lna_sat.h" +#endif +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT +#include "phydm_pmac_tx_setting.h" +#endif +#ifdef PHYDM_MP_SUPPORT +#include "phydm_mp.h" +#endif + +#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT +#include "phydm_cck_rx_pathdiv.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #include "phydm_beamforming.h" +#endif + +#ifdef CONFIG_DIRECTIONAL_BF +#include "phydm_direct_bf.h" +#endif + +#include "phydm_regtable.h" + +/*@HALRF header*/ +#include "halrf/halrf_iqk.h" +#include "halrf/halrf_dpk.h" +#include "halrf/halrf.h" +#include "halrf/halrf_powertracking.h" +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #include "halrf/halphyrf_ap.h" +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #include "halrf/halphyrf_ce.h" +#elif (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + #include "halrf/halphyrf_win.h" +#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + #include "halrf/halphyrf_iot.h" +#endif + +extern const u16 phy_rate_table[84]; + +/*@============================================================*/ +/*@Definition */ +/*@============================================================*/ + +/* Traffic load decision */ +#define TRAFFIC_NO_TP 0 +#define TRAFFIC_ULTRA_LOW 1 +#define TRAFFIC_LOW 2 +#define TRAFFIC_MID 3 +#define TRAFFIC_HIGH 4 + +#define NONE 0 + +#if defined(DM_ODM_CE_MAC80211) +#define MAX_2(x, y) \ + __max2(typeof(x), typeof(y), \ + x, y) +#define __max2(t1, t2, x, y) ({ \ + t1 m80211_max1 = (x); \ + t2 m80211_max2 = (y); \ + m80211_max1 > m80211_max2 ? m80211_max1 : m80211_max2; }) + +#define MIN_2(x, y) \ + __min2(typeof(x), typeof(y), \ + x, y) +#define __min2(t1, t2, x, y) ({ \ + t1 m80211_min1 = (x); \ + t2 m80211_min2 = (y); \ + m80211_min1 < m80211_min2 ? m80211_min1 : m80211_min2; }) + +#define DIFF_2(x, y) \ + __diff2(typeof(x), typeof(y), \ + x, y) +#define __diff2(t1, t2, x, y) ({ \ + t1 __d1 = (x); \ + t2 __d2 = (y); \ + (__d1 >= __d2) ? (__d1 - __d2) : (__d2 - __d1); }) +#else +#define MAX_2(_x_, _y_) (((_x_) > (_y_)) ? (_x_) : (_y_)) +#define MIN_2(_x_, _y_) (((_x_) < (_y_)) ? (_x_) : (_y_)) +#define DIFF_2(_x_, _y_) ((_x_ >= _y_) ? (_x_ - _y_) : (_y_ - _x_)) +#endif + +#define IS_GREATER(_x_, _y_) (((_x_) >= (_y_)) ? true : false) +#define IS_LESS(_x_, _y_) (((_x_) < (_y_)) ? true : false) + +#if defined(DM_ODM_CE_MAC80211) +#define BYTE_DUPLICATE_2_DWORD(B0) ({ \ + u32 __b_dup = (B0);\ + (((__b_dup) << 24) | ((__b_dup) << 16) | ((__b_dup) << 8) | (__b_dup));\ + }) +#else +#define BYTE_DUPLICATE_2_DWORD(B0) \ + (((B0) << 24) | ((B0) << 16) | ((B0) << 8) | (B0)) +#endif +#define BYTE_2_DWORD(B3, B2, B1, B0) \ + (((B3) << 24) | ((B2) << 16) | ((B1) << 8) | (B0)) +#define BIT_2_BYTE(B3, B2, B1, B0) \ + (((B3) << 3) | ((B2) << 2) | ((B1) << 1) | (B0)) + +/*@For cmn sta info*/ +#if defined(DM_ODM_CE_MAC80211) +#define is_sta_active(sta) ({ \ + struct cmn_sta_info *__sta = (sta); \ + ((__sta) && (__sta->dm_ctrl & STA_DM_CTRL_ACTIVE)); \ + }) + +#define IS_FUNC_EN(name) ({ \ + u8 *__is_func_name = (name); \ + (__is_func_name) && (*__is_func_name); \ + }) +#else +#define is_sta_active(sta) ((sta) && (sta->dm_ctrl & STA_DM_CTRL_ACTIVE)) + +#define IS_FUNC_EN(name) ((name) && (*name)) +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define PHYDM_WATCH_DOG_PERIOD 1 /*second*/ +#else + #define PHYDM_WATCH_DOG_PERIOD 2 /*second*/ +#endif + +#define PHY_HIST_SIZE 12 +#define PHY_HIST_TH_SIZE (PHY_HIST_SIZE - 1) + +#define S_TO_US 1000000 + +/*@============================================================*/ +/*structure and define*/ +/*@============================================================*/ + +#define dm_type_by_fw 0 +#define dm_type_by_driver 1 + +#define HW_IGI_TXINFO_TABLE_SIZE 64 + +#ifdef BB_RAM_SUPPORT + +struct phydm_bb_ram_per_sta { + /* @Reg0x1E84 for RAM I/O*/ + boolean hw_igi_en; + boolean tx_pwr_offset0_en; + boolean tx_pwr_offset1_en; + /* @ macid from 0 to 63, above 63 => mapping to 63*/ + u8 macid_addr; + /* @hw_igi value for paths after packet Tx in a period of time*/ + u8 hw_igi; + /* @tx_pwr_offset0 offset for Tx power index*/ + s8 tx_pwr_offset0; + s8 tx_pwr_offset1; + +}; + +struct phydm_bb_ram_ctrl { + /*@ For 98F/14B/22C/12F, each tx_pwr_ofst step will be 1dB*/ + struct phydm_bb_ram_per_sta pram_sta_ctrl[HW_IGI_TXINFO_TABLE_SIZE]; + /*------------ For table2 do not set power offset by macid --------*/ + /* For type == 2'b10, 0x1e70[22:16] = tx_pwr_offset_reg0, 0x1e70[23] = enable */ + boolean tx_pwr_ofst_reg0_en; + u8 tx_pwr_ofst_reg0; + /* For type == 2'b11, 0x1e70[30:24] = tx_pwr_offset_reg1, 0x1e70[31] = enable */ + boolean tx_pwr_ofst_reg1_en; + u8 tx_pwr_ofst_reg1; + boolean hwigi_watchdog_en; + u64 macid_is_linked; + u64 hwigi_macid_is_linked; +}; + +#endif + +struct phydm_phystatus_statistic { + /*@[CCK]*/ + u32 rssi_cck_sum; + u32 rssi_cck_cnt; + u32 rssi_beacon_sum[RF_PATH_MEM_SIZE]; + u32 rssi_beacon_cnt; + #ifdef PHYSTS_3RD_TYPE_SUPPORT + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u32 rssi_cck_sum_abv_2ss[RF_PATH_MEM_SIZE - 1]; + #endif + #endif + /*@[OFDM]*/ + u32 rssi_ofdm_sum[RF_PATH_MEM_SIZE]; + u32 rssi_ofdm_cnt; + u32 evm_ofdm_sum; + u32 snr_ofdm_sum[RF_PATH_MEM_SIZE]; + u16 evm_ofdm_hist[PHY_HIST_SIZE]; + u16 snr_ofdm_hist[PHY_HIST_SIZE]; + /*@[1SS]*/ + u32 rssi_1ss_cnt; + u32 rssi_1ss_sum[RF_PATH_MEM_SIZE]; + u32 evm_1ss_sum; + u32 snr_1ss_sum[RF_PATH_MEM_SIZE]; + u16 evm_1ss_hist[PHY_HIST_SIZE]; + u16 snr_1ss_hist[PHY_HIST_SIZE]; + /*@[2SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u32 rssi_2ss_cnt; + u32 rssi_2ss_sum[RF_PATH_MEM_SIZE]; + u32 evm_2ss_sum[2]; + u32 snr_2ss_sum[RF_PATH_MEM_SIZE]; + u16 evm_2ss_hist[2][PHY_HIST_SIZE]; + u16 snr_2ss_hist[2][PHY_HIST_SIZE]; + #endif + /*@[3SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + u32 rssi_3ss_cnt; + u32 rssi_3ss_sum[RF_PATH_MEM_SIZE]; + u32 evm_3ss_sum[3]; + u32 snr_3ss_sum[RF_PATH_MEM_SIZE]; + u16 evm_3ss_hist[3][PHY_HIST_SIZE]; + u16 snr_3ss_hist[3][PHY_HIST_SIZE]; + #endif + /*@[4SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + u32 rssi_4ss_cnt; + u32 rssi_4ss_sum[RF_PATH_MEM_SIZE]; + u32 evm_4ss_sum[4]; + u32 snr_4ss_sum[RF_PATH_MEM_SIZE]; + u16 evm_4ss_hist[4][PHY_HIST_SIZE]; + u16 snr_4ss_hist[4][PHY_HIST_SIZE]; + #endif +#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + u16 p4_cnt[RF_PATH_MEM_SIZE]; /*phy-sts page4 cnt*/ + u16 cn_sum[RF_PATH_MEM_SIZE]; /*condition number*/ + u16 cn_hist[RF_PATH_MEM_SIZE][PHY_HIST_SIZE]; +#endif +}; + +struct phydm_phystatus_avg { + /*@[CCK]*/ + u8 rssi_cck_avg; + u8 rssi_beacon_avg[RF_PATH_MEM_SIZE]; + #ifdef PHYSTS_3RD_TYPE_SUPPORT + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u8 rssi_cck_avg_abv_2ss[RF_PATH_MEM_SIZE - 1]; + #endif + #endif + /*@[OFDM]*/ + u8 rssi_ofdm_avg[RF_PATH_MEM_SIZE]; + u8 evm_ofdm_avg; + u8 snr_ofdm_avg[RF_PATH_MEM_SIZE]; + /*@[1SS]*/ + u8 rssi_1ss_avg[RF_PATH_MEM_SIZE]; + u8 evm_1ss_avg; + u8 snr_1ss_avg[RF_PATH_MEM_SIZE]; + /*@[2SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + u8 rssi_2ss_avg[RF_PATH_MEM_SIZE]; + u8 evm_2ss_avg[2]; + u8 snr_2ss_avg[RF_PATH_MEM_SIZE]; + #endif + /*@[3SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + u8 rssi_3ss_avg[RF_PATH_MEM_SIZE]; + u8 evm_3ss_avg[3]; + u8 snr_3ss_avg[RF_PATH_MEM_SIZE]; + #endif + /*@[4SS]*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + u8 rssi_4ss_avg[RF_PATH_MEM_SIZE]; + u8 evm_4ss_avg[4]; + u8 snr_4ss_avg[RF_PATH_MEM_SIZE]; + #endif +}; + +struct odm_phy_dbg_info { + /*@ODM Write,debug info*/ + u32 num_qry_phy_status_cck; + u32 num_qry_phy_status_ofdm; +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) + u32 num_qry_mu_pkt; + u32 num_qry_bf_pkt; + u16 num_mu_vht_pkt[VHT_RATE_NUM]; + boolean is_ldpc_pkt; + boolean is_stbc_pkt; + u8 num_of_ppdu[4]; + u8 gid_num[4]; +#endif + u32 condi_num; /*@condition number U(18,4)*/ + u8 condi_num_cdf[CN_CNT_MAX]; + u8 num_qry_beacon_pkt; + u8 beacon_cnt_in_period; /*@beacon cnt within watchdog period*/ + u8 beacon_phy_rate; + u8 show_phy_sts_all_pkt; /*@Show phy status witch not match BSSID*/ + u16 show_phy_sts_max_cnt; /*@show number of phy-status row data per PHYDM watchdog*/ + u16 show_phy_sts_cnt; + u16 num_qry_legacy_pkt[LEGACY_RATE_NUM]; + u16 num_qry_ht_pkt[HT_RATE_NUM]; + u16 num_qry_pkt_sc_20m[LOW_BW_RATE_NUM]; /*@20M SC*/ + boolean ht_pkt_not_zero; + boolean low_bw_20_occur; + #if ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT) + u16 num_qry_vht_pkt[VHT_RATE_NUM]; + u16 num_qry_pkt_sc_40m[LOW_BW_RATE_NUM]; /*@40M SC*/ + boolean vht_pkt_not_zero; + boolean low_bw_40_occur; + #endif + u16 snr_hist_th[PHY_HIST_TH_SIZE]; + u16 evm_hist_th[PHY_HIST_TH_SIZE]; + #ifdef PHYSTS_3RD_TYPE_SUPPORT + u16 cn_hist_th[PHY_HIST_TH_SIZE]; /*U(16,1)*/ + u8 condition_num_seg0; + u8 eigen_val[4]; + s16 cfo_tail[4]; /*per-path's cfo_tail */ + #endif + struct phydm_phystatus_statistic physts_statistic_info; + struct phydm_phystatus_avg phystatus_statistic_avg; +}; + +enum odm_cmninfo { + /*@Fixed value*/ + /*@-----------HOOK BEFORE REG INIT-----------*/ + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, + ODM_CMNINFO_INTERFACE, + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, + ODM_CMNINFO_CUT_VER, + ODM_CMNINFO_FAB_VER, + ODM_CMNINFO_FW_VER, + ODM_CMNINFO_FW_SUB_VER, + ODM_CMNINFO_RF_TYPE, + ODM_CMNINFO_RFE_TYPE, + ODM_CMNINFO_DPK_EN, + ODM_CMNINFO_BOARD_TYPE, + ODM_CMNINFO_PACKAGE_TYPE, + ODM_CMNINFO_EXT_LNA, + ODM_CMNINFO_5G_EXT_LNA, + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_5G_EXT_PA, + ODM_CMNINFO_GPA, + ODM_CMNINFO_APA, + ODM_CMNINFO_GLNA, + ODM_CMNINFO_ALNA, + ODM_CMNINFO_TDMA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_EXT_LNA_GAIN, + ODM_CMNINFO_PATCH_ID, + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + ODM_CMNINFO_CONFIG_BB_RF, + ODM_CMNINFO_IQKPAOFF, + ODM_CMNINFO_HUBUSBMODE, + ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, + ODM_CMNINFO_TX_TP, + ODM_CMNINFO_RX_TP, + ODM_CMNINFO_SOUNDING_SEQ, + ODM_CMNINFO_REGRFKFREEENABLE, + ODM_CMNINFO_RFKFREEENABLE, + ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, + ODM_CMNINFO_VALID_PATH_SET, + ODM_CMNINFO_EFUSE0X3D8, + ODM_CMNINFO_EFUSE0X3D7, + ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, + ODM_CMNINFO_X_CAP_SETTING, + ODM_CMNINFO_ADVANCE_OTA, + ODM_CMNINFO_HP_HWID, + ODM_CMNINFO_TSSI_ENABLE, /*also for cmn_info_update*/ + ODM_CMNINFO_DIS_DPD, + ODM_CMNINFO_POWER_VOLTAGE, + ODM_CMNINFO_ANTDIV_GPIO, + ODM_CMNINFO_EN_AUTO_BW_TH, + ODM_CMNINFO_PEAK_DETECT_MODE, + /*@-----------HOOK BEFORE REG INIT-----------*/ + + /*@Dynamic value:*/ + + /*@--------- POINTER REFERENCE-----------*/ + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_BAND, + ODM_CMNINFO_SEC_CHNL_OFFSET, + ODM_CMNINFO_SEC_MODE, + ODM_CMNINFO_BW, + ODM_CMNINFO_CHNL, + ODM_CMNINFO_FORCED_RATE, + ODM_CMNINFO_ANT_DIV, + ODM_CMNINFO_PATH_DIV, + ODM_CMNINFO_ADAPTIVE_SOML, + ODM_CMNINFO_ADAPTIVITY, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + ODM_CMNINFO_P2P_LINK, + ODM_CMNINFO_FCS_MODE, + ODM_CMNINFO_IS1ANTENNA, + ODM_CMNINFO_RFDEFAULTPATH, + ODM_CMNINFO_DFS_MASTER_ENABLE, + ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, + ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, + ODM_CMNINFO_SOFT_AP_MODE, + ODM_CMNINFO_MP_MODE, + ODM_CMNINFO_INTERRUPT_MASK, + ODM_CMNINFO_BB_OPERATION_MODE, + ODM_CMNINFO_BF_ANTDIV_DECISION, + ODM_CMNINFO_MANUAL_SUPPORTABILITY, + ODM_CMNINFO_EN_DYM_BW_INDICATION, + /*@--------- POINTER REFERENCE-----------*/ + + /*@------------CALL BY VALUE-------------*/ + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK_IN_PROGRESS, + ODM_CMNINFO_LINK, + ODM_CMNINFO_CMW500LINK, + ODM_CMNINFO_STATION_STATE, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_RSSI_MIN_BY_PATH, + ODM_CMNINFO_DBG_COMP, + ODM_CMNINFO_RA_THRESHOLD_HIGH, /*to be removed*/ + ODM_CMNINFO_RA_THRESHOLD_LOW, /*to be removed*/ + ODM_CMNINFO_RF_ANTENNA_TYPE, + ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, + ODM_CMNINFO_BE_FIX_TX_ANT, + ODM_CMNINFO_BT_ENABLED, + ODM_CMNINFO_BT_HS_CONNECT_PROCESS, + ODM_CMNINFO_BT_HS_RSSI, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_LIMITED_DIG, + ODM_CMNINFO_AP_TOTAL_NUM, + ODM_CMNINFO_POWER_TRAINING, + ODM_CMNINFO_DFS_REGION_DOMAIN, + ODM_CMNINFO_BT_CONTINUOUS_TURN, + ODM_CMNINFO_IS_DOWNLOAD_FW, + ODM_CMNINFO_PHYDM_PATCH_ID, + ODM_CMNINFO_RRSR_VAL, + ODM_CMNINFO_LINKED_BF_SUPPORT, + ODM_CMNINFO_FLATNESS_TYPE, + /*@------------CALL BY VALUE-------------*/ + + /*@Dynamic ptr array hook itms.*/ + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_MAX, + +}; + +enum phydm_rfe_bb_source_sel { + PAPE_2G = 0, + PAPE_5G = 1, + LNA0N_2G = 2, + LNAON_5G = 3, + TRSW = 4, + TRSW_B = 5, + GNT_BT = 6, + ZERO = 7, + ANTSEL_0 = 8, + ANTSEL_1 = 9, + ANTSEL_2 = 0xa, + ANTSEL_3 = 0xb, + ANTSEL_4 = 0xc, + ANTSEL_5 = 0xd, + ANTSEL_6 = 0xe, + ANTSEL_7 = 0xf +}; + +enum phydm_info_query { + PHYDM_INFO_FA_OFDM, + PHYDM_INFO_FA_CCK, + PHYDM_INFO_FA_TOTAL, + PHYDM_INFO_CCA_OFDM, + PHYDM_INFO_CCA_CCK, + PHYDM_INFO_CCA_ALL, + PHYDM_INFO_CRC32_OK_VHT, + PHYDM_INFO_CRC32_OK_HT, + PHYDM_INFO_CRC32_OK_LEGACY, + PHYDM_INFO_CRC32_OK_CCK, + PHYDM_INFO_CRC32_ERROR_VHT, + PHYDM_INFO_CRC32_ERROR_HT, + PHYDM_INFO_CRC32_ERROR_LEGACY, + PHYDM_INFO_CRC32_ERROR_CCK, + PHYDM_INFO_EDCCA_FLAG, + PHYDM_INFO_OFDM_ENABLE, + PHYDM_INFO_CCK_ENABLE, + PHYDM_INFO_CRC32_OK_HT_AGG, + PHYDM_INFO_CRC32_ERROR_HT_AGG, + PHYDM_INFO_DBG_PORT_0, + PHYDM_INFO_CURR_IGI, + PHYDM_INFO_RSSI_MIN, + PHYDM_INFO_RSSI_MAX, + PHYDM_INFO_CLM_RATIO, + PHYDM_INFO_NHM_RATIO, + PHYDM_INFO_NHM_NOISE_PWR, + PHYDM_INFO_NHM_PWR, + PHYDM_INFO_NHM_ENV_RATIO, + PHYDM_INFO_TXEN_CCK, + PHYDM_INFO_TXEN_OFDM, + +}; + +enum phydm_api { + PHYDM_API_NBI = 1, + PHYDM_API_CSI_MASK = 2, +}; + +enum phydm_func_idx { /*@F_XXX = PHYDM XXX function*/ + + F00_DIG = 0, + F01_RA_MASK = 1, + F02_DYN_TXPWR = 2, + F03_FA_CNT = 3, + F04_RSSI_MNTR = 4, + F05_CCK_PD = 5, + F06_ANT_DIV = 6, + F07_SMT_ANT = 7, + F08_PWR_TRAIN = 8, + F09_RA = 9, + F10_PATH_DIV = 10, + F11_DFS = 11, + F12_DYN_ARFR = 12, + F13_ADPTVTY = 13, + F14_CFO_TRK = 14, + F15_ENV_MNTR = 15, + F16_PRI_CCA = 16, + F17_ADPTV_SOML = 17, + F18_LNA_SAT_CHK = 18, +}; + +/*@=[PHYDM supportability]==========================================*/ +enum odm_ability { + ODM_BB_DIG = BIT(F00_DIG), + ODM_BB_RA_MASK = BIT(F01_RA_MASK), + ODM_BB_DYNAMIC_TXPWR = BIT(F02_DYN_TXPWR), + ODM_BB_FA_CNT = BIT(F03_FA_CNT), + ODM_BB_RSSI_MONITOR = BIT(F04_RSSI_MNTR), + ODM_BB_CCK_PD = BIT(F05_CCK_PD), + ODM_BB_ANT_DIV = BIT(F06_ANT_DIV), + ODM_BB_SMT_ANT = BIT(F07_SMT_ANT), + ODM_BB_PWR_TRAIN = BIT(F08_PWR_TRAIN), + ODM_BB_RATE_ADAPTIVE = BIT(F09_RA), + ODM_BB_PATH_DIV = BIT(F10_PATH_DIV), + ODM_BB_DFS = BIT(F11_DFS), + ODM_BB_DYNAMIC_ARFR = BIT(F12_DYN_ARFR), + ODM_BB_ADAPTIVITY = BIT(F13_ADPTVTY), + ODM_BB_CFO_TRACKING = BIT(F14_CFO_TRK), + ODM_BB_ENV_MONITOR = BIT(F15_ENV_MNTR), + ODM_BB_PRIMARY_CCA = BIT(F16_PRI_CCA), + ODM_BB_ADAPTIVE_SOML = BIT(F17_ADPTV_SOML), + ODM_BB_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), +}; + +/*@=[PHYDM Debug Component]=====================================*/ +enum phydm_dbg_comp { + /*@BB Driver Functions*/ + DBG_DIG = BIT(F00_DIG), + DBG_RA_MASK = BIT(F01_RA_MASK), + DBG_DYN_TXPWR = BIT(F02_DYN_TXPWR), + DBG_FA_CNT = BIT(F03_FA_CNT), + DBG_RSSI_MNTR = BIT(F04_RSSI_MNTR), + DBG_CCKPD = BIT(F05_CCK_PD), + DBG_ANT_DIV = BIT(F06_ANT_DIV), + DBG_SMT_ANT = BIT(F07_SMT_ANT), + DBG_PWR_TRAIN = BIT(F08_PWR_TRAIN), + DBG_RA = BIT(F09_RA), + DBG_PATH_DIV = BIT(F10_PATH_DIV), + DBG_DFS = BIT(F11_DFS), + DBG_DYN_ARFR = BIT(F12_DYN_ARFR), + DBG_ADPTVTY = BIT(F13_ADPTVTY), + DBG_CFO_TRK = BIT(F14_CFO_TRK), + DBG_ENV_MNTR = BIT(F15_ENV_MNTR), + DBG_PRI_CCA = BIT(F16_PRI_CCA), + DBG_ADPTV_SOML = BIT(F17_ADPTV_SOML), + DBG_LNA_SAT_CHK = BIT(F18_LNA_SAT_CHK), + /*Neet to re-arrange*/ + DBG_PHY_STATUS = BIT(20), + DBG_TMP = BIT(21), + DBG_FW_TRACE = BIT(22), + DBG_TXBF = BIT(23), + DBG_COMMON_FLOW = BIT(24), + DBG_COMP_MCC = BIT(25), + DBG_FW_DM = BIT(26), + DBG_DM_SUMMARY = BIT(27), + ODM_PHY_CONFIG = BIT(28), + ODM_COMP_INIT = BIT(29), + DBG_CMN = BIT(30),/*@common*/ + ODM_COMP_API = BIT(31) +}; + +/*@=========================================================*/ + +/*@ODM_CMNINFO_ONE_PATH_CCA*/ +enum odm_cca_path { + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}; + +enum phy_reg_pg_type { + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +}; + +enum phydm_offload_ability { + PHYDM_PHY_PARAM_OFFLOAD = BIT(0), + PHYDM_RF_IQK_OFFLOAD = BIT(1), + PHYDM_RF_DPK_OFFLOAD = BIT(2), +}; + +enum phydm_init_result { + PHYDM_INIT_SUCCESS = 0, + PHYDM_INIT_FAIL_BBRF_REG_INVALID = 1 +}; + +struct phydm_pause_lv { + s8 lv_dig; + s8 lv_cckpd; + s8 lv_antdiv; + s8 lv_adapt; + s8 lv_adsl; +}; + +struct phydm_func_poiner { + void (*pause_phydm_handler)(void *dm_void, u32 *val_buf, u8 val_len); +}; + +struct pkt_process_info { + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + /*@send phystatus in each sampling time*/ + boolean physts_auto_swch_en; + u8 mac_ppdu_cnt; + u8 phy_ppdu_cnt; /*change with phy cca cnt*/ + u8 page_bitmap_target; + u8 page_bitmap_record; + u8 ppdu_phy_rate; + u8 ppdu_macid; + boolean is_1st_mpdu; + #endif + u8 lna_idx; + u8 vga_idx; +}; + +#ifdef ODM_CONFIG_BT_COEXIST +struct phydm_bt_info { + boolean is_bt_enabled; /*@BT is enabled*/ + boolean is_bt_connect_process; /*@BT HS is under connection progress.*/ + u8 bt_hs_rssi; /*@BT HS mode wifi rssi value.*/ + boolean is_bt_hs_operation; /*@BT HS mode is under progress*/ + boolean is_bt_limited_dig; /*@BT is busy.*/ +}; +#endif + +struct phydm_iot_center { + boolean is_linked_cmw500; + u8 win_patch_id; /*Customer ID*/ + boolean patch_id_100f0401; + boolean patch_id_10120200; + boolean patch_id_40010700; + boolean patch_id_021f0800; + boolean patch_id_011f0500; + u32 phydm_patch_id; /*temp for CCX IOT */ +}; + +#if (RTL8822B_SUPPORT) +struct drp_rtl8822b_struct { + enum bb_path path_judge; + u16 path_a_cck_fa; + u16 path_b_cck_fa; +}; +#endif + +#ifdef CONFIG_MCC_DM +#define MCC_DM_REG_NUM 32 +struct _phydm_mcc_dm_ { + u8 mcc_pre_status; + u8 mcc_reg_id[MCC_DM_REG_NUM]; + u16 mcc_dm_reg[MCC_DM_REG_NUM]; + u8 mcc_dm_val[MCC_DM_REG_NUM][2]; + /*mcc DIG*/ + u8 mcc_rssi[2]; + /*u8 mcc_igi[2];*/ + + /* need to be config by driver*/ + u8 mcc_status; + u8 sta_macid[2][NUM_STA]; + u16 mcc_rf_ch[2]; + +}; +#endif + +#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) +struct phydm_physts { + u8 cck_gi_u_bnd; + u8 cck_gi_l_bnd; +}; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (RT_PLATFORM != PLATFORM_LINUX) + typedef + #endif + +struct dm_struct { +#else/*for AP, CE Team*/ +struct dm_struct { +#endif + /*@Add for different team use temporarily*/ + void *adapter; /*@For CE/NIC team*/ + struct rtl8192cd_priv *priv; /*@For AP team*/ + boolean odm_ready; + enum phy_reg_pg_type phy_reg_pg_value_type; + u8 phy_reg_pg_version; + u64 support_ability; /*@PHYDM function Supportability*/ + u64 pause_ability; /*@PHYDM function pause Supportability*/ + u64 debug_components; + u8 cmn_dbg_msg_period; + u8 cmn_dbg_msg_cnt; + u32 fw_debug_components; + u32 num_qry_phy_status_all; /*@CCK + OFDM*/ + u32 last_num_qry_phy_status_all; + u32 rx_pwdb_ave; + boolean is_init_hw_info_by_rfe; + + //TSSI + u8 en_tssi_mode; + + /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + boolean is_cck_high_power; + u8 rf_path_rx_enable; + /*@------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + + /* @COMMON INFORMATION */ + + /*@Init value*/ + /*@-----------HOOK BEFORE REG INIT-----------*/ + + u8 support_platform; /*@PHYDM Platform info WIN/AP/CE = 1/2/3 */ + u8 normal_rx_path; + u8 valid_path_set; /*@use for single rx path only*/ + boolean brxagcswitch; /* @for rx AGC table switch in Microsoft case */ + u8 support_interface; /*@PHYDM PCIE/USB/SDIO = 1/2/3*/ + u32 support_ic_type; /*@PHYDM supported IC*/ + enum phydm_api_host run_in_drv_fw; /*@PHYDM API is using in FW or Driver*/ + u8 ic_ip_series; /*N/AC/JGR3*/ + enum phydm_phy_sts_type ic_phy_sts_type; /*@Type1/type2/type3*/ + u8 cut_version; /*@cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ + u8 fab_version; /*@Fab version TSMC/UMC = 0/1*/ + u8 fw_version; + u8 fw_sub_version; + u8 rf_type; /*@RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ + u8 rfe_type; + u8 board_type; + u8 package_type; + u16 type_glna; + u16 type_gpa; + u16 type_alna; + u16 type_apa; + u8 ext_lna; /*@with 2G external LNA NO/Yes = 0/1*/ + u8 ext_lna_5g; /*@with 5G external LNA NO/Yes = 0/1*/ + u8 ext_pa; /*@with 2G external PNA NO/Yes = 0/1*/ + u8 ext_pa_5g; /*@with 5G external PNA NO/Yes = 0/1*/ + u8 efuse0x3d7; /*@with Efuse number*/ + u8 efuse0x3d8; + u8 ext_trsw; /*@with external TRSW NO/Yes = 0/1*/ + u8 ext_lna_gain; /*@gain of external lna*/ + boolean is_in_hct_test; + u8 wifi_test; + boolean is_dual_mac_smart_concurrent; + u32 bk_support_ability; /*SD4 only*/ + u8 with_extenal_ant_switch; + /*@cck agc relative*/ + boolean cck_new_agc; + s8 cck_lna_gain_table[8]; + u8 cck_sat_cnt_th_init; + /*@-------------------------------------*/ + u32 phydm_sys_up_time; + u8 num_rf_path; /*@ex: 8821C=1, 8192E=2, 8814B=4*/ + u32 soft_ap_special_setting; + boolean boolean_dummy; + s8 s8_dummy; + u8 u8_dummy; + u16 u16_dummy; + u32 u32_dummy; + u8 rfe_hwsetting_band; + u8 p_advance_ota; + boolean hp_hw_id; + boolean BOOLEAN_temp; + boolean is_dfs_band; + u8 is_rx_blocking_en; + u16 fw_offload_ability; + boolean is_download_fw; + boolean en_dis_dpd; + u16 dis_dpd_rate; + u8 en_auto_bw_th; + boolean is_pause_dig; + #if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT) + u8 txagc_buff[RF_PATH_MEM_SIZE][PHY_NUM_RATE_IDX]; + u32 bp_0x9b0; + #elif (RTL8723F_SUPPORT) + u8 txagc_buff[2][PHY_NUM_RATE_IDX]; + u32 bp_0x9b0; + #endif + #if (RTL8822C_SUPPORT || RTL8723F_SUPPORT) + u8 ofdm_rxagc_l_bnd[16]; + boolean l_bnd_detect[16]; + u16 agc_rf_gain_ori[16][64];/*[table][mp_gain_idx]*/ + u16 agc_rf_gain[16][64];/*[table][mp_gain_idx]*/ + u8 agc_table_cnt; + boolean is_agc_tab_pos_shift; + u8 agc_table_shift; + #endif +/*@-----------HOOK BEFORE REG INIT-----------*/ +/*@===========================================================*/ +/*@====[ CALL BY Reference ]=========================================*/ +/*@===========================================================*/ + + u64 *num_tx_bytes_unicast; /*@TX Unicast byte cnt*/ + u64 *num_rx_bytes_unicast; /*@RX Unicast byte cnt*/ + u8 *band_type; /*@2.4G/5G = 0/1*/ + u8 *sec_ch_offset; /*@Secondary channel offset don't_care/below/above = 0/1/2*/ + u8 *security; /*@security mode Open/WEP/AES/TKIP = 0/1/2/3*/ + u8 *band_width; /*@20M/40M/80M = 0/1/2*/ + u8 *channel; /*@central CH number*/ + boolean *is_scan_in_process; + boolean *is_power_saving; + boolean *is_tdma; + u8 *one_path_cca; /*@CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/ + u8 *antenna_test; + boolean *is_net_closed; + boolean *is_fcs_mode_enable; /*@fast channel switch (= MCC mode)*/ + /*@--------- For 8723B IQK-------------------------------------*/ + boolean *is_1_antenna; + u8 *rf_default_path; /* @0:S1, 1:S0 */ + /*@-----------------------------------------------------------*/ + + u16 *forced_data_rate; + u8 *enable_antdiv; + u8 *enable_pathdiv; + u8 *en_adap_soml; + u8 *edcca_mode; + u8 *hub_usb_mode; /*@1:USB2.0, 2:USB3.0*/ + boolean *is_fw_dw_rsvd_page_in_progress; + u32 *current_tx_tp; + u32 *current_rx_tp; + u8 *sounding_seq; + u32 *soft_ap_mode; + u8 *mp_mode; + u32 *interrupt_mask; + u8 *bb_op_mode; + u32 *manual_supportability; + u8 *dis_dym_bw_indication; +/*@===========================================================*/ +/*@====[ CALL BY VALUE ]===========================================*/ +/*@===========================================================*/ + + u8 disable_phydm_watchdog; + boolean is_link_in_process; + boolean is_wifi_direct; + boolean is_wifi_display; + boolean is_linked; + boolean pre_is_linked; + boolean first_connect; + boolean first_disconnect; + boolean bsta_state; + u8 rssi_min; + u8 rssi_min_macid; + u8 pre_rssi_min; + u8 rssi_max; + u8 rssi_max_macid; + u8 rssi_min_by_path; + boolean is_mp_chip; + boolean is_one_entry_only; + u32 one_entry_macid; + u32 one_entry_tp; + u32 pre_one_entry_tp; + u8 pre_number_linked_client; + u8 number_linked_client; + u8 pre_number_active_client; + u8 number_active_client; + boolean is_disable_phy_api; + u8 rssi_a; + u8 rssi_b; + u8 rssi_c; + u8 rssi_d; + s8 rxsc_80; + s8 rxsc_40; + s8 rxsc_20; + s8 rxsc_l; + u64 rssi_trsw; + u64 rssi_trsw_h; + u64 rssi_trsw_l; + u64 rssi_trsw_iso; + u8 tx_ant_status; /*TX path enable*/ + u8 rx_ant_status; /*RX path enable*/ + #ifdef PHYDM_COMPILE_ABOVE_4SS + enum bb_path tx_4ss_status; /*@Use N-X for 4STS rate*/ + #endif + #ifdef PHYDM_COMPILE_ABOVE_3SS + enum bb_path tx_3ss_status; /*@Use N-X for 3STS rate*/ + #endif + #ifdef PHYDM_COMPILE_ABOVE_2SS + enum bb_path tx_2ss_status; /*@Use N-X for 2STS rate*/ + #endif + enum bb_path tx_1ss_status; /*@Use N-X for 1STS rate*/ + u8 cck_lna_idx; + u8 cck_vga_idx; + u8 curr_station_id; + u8 ofdm_agc_idx[4]; + u8 rx_rate; + u8 rate_ss; + u8 tx_rate; + u8 linked_interval; + u8 pre_channel; + u32 txagc_offset_value_a; + boolean is_txagc_offset_positive_a; + u32 txagc_offset_value_b; + boolean is_txagc_offset_positive_b; + u8 ap_total_num; + boolean flatness_type; + /*@[traffic]*/ + u8 traffic_load; + u8 pre_traffic_load; + u32 tx_tp; /*@Mbps*/ + u32 rx_tp; /*@Mbps*/ + u32 total_tp; /*@Mbps*/ + u8 txrx_state_all; /*@0:tx, 1:rx, 2:bi-dir*/ + u64 cur_tx_ok_cnt; + u64 cur_rx_ok_cnt; + u64 last_tx_ok_cnt; + u64 last_rx_ok_cnt; + u16 consecutive_idlel_time; /*@unit: second*/ + /*@---------------------------*/ + boolean is_bb_swing_offset_positive_a; + boolean is_bb_swing_offset_positive_b; + + /*@[DIG]*/ + boolean MPDIG_2G; /*off MPDIG*/ + u8 times_2g; /*@for MP DIG*/ + u8 force_igi; /*@for debug*/ + + /*@[TDMA-DIG]*/ + u8 tdma_dig_timer_ms; + u8 tdma_dig_state_number; + u8 tdma_dig_low_upper_bond; + u8 force_tdma_low_igi; + u8 force_tdma_high_igi; + u8 fix_expire_to_zero; + boolean original_dig_restore; + /*@---------------------------*/ + + /*@[AntDiv]*/ + u8 ant_div_type; + u8 antdiv_rssi; + u8 fat_comb_a; + u8 fat_comb_b; + u8 antdiv_intvl; + u8 antdiv_delay; + u8 ant_type; + u8 ant_type2; + u8 pre_ant_type; + u8 pre_ant_type2; + u8 antdiv_period; + u8 evm_antdiv_period; + u8 antdiv_select; + u8 antdiv_train_num; /*@training time for each antenna in EVM method*/ + u8 stop_antdiv_rssi_th; + u16 stop_antdiv_tp_diff_th; + u16 stop_antdiv_tp_th; + u8 antdiv_tp_period; + u16 tp_active_th; + u8 tp_active_occur; + u8 path_select; + u8 antdiv_evm_en; + u8 bdc_holdstate; + u8 antdiv_counter; + /*@---------------------------*/ + + u8 ndpa_period; + boolean h2c_rarpt_connect; + boolean cck_agc_report_type; /*@1:4bit LNA, 0:3bit LNA */ + u8 print_agc; + u8 la_mode; + /*@---8821C Antenna and RF Set BTG/WLG/WLA Select---------------*/ + u8 current_rf_set_8821c; + u8 default_rf_set_8821c; + u8 current_ant_num_8821c; + u8 default_ant_num_8821c; + u8 rfe_type_expand; + /*@-----------------------------------------------------------*/ + /*@---For Adaptivtiy---------------------------------------------*/ + s8 TH_L2H_default; + s8 th_edcca_hl_diff_default; + s8 th_l2h_ini; + s8 th_edcca_hl_diff; + boolean carrier_sense_enable; + /*@-----------------------------------------------------------*/ + u8 pre_dbg_priority; + u8 nbi_set_result; + u8 c2h_cmd_start; + u8 fw_debug_trace[60]; + u8 pre_c2h_seq; + boolean fw_buff_is_enpty; + u32 data_frame_num; + /*@--- for spur detection ---------------------------------------*/ + boolean en_reg_mntr_bb; + boolean en_reg_mntr_rf; + boolean en_reg_mntr_mac; + boolean en_reg_mntr_byte; + /*@--------------------------------------------------------------*/ +#if (RTL8814B_SUPPORT || RTL8812F_SUPPORT || RTL8198F_SUPPORT) + u8 dsde_sel; + u8 nbi_path_sel; + u8 csi_wgt; +#endif +#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT) + u8 csi_wgt_th_db[5]; /*@wgt 4,3,2,1,0 */ + /* ^ ^ ^ ^ ^ */ +#endif + /*@------------------------------------------*/ + + /*@--- for noise detection ---------------------------------------*/ + boolean is_noisy_state; + boolean noisy_decision; /*@b_noisy*/ + boolean pre_b_noisy; + u32 noisy_decision_smooth; + /*@-----------------------------------------------------------*/ + + /*@--- for MCC ant weighting ------------------------------------*/ + boolean is_stop_dym_ant_weighting; + /*@-----------------------------------------------------------*/ + + boolean is_disable_dym_ecs; + boolean is_disable_dym_ant_weighting; + struct cmn_sta_info *phydm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; + u8 phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];/*@sta_idx = phydm_macid_table[HW_macid]*/ + +#if (RATE_ADAPTIVE_SUPPORT) + u16 currmin_rpt_time; + struct _phydm_txstatistic_ hw_stats; + struct _odm_ra_info_ ra_info[ODM_ASSOCIATE_ENTRY_NUM]; +/*Use mac_id as array index. STA mac_id=0*/ +/*VWiFi Client mac_id={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119*/ +#endif + /*@2012/02/14 MH Add to share 88E ra with other SW team*/ + /*We need to colelct all support abilit to a proper area.*/ + boolean ra_support88e; + boolean *is_driver_stopped; + boolean *is_driver_is_going_to_pnp_set_power_sleep; + boolean *pinit_adpt_in_progress; + boolean is_user_assign_level; + u8 RSSI_BT; /*@come from BT*/ + + /*@---PSD Relative ---------------------------------------------*/ + boolean is_psd_in_process; + boolean is_psd_active; + /*@-----------------------------------------------------------*/ + + boolean bsomlenabled; /* @D-SoML control */ + u8 no_ndp_cnts; + u16 ndp_cnt_pre; + boolean is_beamformed; + u8 linked_bf_support; + boolean bhtstfdisabled; /* @dynamic HTSTF gain control*/ + u32 n_iqk_cnt; + u32 n_iqk_ok_cnt; + u32 n_iqk_fail_cnt; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + boolean config_bbrf; +#endif + boolean is_disable_power_training; + boolean is_bt_continuous_turn; + u8 enhance_pwr_th[3]; + u8 set_pwr_th[3]; + /*@----------Dyn Tx Pwr ---------------------------------------*/ +#ifdef BB_RAM_SUPPORT + struct phydm_bb_ram_ctrl p_bb_ram_ctrl; +#endif + u8 dynamic_tx_high_power_lvl; + void (*fill_desc_dyntxpwr)(void *dm, u8 *desc, u8 dyn_tx_power); + u8 last_dtp_lvl; + u8 min_power_index; + u32 tx_agc_ofdm_18_6; + /*-------------------------------------------------------------*/ + u8 rx_pkt_type; + +#ifdef CONFIG_PHYDM_DFS_MASTER + u8 dfs_region_domain; + u8 *dfs_master_enabled; + /*@---phydm_radar_detect_with_dbg_parm start --------------------*/ + u8 radar_detect_dbg_parm_en; + u32 radar_detect_reg_918; + u32 radar_detect_reg_91c; + u32 radar_detect_reg_920; + u32 radar_detect_reg_924; + + u32 radar_detect_reg_a40; + u32 radar_detect_reg_a44; + u32 radar_detect_reg_a48; + u32 radar_detect_reg_a4c; + u32 radar_detect_reg_a50; + u32 radar_detect_reg_a54; + + u32 radar_detect_reg_f54; + u32 radar_detect_reg_f58; + u32 radar_detect_reg_f5c; + u32 radar_detect_reg_f70; + u32 radar_detect_reg_f74; + /*@---For zero-wait DFS---------------------------------------*/ + boolean seg1_dfs_flag; + /*@-----------------------------------------------------------*/ +/*@-----------------------------------------------------------*/ +#endif + +/*@=== RTL8721D ===*/ +#if (RTL8721D_SUPPORT) + boolean cbw20_adc80; + boolean invalid_mode; + u8 power_voltage; + u8 cca_cbw20_lev; + u8 cca_cbw40_lev; + u8 antdiv_gpio; + u8 peak_detect_mode; +#endif + +/*@=== PHYDM Timer ========================================== (start)*/ + + struct phydm_timer_list mpt_dig_timer; + struct phydm_timer_list fast_ant_training_timer; +#ifdef ODM_EVM_ENHANCE_ANTDIV + struct phydm_timer_list evm_fast_ant_training_timer; +#endif +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_timer_list tdma_dig_timer; +#endif + struct phydm_timer_list sbdcnt_timer; + +/*@=== PHYDM Workitem ======================================= (start)*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM fast_ant_training_workitem; + RT_WORK_ITEM ra_rpt_workitem; + RT_WORK_ITEM sbdcnt_workitem; + RT_WORK_ITEM phydm_evm_antdiv_workitem; +#ifdef PHYDM_TDMA_DIG_SUPPORT + RT_WORK_ITEM phydm_tdma_dig_workitem; +#endif +#endif +#endif + +/*@=== PHYDM Structure ======================================== (start)*/ + struct phydm_func_poiner phydm_func_handler; + struct phydm_iot_center iot_table; + +#ifdef ODM_CONFIG_BT_COEXIST + struct phydm_bt_info bt_info_table; +#endif + + struct pkt_process_info pkt_proc_struct; + struct phydm_adaptivity_struct adaptivity; +#ifdef CONFIG_PHYDM_DFS_MASTER + struct _DFS_STATISTICS dfs; +#endif + struct odm_noise_monitor noise_level; + struct odm_phy_dbg_info phy_dbg_info; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct odm_phy_dbg_info phy_dbg_info_win_bkp; +#endif +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + struct phydm_bf_rate_info_jgr3 bf_rate_info_jgr3; +#endif + +#ifdef CONFIG_ADAPTIVE_SOML + struct adaptive_soml dm_soml_table; +#endif + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct _BF_DIV_COEX_ dm_bdc_table; + #endif + + #if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo dm_sat_table; + #endif +#endif + +#if (defined(CONFIG_SMART_ANTENNA)) + struct smt_ant smtant_table; +#endif + + struct _hal_rf_ rf_table; /*@for HALRF function*/ + struct dm_rf_calibration_struct rf_calibrate_info; + struct dm_iqk_info IQK_info; + struct dm_dpk_info dpk_info; + struct dm_dack_info dack_info; +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + struct phydm_fat_struct dm_fat_table; + struct sw_antenna_switch dm_swat_table; +#endif + struct phydm_dig_struct dm_dig_table; + +#ifdef PHYDM_SUPPORT_CCKPD + struct phydm_cckpd_struct dm_cckpd_table; + + #ifdef PHYDM_DCC_ENHANCE + struct phydm_dcc_struct dm_dcc_info; /*dig cckpd coex*/ + #endif +#endif + +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + struct phydm_lna_sat_t dm_lna_sat_info; +#endif + +#ifdef CONFIG_MCC_DM + struct _phydm_mcc_dm_ mcc_dm; +#endif + +#ifdef PHYDM_PRIMARY_CCA + struct phydm_pricca_struct dm_pri_cca; +#endif + + struct ra_table dm_ra_table; + struct phydm_fa_struct false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct false_alm_cnt_acc; +#ifdef IS_USE_NEW_TDMA + struct phydm_fa_acc_struct false_alm_cnt_acc_low; +#endif +#endif + struct phydm_cfo_track_struct dm_cfo_track; + struct ccx_info dm_ccx_info; + + struct odm_power_trim_data power_trim_data; +#if (RTL8822B_SUPPORT) + struct drp_rtl8822b_struct phydm_rtl8822b; +#endif + +#ifdef CONFIG_PSD_TOOL + struct psd_info dm_psd_table; +#endif + +#if (PHYDM_LA_MODE_SUPPORT) + struct rt_adcsmp adcsmp; +#endif + +#if (defined(CONFIG_PATH_DIVERSITY)) + struct _ODM_PATH_DIVERSITY_ dm_path_div; +#endif + +#if (defined(CONFIG_ANT_DETECTION)) + struct _ANT_DETECTED_INFO ant_detected_info; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#ifdef PHYDM_BEAMFORMING_SUPPORT + struct _RT_BEAMFORMING_INFO beamforming_info; +#endif +#endif +#ifdef PHYDM_AUTO_DEGBUG + struct phydm_auto_dbg_struct auto_dbg_table; +#endif + + struct phydm_pause_lv pause_lv_table; + struct phydm_api_stuc api_table; +#ifdef PHYDM_POWER_TRAINING_SUPPORT + struct phydm_pow_train_stuc pow_train_table; +#endif + +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT + struct phydm_pmac_tx dm_pmac_tx_table; +#endif + +#ifdef PHYDM_MP_SUPPORT + struct phydm_mp dm_mp_table; +#endif + +#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT + struct phydm_cck_rx_pathdiv dm_cck_rx_pathdiv_table; +#endif +/*@==========================================================*/ + +#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) + /*@-------------------phydm_phystatus report --------------------*/ + struct phydm_physts dm_physts_table; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if (RT_PLATFORM != PLATFORM_LINUX) +} dm_struct; /*@DM_Dynamic_Mechanism_Structure*/ +#else +}; +#endif + +#else /*@for AP,CE Team*/ +}; +#endif + +enum phydm_adv_ota { + PHYDM_PATHB_1RCCA = BIT(0), + PHYDM_HP_OTA_SETTING_A = BIT(1), + PHYDM_HP_OTA_SETTING_B = BIT(2), + PHYDM_ASUS_OTA_SETTING = BIT(3), + PHYDM_ASUS_OTA_SETTING_CCK_PATH = BIT(4), + PHYDM_HP_OTA_SETTING_CCK_PATH = BIT(5), + PHYDM_LENOVO_OTA_SETTING_NBI_CSI = BIT(6), + +}; + +enum phydm_bb_op_mode { + PHYDM_PERFORMANCE_MODE = 0, /*Service one device*/ + PHYDM_BALANCE_MODE = 1, /*@Service more than one device*/ +}; + +enum phydm_structure_type { + PHYDM_FALSEALMCNT, + PHYDM_CFOTRACK, + PHYDM_ADAPTIVITY, + PHYDM_DFS, + PHYDM_ROMINFO, + +}; + +enum odm_bb_config_type { + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, + CONFIG_BB_PHY_REG_MP, + CONFIG_BB_AGC_TAB_DIFF, + CONFIG_BB_RF_CAL_INIT, +}; + +enum odm_rf_config_type { + CONFIG_RF_RADIO, + CONFIG_RF_TXPWR_LMT, + CONFIG_RF_SYN_RADIO, +}; + +enum odm_fw_config_type { + CONFIG_FW_NIC, + CONFIG_FW_NIC_2, + CONFIG_FW_AP, + CONFIG_FW_AP_2, + CONFIG_FW_MP, + CONFIG_FW_WOWLAN, + CONFIG_FW_WOWLAN_2, + CONFIG_FW_AP_WOWLAN, + CONFIG_FW_BT, +}; + +/*status code*/ +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +enum rt_status { + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}; +#endif /*@end of enum rt_status definition*/ + +void +phydm_watchdog_lps(struct dm_struct *dm); + +void +phydm_watchdog_lps_32k(struct dm_struct *dm); + +void +phydm_txcurrentcalibration(struct dm_struct *dm); + +void +phydm_dm_early_init(struct dm_struct *dm); + +enum phydm_init_result +odm_dm_init(struct dm_struct *dm); + +void +odm_dm_reset(struct dm_struct *dm); + +void +phydm_fwoffload_ability_init(struct dm_struct *dm, + enum phydm_offload_ability offload_ability); + +void +phydm_fwoffload_ability_clear(struct dm_struct *dm, + enum phydm_offload_ability offload_ability); + +void +phydm_supportability_en(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void +phydm_pause_dm_watchdog(void *dm_void, enum phydm_pause_type pause_type); + +void +phydm_watchdog(struct dm_struct *dm); + +void +phydm_watchdog_mp(struct dm_struct *dm); + +void +phydm_pause_func_init(void *dm_void); + +u8 +phydm_pause_func(void *dm_void, enum phydm_func_idx pause_func, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_lv, u8 val_lehgth, u32 *val_buf); + +void +phydm_pause_func_console(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_pause_dm_by_asso_pkt(struct dm_struct *dm, + enum phydm_pause_type pause_type, u8 rssi); + +void phydm_fw_dm_ctrl_en(void *dm_void, enum phydm_func_idx fun_idx, + boolean enable); + +void +odm_cmn_info_init(struct dm_struct *dm, enum odm_cmninfo cmn_info, u64 value); + +void +odm_cmn_info_hook(struct dm_struct *dm, enum odm_cmninfo cmn_info, void *value); + +void +odm_cmn_info_update(struct dm_struct *dm, u32 cmn_info, u64 value); + +u32 +phydm_cmn_info_query(struct dm_struct *dm, enum phydm_info_query info_type); + +void +odm_init_all_timers(struct dm_struct *dm); + +void +odm_cancel_all_timers(struct dm_struct *dm); + +void +odm_release_all_timers(struct dm_struct *dm); + +void * +phydm_get_structure(struct dm_struct *dm, u8 structure_type); + +void +phydm_dc_cancellation(struct dm_struct *dm); + +void +phydm_receiver_blocking(void *dm_void); + +void +phydm_dyn_bw_indication(void *dm_void); + +void +phydm_iot_patch_id_update(void *dm_void, u32 iot_idx, boolean en); + + +#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH +void +phydm_tx_collsion_th_init(void *dm_void); + +void +phydm_tx_collsion_th_set(void *dm_void, u8 val_r2t, u8 val_t2r); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void +odm_init_all_work_items( + struct dm_struct *dm +); +void +odm_free_all_work_items( + struct dm_struct *dm +); +#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +void +odm_dtc(struct dm_struct *dm); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void +odm_init_all_threads( + struct dm_struct *dm +); + +void +odm_stop_all_threads( + struct dm_struct *dm +); +#endif + +#endif diff --git a/hal/phydm/phydm.mk b/hal/phydm/phydm.mk new file mode 100644 index 0000000..c5d0ce9 --- /dev/null +++ b/hal/phydm/phydm.mk @@ -0,0 +1,249 @@ +EXTRA_CFLAGS += -I$(src)/hal/phydm + +_PHYDM_FILES := hal/phydm/phydm_debug.o \ + hal/phydm/phydm_antdiv.o\ + hal/phydm/phydm_soml.o\ + hal/phydm/phydm_smt_ant.o\ + hal/phydm/phydm_antdect.o\ + hal/phydm/phydm_interface.o\ + hal/phydm/phydm_phystatus.o\ + hal/phydm/phydm_hwconfig.o\ + hal/phydm/phydm.o\ + hal/phydm/phydm_dig.o\ + hal/phydm/phydm_pathdiv.o\ + hal/phydm/phydm_rainfo.o\ + hal/phydm/phydm_dynamictxpower.o\ + hal/phydm/phydm_adaptivity.o\ + hal/phydm/phydm_cfotracking.o\ + hal/phydm/phydm_noisemonitor.o\ + hal/phydm/phydm_beamforming.o\ + hal/phydm/phydm_direct_bf.o\ + hal/phydm/phydm_dfs.o\ + hal/phydm/txbf/halcomtxbf.o\ + hal/phydm/txbf/haltxbfinterface.o\ + hal/phydm/txbf/phydm_hal_txbf_api.o\ + hal/phydm/phydm_adc_sampling.o\ + hal/phydm/phydm_ccx.o\ + hal/phydm/phydm_psd.o\ + hal/phydm/phydm_primary_cca.o\ + hal/phydm/phydm_cck_pd.o\ + hal/phydm/phydm_rssi_monitor.o\ + hal/phydm/phydm_auto_dbg.o\ + hal/phydm/phydm_math_lib.o\ + hal/phydm/phydm_api.o\ + hal/phydm/phydm_pow_train.o\ + hal/phydm/phydm_lna_sat.o\ + hal/phydm/phydm_pmac_tx_setting.o\ + hal/phydm/phydm_mp.o\ + hal/phydm/phydm_cck_rx_pathdiv.o\ + hal/phydm/halrf/halrf.o\ + hal/phydm/halrf/halrf_debug.o\ + hal/phydm/halrf/halphyrf_ce.o\ + hal/phydm/halrf/halrf_powertracking_ce.o\ + hal/phydm/halrf/halrf_powertracking.o\ + hal/phydm/halrf/halrf_kfree.o\ + hal/phydm/halrf/halrf_psd.o + +ifeq ($(CONFIG_RTL8188E), y) +RTL871X = rtl8188e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\ + hal/phydm/$(RTL871X)/hal8188erateadaptive.o\ + hal/phydm/$(RTL871X)/phydm_rtl8188e.o +endif + +ifeq ($(CONFIG_RTL8192E), y) +RTL871X = rtl8192e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192e.o +endif + + +ifeq ($(CONFIG_RTL8812A), y) +RTL871X = rtl8812a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\ + hal/phydm/$(RTL871X)/phydm_rtl8812a.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + +ifeq ($(CONFIG_RTL8821A), y) +RTL871X = rtl8821a +_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\ + hal/phydm/rtl8821a/halhwimg8821a_bb.o\ + hal/phydm/rtl8821a/halhwimg8821a_rf.o\ + hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\ + hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\ + hal/phydm/rtl8821a/phydm_regconfig8821a.o\ + hal/phydm/rtl8821a/phydm_rtl8821a.o\ + hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + + +ifeq ($(CONFIG_RTL8723B), y) +RTL871X = rtl8723b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723b.o +endif + + +ifeq ($(CONFIG_RTL8814A), y) +RTL871X = rtl8814a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8814a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8814a.o\ + hal/phydm/txbf/haltxbf8814a.o +endif + + +ifeq ($(CONFIG_RTL8723C), y) +RTL871X = rtl8703b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8703b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8703b.o +endif + +ifeq ($(CONFIG_RTL8723D), y) +RTL871X = rtl8723d +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723d.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723d.o +endif + + +ifeq ($(CONFIG_RTL8710B), y) +RTL871X = rtl8710b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8710b.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8710b_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8710b.o +endif + + +ifeq ($(CONFIG_RTL8188F), y) +RTL871X = rtl8188f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \ + hal/phydm/$(RTL871X)/phydm_rtl8188f.o +endif + +ifeq ($(CONFIG_RTL8822B), y) +RTL871X = rtl8822b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \ + hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \ + hal/phydm/halrf/$(RTL871X)/halhwimg8822b_rf.o \ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \ + hal/phydm/$(RTL871X)/phydm_rtl8822b.o + +_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o +endif + + +ifeq ($(CONFIG_RTL8821C), y) +RTL871X = rtl8821c +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\ + hal/phydm/$(RTL871X)/phydm_rtl8821c.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8821c_rf.o \ + hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o +endif +ifeq ($(CONFIG_RTL8192F), y) +RTL871X = rtl8192f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192f.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8192f_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192f.o +endif + +ifeq ($(CONFIG_RTL8198F), y) +RTL871X = rtl8198f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8198f.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8198f_rf.o +endif + +ifeq ($(CONFIG_RTL8822C), y) +RTL871X = rtl8822c +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\ + hal/phydm/$(RTL871X)/phydm_rtl8822c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8822c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8822c_rf.o +endif + +ifeq ($(CONFIG_RTL8814B), y) +RTL871X = rtl8814b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\ + hal/phydm/$(RTL871X)/phydm_extraagc8814b.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8814b_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_dpk_8814b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8814b.o +endif +ifeq ($(CONFIG_RTL8723F), y) +RTL871X = rtl8723f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723f_bb.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8723f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723f.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8723f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_tssi_8723f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_dpk_8723f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8723f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8723f.o\ + hal/phydm/halrf/$(RTL871X)/halhwimg8723f_rf.o +endif \ No newline at end of file diff --git a/hal/phydm/phydm_adaptivity.c b/hal/phydm/phydm_adaptivity.c new file mode 100644 index 0000000..34622f9 --- /dev/null +++ b/hal/phydm/phydm_adaptivity.c @@ -0,0 +1,845 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if WPP_SOFTWARE_TRACE + #include "PhyDM_Adaptivity.tmh" + #endif +#endif +#ifdef PHYDM_SUPPORT_ADAPTIVITY +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +boolean +phydm_check_channel_plan(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + + if (mgnt_info->RegEnableAdaptivity != 2) + return false; + + if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/ + if ((*dm->band_type == ODM_BAND_5G) && + !(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "adaptivity skip 5G domain code : %d\n", + adapt->regulation_5g); + return true; + } else if ((*dm->band_type == ODM_BAND_2_4G) && + !(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "adaptivity skip 2.4G domain code : %d\n", + adapt->regulation_2g); + return true; + } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "adaptivity neither 2G nor 5G band, return\n"); + return true; + } + } else { + if ((*dm->band_type == ODM_BAND_5G) && + !(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "CarrierSense skip 5G domain code : %d\n", + adapt->regulation_5g); + return true; + } else if ((*dm->band_type == ODM_BAND_2_4G) && + !(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "CarrierSense skip 2.4G domain code : %d\n", + adapt->regulation_2g); + return true; + } else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) { + PHYDM_DBG(dm, DBG_ADPTVTY, + "CarrierSense neither 2G nor 5G band, return\n"); + return true; + } + } + + return false; +} + +boolean +phydm_soft_ap_special_set(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + boolean disable_ap_adapt_setting = false; + + if (dm->soft_ap_mode != NULL) { + if (*dm->soft_ap_mode != 0 && + (dm->soft_ap_special_setting & BIT(0))) + disable_ap_adapt_setting = true; + else + disable_ap_adapt_setting = false; + PHYDM_DBG(dm, DBG_ADPTVTY, + "soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n", + dm->soft_ap_special_setting, *dm->soft_ap_mode, + disable_ap_adapt_setting); + } + + return disable_ap_adapt_setting; +} + +boolean +phydm_ap_num_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + boolean dis_adapt = false; + + if (dm->ap_total_num > adapt->ap_num_th) + dis_adapt = true; + else + dis_adapt = false; + + PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num = %d, AP num threshold = %d\n", + dm->ap_total_num, adapt->ap_num_th); + return dis_adapt; +} + +void phydm_check_adaptivity(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + boolean disable_adapt = false; + + if (!adapt->mode_cvrt_en) + return; + + if (phydm_check_channel_plan(dm) || phydm_ap_num_check(dm) || + phydm_soft_ap_special_set(dm)) + disable_adapt = true; + + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && disable_adapt) + *dm->edcca_mode = PHYDM_EDCCA_NORMAL_MODE; + else if (*dm->edcca_mode == PHYDM_EDCCA_NORMAL_MODE && !disable_adapt) + *dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE; +} + +void phydm_set_l2h_th_ini_win(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F)) + dm->th_l2h_ini = 45; + else if (dm->support_ic_type & ODM_RTL8814B) + dm->th_l2h_ini = 49; + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/ + if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) { + dm->th_l2h_ini = -17; + } else { + if (*dm->band_type == ODM_BAND_5G) + dm->th_l2h_ini = -14; + else if (*dm->band_type == ODM_BAND_2_4G) + dm->th_l2h_ini = -9; + } + } else { /*ODM_IC_11N_SERIES*/ + dm->th_l2h_ini = -9; + } +} +#endif + +void phydm_dig_up_bound_lmt_en(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + + if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE || + !dm->is_linked) { + adapt->igi_up_bound_lmt_cnt = 0; + adapt->igi_lmt_en = false; + return; + } + + if (dm->total_tp > 1) { + adapt->igi_lmt_en = true; + adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val; + PHYDM_DBG(dm, DBG_ADPTVTY, + "TP >1, Start limit IGI upper bound\n"); + } else { + if (adapt->igi_up_bound_lmt_cnt == 0) + adapt->igi_lmt_en = false; + else + adapt->igi_up_bound_lmt_cnt--; + } + + PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n", + adapt->igi_up_bound_lmt_cnt); +} + +void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 0x80); + odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 0x80); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H); + odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H); + odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L); + } +} + +void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (state == PHYDM_IGNORE_EDCCA) { + /*@ignore EDCCA*/ + odm_set_mac_reg(dm, R_0x520, BIT(15), 1); + /*@enable EDCCA count down*/ + odm_set_mac_reg(dm, R_0x524, BIT(11), 0); + } else { /*@don't set MAC ignore EDCCA signal*/ + /*@don't ignore EDCCA*/ + odm_set_mac_reg(dm, R_0x520, BIT(15), 0); + /*@disable EDCCA count down*/ + odm_set_mac_reg(dm, R_0x524, BIT(11), 1); + } + PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state); +} + +void phydm_search_pwdb_lower_bound(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + u32 value32 = 0, reg_value32 = 0; + u8 cnt = 0, try_count = 0; + u8 tx_edcca1 = 0; + boolean is_adjust = true; + s8 th_l2h, th_h2l, igi_target_dc = 0x32; + s8 diff = 0; + s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff; + + halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE); + diff = igi_target_dc - IGI; + th_l2h = dm->th_l2h_ini + diff; + if (th_l2h > 10) + th_l2h = 10; + + th_h2l = th_l2h - dm->th_edcca_hl_diff; + phydm_set_edcca_threshold(dm, th_h2l, th_l2h); + ODM_delay_ms(30); + + while (is_adjust) { + /*@check CCA status*/ + /*set debug port to 0x0*/ + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) { + reg_value32 = phydm_get_bb_dbg_port_val(dm); + + while (reg_value32 & BIT(3) && try_count < 3) { + ODM_delay_ms(3); + try_count = try_count + 1; + reg_value32 = phydm_get_bb_dbg_port_val(dm); + } + phydm_release_bb_dbg_port(dm); + try_count = 0; + } + + /*@count EDCCA signal = 1 times*/ + for (cnt = 0; cnt < 20; cnt++) { + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, + adapt->adaptivity_dbg_port)) { + value32 = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } + + if (value32 & BIT(30) && dm->support_ic_type & + (ODM_RTL8723B | ODM_RTL8188E)) + tx_edcca1 = tx_edcca1 + 1; + else if (value32 & BIT(29)) + tx_edcca1 = tx_edcca1 + 1; + } + + if (tx_edcca1 > 1) { + IGI = IGI - 1; + th_l2h = th_l2h + 1; + if (th_l2h > 10) + th_l2h = 10; + + th_h2l = th_l2h - dm->th_edcca_hl_diff; + phydm_set_edcca_threshold(dm, th_h2l, th_l2h); + tx_edcca1 = 0; + if (th_l2h == 10) + is_adjust = false; + + } else { + is_adjust = false; + } + } + + adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF; + adapt->h2l_lb = th_h2l + ADAPT_DC_BACKOFF; + adapt->l2h_lb = th_l2h + ADAPT_DC_BACKOFF; + + halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE); + phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/ +} + +boolean phydm_re_search_condition(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF; + + if (adaptivity_igi_upper <= 0x26) + return true; + else + return false; +} + +void phydm_set_l2h_th_ini(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F)) + dm->th_l2h_ini = 45; + else if (dm->support_ic_type & ODM_RTL8814B) + dm->th_l2h_ini = 49; + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/ + if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) + dm->th_l2h_ini = -17; + else + dm->th_l2h_ini = -14; + } else { /*ODM_IC_11N_SERIES*/ + if (dm->support_ic_type & ODM_RTL8721D) + dm->th_l2h_ini = -14; + else + dm->th_l2h_ini = -11; + } +} + +void phydm_set_l2h_th_ini_carrier_sense(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + dm->th_l2h_ini = 60; /*@ -50dBm*/ + else + dm->th_l2h_ini = 10; /*@ -50dBm*/ +} + +void phydm_set_forgetting_factor(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE) + return; + + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A | + ODM_RTL8195B)) + odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0); +} + +void phydm_edcca_decision_opt(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE) + return; + + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1); + else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1); + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0); +} + +void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + u32 used = *_used; + u32 out_len = *_out_len; + char help[] = "-h"; + u32 dm_value[10] = {0}; + u8 i = 0, input_idx = 0; + u32 reg_value32 = 0; + s8 h2l_diff = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Show adaptivity message: {0}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Leave debug mode: {2}\n"); + goto out; + } + + if (input_idx == 0) + return; + + if (dm_value[0] == PHYDM_ADAPT_DEBUG) { + adaptivity->debug_mode = true; + if (dm_value[1] != 0) + dm->th_l2h_ini = (s8)dm_value[1]; + if (dm_value[2] != 0) + dm->th_edcca_hl_diff = (s8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "th_l2h_ini = %d, th_edcca_hl_diff = %d\n", + dm->th_l2h_ini, dm->th_edcca_hl_diff); + } else if (dm_value[0] == PHYDM_ADAPT_RESUME) { + adaptivity->debug_mode = false; + dm->th_l2h_ini = adaptivity->th_l2h_ini_backup; + dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; + } else if (dm_value[0] == PHYDM_ADAPT_MSG) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "debug_mode = %s, th_l2h_ini = %d\n", + (adaptivity->debug_mode ? "TRUE" : "FALSE"), + dm->th_l2h_ini); + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD); + h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) - + (s8)((0xff000000 & reg_value32) >> 24); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD); + h2l_diff = (s8)(0x000000ff & reg_value32) - + (s8)((0x00ff0000 & reg_value32) >> 16); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD); + h2l_diff = (s8)(0x000000ff & reg_value32) - + (s8)((0x0000ff00 & reg_value32) >> 8); + } + + if (h2l_diff == 7) + PDM_SNPF(out_len, used, output + used, out_len - used, + "adaptivity enable\n"); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "adaptivity disable\n"); + } + +out: + *_used = used; + *_out_len = out_len; +} + +void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (val_len != 2) { + PHYDM_DBG(dm, ODM_COMP_API, + "[Error][adaptivity]Need val_len = 2\n"); + return; + } + phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]); +} + +boolean phydm_edcca_abort(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + u32 is_fw_in_psmode = false; +#endif + + if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) { + PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable\n"); + return true; + } + + if (dm->pause_ability & ODM_BB_ADAPTIVITY) { + PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n", + dm->pause_lv_table.lv_adapt); + return true; + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter, + HW_VAR_FW_PSMODE_STATUS, + (u8 *)(&is_fw_in_psmode)); + + /*@Disable EDCCA while under LPS mode, added by Roger, 2012.09.14.*/ + if (is_fw_in_psmode) + return true; +#endif + + return false; +} + +void phydm_edcca_thre_calc_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + u8 igi = dig_t->cur_ig_value; + s8 th_l2h = 0, th_h2l = 0; + + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) { + /*prevent pwdB clipping and result in Miss Detection*/ + adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini - ADC_BACKOFF); + + if (igi < adapt->l2h_dyn_min) + th_l2h = igi + ADC_BACKOFF; + else + th_l2h = dm->th_l2h_ini; + + th_h2l = th_l2h - dm->th_edcca_hl_diff; + } else { + th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB); + th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL; + } + adapt->th_l2h = th_l2h; + adapt->th_h2l = th_h2l; + + phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h); +} + +void phydm_edcca_thre_calc(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + u8 igi = dig_t->cur_ig_value; + s8 th_l2h = 0, th_h2l = 0; + s8 diff = 0, igi_target = adapt->igi_base; + + if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) { + /*@fix EDCCA hang issue*/ + if (dm->support_ic_type & ODM_RTL8812) { + /*@ADC_mask disable*/ + odm_set_bb_reg(dm, R_0x800, BIT(10), 1); + /*@ADC_mask enable*/ + odm_set_bb_reg(dm, R_0x800, BIT(10), 0); + } + + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) { + /*@Limit IGI upper bound for adaptivity*/ + phydm_dig_up_bound_lmt_en(dm); + diff = igi_target - (s8)igi; + th_l2h = dm->th_l2h_ini + diff; + if (th_l2h > 10) + th_l2h = 10; + + th_h2l = th_l2h - dm->th_edcca_hl_diff; + } else { + th_l2h = 70 - igi; + th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL; + } + /*replace lower bound to prevent EDCCA always equal 1*/ + if (th_h2l < adapt->h2l_lb) + th_h2l = adapt->h2l_lb; + if (th_l2h < adapt->l2h_lb) + th_l2h = adapt->l2h_lb; + PHYDM_DBG(dm, DBG_ADPTVTY, + "adapt_igi_up=0x%x, l2h_lb = %d dBm, h2l_lb = %d dBm\n", + adapt->adapt_igi_up, + IGI_2_DBM(adapt->l2h_lb + adapt->adapt_igi_up), + IGI_2_DBM(adapt->h2l_lb + adapt->adapt_igi_up)); + } else { /* < JGR2 & N*/ + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) { + /*need to consider PwdB upper bound for 8814 later IC*/ + adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini + igi_target); + + if (igi < adapt->l2h_dyn_min) + th_l2h = igi; + else + th_l2h = adapt->l2h_dyn_min; + + th_h2l = th_l2h - dm->th_edcca_hl_diff; + } else { + th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB); + th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL; + } + } + + adapt->th_l2h = th_l2h; + adapt->th_h2l = th_h2l; + + phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h); +} +#endif + +void phydm_set_edcca_threshold_api(void *dm_void) +{ +#ifdef PHYDM_SUPPORT_ADAPTIVITY + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + + if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE) + return; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_edcca_thre_calc_jgr3(dm); + else + phydm_edcca_thre_calc(dm); + + PHYDM_DBG(dm, DBG_ADPTVTY, + "API :IGI = 0x%x, th_l2h = %d, th_h2l = %d\n", + dm->dm_dig_table.cur_ig_value, adapt->th_l2h, adapt->th_h2l); +#endif +} + +void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + + switch (cmn_info) { + case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE: + dm->carrier_sense_enable = (boolean)value; + break; + case PHYDM_ADAPINFO_TH_L2H_INI: + dm->th_l2h_ini = (s8)value; + break; + case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF: + dm->th_edcca_hl_diff = (s8)value; + break; + case PHYDM_ADAPINFO_AP_NUM_TH: + adaptivity->ap_num_th = (u8)value; + break; + case PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND: + adaptivity->switch_th_l2h_ini_in_band = (u8)value; + break; + default: + break; + } +} + +void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + + /*This init variable may be changed in run time.*/ + switch (cmn_info) { + case PHYDM_ADAPINFO_DOMAIN_CODE_2G: + adapt->regulation_2g = (u8)value; + break; + case PHYDM_ADAPINFO_DOMAIN_CODE_5G: + adapt->regulation_5g = (u8)value; + break; + default: + break; + } +} + +void phydm_adaptivity_init(void *dm_void) +{ +#ifdef PHYDM_SUPPORT_ADAPTIVITY + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + + /* @[Config Adaptivity]*/ + if (!dm->edcca_mode) { + pr_debug("[%s] warning!\n", __func__); + dm->edcca_mode = &dm->u8_dummy; + dm->support_ability &= ~ODM_BB_ADAPTIVITY; + return; + } + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (!dm->carrier_sense_enable) { + if (dm->th_l2h_ini == 0 && + !adaptivity->switch_th_l2h_ini_in_band) + phydm_set_l2h_th_ini(dm); + } else { + phydm_set_l2h_th_ini_carrier_sense(dm); + } + + if (dm->th_edcca_hl_diff == 0) + dm->th_edcca_hl_diff = 7; + + if (dm->wifi_test & RT_WIFI_LOGO) + dm->support_ability &= ~ODM_BB_ADAPTIVITY; + + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) + adaptivity->mode_cvrt_en = true; + else + adaptivity->mode_cvrt_en = false; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (!dm->carrier_sense_enable) { + if (dm->th_l2h_ini == 0) + phydm_set_l2h_th_ini(dm); + } else { + phydm_set_l2h_th_ini_carrier_sense(dm); + } + + if (dm->th_edcca_hl_diff == 0) + dm->th_edcca_hl_diff = 7; + + if (dm->wifi_test || *dm->mp_mode) + dm->support_ability &= ~ODM_BB_ADAPTIVITY; +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + if (dm->carrier_sense_enable) { + phydm_set_l2h_th_ini_carrier_sense(dm); + dm->th_edcca_hl_diff = 7; + } else { + dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/ + dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default; + } +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + if (!dm->carrier_sense_enable) { + if (dm->th_l2h_ini == 0) + phydm_set_l2h_th_ini(dm); + } else { + phydm_set_l2h_th_ini_carrier_sense(dm); + } + + if (dm->th_edcca_hl_diff == 0) + dm->th_edcca_hl_diff = 7; +#endif + + adaptivity->debug_mode = false; + adaptivity->th_l2h_ini_backup = dm->th_l2h_ini; + adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff; + adaptivity->igi_base = 0x32; + adaptivity->adapt_igi_up = 0; + adaptivity->h2l_lb = 0; + adaptivity->l2h_lb = 0; + adaptivity->l2h_dyn_min = 0; + adaptivity->th_l2h = 0x7f; + adaptivity->th_h2l = 0x7f; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) + adaptivity->adaptivity_dbg_port = 0x208; + else if (dm->support_ic_type & ODM_IC_11AC_SERIES) + adaptivity->adaptivity_dbg_port = 0x209; + + if (dm->support_ic_type & ODM_IC_11N_SERIES && + !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) { + /*set to page B1*/ + odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1); + /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1); + odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0); + } else { + /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1); + } + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES && + !(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + /*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1); + } + + if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) { + phydm_search_pwdb_lower_bound(dm); + if (phydm_re_search_condition(dm)) + phydm_search_pwdb_lower_bound(dm); + } else { + /*resume to no link state*/ + phydm_set_edcca_threshold(dm, 0x7f, 0x7f); + } + + /*@whether to ignore EDCCA*/ + phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA); + + /*@forgetting factor setting*/ + phydm_set_forgetting_factor(dm); + + /*@EDCCA behavior based on maximum or mean power*/ + phydm_edcca_decision_opt(dm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + adaptivity->igi_up_bound_lmt_val = 180; +#else + adaptivity->igi_up_bound_lmt_val = 90; +#endif + adaptivity->igi_up_bound_lmt_cnt = 0; + adaptivity->igi_lmt_en = false; +#endif +} + +void phydm_adaptivity(void *dm_void) +{ +#ifdef PHYDM_SUPPORT_ADAPTIVITY + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (phydm_edcca_abort(dm)) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + phydm_check_adaptivity(dm); /*@Check adaptivity enable*/ + + if (!dm->carrier_sense_enable && + !adapt->debug_mode && + adapt->switch_th_l2h_ini_in_band) + phydm_set_l2h_th_ini_win(dm); +#endif + + PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__); + PHYDM_DBG(dm, DBG_ADPTVTY, "mode = %s, debug_mode = %d\n", + (*dm->edcca_mode ? + (dm->carrier_sense_enable ? + "CARRIER SENSE" : + "ADAPTIVITY") : + "NORMAL"), + adapt->debug_mode); + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_edcca_thre_calc_jgr3(dm); + else + phydm_edcca_thre_calc(dm); + + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) + PHYDM_DBG(dm, DBG_ADPTVTY, + "th_l2h_ini = %d, th_edcca_hl_diff = %d\n", + dm->th_l2h_ini, dm->th_edcca_hl_diff); + if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) + PHYDM_DBG(dm, DBG_ADPTVTY, + "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n", + dig_t->cur_ig_value, + IGI_2_DBM(adapt->th_l2h + dig_t->cur_ig_value), + IGI_2_DBM(adapt->th_h2l + dig_t->cur_ig_value)); + else + PHYDM_DBG(dm, DBG_ADPTVTY, + "IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n", + dig_t->cur_ig_value, + IGI_2_DBM(adapt->th_l2h), + IGI_2_DBM(adapt->th_h2l)); +#endif +} + diff --git a/hal/phydm/phydm_adaptivity.h b/hal/phydm/phydm_adaptivity.h new file mode 100644 index 0000000..f125fb1 --- /dev/null +++ b/hal/phydm/phydm_adaptivity.h @@ -0,0 +1,126 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMADAPTIVITY_H__ +#define __PHYDMADAPTIVITY_H__ + +#define ADAPTIVITY_VERSION "9.7.07" /*@20190321 changed by Kevin, + *add 8721D threshold l2h init + */ +#define ADC_BACKOFF 12 +#define EDCCA_TH_L2H_LB 48 +#define TH_L2H_DIFF_IGI 8 +#define EDCCA_HL_DIFF_NORMAL 8 +#define IGI_2_DBM(igi) (igi - 110) +/*@ [PHYDM-337][Old IC] EDCCA TH = IGI + REG setting*/ +#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\ + ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812) + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) + #define ADAPT_DC_BACKOFF 2 +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #define ADAPT_DC_BACKOFF 4 +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + #define ADAPT_DC_BACKOFF 0 +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +enum phydm_regulation_type { + REGULATION_FCC = 0, + REGULATION_MKK = 1, + REGULATION_ETSI = 2, + REGULATION_WW = 3, + MAX_REGULATION_NUM = 4 +}; +#endif + +enum phydm_edcca_mode { + PHYDM_EDCCA_NORMAL_MODE = 0, + PHYDM_EDCCA_ADAPT_MODE = 1 +}; + +enum phydm_adapinfo { + PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, + PHYDM_ADAPINFO_TH_L2H_INI, + PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, + PHYDM_ADAPINFO_AP_NUM_TH, + PHYDM_ADAPINFO_DOMAIN_CODE_2G, + PHYDM_ADAPINFO_DOMAIN_CODE_5G, + PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND +}; + +enum phydm_mac_edcca_type { + PHYDM_IGNORE_EDCCA = 0, + PHYDM_DONT_IGNORE_EDCCA = 1 +}; + +enum phydm_adaptivity_debug_mode { + PHYDM_ADAPT_MSG = 0, + PHYDM_ADAPT_DEBUG = 1, + PHYDM_ADAPT_RESUME = 2, +}; + +struct phydm_adaptivity_struct { + boolean mode_cvrt_en; + s8 th_l2h_ini_backup; + s8 th_edcca_hl_diff_backup; + s8 igi_base; + s8 h2l_lb; + s8 l2h_lb; + u8 ap_num_th; + u8 l2h_dyn_min; + u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/ + u8 debug_mode; + u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/ + u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/ + boolean igi_lmt_en; + u8 adapt_igi_up; + u32 rvrt_val[2]; /*@all rvrt_val for pause API must set to u32*/ + s8 th_l2h; + s8 th_h2l; + u8 regulation_2g; + u8 regulation_5g; + u8 switch_th_l2h_ini_in_band; +}; + +#ifdef PHYDM_SUPPORT_ADAPTIVITY +void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len); +#endif + +void phydm_set_edcca_threshold_api(void *dm_void); + +void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value); + +void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info, + u32 value); + +void phydm_adaptivity_init(void *dm_void); + +void phydm_adaptivity(void *dm_void); + +#endif diff --git a/hal/phydm/phydm_adc_sampling.c b/hal/phydm/phydm_adc_sampling.c new file mode 100644 index 0000000..ace8a9d --- /dev/null +++ b/hal/phydm/phydm_adc_sampling.c @@ -0,0 +1,1787 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (PHYDM_LA_MODE_SUPPORT) + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + #if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #include "rtl8197f/Hal8197FPhyReg.h" + #include "WlanHAL/HalMac88XX/halmac_reg2.h" + #else + #include "WlanHAL/HalHeader/HalComReg.h" + #endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if WPP_SOFTWARE_TRACE + #include "phydm_adc_sampling.tmh" + #endif +#endif + +#if RTL8814B_SUPPORT +boolean phydm_la_finish_addr_recover_8814B(void *dm_void, u32 *finish_addr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + boolean recover_success; + + if (dm->support_ic_type != ODM_RTL8814B) + return false; + + if (smp->la_buff_mode == ADCSMP_BUFF_HALF) { + if (*finish_addr < 0x4000) /*0~0x4000*/ + *finish_addr += 0x8000; + + recover_success = true; + } else { + if (*finish_addr >= 0x4000 && *finish_addr < 0x8000) + recover_success = true; + else + recover_success = false; + } + pr_debug("[8814B] recover_success=(%d)\n", recover_success); + + return recover_success; +} +#endif + +#if RTL8198F_SUPPORT +void phydm_la_pre_run(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + u8 i = 0; + u8 tmp = 0; + u8 target_polling_bit = BIT(1); + + if (!(dm->support_ic_type & ODM_RTL8198F)) + return; + + if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) + return; + + /*pre run */ + /*force to bb trigger*/ + odm_set_mac_reg(dm, R_0x7c0, BIT(3), 0); + /*dma_trig_and(AND1) output 1*/ + odm_set_bb_reg(dm, R_0x1ce4, 0xf0000000, 0x0); + /*r_dma_trigger_AND1_inv = 1*/ + odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ + /* polling bit for BB ADC mode */ + odm_set_mac_reg(dm, R_0x7c0, BIT(1), 1); + + pr_debug("buf[end:start]=(0x%x~0x%x)\n", buf->end_pos, buf->start_pos); + + do { + tmp = odm_read_1byte(dm, R_0x7c0); + if ((tmp & target_polling_bit) == false) { + pr_debug("LA pre-run fail.\n"); + phydm_la_stop(dm); + phydm_release_bb_dbg_port(dm); + } else { + ODM_delay_ms(100); + pr_debug("LA pre-run while_cnt = %d.\n", i); + i++; + } + } while (i < 3); + + /*r_dma_trigger_AND1_inv = 0*/ + odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ + + if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) + odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1); +} +#endif + +#if (RTL8821C_SUPPORT || RTL8195B_SUPPORT) +void +phydm_la_clk_en(void *dm_void, boolean enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 val = (enable) ? 1 : 0; + + if (!(dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C))) + return; + + if (dm->support_ic_type == ODM_RTL8821C && + dm->cut_version == ODM_CUT_A) + return; + + odm_set_bb_reg(dm, R_0x95c, BIT(23), val); +} +#endif + +#if (RTL8723F_SUPPORT) +void +phydm_la_mac_clk_en(void *dm_void, boolean enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 val = (enable) ? 1 : 0; + + if (!(dm->support_ic_type & ODM_RTL8723F)) + return; + + odm_set_mac_reg(dm, R_0x1008, BIT(1), val); + /*Set IRAM2/3*/ + odm_set_mac_reg(dm, R_0x1000, 0xc0, 0x0); + odm_set_mac_reg(dm, R_0x1000, 0x3000, 0x3); +} +#endif + +#if (RTL8197F_SUPPORT) +void +phydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + + if (dm->support_ic_type != ODM_RTL8197F) + return; + + if (opt == PHYDM_BACKUP) { + /*Stop DMA*/ + smp->backup_dma = odm_get_mac_reg(dm, R_0x300, 0xffff); + odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff); + } else { /*restore*/ + /*Resume DMA*/ + odm_set_mac_reg(dm, R_0x300, 0x7fff, smp->backup_dma); + } +} +#endif + +#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM +void +phydm_la_mv_data_2_tx_buffer(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + + if (!(dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC)) + return; + + pr_debug("GetTxPktBuf from iMEM\n"); + odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0); /*Disable LA mode HW block*/ + + /* 98F LA memory loccation is separate from normal + * driver use, DMA is no longer required to stop + */ + #if (RTL8197F_SUPPORT) + phydm_la_stop_dma_8197f(dm, PHYDM_BACKUP); + #endif + + /* @move LA mode content from IMEM to TxPktBuffer + * Source : OCPBASE_IMEM 0x00000000 + * Destination : OCPBASE_TXBUF 0x18780000 + * Length : 64K + */ + GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv, + OCPBASE_IMEM, + OCPBASE_TXBUF + + buf->start_pos, + 0x10000); +} +#endif + + +#if(RTL8723F_SUPPORT) +void +phydm_la_mv_data_2_tx_buffer_rtl8723f(void *dm_void, u32 source, u32 dest, u32 length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + //u32 ch0ctrl = (BIT(29)|BIT(31)); + u32 ch0ctrl = BIT(31); + u32 cnt=25000; + + pr_debug("GetTxPktBuf from iMEM\n"); + /*Disable LA mode HW block*/ + odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0); + + /* @move LA mode content from IMEM to TxPktBuffer + * Source : OCPBASE_IMEM 0x14040000 + * Destination : OCPBASE_TXBUF 0x18780000 + * Length : 32K + */ + /* + OCPBASE_IMEM = 0x18600000; + OCPBASE_TXBUF = 0x18780000; + GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv, + OCPBASE_IMEM, + OCPBASE_TXBUF + + buf->start_pos, + 0x8000); + */ + + // TODO: Replace all register define & bit define + + + //check if ddma ch0 is idle + while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){ + ODM_delay_ms(10); + cnt--; + if(cnt==0){ + pr_debug("1 InitDDMA88XX polling fail \n"); + return; + } + } + + ch0ctrl |= length & 0x3FFFF; + + //check if chksum continuous + //ch0ctrl |= BIT(24); + + odm_set_mac_reg(dm, R_0x1200, MASKDWORD, source); /*0x1200[31:0]:Source Address*/ + odm_set_mac_reg(dm, R_0x1204, MASKDWORD, dest); /*0x1204[31:0]:Destination Address*/ + odm_set_mac_reg(dm, R_0x1208, MASKDWORD, ch0ctrl); /*0x1208[17:0]:DMA Length*/ +//check if ddma ch0 is idle + while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){ + ODM_delay_ms(10); + cnt--; + if(cnt==0){ + pr_debug("2 InitDDMA88XX polling fail \n"); + return ; + } + } +} +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + +void phydm_la_bb_adv_reset_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct la_adv_trig *adv = &smp->adv_trig_table; + + odm_memory_set(dm, adv, 0, sizeof(struct la_adv_trig)); + +} + +void phydm_la_bb_adv_trig_setting_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct la_adv_trig *adv = &smp->adv_trig_table; + + pr_debug(" *ADV BB-trig = %d\n", adv->la_adv_bbtrigger_en); + + if (!adv->la_adv_bbtrigger_en) { /*normal LA mode & back to default*/ + /*@AND0*/ + odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0); + + /*@AND1*/ + odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0); + odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ + /*@AND2*/ + odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); + odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ + /*@AND3*/ + odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); + odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ + /*@AND4*/ + odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); /*@AND 4 mask en*/ + odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ + } else { + /*@AND0 */ + /*path 1 default: enable ori. BB trigger*/ + odm_set_bb_reg(dm, R_0x1ce4, BIT(27), + (adv->la_ori_bb_dis ? 1 : 0)); + + /* @AND1 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); + odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, adv->la_and1_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); + + /*@AND2 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(15), adv->la_and2_inv); + odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, adv->la_and2_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, adv->la_and2_val); + + /*@AND3 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(25), adv->la_and3_inv); + odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, adv->la_and3_sel); + odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, adv->la_and3_val); + + /*@AND4 */ + odm_set_bb_reg(dm, R_0x1ce8, BIT(26), adv->la_and4_inv); + odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, adv->la_and4_mask); + odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, adv->la_and4_bitmap); + } +} + +void phydm_la_bb_adv_cmd_show_jgr3(void *dm_void, u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct la_adv_trig *adv = &smp->adv_trig_table; + + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + " *And0 Disable=%d\n", adv->la_ori_bb_dis); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n", + adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv, + adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv, + adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n", + adv->la_and4_mask, adv->la_and4_bitmap, adv->la_and4_inv); +} + +void phydm_la_bb_adv_cmd_jgr3(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct la_adv_trig *adv = &smp->adv_trig_table; + u32 var1[10] = {0}; + u32 adv_trig_en; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + if ((strcmp(input[2], "show") == 0)) { + phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len); + return; + } + + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[0]); + PHYDM_SSCANF(input[3], DCMD_HEX, &var1[1]); + PHYDM_SSCANF(input[4], DCMD_HEX, &var1[2]); + PHYDM_SSCANF(input[5], DCMD_HEX, &var1[3]); + PHYDM_SSCANF(input[6], DCMD_HEX, &var1[4]); + + adv_trig_en = var1[0]; + + if (adv_trig_en != 1) { + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Back to Ori-BB-trig\n"); + phydm_la_bb_adv_reset_jgr3(dm); + return; + } + + adv->la_adv_bbtrigger_en = true; + + if (var1[1] == 0) { + adv->la_ori_bb_dis = (boolean)var1[2]; + } else if (var1[1] == 1) { + adv->la_and1_sel = (u8)var1[2]; + adv->la_and1_val = (u8)var1[3]; + adv->la_and1_inv = (boolean)var1[4]; + } else if (var1[1] == 2) { + adv->la_and2_sel = (u8)var1[2]; + adv->la_and2_val = (u8)var1[3]; + adv->la_and2_inv = (boolean)var1[4]; + } else if (var1[1] == 3) { + adv->la_and3_sel = (u8)var1[2]; + adv->la_and3_val = (u8)var1[3]; + adv->la_and2_inv = (boolean)var1[4]; + } else if (var1[1] == 4) { + adv->la_and4_mask = var1[2]; + adv->la_and4_bitmap = var1[3]; + adv->la_and4_inv = (boolean)var1[4]; + } + + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Adv_trig_en=%d]\n\n", adv_trig_en); + + phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len); +} + +void phydm_la_cmd_fast_jgr3(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct la_adv_trig *adv = &smp->adv_trig_table; + enum auto_detection_state ad_mode; + const u8 ofdm_codeword[8] = {0xb, 0xf, 0xa, 0xe, 0x9, 0xd, 0x8, 0xc}; + u32 codeword; + u8 rate_idx; + u32 trig_time_cca = 0; + s32 val_sign32_tmp = 0; + u32 var[10] = {0}; + u8 bw = *dm->band_width; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) { + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Only Support for JGR-3 ICs\n"); + return; + } + + if (bw > 2) { + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Not Support for BW > %dM\n", 20 << bw); + return; + } + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]); + + trig_time_cca = ((smp->smp_number_max >> (bw + 1)) / 10) + - (2 << (2 - bw)) - (2 - bw); + + if (var[0] < 10) { + /*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/ + /*--- Basic Trigger Setting --------------------------------*/ + smp->la_trig_mode = 1; + smp->la_trig_sig_sel = 2; + smp->la_trigger_time = trig_time_cca; + smp->la_mac_mask_or_hdr_sel = 0; + smp->la_trigger_edge = 0; + smp->la_smp_rate = 2 - bw; + smp->la_count = 0; + if (var[0] == 0) { /*AGC*/ + smp->la_dma_type = 5; + smp->la_dbg_port = 0x870; + } else if (var[0] == 1) { /*EVM*/ + smp->la_dma_type = 4; + smp->la_dbg_port = 0x392; + } else if (var[0] == 2) { /*SNR*/ + smp->la_dma_type = 4; + if (var[1] == 0) + smp->la_dbg_port = 0x89e; + else + smp->la_dbg_port = 0xa9e; + } else if (var[0] == 3) { /*CFO*/ + smp->la_dma_type = 4; + if (var[1] == 0) + smp->la_dbg_port = 0x88c; + else + smp->la_dbg_port = 0xa8c; + } else if (var[0] == 4) { /*ADC*/ + if (var[1] == 0) { + smp->la_dma_type = 0; + smp->la_dbg_port = 0x880; + } else { + smp->la_dma_type = 1; + smp->la_dbg_port = 0xa80; + } + } + /*--- Adv-Trigger Setting------------------------------------*/ + adv->la_adv_bbtrigger_en = false; + } else if (var[0] < 20) { + /*=== [Type: 10 ~ 19]: RX-EVM Trigger ===============================*/ + /*--- Basic Trigger Setting ---------------------------------*/ + smp->la_trig_mode = 0; + smp->la_trig_sig_sel = 0; + smp->la_mac_mask_or_hdr_sel = 0; + smp->la_trigger_edge = 0; + smp->la_smp_rate = 2 - bw; + smp->la_count = 0; + smp->la_dma_type = 4; + smp->la_dbg_port = 0x392; + + /*--- Adv-Trigger Setting -----------------------------------*/ + phydm_la_bb_adv_reset_jgr3(dm); + adv->la_adv_bbtrigger_en = true; + + /*And[0]*/ + adv->la_ori_bb_dis = true; + + /*And[1]*/ + adv->la_and1_inv = 0; + adv->la_and1_sel = 4; /*RX-state*/ + if (var[2] == 0) { + /*L-preamble 8+8+4 = 20*/ + smp->la_trigger_time = trig_time_cca - 20; + /*Legacy Data*/ + adv->la_and1_val = 5; + } else if (var[2] == 1) { + /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/ + smp->la_trigger_time = trig_time_cca - 32 - + (dm->num_rf_path * 4); + /*HT Data*/ + adv->la_and1_val = 18; + } else { + /*VHT-preamble (8+8+4) + (8+4+4*Nrx) +4 = 36 + Nrx * 4*/ + smp->la_trigger_time = trig_time_cca - 36 - + (dm->num_rf_path * 4); + /*VHT Data*/ + adv->la_and1_val = 18; + } + + /*And[2]*/ + adv->la_and2_inv = 0; + adv->la_and2_sel = 0; /*Disable*/ + + /*And[3]*/ + adv->la_and2_inv = 0; + adv->la_and3_sel = 0; /*Disable*/ + + /*And[4]*/ + adv->la_and4_inv = 0; + + if (var[0] == 11) { + /*[>= -X dB]*/ + if (var[1] == 2) { + adv->la_and4_bitmap = 0; + adv->la_and4_mask = 0x1; + } else if (var[1] == 4) { + adv->la_and4_bitmap = 0; + adv->la_and4_mask = 0x3; + } else if (var[1] == 8) { + adv->la_and4_bitmap = 0; + adv->la_and4_mask = 0x7; + } else if (var[1] == 16) { + adv->la_and4_bitmap = 0; + adv->la_and4_mask = 0xf; + } else if (var[1] == 32) { + adv->la_and4_bitmap = 0; + adv->la_and4_mask = 0x1f; + } else if (var[1] == 64) { + adv->la_and4_bitmap = 0; + adv->la_and4_mask = 0x3f; + } else { + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "Not Support >= -%d dB\n", var[1]); + return; + } + } else if (var[0] == 10) { + /*[<= -X dB]*/ + if (var[1] == 2) { + adv->la_and4_bitmap = 0x7e; + adv->la_and4_mask = 0x7e; + } else if (var[1] == 4) { + adv->la_and4_bitmap = 0x7c; + adv->la_and4_mask = 0x7c; + } else if (var[1] == 8) { + adv->la_and4_bitmap = 0x78; + adv->la_and4_mask = 0x78; + } else if (var[1] == 16) { + adv->la_and4_bitmap = 0x70; + adv->la_and4_mask = 0x70; + } else if (var[1] == 32) { + adv->la_and4_bitmap = 0x60; + adv->la_and4_mask = 0x60; + } else if (var[1] == 64) { + adv->la_and4_bitmap = 0x40; + adv->la_and4_mask = 0x40; + } else { + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "Not Support <= -%d dB\n", var[1]); + return; + } + } else if (var[0] == 12) { + /*[= -X dB]*/ + val_sign32_tmp = 0 - (s32)var[1]; + adv->la_and4_bitmap = (u32)(val_sign32_tmp & 0x7f); + adv->la_and4_mask = 0x7f; + } + } else if (var[0] < 30) { + /*=== [Type: 20 ~ 29]: RX-Rate Trigger ==============================*/ + /*--- Basic Trigger Setting ---------------------------------*/ + smp->la_trig_mode = 0; + smp->la_trig_sig_sel = 0; + smp->la_mac_mask_or_hdr_sel = 0; + smp->la_trigger_edge = 0; + smp->la_smp_rate = 2 - bw; + smp->la_count = 0; + smp->la_dma_type = 4; + + rate_idx = (u8)var[1]; + + /*--- Adv-Trigger Setting -----------------------------------*/ + phydm_la_bb_adv_reset_jgr3(dm); + adv->la_adv_bbtrigger_en = true; + + /*And[0]*/ + adv->la_ori_bb_dis = true; + + /*And[1]*/ + adv->la_and1_inv = 0; + adv->la_and1_sel = 4; /*RX-state*/ + + if (rate_idx <= ODM_RATE54M && rate_idx >= ODM_RATE6M) { + ad_mode = AD_LEGACY_MODE; + codeword = (u32)ofdm_codeword[rate_idx - ODM_RATE6M]; + smp->la_dbg_port = 0x3a9; + /*L-preamble 8+8 = 16*/ + smp->la_trigger_time = trig_time_cca - 20; + /*Legacy Data*/ + adv->la_and1_val = 5; + } else if (rate_idx <= ODM_RATEMCS31) { + ad_mode = AD_HT_MODE; + codeword = (u32)(rate_idx - ODM_RATEMCS0); + smp->la_dbg_port = 0x3aa; + /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/ + smp->la_trigger_time = trig_time_cca - 32 - + (dm->num_rf_path * 4); + /*HT,VHT Data*/ + adv->la_and1_val = 18; + } else if (rate_idx <= ODM_RATEVHTSS4MCS9) { + ad_mode = AD_VHT_MODE; + codeword = (u32)phydm_rate_order_compute(dm, rate_idx); + codeword--; + smp->la_dbg_port = 0x3ab; + /*VHT-preamble (8+8+4) + (8+4+4*Nrx) = 36 + Nrx * 4*/ + smp->la_trigger_time = trig_time_cca - 36 - + (dm->num_rf_path * 4); + /*HT,VHT Data*/ + adv->la_and1_val = 18; + } else { + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "Not Support\n"); + return; + } + + /*And[2]*/ + adv->la_and2_inv = 0; + adv->la_and2_sel = 0; /*Disable*/ + + /*And[3]*/ + adv->la_and2_inv = 0; + adv->la_and3_sel = 0; /*Disable*/ + + /*And[4]*/ + adv->la_and4_inv = 0; + + if (var[0] == 20) { + if (ad_mode == AD_LEGACY_MODE) { + adv->la_and4_bitmap = codeword; + adv->la_and4_mask = 0x3000000f; + } else if (ad_mode == AD_HT_MODE) { + adv->la_and4_bitmap = (2 << 28) | codeword; + adv->la_and4_mask = 0x3000003f; + } else { /* AD_VHT_MODE*/ + adv->la_and4_bitmap = (1 << 28) | + (codeword << 4); + adv->la_and4_mask = 0x300000f0; + } + } else { + PDM_SNPF(*_out_len, *_used, output + *_used, + *_out_len - *_used, + "Not Support\n"); + return; + } + } else { + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "Not Support\n"); + return; + } + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Basic-Trigger]\n"); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + " *echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n", + smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type, + smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel, + smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate, + smp->la_count); + pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n", + smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type, + smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel, + smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate, + smp->la_count); + + if (adv->la_adv_bbtrigger_en) { + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + "[Adv-Trigger]\n"); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + " *And0 Disable=%d\n", adv->la_ori_bb_dis); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n", + adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv, + adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv, + adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv); + PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used, + " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n", + adv->la_and4_mask, adv->la_and4_bitmap, + adv->la_and4_inv); + } + phydm_la_set(dm); +} + +#endif + +void +phydm_la_buffer_print(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + u64 la_pattern_msb, la_pattern_lsb; + u64 la_pattern, la_pattern_part; + s64 tmp_s64; + u64 mask = 0xffffffff; + u8 mask_length = 0; + u32 i; + u32 idx; + u32 var[10] = {0}; + + if (!buf->octet || buf->length == 0 || buf->length < smp->smp_number) + return; + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var[3]); + + pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n", + smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type, + smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel, + smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate, + smp->la_count); + pr_debug("[LA Data Dump] smp_number = %d\n", smp->smp_number); + pr_debug("Dump_Start\n"); + + if (var[0] == 0) { + for (i = 0; i < smp->smp_number; i++) { + idx = i << 1; + pr_debug("%08x%08x\n", buf->octet[idx], + buf->octet[idx + 1]); + } + } else if (var[0] == 1) { + /*------------------------*/ + if (var[1] == 0) + pr_debug("[Hex]\n"); + else if (var[1] == 1) + pr_debug("[Dec unsigned]\n"); + else if (var[1] == 2) + pr_debug("[Dec signed]\n"); + + pr_debug("BIT[%d:%d]\n", var[3], var[2]); + + if (var[2] > var[3]) { + pr_debug("[Warning] BIT_L > BIT_H\n"); + return; + } + + mask_length = (u8)(var[3] - var[2] + 1); + mask = phydm_gen_bitmask(mask_length) << var[2]; + /*------------------------*/ + for (i = 0; i < smp->smp_number; i++) { + idx = i << 1; + la_pattern_msb = (u64)buf->octet[idx]; + la_pattern_lsb = (u64)buf->octet[idx + 1]; + la_pattern = (la_pattern_msb << 32) | la_pattern_lsb; + la_pattern_part = (la_pattern & mask) >> var[2]; + + if (var[1] == 0) { + pr_debug("0x%llx\n", la_pattern_part); + } else if (var[1] == 1) { + pr_debug("%llu\n", la_pattern_part); + } else if (var[1] == 2) { + tmp_s64 = phydm_cnvrt_2_sign_64(la_pattern_part, + mask_length); + pr_debug("%lld\n", tmp_s64); + } + } + } + pr_debug("Dump_End\n\n"); +} + +void +phydm_la_buffer_release(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + + if (buf->length != 0x0) { + odm_free_memory(dm, buf->octet, buf->length); + buf->length = 0x0; + } +} + +boolean +phydm_la_buffer_allocate(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + #endif + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + boolean ret = true; + + pr_debug("[LA mode BufferAllocate]\n"); + + if (buf->length == 0) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (PlatformAllocateMemoryWithZero(adapter, (void **)& + buf->octet, + buf->buffer_size) != + RT_STATUS_SUCCESS) + ret = false; + #else + odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size); + + if (!buf->octet) + ret = false; + #endif + + if (ret) + buf->length = buf->buffer_size; + } + + return ret; +} + +void phydm_la_access_tx_pkt_buf(void *dm_void, u32 addr, u32 buff_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + u32 page; + u32 data_l = 0, data_h = 0; + + #if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + indirect_access_sdram_8192f(dm->adapter, TX_PACKET_BUFFER, + TRUE, (u16)addr >> 3, 0, + &data_h, &data_l); + #else + odm_write_1byte(dm, R_0x0106, 0x69); + odm_set_mac_reg(dm, R_0x0140, MASKDWORD, addr >> 3); + data_l = odm_get_mac_reg(dm, R_0x0144, MASKDWORD); + data_h = odm_get_mac_reg(dm, R_0x0148, MASKDWORD); + odm_write_1byte(dm, R_0x0106, 0x0); + #endif + } else + #endif + { + /* Reg140=0x780+(addr>>12), + * addr=0x30~0x3F, total 16 pages + */ + page = addr >> 12; + + if (page != smp->txff_page) { + smp->txff_page = page; + odm_set_mac_reg(dm, R_0x0140, MASKLWORD, 0x780 + page); + } + data_l = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff)); + data_h = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff) + 4); + } + + buf->octet[buff_idx] = data_h; + buf->octet[buff_idx + 1] = data_l; + + /*@==== [Print LA Patterns] ==========================================*/ + if (smp->is_la_print) + pr_debug("%08x%08x\n", data_h, data_l); +} + +void phydm_la_get_tx_pkt_buf(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + u32 i = 0, value32 = 0; + u32 addr = 0, finish_addr = 0; /* @(unit: 8Byte)*/ + boolean is_round_up = false; + u32 addr_8byte = 0; + u32 round_up_point = 0; + u32 index = 0; + u32 imem_base; + u32 txbuf_base; + u32 dma_len; + u32 imem_start_addr; + u32 imem_start_addr_offset; + u32 txbuff_start_addr; + u32 tx_buff_addr; + + #if (RTL8814B_SUPPORT) + boolean recover_success = true; + #endif + + odm_memory_set(dm, buf->octet, 0, buf->length); + pr_debug("GetTxPktBuf\n"); + + /*@==== [Get LA Report] ==============================================*/ + if (dm->support_ic_type & ODM_RTL8192F) { + value32 = odm_read_4byte(dm, R_0x7f0); + is_round_up = (boolean)((value32 & BIT(31)) >> 31); + finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/ + } else { + odm_write_1byte(dm, R_0x0106, 0x69); + value32 = odm_read_4byte(dm, R_0x7c0); + is_round_up = (boolean)((value32 & BIT(31)) >> 31); + + if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) + finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/ + else + finish_addr = (value32 & 0x7FFF0000) >> 16; /*@15bit (unit: 8Byte)*/ + } + + #if (RTL8814B_SUPPORT) + recover_success = phydm_la_finish_addr_recover_8814B(dm, &finish_addr); + #endif + + pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((0x%x))\n", + buf->start_pos, buf->end_pos, buf->buffer_size); + if (is_round_up) { + pr_debug("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n", + buf->start_pos, finish_addr << 3, buf->end_pos); + addr = (finish_addr + 2) << 3; /*+1 or +2 ??*/ + round_up_point = (buf->end_pos - addr) >> 3; /*@Byte to 8Byte*/ + smp->smp_number = smp->smp_number_max; + pr_debug("is_round_up=(%d), round_up_point=(%d), 0x7c0/0x7F0=(0x%x), smp_number=(%d)\n", + is_round_up, round_up_point, value32, smp->smp_number); + } else { + pr_debug("buf_start(0x%x)|------->|finish_addr(0x%x) |buf_end(0x%x)\n", + buf->start_pos, finish_addr << 3, buf->end_pos); + addr = buf->start_pos; + addr_8byte = addr >> 3; + smp->smp_number = DIFF_2(addr_8byte, finish_addr); + + pr_debug("is_round_up=(%d), smp_number=(%d)\n", + is_round_up, smp->smp_number); + } + + /*@==== [Get LA Patterns in TXFF] ====================================*/ + pr_debug("Dump_Start\n"); +#if(RTL8723F_SUPPORT) + imem_base = 0x14040000; + txbuf_base = 0x18780000; + dma_len = 0x8000; + txbuff_start_addr = txbuf_base; + imem_start_addr_offset = addr; + if (is_round_up) { + for(index = 0;index < 4;index++) { + dma_len = 0x8000; + imem_start_addr= imem_base + (imem_start_addr_offset&0x1FFFF); + + if((imem_start_addr_offset + 0x8000) >= buf->end_pos) { + dma_len = buf->end_pos-imem_start_addr_offset; + + phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len); + + tx_buff_addr = 0; + for (i = 0; i < (dma_len >> 3); i++) { + phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1); + tx_buff_addr += 8; + } + imem_start_addr = imem_base; + dma_len = 0x8000-dma_len; + phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len); + + tx_buff_addr = 0; + for (i = 0; i < (dma_len >> 3); i++) { + phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1); + tx_buff_addr += 8; + } + imem_start_addr_offset = dma_len; + } + else { + dma_len = 0x8000; + phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len); + + tx_buff_addr = 0; + for (i = 0; i <4096; i++) { + phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1); + tx_buff_addr += 8; + } + imem_start_addr_offset += 0x8000; + } + } + } else { + for(index = 0; index < 4;index++) { + imem_start_addr = imem_base + (imem_start_addr_offset & 0x1FFFF); + if ((imem_start_addr_offset + 0x8000) > (finish_addr << 3)) + dma_len = (finish_addr << 3) - imem_start_addr_offset; /*0x1208[17:0]:DMA Length*/ + phydm_la_mv_data_2_tx_buffer_rtl8723f(dm,imem_start_addr, txbuff_start_addr, dma_len); + tx_buff_addr = 0; + for (i = 0; i < (dma_len >> 3); i++) { + phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1); + tx_buff_addr += 8; + } + dma_len = 0x8000; + imem_start_addr_offset += 0x8000; + if (imem_start_addr_offset > (finish_addr << 3)) + break; + } + } +#else + + #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM + phydm_la_mv_data_2_tx_buffer(dm); + #endif + + #if (RTL8814B_SUPPORT) + if ((dm->support_ic_type & ODM_RTL8814B) && !recover_success) { + addr = buf->start_pos; + smp->smp_number = smp->smp_number_max; + } + #endif + + for (i = 0; i < smp->smp_number; i++) { + phydm_la_access_tx_pkt_buf(dm, addr, i << 1); + addr += 8; + + if (addr >= buf->end_pos) + addr = buf->start_pos; /*Ring buffer*/ + } + + #if (RTL8197F_SUPPORT) + phydm_la_stop_dma_8197f(dm, PHYDM_RESTORE); + #endif +#endif + pr_debug("Dump_End\n"); +} + +void phydm_la_set_trig_src(void *dm_void, u8 la_trig_mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg = (dm->support_ic_type == ODM_RTL8192F) ? R_0x7f0 : R_0x7c0; + + if (la_trig_mode == PHYDM_ADC_MAC_TRIG) + odm_set_mac_reg(dm, reg, BIT(3), 1); + else + odm_set_mac_reg(dm, reg, BIT(3), 0); +} + +void phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + u32 reg_value = 0; + u32 reg1 = 0, reg2 = 0, reg3 = 0; + + if (dm->support_ic_type & ODM_RTL8192F) { + reg1 = R_0x7f0; + reg2 = R_0x7f4; + reg3 = R_0x7f8; + } else { + reg1 = R_0x7c0; + reg2 = R_0x7c4; + reg3 = R_0x7c8; + } + + odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/ + /*@Enable LA mode HW block*/ + odm_set_mac_reg(dm, reg1, BIT(0), 1); + + #if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) + phydm_la_mac_clk_en(dm, true); + #endif + + if (smp->la_trig_mode == PHYDM_MAC_TRIG) { + smp->la_dump_mode = LA_MAC_DBG_DUMP; + /*polling bit for MAC mode*/ + odm_set_mac_reg(dm, reg1, BIT(2), 1); + /*trigger mode for MAC*/ + odm_set_mac_reg(dm, reg1, 0x18, smp->la_trigger_edge); + pr_debug("[MAC_trig] ref_mask=(0x%x), ref_value=(0x%x), dbg_port =(0x%x)\n", + smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel, + smp->la_dbg_port); + /*@[Set MAC Debug Port]*/ + odm_set_mac_reg(dm, R_0xf4, BIT(16), 1); + odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port); + odm_set_mac_reg(dm, reg2, MASKDWORD, + smp->la_mac_mask_or_hdr_sel); + odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel); + } else { + smp->la_dump_mode = LA_BB_ADC_DUMP; + + if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { + /*polling bit for MAC trigger event*/ + if (impossible_trig_condi) + phydm_la_set_trig_src(dm, PHYDM_ADC_BB_TRIG); + else + phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG); + + odm_set_mac_reg(dm, reg1, 0xc0, smp->la_trig_sig_sel); + + if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) { + /* @manual trigger reg1[5] = 0->1*/ + odm_set_mac_reg(dm, reg1, BIT(5), 1); + } + } + /*polling bit for BB ADC mode*/ + odm_set_mac_reg(dm, reg1, BIT(1), 1); + } + + reg_value = odm_get_mac_reg(dm, reg1, 0xff); + pr_debug("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1, reg_value); + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1, + reg_value)); + #endif +} + +void phydm_la_set_bb_dbg_port(void *dm_void, boolean impossible_trig_condi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + + u8 trig_mode = smp->la_trig_mode; + u32 trig_sel = smp->la_trig_sig_sel; + u32 dbg_port = smp->la_dbg_port; + + if (trig_mode == PHYDM_MAC_TRIG) + trig_sel = 0; /*@ignore this setting*/ + + /*set BB debug port*/ + if (impossible_trig_condi) { + dbg_port = 0xf; + trig_sel = 0; + pr_debug("[BB Setting] fake-trigger!\n"); + } + + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) { + pr_debug(" *Set dbg_port=(0x%x)\n", dbg_port); + } else { + dbg_port = phydm_get_bb_dbg_port_idx(dm); + pr_debug("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port); + } + + /*@debug port bit*/ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel); + #endif + } else { + odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel); + } + + if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) { + pr_debug(" *Set dbg_port[BIT] = %d\n", trig_sel); + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + (" *Set dbg_port[BIT] = %d\n", trig_sel)); + #endif + } +} + +void phydm_la_set_bb(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + + u8 trig_mode = smp->la_trig_mode; + u8 edge = smp->la_trigger_edge; + u8 smp_rate = smp->la_smp_rate; + u8 dma_type = smp->la_dma_type; + u32 dbg_port_hdr_sel = 0; + char *trig_mode_word = NULL; + + pr_debug("3. [BB Setting] mode=(%d), Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n", + trig_mode, + (edge == 0) ? "P" : "N", 80 >> smp_rate, dma_type); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (trig_mode == PHYDM_ADC_RF0_TRIG) + dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/ + else if (trig_mode == PHYDM_ADC_RF1_TRIG) + dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/ + else if ((trig_mode == PHYDM_ADC_BB_TRIG) || + (trig_mode == PHYDM_ADC_MAC_TRIG)) { + if (smp->la_mac_mask_or_hdr_sel <= 0xf) + dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel; + else + dbg_port_hdr_sel = 0; + } + + phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel); + + odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1);/*@update rpt every pkt*/ + odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type); + /*@0: posedge, 1: negedge*/ + odm_set_bb_reg(dm, R_0x95c, BIT(31), edge); + odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate); + /* @(0:) '80MHz' + * (1:) '40MHz' + * (2:) '20MHz' + * (3:) '10MHz' + * (4:) '5MHz' + * (5:) '2.5MHz' + * (6:) '1.25MHz' + * (7:) '160MHz (for BW160 ic)' + */ + #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT) + phydm_la_clk_en(dm, true); + #endif + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);/*@update rpt every pkt*/ + /*@MAC-PHY timing*/ + odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0); + odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/ + odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type); + /*@0: posedge, 1: negedge ??*/ + odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge); + odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate); + + phydm_la_bb_adv_trig_setting_jgr3(dm); + #endif + } else { + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); /*@update rpt every pkt*/ + + #if (RTL8192F_SUPPORT) + if ((dm->support_ic_type & ODM_RTL8192F)) + /*@LA reset HW block enable for true-mac asic*/ + odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1); + #endif + + odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type); + /*@0: posedge, 1: negedge*/ + odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge); + odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate); + /* @(0:) '80MHz' + * (1:) '40MHz' + * (2:) '20MHz' + * (3:) '10MHz' + * (4:) '5MHz' + * (5:) '2.5MHz' + * (6:) '1.25MHz' + * (7:) '160MHz (for BW160 ic)' + */ + } +} + +void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 time_unit_num = 0; + u32 unit = 0; + + if (trigger_time_mu_sec < 128) + unit = 0; /*unit: 1mu sec*/ + else if (trigger_time_mu_sec < 256) + unit = 1; /*unit: 2mu sec*/ + else if (trigger_time_mu_sec < 512) + unit = 2; /*unit: 4mu sec*/ + else if (trigger_time_mu_sec < 1024) + unit = 3; /*unit: 8mu sec*/ + else if (trigger_time_mu_sec < 2048) + unit = 4; /*unit: 16mu sec*/ + else if (trigger_time_mu_sec < 4096) + unit = 5; /*unit: 32mu sec*/ + else if (trigger_time_mu_sec < 8192) + unit = 6; /*unit: 64mu sec*/ + else if (trigger_time_mu_sec < 16384) + if (dm->support_ic_type & ODM_RTL8723F) + unit = 7; /*unit: 128mu sec*/ + + time_unit_num = (u8)(trigger_time_mu_sec >> unit); + + pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", + time_unit_num, unit); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, ( + "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", + time_unit_num, unit)); + #endif + + if (dm->support_ic_type & ODM_RTL8192F) { + odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit); + odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f)); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_RTL8814B) { + odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit); + odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f)); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit); + odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f)); + #endif + } else { + odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit); + odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f)); + } +} + +void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct rtl8192cd_priv *priv = dm->priv; + u8 normal_LA_on = priv->pmib->miscEntry.normal_LA_on; +#endif + u32 buff_size_base = 0; + u32 end_pos_tmp = 0; + + smp->la_buff_mode = mode; + switch (dm->support_ic_type) { + case ODM_RTL8814A: + buff_size_base = 0x10000; + end_pos_tmp = 0x40000; + break; + case ODM_RTL8822B: + case ODM_RTL8822C: + case ODM_RTL8812F: + buff_size_base = 0x20000; /*@WIN: TX_FIFO_SIZE_LA_8822C*/ + end_pos_tmp = 0x40000; + break; + case ODM_RTL8814B: + buff_size_base = 0x30000; + end_pos_tmp = 0x60000; + break; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + case ODM_RTL8197F: + case ODM_RTL8198F: + case ODM_RTL8197G: + buff_size_base = 0x10000; + end_pos_tmp = (normal_LA_on == 1) ? 0x20000 : 0x10000; + break; +#endif + case ODM_RTL8192F: + buff_size_base = 0xE000; + end_pos_tmp = 0x10000; + break; + case ODM_RTL8821C: + buff_size_base = 0x8000; + end_pos_tmp = 0x10000; + break; + case ODM_RTL8195B: + buff_size_base = 0x4000; + end_pos_tmp = 0x8000; + break; + case ODM_RTL8723F: + buff_size_base = 0x20000; + end_pos_tmp = 0x20000; + break; + default: + pr_debug("[%s] Warning!", __func__); + break; + } + + buf->buffer_size = buff_size_base; + + if (dm->support_ic_type & ODM_RTL8814B) { + if (mode == ADCSMP_BUFF_HALF) { + odm_set_mac_reg(dm, R_0x7cc, BIT(21), 0); + } else { + buf->buffer_size = buf->buffer_size << 1; + odm_set_mac_reg(dm, R_0x7cc, BIT(21), 1); + } + } else if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) { + if (mode == ADCSMP_BUFF_HALF) { + odm_set_mac_reg(dm, R_0x7cc, BIT(30), 0); + } else { + buf->buffer_size = buf->buffer_size << 1; + odm_set_mac_reg(dm, R_0x7cc, BIT(30), 1); + } + } + + buf->end_pos = end_pos_tmp; + buf->start_pos = end_pos_tmp - buf->buffer_size; + smp->smp_number_max = buf->buffer_size >> 3; + + pr_debug("start_addr=(0x%x), end_addr=(0x%x), buffer_size=(0x%x), smp_number_max=(%d)\n", + buf->start_pos, buf->end_pos, buf->buffer_size, + smp->smp_number_max); +} + +void phydm_la_adc_smp_start(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + u8 tmp_u1b = 0; + u8 i = 0; + u8 polling_bit = 0; + u8 bkp_val = 0; + boolean polling_ok = false; + boolean impossible_trig_condi = (smp->en_fake_trig) ? true : false; + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("1. [BB Setting] Mode=(%d), DbgPort=(0x%x), Edge=(%d), SmpRate=(%d), Trig_Sel=(0x%x), Dma_type=(%d)\n", + smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge, + smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type)); + #endif + pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n", + smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge, + smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type); + + if(dm->support_ic_type & ODM_RTL8723F) + bkp_val = (u8)odm_get_mac_reg(dm, R_0x1008, BIT(1)); + + phydm_la_set_mac_trigger_time(dm, smp->la_trigger_time); + phydm_la_set_bb(dm); + phydm_la_set_bb_dbg_port(dm, impossible_trig_condi); + phydm_la_set_mac_iq_dump(dm, impossible_trig_condi); + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_stop(dm->priv); + #endif + + if (impossible_trig_condi) { + ODM_delay_ms(100); + phydm_la_set_bb_dbg_port(dm, false); + + if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { + phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG); + } + } +#if RTL8198F_SUPPORT + phydm_la_pre_run(dm); +#endif + polling_bit = (smp->la_dump_mode == LA_BB_ADC_DUMP) ? BIT(1) : BIT(2); + do { /*Polling time always use 100ms, when it exceed 2s, break loop*/ + if (dm->support_ic_type & ODM_RTL8192F) + tmp_u1b = odm_read_1byte(dm, R_0x7f0); + else + tmp_u1b = odm_read_1byte(dm, R_0x7c0); + + pr_debug("[%d] polling rpt=((0x%x))\n", i, tmp_u1b); + + if (smp->adc_smp_state != ADCSMP_STATE_SET) { + pr_debug("[state Error] state != ADCSMP_STATE_SET\n"); + break; + + } else if (tmp_u1b & polling_bit) { + ODM_delay_ms(100); + i++; + continue; + } else { + pr_debug("[LA Query OK] polling_bit=%d\n", polling_bit); + polling_ok = true; + break; + } + } while (i < 20); + + if (smp->adc_smp_state == ADCSMP_STATE_SET) { + if (polling_ok) + phydm_la_get_tx_pkt_buf(dm); + else + pr_debug("[Polling timeout]\n"); + } + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_resume(dm->priv); + #endif + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (smp->adc_smp_state == ADCSMP_STATE_SET) + smp->adc_smp_state = ADCSMP_STATE_QUERY; + #endif + + pr_debug("[LA mode] la_count = ((%d))\n", smp->la_count); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("[LA mode] la_count = ((%d))\n", smp->la_count)); + #endif + + phydm_la_stop(dm); + + if (smp->la_count == 0) { + pr_debug("LA Dump finished ---------->\n\n\n"); + phydm_release_bb_dbg_port(dm); + + #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT) + phydm_la_clk_en(dm, false); + #endif + #if (RTL8723F_SUPPORT) + if(dm->support_ic_type & ODM_RTL8723F) + phydm_la_mac_clk_en(dm, (bkp_val == 1) ? true : false); + #endif + } else { + smp->la_count--; + pr_debug("LA Dump more ---------->\n\n\n"); + phydm_la_set(dm); + } +} + +void phydm_la_set(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_set_success = true; + struct rt_adcsmp *smp = &dm->adcsmp; + + if (smp->adc_smp_state != ADCSMP_STATE_IDLE) + is_set_success = false; + else if (smp->adc_smp_buf.length == 0) + is_set_success = phydm_la_buffer_allocate(dm); + + if (!is_set_success) { + pr_debug("[LA Set Fail] LA_State=(%d)\n", smp->adc_smp_state); + return; + } + + smp->adc_smp_state = ADCSMP_STATE_SET; + + pr_debug("[LA Set Success] LA_State=(%d)\n", smp->adc_smp_state); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + pr_debug("ADCSmp_work_item_index=(%d)\n", smp->la_work_item_index); + + if (smp->la_work_item_index != 0) { + odm_schedule_work_item(&smp->adc_smp_work_item_1); + smp->la_work_item_index = 0; + } else { + odm_schedule_work_item(&smp->adc_smp_work_item); + smp->la_work_item_index = 1; + } +#else + phydm_la_adc_smp_start(dm); +#endif +} + +void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE)) + return; + +#ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM + if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) { + if (dm->is_download_fw) + return; + } + #if RTL8198F_SUPPORT + if (dm->support_ic_type & ODM_RTL8198F) { + if (!*dm->mp_mode && !dm->priv->pmib->miscEntry.normal_LA_on) { + pr_debug("plz re-set normal_LA_on = 1 & DnUp.\n"); + return; + } + } + #endif +#endif + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + /*@dbg_print("echo cmd input_num = %d\n", input_num);*/ + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "=====[LA Mode Help] =============================\n"); + /*Trigger*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "BB_trig: 1 0 {DbgPort Bit} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {Edge: 0(P),1(N)} {f_smp:80 >> N} {Capture num}\n\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "MAC_trig: 1 1 {0-ok/1-fail/2-cca} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {N/A} {f_smp:80 >> N} {Cpture num}\n\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "All: {En} {0:ADC_BB_trig,1:ADC MAC_trig,2:RF0,3:RF1,4:MAC}\n\t{BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA#} {TrigTime}\n\t{DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n\n"); + /*Adv-Trig*/ + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + PDM_SNPF(out_len, used, output + used, out_len - used, + "adv show\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "adv {adv_trig_en} {0:And[0]_disable} {en}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "adv {adv_trig_en} {1~3: And[3:0]} {Sel} {Val} {Inv}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "adv {adv_trig_en} {4: And[4]} {BitMask} {BitVal} {Inv}\n\n"); + #endif + /*Setting*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "set {1:tx_buff_size} {0: half, 1:full}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "set {2:Fake Trigger} {en}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "set {3:Auto Print} {en}\n\n"); + /*Print*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "print {0: all(Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "print {1: partial} {0:hex 1:dec 2: s-dec} {bit_L} {bit_H}\n\n"); + + /*Fast Trigger*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {0: CCA trig & AGC Dbg Port}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {1: CCA trig & EVM Dbg Port}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {2: CCA trig & SNR Dbg Port}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {3: CCA trig & CFO Dbg Port}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {4: CCA trig & ADC output Dbg Port}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {10: EVM>=-X dB, 11: EVM<=-X dB} {X=2/4/8/16/32/64} {0:Lgcy, 1:HT}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {12: EVM=-X dB} {X} {0:Lgcy, 1:HT}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fast {20: RX-rate-idx=X} {X}\n"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "=================================================\n"); + } else if ((strcmp(input[1], "print") == 0)) { + phydm_la_buffer_print(dm, input, &used, output, &out_len); +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if ((strcmp(input[1], "fast") == 0)) { + phydm_la_cmd_fast_jgr3(dm, input, &used, output, &out_len); + + } else if ((strcmp(input[1], "adv") == 0)) { + phydm_la_bb_adv_cmd_jgr3(dm, input, &used, output, &out_len); +#endif + } else if ((strcmp(input[1], "set") == 0)) { + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + + if (var1[1] == 1) { + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + phydm_la_set_buff_mode(dm, (enum la_buff_mode)var1[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Buff_mode=(%d/2)\n", smp->la_buff_mode + 1); + } else if (var1[1] == 2) { + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + smp->en_fake_trig = (boolean)var1[2]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "en_fake_trig=(%d)\n", smp->en_fake_trig); + } else if (var1[1] == 3) { + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + smp->is_la_print = (boolean)var1[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Auto print=(%d)\n", smp->is_la_print); + } + } else if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + + smp->la_trig_mode = (u8)var1[1]; + + if (smp->la_trig_mode == PHYDM_MAC_TRIG) + PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]); + else + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + smp->la_trig_sig_sel = var1[2]; + + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]); + PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]); + PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]); + PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]); + PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]); + PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]); + + smp->la_dma_type = (u8)var1[3]; + smp->la_trigger_time = var1[4]; /*unit: us*/ + smp->la_mac_mask_or_hdr_sel = var1[5]; + smp->la_dbg_port = var1[6]; + smp->la_trigger_edge = (u8)var1[7]; + smp->la_smp_rate = (u8)(var1[8] & 0x7); + smp->la_count = var1[9]; + + pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n", + var1[0], var1[1], var1[2], var1[3], var1[4], + var1[5], var1[6], var1[7], var1[8], var1[9]); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, + ("echo lamode %d %d %d %d %d %d %x %d %d %d\n", + var1[0], var1[1], var1[2], var1[3], + var1[4], var1[5], var1[6], var1[7], + var1[8], var1[9])); + #endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", + smp->la_trig_mode, smp->la_trig_sig_sel, + smp->la_dma_type); + PDM_SNPF(out_len, used, output + used, out_len - used, + "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", + smp->la_trigger_time, + smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port); + PDM_SNPF(out_len, used, output + used, out_len - used, + "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", + smp->la_trigger_edge, (80 >> smp->la_smp_rate), + smp->la_count); + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + PDM_SNPF(out_len, used, output + used, out_len - used, + "k.en_new_bbtrigger = ((%d))\n", + smp->adv_trig_table.la_adv_bbtrigger_en); + #endif + + phydm_la_set(dm); + } else { + phydm_la_stop(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable LA mode\n"); + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_la_stop(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + + smp->adc_smp_state = ADCSMP_STATE_IDLE; +} + +void phydm_la_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct rt_adcsmp *smp = &dm->adcsmp; + struct rt_adcsmp_string *buf = &smp->adc_smp_buf; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE)) + return; + + smp->adc_smp_state = ADCSMP_STATE_IDLE; + smp->is_la_print = true; + smp->en_fake_trig = false; + smp->txff_page = 0xffffffff; + phydm_la_set_buff_mode(dm, ADCSMP_BUFF_HALF); + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + phydm_la_bb_adv_reset_jgr3(dm); + #endif +} + +void adc_smp_de_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE)) + return; + + phydm_la_stop(dm); + phydm_la_buffer_release(dm); +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +void adc_smp_work_item_callback(void *context) +{ + void *adapter = (void *)context; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct rt_adcsmp *smp = &dm->adcsmp; + + pr_debug("[WorkItem Call back] LA_State=(%d)\n", smp->adc_smp_state); + phydm_la_adc_smp_start(dm); +} +#endif +#endif /*@endif PHYDM_LA_MODE_SUPPORT*/ diff --git a/hal/phydm/phydm_adc_sampling.h b/hal/phydm/phydm_adc_sampling.h new file mode 100644 index 0000000..0e00e27 --- /dev/null +++ b/hal/phydm/phydm_adc_sampling.h @@ -0,0 +1,172 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __INC_ADCSMP_H +#define __INC_ADCSMP_H + +#if (PHYDM_LA_MODE_SUPPORT) + +/* 2020.07.03 [8723F] Fix SD4 compile error*/ +#define DYNAMIC_LA_MODE "4.2" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT || RTL8197G_SUPPORT) + #define PHYDM_COMPILE_LA_STORE_IN_IMEM +#endif +#endif + +#define PHYDM_LA_STORE_IN_IMEM_IC (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8197G) + +#define FULL_BUFF_MODE_SUPPORT (ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\ + ODM_RTL8812F | ODM_RTL8814B) + +/* @ ============================================================ + * enumrate + * ============================================================ + */ +enum la_dump_mode { + LA_BB_ADC_DUMP = 0, + LA_MAC_DBG_DUMP = 1 +}; + +enum rt_adcsmp_trig_sel { + PHYDM_ADC_BB_TRIG = 0, + PHYDM_ADC_MAC_TRIG = 1, + PHYDM_ADC_RF0_TRIG = 2, + PHYDM_ADC_RF1_TRIG = 3, + PHYDM_MAC_TRIG = 4 +}; + +enum rt_adcsmp_trig_sig_sel { + ADCSMP_TRIG_CRCOK = 0, + ADCSMP_TRIG_CRCFAIL = 1, + ADCSMP_TRIG_CCA = 2, + ADCSMP_TRIG_REG = 3 +}; + +enum rt_adcsmp_state { + ADCSMP_STATE_IDLE = 0, + ADCSMP_STATE_SET = 1, + ADCSMP_STATE_QUERY = 2 +}; + +enum la_buff_mode { + ADCSMP_BUFF_HALF = 0, + ADCSMP_BUFF_ALL = 1 /*Only use in MP Driver*/ +}; + +/* @ ============================================================ + * structure + * ============================================================ + */ + +struct rt_adcsmp_string { + u32 *octet; + u32 length; + u32 buffer_size; + u32 start_pos; + u32 end_pos; /*@buf addr*/ +}; + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +struct la_adv_trig { + boolean la_adv_bbtrigger_en; + boolean la_ori_bb_dis; + u8 la_and1_sel; + u8 la_and1_val; + boolean la_and1_inv; + u8 la_and2_sel; + u8 la_and2_val; + boolean la_and2_inv; + u8 la_and3_sel; + u8 la_and3_val; + boolean la_and3_inv; + u32 la_and4_mask; + u32 la_and4_bitmap; + boolean la_and4_inv; +}; +#endif + +struct rt_adcsmp { + struct rt_adcsmp_string adc_smp_buf; + enum rt_adcsmp_state adc_smp_state; + enum la_buff_mode la_buff_mode; + enum la_dump_mode la_dump_mode; + u8 la_trig_mode; + u32 la_trig_sig_sel; + u8 la_dma_type; + u32 la_trigger_time; + /*@1.BB mode: Dbg port header sel, 2.MAC mode: for reference mask*/ + u32 la_mac_mask_or_hdr_sel; + u32 la_dbg_port; + u8 la_trigger_edge; + u8 la_smp_rate; + u32 la_count; + u32 smp_number; + u32 smp_number_max; + u32 txff_page; + boolean is_la_print; + boolean en_fake_trig; +#if (RTL8197F_SUPPORT) + u32 backup_dma; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 la_work_item_index; + RT_WORK_ITEM adc_smp_work_item; + RT_WORK_ITEM adc_smp_work_item_1; +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + struct la_adv_trig adv_trig_table; +#endif +}; + +/* @ ============================================================ + * Function Prototype + * ============================================================ + */ + +void phydm_la_set(void *dm_void); + +void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); + +void phydm_la_stop(void *dm_void); + +void phydm_la_init(void *dm_void); + +void adc_smp_de_init(void *dm_void); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +void adc_smp_work_item_callback(void *context); +#endif +#endif +#endif diff --git a/hal/phydm/phydm_antdect.c b/hal/phydm/phydm_antdect.c new file mode 100644 index 0000000..a321389 --- /dev/null +++ b/hal/phydm/phydm_antdect.c @@ -0,0 +1,888 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CONFIG_ANT_DETECTION + +/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter) + * IS_ANT_DETECT_SUPPORT_RSSI(adapter) + * IS_ANT_DETECT_SUPPORT_PSD(adapter) */ + +/* @1 [1. Single Tone method] =================================================== */ + +/*@ + * Description: + * Set Single/Dual Antenna default setting for products that do not do detection in advance. + * + * Added by Joseph, 2012.03.22 + * */ +void odm_sw_ant_div_construct_scan_chnl( + void *adapter, + u8 scan_chnl) +{ +} + +u8 odm_sw_ant_div_select_scan_chnl( + void *adapter) +{ + return 0; +} + +void odm_single_dual_antenna_default_setting( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + void *adapter = dm->adapter; + + u8 bt_ant_num = BT_GetPgAntNum(adapter); + /* Set default antenna A and B status */ + if (bt_ant_num == 2) { + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = true; + + } else if (bt_ant_num == 1) { + /* Set antenna A as default */ + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = false; + + } else + RT_ASSERT(false, ("Incorrect antenna number!!\n")); +} + +/* @2 8723A ANT DETECT + * + * Description: + * Implement IQK single tone for RF DPK loopback and BB PSD scanning. + * This function is cooperated with BB team Neil. + * + * Added by Roger, 2011.12.15 + * */ +boolean +odm_single_dual_antenna_detection( + void *dm_void, + u8 mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 current_channel, rf_loop_reg; + u8 n; + u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca; + u8 initial_gain = 0x5a; + u32 PSD_report_tmp; + u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0; + boolean is_result = true; + + PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__); + + if (!(dm->support_ic_type & ODM_RTL8723B)) + return is_result; + + /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ + if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter))) + return is_result; + + /* @1 Backup Current RF/BB Settings */ + + current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK); + if (dm->support_ic_type & ODM_RTL8723B) { + reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD); + reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD); + reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD); + reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29)); + odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1); + odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77); + odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */ + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */ + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0); + } + + ODM_delay_us(10); + + /* Store A path Register 88c, c08, 874, c50 */ + reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD); + regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD); + reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD); + regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + + /* Store AFE Registers */ + if (dm->support_ic_type & ODM_RTL8723B) + afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD); + + /* Set PSD 128 pts */ + odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */ + + /* To SET CH1 to do */ + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */ + + /* @AFE all on step */ + if (dm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016); + + /* @3 wire Disable */ + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0); + + /* @BB IQK setting */ + odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4); + odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000); + + /* @IQK setting tone@ 4.34Mhz */ + odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C); + odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00); + + /* Page B init */ + odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000); + odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000); + odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800); + odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f); + if (dm->support_ic_type & ODM_RTL8723B) { + odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016); + odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016); + } + odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain); + + /* @IQK Single tone start */ + odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000); + odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000); + odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000); + + ODM_delay_us(10000); + + /* PSD report of antenna A */ + PSD_report_tmp = 0x0; + for (n = 0; n < 2; n++) { + PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain); + if (PSD_report_tmp > ant_a_report) + ant_a_report = PSD_report_tmp; + } + + /* @change to Antenna B */ + if (dm->support_ic_type & ODM_RTL8723B) { + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); + } + + ODM_delay_us(10); + + /* PSD report of antenna B */ + PSD_report_tmp = 0x0; + for (n = 0; n < 2; n++) { + PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain); + if (PSD_report_tmp > ant_b_report) + ant_b_report = PSD_report_tmp; + } + + /* @Close IQK Single Tone function */ + odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000); + + /* @1 Return to antanna A */ + if (dm->support_ic_type & ODM_RTL8723B) { + /* @external DPDT */ + odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c); + + /* @internal S0/S1 */ + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930); + odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064); + } + + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c); + odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08); + odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40); + odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50); + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg); + + /* Reload AFE Registers */ + if (dm->support_ic_type & ODM_RTL8723B) + odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca); + + if (dm->support_ic_type & ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416, + ant_a_report); + PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416, + ant_b_report); + + /* @2 Test ant B based on ant A is ON */ + if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) { + u8 TH1 = 2, TH2 = 6; + + if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) { + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n", + __func__); + } else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) || + ((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) { + dm_swat_table->ANTA_ON = false; + dm_swat_table->ANTB_ON = false; + is_result = false; + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Need to check again\n", + __func__); + } else { + dm_swat_table->ANTA_ON = true; + dm_swat_table->ANTB_ON = false; + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Single Antenna\n", __func__); + } + dm->ant_detected_info.is_ant_detected = true; + dm->ant_detected_info.db_for_ant_a = ant_a_report; + dm->ant_detected_info.db_for_ant_b = ant_b_report; + dm->ant_detected_info.db_for_ant_o = ant_0_report; + + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n"); + is_result = false; + } + } + return is_result; +} + +/* @1 [2. Scan AP RSSI method] ================================================== */ + +boolean +odm_sw_ant_div_check_before_link( + void *dm_void) +{ +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + //PMGNT_INFO mgnt_info = &adapter->MgntInfo; + PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo); + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + s8 score = 0; + PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc; + u8 power_target_L = 9, power_target_H = 16; + u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff; + u16 index, counter = 0; + static u8 scan_channel; + u32 tmp_swas_no_link_bk_reg948; + + PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", + dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON); + + /* @if(HP id) */ + { + if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "8723B RSSI-based Antenna Detection is done\n"); + return false; + } + + if (dm->support_ic_type == ODM_RTL8723B) { + if (dm_swat_table->swas_no_link_bk_reg948 == 0xff) + dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH); + } + } + + if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast. //By YJ,120413 */ + /* The ODM structure is not initialized. */ + return false; + } + + /* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */ + if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter))) + return false; + else + PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n"); + + /* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */ + odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK); + if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) { + odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n", + __func__, mgnt_info->RFChangeInProgress, + hal_data->eRFPowerState); + + dm_swat_table->swas_no_link_state = 0; + + return false; + } else + odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK); + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n", + dm_swat_table->swas_no_link_state); + /* @1 Run AntDiv mechanism "Before Link" part. */ + if (dm_swat_table->swas_no_link_state == 0) { + /* @1 Prepare to do Scan again to check current antenna state. */ + + /* Set check state to next step. */ + dm_swat_table->swas_no_link_state = 1; + + /* @Copy Current Scan list. */ + mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc; + PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC); + + /* @Go back to scan function again. */ + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n", + __func__); + mgnt_info->ScanStep = 0; + mgnt_info->bScanAntDetect = true; + scan_channel = odm_sw_ant_div_select_scan_chnl(adapter); + + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (fat_tab->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); + else + odm_update_rx_idle_ant(dm, MAIN_ANT); + if (scan_channel == 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: No AP List Avaiable, Using ant(%s)\n", + __func__, + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "AUX_ANT" : "MAIN_ANT"); + + if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) { + dm_swat_table->ant_5g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + } else { + dm_swat_table->ant_2g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + } + return false; + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Change to %s for testing.\n", __func__, + ((fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT")); + } else if (dm->support_ic_type & (ODM_RTL8723B)) { + /*Switch Antenna to another one.*/ + + tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH); + + if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) { + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1); + dm_swat_table->cur_antenna = AUX_ANT; + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Reg[948]= (( %x )) was in wrong state\n", + tmp_swas_no_link_bk_reg948); + return false; + } + ODM_delay_us(10); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Change to (( %s-ant)) for testing.\n", + __func__, + (dm_swat_table->cur_antenna == MAIN_ANT) ? + "MAIN" : "AUX"); + } + + odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); + + return true; + } else { /* @dm_swat_table->swas_no_link_state == 1 */ + /* @1 ScanComple() is called after antenna swiched. */ + /* @1 Check scan result and determine which antenna is going */ + /* @1 to be used. */ + + PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n", + mgnt_info->tmpNumBssDesc); /* @debug for Dino */ + + for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) { + p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */ + p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */ + + if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: ERROR!! This shall not happen.\n", + __func__); + continue; + } + + if (dm->support_ic_type != ODM_RTL8723B) { + if (p_tmp_bss_desc->ChannelNumber == scan_channel) { + if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + + score++; + PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); + } else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) { + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + score--; + } else { + if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) { + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen); + PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n"); + } + } + } + } else { /* @8723B */ + if (p_tmp_bss_desc->ChannelNumber == scan_channel) { + PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber); + + if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */ + counter++; + tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); + +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */ +#endif + if (tmp_power_diff > max_power_diff) + max_power_diff = tmp_power_diff; + if (tmp_power_diff < min_power_diff) + min_power_diff = tmp_power_diff; +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */ +#endif + + PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS)); + } else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */ + counter++; + tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); + if (tmp_power_diff > max_power_diff) + max_power_diff = tmp_power_diff; + if (tmp_power_diff < min_power_diff) + min_power_diff = tmp_power_diff; + } else { /* Pow(Ant1) = Pow(Ant2) */ + if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */ + PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000); + if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) { + counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf); + PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf); + min_power_diff = 0; + } + } else + PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000); + } + } + } + } + + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) { + if (mgnt_info->NumBssDesc != 0 && score < 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Using ant(%s)\n", __func__, + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT"); + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "%s: Remain ant(%s)\n", __func__, + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "AUX_ANT" : "MAIN_ANT"); + + if (fat_tab->rx_idle_ant == MAIN_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); + else + odm_update_rx_idle_ant(dm, MAIN_ANT); + } + + if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) { + dm_swat_table->ant_5g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, + "dm_swat_table->ant_5g=%s\n", + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT"); + } else { + dm_swat_table->ant_2g = fat_tab->rx_idle_ant; + PHYDM_DBG(dm, DBG_ANT_DIV, + "dm_swat_table->ant_2g=%s\n", + (fat_tab->rx_idle_ant == MAIN_ANT) ? + "MAIN_ANT" : "AUX_ANT"); + } + } else if (dm->support_ic_type == ODM_RTL8723B) { + if (counter == 0) { + if (dm->dm_swat_table.pre_aux_fail_detec == false) { + dm->dm_swat_table.pre_aux_fail_detec = true; + dm->dm_swat_table.rssi_ant_dect_result = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n"); + + /* @3 [ Scan again ] */ + odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); + return true; + } else { /* pre_aux_fail_detec == true */ + /* @2 [ Single Antenna ] */ + dm->dm_swat_table.pre_aux_fail_detec = false; + dm->dm_swat_table.rssi_ant_dect_result = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__); + } + dm->dm_swat_table.aux_fail_detec_counter++; + } else { + dm->dm_swat_table.pre_aux_fail_detec = false; + + if (counter == 3) { + avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2); + PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff); + } else if (counter >= 4) { + avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2); + PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff); + + } else { /* @counter==1,2 */ + avg_power_diff = power_diff / counter; + PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff); + } + + /* @2 [ Retry ] */ + if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) { + dm->dm_swat_table.retry_counter++; + + if (dm->dm_swat_table.retry_counter <= 3) { + dm->dm_swat_table.rssi_ant_dect_result = false; + PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff); + + /* @3 [ Scan again ] */ + odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel); + PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5); + return true; + } else { + dm->dm_swat_table.rssi_ant_dect_result = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__); + } + } + /* @2 [ Dual Antenna ] */ + else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) { + dm->dm_swat_table.rssi_ant_dect_result = true; + if (dm->dm_swat_table.ANTB_ON == false) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = true; + } + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__); + dm->dm_swat_table.dual_ant_counter++; + + /* set bt coexDM from 1ant coexDM to 2ant coexDM */ + BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); + + /* @3 [ Init antenna diversity ] */ + dm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(dm); + } + /* @2 [ Single Antenna ] */ + else if (avg_power_diff > power_target_H) { + dm->dm_swat_table.rssi_ant_dect_result = true; + if (dm->dm_swat_table.ANTB_ON == true) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = false; +#if 0 + /* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */ +#endif + } + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__); + dm->dm_swat_table.single_ant_counter++; + } + } +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */ +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n", + dm->dm_swat_table.dual_ant_counter, + dm->dm_swat_table.single_ant_counter, + dm->dm_swat_table.retry_counter, + dm->dm_swat_table.aux_fail_detec_counter); + + /* @2 recover the antenna setting */ + + if (dm->dm_swat_table.ANTB_ON == false) + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948)); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n", + dm->dm_swat_table.rssi_ant_dect_result, + dm_swat_table->swas_no_link_bk_reg948); + } + + /* @Check state reset to default and wait for next time. */ + dm_swat_table->swas_no_link_state = 0; + mgnt_info->bScanAntDetect = false; + + return false; + } + +#else + return false; +#endif + + return false; +} + +/* @1 [3. PSD method] ========================================================== */ +void odm_single_dual_antenna_detection_psd( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 channel_ori; + u8 initial_gain = 0x36; + u8 tone_idx; + u8 tone_lenth_1 = 7, tone_lenth_2 = 4; + u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56}; + u16 tone_idx_2[4] = {8, 24, 40, 56}; + u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0}; + /* u8 tone_lenth_1=4, tone_lenth_2=2; */ + /* u16 tone_idx_1[4]={88, 120, 24, 56}; */ + /* u16 tone_idx_2[2]={ 24, 56}; */ + /* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */ + + u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0; + u32 PSD_power_threshold; + u32 main_psd_result = 0, aux_psd_result = 0; + u32 regc50, reg948, regb2c, regc14, reg908; + u32 i = 0, test_num = 8; + + if (dm->support_ic_type != ODM_RTL8723B) + return; + + PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__); + + /* @2 [ Backup Current RF/BB Settings ] */ + + channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK); + reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD); + regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD); + regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD); + regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD); + reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD); + + /* @2 [ setting for doing PSD function (CH4)] */ + odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */ + odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */ + odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ + + /* PHYTXON while loop */ + odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803); + while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) { + i++; + if (i > 1000000) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Wait in %s() more than %d times!\n", + __FUNCTION__, i); + break; + } + } + + odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain); + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */ + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */ + odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */ + ODM_delay_us(3000); + + /* @2 [ Doing PSD Function in (CH4)] */ + + /* @Antenna A */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200); + ODM_delay_us(10); + PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n"); + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_main[tone_idx] ) */ + psd_report_main[tone_idx] += PSD_report_temp; + } + } + /* @Antenna B */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280); + ODM_delay_us(10); + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */ + psd_report_aux[tone_idx] += PSD_report_temp; + } + } + /* @2 [ Doing PSD Function in (CH8)] */ + + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */ + ODM_delay_us(3000); + + odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain); + odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */ + + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */ + ODM_delay_us(3000); + + /* @Antenna A */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200); + ODM_delay_us(10); + + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_main[tone_idx] ) */ + psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp; + } + } + + /* @Antenna B */ + PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n"); + odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280); + ODM_delay_us(10); + + for (i = 0; i < test_num; i++) { + for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) { + PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain); + /* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */ + psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp; + } + } + + /* @2 [ Calculate Result ] */ + + PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n"); + for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), + psd_report_main[tone_idx]); + main_psd_result += psd_report_main[tone_idx]; + if (psd_report_main[tone_idx] > max_psd_report_main) + max_psd_report_main = psd_report_main[tone_idx]; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "--------------------------- \nTotal_Main= (( %d ))\n", + main_psd_result); + PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n", + max_psd_report_main); + + PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n"); + for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1), + psd_report_aux[tone_idx]); + aux_psd_result += psd_report_aux[tone_idx]; + if (psd_report_aux[tone_idx] > max_psd_report_aux) + max_psd_report_aux = psd_report_aux[tone_idx]; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "--------------------------- \nTotal_Aux= (( %d ))\n", + aux_psd_result); + PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n", + max_psd_report_aux); + + /* @main_psd_result=main_psd_result-max_psd_report_main; */ + /* @aux_psd_result=aux_psd_result-max_psd_report_aux; */ + PSD_power_threshold = (main_psd_result * 7) >> 3; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", + main_psd_result, aux_psd_result, PSD_power_threshold); + + /* @3 [ Dual Antenna ] */ + if (aux_psd_result >= PSD_power_threshold) { + if (dm->dm_swat_table.ANTB_ON == false) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = true; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): Dual antenna\n"); + +#if 0 + /* set bt coexDM from 1ant coexDM to 2ant coexDM */ + /* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */ +#endif + + /* @Init antenna diversity */ + dm->support_ability |= ODM_BB_ANT_DIV; + odm_ant_div_init(dm); + } + /* @3 [ Single Antenna ] */ + else { + if (dm->dm_swat_table.ANTB_ON == true) { + dm->dm_swat_table.ANTA_ON = true; + dm->dm_swat_table.ANTB_ON = false; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_sw_ant_div_check_before_link(): Single antenna\n"); + } + + /* @2 [ Recover all parameters ] */ + + odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori); + odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */ + odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50); + + odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948); + odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c); + + odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */ + odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */ + odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */ + odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908); + + return; +} + +void odm_sw_ant_detect_init(void *dm_void) +{ +#if (RTL8723B_SUPPORT == 1) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + + if (dm->support_ic_type != ODM_RTL8723B) + return; + + /* @dm_swat_table->pre_antenna = MAIN_ANT; */ + /* @dm_swat_table->cur_antenna = MAIN_ANT; */ + dm_swat_table->swas_no_link_state = 0; + dm_swat_table->pre_aux_fail_detec = false; + dm_swat_table->swas_no_link_bk_reg948 = 0xff; + +#ifdef CONFIG_PSD_TOOL + phydm_psd_init(dm); +#endif +#endif +} +#endif + diff --git a/hal/phydm/phydm_antdect.h b/hal/phydm/phydm_antdect.h new file mode 100644 index 0000000..f7fc75f --- /dev/null +++ b/hal/phydm/phydm_antdect.h @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMANTDECT_H__ +#define __PHYDMANTDECT_H__ + +#define ANTDECT_VERSION "2.1" + +#if (defined(CONFIG_ANT_DETECTION)) +/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */ +/* @ANT Test */ +#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/ +#define ANTTESTA 0x01 /*@ant A will be Testing*/ +#define ANTTESTB 0x02 /*@ant B will be testing*/ + +#define MAX_ANTENNA_DETECTION_CNT 10 + +struct _ANT_DETECTED_INFO { + boolean is_ant_detected; + u32 db_for_ant_a; + u32 db_for_ant_b; + u32 db_for_ant_o; +}; + +enum dm_swas { + antenna_a = 1, + antenna_b = 2, + antenna_max = 3, +}; + +/* @1 [1. Single Tone method] =================================================== */ + +void odm_single_dual_antenna_default_setting( + void *dm_void); + +boolean +odm_single_dual_antenna_detection( + void *dm_void, + u8 mode); + +/* @1 [2. Scan AP RSSI method] ================================================== */ + +#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link + +boolean +odm_sw_ant_div_check_before_link( + void *dm_void); + +/* @1 [3. PSD method] ========================================================== */ + +void odm_single_dual_antenna_detection_psd( + void *dm_void); + +void odm_sw_ant_detect_init(void *dm_void); +#endif +#endif diff --git a/hal/phydm/phydm_antdiv.c b/hal/phydm/phydm_antdiv.c new file mode 100644 index 0000000..3c2cc58 --- /dev/null +++ b/hal/phydm/phydm_antdiv.c @@ -0,0 +1,6640 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/******************************************************* + * when antenna test utility is on or some testing need to disable antenna + * diversity call this function to disable all ODM related mechanisms which + * will switch antenna. + ***************************************************** + */ +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY +#if (RTL8710C_SUPPORT == 1) +void odm_s0s1_sw_ant_div_init_8710c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8710C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); + /*MAC setting*/ + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17 | BIT16); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x10, 0x307); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x08, 0x80000111); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1208, 0x800000); + + /* Status init */ + fat_tab->is_become_linked = false; + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->double_chk_flag = 0; + swat_tab->cur_antenna = MAIN_ANT; + swat_tab->pre_ant = MAIN_ANT; + dm->antdiv_counter = CONFIG_ANTDIV_PERIOD; +} + +void odm_trx_hw_ant_div_init_8710c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[8710C] AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV]\n"); + odm_set_mac_reg(dm, R_0x74, BIT(13) | BIT(12), 1); + odm_set_mac_reg(dm, R_0x74, BIT(4), 1); + + /*@BT Coexistence*/ + /*@keep antsel_map when GNT_BT = 1*/ + odm_set_bb_reg(dm, R_0x864, BIT(12), 1); + + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 1); + odm_set_bb_reg(dm, R_0x930, 0xF00, 8); /* RFE CTRL_2 ANTSEL0 */ + + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); + odm_set_bb_reg(dm, R_0x804, BIT(8), 0); /* r_keep_rfpin */ + + /*@Mapping Table*/ + //odm_set_bb_reg(dm, R_0x864, BIT2|BIT1|BIT0, 2); + odm_set_bb_reg(dm, R_0x944, 0xFFFF, 0xffff); + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); + /*@antenna training */ + odm_set_bb_reg(dm, R_0xe08, BIT(16), 0); + + //need to check!!!!!!!!!! + /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */ + odm_set_bb_reg(dm, R_0xccc, BIT(12), 0); + /* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01); + /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0); + /* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/ + odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06); + /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */ + odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00); + + /*OFDM HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0x80); + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); + odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04); + + /*@CCK HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0); + + odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf); + odm_set_bb_reg(dm, R_0xa14, 0x1F, 0xf); + odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1); +} +void odm_update_rx_idle_ant_8710c(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***odm_update_rx_idle_ant_8710c!!!\n"); + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + if (default_ant == 0x0) + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1210,0x800000); + else + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1214,0x800000); + + fat_tab->rx_idle_ant = ant; + }else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); + /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); + /*@Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); + /*@Default TX*/ + fat_tab->rx_idle_ant = ant; + } +} +#endif + +#if (RTL8721D_SUPPORT == 1) + +void odm_update_rx_idle_ant_8721d(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); + /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); + /*@Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); + /*@Default TX*/ + fat_tab->rx_idle_ant = ant; +} + +void odm_trx_hw_ant_div_init_8721d(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[8721D] AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV]\n"); + + /*@BT Coexistence*/ + /*@keep antsel_map when GNT_BT = 1*/ + odm_set_bb_reg(dm, R_0x864, BIT(12), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 0); + /* @Disable hw antsw & fast_train.antsw when BT TX/RX */ + odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c); + + switch (dm->antdiv_gpio) { + case ANTDIV_GPIO_PA2PA4: { + PAD_CMD(_PA_2, ENABLE); + Pinmux_Config(_PA_2, PINMUX_FUNCTION_RFE); + PAD_CMD(_PA_4, ENABLE); + Pinmux_Config(_PA_4, PINMUX_FUNCTION_RFE); + break; + } + case ANTDIV_GPIO_PA5PA6: { + PAD_CMD(_PA_5, ENABLE); + Pinmux_Config(_PA_5, PINMUX_FUNCTION_RFE); + PAD_CMD(_PA_6, ENABLE); + Pinmux_Config(_PA_6, PINMUX_FUNCTION_RFE); + break; + } + case ANTDIV_GPIO_PA12PA13: { + PAD_CMD(_PA_12, ENABLE); + Pinmux_Config(_PA_12, PINMUX_FUNCTION_RFE); + PAD_CMD(_PA_13, ENABLE); + Pinmux_Config(_PA_13, PINMUX_FUNCTION_RFE); + break; + } + case ANTDIV_GPIO_PA14PA15: { + PAD_CMD(_PA_14, ENABLE); + Pinmux_Config(_PA_14, PINMUX_FUNCTION_RFE); + PAD_CMD(_PA_15, ENABLE); + Pinmux_Config(_PA_15, PINMUX_FUNCTION_RFE); + break; + } + case ANTDIV_GPIO_PA16PA17: { + PAD_CMD(_PA_16, ENABLE); + Pinmux_Config(_PA_16, PINMUX_FUNCTION_RFE); + PAD_CMD(_PA_17, ENABLE); + Pinmux_Config(_PA_17, PINMUX_FUNCTION_RFE); + break; + } + case ANTDIV_GPIO_PB1PB2: { + PAD_CMD(_PB_1, ENABLE); + Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE); + PAD_CMD(_PB_2, ENABLE); + Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE); + break; + } + case ANTDIV_GPIO_PB26PB29: { + PAD_CMD(_PB_26, ENABLE); + Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE); + PAD_CMD(_PB_29, ENABLE); + Pinmux_Config(_PB_29, PINMUX_FUNCTION_RFE); + break; + } + case ANTDIV_GPIO_PB1PB2PB26:{ + PAD_CMD(_PB_1, ENABLE); + Pinmux_Config(_PB_1, PINMUX_FUNCTION_RFE); + PAD_CMD(_PB_2, ENABLE); + Pinmux_Config(_PB_2, PINMUX_FUNCTION_RFE); + PAD_CMD(_PB_26, ENABLE); + Pinmux_Config(_PB_26, PINMUX_FUNCTION_RFE); + break; + } + default: { + } + } + + if (dm->antdiv_gpio == ANTDIV_GPIO_PA12PA13 || + dm->antdiv_gpio == ANTDIV_GPIO_PA14PA15 || + dm->antdiv_gpio == ANTDIV_GPIO_PA16PA17 || + dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2) { + /* ANT_SEL_P, ANT_SEL_N */ + odm_set_bb_reg(dm, R_0x930, 0xF, 8); + odm_set_bb_reg(dm, R_0x930, 0xF0, 8); + odm_set_bb_reg(dm, R_0x92c, BIT(1) | BIT(0), 2); + odm_set_bb_reg(dm, R_0x944, 0x00000003, 0x3); + } else if (dm->antdiv_gpio == ANTDIV_GPIO_PA2PA4 || + dm->antdiv_gpio == ANTDIV_GPIO_PA5PA6 || + dm->antdiv_gpio == ANTDIV_GPIO_PB26PB29) { + /* TRSW_P, TRSW_N */ + odm_set_bb_reg(dm, R_0x930, 0xF00, 8); + odm_set_bb_reg(dm, R_0x930, 0xF000, 8); + odm_set_bb_reg(dm, R_0x92c, BIT(3) | BIT(2), 2); + odm_set_bb_reg(dm, R_0x944, 0x0000000C, 0x3); + } + else if(dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26){ + /* 3 antenna diversity for AmebaD only */ + odm_set_bb_reg(dm, R_0x930, 0xF, 8); + odm_set_bb_reg(dm, R_0x930, 0xF0, 9); + odm_set_bb_reg(dm, R_0x930, 0xF00,0xa); /* set the RFE control table to select antenna*/ + odm_set_bb_reg(dm, R_0x944, 0x00000007, 0x7); + } + + u32 sysreg208 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0); + + sysreg208 |= BIT(28); + HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_FUNC_EN0, sysreg208); + + u32 sysreg344 = + HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL); + + sysreg344 |= BIT(9); + HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344); + + u32 sysreg280 = HAL_READ32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0); + + sysreg280 |= 0x7; + HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_LP_SYSPLL_CTRL0, sysreg280); + + sysreg344 |= BIT(8); + HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344); + + sysreg344 |= BIT(0); + HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_AUDIO_SHARE_PAD_CTRL, sysreg344); + + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x804, 0xF00, 1); /* r_keep_rfpin */ + + /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ + /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/ + /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/ + /*@GNT_WL tx*/ + odm_set_bb_reg(dm, R_0x950, BIT(29), 0); + + /*@Mapping Table*/ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); + if (dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) { + odm_set_bb_reg(dm, R_0x914, 0x00000F, 0x1); + odm_set_bb_reg(dm, R_0x914, 0x000F00, 0x2); + odm_set_bb_reg(dm, R_0x914, 0x0F0000, 0x4); + } + /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */ + /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */ + + /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */ + odm_set_bb_reg(dm, R_0xccc, BIT(12), 0); + /* @Low-to-High threshold for WLBB_SEL_RF_ON */ + /*when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01); + /* @High-to-Low threshold for WLBB_SEL_RF_ON */ + /* when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0); + /* @b Low-to-High threshold for WLBB_SEL_RF_ON*/ + /*when OFDM disable ( only CCK ) */ + odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06); + /* @High-to-Low threshold for WLBB_SEL_RF_ON*/ + /* when OFDM disable ( only CCK ) */ + odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00); + + /*OFDM HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); + odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04); + + /*@CCK HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 0); + odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0); + + odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf); + odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8); + odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1); + + /*@disable antenna training */ + odm_set_bb_reg(dm, R_0xe08, BIT(16), 0); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); +} +#endif + +void odm_stop_antenna_switch_dm(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + /* @disable ODM antenna diversity */ + dm->support_ability &= ~ODM_BB_ANT_DIV; +#if (RTL8710C_SUPPORT == 1) + dm->support_ability |= ODM_BB_ANT_DIV; +#endif + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n"); +} + +void phydm_enable_antenna_diversity(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + dm->support_ability |= ODM_BB_ANT_DIV; + dm->antdiv_select = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n"); + odm_antenna_diversity_init(dm); +} + +void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,...*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type == ODM_RTL8723B) { + if (ant_setting == 0) /* @ant A*/ + odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000); + else if (ant_setting == 1) + odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280); + } else if (dm->support_ic_type == ODM_RTL8723D) { + if (ant_setting == 0) /* @ant A*/ + odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000); + else if (ant_setting == 1) + odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280); + } +} + +/* ****************************************************** */ + +void odm_sw_ant_div_rest_after_link(void *dm_void) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 i; + + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->rssi_trying = 0; + swat_tab->double_chk_flag = 0; + fat_tab->rx_idle_ant = MAIN_ANT; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + phydm_antdiv_reset_statistic(dm, i); + } + +#endif +} + +void phydm_n_on_off(void *dm_void, u8 swch, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (path == ANT_PATH_A) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + } else if (path == ANT_PATH_B) { + odm_set_bb_reg(dm, R_0xc58, BIT(7), swch); + } else if (path == ANT_PATH_AB) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + odm_set_bb_reg(dm, R_0xc58, BIT(7), swch); + } + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); +#if (RTL8723D_SUPPORT == 1) + /*@Mingzhi 2017-05-08*/ + if (dm->support_ic_type == ODM_RTL8723D) { + if (swch == ANTDIV_ON) { + odm_set_bb_reg(dm, R_0xce0, BIT(1), 1); + odm_set_bb_reg(dm, R_0x948, BIT(6), 1); + /*@1:HW ctrl 0:SW ctrl*/ + } else { + odm_set_bb_reg(dm, R_0xce0, BIT(1), 0); + odm_set_bb_reg(dm, R_0x948, BIT(6), 0); + /*@1:HW ctrl 0:SW ctrl*/ + } + } +#endif +} + +void phydm_ac_on_off(void *dm_void, u8 swch, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (dm->support_ic_type & ODM_RTL8812) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + /* OFDM AntDiv function block enable */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + /* @CCK AntDiv function block enable */ + } else if (dm->support_ic_type & ODM_RTL8822B) { + odm_set_bb_reg(dm, R_0x800, BIT(25), swch); + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + if (path == ANT_PATH_A) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + } else if (path == ANT_PATH_B) { + odm_set_bb_reg(dm, R_0xe50, BIT(7), swch); + } else if (path == ANT_PATH_AB) { + odm_set_bb_reg(dm, R_0xc50, BIT(7), swch); + odm_set_bb_reg(dm, R_0xe50, BIT(7), swch); + } + } else { + odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch); + /* OFDM AntDiv function block enable */ + + if (dm->cut_version >= ODM_CUT_C && + dm->support_ic_type == ODM_RTL8821 && + dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + odm_set_bb_reg(dm, R_0x800, BIT(25), swch); + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + /* @CCK AntDiv function block enable */ + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + odm_set_bb_reg(dm, R_0x800, BIT(25), swch); + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + /* @CCK AntDiv function block enable */ + } + } +} + +void phydm_jgr3_on_off(void *dm_void, u8 swch, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + odm_set_bb_reg(dm, R_0x8a0, BIT(17), swch); + /* OFDM AntDiv function block enable */ + if (dm->support_ic_type & ODM_RTL8723F) { + odm_set_bb_reg(dm, R_0x1a48, BIT(16), swch); + /* @CCK AntDiv function block enable */ + } + else{ + odm_set_bb_reg(dm, R_0xa00, BIT(15), swch); + /* @CCK AntDiv function block enable */ + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "[8723F] AntDiv_on\n"); +} + +void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (fat_tab->ant_div_on_off != swch) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) + return; + + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "(( Turn %s )) N-Series HW-AntDiv block\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + phydm_n_on_off(dm, swch, path); + + } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "(( Turn %s )) AC-Series HW-AntDiv block\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + phydm_ac_on_off(dm, swch, path); + } else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "(( Turn %s )) JGR3 HW-AntDiv block\n", + (swch == ANTDIV_ON) ? "ON" : "OFF"); + phydm_jgr3_on_off(dm, swch, path); + } + } + fat_tab->ant_div_on_off = swch; +} + +void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 enable; + + if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT) + enable = (swch == TX_BY_DESC) ? 1 : 0; + else + enable = 0; /*@Force TX by Reg*/ + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0x80c, BIT(21), enable); + else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0x900, BIT(18), enable); + else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0x186c, BIT(1), enable); + + PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n", + (enable == TX_BY_DESC) ? "DESC" : "REG"); + } +} + +void phydm_antdiv_reset_statistic(void *dm_void, u32 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + fat_tab->main_sum[macid] = 0; + fat_tab->aux_sum[macid] = 0; + fat_tab->main_cnt[macid] = 0; + fat_tab->aux_cnt[macid] = 0; + fat_tab->main_sum_cck[macid] = 0; + fat_tab->aux_sum_cck[macid] = 0; + fat_tab->main_cnt_cck[macid] = 0; + fat_tab->aux_cnt_cck[macid] = 0; +} + +void phydm_fast_training_enable(void *dm_void, u8 swch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 enable; + + if (swch == FAT_ON) + enable = 1; + else + enable = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable); + + if (dm->support_ic_type == ODM_RTL8188E) { + odm_set_bb_reg(dm, R_0xe08, BIT(16), enable); + /*@enable fast training*/ + } else if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, R_0xb34, BIT(28), enable); + /*@enable fast training (path-A)*/ +#if 0 + odm_set_bb_reg(dm, R_0xb34, BIT(29), enable); + /*enable fast training (path-B)*/ +#endif + } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) { + odm_set_bb_reg(dm, R_0x900, BIT(19), enable); + /*@enable fast training */ + } +} + +void phydm_keep_rx_ack_ant_by_tx_ant_time(void *dm_void, u32 time) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/ + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0xe20, 0xf00000, time); + else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) + odm_set_bb_reg(dm, R_0x818, 0xf00000, time); + if (dm->support_ic_type & ODM_RTL8723F) { + odm_set_bb_reg(dm, R_0x1c8c, 0xf00, time); + /* keep antenna index after tx */ + } + + +} + +void phydm_update_rx_idle_ac(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant, u32 default_tx_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2); + /* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to */ + /* @prevnt incorrect 0xc08 bit0-15.We still not know why it is changed*/ + value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | + BIT(5) | BIT(4) | BIT(3)); + value16 |= ((u16)default_ant << 3); + value16 |= ((u16)optional_ant << 6); + value16 |= ((u16)default_tx_ant << 9); + odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16); +#if 0 + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x380000, default_ant); + /* @Default RX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0x1c00000, optional_ant); + /* Optional RX */ + odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, 0xe000000, default_ant); + /* @Default TX */ +#endif +} + +void phydm_update_rx_idle_n(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant, u32 default_tx_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32; + + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) { + odm_set_bb_reg(dm, R_0xb38, 0x38, default_ant); + /* @Default RX */ + odm_set_bb_reg(dm, R_0xb38, 0x1c0, optional_ant); + /* Optional RX */ + odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant); + /* @Default TX */ +#if (RTL8723B_SUPPORT == 1) + } else if (dm->support_ic_type == ODM_RTL8723B) { + value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF); + + if (value32 != 0x280) + odm_update_rx_idle_ant_8723b(dm, ant, default_ant, + optional_ant); + else + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"); +#endif + +#if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/ + } else if (dm->support_ic_type == ODM_RTL8723D) { + phydm_set_tx_ant_pwr_8723d(dm, ant); + odm_update_rx_idle_ant_8723d(dm, ant, default_ant, + optional_ant); +#endif + +#if (RTL8721D_SUPPORT == 1) + } else if (dm->support_ic_type == ODM_RTL8721D) { + odm_update_rx_idle_ant_8721d(dm, ant, default_ant, + optional_ant); +#endif + +#if (RTL8710C_SUPPORT == 1) + } else if (dm->support_ic_type == ODM_RTL8710C) { + odm_update_rx_idle_ant_8710c(dm, ant, default_ant, + optional_ant); +#endif + + } else { +/*@8188E & 8188F*/ +/*@ if (dm->support_ic_type == ODM_RTL8723D) {*/ +/*#if (RTL8723D_SUPPORT == 1)*/ +/* phydm_set_tx_ant_pwr_8723d(dm, ant);*/ +/*#endif*/ +/* }*/ +#if (RTL8188F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188F) + phydm_update_rx_idle_antenna_8188F(dm, default_ant); +#endif + + odm_set_bb_reg(dm, R_0x864, 0x38, default_ant);/*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant); + /*Optional RX*/ + odm_set_bb_reg(dm, R_0x860, 0x7000, default_tx_ant); + /*@Default TX*/ + } +} + +void phydm_update_rx_idle_jgr3(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant, u32 default_tx_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32; + + odm_set_bb_reg(dm, R_0x1884, 0xf0, default_ant);/*@Default RX*/ + odm_set_bb_reg(dm, R_0x1884, 0xf00, optional_ant); + /*Optional RX*/ + odm_set_bb_reg(dm, R_0x1884, 0xf000, default_tx_ant); + /*@Default TX*/ +} +void odm_update_rx_idle_ant(void *dm_void, u8 ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 default_ant, optional_ant, value32, default_tx_ant; + if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) { + PHYDM_DBG(dm, DBG_ANT_DIV,"JGR3 HW-AntDiv block\n"); + } + else{ + PHYDM_DBG(dm, DBG_ANT_DIV,"not suppoty JGR3 HW-AntDiv block\n"); + PHYDM_DBG(dm, DBG_ANT_DIV,"dm->support_ic_type=%d\n",dm->support_ic_type); +} + if (fat_tab->rx_idle_ant != ant) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + if (!(dm->support_ic_type & ODM_RTL8723B)) + fat_tab->rx_idle_ant = ant; + + if (ant == MAIN_ANT) { + default_ant = ANT1_2G; + optional_ant = ANT2_2G; + } else { + default_ant = ANT2_2G; + optional_ant = ANT1_2G; + } + + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + default_tx_ant = (fat_tab->b_fix_tx_ant == + FIX_TX_AT_MAIN) ? 0 : 1; + else + default_tx_ant = default_ant; + + if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) { + phydm_update_rx_idle_n(dm, ant, default_ant, + optional_ant, default_tx_ant); + } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) { + phydm_update_rx_idle_ac(dm, ant, default_ant, + optional_ant, default_tx_ant); + } else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) { + phydm_update_rx_idle_jgr3(dm, ant, default_ant, + optional_ant, default_tx_ant); + } + /*PathA Resp Tx*/ + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | + ODM_RTL8814A | ODM_RTL8195B)) + odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant); + else if (dm->support_ic_type == ODM_RTL8188E) + odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant); + else if (dm->support_ic_type & ODM_JGR3_ANTDIV_SUPPORT) + odm_set_mac_reg(dm, R_0x6f8, 0xf, default_tx_ant); + else + odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant); + + } else { /* @fat_tab->rx_idle_ant == ant */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Stay in Ori-ant ] rx_idle_ant =%s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + fat_tab->rx_idle_ant = ant; + } +} + +#if (RTL8721D_SUPPORT) +void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant) /* added by Jiao Qi on May.25,2020, for AmebaD SP3T only */ +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 default_ant, optional_ant, value32, default_tx_ant; + + if (!(dm->support_ic_type & ODM_RTL8723B)) + fat_tab->rx_idle_ant = ant; + + default_ant = fat_tab->ant_idx_vec[0]-1; + optional_ant = fat_tab->ant_idx_vec[1]-1; + + if(fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + default_tx_ant = (fat_tab->b_fix_tx_ant == + FIX_TX_AT_MAIN) ? 0 : 1; + else + default_tx_ant = default_ant; + + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); + /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); + /*@Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); + /*@Default TX*/ + + /*PathA Resp Tx*/ + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | + ODM_RTL8814A)) + odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant); + else if (dm->support_ic_type == ODM_RTL8188E) + odm_set_mac_reg(dm, R_0x6d8, 0xc0, default_tx_ant); + else + odm_set_mac_reg(dm, R_0x6d8, 0x700, default_tx_ant); + +} +#endif +void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 default_ant, optional_ant, value32, default_tx_ant; + + if (fat_tab->rx_idle_ant2 != ant) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + if (ant == MAIN_ANT) { + default_ant = ANT1_2G; + optional_ant = ANT2_2G; + } else { + default_ant = ANT2_2G; + optional_ant = ANT1_2G; + } + + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + default_tx_ant = (fat_tab->b_fix_tx_ant == + FIX_TX_AT_MAIN) ? 0 : 1; + else + default_tx_ant = default_ant; + if (dm->support_ic_type & ODM_RTL8822B) { + u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2); + + v16 &= ~(0xff8);/*0xE08[11:3]*/ + v16 |= ((u16)default_ant << 3); + v16 |= ((u16)optional_ant << 6); + v16 |= ((u16)default_tx_ant << 9); + odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16); + odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant); + /*PathB Resp Tx*/ + } + } else { + /* fat_tab->rx_idle_ant2 == ant */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n", + (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + fat_tab->rx_idle_ant2 = ant; + } +} + +void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n"); + return; + } + + odm_update_rx_idle_ant(dm, (u8)(*val_buf)); +} + +void odm_update_tx_ant(void *dm_void, u8 ant, u32 mac_id) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 tx_ant; + + if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT) + ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? + MAIN_ANT : AUX_ANT; + + if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + tx_ant = ant; + else { + if (ant == MAIN_ANT) + tx_ant = ANT1_2G; + else + tx_ant = ANT2_2G; + } +#if (RTL8721D_SUPPORT) + if (dm->antdiv_gpio != ANTDIV_GPIO_PB1PB2PB26) { + if (ant == MAIN_ANT) + tx_ant = ANT1_2G; + else + tx_ant = ANT2_2G; + } + else + tx_ant = fat_tab->ant_idx_vec[0]-1; +#endif + fat_tab->antsel_a[mac_id] = tx_ant & BIT(0); + fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1; + fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Set TX-DESC value]: mac_id:(( %d )), tx_ant = (( %s ))\n", + mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); +#if 0 + PHYDM_DBG(dm, DBG_ANT_DIV, + "antsel_tr_mux=(( 3'b%d%d%d ))\n", + fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], + fat_tab->antsel_a[mac_id]); +#endif +} + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +void odm_bdc_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n"); + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_mode = BDC_MODE_NULL; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->bd_ccoex_type_wbfer = 0; + dm->bdc_holdstate = 0xff; + + if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008); + odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0); + } else if (dm->support_ic_type == ODM_RTL8812) { + odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008); + /* @0x9b0[30:0] = 01081008 */ + odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0); + /* @0x9b4[31:0] = 00000000 */ + } +} + +void odm_CSI_on_off( + void *dm_void, + u8 CSI_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + if (CSI_en == CSI_ON) { + if (dm->support_ic_type == ODM_RTL8192E) + odm_set_mac_reg(dm, R_0xd84, BIT(11), 1); + /* @0xd84[11]=1 */ + else if (dm->support_ic_type == ODM_RTL8812) + odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1); + /* @0x9b0[31]=1 */ + + } else if (CSI_en == CSI_OFF) { + if (dm->support_ic_type == ODM_RTL8192E) + odm_set_mac_reg(dm, R_0xd84, BIT(11), 0); + /* @0xd84[11]=0 */ + else if (dm->support_ic_type == ODM_RTL8812) + odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0); + /* @0x9b0[31]=0 */ + } +} + +void odm_bd_ccoex_type_with_bfer_client( + void *dm_void, + u8 swch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u8 bd_ccoex_type_wbfer; + + if (swch == DIVON_CSIOFF) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n"); + bd_ccoex_type_wbfer = 1; + + if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + odm_CSI_on_off(dm, CSI_OFF); + dm_bdc_table->bd_ccoex_type_wbfer = 1; + } + } else if (swch == DIVOFF_CSION) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n"); + bd_ccoex_type_wbfer = 2; + + if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + odm_CSI_on_off(dm, CSI_ON); + dm_bdc_table->bd_ccoex_type_wbfer = 2; + } + } +} + +void odm_bf_ant_div_mode_arbitration( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u8 current_bdc_mode; + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + PHYDM_DBG(dm, DBG_ANT_DIV, "\n"); + + /* @2 mode 1 */ + if (dm_bdc_table->num_txbfee_client != 0 && + dm_bdc_table->num_txbfer_client == 0) { + current_bdc_mode = BDC_MODE_1; + + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_1; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + dm_bdc_table->bdc_rx_idle_update_counter = 1; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n"); + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode1 ))\n"); + } + /* @2 mode 2 */ + else if ((dm_bdc_table->num_txbfee_client == 0) && + (dm_bdc_table->num_txbfer_client != 0)) { + current_bdc_mode = BDC_MODE_2; + + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_2; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_try_flag = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n"); + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode2 ))\n"); + } + /* @2 mode 3 */ + else if ((dm_bdc_table->num_txbfee_client != 0) && + (dm_bdc_table->num_txbfer_client != 0)) { + current_bdc_mode = BDC_MODE_3; + + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_3; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->bdc_rx_idle_update_counter = 1; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n"); + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode3 ))\n"); + } + /* @2 mode 4 */ + else if ((dm_bdc_table->num_txbfee_client == 0) && + (dm_bdc_table->num_txbfer_client == 0)) { + current_bdc_mode = BDC_MODE_4; + + if (current_bdc_mode != dm_bdc_table->bdc_mode) { + dm_bdc_table->bdc_mode = BDC_MODE_4; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n"); + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Antdiv + BF coextance mode] : (( Mode4 ))\n"); + } +#endif +} + +void odm_div_train_state_setting( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE]\n"); + dm_bdc_table->bdc_try_counter = 2; + dm_bdc_table->bdc_try_flag = 1; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); +} + +void odm_bd_ccoex_bfee_rx_div_arbitration( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + boolean stop_bf_flag; + u8 bdc_active_mode; + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***{ num_BFee, num_BFer, num_client} = (( %d , %d , %d))\n", + dm_bdc_table->num_txbfee_client, + dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client); + PHYDM_DBG(dm, DBG_ANT_DIV, + "***{ num_BF_tars, num_DIV_tars } = (( %d , %d ))\n", + dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar); + + /* @2 [ MIB control ] */ + if (dm->bdc_holdstate == 2) { + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n"); + return; + } else if (dm->bdc_holdstate == 1) { + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n"); + return; + } + + /* @------------------------------------------------------------ */ + + /* @2 mode 2 & 3 */ + if (dm_bdc_table->bdc_mode == BDC_MODE_2 || + dm_bdc_table->bdc_mode == BDC_MODE_3) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "\n{ Try_flag, Try_counter } = { %d , %d }\n", + dm_bdc_table->bdc_try_flag, + dm_bdc_table->bdc_try_counter); + PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n", + dm_bdc_table->bd_ccoex_type_wbfer); + + /* @All Client have Bfer-Cap------------------------------- */ + if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) { + /* @BFer STA Only?: yes */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "BFer STA only? (( Yes ))\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + return; + } else + PHYDM_DBG(dm, DBG_ANT_DIV, + "BFer STA only? (( No ))\n"); + if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "All DIV-STA are idle, but BF-STA not\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + return; + } else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "All BF-STA are idle, but DIV-STA not\n"); + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + return; + } + + /* Select active mode-------------------------------------- */ + if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1, Selsect_2 */ + if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 1 ))\n"); + dm_bdc_table->bdc_active_mode = 1; + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 2 ))\n"); + dm_bdc_table->bdc_active_mode = 2; + } + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + return; + } else { /* num_bf_tar > 0 */ + if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 3 ))\n"); + dm_bdc_table->bdc_active_mode = 3; + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = bdc_bfer_train_state; + odm_bd_ccoex_type_with_bfer_client(dm, + DIVOFF_CSION) + ; + return; + } else { /* Selsect_4 */ + bdc_active_mode = 4; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Select active mode (( 4 ))\n"); + + if (bdc_active_mode != dm_bdc_table->bdc_active_mode) { + dm_bdc_table->bdc_active_mode = 4; + PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 )) & return!!!\n"); + return; + } + } + } + +#if 1 + if (dm->bdc_holdstate == 0xff) { + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n"); + return; + } +#endif + + /* @Does Client number changed ? ------------------------------- */ + if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) { + dm_bdc_table->bdc_try_flag = 0; + dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE ))\n"); + } + dm_bdc_table->pre_num_client = dm_bdc_table->num_client; + + if (dm_bdc_table->bdc_try_flag == 0) { + /* @2 DIV_TRAIN_STATE (mode 2-0) */ + if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE) + odm_div_train_state_setting(dm); + /* @2 BFer_TRAIN_STATE (mode 2-1) */ + else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-1. BFer_TRAIN_STATE ]*****\n"); + +#if 0 + /* @if(dm_bdc_table->num_bf_tar==0) */ + /* @{ */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */ + /* odm_div_train_state_setting( dm); */ + /* @} */ + /* else */ /* num_bf_tar != 0 */ + /* @{ */ +#endif + dm_bdc_table->bdc_try_counter = 2; + dm_bdc_table->bdc_try_flag = 1; + dm_bdc_table->BDC_state = BDC_DECISION_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + PHYDM_DBG(dm, DBG_ANT_DIV, + "BF_tars exist? : (( Yes )), [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n"); + /* @} */ + } + /* @2 DECISION_STATE (mode 2-2) */ + else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-2. DECISION_STATE]*****\n"); +#if 0 + /* @if(dm_bdc_table->num_bf_tar==0) */ + /* @{ */ + /* ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */ + /* odm_div_train_state_setting( dm); */ + /* @} */ + /* else */ /* num_bf_tar != 0 */ + /* @{ */ +#endif + if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false) + stop_bf_flag = true; + else + stop_bf_flag = false; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, stop_bf_flag } = { %d, %d, %d }\n", + dm_bdc_table->BF_pass, + dm_bdc_table->DIV_pass, stop_bf_flag); + + if (stop_bf_flag == true) { /* @DIV_en */ + dm_bdc_table->bdc_hold_counter = 10; /* @20 */ + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n"); + } else { /* @BF_en */ + dm_bdc_table->bdc_hold_counter = 10; /* @20 */ + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n"); + } + /* @} */ + } + /* @2 BF-HOLD_STATE (mode 2-3) */ + else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-3. BF_HOLD_STATE ]*****\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "bdc_hold_counter = (( %d ))\n", + dm_bdc_table->bdc_hold_counter); + + if (dm_bdc_table->bdc_hold_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); + odm_div_train_state_setting(dm); + } else { + dm_bdc_table->bdc_hold_counter--; + +#if 0 + /* @if(dm_bdc_table->num_bf_tar==0) */ + /* @{ */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */ + /* odm_div_train_state_setting( dm); */ + /* @} */ + /* else */ /* num_bf_tar != 0 */ + /* @{ */ + /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist? : (( Yes ))\n"); */ +#endif + dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n"); + /* @} */ + } + } + /* @2 DIV-HOLD_STATE (mode 2-4) */ + else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*****[2-4. DIV_HOLD_STATE ]*****\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "bdc_hold_counter = (( %d ))\n", + dm_bdc_table->bdc_hold_counter); + + if (dm_bdc_table->bdc_hold_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); + odm_div_train_state_setting(dm); + } else { + dm_bdc_table->bdc_hold_counter--; + dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE; + odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF); + PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n"); + } + } + + } else if (dm_bdc_table->bdc_try_flag == 1) { + /* @2 Set Training counter */ + if (dm_bdc_table->bdc_try_counter > 1) { + dm_bdc_table->bdc_try_counter--; + if (dm_bdc_table->bdc_try_counter == 1) + dm_bdc_table->bdc_try_flag = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n"); + /* return ; */ + } + } + } + + PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n"); + +#endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ +} + +#endif +#endif /* @#ifdef PHYDM_BEAMFORMING_SUPPORT*/ + +#if (RTL8188E_SUPPORT == 1) + +void odm_rx_hw_ant_div_init_88e(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* @MAC setting */ + value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, + value32 | (BIT(23) | BIT(25))); + /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); + /* reg870[8]=1'b0, reg870[9]=1'b0 */ + /* antsel antselb by HW */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); + /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); + /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); + /* regb2c[31]=1'b1 */ /* output at CG only */ + /* OFDM Settings */ + odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + /* @CCK Settings */ + odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); + /* @CCK complete HW AntDiv within 64 samples */ + + odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); + /* @antenna mapping table */ + + fat_tab->enable_ctrl_frame_antdiv = 1; +} + +void odm_trx_hw_ant_div_init_88e(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* @MAC setting */ + value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD); + odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, + value32 | (BIT(23) | BIT(25))); + /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + /* Pin Settings */ + odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); + /* reg870[8]=1'b0, reg870[9]=1'b0 */ + /* antsel antselb by HW */ + odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); + /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); + /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); + /* regb2c[31]=1'b1 */ /* output at CG only */ + /* OFDM Settings */ + odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0); + /* @CCK Settings */ + odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); + /* @CCK complete HW AntDiv within 64 samples */ + + /* @antenna mapping table */ + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x700, 1); + /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, 0x3800, 2); + /* Reg858[13:11]=3'b010 */ + } else /* @MPchip */ + odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); + /*Reg914=3'b010, Reg915=3'b001*/ + + fat_tab->enable_ctrl_frame_antdiv = 1; +} + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) +void odm_smart_hw_ant_div_init_88e( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32, i; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8188E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"); + +#if 0 + if (*dm->mp_mode == true) { + PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n", + dm->ant_div_type); + return; + } +#endif + + fat_tab->train_idx = 0; + fat_tab->fat_state = FAT_PREPARE_STATE; + + dm->fat_comb_a = 5; + dm->antdiv_intvl = 0x64; /* @100ms */ + + for (i = 0; i < 6; i++) + fat_tab->bssid[i] = 0; + for (i = 0; i < (dm->fat_comb_a); i++) { + fat_tab->ant_sum_rssi[i] = 0; + fat_tab->ant_rssi_cnt[i] = 0; + fat_tab->ant_ave_rssi[i] = 0; + } + + /* @MAC setting */ + value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD); + odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */ + value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD); + odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */ + /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */ + /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18)); */ /* append MACID in reponse packet */ + + /* @Match MAC ADDR */ + odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); + odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0); + + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0 */ /* antsel antselb by HW */ + odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0 */ /* antsel2 by HW */ + odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0 */ /* disable CS/CG switch */ + odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1 */ /* output at CS only */ + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0); + + /* @antenna mapping table */ + if (dm->fat_comb_a == 2) { + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */ + odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */ + } else { /* @MPchip */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); + } + } else { + if (!dm->is_mp_chip) { /* testchip */ + odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */ + odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */ + odm_set_bb_reg(dm, R_0x878, BIT(16), 0); + odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */ + odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */ + odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */ + odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */ + odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */ + odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */ + } else { /* @MPchip */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */ + odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */ + } + } + + /* @Default ant setting when no fast training */ + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */ + + /* @Enter Traing state */ + odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6 */ /* ant combination=reg864[2:0]+1 */ + +#if 0 + /* SW Control */ + /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */ + /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */ + /* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */ + /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */ + /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */ + /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */ +#endif +} +#endif + +#endif /* @#if (RTL8188E_SUPPORT == 1) */ + +#if (RTL8192E_SUPPORT == 1) +void odm_rx_hw_ant_div_init_92e(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + +#if 0 + if (*dm->mp_mode == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); + /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); + /* @1:CG, 0:CS */ + return; + } +#endif + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); + /* reg870[8]=1'b0, antsel is controled by HWs */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); + /* regc50[8]=1'b1 CS/CG switching is controled by HWs*/ + + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); + /* @antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ + + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); + /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); + /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @CCK complete HW AntDiv within 64 samples */ + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} + +void odm_trx_hw_ant_div_init_92e(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if 0 + if (*dm->mp_mode == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */ + return; + } +#endif + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* @3 --RFE pin setting--------- */ + /* @[MAC] */ + odm_set_mac_reg(dm, R_0x38, BIT(11), 1); + /* @DBG PAD Driving control (GPIO 8) */ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */ + odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */ + /* @[BB] */ + odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */ + odm_set_bb_reg(dm, R_0x944, BIT(8), 1); + odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0); + /* r_rfe_path_sel_ (RFE_CTRL_3) */ + odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0); + /* r_rfe_path_sel_ (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */ + odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */ + odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */ + odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ + /* @3 ------------------------- */ + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); + /* path-A */ /* disable CS/CG switch */ + +#if 0 + /* @Let it follows PHY_REG for bit9 setting */ + if (dm->priv->pshare->rf_ft_var.use_ext_pa || + dm->priv->pshare->rf_ft_var.use_ext_lna) + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);/* path-A output at CS */ + else + odm_set_bb_reg(dm, R_0xc50, BIT(9), 0); + /* path-A output at CG ->normal power */ +#endif + + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); + /* path-A*/ /* antsel antselb by HW */ + odm_set_bb_reg(dm, R_0xb38, BIT(10), 0);/* path-A*/ /* antsel2 by HW */ + + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); + /* @antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ + + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); + /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); + /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @CCK complete HW AntDiv within 64 samples */ + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) +void odm_smart_hw_ant_div_init_92e( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8192E AntDiv_Init => ant_div_type=[CG_TRX_SMART_ANTDIV]\n"); +} +#endif + +#endif /* @#if (RTL8192E_SUPPORT == 1) */ + +#if (RTL8192F_SUPPORT == 1) +void odm_rx_hw_ant_div_init_92f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); + /* reg870[8]=1'b0, "antsel" is controlled by HWs */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); + /* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */ + + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); + /* @antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ + + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); + /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); + /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @CCK complete HW AntDiv within 64 samples */ + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} + +void odm_trx_hw_ant_div_init_92f(void *dm_void) + +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + /* @3 --RFE pin setting--------- */ + /* @[MAC] */ + odm_set_mac_reg(dm, R_0x1048, BIT(0), 1); + /* @DBG PAD Driving control (gpioA_0) */ + odm_set_mac_reg(dm, R_0x1048, BIT(1), 1); + /* @DBG PAD Driving control (gpioA_1) */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); + odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0); + /* @gpioA_0,gpioA_1*/ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + /* @[BB] */ + odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */ + odm_set_bb_reg(dm, R_0x944, BIT(9), 1); + odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0); + /* r_rfe_path_sel_ (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0); + /* r_rfe_path_sel_ (RFE_CTRL_9) */ + odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */ + odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv (RFE_CTRL_8) */ + odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv (RFE_CTRL_9) */ + odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */ + odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */ + /* @3 ------------------------- */ + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); + /* path-A,disable CS/CG switch */ + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); + /* path-A*, antsel antselb by HW */ + odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */ + + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); + /* @antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ + + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); + /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); + /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @CCK complete HW AntDiv within 64 samples */ + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} + +#endif /* @#if (RTL8192F_SUPPORT == 1) */ + +#if (RTL8822B_SUPPORT == 1) +void phydm_trx_hw_ant_div_init_22b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1); + odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0); + /* @------------------------- */ + + /* @Mapping table */ + /* @antenna mapping table */ + odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100); + + /* OFDM Settings */ + /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); + /* @bias */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); + odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1); + + /* @CCK Settings */ + /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* @CCK complete HW AntDiv within 64 samples */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @BT Coexistence */ + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); +#if (defined(CONFIG_2T4R_ANTENNA)) + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8822B AntDiv_Init => 2T4R case\n"); + /* Pin Settings */ + odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1); + odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1); + odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0); + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xeac, BIT(9), 1); + /* @keep antsel_map when GNT_BT = 1 */ + /* Mapping table */ + /* antenna mapping table */ + odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100); + /*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/ +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} +#endif /* @#if (RTL8822B_SUPPORT == 1) */ + +#if (RTL8197F_SUPPORT == 1) +void phydm_rx_hw_ant_div_init_97f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + +#if 0 + if (*dm->mp_mode == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); + /* r_rxdiv_enable_anta regc50[8]=1'b0 0: control by c50[9] */ + odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* @1:CG, 0:CS */ + return; + } +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); + /* reg870[8]=1'b0, */ /* "antsel" is controlled by HWs */ + odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); + /* regc50[8]=1'b1 *//*"CS/CG switching" is controlled by HWs */ + + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); + /* @antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */ + + /* @CCK Settings */ + odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); + /* Select which path to receive for CCK_1 & CCK_2 */ + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); + /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* @Fix CCK PHY status report issue */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @CCK complete HW AntDiv within 64 samples */ + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} +#endif //#if (RTL8197F_SUPPORT == 1) + +#if (RTL8197G_SUPPORT == 1) +void phydm_rx_hw_ant_div_init_97g(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0x1884, BIT(23), 0); + /* reg1844[23]=1'b0 *//*"CS/CG switching" is controlled by HWs*/ + odm_set_bb_reg(dm, R_0x1884, BIT(16), 1); + /* reg1844[16]=1'b1 *//*"antsel" is controlled by HWs*/ + + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x1870, 0xFFFF, 0x0100); + /* @antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0x1938, 0xFFE0, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x1938, 0x7FF0000, 0x0); /* @bias */ + + +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} +#endif //#if (RTL8197F_SUPPORT == 1) + +#if (RTL8723F_SUPPORT == 1) +void phydm_rx_hw_ant_div_init_23f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + /* @3 --RFE pin setting--------- */ + /* @[MAC] */ + /* @gpioA_11,gpioA_12*/ + odm_set_mac_reg(dm, R_0x10d8, 0xFF000000, 0x16); + odm_set_mac_reg(dm, R_0x10dc, 0xFF, 0x16); + /* @[BB] */ + odm_set_bb_reg(dm, R_0x1c94, BIT(2) | BIT(3), 0x3); /* output enable */ + odm_set_bb_reg(dm, R_0x1ca0, BIT(2) | BIT(3), 0x0); + odm_set_bb_reg(dm, R_0x1c98, BIT(4) | BIT(5), 0x0); + /* r_rfe_path_sel_ (RFE_CTRL_2) */ + odm_set_bb_reg(dm, R_0x1c98, BIT(6) | BIT(7), 0x0); + /* r_rfe_path_sel_ (RFE_CTRL_3) */ + odm_set_bb_reg(dm, R_0x1838, BIT(28), 0); /* RFE_buffer_en */ + odm_set_bb_reg(dm, R_0x183c, BIT(2), 1); /* rfe_inv (RFE_CTRL_2) */ + odm_set_bb_reg(dm, R_0x183c, BIT(3), 0); /* rfe_inv (RFE_CTRL_3) */ + odm_set_bb_reg(dm, R_0x1840, 0xF00, 0x8); /* path-A, RFE_CTRL_2 */ + odm_set_bb_reg(dm, R_0x1840, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */ + /* @3 ------------------------- */ + + /* Pin Settings */ + odm_set_bb_reg(dm, R_0x1884, BIT(23), 0); + odm_set_bb_reg(dm, R_0x1884, BIT(25), 0); + /* reg1844[23]=1'b0 *//*"CG switching" is controlled by HWs*/ + /* reg1844[25]=1'b0 *//*"CG switching" is controlled by HWs*/ + odm_set_bb_reg(dm, R_0x1884, BIT(16), 1); + /* reg1844[16]=1'b1 *//*"antsel" is controlled by HWs*/ + + /* @Mapping table */ + odm_set_bb_reg(dm, R_0x1870, 0xFFFF, 0x0100); + /* @antenna mapping table */ + + /* OFDM Settings */ + odm_set_bb_reg(dm, R_0x1938, 0xFFE0, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x1938, 0x7FF0000, 0x0); /* @bias */ +#ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_evm_sw_antdiv_init(dm); +#endif +} +#endif //#if (RTL8723F_SUPPORT == 1) + +#if (RTL8723D_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8723d(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /*@BT Coexistence*/ + /*@keep antsel_map when GNT_BT = 1*/ + odm_set_bb_reg(dm, R_0x864, BIT(12), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 0); + /* @Disable hw antsw & fast_train.antsw when BT TX/RX */ + odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c); + + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); +#if 0 + /*PTA setting: WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL)*/ + /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/ + /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/ +#endif + /*@GNT_WL tx*/ + odm_set_bb_reg(dm, R_0x950, BIT(29), 0); + + /*@Mapping Table*/ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3); +#if 0 + /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */ + /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */ +#endif + + /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */ + odm_set_bb_reg(dm, R_0xccc, BIT(12), 0); + /* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01); + /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */ + odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0); + /* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable (CCK)*/ + odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06); + /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable (CCK) */ + odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00); + + /*OFDM HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); + odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04); + + /*@CCK HW AntDiv Parameters*/ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0); + + odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf); + odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8); + odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0); + odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1); + + /*@disable antenna training */ + odm_set_bb_reg(dm, R_0xe08, BIT(16), 0); + odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); +} +/*@Mingzhi 2017-05-08*/ + +void odm_s0s1_sw_ant_div_init_8723d(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); + + /*@keep antsel_map when GNT_BT = 1*/ + odm_set_bb_reg(dm, R_0x864, BIT(12), 1); + + /* @Disable antsw when GNT_BT=1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 0); + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); + + /* Output Pin Settings */ +#if 0 + /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */ +#endif + odm_set_bb_reg(dm, R_0x870, BIT(8), 1); + odm_set_bb_reg(dm, R_0x870, BIT(9), 1); + + /* Status init */ + fat_tab->is_become_linked = false; + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->double_chk_flag = 0; + swat_tab->cur_antenna = MAIN_ANT; + swat_tab->pre_ant = MAIN_ANT; + dm->antdiv_counter = CONFIG_ANTDIV_PERIOD; + + /* @2 [--For HW Bug setting] */ + odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */ +} + +void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; + u8 count = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + /*score board to BT ,a002:WL to do ant-div*/ + odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002); + ODM_delay_us(50); +#endif +#if 0 + /* odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); */ +#endif + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant); + odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant); + } + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); + /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); + /*Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); + /*@Default TX*/ + fat_tab->rx_idle_ant = ant; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + /*score board to BT ,a000:WL@S1 a001:WL@S0*/ + if (default_ant == ANT1_2G) + odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000); + else + odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001); +#endif +} + +void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; + + fat_tab->rx_idle_ant = ant; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(adapter, *dm->channel); +#endif +} +#endif + +#if (RTL8723B_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8723b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8723B AntDiv_Init => ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n"); + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */ + odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); + /* @do 64 samples */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0x864, BIT(12), 0); + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x874, BIT(23), 0); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + /* Output Pin Settings */ + odm_set_bb_reg(dm, R_0x870, BIT(8), 0); + + odm_set_bb_reg(dm, R_0x948, BIT(6), 0); + /* WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) */ + odm_set_bb_reg(dm, R_0x948, BIT(7), 0); + + odm_set_mac_reg(dm, R_0x40, BIT(3), 1); + odm_set_mac_reg(dm, R_0x38, BIT(11), 1); + odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2); + /* select DPDT_P and DPDT_N as output pin */ + + odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */ + odm_set_bb_reg(dm, R_0x944, BIT(31), 0); + + odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */ + + odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */ + + /* @2 [--For HW Bug setting] */ + if (dm->ant_type == ODM_AUTO_ANT) + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); + /* @CCK AntDiv function block enable */ +} + +void odm_s0s1_sw_ant_div_init_8723b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n"); + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1); + +#if 0 + /* Output Pin Settings */ + /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */ +#endif + odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); + + fat_tab->is_become_linked = false; + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->double_chk_flag = 0; + + /* @2 [--For HW Bug setting] */ + odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant by Reg */ +} + +void odm_update_rx_idle_ant_8723b( + void *dm_void, + u8 ant, + u32 default_ant, + u32 optional_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + void *adapter = dm->adapter; + u8 count = 0; + /*u8 u1_temp;*/ + /*u8 h2c_parameter;*/ + + if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n"); + return; + } + +#if 0 + /* Send H2C command to FW */ + /* @Enable wifi calibration */ + h2c_parameter = true; + odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); + + /* @Check if H2C command sucess or not (0x1e6) */ + u1_temp = odm_read_1byte(dm, 0x1e6); + while ((u1_temp != 0x1) && (count < 100)) { + ODM_delay_us(10); + u1_temp = odm_read_1byte(dm, 0x1e6); + count++; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n", + u1_temp, count); + + if (u1_temp == 0x1) { + /* @Check if BT is doing IQK (0x1e7) */ + count = 0; + u1_temp = odm_read_1byte(dm, 0x1e7); + while ((!(u1_temp & BIT(0))) && (count < 100)) { + ODM_delay_us(50); + u1_temp = odm_read_1byte(dm, 0x1e7); + count++; + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n", + u1_temp, count); + + if (u1_temp & BIT(0)) { + odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); + odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant); + odm_set_bb_reg(dm, R_0x864, 0x38, default_ant); + /* @Default RX */ + odm_set_bb_reg(dm, R_0x864, 0x1c0, optional_ant); + /* @Optional RX */ + odm_set_bb_reg(dm, R_0x860, 0x7000, default_ant); + /* @Default TX */ + fat_tab->rx_idle_ant = ant; + + /* Set TX AGC by S0/S1 */ + /* Need to consider Linux driver */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(adapter, *dm->channel); +#endif + + /* Set IQC by S0/S1 */ + odm_set_iqc_by_rfpath(dm, default_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"); + } else + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n"); + } else + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n"); + + /* Send H2C command to FW */ + /* @Disable wifi calibration */ + h2c_parameter = false; + odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); +#else + + odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1); + odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant); + odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); + /*@Default RX*/ + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); + /*Optional RX*/ + odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); + /*@Default TX*/ + fat_tab->rx_idle_ant = ant; + +/* Set TX AGC by S0/S1 */ +/* Need to consider Linux driver */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(adapter, *dm->channel); +#endif + + /* Set IQC by S0/S1 */ + odm_set_iqc_by_rfpath(dm, default_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n"); + +#endif +} + +boolean +phydm_is_bt_enable_8723b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 bt_state; +#if 0 + /*u32 reg75;*/ + + /*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/ + /*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/ +#endif + odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5); + bt_state = odm_get_bb_reg(dm, R_0xa0, 0xf); +#if 0 + /*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/ +#endif + + if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13) + return true; + else + return false; +} +#endif /* @#if (RTL8723B_SUPPORT == 1) */ + +#if (RTL8821A_SUPPORT == 1) + +void odm_trx_hw_ant_div_init_8821a(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Output Pin Settings */ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ + + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); + + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); + /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); + /* @CCK AntDiv function block enable */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); + /* settling time of antdiv by RF LNA = 100ns */ + + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); +} + +void odm_s0s1_sw_ant_div_init_8821a(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Output Pin Settings */ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ + + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); + + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); + /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); + /* @CCK AntDiv function block enable */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); + /* settling time of antdiv by RF LNA = 100ns */ + + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); + + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); + + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->double_chk_flag = 0; + swat_tab->cur_antenna = MAIN_ANT; + swat_tab->pre_ant = MAIN_ANT; + swat_tab->swas_no_link_state = 0; +} +#endif /* @#if (RTL8821A_SUPPORT == 1) */ + +#if (RTL8821C_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + /* Output Pin Settings */ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ + + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); + + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); + /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); + /* @CCK AntDiv function block enable */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + /* Timming issue */ + odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); + /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); + /* settling time of antdiv by RF LNA = 100ns */ + + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); +} + +void phydm_s0s1_sw_ant_div_init_8821c(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Output Pin Settings */ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */ + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */ + + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); + + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + /* select DPDT_P and DPDT_N as output pin */ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */ + odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); + /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); + /* @CCK AntDiv function block enable */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); + /* settling time of antdiv by RF LNA = 100ns */ + + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); + + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); + + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->double_chk_flag = 0; + swat_tab->cur_antenna = MAIN_ANT; + swat_tab->pre_ant = MAIN_ANT; + swat_tab->swas_no_link_state = 0; +} +#endif /* @#if (RTL8821C_SUPPORT == 1) */ + +#if (RTL8195B_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8195b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0); + /*RFE control pin 0,1*/ + odm_set_bb_reg(dm, R_0xcb0, 0xF, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb0, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb4, BIT(20), 0); /* @DPDT_P non-inverse */ + odm_set_bb_reg(dm, R_0xcb4, BIT(21), 1); /* @DPDT_N inverse */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + odm_set_bb_reg(dm, R_0x800, BIT(25), 0); + /* @ANTSEL_CCK sent to the smart_antenna circuit */ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); + /* @CCK AntDiv function block enable */ + + /* @BT Coexistence */ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); + /* @keep antsel_map when GNT_BT = 1 */ + odm_set_bb_reg(dm, R_0x804, BIT(4), 1); + /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */ + + /* Timming issue */ + odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); + /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); + /* settling time of antdiv by RF LNA = 100ns */ + + /* response TX ant by RX ant */ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); +} +#endif /* @#if (RTL8195B_SUPPORT == 1) */ + +#if (RTL8881A_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8881a(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* Output Pin Settings */ + /* @[SPDT related] */ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + odm_set_mac_reg(dm, R_0x4c, BIT(26), 0); + odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */ + odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0); + odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1); + odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); + /* settling time of antdiv by RF LNA = 100ns */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + /* @2 [--For HW Bug setting] */ + + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); + /* TX ant by Reg *//* A-cut bug */ +} + +#endif /* @#if (RTL8881A_SUPPORT == 1) */ + +#if (RTL8812A_SUPPORT == 1) +void odm_trx_hw_ant_div_init_8812a(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + + /* @3 */ /* @3 --RFE pin setting--------- */ + /* @[BB] */ + odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0); + /* @disable SW switch */ + odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */ + odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */ + odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0); + odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1); + odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */ + odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */ + /* @3 ------------------------- */ + + /* @Mapping Table */ + odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0); + odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1); + + /* OFDM HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */ + odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */ + odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); + /* settling time of antdiv by RF LNA = 100ns */ + + /* @CCK HW AntDiv Parameters */ + odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); + /* patch for clk from 88M to 80M */ + odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */ + + /* @2 [--For HW Bug setting] */ + + odm_set_bb_reg(dm, R_0x900, BIT(18), 0); + /* TX ant by Reg */ /* A-cut bug */ +} + +#endif /* @#if (RTL8812A_SUPPORT == 1) */ + +#if (RTL8188F_SUPPORT == 1) +void odm_s0s1_sw_ant_div_init_8188f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s]=====>\n", __func__); + +#if 0 + /*@GPIO setting*/ + /*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */ + /*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/ + /*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/ + /*enable_output for P_GPIO[4:3]*/ + /*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/ + /*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/ +#endif + + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) + odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3); + /*@enable_output for P_GPIO[4:3]*/ + else if (dm->support_interface == ODM_ITRF_SDIO) + odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1); + /*@enable_output for P_GPIO[2]*/ + } + + fat_tab->is_become_linked = false; + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->double_chk_flag = 0; +} + +void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 codeword; + + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) { + if (default_ant == ANT1_2G) + codeword = 1; /*@2'b01*/ + else + codeword = 2; /*@2'b10*/ + odm_set_mac_reg(dm, R_0x44, 0x1800, codeword); + /*@GPIO[4:3] output value*/ + } else if (dm->support_interface == ODM_ITRF_SDIO) { + if (default_ant == ANT1_2G) { + codeword = 0; /*@1'b0*/ + odm_set_bb_reg(dm, R_0x870, 0x300, 0x3); + odm_set_bb_reg(dm, R_0x860, 0x300, 0x1); + } else { + codeword = 1; /*@1'b1*/ + odm_set_bb_reg(dm, R_0x870, 0x300, 0x3); + odm_set_bb_reg(dm, R_0x860, 0x300, 0x2); + } + odm_set_mac_reg(dm, R_0x44, BIT(10), codeword); + /*@GPIO[2] output value*/ + } + } +} +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV +void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct phydm_perpkt_info_struct *pktinfo = NULL; + u8 data_rate = 0; + + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + data_rate = pktinfo->data_rate & 0x7f; + + if (!fat_tab->get_stats) + return; + + if (fat_tab->antsel_rx_keep_0 == ANT1_2G) { + if (data_rate >= ODM_RATEMCS0 && + data_rate <= ODM_RATEMCS15) + fat_tab->main_ht_cnt[data_rate - ODM_RATEMCS0]++; + else if (data_rate >= ODM_RATEVHTSS1MCS0 && + data_rate <= ODM_RATEVHTSS2MCS9) + fat_tab->main_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++; + } else { /*ANT2_2G*/ + if (data_rate >= ODM_RATEMCS0 && + data_rate <= ODM_RATEMCS15) + fat_tab->aux_ht_cnt[data_rate - ODM_RATEMCS0]++; + else if (data_rate >= ODM_RATEVHTSS1MCS0 && + data_rate <= ODM_RATEVHTSS2MCS9) + fat_tab->aux_vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++; + } +} + +void phydm_antdiv_reset_rx_rate(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + odm_memory_set(dm, &fat_tab->main_ht_cnt[0], 0, HT_IDX * 2); + odm_memory_set(dm, &fat_tab->aux_ht_cnt[0], 0, HT_IDX * 2); + odm_memory_set(dm, &fat_tab->main_vht_cnt[0], 0, VHT_IDX * 2); + odm_memory_set(dm, &fat_tab->aux_vht_cnt[0], 0, VHT_IDX * 2); +} + +void phydm_statistics_evm_1ss(void *dm_void, void *phy_info_void, + u8 antsel_tr_mux, u32 id, u32 utility) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct phydm_phyinfo_struct *phy_info = NULL; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0]) + << 5); + fat_tab->main_evm_cnt[id]++; + } else { + fat_tab->aux_evm_sum[id] += ((phy_info->rx_mimo_evm_dbm[0]) + << 5); + fat_tab->aux_evm_cnt[id]++; + } +} + +void phydm_statistics_evm_2ss(void *dm_void, void *phy_info_void, + u8 antsel_tr_mux, u32 id, u32 utility) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct phydm_phyinfo_struct *phy_info = NULL; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_evm_2ss_sum[id][0] += phy_info->rx_mimo_evm_dbm[0] + << 5; + fat_tab->main_evm_2ss_sum[id][1] += phy_info->rx_mimo_evm_dbm[1] + << 5; + fat_tab->main_evm_2ss_cnt[id]++; + + } else { + fat_tab->aux_evm_2ss_sum[id][0] += (phy_info->rx_mimo_evm_dbm[0] + << 5); + fat_tab->aux_evm_2ss_sum[id][1] += (phy_info->rx_mimo_evm_dbm[1] + << 5); + fat_tab->aux_evm_2ss_cnt[id]++; + } +} + +void phydm_evm_sw_antdiv_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + /*@EVM enhance AntDiv method init----------------*/ + fat_tab->evm_method_enable = 0; + fat_tab->fat_state = NORMAL_STATE_MIAN; + fat_tab->fat_state_cnt = 0; + fat_tab->pre_antdiv_rssi = 0; + + dm->antdiv_intvl = 30; + dm->antdiv_delay = 20; + dm->antdiv_train_num = 4; + if (dm->support_ic_type & ODM_RTL8192E) + odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf); + dm->antdiv_evm_en = 1; + /*@dm->antdiv_period=1;*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + dm->evm_antdiv_period = 1; +#else + dm->evm_antdiv_period = 3; +#endif + dm->stop_antdiv_rssi_th = 3; + dm->stop_antdiv_tp_th = 80; + dm->antdiv_tp_period = 3; + dm->stop_antdiv_tp_diff_th = 5; +} + +void odm_evm_fast_ant_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + fat_tab->evm_method_enable = 0; + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB); + fat_tab->fat_state = NORMAL_STATE_MIAN; + fat_tab->fat_state_cnt = 0; + dm->antdiv_period = 0; + odm_set_mac_reg(dm, R_0x608, BIT(8), 0); +} + +void odm_evm_enhance_ant_div(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 main_rssi, aux_rssi; + u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1; + u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0; + u32 main_2ss_evm[2], aux_2ss_evm[2]; + u32 main_1ss_evm, aux_1ss_evm; + u32 main_2ss_evm_sum, aux_2ss_evm_sum; + u8 score_EVM = 0, score_CRC = 0; + u8 rssi_larger_ant = 0; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 value32, i, mac_id; + boolean main_above1 = false, aux_above1 = false; + boolean force_antenna = false; + struct cmn_sta_info *sta; + u32 main_tp_avg, aux_tp_avg; + u8 curr_rssi, rssi_diff; + u32 tp_diff, tp_diff_avg; + u16 main_max_cnt = 0, aux_max_cnt = 0; + u16 main_max_idx = 0, aux_max_idx = 0; + u16 main_cnt_all = 0, aux_cnt_all = 0; + u8 rate_num = dm->num_rf_path; + u8 rate_ss_shift = 0; + u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0; + u8 target_ant_evm_1ss, target_ant_evm_2ss; + u8 decision_evm_ss; + u8 next_ant; + + fat_tab->target_ant_enhance = 0xFF; + + if ((dm->support_ic_type & ODM_EVM_ANTDIV_IC)) { + if (dm->is_one_entry_only) { +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */ +#endif + mac_id = dm->one_entry_macid; + sta = dm->phydm_sta_info[mac_id]; + + main_rssi = (fat_tab->main_cnt[mac_id] != 0) ? (fat_tab->main_sum[mac_id] / fat_tab->main_cnt[mac_id]) : 0; + aux_rssi = (fat_tab->aux_cnt[mac_id] != 0) ? (fat_tab->aux_sum[mac_id] / fat_tab->aux_cnt[mac_id]) : 0; + + if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF)) + diff_rssi = FORCE_RSSI_DIFF; + else if (main_rssi != 0 && aux_rssi != 0) + diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi); + + if (main_rssi >= aux_rssi) + rssi_larger_ant = MAIN_ANT; + else + rssi_larger_ant = AUX_ANT; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Main_Cnt=(( %d )), main_rssi=(( %d ))\n", + fat_tab->main_cnt[mac_id], main_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n", + fat_tab->aux_cnt[mac_id], aux_rssi); + + if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1) + /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */ + ) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "> TH_H || evm_method_enable==1\n"); + + if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt); + + /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/ + if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) { + if (fat_tab->fat_state_cnt == 0) { + /*Reset EVM 1SS Method */ + fat_tab->main_evm_sum[mac_id] = 0; + fat_tab->aux_evm_sum[mac_id] = 0; + fat_tab->main_evm_cnt[mac_id] = 0; + fat_tab->aux_evm_cnt[mac_id] = 0; + /*Reset EVM 2SS Method */ + fat_tab->main_evm_2ss_sum[mac_id][0] = 0; + fat_tab->main_evm_2ss_sum[mac_id][1] = 0; + fat_tab->aux_evm_2ss_sum[mac_id][0] = 0; + fat_tab->aux_evm_2ss_sum[mac_id][1] = 0; + fat_tab->main_evm_2ss_cnt[mac_id] = 0; + fat_tab->aux_evm_2ss_cnt[mac_id] = 0; + + /*Reset TP Method */ + fat_tab->main_tp = 0; + fat_tab->aux_tp = 0; + fat_tab->main_tp_cnt = 0; + fat_tab->aux_tp_cnt = 0; + phydm_antdiv_reset_rx_rate(dm); + + /*Reset CRC Method */ + fat_tab->main_crc32_ok_cnt = 0; + fat_tab->main_crc32_fail_cnt = 0; + fat_tab->aux_crc32_ok_cnt = 0; + fat_tab->aux_crc32_fail_cnt = 0; + +#ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH + if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) { + /*@1. Skip training: RSSI*/ +#if 0 + /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/ +#endif + curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi); + rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi); + + PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi); + + fat_tab->pre_antdiv_rssi = curr_rssi; + if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0) + rssi_return = 1; + + /*@2. Skip training: TP Diff*/ + tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp); + + PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp); + fat_tab->pre_antdiv_tp = dm->rx_tp; + if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0)) + tp_diff_return = 1; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp); + /*@3. Skip training: TP*/ + if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th)) + tp_return = 1; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return); + /*@4. Joint Return Decision*/ + if (tp_return) { + if (tp_diff_return || rssi_diff) { + PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n"); + return; + } + } + } +#endif + + fat_tab->evm_method_enable = 1; + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); + dm->antdiv_period = dm->evm_antdiv_period; + odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/ + fat_tab->fat_state_cnt++; + fat_tab->get_stats = false; + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? MAIN_ANT : AUX_ANT; + odm_update_rx_idle_ant(dm, next_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n"); + odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms + } else if ((fat_tab->fat_state_cnt % 2) != 0) { + fat_tab->fat_state_cnt++; + fat_tab->get_stats = true; + odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms + } else if ((fat_tab->fat_state_cnt % 2) == 0) { + fat_tab->fat_state_cnt++; + fat_tab->get_stats = false; + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Antdiv Delay ]\n"); + odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_delay); //ms + } + } + /*@Decision state: 4==============================================================*/ + else { + fat_tab->get_stats = false; + fat_tab->fat_state_cnt = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n"); + +/* @3 [CRC32 statistic] */ +#if 0 + if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) { + fat_tab->target_ant_crc32 = MAIN_ANT; + force_antenna = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n"); + } else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) { + fat_tab->target_ant_crc32 = AUX_ANT; + force_antenna = true; + PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n"); + } else +#endif + { + if (fat_tab->main_crc32_fail_cnt <= 5) + fat_tab->main_crc32_fail_cnt = 5; + + if (fat_tab->aux_crc32_fail_cnt <= 5) + fat_tab->aux_crc32_fail_cnt = 5; + + if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt) + main_above1 = true; + + if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt) + aux_above1 = true; + + if (main_above1 == true && aux_above1 == false) { + force_antenna = true; + fat_tab->target_ant_crc32 = MAIN_ANT; + } else if (main_above1 == false && aux_above1 == true) { + force_antenna = true; + fat_tab->target_ant_crc32 = AUX_ANT; + } else if (main_above1 == true && aux_above1 == true) { + main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt; + aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt; + fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + + if (main_crc_utility != 0 && aux_crc_utility != 0) { + if (main_crc_utility >= aux_crc_utility) + utility_ratio = (main_crc_utility << 1) / aux_crc_utility; + else + utility_ratio = (aux_crc_utility << 1) / main_crc_utility; + } + } else if (main_above1 == false && aux_above1 == false) { + if (fat_tab->main_crc32_ok_cnt == 0) + fat_tab->main_crc32_ok_cnt = 1; + if (fat_tab->aux_crc32_ok_cnt == 0) + fat_tab->aux_crc32_ok_cnt = 1; + + main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt; + aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt; + fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT); + + if (main_crc_utility != 0 && aux_crc_utility != 0) { + if (main_crc_utility >= aux_crc_utility) + utility_ratio = (main_crc_utility << 1) / (aux_crc_utility); + else + utility_ratio = (aux_crc_utility << 1) / (main_crc_utility); + } + } + } + odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */ + PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility); + PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility); + PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + for (i = 0; i < HT_IDX; i++) { + main_cnt_all += fat_tab->main_ht_cnt[i]; + aux_cnt_all += fat_tab->aux_ht_cnt[i]; + + if (fat_tab->main_ht_cnt[i] > main_max_cnt) { + main_max_cnt = fat_tab->main_ht_cnt[i]; + main_max_idx = i; + } + + if (fat_tab->aux_ht_cnt[i] > aux_max_cnt) { + aux_max_cnt = fat_tab->aux_ht_cnt[i]; + aux_max_idx = i; + } + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ANT_DIV, "*main_ht_cnt HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift + 7), + fat_tab->main_ht_cnt[rate_ss_shift + 0], fat_tab->main_ht_cnt[rate_ss_shift + 1], + fat_tab->main_ht_cnt[rate_ss_shift + 2], fat_tab->main_ht_cnt[rate_ss_shift + 3], + fat_tab->main_ht_cnt[rate_ss_shift + 4], fat_tab->main_ht_cnt[rate_ss_shift + 5], + fat_tab->main_ht_cnt[rate_ss_shift + 6], fat_tab->main_ht_cnt[rate_ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + rate_ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ANT_DIV, "*aux_ht_cnt HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (rate_ss_shift), (rate_ss_shift + 7), + fat_tab->aux_ht_cnt[rate_ss_shift + 0], fat_tab->aux_ht_cnt[rate_ss_shift + 1], + fat_tab->aux_ht_cnt[rate_ss_shift + 2], fat_tab->aux_ht_cnt[rate_ss_shift + 3], + fat_tab->aux_ht_cnt[rate_ss_shift + 4], fat_tab->aux_ht_cnt[rate_ss_shift + 5], + fat_tab->aux_ht_cnt[rate_ss_shift + 6], fat_tab->aux_ht_cnt[rate_ss_shift + 7]); + } + + /* @3 [EVM statistic] */ + /*@1SS EVM*/ + main_1ss_evm = (fat_tab->main_evm_cnt[mac_id] != 0) ? (fat_tab->main_evm_sum[mac_id] / fat_tab->main_evm_cnt[mac_id]) : 0; + aux_1ss_evm = (fat_tab->aux_evm_cnt[mac_id] != 0) ? (fat_tab->aux_evm_sum[mac_id] / fat_tab->aux_evm_cnt[mac_id]) : 0; + target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= (( %d ))\n", fat_tab->main_evm_cnt[mac_id], main_1ss_evm); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = (( %d ))\n", fat_tab->aux_evm_cnt[mac_id], aux_1ss_evm); + + /*@2SS EVM*/ + main_2ss_evm[0] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][0] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0; + main_2ss_evm[1] = (fat_tab->main_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->main_evm_2ss_sum[mac_id][1] / fat_tab->main_evm_2ss_cnt[mac_id]) : 0; + main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1]; + + aux_2ss_evm[0] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][0] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0; + aux_2ss_evm[1] = (fat_tab->aux_evm_2ss_cnt[mac_id] != 0) ? (fat_tab->aux_evm_2ss_sum[mac_id][1] / fat_tab->aux_evm_2ss_cnt[mac_id]) : 0; + aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1]; + + target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + fat_tab->main_evm_2ss_cnt[mac_id], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n", + fat_tab->aux_evm_2ss_cnt[mac_id], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum); + + if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) { + decision_evm_ss = 2; + main_evm = main_2ss_evm_sum; + aux_evm = aux_2ss_evm_sum; + fat_tab->target_ant_evm = target_ant_evm_2ss; + } else { + decision_evm_ss = 1; + main_evm = main_1ss_evm; + aux_evm = aux_1ss_evm; + fat_tab->target_ant_evm = target_ant_evm_1ss; + } + + if ((main_evm == 0 || aux_evm == 0)) + diff_EVM = 100; + else if (main_evm >= aux_evm) + diff_EVM = main_evm - aux_evm; + else + diff_EVM = aux_evm - main_evm; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + //3 [TP statistic] + main_tp_avg = (fat_tab->main_tp_cnt != 0) ? (fat_tab->main_tp / fat_tab->main_tp_cnt) : 0; + aux_tp_avg = (fat_tab->aux_tp_cnt != 0) ? (fat_tab->aux_tp / fat_tab->aux_tp_cnt) : 0; + tp_diff_avg = DIFF_2(main_tp_avg, aux_tp_avg); + fat_tab->target_ant_tp = (tp_diff_avg < 100) ? (fat_tab->pre_target_ant_enhance) : ((main_tp_avg >= aux_tp_avg) ? MAIN_ANT : AUX_ANT); + + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->main_tp_cnt, main_tp_avg); + PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->aux_tp_cnt, aux_tp_avg); + PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + /*Reset TP Method */ + fat_tab->main_tp = 0; + fat_tab->aux_tp = 0; + fat_tab->main_tp_cnt = 0; + fat_tab->aux_tp_cnt = 0; + + /* @2 [ Decision state ] */ + #if 1 + if (main_max_idx == aux_max_idx && ((main_cnt_all + aux_cnt_all) != 0)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision EVM, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx); + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision TP, main_max_idx = ((MCS%d)), aux_max_idx = ((MCS%d))\n", main_max_idx, aux_max_idx); + fat_tab->target_ant_enhance = fat_tab->target_ant_tp; + } + #else + if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + + if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30) + fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance; + else + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; + } + #if 0 + else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; + } + #endif + else if (diff_EVM >= 20) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; + } else if (utility_ratio >= 6 && force_antenna == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM); + + if (force_antenna == true) + score_CRC = 2; + else if (utility_ratio >= 5) /*@>2.5*/ + score_CRC = 2; + else if (utility_ratio >= 4) /*@>2*/ + score_CRC = 1; + else + score_CRC = 0; + + if (diff_EVM >= 15) + score_EVM = 3; + else if (diff_EVM >= 10) + score_EVM = 2; + else if (diff_EVM >= 5) + score_EVM = 1; + else + score_EVM = 0; + + if (score_CRC > score_EVM) + fat_tab->target_ant_enhance = fat_tab->target_ant_crc32; + else if (score_CRC < score_EVM) + fat_tab->target_ant_enhance = fat_tab->target_ant_evm; + else + fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance; + } + #endif + fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance; + + PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + } + } else { /* RSSI< = evm_rssi_th_low */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[ TH_L ]\n"); + odm_evm_fast_ant_reset(dm); + } + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[escape from> TH_H || evm_method_enable==1]\n"); + odm_evm_fast_ant_reset(dm); + } + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n"); + odm_evm_fast_ant_reset(dm); + } + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_evm_antdiv_callback( + struct phydm_timer_list *timer) +{ + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + #if USE_WORKITEM + odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem); + #else + { + odm_hw_ant_div(dm); + } + #endif + #else + odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem); + #endif +} + +void phydm_evm_antdiv_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + odm_hw_ant_div(dm); +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_evm_antdiv_callback(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *padapter = dm->adapter; + + if (*dm->is_net_closed) + return; + if (dm->support_interface == ODM_ITRF_PCIE) { + odm_hw_ant_div(dm); + } else { + /* @Can't do I/O in timer callback*/ + phydm_run_in_thread_cmd(dm, + phydm_evm_antdiv_workitem_callback, + padapter); + } +} + +void phydm_evm_antdiv_workitem_callback(void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->odmpriv; + + odm_hw_ant_div(dm); +} + +#else +void phydm_evm_antdiv_callback( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n"); + odm_hw_ant_div(dm); +} +#endif + +#endif + +void odm_hw_ant_div(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0; + u32 main_rssi, aux_rssi, mian_cnt, aux_cnt, local_max_rssi; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct cmn_sta_info *sta; + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u32 TH1 = 500000; + u32 TH2 = 10000000; + u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp; + u8 monitor_rssi_threshold = 30; + + dm_bdc_table->BF_pass = true; + dm_bdc_table->DIV_pass = true; + dm_bdc_table->is_all_div_sta_idle = true; + dm_bdc_table->is_all_bf_sta_idle = true; + dm_bdc_table->num_bf_tar = 0; + dm_bdc_table->num_div_tar = 0; + dm_bdc_table->num_client = 0; +#endif +#endif + + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked) { + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); + odm_update_rx_idle_ant(dm, MAIN_ANT); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + dm->antdiv_period = 0; + + fat_tab->is_become_linked = dm->is_linked; + } + return; + } else { + if (!fat_tab->is_become_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB); + #if 0 + /*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/ + + /* @if(dm->support_ic_type == ODM_RTL8821 ) */ + /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ + /* CCK AntDiv function disable */ + + /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ + /* @else if(dm->support_ic_type == ODM_RTL8881A) */ + /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ + /* CCK AntDiv function disable */ + /* @#endif */ + + /* @else if(dm->support_ic_type == ODM_RTL8723B ||*/ + /* @dm->support_ic_type == ODM_RTL8812) */ + /* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */ + /* CCK AntDiv function disable */ + #endif + + fat_tab->is_become_linked = dm->is_linked; + + if (dm->support_ic_type == ODM_RTL8723B && + dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_set_bb_reg(dm, R_0x930, 0xF0, 8); + /* @DPDT_P = ANTSEL[0] for 8723B AntDiv */ + odm_set_bb_reg(dm, R_0x930, 0xF, 8); + /* @DPDT_N = ANTSEL[0] */ + } + + /* @ BDC Init */ + #ifdef PHYDM_BEAMFORMING_SUPPORT + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_bdc_init(dm); + #endif + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + odm_evm_fast_ant_reset(dm); + #endif + } + } + + if (!(*fat_tab->p_force_tx_by_desc)) { + if (dm->is_one_entry_only) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (dm->antdiv_evm_en == 1) { + odm_evm_enhance_ant_div(dm); + if (fat_tab->fat_state_cnt != 0) + return; + } else + odm_evm_fast_ant_reset(dm); +#endif + +/* @2 BDC mode Arbitration */ +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0) + odm_bf_ant_div_mode_arbitration(dm); +#endif +#endif + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (!is_sta_active(sta)) { + phydm_antdiv_reset_statistic(dm, i); + continue; + } + + /* @2 Caculate RSSI per Antenna */ + if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) { + mian_cnt = fat_tab->main_cnt[i]; + aux_cnt = fat_tab->aux_cnt[i]; + main_rssi = (mian_cnt != 0) ? + (fat_tab->main_sum[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? + (fat_tab->aux_sum[i] / aux_cnt) : 0; + target_ant = (mian_cnt == aux_cnt) ? + fat_tab->rx_idle_ant : + ((mian_cnt >= aux_cnt) ? + fat_tab->ant_idx_vec[0]:fat_tab->ant_idx_vec[1]); + /*Use counter number for OFDM*/ + + } else { /*@CCK only case*/ + mian_cnt = fat_tab->main_cnt_cck[i]; + aux_cnt = fat_tab->aux_cnt_cck[i]; + main_rssi = (mian_cnt != 0) ? + (fat_tab->main_sum_cck[i] / mian_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? + (fat_tab->aux_sum_cck[i] / aux_cnt) : 0; + target_ant = (main_rssi == aux_rssi) ? + fat_tab->rx_idle_ant : + ((main_rssi >= aux_rssi) ? + fat_tab->ant_idx_vec[0]:fat_tab->ant_idx_vec[1]); + /*Use RSSI for CCK only case*/ + } +#if (RTL8721D_SUPPORT) + if(dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) { /* added by Jiao Qi on May.25,2020, only for 3 antenna diversity */ + u8 tmp; + if(target_ant == fat_tab->ant_idx_vec[0]){/* switch the second & third ant index */ + tmp = fat_tab->ant_idx_vec[1]; + fat_tab->ant_idx_vec[1] = fat_tab->ant_idx_vec[2]; + fat_tab->ant_idx_vec[2] = tmp; + }else{ + /* switch the first & second ant index */ + tmp = fat_tab->ant_idx_vec[0]; + fat_tab->ant_idx_vec[0] = fat_tab->ant_idx_vec[1]; + fat_tab->ant_idx_vec[1] = tmp; + /* switch the second & third ant index */ + tmp = fat_tab->ant_idx_vec[1]; + fat_tab->ant_idx_vec[1] = fat_tab->ant_idx_vec[2]; + fat_tab->ant_idx_vec[2] = tmp; + } + } +#endif + + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** Client[ %d ] : Main_Cnt = (( %d )) , CCK_Main_Cnt = (( %d )) , main_rssi= (( %d ))\n", + i, fat_tab->main_cnt[i], + fat_tab->main_cnt_cck[i], main_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** Client[ %d ] : Aux_Cnt = (( %d )) , CCK_Aux_Cnt = (( %d )) , aux_rssi = (( %d ))\n", + i, fat_tab->aux_cnt[i], + fat_tab->aux_cnt_cck[i], aux_rssi); + + local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi; + /* @ Select max_rssi for DIG */ + if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40) + ant_div_max_rssi = local_max_rssi; + if (local_max_rssi > max_rssi) + max_rssi = local_max_rssi; + + /* @ Select RX Idle Antenna */ + if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) { + rx_idle_ant = target_ant; + min_max_rssi = local_max_rssi; + } + +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (dm->antdiv_evm_en == 1) { + if (fat_tab->target_ant_enhance != 0xFF) { + target_ant = fat_tab->target_ant_enhance; + rx_idle_ant = fat_tab->target_ant_enhance; + } + } +#endif + + /* @2 Select TX Antenna */ + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + #ifdef PHYDM_BEAMFORMING_SUPPORT + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (dm_bdc_table->w_bfee_client[i] == 0) + #endif + #endif + { + odm_update_tx_ant(dm, target_ant, i); + } + } + +/* @------------------------------------------------------------ */ + + #ifdef PHYDM_BEAMFORMING_SUPPORT + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + dm_bdc_table->num_client++; + + if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) { + /* @2 Byte counter */ + + ma_rx_temp = sta->rx_moving_average_tp; /* RX TP ( bit /sec) */ + + if (dm_bdc_table->BDC_state == bdc_bfer_train_state) + dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp; + else + dm_bdc_table->MA_rx_TP[i] = ma_rx_temp; + + if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) { + if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */ + dm_bdc_table->num_bf_tar++; + + if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) { + improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */ + dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false; + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass); + } + } else { /* @DIV_Target */ + dm_bdc_table->num_div_tar++; + + if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) { + degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */ + dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false; + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass); + } + } + } + + if (ma_rx_temp > TH1) { + if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */ + dm_bdc_table->is_all_bf_sta_idle = false; + else /* @DIV_Target */ + dm_bdc_table->is_all_div_sta_idle = false; + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** Client[ %d ] : { BFmeeCap, BFmerCap} = { %d , %d }\n", + i, dm_bdc_table->w_bfee_client[i], + dm_bdc_table->w_bfer_client[i]); + + if (dm_bdc_table->BDC_state == bdc_bfer_train_state) + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]); + + else + PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] : MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]); + } + #endif + #endif + + #ifdef PHYDM_BEAMFORMING_SUPPORT + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (dm_bdc_table->bdc_try_flag == 0) + #endif + #endif + { + phydm_antdiv_reset_statistic(dm, i); + } + } + +/* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n", + (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** bdc_rx_idle_update_counter = (( %d ))\n", + dm_bdc_table->bdc_rx_idle_update_counter); + + if (dm_bdc_table->bdc_rx_idle_update_counter == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "***Update RxIdle Antenna!!!\n"); + dm_bdc_table->bdc_rx_idle_update_counter = 30; + odm_update_rx_idle_ant(dm, rx_idle_ant); + } else { + dm_bdc_table->bdc_rx_idle_update_counter--; + PHYDM_DBG(dm, DBG_ANT_DIV, + "***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n"); + } + } else +#endif +#endif + odm_update_rx_idle_ant(dm, rx_idle_ant); +#else +#if (RTL8721D_SUPPORT) +if (dm->antdiv_gpio == ANTDIV_GPIO_PB1PB2PB26) { + if(odm_get_bb_reg(dm,R_0xc50,0x80) || odm_get_bb_reg(dm, R_0xa00, 0x8000)) + odm_update_rx_idle_ant_sp3t(dm, rx_idle_ant); +} +else +#endif + odm_update_rx_idle_ant(dm, rx_idle_ant); + +#endif /* @#if(DM_ODM_SUPPORT_TYPE == ODM_AP) */ + +/* @2 BDC Main Algorithm */ +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0) + odm_bd_ccoex_bfee_rx_div_arbitration(dm); + + dm_bdc_table->num_txbfee_client = 0; + dm_bdc_table->num_txbfer_client = 0; +#endif +#endif + + if (ant_div_max_rssi == 0) + dig_t->ant_div_rssi_max = dm->rssi_min; + else + dig_t->ant_div_rssi_max = ant_div_max_rssi; + + PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n"); +} + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + +void odm_s0s1_sw_ant_div_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + fat_tab->is_become_linked = false; + swat_tab->try_flag = SWAW_STEP_INIT; + swat_tab->double_chk_flag = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n", + __func__, fat_tab->is_become_linked); +} + +void phydm_sw_antdiv_train_time(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0; + u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0; + u8 train_time_temp; + + if (dm->traffic_load == TRAFFIC_HIGH) { + train_time_temp = swat_tab->train_time; + + if (swat_tab->train_time_flag == 3) { + high_traffic_train_time_l = 0xa; + + if (train_time_temp <= 16) + train_time_temp = high_traffic_train_time_l; + else + train_time_temp -= 16; + + } else if (swat_tab->train_time_flag == 2) { + train_time_temp -= 8; + high_traffic_train_time_l = 0xf; + } else if (swat_tab->train_time_flag == 1) { + train_time_temp -= 4; + high_traffic_train_time_l = 0x1e; + } else if (swat_tab->train_time_flag == 0) { + train_time_temp += 8; + high_traffic_train_time_l = 0x28; + } + + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) + high_traffic_train_time_l += 0xa; + } + + /* @-- */ + if (train_time_temp > high_traffic_train_time_u) + train_time_temp = high_traffic_train_time_u; + + else if (train_time_temp < high_traffic_train_time_l) + train_time_temp = high_traffic_train_time_l; + + swat_tab->train_time = train_time_temp; /*@10ms~200ms*/ + + PHYDM_DBG(dm, DBG_ANT_DIV, + "train_time_flag=((%d)), train_time=((%d))\n", + swat_tab->train_time_flag, + swat_tab->train_time); + + } else if ((dm->traffic_load == TRAFFIC_MID) || + (dm->traffic_load == TRAFFIC_LOW)) { + train_time_temp = swat_tab->train_time; + + if (swat_tab->train_time_flag == 3) { + low_traffic_train_time_l = 10; + if (train_time_temp < 50) + train_time_temp = low_traffic_train_time_l; + else + train_time_temp -= 50; + } else if (swat_tab->train_time_flag == 2) { + train_time_temp -= 30; + low_traffic_train_time_l = 36; + } else if (swat_tab->train_time_flag == 1) { + train_time_temp -= 10; + low_traffic_train_time_l = 40; + } else { + train_time_temp += 10; + low_traffic_train_time_l = 50; + } + + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) + low_traffic_train_time_l += 10; + } + + /* @-- */ + if (train_time_temp >= low_traffic_train_time_u) + train_time_temp = low_traffic_train_time_u; + + else if (train_time_temp <= low_traffic_train_time_l) + train_time_temp = low_traffic_train_time_l; + + swat_tab->train_time = train_time_temp; /*@10ms~200ms*/ + + PHYDM_DBG(dm, DBG_ANT_DIV, + "train_time_flag=((%d)) , train_time=((%d))\n", + swat_tab->train_time_flag, swat_tab->train_time); + + } else { + swat_tab->train_time = 0xc8; /*@200ms*/ + } +} + +void phydm_sw_antdiv_decision(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi; + u32 main_rssi, aux_rssi; + u8 rx_idle_ant = swat_tab->pre_ant; + u8 target_ant = swat_tab->pre_ant, next_ant = 0; + struct cmn_sta_info *entry = NULL; + u32 main_cnt = 0, aux_cnt = 0, main_sum = 0, aux_sum = 0; + u32 main_ctrl_cnt = 0, aux_ctrl_cnt = 0; + boolean is_by_ctrl_frame = false; + boolean cond_23d_main, cond_23d_aux; + u64 pkt_cnt_total = 0; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + entry = dm->phydm_sta_info[i]; + if (!is_sta_active(entry)) { + phydm_antdiv_reset_statistic(dm, i); + continue; + } + + /* @2 Caculate RSSI per Antenna */ + if (fat_tab->main_cnt[i] != 0 || fat_tab->aux_cnt[i] != 0) { + main_cnt = (u32)fat_tab->main_cnt[i]; + aux_cnt = (u32)fat_tab->aux_cnt[i]; + main_rssi = (main_cnt != 0) ? + (fat_tab->main_sum[i] / main_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? + (fat_tab->aux_sum[i] / aux_cnt) : 0; + if (dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710C) { + cond_23d_main = (aux_cnt > main_cnt) && + ((main_rssi - aux_rssi < 5) || + (aux_rssi > main_rssi)); + cond_23d_aux = (main_cnt > aux_cnt) && + ((aux_rssi - main_rssi < 5) || + (main_rssi > aux_rssi)); + if (swat_tab->pre_ant == MAIN_ANT) { + if (main_cnt == 0) + target_ant = (aux_cnt != 0) ? + AUX_ANT : + swat_tab->pre_ant; + else + target_ant = cond_23d_main ? + AUX_ANT : + swat_tab->pre_ant; + } else { + if (aux_cnt == 0) + target_ant = (main_cnt != 0) ? + MAIN_ANT : + swat_tab->pre_ant; + else + target_ant = cond_23d_aux ? + MAIN_ANT : + swat_tab->pre_ant; + } + } else { + if (swat_tab->pre_ant == MAIN_ANT) { + target_ant = (aux_rssi > main_rssi) ? + AUX_ANT : + swat_tab->pre_ant; + } else if (swat_tab->pre_ant == AUX_ANT) { + target_ant = (main_rssi > aux_rssi) ? + MAIN_ANT : + swat_tab->pre_ant; + } + } + } else { /*@CCK only case*/ + main_cnt = fat_tab->main_cnt_cck[i]; + aux_cnt = fat_tab->aux_cnt_cck[i]; + main_rssi = (main_cnt != 0) ? + (fat_tab->main_sum_cck[i] / main_cnt) : 0; + aux_rssi = (aux_cnt != 0) ? + (fat_tab->aux_sum_cck[i] / aux_cnt) : 0; + target_ant = (main_rssi == aux_rssi) ? + swat_tab->pre_ant : + ((main_rssi >= aux_rssi) ? + MAIN_ANT : AUX_ANT); + /*Use RSSI for CCK only case*/ + } + local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi; + local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d ))\n", + fat_tab->main_cnt_cck[i], fat_tab->aux_cnt_cck[i]); + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d ))\n", + fat_tab->main_cnt[i], fat_tab->aux_cnt[i]); + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** main_Cnt = (( %d )) , aux_Cnt = (( %d ))\n", + main_cnt, aux_cnt); + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** main_rssi= (( %d )) , aux_rssi = (( %d ))\n", + main_rssi, aux_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, + (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"); + + /* @2 Select RX Idle Antenna */ + + if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) { + rx_idle_ant = target_ant; + min_max_rssi = local_max_rssi; + PHYDM_DBG(dm, DBG_ANT_DIV, + "*** local_max_rssi-local_min_rssi = ((%d))\n", + (local_max_rssi - local_min_rssi)); + + if ((local_max_rssi - local_min_rssi) > 8) { + if (local_min_rssi != 0) { + swat_tab->train_time_flag = 3; + } else { + if (min_max_rssi > RSSI_CHECK_THRESHOLD) + swat_tab->train_time_flag = 0; + else + swat_tab->train_time_flag = 3; + } + } else if ((local_max_rssi - local_min_rssi) > 5) { + swat_tab->train_time_flag = 2; + } else if ((local_max_rssi - local_min_rssi) > 2) { + swat_tab->train_time_flag = 1; + } else { + swat_tab->train_time_flag = 0; + } + } + + /* @2 Select TX Antenna */ + if (target_ant == MAIN_ANT) + fat_tab->antsel_a[i] = ANT1_2G; + else + fat_tab->antsel_a[i] = ANT2_2G; + + phydm_antdiv_reset_statistic(dm, i); + pkt_cnt_total += (main_cnt + aux_cnt); + } + + if (swat_tab->is_sw_ant_div_by_ctrl_frame) { + odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE); + is_by_ctrl_frame = true; + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Control frame packet counter = %d, data frame packet counter = %llu\n", + swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame, pkt_cnt_total); + + if (min_max_rssi == 0xff || ((pkt_cnt_total < + (swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && + dm->phy_dbg_info.num_qry_beacon_pkt < 2)) { + min_max_rssi = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Check RSSI of control frame because min_max_rssi == 0xff\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, "is_by_ctrl_frame = %d\n", + is_by_ctrl_frame); + + if (is_by_ctrl_frame) { + main_ctrl_cnt = fat_tab->main_ctrl_cnt; + aux_ctrl_cnt = fat_tab->aux_ctrl_cnt; + main_rssi = (main_ctrl_cnt != 0) ? + (fat_tab->main_ctrl_sum / main_ctrl_cnt) : + 0; + aux_rssi = (aux_ctrl_cnt != 0) ? + (fat_tab->aux_ctrl_sum / aux_ctrl_cnt) : 0; + + if (main_ctrl_cnt <= 1 && + fat_tab->cck_ctrl_frame_cnt_main >= 1) + main_rssi = 0; + + if (aux_ctrl_cnt <= 1 && + fat_tab->cck_ctrl_frame_cnt_aux >= 1) + aux_rssi = 0; + + if (main_rssi != 0 || aux_rssi != 0) { + rx_idle_ant = (main_rssi == aux_rssi) ? + swat_tab->pre_ant : + ((main_rssi >= aux_rssi) ? + MAIN_ANT : AUX_ANT); + local_max_rssi = (main_rssi >= aux_rssi) ? + main_rssi : aux_rssi; + local_min_rssi = (main_rssi >= aux_rssi) ? + aux_rssi : main_rssi; + + if ((local_max_rssi - local_min_rssi) > 8) + swat_tab->train_time_flag = 3; + else if ((local_max_rssi - local_min_rssi) > 5) + swat_tab->train_time_flag = 2; + else if ((local_max_rssi - local_min_rssi) > 2) + swat_tab->train_time_flag = 1; + else + swat_tab->train_time_flag = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Control frame: main_rssi = %d, aux_rssi = %d\n", + main_rssi, aux_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "rx_idle_ant decided by control frame = %s\n", + (rx_idle_ant == MAIN_ANT ? + "MAIN" : "AUX")); + } + } + } + + fat_tab->min_max_rssi = min_max_rssi; + swat_tab->try_flag = SWAW_STEP_PEEK; + + if (swat_tab->double_chk_flag == 1) { + swat_tab->double_chk_flag = 0; + + if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " [Double check] min_max_rssi ((%d)) > %d again!!\n", + fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD); + + odm_update_rx_idle_ant(dm, rx_idle_ant); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[reset try_flag = 0] Training accomplished !!!]\n\n\n"); + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + " [Double check] min_max_rssi ((%d)) <= %d !!\n", + fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD); + + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? + AUX_ANT : MAIN_ANT; + swat_tab->try_flag = SWAW_STEP_PEEK; + swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[set try_flag=0] Normal state: Need to tryg again!!\n\n\n"); + } + } else { + if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD) + swat_tab->reset_idx = RSSI_CHECK_RESET_PERIOD; + + swat_tab->pre_ant = rx_idle_ant; + odm_update_rx_idle_ant(dm, rx_idle_ant); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[reset try_flag = 0] Training accomplished !!!]\n\n\n"); + } +} + +void odm_s0s1_sw_ant_div(void *dm_void, u8 step) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 value32; + u8 next_ant = 0; + + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + if (fat_tab->is_become_linked == true) { + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + if (dm->support_ic_type == ODM_RTL8723B) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Set REG 948[9:6]=0x0\n"); + odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0); + } + fat_tab->is_become_linked = dm->is_linked; + } + return; + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + + if (dm->support_ic_type == ODM_RTL8723B) { + value32 = odm_get_bb_reg(dm, R_0x864, 0x38); + +#if (RTL8723B_SUPPORT == 1) + if (value32 == 0x0) + odm_update_rx_idle_ant_8723b(dm, + MAIN_ANT, + ANT1_2G, + ANT2_2G); + else if (value32 == 0x1) + odm_update_rx_idle_ant_8723b(dm, + AUX_ANT, + ANT2_2G, + ANT1_2G); +#endif + + PHYDM_DBG(dm, DBG_ANT_DIV, + "8723B: First link! Force antenna to %s\n", + (value32 == 0x0 ? "MAIN" : "AUX")); + } + + if (dm->support_ic_type == ODM_RTL8723D) { + value32 = odm_get_bb_reg(dm, R_0x864, 0x38); +#if (RTL8723D_SUPPORT == 1) + if (value32 == 0x0) + odm_update_rx_idle_ant_8723d(dm, + MAIN_ANT, + ANT1_2G, + ANT2_2G); + else if (value32 == 0x1) + odm_update_rx_idle_ant_8723d(dm, + AUX_ANT, + ANT2_2G, + ANT1_2G); + PHYDM_DBG(dm, DBG_ANT_DIV, + "8723D: First link! Force antenna to %s\n", + (value32 == 0x0 ? "MAIN" : "AUX")); +#endif + } + if (dm->support_ic_type == ODM_RTL8710C) { +#if (RTL8710C_SUPPORT == 1) + value32 = (HAL_READ32(SYSTEM_CTRL_BASE, R_0x121c) & 0x800000); + if (value32 == 0x0) + odm_update_rx_idle_ant_8710c(dm, + MAIN_ANT, + ANT1_2G, + ANT2_2G); + else if (value32 == 0x1) + odm_update_rx_idle_ant_8710c(dm, + AUX_ANT, + ANT2_2G, + ANT1_2G); + PHYDM_DBG(dm, DBG_ANT_DIV, + "8710C: First link! Force antenna to %s\n", + (value32 == 0x0 ? "MAIN" : "AUX")); +#endif + } + fat_tab->is_become_linked = dm->is_linked; + } + } + + if (!(*fat_tab->p_force_tx_by_desc)) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n", + __LINE__, swat_tab->try_flag, step, + swat_tab->double_chk_flag); + + /* @ Handling step mismatch condition. */ + /* @ Peak step is not finished at last time. */ + /* @ Recover the variable and check again. */ + if (step != swat_tab->try_flag) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[step != try_flag] Need to Reset After Link\n"); + odm_sw_ant_div_rest_after_link(dm); + } + + if (swat_tab->try_flag == SWAW_STEP_INIT) { + swat_tab->try_flag = SWAW_STEP_PEEK; + swat_tab->train_time_flag = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[set try_flag = 0] Prepare for peek!\n\n"); + return; + + } else { + /* @1 Normal state (Begin Trying) */ + if (swat_tab->try_flag == SWAW_STEP_PEEK) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n", + dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt, + dm->traffic_load); + phydm_sw_antdiv_train_time(dm); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Current min_max_rssi is ((%d))\n", + fat_tab->min_max_rssi); + + /* @---reset index--- */ + if (swat_tab->reset_idx >= RSSI_CHECK_RESET_PERIOD) { + fat_tab->min_max_rssi = 0; + swat_tab->reset_idx = 0; + } + PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n", + swat_tab->reset_idx); + + swat_tab->reset_idx++; + + /* @---double check flag--- */ + if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD && + swat_tab->double_chk_flag == 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " min_max_rssi is ((%d)), and > %d\n", + fat_tab->min_max_rssi, + RSSI_CHECK_THRESHOLD); + + swat_tab->double_chk_flag = 1; + swat_tab->try_flag = SWAW_STEP_DETERMINE; + swat_tab->rssi_trying = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Test the current ant for (( %d )) ms again\n", + swat_tab->train_time); + odm_update_rx_idle_ant(dm, + fat_tab->rx_idle_ant); + odm_set_timer(dm, &swat_tab->sw_antdiv_timer, + swat_tab->train_time); /*@ms*/ + return; + } + + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? + AUX_ANT : MAIN_ANT; + + swat_tab->try_flag = SWAW_STEP_DETERMINE; + + if (swat_tab->reset_idx <= 1) + swat_tab->rssi_trying = 2; + else + swat_tab->rssi_trying = 1; + + odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[set try_flag=1] Normal state: Begin Trying!!\n"); + + } else if ((swat_tab->try_flag == SWAW_STEP_DETERMINE) && + (swat_tab->double_chk_flag == 0)) { + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? + AUX_ANT : MAIN_ANT; + swat_tab->rssi_trying--; + } + + /* @1 Decision state */ + if (swat_tab->try_flag == SWAW_STEP_DETERMINE && + swat_tab->rssi_trying == 0) { + phydm_sw_antdiv_decision(dm); + return; + } + } + + /* @1 4.Change TRX antenna */ + + PHYDM_DBG(dm, DBG_ANT_DIV, + "rssi_trying = (( %d )), ant: (( %s )) >>> (( %s ))\n", + swat_tab->rssi_trying, + (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"), + (next_ant == MAIN_ANT ? "MAIN" : "AUX")); + + odm_update_rx_idle_ant(dm, next_ant); + + /* @1 5.Reset Statistics */ + + fat_tab->rx_idle_ant = next_ant; + + if (dm->support_ic_type == ODM_RTL8723D || dm->support_ic_type == ODM_RTL8710C) { + + if (fat_tab->rx_idle_ant == MAIN_ANT) { + fat_tab->main_sum[0] = 0; + fat_tab->main_cnt[0] = 0; + fat_tab->main_sum_cck[0] = 0; + fat_tab->main_cnt_cck[0] = 0; + } else { + fat_tab->aux_sum[0] = 0; + fat_tab->aux_cnt[0] = 0; + fat_tab->aux_sum_cck[0] = 0; + fat_tab->aux_cnt_cck[0] = 0; + } + } + + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_SDIO) { + ODM_delay_us(200); + + if (fat_tab->rx_idle_ant == MAIN_ANT) { + fat_tab->main_sum[0] = 0; + fat_tab->main_cnt[0] = 0; + fat_tab->main_sum_cck[0] = 0; + fat_tab->main_cnt_cck[0] = 0; + } else { + fat_tab->aux_sum[0] = 0; + fat_tab->aux_cnt[0] = 0; + fat_tab->aux_sum_cck[0] = 0; + fat_tab->aux_cnt_cck[0] = 0; + } + } + } + /* @1 6.Set next timer (Trying state) */ + PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n", + (next_ant == MAIN_ANT ? "MAIN" : "AUX"), + swat_tab->train_time); + odm_set_timer(dm, &swat_tab->sw_antdiv_timer, swat_tab->train_time); + /*@ms*/ +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void odm_sw_antdiv_callback(struct phydm_timer_list *timer) +{ + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct sw_antenna_switch *swat_tab = &hal_data->DM_OutSrc.dm_swat_table; + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem); +#else + { +#if 0 + /* @dbg_print("SW_antdiv_Callback"); */ +#endif + odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); + } +#endif +#else + odm_schedule_work_item(&swat_tab->phydm_sw_antenna_switch_workitem); +#endif +} + +void odm_sw_antdiv_workitem_callback(void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + +#if 0 + /* @dbg_print("SW_antdiv_Workitem_Callback"); */ +#endif + odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE); +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +void odm_sw_antdiv_workitem_callback(void *context) +{ + void * + adapter = (void *)context; + HAL_DATA_TYPE + *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + +#if 0 + /*@dbg_print("SW_antdiv_Workitem_Callback");*/ +#endif + odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE); +} + +void odm_sw_antdiv_callback(void *function_context) +{ + struct dm_struct *dm = (struct dm_struct *)function_context; + void *padapter = dm->adapter; + if (*dm->is_net_closed == true) + return; + +#if 0 /* @Can't do I/O in timer callback*/ + odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE); +#else + rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, + padapter); +#endif +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) +void odm_sw_antdiv_callback(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n"); + odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE); +} +#endif + +void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + switch (step) { + case SWAW_STEP_PEEK: + swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame = 0; + swat_tab->is_sw_ant_div_by_ctrl_frame = true; + fat_tab->main_ctrl_cnt = 0; + fat_tab->aux_ctrl_cnt = 0; + fat_tab->main_ctrl_sum = 0; + fat_tab->aux_ctrl_sum = 0; + fat_tab->cck_ctrl_frame_cnt_main = 0; + fat_tab->cck_ctrl_frame_cnt_aux = 0; + fat_tab->ofdm_ctrl_frame_cnt_main = 0; + fat_tab->ofdm_ctrl_frame_cnt_aux = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n"); + break; + case SWAW_STEP_DETERMINE: + swat_tab->is_sw_ant_div_by_ctrl_frame = false; + PHYDM_DBG(dm, DBG_ANT_DIV, + "odm_S0S1_SwAntDivForAPMode(): Stop peek\n"); + break; + default: + swat_tab->is_sw_ant_div_by_ctrl_frame = false; + break; + } +} + +void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux, + u32 rx_pwdb_all) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_ctrl_sum += rx_pwdb_all; + fat_tab->main_ctrl_cnt++; + } else { + fat_tab->aux_ctrl_sum += rx_pwdb_all; + fat_tab->aux_ctrl_cnt++; + } +} + +void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void, + void *phy_info_void, + void *pkt_info_void + /* struct phydm_phyinfo_struct* phy_info, */ + /* struct phydm_perpkt_info_struct* pktinfo */ + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = NULL; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 rssi_cck; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + + if (dm->ant_div_type != S0S1_SW_ANTDIV) + return; + + /* @In try state */ + if (!swat_tab->is_sw_ant_div_by_ctrl_frame) + return; + + /* No HW error and match receiver address */ + if (!pktinfo->is_to_self) + return; + + swat_tab->pkt_cnt_sw_ant_div_by_ctrl_frame++; + + if (pktinfo->is_cck_rate) { + rssi_cck = phy_info->rx_mimo_signal_strength[RF_PATH_A]; + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? + ANT1_2G : ANT2_2G; + + if (fat_tab->antsel_rx_keep_0 == ANT1_2G) + fat_tab->cck_ctrl_frame_cnt_main++; + else + fat_tab->cck_ctrl_frame_cnt_aux++; + + odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0, + rssi_cck); + } else { + fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? + ANT1_2G : ANT2_2G; + + if (fat_tab->antsel_rx_keep_0 == ANT1_2G) + fat_tab->ofdm_ctrl_frame_cnt_main++; + else + fat_tab->ofdm_ctrl_frame_cnt_aux++; + + odm_antsel_statistics_ctrl(dm, fat_tab->antsel_rx_keep_0, + phy_info->rx_pwdb_all); + } +} + +#endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */ + +void odm_set_next_mac_addr_target(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct cmn_sta_info *entry; + u32 value32, i; + + PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__); + + if (dm->is_linked) { + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM) + fat_tab->train_idx = 0; + else + fat_tab->train_idx++; + + entry = dm->phydm_sta_info[fat_tab->train_idx]; + + if (is_sta_active(entry)) { + /*@Match MAC ADDR*/ + value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4]; + + odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/ + + value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0]; + + odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/ + + PHYDM_DBG(dm, DBG_ANT_DIV, + "fat_tab->train_idx=%d\n", + fat_tab->train_idx); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Training MAC addr = %x:%x:%x:%x:%x:%x\n", + entry->mac_addr[5], + entry->mac_addr[4], + entry->mac_addr[3], + entry->mac_addr[2], + entry->mac_addr[1], + entry->mac_addr[0]); + + break; + } + } + } +} + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + +void odm_fast_ant_training( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + u32 max_rssi_path_a = 0, pckcnt_path_a = 0; + u8 i, target_ant_path_a = 0; + boolean is_pkt_filter_macth_path_a = false; +#if (RTL8192E_SUPPORT == 1) + u32 max_rssi_path_b = 0, pckcnt_path_b = 0; + u8 target_ant_path_b = 0; + boolean is_pkt_filter_macth_path_b = false; +#endif + + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + phydm_fast_training_enable(dm, FAT_OFF); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + fat_tab->is_become_linked = dm->is_linked; + } + return; + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n"); + fat_tab->is_become_linked = dm->is_linked; + } + } + + if (!(*fat_tab->p_force_tx_by_desc)) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + + if (dm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); +#if (RTL8192E_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8192E) { + odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A */ /* ant combination=regB38[2:0]+1 */ + odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B */ /* ant combination=regB38[18:16]+1 */ + } +#endif + + PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__); + + /* @1 TRAINING STATE */ + if (fat_tab->fat_state == FAT_TRAINING_STATE) { + /* @2 Caculate RSSI per Antenna */ + + /* @3 [path-A]--------------------------- */ + for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */ + if (fat_tab->ant_rssi_cnt[i] == 0) + fat_tab->ant_ave_rssi[i] = 0; + else { + fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i]; + is_pkt_filter_macth_path_a = true; + } + + if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) { + max_rssi_path_a = fat_tab->ant_ave_rssi[i]; + pckcnt_path_a = fat_tab->ant_rssi_cnt[i]; + target_ant_path_a = i; + } else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) { + if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) { + max_rssi_path_a = fat_tab->ant_ave_rssi[i]; + pckcnt_path_a = fat_tab->ant_rssi_cnt[i]; + target_ant_path_a = i; + } + } + + PHYDM_DBG( + "*** ant-index : [ %d ], counter = (( %d )), Avg RSSI = (( %d ))\n", + i, fat_tab->ant_rssi_cnt[i], + fat_tab->ant_ave_rssi[i]); + } + +#if 0 +#if (RTL8192E_SUPPORT == 1) + /* @3 [path-B]--------------------------- */ + for (i = 0; i < (dm->fat_comb_b); i++) { + if (fat_tab->antRSSIcnt_pathB[i] == 0) + fat_tab->antAveRSSI_pathB[i] = 0; + else { /* @(ant_rssi_cnt[i] != 0) */ + fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i]; + is_pkt_filter_macth_path_b = true; + } + if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) { + max_rssi_path_b = fat_tab->antAveRSSI_pathB[i]; + pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i]; + target_ant_path_b = (u8)i; + } + if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) { + if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) { + max_rssi_path_b = fat_tab->antAveRSSI_pathB[i]; + target_ant_path_b = (u8)i; + } + } + if (dm->fat_print_rssi == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "***{path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d ))\n", + i, fat_tab->antSumRSSI_pathB[i], i, + fat_tab->antRSSIcnt_pathB[i], i, + fat_tab->antAveRSSI_pathB[i]); + } + } +#endif +#endif + + /* @1 DECISION STATE */ + + /* @2 Select TRX Antenna */ + + phydm_fast_training_enable(dm, FAT_OFF); + + /* @3 [path-A]--------------------------- */ + if (is_pkt_filter_macth_path_a == false) { +#if 0 + /* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */ +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "{path-A}: None Packet is matched\n"); + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + } else { + PHYDM_DBG( + "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n", + target_ant_path_a, max_rssi_path_a); + + /* @3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT */ + if (dm->support_ic_type == ODM_RTL8188E) + odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); + else if (dm->support_ic_type == ODM_RTL8192E) + odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */ + + /* @3 [ update TX ant ] */ + odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx)); + + if (target_ant_path_a == 0) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + } +#if 0 +#if (RTL8192E_SUPPORT == 1) + /* @3 [path-B]--------------------------- */ + if (is_pkt_filter_macth_path_b == false) { + if (dm->fat_print_rssi == 1) + PHYDM_DBG(dm, DBG_ANT_DIV, + "***[%d]{path-B}: None Packet is matched\n\n\n", + __LINE__); + } else { + if (dm->fat_print_rssi == 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n", + target_ant_path_b, max_rssi_path_b); + } + odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b); /* @Default RX is Omni, Optional RX is the best decision by FAT */ + odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1 //from TX Info */ + + fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b; + } +#endif +#endif + + /* @2 Reset counter */ + for (i = 0; i < (dm->fat_comb_a); i++) { + fat_tab->ant_sum_rssi[i] = 0; + fat_tab->ant_rssi_cnt[i] = 0; + } + /*@ + #if (RTL8192E_SUPPORT == 1) + for(i=0; i<=(dm->fat_comb_b); i++) + { + fat_tab->antSumRSSI_pathB[i] = 0; + fat_tab->antRSSIcnt_pathB[i] = 0; + } + #endif + */ + + fat_tab->fat_state = FAT_PREPARE_STATE; + return; + } + + /* @1 NORMAL STATE */ + if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n"); + + odm_set_next_mac_addr_target(dm); + + /* @2 Prepare Training */ + fat_tab->fat_state = FAT_TRAINING_STATE; + phydm_fast_training_enable(dm, FAT_ON); + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + /* @enable HW AntDiv */ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n"); + + odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */ + } +} + +void odm_fast_ant_training_callback( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (*(dm->is_net_closed) == true) + return; +#endif + +#if USE_WORKITEM + odm_schedule_work_item(&dm->fast_ant_training_workitem); +#else + PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__); + odm_fast_ant_training(dm); +#endif +} + +void odm_fast_ant_training_work_item_callback( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__); + odm_fast_ant_training(dm); +} + +#endif + +void odm_ant_div_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *swat_tab = &dm->dm_swat_table; + u8 i; + if (!(dm->support_ability & ODM_BB_ANT_DIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] Not Support Antenna Diversity Function\n"); + return; + } +/* @--- */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n"); + if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n"); + if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G)) + PHYDM_DBG(dm, DBG_ANT_DIV, + "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"); + +#endif + /* @--- */ + + /* @2 [--General---] */ + dm->antdiv_period = 0; + + fat_tab->is_become_linked = false; + fat_tab->ant_div_on_off = 0xff; + + for(i=0;i<3;i++) + fat_tab->ant_idx_vec[i]=i+1; /* initialize ant_idx_vec for SP3T */ + + +/* @3 - AP - */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#ifdef PHYDM_BEAMFORMING_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_bdc_init(dm); +#endif +#endif + +/* @3 - WIN - */ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + swat_tab->ant_5g = MAIN_ANT; + swat_tab->ant_2g = MAIN_ANT; +//#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) +// swat_tab->ant_2g = MAIN_ANT; +#endif + + /* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */ + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB); + + dm->ant_type = ODM_AUTO_ANT; + + fat_tab->rx_idle_ant = 0xff; + + if (dm->support_ic_type == ODM_RTL8710C) { + /* Soft ware*/ +#if (RTL8710C_SUPPORT == 1) + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17 | BIT16); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x10, 0x307);// 1: enable gpio db32 clock , 1: enable gpio pclock + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x08, 0x80000111); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0x1208, 0x800000); + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) | BIT18 | BIT17); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xdc, HAL_READ32(SYSTEM_CTRL_BASE, R_0xdc) & (~BIT16)); + HAL_WRITE32(SYSTEM_CTRL_BASE, R_0xac, HAL_READ32(SYSTEM_CTRL_BASE, R_0xac) | BIT24 | BIT6); + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8710C Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } +#endif + } + + /*to make RX-idle-antenna will be updated absolutly*/ + odm_update_rx_idle_ant(dm, MAIN_ANT); + phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0); + /* Timming issue: keep Rx ant after tx for ACK(5 x 3.2 mu = 16mu sec)*/ + + /* @2 [---Set TX Antenna---] */ + if (!fat_tab->p_force_tx_by_desc) { + fat_tab->force_tx_by_desc = 0; + fat_tab->p_force_tx_by_desc = &fat_tab->force_tx_by_desc; + } + PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_by_desc = %d\n", + *fat_tab->p_force_tx_by_desc); + + if (*fat_tab->p_force_tx_by_desc) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + + /* @2 [--88E---] */ + if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && + dm->ant_div_type != CG_TRX_HW_ANTDIV && + dm->ant_div_type != CG_TRX_SMART_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 88E Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_88e(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_88e(dm); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_88e(dm); +#endif +#endif + } + +/* @2 [--92E---] */ +#if (RTL8192E_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8192E) { + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && + dm->ant_div_type != CG_TRX_HW_ANTDIV && + dm->ant_div_type != CG_TRX_SMART_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8192E Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_92e(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_92e(dm); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_smart_hw_ant_div_init_92e(dm); +#endif + } +#endif + + /* @2 [--92F---] */ +#if (RTL8192F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8192F) { + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */ + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8192F Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + } + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_rx_hw_ant_div_init_92f(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_92f(dm); + } +#endif + +#if (RTL8197F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8197F) { + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8197F Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + phydm_rx_hw_ant_div_init_97f(dm); + } +#endif + +#if (RTL8197G_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8197G) { + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + + if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8197F Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + phydm_rx_hw_ant_div_init_97g(dm); + } +#endif + +#if (RTL8723F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8723F) { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8723F Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + phydm_rx_hw_ant_div_init_23f(dm); + } +#endif +/* @2 [--8723B---] */ +#if (RTL8723B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8723B) { + dm->ant_div_type = S0S1_SW_ANTDIV; + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (dm->ant_div_type != S0S1_SW_ANTDIV && + dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8723B Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8723b(dm); + else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723b(dm); + } +#endif +/*@2 [--8723D---]*/ +#if (RTL8723D_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8723D) { + if (fat_tab->p_default_s0_s1 == NULL) { + fat_tab->default_s0_s1 = 1; + fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1; + } + PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n", + *fat_tab->p_default_s0_s1); + + if (*fat_tab->p_default_s0_s1 == true) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else + odm_update_rx_idle_ant(dm, AUX_ANT); + + if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8723d(dm); + else if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8723d(dm); + else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8723D Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + } +#endif +#if (RTL8710C_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8710C) { + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8710c(dm); + else if(dm->ant_div_type == S0S1_SW_ANTDIV){ + if (fat_tab->p_default_s0_s1 == NULL){ + fat_tab->default_s0_s1 = 1; + fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1; + } + PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n", + *fat_tab->p_default_s0_s1); + if (*fat_tab->p_default_s0_s1 == true) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else + odm_update_rx_idle_ant(dm, AUX_ANT); + odm_s0s1_sw_ant_div_init_8710c(dm); + } + } +#endif +#if (RTL8721D_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8721D) { + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8721D Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8721d(dm); + } +#endif +/* @2 [--8811A 8821A---] */ +#if (RTL8821A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8821) { +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + dm->ant_div_type = HL_SW_SMART_ANT_TYPE1; + + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + odm_trx_hw_ant_div_init_8821a(dm); + phydm_hl_smart_ant_type1_init_8821a(dm); + } else +#endif + { +#ifdef ODM_CONFIG_BT_COEXIST + dm->ant_div_type = S0S1_SW_ANTDIV; +#else + dm->ant_div_type = CG_TRX_HW_ANTDIV; +#endif + + if (dm->ant_div_type != CG_TRX_HW_ANTDIV && + dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8821A & 8811A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_trx_hw_ant_div_init_8821a(dm); + else if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_init_8821a(dm); + } + } +#endif + +/* @2 [--8821C---] */ +#if (RTL8821C_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8821C) { + dm->ant_div_type = S0S1_SW_ANTDIV; + if (dm->ant_div_type != S0S1_SW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8821C Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + phydm_s0s1_sw_ant_div_init_8821c(dm); + odm_trx_hw_ant_div_init_8821c(dm); + } +#endif + +/* @2 [--8195B---] */ +#if (RTL8195B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8195B) { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8821C Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + odm_trx_hw_ant_div_init_8195b(dm); + } +#endif + +/* @2 [--8881A---] */ +#if (RTL8881A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8881A) { + /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */ + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_trx_hw_ant_div_init_8881a(dm); + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8881A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + + odm_trx_hw_ant_div_init_8881a(dm); + } +#endif + +/* @2 [--8812---] */ +#if (RTL8812A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8812) { + /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */ + + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8812A Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + odm_trx_hw_ant_div_init_8812a(dm); + } +#endif + +/*@[--8188F---]*/ +#if (RTL8188F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8188F) { + dm->ant_div_type = S0S1_SW_ANTDIV; + odm_s0s1_sw_ant_div_init_8188f(dm); + } +#endif + +/*@[--8822B---]*/ +#if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + + if (dm->ant_div_type != CG_TRX_HW_ANTDIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] 8822B Not Supprrt This AntDiv type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + return; + } + phydm_trx_hw_ant_div_init_22b(dm); +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + dm->ant_div_type = HL_SW_SMART_ANT_TYPE2; + + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) + phydm_hl_smart_ant_type2_init_8822b(dm); +#endif + } +#endif + +/*@PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",*/ +/*dm->support_ic_type);*/ +/*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",*/ +/* (dm->support_ability & ODM_BB_ANT_DIV)>>6);*/ +/*PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type);*/ +} + +void odm_ant_div(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; +#endif + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "tp_active_occur=((%d)), evm_method_enable=((%d))\n", + dm->tp_active_occur, fat_tab->evm_method_enable); + + if (dm->tp_active_occur == 1 && + fat_tab->evm_method_enable == 1) { + fat_tab->idx_ant_div_counter_5g = dm->antdiv_period; + fat_tab->idx_ant_div_counter_2g = dm->antdiv_period; + } + } +#endif + + if (*dm->band_type == ODM_BAND_5G) { + if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) { + fat_tab->idx_ant_div_counter_5g++; + return; + } else + fat_tab->idx_ant_div_counter_5g = 0; + } else if (*dm->band_type == ODM_BAND_2_4G) { + if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) { + fat_tab->idx_ant_div_counter_2g++; + return; + } else + fat_tab->idx_ant_div_counter_2g = 0; + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (fat_tab->enable_ctrl_frame_antdiv) { + if (dm->data_frame_num <= 10 && dm->is_linked) + fat_tab->use_ctrl_frame_antdiv = 1; + else + fat_tab->use_ctrl_frame_antdiv = 0; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", + fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num); + dm->data_frame_num = 0; + } + + { +#ifdef PHYDM_BEAMFORMING_SUPPORT + + enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm); + PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n", + dm->is_bt_continuous_turn); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv Beam Cap ] cap= ((%d))\n", beamform_cap); + if (!dm->is_bt_continuous_turn) { + if ((beamform_cap & BEAMFORMEE_CAP) && + (!(*fat_tab->is_no_csi_feedback))) { + /* @BFmee On && Div On->Div Off */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv : OFF ] BFmee ==1; cap= ((%d))\n", + beamform_cap); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv BF] is_no_csi_feedback= ((%d))\n", + *(fat_tab->is_no_csi_feedback)); + if (fat_tab->fix_ant_bfee == 0) { + odm_ant_div_on_off(dm, ANTDIV_OFF, + ANT_PATH_A); + fat_tab->fix_ant_bfee = 1; + } + return; + } else { /* @BFmee Off && Div Off->Div On */ + if (fat_tab->fix_ant_bfee == 1 && + dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv : ON ] BFmee ==0; cap=((%d))\n", + beamform_cap); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ AntDiv BF] is_no_csi_feedback= ((%d))\n", + *fat_tab->is_no_csi_feedback); + if (dm->ant_div_type != S0S1_SW_ANTDIV) + odm_ant_div_on_off(dm, ANTDIV_ON + , ANT_PATH_A) + ; + fat_tab->fix_ant_bfee = 0; + } + } + } else { + if (fat_tab->div_path_type == ANT_PATH_A) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + else if (fat_tab->div_path_type == ANT_PATH_B) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + else if (fat_tab->div_path_type == ANT_PATH_AB) + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB); + } +#endif + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + /* @----------just for fool proof */ + + if (dm->antdiv_rssi) + dm->debug_components |= DBG_ANT_DIV; + else + dm->debug_components &= ~DBG_ANT_DIV; + + if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) { + if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) { + if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } +#endif + + /* @---------- */ + + if (dm->antdiv_select == 1) + dm->ant_type = ODM_FIX_MAIN_ANT; + else if (dm->antdiv_select == 2) + dm->ant_type = ODM_FIX_AUX_ANT; + else { /* @if (dm->antdiv_select==0) */ + dm->ant_type = ODM_AUTO_ANT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*Stop Antenna diversity for CMW500 testing case*/ + if (dm->consecutive_idlel_time >= 10) { + dm->ant_type = ODM_FIX_MAIN_ANT; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n", + dm->consecutive_idlel_time); + } +#endif + } + + /*PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (%d), pre_ant_type= (%d)\n",*/ + /*dm->ant_type,dm->pre_ant_type); */ + + if (dm->ant_type != ODM_AUTO_ANT) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n", + (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX"); + + if (dm->ant_type != dm->pre_ant_type) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + + if (dm->ant_type == ODM_FIX_MAIN_ANT) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else if (dm->ant_type == ODM_FIX_AUX_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); + } + dm->pre_ant_type = dm->ant_type; + return; + } else { + if (dm->ant_type != dm->pre_ant_type) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + dm->pre_ant_type = dm->ant_type; + } +#if (defined(CONFIG_2T4R_ANTENNA)) + if (dm->ant_type2 != ODM_AUTO_ANT) { + PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n", + (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX"); + + if (dm->ant_type2 != dm->pre_ant_type2) { + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + + if (dm->ant_type2 == ODM_FIX_MAIN_ANT) + phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT); + else if (dm->ant_type2 == ODM_FIX_AUX_ANT) + phydm_update_rx_idle_ant_pathb(dm, AUX_ANT); + } + dm->pre_ant_type2 = dm->ant_type2; + return; + } + if (dm->ant_type2 != dm->pre_ant_type2) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + dm->pre_ant_type2 = dm->ant_type2; + +#endif + +/*@ ----------------------------------------------- */ +/*@ [--8188E--] */ + if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + if (dm->ant_div_type == CG_TRX_HW_ANTDIV || + dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_hw_ant_div(dm); + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ + (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(dm); +#endif + +#endif + } +/*@ [--8192E--] */ +#if (RTL8192E_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8192E) { + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV || + dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ + (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) + odm_fast_ant_training(dm); +#endif + } +#endif +/*@ [--8197F--] */ +#if (RTL8197F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8197F) { + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_hw_ant_div(dm); + } +#endif + +/*@ [--8197G--] */ +#if (RTL8197G_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8197G) { + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + odm_hw_ant_div(dm); + } +#endif + +/*@ [--8723F--] */ +#if (RTL8723F_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8723F) { + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); + } +#endif + +#if (RTL8723B_SUPPORT == 1) +/*@ [--8723B---] */ + else if (dm->support_ic_type == ODM_RTL8723B) { + if (phydm_is_bt_enable_8723b(dm)) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n"); + if (fat_tab->is_become_linked == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Set REG 948[9:6]=0x0\n"); + if (dm->support_ic_type == ODM_RTL8723B) + odm_set_bb_reg(dm, R_0x948, 0x3c0, 0x0) + ; + + fat_tab->is_become_linked = false; + } + } else { + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + #endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); + } + } +#endif +/*@ [--8723D--]*/ +#if (RTL8723D_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8723D) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) { + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + dm->antdiv_counter--; + } else { + dm->antdiv_counter--; + } + if (dm->antdiv_counter == 0) + dm->antdiv_counter = CONFIG_ANTDIV_PERIOD; + #endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_hw_ant_div(dm); + } + } +#endif +#if (RTL8721D_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8721D) { + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_hw_ant_div(dm); + } + } +#endif +#if (RTL8710C_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8710C) { + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + if (dm->antdiv_counter == CONFIG_ANTDIV_PERIOD) { + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + dm->antdiv_counter--; + } else { + dm->antdiv_counter--; + } + if (dm->antdiv_counter == 0) + dm->antdiv_counter = CONFIG_ANTDIV_PERIOD; + #endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_hw_ant_div(dm); + } + } +#endif +/*@ [--8821A--] */ +#if (RTL8821A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8821) { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + if (sat_tab->fix_beam_pattern_en != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", + sat_tab->fix_beam_pattern_codeword); + /*return;*/ + } else { + odm_fast_ant_training_hl_smart_antenna_type1(dm); + } + + } else + #endif + { + #ifdef ODM_CONFIG_BT_COEXIST + if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/ + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + " [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n"); + /*odm_set_bb_reg(dm, 0x8d4, BIT24, 1);*/ + if (fat_tab->is_become_linked == true) + odm_ant_div_on_off(dm, + ANTDIV_ON, + ANT_PATH_A); + } + + } else { /*@BT enabled*/ + + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + " [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n"); + /*odm_set_bb_reg(dm, 0x8d4, BIT24, 0);*/ + odm_ant_div_on_off(dm, ANTDIV_OFF, + ANT_PATH_A); + } + } + #endif + + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + #endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_hw_ant_div(dm); + } + } + } +#endif + +/*@ [--8821C--] */ +#if (RTL8821C_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8821C) { + if (!dm->is_bt_continuous_turn) { + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "is_bt_continuous_turn = ((%d)) ==> SW AntDiv\n", + dm->is_bt_continuous_turn); + + } else { + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "is_bt_continuous_turn = ((%d)) ==> HW AntDiv\n", + dm->is_bt_continuous_turn); + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + } + + if (fat_tab->force_antdiv_type) + dm->ant_div_type = fat_tab->antdiv_type_dbg; + + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + #endif + } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + odm_hw_ant_div(dm); + } + } +#endif + +/* @ [--8195B--] */ +#if (RTL8195B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8195B) { + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) { + odm_hw_ant_div(dm); + } + } +#endif + +/* @ [--8881A--] */ +#if (RTL8881A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8881A) + odm_hw_ant_div(dm); +#endif + +/*@ [--8812A--] */ +#if (RTL8812A_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8812) + odm_hw_ant_div(dm); +#endif + +#if (RTL8188F_SUPPORT == 1) +/*@ [--8188F--]*/ + else if (dm->support_ic_type == ODM_RTL8188F) { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK); + #endif + } +#endif + +/*@ [--8822B--]*/ +#if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + if (dm->ant_div_type == CG_TRX_HW_ANTDIV) + odm_hw_ant_div(dm); + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) { + if (sat_tab->fix_beam_pattern_en != 0) + PHYDM_DBG(dm, DBG_ANT_DIV, + " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", + sat_tab->fix_beam_pattern_codeword); + else + phydm_fast_ant_training_hl_smart_antenna_type2(dm); + } + #endif + } +#endif +} + +void odm_antsel_statistics(void *dm_void, void *phy_info_void, + u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method, + u8 is_cck_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct phydm_phyinfo_struct *phy_info = NULL; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + + if (method == RSSI_METHOD) { + if (is_cck_rate) { + if (antsel_tr_mux == fat_tab->ant_idx_vec[0]-1) { + /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/ + if (fat_tab->main_sum_cck[mac_id] > 65435) + return; + + fat_tab->main_sum_cck[mac_id] += (u16)utility; + fat_tab->main_cnt_cck[mac_id]++; + } else { + if (fat_tab->aux_sum_cck[mac_id] > 65435) + return; + + fat_tab->aux_sum_cck[mac_id] += (u16)utility; + fat_tab->aux_cnt_cck[mac_id]++; + } + + } else { /*ofdm rate*/ + + if (antsel_tr_mux == fat_tab->ant_idx_vec[0]-1) { + if (fat_tab->main_sum[mac_id] > 65435) + return; + + fat_tab->main_sum[mac_id] += (u16)utility; + fat_tab->main_cnt[mac_id]++; + } else { + if (fat_tab->aux_sum[mac_id] > 65435) + return; + + fat_tab->aux_sum[mac_id] += (u16)utility; + fat_tab->aux_cnt[mac_id]++; + } + } + } +#ifdef ODM_EVM_ENHANCE_ANTDIV + else if (method == EVM_METHOD) { + if (!fat_tab->get_stats) + return; + + if (dm->rate_ss == 1) { + phydm_statistics_evm_1ss(dm, phy_info, antsel_tr_mux, + mac_id, utility); + } else { /*@>= 2SS*/ + phydm_statistics_evm_2ss(dm, phy_info, antsel_tr_mux, + mac_id, utility); + } + + } else if (method == CRC32_METHOD) { + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_crc32_ok_cnt += utility; + fat_tab->main_crc32_fail_cnt++; + } else { + fat_tab->aux_crc32_ok_cnt += utility; + fat_tab->aux_crc32_fail_cnt++; + } + + } else if (method == TP_METHOD) { + if (!fat_tab->get_stats) + return; + if (utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) { + if (antsel_tr_mux == ANT1_2G) { + fat_tab->main_tp += (phy_rate_table[utility]) + << 5; + fat_tab->main_tp_cnt++; + } else { + fat_tab->aux_tp += (phy_rate_table[utility]) + << 5; + fat_tab->aux_tp_cnt++; + } + } + } +#endif +} + +void odm_process_rssi_smart(void *dm_void, void *phy_info_void, + void *pkt_info_void, u8 rx_power_ant0) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = NULL; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + + if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) && + pktinfo->is_packet_to_self && + fat_tab->fat_state == FAT_TRAINING_STATE) { + /* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */ + u8 antsel_tr_mux; + + antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) | + (fat_tab->antsel_rx_keep_1 << 1) | + fat_tab->antsel_rx_keep_0; + fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0; + fat_tab->ant_rssi_cnt[antsel_tr_mux]++; + } +} + +void odm_process_rssi_normal(void *dm_void, void *phy_info_void, + void *pkt_info_void, u8 rx_pwr0) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = NULL; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 rx_evm0, rx_evm1; + boolean b_main; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + rx_evm0 = phy_info->rx_mimo_signal_quality[0]; + rx_evm1 = phy_info->rx_mimo_signal_quality[1]; + + if (!(pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv)) + return; + + if (dm->ant_div_type == S0S1_SW_ANTDIV) { + if (pktinfo->is_cck_rate || + dm->support_ic_type == ODM_RTL8188F || dm->support_ic_type == ODM_RTL8710C) { + + b_main = (fat_tab->rx_idle_ant == MAIN_ANT); + fat_tab->antsel_rx_keep_0 = b_main ? ANT1_2G : ANT2_2G; + } + + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, + pktinfo->station_id, rx_pwr0, RSSI_METHOD, + pktinfo->is_cck_rate); + } else { + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, + pktinfo->station_id, rx_pwr0, RSSI_METHOD, + pktinfo->is_cck_rate); + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if (!(dm->support_ic_type & ODM_EVM_ANTDIV_IC)) + return; + if (pktinfo->is_cck_rate) + return; + + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, + pktinfo->station_id, rx_evm0, EVM_METHOD, + pktinfo->is_cck_rate); + odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, + pktinfo->station_id, pktinfo->data_rate, + TP_METHOD, pktinfo->is_cck_rate); + #endif + } +} + +void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void, + void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = NULL; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; +#if (defined(CONFIG_HL_SMART_ANTENNA)) + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 beam_tmp; + u8 next_ant; + u8 train_pkt_number; +#endif + boolean b_main; + u8 rx_power_ant0, rx_power_ant1; + u8 rx_evm_ant0, rx_evm_ant1; + u8 rssi_avg; + u64 rssi_linear = 0; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + rx_power_ant0 = phy_info->rx_mimo_signal_strength[0]; + rx_power_ant1 = phy_info->rx_mimo_signal_strength[1]; + rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0]; + rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1]; + + if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) { + if (rx_power_ant1 < 100) { + rssi_linear = phydm_db_2_linear(rx_power_ant0) + + phydm_db_2_linear(rx_power_ant1); + /* @Rounding and removing fractional bits */ + rssi_linear = (rssi_linear + + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; + /* @Calculate average RSSI */ + rssi_linear = DIVIDED_2(rssi_linear); + /* @averaged PWDB */ + rssi_avg = (u8)odm_convert_to_db(rssi_linear); + } + + } else { + rx_power_ant0 = (u8)phy_info->rx_pwdb_all; + rssi_avg = rx_power_ant0; + } + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE)) + phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/ + else +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +#ifdef CONFIG_FAT_PATCH + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) { + /*@[Beacon]*/ + if (pktinfo->is_packet_beacon) { + sat_tab->beacon_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "MatchBSSID_beacon_counter = ((%d))\n", + sat_tab->beacon_counter); + + if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) { + if (sat_tab->ant_num > 1) { + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); + } + + sat_tab->update_beam_idx++; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + sat_tab->pre_beacon_counter, + sat_tab->pkt_counter, + sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + /*@[data]*/ + else if (pktinfo->is_packet_to_self) { + if (sat_tab->pkt_skip_statistic_en == 0) { + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0); + */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n", + pktinfo->station_id, + sat_tab->pkt_counter, + fat_tab->antsel_rx_keep_0, + sat_tab->fast_training_beam_num, + rx_power_ant0); + + sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0; + sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++; + sat_tab->pkt_counter++; + +#if 1 + train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num]; +#else + train_pkt_number = sat_tab->per_beam_training_pkt_num; +#endif + + /*Swich Antenna erery N pkts*/ + if (sat_tab->pkt_counter == train_pkt_number) { + if (sat_tab->ant_num > 1) { + PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number); + next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + odm_update_rx_idle_ant(dm, next_ant); + } + + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n", + sat_tab->pre_beacon_counter, sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + } + + /*Swich Beam after switch "sat_tab->ant_num" antennas*/ + if (sat_tab->update_beam_idx == sat_tab->ant_num) { + sat_tab->update_beam_idx = 0; + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + odm_fast_ant_training_hl_smart_antenna_type1(dm); +#endif +#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); +#endif + + } else { + sat_tab->fast_training_beam_num++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Update Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, + sat_tab->fast_training_beam_num); + phydm_set_all_ant_same_beam_num(dm); + + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } + } +#else + + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { + if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && + pktinfo->is_packet_to_self && + fat_tab->fat_state == FAT_TRAINING_STATE) { + if (sat_tab->pkt_skip_statistic_en == 0) { + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0); + */ + PHYDM_DBG(dm, DBG_ANT_DIV, + "StaID[%d]: antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pktinfo->station_id, + fat_tab->antsel_rx_keep_0, + pktinfo->is_packet_to_self, + sat_tab->fast_training_beam_num, + rx_power_ant0); + + sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0; + sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++; + sat_tab->pkt_counter++; + + /*swich beam every N pkt*/ + if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) { + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + odm_fast_ant_training_hl_smart_antenna_type1(dm); +#endif +#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); +#endif + + } else { + sat_tab->fast_training_beam_num++; + phydm_set_all_ant_same_beam_num(dm); + + fat_tab->fat_state = FAT_TRAINING_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num); + } + } + } + } + } +#endif + else +#endif + if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) { + odm_process_rssi_smart(dm, phy_info, pktinfo, + rx_power_ant0); + } else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */ + odm_process_rssi_normal(dm, phy_info, pktinfo, + rx_power_ant0); + } +#if 0 +/* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n", + * pktinfo->is_cck_rate, phy_info->rx_pwdb_all); + * PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n", + * fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1, + * fat_tab->antsel_rx_keep_0); + */ +#endif +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT)) +void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + return; + + if (dm->support_ic_type == (ODM_RTL8723B | ODM_RTL8721D)) { +#if (RTL8723B_SUPPORT == 1 || RTL8721D_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]); +/*PHYDM_DBG(dm,DBG_ANT_DIV, + * "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], + * fat_tab->antsel_a[mac_id]); + */ +#endif + } else if (dm->support_ic_type == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]); +/*PHYDM_DBG(dm,DBG_ANT_DIV, + * "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], + * fat_tab->antsel_a[mac_id]); + */ +#endif + } else if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]); + SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]); + SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]); +/*PHYDM_DBG(dm,DBG_ANT_DIV, + * "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], + * fat_tab->antsel_a[mac_id]); + */ +#endif + } else if (dm->support_ic_type == ODM_RTL8821C) { +#if (RTL8821C_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]); +/*PHYDM_DBG(dm,DBG_ANT_DIV, + * "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n", + * mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], + * fat_tab->antsel_a[mac_id]); + */ +#endif + } else if (dm->support_ic_type == ODM_RTL8195B) { +#if (RTL8195B_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8195B(desc, fat_tab->antsel_a[mac_id]); +#endif + } else if (dm->support_ic_type == ODM_RTL8822B) { +#if (RTL8822B_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]); +#endif + + } +} +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + +void odm_set_tx_ant_by_tx_info( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid) +{ + struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/ + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + return; + + if (dm->support_ic_type == ODM_RTL8881A) { +#if 0 + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */ +#endif + pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8192E) { +#if 0 + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ +#endif + pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8197F) { +#if 0 + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ +#endif + pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8822B) { + pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16))); + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + } else if (dm->support_ic_type == ODM_RTL8188E) { +#if 0 + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/ +#endif + pdesc->Dword2 &= set_desc(~BIT(24)); + pdesc->Dword2 &= set_desc(~BIT(25)); + pdesc->Dword7 &= set_desc(~BIT(29)); + + pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24); + pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25); + pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29); + + } else if (dm->support_ic_type == ODM_RTL8812) { + /*@[path-A]*/ +#if 0 + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/ +#endif + + pdesc->Dword6 &= set_desc(~BIT(16)); + pdesc->Dword6 &= set_desc(~BIT(17)); + pdesc->Dword6 &= set_desc(~BIT(18)); + + pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16); + pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17); + pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18); + } +} + +#if 1 /*@def CONFIG_WLAN_HAL*/ +void odm_set_tx_ant_by_tx_info_hal( + struct rtl8192cd_priv *priv, + void *pdesc_data, + u16 aid) +{ + struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/ + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + + if (dm->ant_div_type == CGCS_RX_HW_ANTDIV) + return; + + if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A | + ODM_RTL8197F | ODM_RTL8822B)) { +#if 0 + /*panic_printk("[%s] [%d] **odm_set_tx_ant_by_tx_info_hal**\n", + * __FUNCTION__,__LINE__); + */ +#endif + pdescdata->ant_sel = 1; + pdescdata->ant_sel_a = fat_tab->antsel_a[aid]; + } +} +#endif /*@#ifdef CONFIG_WLAN_HAL*/ + +#endif + +void odm_ant_div_config(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n"); + /*@ + if(dm->support_ic_type==ODM_RTL8723B) + { + if((!dm->swat_tab.ANTA_ON || !dm->swat_tab.ANTB_ON)) + dm->support_ability &= ~(ODM_BB_ANT_DIV); + } + */ + #if (defined(CONFIG_2T3R_ANTENNA)) + #if (RTL8822B_SUPPORT == 1) + dm->rfe_type = ANT_2T3R_RFE_TYPE; + #endif + #endif + + #if (defined(CONFIG_2T4R_ANTENNA)) + #if (RTL8822B_SUPPORT == 1) + dm->rfe_type = ANT_2T4R_RFE_TYPE; + #endif + #endif + + if (dm->support_ic_type == ODM_RTL8723D) + dm->ant_div_type = S0S1_SW_ANTDIV; +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + + PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n"); + + if (dm->support_ic_type == ODM_RTL8723B) + dm->ant_div_type = S0S1_SW_ANTDIV; + + if (dm->support_ic_type == ODM_RTL8723D) + dm->ant_div_type = S0S1_SW_ANTDIV; +#elif (DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + + PHYDM_DBG(dm, DBG_ANT_DIV, "IOT Config Antenna Diversity\n"); + + if (dm->support_ic_type == ODM_RTL8721D) + dm->ant_div_type = CG_TRX_HW_ANTDIV; + if (dm->support_ic_type == ODM_RTL8710C){ + if(dm->cut_version > ODM_CUT_C) + dm->ant_div_type = CG_TRX_HW_ANTDIV; + else + dm->ant_div_type = S0S1_SW_ANTDIV; + } + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + + PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n"); + + /* @2 [ NOT_SUPPORT_ANTDIV ] */ +#if (defined(CONFIG_NOT_SUPPORT_ANTDIV)) + dm->support_ability &= ~(ODM_BB_ANT_DIV); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n"); + + /* @2 [ 2G&5G_SUPPORT_ANTDIV ] */ +#elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV)) + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n"); + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G); + + if (dm->support_ic_type & ODM_ANTDIV_SUPPORT) + dm->support_ability |= ODM_BB_ANT_DIV; + if (*dm->band_type == ODM_BAND_5G) { + #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); + panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); + #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) ||\ + defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); + panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); + #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"); + #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"); + #endif + } else if (*dm->band_type == ODM_BAND_2_4G) { + #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); + #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) ||\ + defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); + #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"); + #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"); + #endif + } + + /* @2 [ 5G_SUPPORT_ANTDIV ] */ +#elif (defined(CONFIG_5G_SUPPORT_ANTDIV)) + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); + panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G); + if (*dm->band_type == ODM_BAND_5G) { + if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC) + dm->support_ability |= ODM_BB_ANT_DIV; + #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY)) + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); + panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); + #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY)) + dm->ant_div_type = CG_TRX_HW_ANTDIV; + panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); + #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n"); + #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY)) + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n"); + #endif + } else if (*dm->band_type == ODM_BAND_2_4G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + } + + /* @2 [ 2G_SUPPORT_ANTDIV ] */ +#elif (defined(CONFIG_2G_SUPPORT_ANTDIV)) + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n"); + fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G); + if (*dm->band_type == ODM_BAND_2_4G) { + if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC) + dm->support_ability |= ODM_BB_ANT_DIV; + #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY)) + dm->ant_div_type = CGCS_RX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n"); + #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY)) + dm->ant_div_type = CG_TRX_HW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n"); + #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + dm->ant_div_type = CG_TRX_SMART_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n"); + #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY)) + dm->ant_div_type = S0S1_SW_ANTDIV; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n"); + #endif + } else if (*dm->band_type == ODM_BAND_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n"); + dm->support_ability &= ~(ODM_BB_ANT_DIV); + } +#endif + + if (!(dm->support_ic_type & ODM_ANTDIV_SUPPORT_IC)) { + fat_tab->ant_div_2g_5g = 0; + dm->support_ability &= ~(ODM_BB_ANT_DIV); + } +#endif + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n", + ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0)); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n", + dm->dm_fat_table.b_fix_tx_ant); +} + +void odm_ant_div_timers(void *dm_void, u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + if (state == INIT_ANTDIV_TIMMER) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_initialize_timer(dm, + &dm->dm_swat_table.sw_antdiv_timer, + (void *)odm_sw_antdiv_callback, NULL, + "sw_antdiv_timer"); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ + (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_initialize_timer(dm, &dm->fast_ant_training_timer, + (void *)odm_fast_ant_training_callback, + NULL, "fast_ant_training_timer"); +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer, + (void *)phydm_evm_antdiv_callback, NULL, + "evm_fast_ant_training_timer"); +#endif + } else if (state == CANCEL_ANTDIV_TIMMER) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_cancel_timer(dm, + &dm->dm_swat_table.sw_antdiv_timer); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ + (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_cancel_timer(dm, &dm->fast_ant_training_timer); +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer); +#endif + } else if (state == RELEASE_ANTDIV_TIMMER) { +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_release_timer(dm, + &dm->dm_swat_table.sw_antdiv_timer); +#elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ + (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + odm_release_timer(dm, &dm->fast_ant_training_timer); +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV + odm_release_timer(dm, &dm->evm_fast_ant_training_timer); +#endif + } +} + +void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + char help[] = "-h"; + u8 i, input_idx = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {0:auto, 1:fix main, 2:fix auto}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {antdiv_period}\n"); + #if (RTL8821C_SUPPORT == 1) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n"); + #endif + + } else if (dm_value[0] == 1) { + /*@fixed or auto antenna*/ + if (dm_value[1] == 0) { + dm->ant_type = ODM_AUTO_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: Auto\n"); + } else if (dm_value[1] == 1) { + dm->ant_type = ODM_FIX_MAIN_ANT; + + #if (RTL8710C_SUPPORT == 1) + dm->antdiv_select = 1; + #endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: Fix Main\n"); + } else if (dm_value[1] == 2) { + dm->ant_type = ODM_FIX_AUX_ANT; + + #if (RTL8710C_SUPPORT == 1) + dm->antdiv_select = 2; + #endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: Fix Aux\n"); + } + + if (dm->ant_type != ODM_AUTO_ANT) { + odm_stop_antenna_switch_dm(dm); + if (dm->ant_type == ODM_FIX_MAIN_ANT) + odm_update_rx_idle_ant(dm, MAIN_ANT); + else if (dm->ant_type == ODM_FIX_AUX_ANT) + odm_update_rx_idle_ant(dm, AUX_ANT); + } else { + phydm_enable_antenna_diversity(dm); + } + dm->pre_ant_type = dm->ant_type; + } else if (dm_value[0] == 2) { + /*@dynamic period for AntDiv*/ + dm->antdiv_period = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv_period=((%d))\n", dm->antdiv_period); + } + #if (RTL8821C_SUPPORT == 1) + else if (dm_value[0] == 3 && + dm->support_ic_type == ODM_RTL8821C) { + /*Only for 8821C*/ + if (dm_value[1] == 0) { + fat_tab->force_antdiv_type = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[8821C] AntDiv: Default\n"); + } else if (dm_value[1] == 1) { + fat_tab->force_antdiv_type = true; + fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[8821C] AntDiv: HW diversity\n"); + } else if (dm_value[1] == 2) { + fat_tab->force_antdiv_type = true; + fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[8821C] AntDiv: SW diversity\n"); + } + } + #endif + #ifdef ODM_EVM_ENHANCE_ANTDIV + else if (dm_value[0] == 4) { + if (dm_value[1] == 0) { + /*@init parameters for EVM AntDiv*/ + phydm_evm_sw_antdiv_init(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "init evm antdiv parameters\n"); + } else if (dm_value[1] == 1) { + /*training number for EVM AntDiv*/ + dm->antdiv_train_num = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_train_num = ((%d))\n", + dm->antdiv_train_num); + } else if (dm_value[1] == 2) { + /*training interval for EVM AntDiv*/ + dm->antdiv_intvl = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_intvl = ((%d))\n", + dm->antdiv_intvl); + } else if (dm_value[1] == 3) { + /*@function period for EVM AntDiv*/ + dm->evm_antdiv_period = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "evm_antdiv_period = ((%d))\n", + dm->evm_antdiv_period); + } else if (dm_value[1] == 100) {/*show parameters*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "ant_type = ((%d))\n", dm->ant_type); + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_train_num = ((%d))\n", + dm->antdiv_train_num); + PDM_SNPF(out_len, used, output + used, out_len - used, + "antdiv_intvl = ((%d))\n", + dm->antdiv_intvl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "evm_antdiv_period = ((%d))\n", + dm->evm_antdiv_period); + } + } + #ifdef CONFIG_2T4R_ANTENNA + else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/ + + if (dm_value[1] == 0) { + dm->ant_type2 = ODM_AUTO_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: PathB Auto\n"); + } else if (dm_value[1] == 1) { + dm->ant_type2 = ODM_FIX_MAIN_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: PathB Fix Main\n"); + } else if (dm_value[1] == 2) { + dm->ant_type2 = ODM_FIX_AUX_ANT; + PDM_SNPF(out_len, used, output + used, out_len - used, + "AntDiv: PathB Fix Aux\n"); + } + + if (dm->ant_type2 != ODM_AUTO_ANT) { + odm_stop_antenna_switch_dm(dm); + if (dm->ant_type2 == ODM_FIX_MAIN_ANT) + phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT); + else if (dm->ant_type2 == ODM_FIX_AUX_ANT) + phydm_update_rx_idle_ant_pathb(dm, AUX_ANT); + } else { + phydm_enable_antenna_diversity(dm); + } + dm->pre_ant_type2 = dm->ant_type2; + } + #endif + #endif + *_used = used; + *_out_len = out_len; +} + +void odm_ant_div_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + if (dm->ant_div_type == S0S1_SW_ANTDIV) + odm_s0s1_sw_ant_div_reset(dm); + #endif +} + +void odm_antenna_diversity_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_ant_div_config(dm); + odm_ant_div_init(dm); +} + +void odm_antenna_diversity(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (*dm->mp_mode) + return; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Return!!!] Not Support Antenna Diversity Function\n"); + return; + } + + if (dm->pause_ability & ODM_BB_ANT_DIV) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n", + dm->pause_lv_table.lv_antdiv); + return; + } + + odm_ant_div(dm); +} +#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/ diff --git a/hal/phydm/phydm_antdiv.h b/hal/phydm/phydm_antdiv.h new file mode 100644 index 0000000..0de588d --- /dev/null +++ b/hal/phydm/phydm_antdiv.h @@ -0,0 +1,547 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMANTDIV_H__ +#define __PHYDMANTDIV_H__ + +/*@#define ANTDIV_VERSION "2.0" //2014.11.04*/ +/*@#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ +/*@#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ +/*@#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen,remove 92c 92d 8723a*/ +/*@#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna*/ + /*@diversity when BT is enable for 8723B*/ +/*@#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not*/ + /*@need to check the antenna is control by BT,*/ + /*@because antenna diversity only works when */ + /*@BT is disable or radio off*/ +/*@#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart */ + /*@Antenna 2. Add 8188F SW S0S1 Antenna*/ + /*@Diversity*/ +/*@#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna*/ + /*@detection result from BT-coex. for 8723B,*/ + /*@not from PHYDM*/ +/*@#define ANTDIV_VERSION "3.6"*/ /*@2015.11.16 Stanley */ +/*@#define ANTDIV_VERSION "3.7" 2015.11.20 Dino Add SmartAnt FAT Patch */ +/*@#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic*/ + /*@training packet num */ +/*@#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for*/ + /*@converting single & two smtant, and add cmd*/ + /*@for adjust truth table */ +#define ANTDIV_VERSION "4.0" /*@2017.05.25 Mark, Add SW antenna diversity*/ + /*@for 8821c because HW transient issue */ + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#define ANTDIV_INIT 0xff +#define MAIN_ANT 1 /*@ant A or ant Main or S1*/ +#define AUX_ANT 2 /*@AntB or ant Aux or S0*/ +#define MAX_ANT 3 /* @3 for AP using*/ + +#define ANT1_2G 0 +/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT2_2G 1 +/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ +/*smart antenna*/ +#define SUPPORT_RF_PATH_NUM 4 +#define SUPPORT_BEAM_PATTERN_NUM 4 +#define NUM_ANTENNA_8821A 2 + +#define SUPPORT_BEAM_SET_PATTERN_NUM 16 + +#define NO_FIX_TX_ANT 0 +#define FIX_TX_AT_MAIN 1 +#define FIX_AUX_AT_MAIN 2 + +/* @Antenna Diversty Control type */ +#define ODM_AUTO_ANT 0 +#define ODM_FIX_MAIN_ANT 1 +#define ODM_FIX_AUX_ANT 2 + +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\ + ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\ + ODM_RTL8197F | ODM_RTL8721D | ODM_RTL8710C) +#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\ + ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B |\ + ODM_RTL8195B) +#define ODM_JGR3_ANTDIV_SUPPORT (ODM_RTL8197G | ODM_RTL8723F) +#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT |\ + ODM_JGR3_ANTDIV_SUPPORT) +#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) +#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B) + +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\ + ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\ + ODM_RTL8197F | ODM_RTL8197G|ODM_RTL8723F) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\ + ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B|ODM_RTL8723F) + +#define ODM_ANTDIV_SUPPORT_IC (ODM_ANTDIV_2G_SUPPORT_IC | ODM_ANTDIV_5G_SUPPORT_IC) + +#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B |\ + ODM_RTL8197G) + +#define ODM_ANTDIV_2G BIT(0) +#define ODM_ANTDIV_5G BIT(1) + +#define ANTDIV_ON 1 +#define ANTDIV_OFF 0 + +#define ANT_PATH_A 0 +#define ANT_PATH_B 1 +#define ANT_PATH_AB 2 + +#define FAT_ON 1 +#define FAT_OFF 0 + +#define TX_BY_DESC 1 +#define TX_BY_REG 0 + +#define RSSI_METHOD 0 +#define EVM_METHOD 1 +#define CRC32_METHOD 2 +#define TP_METHOD 3 + +#define INIT_ANTDIV_TIMMER 0 +#define CANCEL_ANTDIV_TIMMER 1 +#define RELEASE_ANTDIV_TIMMER 2 + +#define CRC32_FAIL 1 +#define CRC32_OK 0 + +#define evm_rssi_th_high 25 +#define evm_rssi_th_low 20 + +#define NORMAL_STATE_MIAN 1 +#define NORMAL_STATE_AUX 2 +#define TRAINING_STATE 3 + +#define FORCE_RSSI_DIFF 10 + +#define HT_IDX 16 +#define VHT_IDX 20 + +#define CSI_ON 1 +#define CSI_OFF 0 + +#define DIVON_CSIOFF 1 +#define DIVOFF_CSION 2 + +#define BDC_DIV_TRAIN_STATE 0 +#define bdc_bfer_train_state 1 +#define BDC_DECISION_STATE 2 +#define BDC_BF_HOLD_STATE 3 +#define BDC_DIV_HOLD_STATE 4 + +#define BDC_MODE_1 1 +#define BDC_MODE_2 2 +#define BDC_MODE_3 3 +#define BDC_MODE_4 4 +#define BDC_MODE_NULL 0xff + +/*SW S0S1 antenna diversity*/ +#define SWAW_STEP_INIT 0xff +#define SWAW_STEP_PEEK 0 +#define SWAW_STEP_DETERMINE 1 + +#define RSSI_CHECK_RESET_PERIOD 10 +#define RSSI_CHECK_THRESHOLD 50 + +/*@Hong Lin Smart antenna*/ +#define HL_SMTANT_2WIRE_DATA_LEN 24 + +#if (RTL8723D_SUPPORT == 1 || RTL8710C_SUPPORT == 1) + #ifndef CONFIG_ANTDIV_PERIOD + #define CONFIG_ANTDIV_PERIOD 1 + #endif +#endif +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + + +struct sw_antenna_switch { + u8 double_chk_flag; + /*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than*/ + /*@check this antenna again*/ + u8 try_flag; + s32 pre_rssi; + u8 cur_antenna; + u8 pre_ant; + u8 rssi_trying; + u8 reset_idx; + u8 train_time; + u8 train_time_flag; + /*@base on RSSI difference between two antennas*/ + struct phydm_timer_list sw_antdiv_timer; + u32 pkt_cnt_sw_ant_div_by_ctrl_frame; + boolean is_sw_ant_div_by_ctrl_frame; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM phydm_sw_antenna_switch_workitem; +#endif +#endif + + /* @AntDect (Before link Antenna Switch check) need to be moved*/ + u16 single_ant_counter; + u16 dual_ant_counter; + u16 aux_fail_detec_counter; + u16 retry_counter; + u8 swas_no_link_state; + u32 swas_no_link_bk_reg948; + boolean ANTA_ON; /*To indicate ant A is or not*/ + boolean ANTB_ON; /*@To indicate ant B is on or not*/ + boolean pre_aux_fail_detec; + boolean rssi_ant_dect_result; + u8 ant_5g; + u8 ant_2g; +}; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) +struct _BF_DIV_COEX_ { + boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM]; + boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; + u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; + + u8 bd_ccoex_type_wbfer; + u8 num_txbfee_client; + u8 num_txbfer_client; + u8 bdc_try_counter; + u8 bdc_hold_counter; + u8 bdc_mode; + u8 bdc_active_mode; + u8 BDC_state; + u8 bdc_rx_idle_update_counter; + u8 num_client; + u8 pre_num_client; + u8 num_bf_tar; + u8 num_div_tar; + + boolean is_all_div_sta_idle; + boolean is_all_bf_sta_idle; + boolean bdc_try_flag; + boolean BF_pass; + boolean DIV_pass; +}; +#endif +#endif + +struct phydm_fat_struct { + u8 bssid[6]; + u8 antsel_rx_keep_0; + u8 antsel_rx_keep_1; + u8 antsel_rx_keep_2; + u8 antsel_rx_keep_3; + u32 ant_sum_rssi[7]; + u32 ant_rssi_cnt[7]; + u32 ant_ave_rssi[7]; + u8 fat_state; + u8 fat_state_cnt; + u32 train_idx; + u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ht_cnt[HT_IDX]; + u16 aux_ht_cnt[HT_IDX]; + u16 main_vht_cnt[VHT_IDX]; + u16 aux_vht_cnt[VHT_IDX]; + u16 main_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u8 rx_idle_ant; + u8 rx_idle_ant2; + u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ + u8 ant_div_on_off; + u8 div_path_type; + boolean is_become_linked; + boolean get_stats; + u32 min_max_rssi; + u8 idx_ant_div_counter_2g; + u8 idx_ant_div_counter_5g; + u8 ant_div_2g_5g; + +#ifdef ODM_EVM_ENHANCE_ANTDIV + /*@For 1SS RX phy rate*/ + u32 main_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 aux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 main_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u32 aux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + + /*@For 2SS RX phy rate*/ + u32 main_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/ + u32 aux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/ + u32 main_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u32 aux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + + boolean evm_method_enable; + u8 target_ant_evm; + u8 target_ant_crc32; + u8 target_ant_tp; + u8 target_ant_enhance; + u8 pre_target_ant_enhance; + u16 main_mpdu_ok_cnt; + u16 aux_mpdu_ok_cnt; + + u32 crc32_ok_cnt; + u32 crc32_fail_cnt; + u32 main_crc32_ok_cnt; + u32 aux_crc32_ok_cnt; + u32 main_crc32_fail_cnt; + u32 aux_crc32_fail_cnt; + + u32 main_tp; + u32 aux_tp; + u32 main_tp_cnt; + u32 aux_tp_cnt; + + u8 pre_antdiv_rssi; + u8 pre_antdiv_tp; +#endif +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT)) + u32 cck_ctrl_frame_cnt_main; + u32 cck_ctrl_frame_cnt_aux; + u32 ofdm_ctrl_frame_cnt_main; + u32 ofdm_ctrl_frame_cnt_aux; + u32 main_ctrl_sum; + u32 aux_ctrl_sum; + u32 main_ctrl_cnt; + u32 aux_ctrl_cnt; +#endif + + u8 b_fix_tx_ant; + boolean fix_ant_bfee; + boolean enable_ctrl_frame_antdiv; + boolean use_ctrl_frame_antdiv; + boolean *is_no_csi_feedback; + boolean force_antdiv_type; + u8 antdiv_type_dbg; + u8 hw_antsw_occur; + u8 *p_force_tx_by_desc; + u8 force_tx_by_desc; + /*@A temp value, will hook to driver team's outer parameter later*/ + u8 *p_default_s0_s1; + u8 default_s0_s1; + u8 ant_idx_vec[3]; /* for SP3T only, added by Jiao Qi on June.6,2020*/ + + +}; + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +enum fat_state /*@Fast antenna training*/ +{ + FAT_BEFORE_LINK_STATE = 0, + FAT_PREPARE_STATE = 1, + FAT_TRAINING_STATE = 2, + FAT_DECISION_STATE = 3 +}; + +enum ant_div_type { + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, + S0S1_SW_ANTDIV = 0x06, /*@8723B intrnal switch S0 S1*/ + S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ + HL_SW_SMART_ANT_TYPE1 = 0x10, + /*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/ + /*@and each ant. is equipped with 4 antenna patterns*/ + HL_SW_SMART_ANT_TYPE2 = 0x11 + /*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ +}; + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ + +void odm_stop_antenna_switch_dm(void *dm_void); + +void phydm_enable_antenna_diversity(void *dm_void); + +void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/ + ); + +#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link + +void odm_sw_ant_div_rest_after_link(void *dm_void); + +void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path); + +void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch); + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + +void phydm_antdiv_reset_statistic(void *dm_void, u32 macid); + +void odm_update_rx_idle_ant(void *dm_void, u8 ant); + +void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant); + +void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant); + +void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len); + +#if (RTL8723B_SUPPORT == 1) +void odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant); +#endif + +#if (RTL8188F_SUPPORT == 1) +void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant); +#endif + +#if (RTL8723D_SUPPORT == 1) + +void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant); + +void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant, + u32 optional_ant); + +#endif + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void odm_sw_antdiv_callback(struct phydm_timer_list *timer); + +void odm_sw_antdiv_workitem_callback(void *context); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +void odm_sw_antdiv_workitem_callback(void *context); + +void odm_sw_antdiv_callback(void *function_context); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + +void odm_sw_antdiv_callback(void *dm_void); + +#endif + +void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step); + +void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux, + u32 rx_pwdb_all); + +void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void, + void *phy_info_void, + void *pkt_info_void); + +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV +void phydm_evm_sw_antdiv_init(void *dm_void); + +void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void); + +void phydm_antdiv_reset_rx_rate(void *dm_void); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_evm_antdiv_callback(struct phydm_timer_list *timer); + +void phydm_evm_antdiv_workitem_callback(void *context); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_evm_antdiv_callback(void *dm_void); + +void phydm_evm_antdiv_workitem_callback(void *context); + +#else +void phydm_evm_antdiv_callback(void *dm_void); +#endif + +#endif + +void odm_hw_ant_div(void *dm_void); + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\ + (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) +void odm_fast_ant_training( + void *dm_void); + +void odm_fast_ant_training_callback(void *dm_void); + +void odm_fast_ant_training_work_item_callback(void *dm_void); +#endif + +void odm_ant_div_init(void *dm_void); + +void odm_ant_div(void *dm_void); + +void odm_antsel_statistics(void *dm_void, void *phy_info_void, + u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method, + u8 is_cck_rate); + +void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void, + void *pkt_info_void); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + +struct tx_desc; +/*@declared tx_desc here or compile error happened when enabled 8822B*/ + +void odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, unsigned short aid); + +#if 1 /*@def def CONFIG_WLAN_HAL*/ +void odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv, + void *pdesc_data, u16 aid); +#endif /*@#ifdef CONFIG_WLAN_HAL*/ +#endif + +void odm_ant_div_config(void *dm_void); + +void odm_ant_div_timers(void *dm_void, u8 state); + +void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void odm_ant_div_reset(void *dm_void); + +void odm_antenna_diversity_init(void *dm_void); + +void odm_antenna_diversity(void *dm_void); +#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/ +#endif /*@#ifndef __ODMANTDIV_H__*/ diff --git a/hal/phydm/phydm_api.c b/hal/phydm/phydm_api.c new file mode 100644 index 0000000..4daaa5b --- /dev/null +++ b/hal/phydm/phydm_api.c @@ -0,0 +1,3754 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + * ************************************************************ + */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum channel_width bw = 0; + + /* @Check RX bandwidth */ + if (rxsc == 0) + bw = *dm->band_width; /*@full bw*/ + else if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if (rxsc >= 9 && rxsc <= 12) + bw = CHANNEL_WIDTH_40; + else /*if (rxsc >= 13)*/ + bw = CHANNEL_WIDTH_80; + + return bw; +} + +void phydm_reset_bb_hw_cnt(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@ Reset all counter when 1 */ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) { + odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0); + odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1); + } + #endif + odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1); + odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@ Reset all counter when 1 (including PMAC and PHY)*/ + /* Reset Page F counter*/ + odm_set_bb_reg(dm, R_0xb58, BIT(0), 1); + odm_set_bb_reg(dm, R_0xb58, BIT(0), 0); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x1); + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0x0); + } +} + +void phydm_dynamic_ant_weighting(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#ifdef DYN_ANT_WEIGHTING_SUPPORT + #if (RTL8197F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8197F)) + phydm_dynamic_ant_weighting_8197f(dm); + #endif + + #if (RTL8812A_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8812)) { + phydm_dynamic_ant_weighting_8812a(dm); + } + #endif + + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822B)) + phydm_dynamic_ant_weighting_8822b(dm); + #endif +#endif +} + +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if (!(dm->support_ic_type & + (ODM_RTL8192F | ODM_RTL8822B | ODM_RTL8812 | ODM_RTL8197F))) { + return; + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "echo dis_dym_ant_weighting {0/1}\n"); + + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) { + dm->is_disable_dym_ant_weighting = 1; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable dyn-ant-weighting\n"); + } else { + dm->is_disable_dym_ant_weighting = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Enable dyn-ant-weighting\n"); + } + } + *_used = used; + *_out_len = out_len; +} +#endif + +void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rx_ant = 0, tx_ant = 0; + u8 path_bitmap = 1; + + path_bitmap = (u8)phydm_gen_bitmask(num_rf_path); + + /*PHYDM_DBG(dm, ODM_COMP_INIT, "path_bitmap=0x%x\n", path_bitmap);*/ + + dm->tx_ant_status = path_bitmap; + dm->rx_ant_status = path_bitmap; + + if (num_rf_path == PDM_1SS) + return; + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & + (ODM_RTL8192F | ODM_RTL8192E | ODM_RTL8197F)) { + dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0xc04, 0x3); + dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x90c, 0x3); + } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8814A)) { + dm->rx_ant_status = (u8)odm_get_bb_reg(dm, R_0x808, 0xf); + dm->tx_ant_status = (u8)odm_get_bb_reg(dm, R_0x80c, 0xf); + } + #endif + /* @trx_ant_status are already updated in trx mode API in JGR3 ICs */ + + PHYDM_DBG(dm, ODM_COMP_INIT, "[%s]ant_status{tx,rx}={0x%x, 0x%x}\n", + __func__, dm->tx_ant_status, dm->rx_ant_status); +} + +void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path) +{ +#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT || RTL8812A_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ofdm_tx_path = 0x33; + + if (dm->num_rf_path == PDM_1SS) + return; + + switch (dm->support_ic_type) { + #if (RTL8192E_SUPPORT || RTL8192F_SUPPORT) + case ODM_RTL8192E: + case ODM_RTL8192F: + if (path == BB_PATH_A) + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313); + else if (path == BB_PATH_B) + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x82221323); + else if (path == BB_PATH_AB) + odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333); + + break; + #endif + + #if (RTL8812A_SUPPORT) + case ODM_RTL8812: + if (path == BB_PATH_A) + ofdm_tx_path = 0x11; + else if (path == BB_PATH_B) + ofdm_tx_path = 0x22; + else if (path == BB_PATH_AB) + ofdm_tx_path = 0x33; + + odm_set_bb_reg(dm, R_0x80c, 0xff00, ofdm_tx_path); + + break; + #endif + + default: + break; + } +#endif +} + +void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 val = 0; + + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8192F)) { +#if (RTL8192E_SUPPORT || RTL8192F_SUPPORT) + if (path == BB_PATH_A) + val = 1; + else if (path == BB_PATH_B) + val = 2; + else if (path == BB_PATH_AB) + val = 3; + + odm_set_bb_reg(dm, R_0xc04, 0xff, ((val << 4) | val)); + odm_set_bb_reg(dm, R_0xd04, 0xf, val); +#endif + } +#if (RTL8812A_SUPPORT || RTL8822B_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) { + if (path == BB_PATH_A) + val = 1; + else if (path == BB_PATH_B) + val = 2; + else if (path == BB_PATH_AB) + val = 3; + + odm_set_bb_reg(dm, R_0x808, MASKBYTE0, ((val << 4) | val)); + } +#endif +} + +void phydm_config_cck_rx_antenna_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & ODM_IC_1SS) + return; + + /*@CCK 2R CCA parameters*/ + odm_set_bb_reg(dm, R_0xa00, BIT(15), 0x0); /*@Disable Ant diversity*/ + odm_set_bb_reg(dm, R_0xa70, BIT(7), 0); /*@Concurrent CCA at LSB & USB*/ + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); /*RX path diversity enable*/ + odm_set_bb_reg(dm, R_0xa14, BIT(7), 0); /*r_en_mrc_antsel*/ + odm_set_bb_reg(dm, R_0xa20, (BIT(5) | BIT(4)), 1); /*@MBC weighting*/ + + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0xa08, BIT(28), 1); /*r_cck_2nd_sel_eco*/ + else if (dm->support_ic_type & ODM_RTL8814A) + odm_set_bb_reg(dm, R_0xa84, BIT(28), 1); /*@2R CCA only*/ +#endif +} + +void phydm_config_cck_rx_path(void *dm_void, enum bb_path path) +{ +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 path_div_select = 0; + u8 cck_path[2] = {0}; + u8 en_2R_path = 0; + u8 en_2R_mrc = 0; + u8 i = 0, j = 0; + u8 num_enable_path = 0; + u8 cck_mrc_max_path = 2; + + if (dm->support_ic_type & ODM_IC_1SS) + return; + + for (i = 0; i < 4; i++) { + if (path & BIT(i)) { /*@ex: PHYDM_ABCD*/ + num_enable_path++; + cck_path[j] = i; + j++; + } + if (num_enable_path >= cck_mrc_max_path) + break; + } + + if (num_enable_path > 1) { + path_div_select = 1; + en_2R_path = 1; + en_2R_mrc = 1; + } else { + path_div_select = 0; + en_2R_path = 0; + en_2R_mrc = 0; + } + /*@CCK_1 input signal path*/ + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), cck_path[0]); + /*@CCK_2 input signal path*/ + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), cck_path[1]); + /*@enable Rx path diversity*/ + odm_set_bb_reg(dm, R_0xa74, BIT(8), path_div_select); + /*@enable 2R Rx path*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(18), en_2R_path); + /*@enable 2R MRC*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(22), en_2R_mrc); + if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) { + if (path == BB_PATH_A) { + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0); + } else if (path == BB_PATH_B) {/*@for DC cancellation*/ + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 0); + odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 0); + } else if (path == BB_PATH_AB) { + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1); + odm_set_bb_reg(dm, R_0xa74, BIT(8), 1); + odm_set_bb_reg(dm, R_0xa2c, (BIT(18) | BIT(17)), 1); + odm_set_bb_reg(dm, R_0xa2c, (BIT(22) | BIT(21)), 1); + } + } else if (dm->support_ic_type & ODM_RTL8822B) { + if (path == BB_PATH_A) { + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 0); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 0); + } else { + odm_set_bb_reg(dm, R_0xa04, (BIT(27) | BIT(26)), 1); + odm_set_bb_reg(dm, R_0xa04, (BIT(25) | BIT(24)), 1); + } + } + +#endif +} + +void phydm_config_cck_tx_path(void *dm_void, enum bb_path path) +{ +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (path == BB_PATH_A) + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8); + else if (path == BB_PATH_B) + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x4); + else /*if (path == BB_PATH_AB)*/ + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc); +#endif +} + +void phydm_config_trx_path_v2(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8197G_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8198F_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0; + enum bb_path tx_path, rx_path, tx_path_ctrl; + boolean dbg_mode_en; + + if (!(dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8822C | + ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8198F))) + return; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + dbg_mode_en = (boolean)val[0]; + tx_path = (enum bb_path)val[1]; + rx_path = (enum bb_path)val[2]; + tx_path_ctrl = (enum bb_path)val[3]; + + if ((strcmp(input[1], help) == 0)) { + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8822B | + ODM_RTL8192F)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en} {tx_path} {rx_path} {ff:auto, else:1ss_tx_path}\n" + ); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en} {tx_path} {rx_path} {is_tx_2_path}\n"); + } + + } else if (dbg_mode_en) { + dm->is_disable_phy_api = false; + phydm_api_trx_mode(dm, tx_path, rx_path, tx_path_ctrl); + dm->is_disable_phy_api = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "T/RX path = 0x%x/0x%x, tx_path_ctrl=%d\n", + tx_path, rx_path, tx_path_ctrl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "T/RX path_en={0x%x, 0x%x}, tx_1ss=%d\n", + dm->tx_ant_status, dm->rx_ant_status, + dm->tx_1ss_status); + } else { + dm->is_disable_phy_api = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable API debug mode\n"); + } +#endif +} + +void phydm_config_trx_path_v1(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8192E_SUPPORT || RTL8812A_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0; + + if (!(dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812))) + return; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0:CCK, 1:OFDM} {1:TX, 2:RX} {1:path_A, 2:path_B, 3:path_AB}\n"); + + *_used = used; + *_out_len = out_len; + return; + + } else if (val[0] == 0) { + /* @CCK */ + if (val[1] == 1) { /*TX*/ + if (val[2] == 1) + phydm_config_cck_tx_path(dm, BB_PATH_A); + else if (val[2] == 2) + phydm_config_cck_tx_path(dm, BB_PATH_B); + else if (val[2] == 3) + phydm_config_cck_tx_path(dm, BB_PATH_AB); + } else if (val[1] == 2) { /*RX*/ + + phydm_config_cck_rx_antenna_init(dm); + + if (val[2] == 1) + phydm_config_cck_rx_path(dm, BB_PATH_A); + else if (val[2] == 2) + phydm_config_cck_rx_path(dm, BB_PATH_B); + else if (val[2] == 3) + phydm_config_cck_rx_path(dm, BB_PATH_AB); + } + } + /* OFDM */ + else if (val[0] == 1) { + if (val[1] == 1) /*TX*/ + phydm_config_ofdm_tx_path(dm, val[2]); + else if (val[1] == 2) /*RX*/ + phydm_config_ofdm_rx_path(dm, val[2]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n", + (val[0] == 1) ? "OFDM" : "CCK", + (val[1] == 1) ? "TX" : "RX", + (val[2] & 0x1) ? "A" : "", (val[2] & 0x2) ? "B" : "", + (val[2] & 0x4) ? "C" : "", + (val[2] & 0x8) ? "D" : ""); + + *_used = used; + *_out_len = out_len; +#endif +} + +void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) { + #if (RTL8192E_SUPPORT || RTL8812A_SUPPORT) + phydm_config_trx_path_v1(dm, input, _used, output, _out_len); + #endif + } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | + ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G | ODM_RTL8814B | ODM_RTL8198F)) { + #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\ + RTL8197G_SUPPORT || RTL8198F_SUPPORT) + phydm_config_trx_path_v2(dm, input, _used, output, _out_len); + #endif + } +} + +void phydm_tx_2path(void *dm_void) +{ +#if (defined(PHYDM_COMPILE_IC_2SS)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum bb_path rx_path = (enum bb_path)dm->rx_ant_status; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); + + + if (!(dm->support_ic_type & ODM_IC_2SS)) + return; + + #if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F | + ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) + phydm_api_trx_mode(dm, BB_PATH_AB, rx_path, BB_PATH_AB); + #endif + + #if (RTL8812A_SUPPORT || RTL8192E_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + phydm_config_cck_tx_path(dm, BB_PATH_AB); + phydm_config_ofdm_tx_path(dm, BB_PATH_AB); + } + #endif +#endif +} + +void phydm_stop_3_wire(void *dm_void, u8 set_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (set_type == PHYDM_SET) { + /*@[Stop 3-wires]*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x180c, 0x3, 0x0); + odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + odm_set_bb_reg(dm, R_0x410c, 0x3, 0x0); + odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1); + } + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + odm_set_bb_reg(dm, R_0x520c, 0x3, 0x0); + odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1); + odm_set_bb_reg(dm, R_0x530c, 0x3, 0x0); + odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1); + } + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0xc00, 0xf, 0x4); + odm_set_bb_reg(dm, R_0xe00, 0xf, 0x4); + } else { + odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0xf); + } + + } else { /*@if (set_type == PHYDM_REVERT)*/ + + /*@[Start 3-wires]*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x180c, 0x3, 0x3); + odm_set_bb_reg(dm, R_0x180c, BIT(28), 0x1); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + odm_set_bb_reg(dm, R_0x410c, 0x3, 0x3); + odm_set_bb_reg(dm, R_0x410c, BIT(28), 0x1); + } + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + odm_set_bb_reg(dm, R_0x520c, 0x3, 0x3); + odm_set_bb_reg(dm, R_0x520c, BIT(28), 0x1); + odm_set_bb_reg(dm, R_0x530c, 0x3, 0x3); + odm_set_bb_reg(dm, R_0x530c, BIT(28), 0x1); + } + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0xc00, 0xf, 0x7); + odm_set_bb_reg(dm, R_0xe00, 0xf, 0x7); + } else { + odm_set_bb_reg(dm, R_0x88c, 0xf00000, 0x0); + } + } +} + +u8 phydm_stop_ic_trx(void *dm_void, u8 set_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_api_stuc *api = &dm->api_table; + u8 i = 0; + boolean trx_idle_success = false; + u32 dbg_port_value = 0; + + if (set_type == PHYDM_SET) { + /*[Stop TRX]---------------------------------------------------------*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #if (RTL8723F_SUPPORT) + /*Judy 2020-0515*/ + /*set debug port to 0x0*/ + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0)) + return PHYDM_SET_FAIL; + #endif + for (i = 0; i < 100; i++) { + dbg_port_value = odm_get_bb_reg(dm, R_0x2db4, + MASKDWORD); + /* BB idle */ + if ((dbg_port_value & 0x1FFEFF3F) == 0 && + (dbg_port_value & 0xC0010000) == + 0xC0010000) { + PHYDM_DBG(dm, ODM_COMP_API, + "Stop trx wait for (%d) times\n", + i); + + trx_idle_success = true; + break; + } + } + } else { + /*set debug port to 0x0*/ + if (!phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0x0)) + return PHYDM_SET_FAIL; + for (i = 0; i < 100; i++) { + dbg_port_value = phydm_get_bb_dbg_port_val(dm); + /* PHYTXON && CCA_all */ + if (dm->support_ic_type & (ODM_RTL8721D | + ODM_RTL8710B | ODM_RTL8710C | + ODM_RTL8188F | ODM_RTL8723D)) { + if ((dbg_port_value & + (BIT(20) | BIT(15))) == 0) { + PHYDM_DBG(dm, ODM_COMP_API, + "Stop trx wait for (%d) times\n", + i); + + trx_idle_success = true; + break; + } + } else { + if ((dbg_port_value & + (BIT(17) | BIT(3))) == 0) { + PHYDM_DBG(dm, ODM_COMP_API, + "Stop trx wait for (%d) times\n", + i); + + trx_idle_success = true; + break; + } + } + ODM_delay_ms(1); + } + phydm_release_bb_dbg_port(dm); + } + + if (trx_idle_success) { + api->tx_queue_bitmap = odm_read_1byte(dm, R_0x522); + + /*pause all TX queue*/ + odm_set_mac_reg(dm, R_0x520, 0xff0000, 0xff); + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /*disable OFDM RX CCA*/ + odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*disable OFDM RX CCA*/ + odm_set_bb_reg(dm, R_0x838, BIT(1), 1); + } else { + api->rxiqc_reg1 = odm_read_4byte(dm, R_0xc14); + api->rxiqc_reg2 = odm_read_4byte(dm, R_0xc1c); + /* [ Set IQK Matrix = 0 ] + * equivalent to [ Turn off CCA] + */ + odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0xc1c, MASKDWORD, 0x0); + } + phydm_dis_cck_trx(dm, PHYDM_SET); + } else { + return PHYDM_SET_FAIL; + } + + return PHYDM_SET_SUCCESS; + + } else { /*@if (set_type == PHYDM_REVERT)*/ + /*Release all TX queue*/ + odm_write_1byte(dm, R_0x522, api->tx_queue_bitmap); + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /*@enable OFDM RX CCA*/ + odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0); + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*@enable OFDM RX CCA*/ + odm_set_bb_reg(dm, R_0x838, BIT(1), 0); + } else { + /* @[Set IQK Matrix = 0] equivalent to [ Turn off CCA]*/ + odm_write_4byte(dm, R_0xc14, api->rxiqc_reg1); + odm_write_4byte(dm, R_0xc1c, api->rxiqc_reg2); + } + phydm_dis_cck_trx(dm, PHYDM_REVERT); + return PHYDM_SET_SUCCESS; + } +} + +void phydm_dis_cck_trx(void *dm_void, u8 set_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_api_stuc *api = &dm->api_table; + + if (set_type == PHYDM_SET) { + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if(dm->support_ic_type & ODM_RTL8723F) { + api->ccktx_path = 1; + /* @disable CCK CCA */ + odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1); + /* @disable CCK Tx */ + odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x1); + } else { + api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0x1a04, + 0xf0000000); + /* @CCK RxIQ weighting = [0,0] */ + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3); + /* @disable CCK Tx */ + odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, 0x0); + } + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04, + 0xf0000000); + /* @disable CCK block */ + odm_set_bb_reg(dm, R_0x808, BIT(28), 0); + /* @disable CCK Tx */ + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0); + } else { + api->ccktx_path = (u8)odm_get_bb_reg(dm, R_0xa04, + 0xf0000000); + /* @disable whole CCK block */ + odm_set_bb_reg(dm, R_0x800, BIT(24), 0); + /* @disable CCK Tx */ + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x0); + } + } else if (set_type == PHYDM_REVERT) { + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if(dm->support_ic_type & ODM_RTL8723F) { + /* @enable CCK CCA */ + odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0); + /* @enable CCK Tx */ + odm_set_bb_reg(dm, R_0x2a00, BIT(1), 0x0); + } else { + /* @CCK RxIQ weighting = [1,1] */ + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0); + /* @enable CCK Tx */ + odm_set_bb_reg(dm, R_0x1a04, 0xf0000000, + api->ccktx_path); + } + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /* @enable CCK block */ + odm_set_bb_reg(dm, R_0x808, BIT(28), 1); + /* @enable CCK Tx */ + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, + api->ccktx_path); + } else { + /* @enable whole CCK block */ + odm_set_bb_reg(dm, R_0x800, BIT(24), 1); + /* @enable CCK Tx */ + odm_set_bb_reg(dm, R_0xa04, 0xf0000000, + api->ccktx_path); + } + } +} + +void phydm_bw_fixed_enable(void *dm_void, u8 enable) +{ +#ifdef CONFIG_BW_INDICATION + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean val = (enable == FUNC_ENABLE) ? 1 : 0; + + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B)) + odm_set_bb_reg(dm, R_0x840, BIT(4), val); + else if (dm->support_ic_type & ODM_RTL8822C) + odm_set_bb_reg(dm, R_0x878, BIT(28), val); +#endif +} + +void phydm_bw_fixed_setting(void *dm_void) +{ +#ifdef CONFIG_BW_INDICATION + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_api_stuc *api = &dm->api_table; + u8 bw = *dm->band_width; + u32 reg = 0, reg_mask = 0, reg_value = 0; + + if (!(dm->support_ic_type & ODM_DYM_BW_INDICATION_SUPPORT)) + return; + + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | + ODM_RTL8195B)) { + reg = R_0x840; + reg_mask = 0xf; + reg_value = api->pri_ch_idx; + } else if (dm->support_ic_type & ODM_RTL8822C) { + reg = R_0x878; + reg_mask = 0xc0000000; + reg_value = 0x0; + } + + switch (bw) { + case CHANNEL_WIDTH_80: + odm_set_bb_reg(dm, reg, reg_mask, reg_value); + break; + case CHANNEL_WIDTH_40: + odm_set_bb_reg(dm, reg, reg_mask, reg_value); + break; + default: + odm_set_bb_reg(dm, reg, reg_mask, 0x0); + } + + phydm_bw_fixed_enable(dm, FUNC_ENABLE); +#endif +} + +void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch) +{ +#if (RTL8821A_SUPPORT || RTL8881A_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A))) + return; + + /*Output Pin Settings*/ + + /*select DPDT_P and DPDT_N as output pin*/ + odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); + + /*@by WLAN control*/ + odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); + + /*@DPDT_N = 1b'0*/ /*@DPDT_P = 1b'0*/ + odm_set_bb_reg(dm, R_0xcb4, 0xFF, 77); + + if (ext_ant_switch == 1) { /*@2b'01*/ + odm_set_bb_reg(dm, R_0xcb4, (BIT(29) | BIT(28)), 1); + PHYDM_DBG(dm, ODM_COMP_API, "8821A ant swh=2b'01\n"); + } else if (ext_ant_switch == 2) { /*@2b'10*/ + odm_set_bb_reg(dm, R_0xcb4, BIT(29) | BIT(28), 2); + PHYDM_DBG(dm, ODM_COMP_API, "*8821A ant swh=2b'10\n"); + } +#endif +} + +void phydm_csi_mask_enable(void *dm_void, u32 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean en = false; + + en = (enable == FUNC_ENABLE) ? true : false; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xd2c, BIT(28), en); + PHYDM_DBG(dm, ODM_COMP_API, + "Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", en); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0xc0c, BIT(3), en); + PHYDM_DBG(dm, ODM_COMP_API, + "Enable CSI Mask: Reg 0xc0c[3] = ((0x%x))\n", en); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x874, BIT(0), en); + PHYDM_DBG(dm, ODM_COMP_API, + "Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", en); + } +} + +void phydm_clean_all_csi_mask(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xd40, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0xd44, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0xd48, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0xd4c, MASKDWORD, 0); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + u8 i = 0, idx_lmt = 0; + + if (dm->support_ic_type & + (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) + idx_lmt = 127; + else /*@for IC supporting 80 + 80*/ + idx_lmt = 255; + + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3); + odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1); + for (i = 0; i < idx_lmt; i++) { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, i); + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE0, 0x0); + } + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x880, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x884, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x888, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x88c, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x890, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x894, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x898, MASKDWORD, 0); + odm_set_bb_reg(dm, R_0x89c, MASKDWORD, 0); + } +} + +void phydm_set_csi_mask(void *dm_void, u32 tone_idx_tmp, u8 tone_direction) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 byte_offset = 0, bit_offset = 0; + u32 target_reg = 0; + u8 reg_tmp_value = 0; + u32 tone_num = 64; + u32 tone_num_shift = 0; + u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0; + + /* @calculate real tone idx*/ + if ((tone_idx_tmp % 10) >= 5) + tone_idx_tmp += 10; + + tone_idx_tmp = (tone_idx_tmp / 10); + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + tone_num = 64; + csi_mask_reg_p = 0xD40; + csi_mask_reg_n = 0xD48; + + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + tone_num = 128; + csi_mask_reg_p = 0x880; + csi_mask_reg_n = 0x890; + } + + if (tone_direction == FREQ_POSITIVE) { + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_p + byte_offset; + + } else { + tone_num_shift = tone_num; + + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = tone_num - tone_idx_tmp; + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_n + byte_offset; + } + + reg_tmp_value = odm_read_1byte(dm, target_reg); + PHYDM_DBG(dm, ODM_COMP_API, + "Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value); + reg_tmp_value |= BIT(bit_offset); + odm_write_1byte(dm, target_reg, reg_tmp_value); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", + (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value); +} + +void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*tone_idx X 10*/ + u32 nbi_128[NBI_128TONE] = {25, 55, 85, 115, 135, + 155, 185, 205, 225, 245, + 265, 285, 305, 335, 355, + 375, 395, 415, 435, 455, + 485, 505, 525, 555, 585, 615, 635}; + /*tone_idx X 10*/ + u32 nbi_256[NBI_256TONE] = {25, 55, 85, 115, 135, + 155, 175, 195, 225, 245, + 265, 285, 305, 325, 345, + 365, 385, 405, 425, 445, + 465, 485, 505, 525, 545, + 565, 585, 605, 625, 645, + 665, 695, 715, 735, 755, + 775, 795, 815, 835, 855, + 875, 895, 915, 935, 955, + 975, 995, 1015, 1035, 1055, + 1085, 1105, 1125, 1145, 1175, + 1195, 1225, 1255, 1275}; + u32 reg_idx = 0; + u32 i; + u8 nbi_table_idx = FFT_128_TYPE; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + nbi_table_idx = FFT_128_TYPE; + } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) { + nbi_table_idx = FFT_256_TYPE; + } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) { + if (bw == 80) + nbi_table_idx = FFT_256_TYPE; + else /*@20M, 40M*/ + nbi_table_idx = FFT_128_TYPE; + } + + if (nbi_table_idx == FFT_128_TYPE) { + for (i = 0; i < NBI_128TONE; i++) { + if (tone_idx_tmp < nbi_128[i]) { + reg_idx = i + 1; + break; + } + } + + } else if (nbi_table_idx == FFT_256_TYPE) { + for (i = 0; i < NBI_256TONE; i++) { + if (tone_idx_tmp < nbi_256[i]) { + reg_idx = i + 1; + break; + } + } + } + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0xc40, 0x1f000000, reg_idx); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", + reg_idx); + } else { + odm_set_bb_reg(dm, R_0x87c, 0xfc000, reg_idx); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", + reg_idx); + } +} + +void phydm_nbi_enable(void *dm_void, u32 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + val = (enable == FUNC_ENABLE) ? 1 : 0; + + PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val); + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (dm->support_ic_type & (ODM_RTL8192F | ODM_RTL8197F)) { + val = (enable == FUNC_ENABLE) ? 0xf : 0; + odm_set_bb_reg(dm, R_0xc50, 0xf000000, val); + } else { + odm_set_bb_reg(dm, R_0xc40, BIT(9), val); + } + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | + ODM_RTL8195B)) { + odm_set_bb_reg(dm, R_0x87c, BIT(13), val); + odm_set_bb_reg(dm, R_0xc20, BIT(28), val); + if (dm->rf_type > RF_1T1R) + odm_set_bb_reg(dm, R_0xe20, BIT(28), val); + } else { + odm_set_bb_reg(dm, R_0x87c, BIT(13), val); + } + } +} + +u8 phydm_find_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch, u32 *fc_in) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = *fc_in; + u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, + 108, 116, 124, 132, 140, + 149, 157, 165, 173}; + u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, + 149, 165}; + u32 *start_ch = &start_ch_per_40m[0]; + u32 num_start_channel = NUM_START_CH_40M; + u32 channel_offset = 0; + u32 i; + + /*@2.4G*/ + if (channel <= 14 && channel > 0) { + if (bw == 80) + return PHYDM_SET_FAIL; + + fc = 2412 + (channel - 1) * 5; + + if (bw == 40 && second_ch == PHYDM_ABOVE) { + if (channel >= 10) { + PHYDM_DBG(dm, ODM_COMP_API, + "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", + channel, second_ch); + return PHYDM_SET_FAIL; + } + fc += 10; + } else if (bw == 40 && (second_ch == PHYDM_BELOW)) { + if (channel <= 2) { + PHYDM_DBG(dm, ODM_COMP_API, + "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", + channel, second_ch); + return PHYDM_SET_FAIL; + } + fc -= 10; + } + } + /*@5G*/ + else if (channel >= 36 && channel <= 177) { + if (bw != 20) { + if (bw == 40) { + num_start_channel = NUM_START_CH_40M; + start_ch = &start_ch_per_40m[0]; + channel_offset = CH_OFFSET_40M; + } else if (bw == 80) { + num_start_channel = NUM_START_CH_80M; + start_ch = &start_ch_per_80m[0]; + channel_offset = CH_OFFSET_80M; + } + + for (i = 0; i < (num_start_channel - 1); i++) { + if (channel < start_ch[i + 1]) { + channel = start_ch[i] + channel_offset; + break; + } + } + PHYDM_DBG(dm, ODM_COMP_API, "Mod_CH = ((%d))\n", + channel); + } + + fc = 5180 + (channel - 36) * 5; + + } else { + PHYDM_DBG(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n", + channel); + return PHYDM_SET_FAIL; + } + + *fc_in = fc; + + return PHYDM_SET_SUCCESS; +} + +u8 phydm_find_intf_distance(void *dm_void, u32 bw, u32 fc, u32 f_interference, + u32 *tone_idx_tmp_in) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 bw_up = 0, bw_low = 0; + u32 int_distance = 0; + u32 tone_idx_tmp = 0; + u8 set_result = PHYDM_SET_NO_NEED; + + bw_up = fc + bw / 2; + bw_low = fc - bw / 2; + + PHYDM_DBG(dm, ODM_COMP_API, + "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, + fc, bw_up, f_interference); + + if (f_interference >= bw_low && f_interference <= bw_up) { + int_distance = DIFF_2(fc, f_interference); + /*@10*(int_distance /0.3125)*/ + tone_idx_tmp = (int_distance << 5); + PHYDM_DBG(dm, ODM_COMP_API, + "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", + int_distance, tone_idx_tmp / 10, + tone_idx_tmp % 10); + *tone_idx_tmp_in = tone_idx_tmp; + set_result = PHYDM_SET_SUCCESS; + } + + return set_result; +} + +u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, + u32 f_intf, u32 sec_ch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + set_result = PHYDM_SET_SUCCESS; + phydm_clean_all_csi_mask(dm); + + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_intf, + (((bw == 20) || (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_set_csi_mask(dm, tone_idx, direction); + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_csi_mask_enable(dm, enable); + else + phydm_csi_mask_enable(dm, FUNC_DISABLE); + + return set_result; +} + +boolean phydm_spur_case_mapping(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 channel = *dm->channel, bw = *dm->band_width; + boolean mapping_result = false; +#if (RTL8814B_SUPPORT == 1) + if (channel == 153 && bw == CHANNEL_WIDTH_20) + mapping_result = true; + else if (channel == 151 && bw == CHANNEL_WIDTH_40) + mapping_result = true; + else if (channel == 155 && bw == CHANNEL_WIDTH_80) + mapping_result = true; +#endif + return mapping_result; +} + +enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum odm_rf_band rf_band = ODM_RF_BAND_5G_LOW; + + if (central_ch <= 14) + rf_band = ODM_RF_BAND_2G; + else if (central_ch >= 36 && central_ch <= 64) + rf_band = ODM_RF_BAND_5G_LOW; + else if ((central_ch >= 100) && (central_ch <= 144)) + rf_band = ODM_RF_BAND_5G_MID; + else if (central_ch >= 149) + rf_band = ODM_RF_BAND_5G_HIGH; + else + PHYDM_DBG(dm, ODM_COMP_API, "mapping channel to band fail\n"); + + return rf_band; +} + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx) +{ +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_1b04 = 0, reg_1b08 = 0, reg_1b0c_11_10 = 0; + u32 reg_1b14 = 0, reg_1b18 = 0, reg_1b1c = 0; + u32 reg_1b28 = 0; + u32 reg_1bcc_5_0 = 0; + u32 reg_1b2c_27_16 = 0, reg_1b34 = 0, reg_1bd4 = 0; + u32 reg_180c = 0, reg_410c = 0, reg_520c = 0, reg_530c = 0; + u32 igi = 0; + u32 i = 0; + u32 psd_val = 0, psd_val_msb = 0, psd_val_lsb = 0, psd_max = 0; + u32 psd_status_temp = 0; + u16 poll_cnt = 0; + + /*read and record the ori. value*/ + reg_1b04 = odm_get_bb_reg(dm, R_0x1b04, MASKDWORD); + reg_1b08 = odm_get_bb_reg(dm, R_0x1b08, MASKDWORD); + reg_1b0c_11_10 = odm_get_bb_reg(dm, R_0x1b0c, 0xc00); + reg_1b14 = odm_get_bb_reg(dm, R_0x1b14, MASKDWORD); + reg_1b18 = odm_get_bb_reg(dm, R_0x1b18, MASKDWORD); + reg_1b1c = odm_get_bb_reg(dm, R_0x1b1c, MASKDWORD); + reg_1b28 = odm_get_bb_reg(dm, R_0x1b28, MASKDWORD); + reg_1bcc_5_0 = odm_get_bb_reg(dm, R_0x1bcc, 0x3f); + reg_1b2c_27_16 = odm_get_bb_reg(dm, R_0x1b2c, 0xfff0000); + reg_1b34 = odm_get_bb_reg(dm, R_0x1b34, MASKDWORD); + reg_1bd4 = odm_get_bb_reg(dm, R_0x1bd4, MASKDWORD); + igi = odm_get_bb_reg(dm, R_0x1d70, MASKDWORD); + reg_180c = odm_get_bb_reg(dm, R_0x180c, 0x3); + reg_410c = odm_get_bb_reg(dm, R_0x410c, 0x3); + reg_520c = odm_get_bb_reg(dm, R_0x520c, 0x3); + reg_530c = odm_get_bb_reg(dm, R_0x530c, 0x3); + + /*rf psd reg setting*/ + odm_set_bb_reg(dm, R_0x1b00, 0x6, path); /*path is RF_path*/ + odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, 0x80); + odm_set_bb_reg(dm, R_0x1b0c, 0xc00, 0x3); + odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, 0x1); +/*#if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/ + odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x82103D21); +/*#else*/ + /*odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, 0x821A3D21);*/ +/*#endif*/ + odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, 0x0); + odm_set_bb_reg(dm, R_0x1bcc, 0x3f, 0x3f); + odm_set_bb_reg(dm, R_0x8a0, 0xf, 0x0); /* AGC off */ + odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, 0x20202020); + + for (i = tone_idx - 1; i <= tone_idx + 1; i++) { + /*set psd tone_idx for detection*/ + odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, i); + /*one shot for RXIQK psd*/ + odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x1); + odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, 0x0); + + if (dm->support_ic_type & ODM_RTL8814B) + for (poll_cnt = 0; poll_cnt < 20; poll_cnt++) { + odm_set_bb_reg(dm, R_0x1bd4, 0x3f0000, 0x2b); + psd_status_temp = odm_get_bb_reg(dm, R_0x1bfc, + BIT(1)); + if (!psd_status_temp) + ODM_delay_us(10); + else + break; + } + else + ODM_delay_us(250); + + /*read RxIQK power*/ + odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x00250001); + if (dm->support_ic_type & ODM_RTL8814B) + psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x7ff0000); + else if (dm->support_ic_type & ODM_RTL8198F) + psd_val_msb = odm_get_bb_reg(dm, R_0x1bfc, 0x1f0000); + + odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, 0x002e0001); + psd_val_lsb = odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD); + if (dm->support_ic_type & ODM_RTL8814B) + psd_val = (psd_val_msb << 21) + (psd_val_lsb >> 11); + else if (dm->support_ic_type & ODM_RTL8198F) + psd_val = (psd_val_msb << 27) + (psd_val_lsb >> 5); + + if (psd_val > psd_max) + psd_max = psd_val; + } + + /*refill the ori. value*/ + odm_set_bb_reg(dm, R_0x1b00, 0x6, path); + odm_set_bb_reg(dm, R_0x1b04, MASKDWORD, reg_1b04); + odm_set_bb_reg(dm, R_0x1b08, MASKDWORD, reg_1b08); + odm_set_bb_reg(dm, R_0x1b0c, 0xc00, reg_1b0c_11_10); + odm_set_bb_reg(dm, R_0x1b14, MASKDWORD, reg_1b14); + odm_set_bb_reg(dm, R_0x1b18, MASKDWORD, reg_1b18); + odm_set_bb_reg(dm, R_0x1b1c, MASKDWORD, reg_1b1c); + odm_set_bb_reg(dm, R_0x1b28, MASKDWORD, reg_1b28); + odm_set_bb_reg(dm, R_0x1bcc, 0x3f, reg_1bcc_5_0); + odm_set_bb_reg(dm, R_0x1b2c, 0xfff0000, reg_1b2c_27_16); + odm_set_bb_reg(dm, R_0x1b34, MASKDWORD, reg_1b34); + odm_set_bb_reg(dm, R_0x1bd4, MASKDWORD, reg_1bd4); + odm_set_bb_reg(dm, R_0x8a0, 0xf, 0xf); /* AGC on */ + odm_set_bb_reg(dm, R_0x1d70, MASKDWORD, igi); + PHYDM_DBG(dm, ODM_COMP_API, "psd_max %d\n", psd_max); + + return psd_max; +#else + return 0; +#endif +} + +u8 phydm_find_intf_distance_jgr3(void *dm_void, u32 bw, u32 fc, + u32 f_interference, u32 *tone_idx_tmp_in) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 bw_up = 0, bw_low = 0; + u32 int_distance = 0; + u32 tone_idx_tmp = 0; + u8 set_result = PHYDM_SET_NO_NEED; + u8 channel = *dm->channel; + + bw_up = 1000 * (fc + bw / 2); + bw_low = 1000 * (fc - bw / 2); + fc = 1000 * fc; + + PHYDM_DBG(dm, ODM_COMP_API, + "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, + fc, bw_up, f_interference); + + if (f_interference >= bw_low && f_interference <= bw_up) { + int_distance = DIFF_2(fc, f_interference); + /*@10*(int_distance /0.3125)*/ + if (channel < 15 && + (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F))) + tone_idx_tmp = int_distance / 312; + else + tone_idx_tmp = ((int_distance + 156) / 312); + PHYDM_DBG(dm, ODM_COMP_API, + "int_distance = ((%d)) , tone_idx_tmp = ((%d))\n", + int_distance, tone_idx_tmp); + *tone_idx_tmp_in = tone_idx_tmp; + set_result = PHYDM_SET_SUCCESS; + } + + return set_result; +} + +u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, + u32 f_intf, u32 sec_ch, u8 wgt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + phydm_csi_mask_enable(dm, FUNC_ENABLE); + phydm_clean_all_csi_mask(dm); + phydm_csi_mask_enable(dm, FUNC_DISABLE); + set_result = PHYDM_SET_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s)), wgt = ((%d))\n", + ch, bw, f_intf, + (((bw == 20) || (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L"), wgt); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= 1000 * fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_csi_mask_enable(dm, FUNC_ENABLE); + phydm_set_csi_mask_jgr3(dm, tone_idx, direction, + wgt); + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + if (!(set_result == PHYDM_SET_SUCCESS)) + phydm_csi_mask_enable(dm, FUNC_DISABLE); + } + + return set_result; +} + +void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 wgt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 multi_tone_idx_tmp = 0; + u32 reg_tmp = 0; + u32 tone_num = 64; + u32 table_addr = 0; + u32 addr = 0; + u8 rf_bw = 0; + u8 value = 0; + u8 channel = *dm->channel; + + rf_bw = odm_read_1byte(dm, R_0x9b0); + if (((rf_bw & 0xc) >> 2) == 0x2) + tone_num = 128; /* @RF80 : tone(-1) at tone_idx=255 */ + else + tone_num = 64; /* @RF20/40 : tone(-1) at tone_idx=127 */ + + if (tone_direction == FREQ_POSITIVE) { + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + } else { + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = (tone_num << 1) - tone_idx_tmp; + } + table_addr = tone_idx_tmp >> 1; + + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "Pre Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3); + odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1); + + if (channel < 15 && + (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8198F))) { + if (tone_idx_tmp % 2 == 1) { + if (tone_direction == FREQ_POSITIVE) { + /*===Tone 1===*/ + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = (BIT(3) | (wgt & 0x7)) << 4; + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + /*===Tone 2===*/ + value = 0; + multi_tone_idx_tmp = tone_idx_tmp + 1; + table_addr = multi_tone_idx_tmp >> 1; + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = (BIT(3) | (wgt & 0x7)); + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + } else { + /*===Tone 1 & 2===*/ + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = ((BIT(3) | (wgt & 0x7)) << 4) | + (BIT(3) | (wgt & 0x7)); + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + } + } else { + if (tone_direction == FREQ_POSITIVE) { + /*===Tone 1 & 2===*/ + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = ((BIT(3) | (wgt & 0x7)) << 4) | + (BIT(3) | (wgt & 0x7)); + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone 1 & 2 idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + } else { + /*===Tone 1===*/ + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = (BIT(3) | (wgt & 0x7)); + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone 1 idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + + /*===Tone 2===*/ + value = 0; + multi_tone_idx_tmp = tone_idx_tmp - 1; + table_addr = multi_tone_idx_tmp >> 1; + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = (BIT(3) | (wgt & 0x7)) << 4; + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone 2 idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + } + } + } else { + if ((dm->support_ic_type & (ODM_RTL8814B)) && + phydm_spur_case_mapping(dm)) { + if (!(tone_idx_tmp % 2)) { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = ((BIT(3) | (((wgt + 4) <= 7 ? (wgt + + 4) : 7) & 0x7)) << 4) | (BIT(3) | + (wgt & 0x7)); + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + if (tone_idx_tmp == 0) + table_addr = tone_num - 1; + else + table_addr = table_addr - 1; + if (tone_idx_tmp != tone_num) { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = (BIT(3) | (((wgt + 4) <= 7 ? + (wgt + 4) : 7) & 0x7)) << 4; + odm_set_bb_reg(dm, R_0x1d94, 0xff, + value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask Reg0x1d94 = ((0x%x))\n", + reg_tmp); + } + } else { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = ((BIT(3) | (wgt & 0x7)) << 4) | + (BIT(3) | (((wgt + 4) <= 7 ? (wgt + + 4) : 7) & 0x7)); + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + if (tone_idx_tmp == (tone_num << 1) - 1) + table_addr = 0; + else + table_addr = table_addr + 1; + if (tone_idx_tmp != tone_num - 1) { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, + (table_addr & 0xff)); + value = (BIT(3) | (((wgt + 4) <= 7 ? + (wgt + 4) : 7) & 0x7)); + odm_set_bb_reg(dm, R_0x1d94, 0xff, + value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask Reg0x1d94 = ((0x%x))\n", + reg_tmp); + } + } + } else { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, (table_addr & + 0xff)); + if (tone_idx_tmp % 2) + value = (BIT(3) | (wgt & 0x7)) << 4; + else + value = BIT(3) | (wgt & 0x7); + + odm_set_bb_reg(dm, R_0x1d94, 0xff, value); + reg_tmp = odm_read_4byte(dm, R_0x1d94); + PHYDM_DBG(dm, ODM_COMP_API, + "New Mask tone idx[%d]: Reg0x1d94 = ((0x%x))\n", + tone_idx_tmp, reg_tmp); + } + } + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0); +} + +void phydm_nbi_reset_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_set_bb_reg(dm, R_0x818, BIT(3), 1); + odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0); + odm_set_bb_reg(dm, R_0x818, BIT(3), 0); + odm_set_bb_reg(dm, R_0x818, BIT(11), 0); + #if RTL8814B_SUPPORT + if (dm->support_ic_type & ODM_RTL8814B) { + odm_set_bb_reg(dm, R_0x1944, 0x300, 0x3); + odm_set_bb_reg(dm, R_0x4044, 0x300, 0x3); + odm_set_bb_reg(dm, R_0x5044, 0x300, 0x3); + odm_set_bb_reg(dm, R_0x5144, 0x300, 0x3); + odm_set_bb_reg(dm, R_0x810, 0xf, 0x0); + odm_set_bb_reg(dm, R_0x810, 0xf0000, 0x0); + odm_set_bb_reg(dm, R_0xc24, MASKDWORD, 0x406000ff); + } + #endif +} + +u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + phydm_nbi_reset_jgr3(dm); + set_result = PHYDM_SET_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_intf, + (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) || + (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance_jgr3(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= 1000 * fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_set_nbi_reg_jgr3(dm, tone_idx, direction, + path); + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_nbi_enable_jgr3(dm, enable, path); + else + phydm_nbi_enable_jgr3(dm, FUNC_DISABLE, path); + + if (dm->support_ic_type & ODM_RTL8814B) + odm_set_bb_reg(dm, R_0x1d3c, BIT(19), 0); + + return set_result; +} + +void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_tmp_value = 0; + u32 tone_num = 64; + u32 addr = 0; + u8 rf_bw = 0; + + rf_bw = odm_read_1byte(dm, R_0x9b0); + if (((rf_bw & 0xc) >> 2) == 0x2) + tone_num = 128; /* RF80 : tone-1 at tone_idx=255 */ + else + tone_num = 64; /* RF20/40 : tone-1 at tone_idx=127 */ + + if (tone_direction == FREQ_POSITIVE) { + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + } else { + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = (tone_num << 1) - tone_idx_tmp; + } + /*Mark the tone idx for Packet detection*/ + #if RTL8814B_SUPPORT + if (dm->support_ic_type & ODM_RTL8814B) { + odm_set_bb_reg(dm, R_0xc24, 0xff, 0xff); + if ((*dm->channel == 5) && + (*dm->band_width == CHANNEL_WIDTH_40)) + odm_set_bb_reg(dm, R_0xc24, 0xff00, 0x1a); + else + odm_set_bb_reg(dm, R_0xc24, 0xff00, tone_idx_tmp); + } + #endif + switch (path) { + case RF_PATH_A: + odm_set_bb_reg(dm, R_0x1944, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-A = ((0x%x))\n", + tone_idx_tmp, tone_idx_tmp); + break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case RF_PATH_B: + odm_set_bb_reg(dm, R_0x4044, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-B = ((0x%x))\n", + tone_idx_tmp, tone_idx_tmp); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case RF_PATH_C: + odm_set_bb_reg(dm, R_0x5044, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-C = ((0x%x))\n", + tone_idx_tmp, tone_idx_tmp); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case RF_PATH_D: + odm_set_bb_reg(dm, R_0x5144, 0x001FF000, tone_idx_tmp); + PHYDM_DBG(dm, ODM_COMP_API, + "Set tone idx[%d]:PATH-D = ((0x%x))\n", + tone_idx_tmp, tone_idx_tmp); + break; + #endif + default: + break; + } +} + +void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean val = false; + + val = (enable == FUNC_ENABLE) ? true : false; + + PHYDM_DBG(dm, ODM_COMP_API, "Enable NBI=%d\n", val); + + if (dm->support_ic_type & ODM_RTL8814B) { + odm_set_bb_reg(dm, R_0x1d3c, BIT(19), val); + odm_set_bb_reg(dm, R_0x818, BIT(3), val); + } else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) { + odm_set_bb_reg(dm, R_0x818, BIT(3), !val); + } + odm_set_bb_reg(dm, R_0x818, BIT(11), val); + odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0xf); + + if (enable == FUNC_ENABLE) { + switch (path) { + case RF_PATH_A: + odm_set_bb_reg(dm, R_0x1940, BIT(31), val); + break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case RF_PATH_B: + odm_set_bb_reg(dm, R_0x4040, BIT(31), val); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case RF_PATH_C: + odm_set_bb_reg(dm, R_0x5040, BIT(31), val); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case RF_PATH_D: + odm_set_bb_reg(dm, R_0x5140, BIT(31), val); + break; + #endif + default: + break; + } + } else { + odm_set_bb_reg(dm, R_0x1940, BIT(31), val); + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + odm_set_bb_reg(dm, R_0x4040, BIT(31), val); + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + odm_set_bb_reg(dm, R_0x5040, BIT(31), val); + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + odm_set_bb_reg(dm, R_0x5140, BIT(31), val); + #endif + #if RTL8812F_SUPPORT + if (dm->support_ic_type & ODM_RTL8812F) { + odm_set_bb_reg(dm, R_0x818, BIT(3), val); + odm_set_bb_reg(dm, R_0x1d3c, 0x78000000, 0x0); + } + #endif + } +} + +u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info, + enum rf_path ant_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 evm_org, cfo_org, rxsnr_org; + u8 i, return_info = 0, tmp_lsb = 0, tmp_msb = 0, tmp_info = 0; + + /* Update the status for each pkt */ + odm_set_bb_reg(dm, R_0x8c4, 0xfff000, 0x448); + odm_set_bb_reg(dm, R_0x8c0, MASKLWORD, 0x4001); + /* PHY status Page1 */ + odm_set_bb_reg(dm, R_0x8c0, 0x3C00000, 0x1); + /*choose debug port for phystatus */ + odm_set_bb_reg(dm, R_0x1c3c, 0xFFF00, 0x380); + + if (info == PHY_PWDB) { + /* Choose the report of the diff path */ + if (ant_path == RF_PATH_A) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1); + else if (ant_path == RF_PATH_B) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x2); + else if (ant_path == RF_PATH_C) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x3); + else if (ant_path == RF_PATH_D) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x4); + } else if (info == PHY_EVM) { + /* Choose the report of the diff path */ + if (ant_path == RF_PATH_A) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10); + else if (ant_path == RF_PATH_B) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x11); + else if (ant_path == RF_PATH_C) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12); + else if (ant_path == RF_PATH_D) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13); + return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff); + } else if (info == PHY_CFO) { + /* Choose the report of the diff path */ + if (ant_path == RF_PATH_A) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14); + else if (ant_path == RF_PATH_B) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15); + else if (ant_path == RF_PATH_C) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x16); + else if (ant_path == RF_PATH_D) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x17); + return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff); + } else if (info == PHY_RXSNR) { + /* Choose the report of the diff path */ + if (ant_path == RF_PATH_A) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x18); + else if (ant_path == RF_PATH_B) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x19); + else if (ant_path == RF_PATH_C) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1a); + else if (ant_path == RF_PATH_D) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x1b); + return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff); + } else if (info == PHY_LGAIN) { + /* choose page */ + odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2); + /* Choose the report of the diff path */ + if (ant_path == RF_PATH_A) { + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd); + tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f); + return_info = tmp_info; + } else if (ant_path == RF_PATH_B) { + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xd); + tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xc0); + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe); + tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf); + tmp_info |= (tmp_msb << 2) | tmp_lsb; + return_info = tmp_info; + } else if (ant_path == RF_PATH_C) { + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xe); + tmp_lsb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xf0); + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0xf); + tmp_msb = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3); + tmp_info |= (tmp_msb << 4) | tmp_lsb; + return_info = tmp_info; + } else if (ant_path == RF_PATH_D) { + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x10); + tmp_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0x3f); + return_info = tmp_info; + } + } else if (info == PHY_HT_AAGC_GAIN) { + /* choose page */ + odm_set_bb_reg(dm, R_0x8c0, 0x3c00000, 0x2); + /* Choose the report of the diff path */ + if (ant_path == RF_PATH_A) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x12); + else if (ant_path == RF_PATH_B) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x13); + else if (ant_path == RF_PATH_C) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x14); + else if (ant_path == RF_PATH_D) + odm_set_bb_reg(dm, R_0x8c4, 0x3ff, 0x15); + return_info = (u8)odm_get_bb_reg(dm, R_0x2dbc, 0xff); + } + return return_info; +} + +void phydm_ex_hal8814b_wifi_only_hw_config(void *dm_void) +{ + /*BB control*/ + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2);*/ + /*SW control*/ + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77);*/ + /*antenna mux switch */ + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3);*/ + + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0);*/ + + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0);*/ + /*switch to WL side controller and gnt_wl gnt_bt debug signal */ + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e);*/ + /*gnt_wl=1 , gnt_bt=0*/ + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, + * 0x7700); + */ + /*halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, + * 0xc00f0038); + */ +} + +void phydm_user_position_for_sniffer(void *dm_void, u8 user_position) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /* user position valid */ + odm_set_bb_reg(dm, R_0xa68, BIT(17), 1); + /* Select user seat from pmac */ + odm_set_bb_reg(dm, R_0xa68, BIT(16), 1); + /*user seat*/ + odm_set_bb_reg(dm, R_0xa68, (BIT(19) | BIT(18)), user_position); +} + +boolean +phydm_bb_ctrl_txagc_ofst_jgr3(void *dm_void, s8 pw_offset, /*@(unit: dB)*/ + u8 add_half_db /*@(+0.5 dB)*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 pw_idx = pw_offset * 4; /*@ 7Bit, 0.25dB unit*/ + + if (pw_offset < -16 || pw_offset > 15) { + pr_debug("[Warning][%s]Ofst error=%d", __func__, pw_offset); + return false; + } + + if (add_half_db) + pw_idx += 2; + + PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx); + + odm_set_bb_reg(dm, R_0x18a0, 0x3f, pw_idx); + + if (dm->num_rf_path >= 2) + odm_set_bb_reg(dm, R_0x41a0, 0x3f, pw_idx); + + if (dm->num_rf_path >= 3) + odm_set_bb_reg(dm, R_0x52a0, 0x3f, pw_idx); + + if (dm->num_rf_path >= 4) + odm_set_bb_reg(dm, R_0x53a0, 0x3f, pw_idx); + + return true; +} + +#endif +u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 fc = 2412; + u8 direction = FREQ_POSITIVE; + u32 tone_idx = 0; + u8 set_result = PHYDM_SET_SUCCESS; + u8 rpt = 0; + + if (enable == FUNC_DISABLE) { + set_result = PHYDM_SET_SUCCESS; + } else { + PHYDM_DBG(dm, ODM_COMP_API, + "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_intf, + (((sec_ch == PHYDM_DONT_CARE) || (bw == 20) || + (ch > 14)) ? "Don't care" : + (sec_ch == PHYDM_ABOVE) ? "H" : "L")); + + /*@calculate fc*/ + if (phydm_find_fc(dm, ch, bw, sec_ch, &fc) == PHYDM_SET_FAIL) { + set_result = PHYDM_SET_FAIL; + } else { + /*@calculate interference distance*/ + rpt = phydm_find_intf_distance(dm, bw, fc, f_intf, + &tone_idx); + if (rpt == PHYDM_SET_SUCCESS) { + if (f_intf >= fc) + direction = FREQ_POSITIVE; + else + direction = FREQ_NEGATIVE; + + phydm_set_nbi_reg(dm, tone_idx, bw); + + set_result = PHYDM_SET_SUCCESS; + } else { + set_result = PHYDM_SET_NO_NEED; + } + } + } + + if (set_result == PHYDM_SET_SUCCESS) + phydm_nbi_enable(dm, enable); + else + phydm_nbi_enable(dm, FUNC_DISABLE); + + return set_result; +} + +void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0, idx_lmt = 0; + u32 enable = 0; /*@function enable*/ + u32 ch = 0; + u32 bw = 0; + u32 f_int = 0; /*@interference frequency*/ + u32 sec_ch = 0; /*secondary channel*/ + u8 rpt = 0; + u8 path = 0; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + idx_lmt = 6; + else + idx_lmt = 5; + for (i = 0; i < idx_lmt; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + enable = val[0]; + ch = val[1]; + bw = val[2]; + f_int = val[3]; + sec_ch = val[4]; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + path = (u8)val[5]; + #endif + + if ((strcmp(input[1], help) == 0)) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)} {Path:A~D(0~3)}\n"); + else + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(khz)} {Scnd_CH(L=1, H=2)}\n"); + *_used = used; + *_out_len = out_len; + return; + } else if (val[0] == FUNC_ENABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_int, + ((sec_ch == PHYDM_DONT_CARE) || + (bw == 20) || (ch > 14)) ? "Don't care" : + ((sec_ch == PHYDM_ABOVE) ? "H" : "L")); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int, + sec_ch, path); + else + #endif + rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else if (val[0] == FUNC_DISABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Disable NBI]\n"); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_nbi_setting_jgr3(dm, enable, ch, bw, f_int, + sec_ch, path); + else + #endif + rpt = phydm_nbi_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else { + rpt = PHYDM_SET_FAIL; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[NBI set result: %s]\n", + (rpt == PHYDM_SET_SUCCESS) ? "Success" : + ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error")); + + *_used = used; + *_out_len = out_len; +} + +void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0, idx_lmt = 0; + u32 enable = 0; /*@function enable*/ + u32 ch = 0; + u32 bw = 0; + u32 f_int = 0; /*@interference frequency*/ + u32 sec_ch = 0; /*secondary channel*/ + u8 rpt = 0; + u8 wgt = 0; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + idx_lmt = 6; + else + idx_lmt = 5; + + for (i = 0; i < idx_lmt; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + enable = val[0]; + ch = val[1]; + bw = val[2]; + f_int = val[3]; + sec_ch = val[4]; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + wgt = (u8)val[5]; + #endif + + if ((strcmp(input[1], help) == 0)) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(KHz)} {Scnd_CH(L=1, H=2)}\n{wgt:(7:3/4),(6~1: 1/2 ~ 1/64),(0:0)}\n"); + else + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en:1 Dis:2} {ch} {BW:20/40/80} {f_intf(Mhz)} {Scnd_CH(L=1, H=2)}\n"); + + *_used = used; + *_out_len = out_len; + return; + + } else if (val[0] == FUNC_ENABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + ch, bw, f_int, + (ch > 14) ? "Don't care" : + (((sec_ch == PHYDM_DONT_CARE) || + (bw == 20) || (ch > 14)) ? "H" : "L")); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw, + f_int, sec_ch, wgt); + else + #endif + rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else if (val[0] == FUNC_DISABLE) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Disable CSI MASK]\n"); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + rpt = phydm_csi_mask_setting_jgr3(dm, enable, ch, bw, + f_int, sec_ch, wgt); + else + #endif + rpt = phydm_csi_mask_setting(dm, enable, ch, bw, f_int, + sec_ch); + } else { + rpt = PHYDM_SET_FAIL; + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "[CSI MASK set result: %s]\n", + (rpt == PHYDM_SET_SUCCESS) ? "Success" : + ((rpt == PHYDM_SET_NO_NEED) ? "No need" : "Error")); + + *_used = used; + *_out_len = out_len; +} + +void phydm_stop_ck320(void *dm_void, u8 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = enable ? 1 : 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8b4, BIT(6), val); + } else { + if (dm->support_ic_type & ODM_IC_N_2SS) /*N-2SS*/ + odm_set_bb_reg(dm, R_0x87c, BIT(29), val); + else /*N-1SS*/ + odm_set_bb_reg(dm, R_0x87c, BIT(31), val); + } +} + +boolean +phydm_bb_ctrl_txagc_ofst(void *dm_void, s8 pw_offset, /*@(unit: dB)*/ + u8 add_half_db /*@(+0.5 dB)*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 pw_idx; + u8 offset_bit_num = 0; + + if (dm->support_ic_type & N_IC_TX_OFFEST_5_BIT) { + /*@ 5Bit, 0.5dB unit*/ + if (pw_offset < -8 || pw_offset > 7) { + pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset); + return false; + } + offset_bit_num = 5; + } else { + if (pw_offset < -16 || pw_offset > 15) { + pr_debug("[Warning][%s] Ofst=%d", __func__, pw_offset); + return false; + } + if (dm->support_ic_type & N_IC_TX_OFFEST_7_BIT) { + /*@ 7Bit, 0.25dB unit*/ + offset_bit_num = 7; + } else { + /*@ 6Bit, 0.5dB unit*/ + offset_bit_num = 6; + } + } + + pw_idx = (offset_bit_num == 7) ? pw_offset * 4 : pw_offset * 2; + + if (add_half_db) + pw_idx = (offset_bit_num == 7) ? pw_idx + 2 : pw_idx + 1; + + PHYDM_DBG(dm, ODM_COMP_API, "Pw_ofst=0x%x\n", pw_idx); + + switch (dm->ic_ip_series) { + case PHYDM_IC_AC: + odm_set_bb_reg(dm, R_0x8b4, 0x3f, pw_idx); /*6Bit*/ + break; + case PHYDM_IC_N: + if (offset_bit_num == 5) { + odm_set_bb_reg(dm, R_0x80c, 0x1f00, pw_idx); + if (dm->num_rf_path >= 2) + odm_set_bb_reg(dm, R_0x80c, 0x3e000, pw_idx); + } else if (offset_bit_num == 6) { + odm_set_bb_reg(dm, R_0x80c, 0x3f00, pw_idx); + if (dm->num_rf_path >= 2) + odm_set_bb_reg(dm, R_0x80c, 0xfc000, pw_idx); + } else { /*7Bit*/ + odm_set_bb_reg(dm, R_0x80c, 0x7f00, pw_idx); + if (dm->num_rf_path >= 2) + odm_set_bb_reg(dm, R_0x80c, 0x3f8000, pw_idx); + } + break; + } + return true; +} + +boolean +phydm_set_bb_txagc_offset(void *dm_void, s8 pw_offset, /*@(unit: dB)*/ + u8 add_half_db /*@(+0.5 dB)*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean rpt = false; + + PHYDM_DBG(dm, ODM_COMP_API, "power_offset=%d, add_half_db =%d\n", + pw_offset, add_half_db); + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + rpt = phydm_bb_ctrl_txagc_ofst_jgr3(dm, pw_offset, add_half_db); + } else +#endif + { + rpt = phydm_bb_ctrl_txagc_ofst(dm, pw_offset, add_half_db); + } + + PHYDM_DBG(dm, ODM_COMP_API, "TX AGC Offset set_success=%d", rpt); + + return rpt; +} + +#ifdef PHYDM_COMMON_API_SUPPORT +void phydm_reset_txagc(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0}; + u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8}; + u32 r_txagc_diff = R_0x3a00; + u8 i = 0; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) { + PHYDM_DBG(dm, ODM_COMP_API, "Only for JGR3 ICs!\n"); + return; + } + + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + odm_set_bb_reg(dm, r_txagc_cck[i], 0x7f0000, 0x0); + odm_set_bb_reg(dm, r_txagc_ofdm[i], 0x1fc00, 0x0); + } + + for (i = 0; i <= ODM_RATEVHTSS4MCS6; i = i + 4) + odm_set_bb_reg(dm, r_txagc_diff + i, MASKDWORD, 0x0); +} +boolean +phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path, + boolean is_positive) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + u32 txagc_cck = 0; + u32 txagc_ofdm = 0; + u32 r_txagc_ofdm[4] = {R_0x18e8, R_0x41e8, R_0x52e8, R_0x53e8}; + u32 r_txagc_cck[4] = {R_0x18a0, R_0x41a0, R_0x52a0, R_0x53a0}; + u32 r_new_txagc[1] = {R_0x4308}; + + #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) { + if (path > RF_PATH_B) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n", + path); + return false; + } + txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path], + 0x7F0000); + txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path], + 0x1FC00); + if (is_positive) { + if (((txagc_cck + pwr_offset) > 127) || + ((txagc_ofdm + pwr_offset) > 127)) + return false; + + txagc_cck += pwr_offset; + txagc_ofdm += pwr_offset; + } else { + if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm) + return false; + + txagc_cck -= pwr_offset; + txagc_ofdm -= pwr_offset; + } + #if (RTL8822C_SUPPORT) + ret = config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_cck, + path, PDM_CCK); + ret &= config_phydm_write_txagc_ref_8822c(dm, (u8)txagc_ofdm, + path, PDM_OFDM); + #endif + #if (RTL8812F_SUPPORT) + ret = config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_cck, + path, PDM_CCK); + ret &= config_phydm_write_txagc_ref_8812f(dm, (u8)txagc_ofdm, + path, PDM_OFDM); + #endif + #if (RTL8197G_SUPPORT) + ret = config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_cck, + path, PDM_CCK); + ret &= config_phydm_write_txagc_ref_8197g(dm, (u8)txagc_ofdm, + path, PDM_OFDM); + #endif + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n", + __func__, path, txagc_cck, txagc_ofdm); + } + #endif + + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) { + if (path > RF_PATH_D) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n", + path); + return false; + } + txagc_cck = (u8)odm_get_bb_reg(dm, r_txagc_cck[path], + 0x7F0000); + txagc_ofdm = (u8)odm_get_bb_reg(dm, r_txagc_ofdm[path], + 0x1FC00); + if (is_positive) { + if (((txagc_cck + pwr_offset) > 127) || + ((txagc_ofdm + pwr_offset) > 127)) + return false; + + txagc_cck += pwr_offset; + txagc_ofdm += pwr_offset; + } else { + if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm) + return false; + + txagc_cck -= pwr_offset; + txagc_ofdm -= pwr_offset; + } + #if (RTL8198F_SUPPORT) + ret = config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_cck, + path, PDM_CCK); + ret &= config_phydm_write_txagc_ref_8198f(dm, (u8)txagc_ofdm, + path, PDM_OFDM); + #endif + #if (RTL8814B_SUPPORT) + ret = config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_cck, + path, PDM_CCK); + ret &= config_phydm_write_txagc_ref_8814b(dm, (u8)txagc_ofdm, + path, PDM_OFDM); + #endif + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n", + __func__, path, txagc_cck, txagc_ofdm); + } + #endif + + #if (RTL8723F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8723F)) { + if (path > RF_PATH_A) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Unsupported path (%d)\n", + path); + return false; + } + txagc_cck = (u8)odm_get_bb_reg(dm, r_new_txagc[path], + 0x0000007f); + txagc_ofdm = (u8)odm_get_bb_reg(dm, r_new_txagc[path], + 0x00007f00); + if (is_positive) { + if (((txagc_cck + pwr_offset) > 127) || + ((txagc_ofdm + pwr_offset) > 127)) + return false; + + txagc_cck += pwr_offset; + txagc_ofdm += pwr_offset; + } else { + if (pwr_offset > txagc_cck || pwr_offset > txagc_ofdm) + return false; + + txagc_cck -= pwr_offset; + txagc_ofdm -= pwr_offset; + } + #if (RTL8723F_SUPPORT) + ret = config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_cck, + path, PDM_CCK); + ret &= config_phydm_write_txagc_ref_8723f(dm, (u8)txagc_ofdm, + path, PDM_OFDM); + #endif + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d txagc_cck_ref=%x txagc_ofdm_ref=0x%x\n", + __func__, path, txagc_cck, txagc_ofdm); + } + #endif + + return ret; +} + +boolean +phydm_api_set_txagc(void *dm_void, u32 pwr_idx, enum rf_path path, + u8 rate, boolean is_single_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT ||\ + RTL8814B_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) + u8 base = 0; + u8 txagc_tmp = 0; + s8 pw_by_rate_tmp = 0; + s8 pw_by_rate_new = 0; + #endif + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + u8 i = 0; + #endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) { + if (is_single_rate) { + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) + ret = phydm_write_txagc_1byte_8822b(dm, pwr_idx, + path, rate); + #endif + + #if (RTL8821C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8821C) + ret = phydm_write_txagc_1byte_8821c(dm, pwr_idx, + path, rate); + #endif + + #if (RTL8195B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8195B) + ret = phydm_write_txagc_1byte_8195b(dm, pwr_idx, + path, rate); + #endif + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + set_current_tx_agc(dm->priv, path, rate, (u8)pwr_idx); + #endif + + } else { + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) + ret = config_phydm_write_txagc_8822b(dm, + pwr_idx, + path, + rate); + #endif + + #if (RTL8821C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8821C) + ret = config_phydm_write_txagc_8821c(dm, + pwr_idx, + path, + rate); + #endif + + #if (RTL8195B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8195B) + ret = config_phydm_write_txagc_8195b(dm, + pwr_idx, + path, + rate); + #endif + + #if (DM_ODM_SUPPORT_TYPE & ODM_AP) + for (i = 0; i < 4; i++) + set_current_tx_agc(dm->priv, path, (rate + i), + (u8)pwr_idx); + #endif + } + } +#endif + +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8198f(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8198f(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8198f(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + base = base & 0x7f; + if (DIFF_2((pwr_idx & 0x7f), base) > 64 || pwr_idx > 127) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8198f(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8822c(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8822c(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8822c(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + base = base & 0x7f; + if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8822c(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8814b(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8814b(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8814b(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + base = base & 0x7f; + if (DIFF_2((pwr_idx & 0x7f), base) > 64) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8814b(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif + +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8812F) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8812f(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8812f(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8812f(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + base = base & 0x7f; + if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8812f(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif + +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8197g(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8197g(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8197g(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + base = base & 0x7f; + if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8197g(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif +#if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) { + if (rate < 0x4) + txagc_tmp = config_phydm_read_txagc_8723f(dm, path, + rate, + PDM_CCK); + else + txagc_tmp = config_phydm_read_txagc_8723f(dm, path, + rate, + PDM_OFDM); + + pw_by_rate_tmp = config_phydm_read_txagc_diff_8723f(dm, rate); + base = txagc_tmp - pw_by_rate_tmp; + base = base & 0x7f; + if (DIFF_2((pwr_idx & 0x7f), base) > 63 || pwr_idx > 127) + return false; + + pw_by_rate_new = (s8)(pwr_idx - base); + ret = phydm_write_txagc_1byte_8723f(dm, pw_by_rate_new, rate); + PHYDM_DBG(dm, ODM_PHY_CONFIG, + "%s: path-%d rate_idx=%x base=0x%x new_diff=0x%x\n", + __func__, path, rate, base, pw_by_rate_new); + } +#endif + +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_write_txagc_8197f(dm, pwr_idx, path, rate); +#endif + +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + ret = config_phydm_write_txagc_8192f(dm, pwr_idx, path, rate); +#endif + +#if (RTL8721D_SUPPORT) + if (dm->support_ic_type & ODM_RTL8721D) + ret = config_phydm_write_txagc_8721d(dm, pwr_idx, path, rate); +#endif +#if (RTL8710C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8710C) + ret = config_phydm_write_txagc_8710c(dm, pwr_idx, path, rate); +#endif + return ret; +} + +u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ret = 0; + +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + ret = config_phydm_read_txagc_8822b(dm, path, hw_rate); +#endif + +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + ret = config_phydm_read_txagc_8197f(dm, path, hw_rate); +#endif + +#if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) + ret = config_phydm_read_txagc_8821c(dm, path, hw_rate); +#endif + +#if (RTL8195B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8195B) + ret = config_phydm_read_txagc_8195b(dm, path, hw_rate); +#endif + +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + ret = config_phydm_read_txagc_8192f(dm, path, hw_rate); +#endif + +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8198f(dm, path, hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8198f(dm, path, hw_rate, + PDM_OFDM); + } + } +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8822c(dm, path, hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8822c(dm, path, hw_rate, + PDM_OFDM); + } + } +#endif + +#if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8723f(dm, path, hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8723f(dm, path, hw_rate, + PDM_OFDM); + } + } +#endif + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8814b(dm, path, hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8814b(dm, path, hw_rate, + PDM_OFDM); + } + } +#endif + +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8812F) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8812f(dm, path, hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8812f(dm, path, hw_rate, + PDM_OFDM); + } + } +#endif + +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) { + if (hw_rate < 0x4) { + ret = config_phydm_read_txagc_8197g(dm, path, + hw_rate, + PDM_CCK); + } else { + ret = config_phydm_read_txagc_8197g(dm, path, + hw_rate, + PDM_OFDM); + } + } +#endif + +#if (RTL8721D_SUPPORT) + if (dm->support_ic_type & ODM_RTL8721D) + ret = config_phydm_read_txagc_8721d(dm, path, hw_rate); +#endif +#if (RTL8710C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8710C) + ret = config_phydm_read_txagc_8710c(dm, path, hw_rate); +#endif + return ret; +} + +#if (RTL8822C_SUPPORT) +void phydm_shift_rxagc_table(void *dm_void, boolean is_pos_shift, u8 sft) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u8 j = 0; + u32 reg = 0; + u16 max_rf_gain = 0; + u16 min_rf_gain = 0; + + dm->is_agc_tab_pos_shift = is_pos_shift; + dm->agc_table_shift = sft; + + for (i = 0; i <= dm->agc_table_cnt; i++) { + max_rf_gain = dm->agc_rf_gain_ori[i][0]; + min_rf_gain = dm->agc_rf_gain_ori[i][63]; + + if (dm->support_ic_type & ODM_RTL8822C) + dm->l_bnd_detect[i] = false; + + for (j = 0; j < 64; j++) { + if (is_pos_shift) { + if (j < sft) + reg = (max_rf_gain & 0x3ff); + else + reg = (dm->agc_rf_gain_ori[i][j - sft] & + 0x3ff); + } else { + if (j > 63 - sft) + reg = (min_rf_gain & 0x3ff); + + else + reg = (dm->agc_rf_gain_ori[i][j + sft] & + 0x3ff); + } + dm->agc_rf_gain[i][j] = (u16)(reg & 0x3ff); + + reg |= (j & 0x3f) << 16;/*mp_gain_idx*/ + reg |= (i & 0xf) << 22;/*table*/ + reg |= BIT(29) | BIT(28);/*write en*/ + odm_set_bb_reg(dm, R_0x1d90, MASKDWORD, reg); + } + } + + if (dm->support_ic_type & ODM_RTL8822C) + odm_set_bb_reg(dm, R_0x828, 0xf8, L_BND_DEFAULT_8822C); +} +#endif + +boolean +phydm_api_switch_bw_channel(void *dm_void, u8 ch, u8 pri_ch, + enum channel_width bw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + + switch (dm->support_ic_type) { +#if (RTL8822B_SUPPORT) + case ODM_RTL8822B: + ret = config_phydm_switch_channel_bw_8822b(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8197F_SUPPORT) + case ODM_RTL8197F: + ret = config_phydm_switch_channel_bw_8197f(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8821C_SUPPORT) + case ODM_RTL8821C: + ret = config_phydm_switch_channel_bw_8821c(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8195B_SUPPORT) + case ODM_RTL8195B: + ret = config_phydm_switch_channel_bw_8195b(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8192F_SUPPORT) + case ODM_RTL8192F: + ret = config_phydm_switch_channel_bw_8192f(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8198F_SUPPORT) + case ODM_RTL8198F: + ret = config_phydm_switch_channel_bw_8198f(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8822C_SUPPORT) + case ODM_RTL8822C: + ret = config_phydm_switch_channel_bw_8822c(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8723F_SUPPORT) + case ODM_RTL8723F: + ret = config_phydm_switch_channel_bw_8723f(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8814B_SUPPORT) + case ODM_RTL8814B: + ret = config_phydm_switch_channel_bw_8814b(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8812F_SUPPORT) + case ODM_RTL8812F: + ret = config_phydm_switch_channel_bw_8812f(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8197G_SUPPORT) + case ODM_RTL8197G: + ret = config_phydm_switch_channel_bw_8197g(dm, ch, pri_ch, bw); + break; +#endif + +#if (RTL8721D_SUPPORT) + case ODM_RTL8721D: + ret = config_phydm_switch_channel_bw_8721d(dm, ch, pri_ch, bw); + break; +#endif +#if (RTL8710C_SUPPORT) + case ODM_RTL8710C: + ret = config_phydm_switch_channel_bw_8710c(dm, ch, pri_ch, bw); + break; +#endif + + default: + break; + } + return ret; +} + +boolean +phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path, + enum bb_path tx_path_ctrl) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; + boolean is_2tx = false; + + if (tx_path_ctrl == BB_PATH_AB) + is_2tx = true; + + switch (dm->support_ic_type) { + #if (RTL8822B_SUPPORT) + case ODM_RTL8822B: + ret = config_phydm_trx_mode_8822b(dm, tx_path, rx_path, + tx_path_ctrl); + break; + #endif + + #if (RTL8197F_SUPPORT) + case ODM_RTL8197F: + ret = config_phydm_trx_mode_8197f(dm, tx_path, rx_path, is_2tx); + break; + #endif + + #if (RTL8192F_SUPPORT) + case ODM_RTL8192F: + ret = config_phydm_trx_mode_8192f(dm, tx_path, rx_path, + tx_path_ctrl); + break; + #endif + + #if (RTL8198F_SUPPORT) + case ODM_RTL8198F: + ret = config_phydm_trx_mode_8198f(dm, tx_path, rx_path, is_2tx); + break; + #endif + + #if (RTL8814B_SUPPORT) + case ODM_RTL8814B: + ret = config_phydm_trx_mode_8814b(dm, tx_path, rx_path); + break; + #endif + + #if (RTL8822C_SUPPORT) + case ODM_RTL8822C: + ret = config_phydm_trx_mode_8822c(dm, tx_path, rx_path, + tx_path_ctrl); + break; + #endif + + #if (RTL8812F_SUPPORT) + case ODM_RTL8812F: + ret = config_phydm_trx_mode_8812f(dm, tx_path, rx_path, is_2tx); + break; + #endif + + #if (RTL8197G_SUPPORT) + case ODM_RTL8197G: + ret = config_phydm_trx_mode_8197g(dm, tx_path, rx_path, is_2tx); + break; + #endif + + #if (RTL8721D_SUPPORT) + case ODM_RTL8721D: + ret = config_phydm_trx_mode_8721d(dm, tx_path, rx_path, is_2tx); + break; + #endif + + #if (RTL8710C_SUPPORT) + case ODM_RTL8710C: + ret = config_phydm_trx_mode_8710c(dm, tx_path, rx_path, is_2tx); + break; + #endif + } + return ret; +} +#endif + +#ifdef PHYDM_COMMON_API_NOT_SUPPORT +u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 read_back_data = INVALID_TXAGC_DATA; + u32 reg_txagc; + u32 reg_mask; + /* This function is for 92E/88E etc... */ + /* @Input need to be HW rate index, not driver rate index!!!! */ + + /* @Error handling */ + if (path > RF_PATH_B || hw_rate > ODM_RATEMCS15) { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: unsupported path (%d)\n", + __func__, path); + return INVALID_TXAGC_DATA; + } + + if (path == RF_PATH_A) { + switch (hw_rate) { + case ODM_RATE1M: + reg_txagc = R_0xe08; + reg_mask = 0x00007f00; + break; + case ODM_RATE2M: + reg_txagc = R_0x86c; + reg_mask = 0x00007f00; + break; + case ODM_RATE5_5M: + reg_txagc = R_0x86c; + reg_mask = 0x007f0000; + break; + case ODM_RATE11M: + reg_txagc = R_0x86c; + reg_mask = 0x7f000000; + break; + + case ODM_RATE6M: + reg_txagc = R_0xe00; + reg_mask = 0x0000007f; + break; + case ODM_RATE9M: + reg_txagc = R_0xe00; + reg_mask = 0x00007f00; + break; + case ODM_RATE12M: + reg_txagc = R_0xe00; + reg_mask = 0x007f0000; + break; + case ODM_RATE18M: + reg_txagc = R_0xe00; + reg_mask = 0x7f000000; + break; + case ODM_RATE24M: + reg_txagc = R_0xe04; + reg_mask = 0x0000007f; + break; + case ODM_RATE36M: + reg_txagc = R_0xe04; + reg_mask = 0x00007f00; + break; + case ODM_RATE48M: + reg_txagc = R_0xe04; + reg_mask = 0x007f0000; + break; + case ODM_RATE54M: + reg_txagc = R_0xe04; + reg_mask = 0x7f000000; + break; + + case ODM_RATEMCS0: + reg_txagc = R_0xe10; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS1: + reg_txagc = R_0xe10; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS2: + reg_txagc = R_0xe10; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS3: + reg_txagc = R_0xe10; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS4: + reg_txagc = R_0xe14; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS5: + reg_txagc = R_0xe14; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS6: + reg_txagc = R_0xe14; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS7: + reg_txagc = R_0xe14; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS8: + reg_txagc = R_0xe18; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS9: + reg_txagc = R_0xe18; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS10: + reg_txagc = R_0xe18; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS11: + reg_txagc = R_0xe18; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS12: + reg_txagc = R_0xe1c; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS13: + reg_txagc = R_0xe1c; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS14: + reg_txagc = R_0xe1c; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS15: + reg_txagc = R_0xe1c; + reg_mask = 0x7f000000; + break; + + default: + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n"); + break; + } + } else if (path == RF_PATH_B) { + switch (hw_rate) { + case ODM_RATE1M: + reg_txagc = R_0x838; + reg_mask = 0x00007f00; + break; + case ODM_RATE2M: + reg_txagc = R_0x838; + reg_mask = 0x007f0000; + break; + case ODM_RATE5_5M: + reg_txagc = R_0x838; + reg_mask = 0x7f000000; + break; + case ODM_RATE11M: + reg_txagc = R_0x86c; + reg_mask = 0x0000007f; + break; + + case ODM_RATE6M: + reg_txagc = R_0x830; + reg_mask = 0x0000007f; + break; + case ODM_RATE9M: + reg_txagc = R_0x830; + reg_mask = 0x00007f00; + break; + case ODM_RATE12M: + reg_txagc = R_0x830; + reg_mask = 0x007f0000; + break; + case ODM_RATE18M: + reg_txagc = R_0x830; + reg_mask = 0x7f000000; + break; + case ODM_RATE24M: + reg_txagc = R_0x834; + reg_mask = 0x0000007f; + break; + case ODM_RATE36M: + reg_txagc = R_0x834; + reg_mask = 0x00007f00; + break; + case ODM_RATE48M: + reg_txagc = R_0x834; + reg_mask = 0x007f0000; + break; + case ODM_RATE54M: + reg_txagc = R_0x834; + reg_mask = 0x7f000000; + break; + + case ODM_RATEMCS0: + reg_txagc = R_0x83c; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS1: + reg_txagc = R_0x83c; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS2: + reg_txagc = R_0x83c; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS3: + reg_txagc = R_0x83c; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS4: + reg_txagc = R_0x848; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS5: + reg_txagc = R_0x848; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS6: + reg_txagc = R_0x848; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS7: + reg_txagc = R_0x848; + reg_mask = 0x7f000000; + break; + + case ODM_RATEMCS8: + reg_txagc = R_0x84c; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS9: + reg_txagc = R_0x84c; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS10: + reg_txagc = R_0x84c; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS11: + reg_txagc = R_0x84c; + reg_mask = 0x7f000000; + break; + case ODM_RATEMCS12: + reg_txagc = R_0x868; + reg_mask = 0x0000007f; + break; + case ODM_RATEMCS13: + reg_txagc = R_0x868; + reg_mask = 0x00007f00; + break; + case ODM_RATEMCS14: + reg_txagc = R_0x868; + reg_mask = 0x007f0000; + break; + case ODM_RATEMCS15: + reg_txagc = R_0x868; + reg_mask = 0x7f000000; + break; + + default: + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid HWrate!\n"); + break; + } + } else { + PHYDM_DBG(dm, ODM_PHY_CONFIG, "Invalid RF path!!\n"); + } + read_back_data = (u8)odm_get_bb_reg(dm, reg_txagc, reg_mask); + PHYDM_DBG(dm, ODM_PHY_CONFIG, "%s: path-%d rate index 0x%x = 0x%x\n", + __func__, path, hw_rate, read_back_data); + return read_back_data; +} +#endif + +#ifdef CONFIG_MCC_DM +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void phydm_set_weighting_cmn(struct dm_struct *dm) +{ + PHYDM_DBG(dm, DBG_COMP_MCC, "%s\n", __func__); + odm_set_bb_reg(dm, 0xc04, (BIT(18) | BIT(21)), 0x0); + odm_set_bb_reg(dm, 0xe04, (BIT(18) | BIT(21)), 0x0); +} + +void phydm_set_weighting_mcc(u8 b_equal_weighting, void *dm_void, u8 port) +{ + /*u8 reg_8;*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + u8 val_0x98e, val_0x98f, val_0x81b; + u32 temp_reg; + + PHYDM_DBG(dm, DBG_COMP_MCC, "ant_weighting_mcc, port = %d\n", port); + if (b_equal_weighting) { + temp_reg = odm_get_bb_reg(dm, 0x98c, 0x00ff0000); + val_0x98e = (u8)(temp_reg >> 16) & 0xc0; + temp_reg = odm_get_bb_reg(dm, 0x98c, 0xff000000); + val_0x98f = (u8)(temp_reg >> 24) & 0x7f; + temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000); + val_0x81b = (u8)(temp_reg >> 24) & 0xfd; + PHYDM_DBG(dm, DBG_COMP_MCC, "Equal weighting ,rssi_min = %d\n", + dm->rssi_min); + /*equal weighting*/ + } else { + val_0x98e = 0x44; + val_0x98f = 0x43; + temp_reg = odm_get_bb_reg(dm, 0x818, 0xff000000); + val_0x81b = (u8)(temp_reg >> 24) | BIT(2); + PHYDM_DBG(dm, DBG_COMP_MCC, "AGC weighting ,rssi_min = %d\n", + dm->rssi_min); + /*fix sec_min_wgt = 1/2*/ + } + mcc_dm->mcc_reg_id[2] = 0x2; + mcc_dm->mcc_dm_reg[2] = 0x98e; + mcc_dm->mcc_dm_val[2][port] = val_0x98e; + + mcc_dm->mcc_reg_id[3] = 0x3; + mcc_dm->mcc_dm_reg[3] = 0x98f; + mcc_dm->mcc_dm_val[3][port] = val_0x98f; + + mcc_dm->mcc_reg_id[4] = 0x4; + mcc_dm->mcc_dm_reg[4] = 0x81b; + mcc_dm->mcc_dm_val[4][port] = val_0x81b; +} + +void phydm_dyn_ant_dec_mcc(u8 port, u8 rssi_in, void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rssi_l2h = 43, rssi_h2l = 37; + + if (rssi_in == 0xff) + phydm_set_weighting_mcc(FALSE, dm, port); + else if (rssi_in >= rssi_l2h) + phydm_set_weighting_mcc(TRUE, dm, port); + else if (rssi_in <= rssi_h2l) + phydm_set_weighting_mcc(FALSE, dm, port); +} + +void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + u8 i; + + phydm_set_weighting_cmn(dm); + for (i = 0; i <= 1; i++) + phydm_dyn_ant_dec_mcc(i, mcc_dm->mcc_rssi[i], dm); +} +#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/ + +void phydm_mcc_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + u8 i; + + /*PHYDM_DBG(dm, DBG_COMP_MCC, ("MCC init\n"));*/ + PHYDM_DBG(dm, DBG_COMP_MCC, "MCC init\n"); + for (i = 0; i < MCC_DM_REG_NUM; i++) { + mcc_dm->mcc_reg_id[i] = 0xff; + mcc_dm->mcc_dm_reg[i] = 0; + mcc_dm->mcc_dm_val[i][0] = 0; + mcc_dm->mcc_dm_val[i][1] = 0; + } + for (i = 0; i < NUM_STA; i++) { + mcc_dm->sta_macid[0][i] = 0xff; + mcc_dm->sta_macid[1][i] = 0xff; + } + /* Function init */ + dm->is_stop_dym_ant_weighting = 0; +} + +u8 phydm_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + struct cmn_sta_info *p_entry = NULL; + u8 shift = 0; + u8 i = 0; + u8 j = 0; + u8 rssi_min[2] = {0xff, 0xff}; + u8 sta_num = 8; + u8 mcc_macid = 0; + + for (i = 0; i <= 1; i++) { + for (j = 0; j < sta_num; j++) { + if (mcc_dm->sta_macid[i][j] != 0xff) { + mcc_macid = mcc_dm->sta_macid[i][j]; + p_entry = dm->phydm_sta_info[mcc_macid]; + if (!p_entry) { + PHYDM_DBG(dm, DBG_COMP_MCC, + "PEntry NULL(mac=%d)\n", + mcc_dm->sta_macid[i][j]); + return _FAIL; + } + PHYDM_DBG(dm, DBG_COMP_MCC, + "undec_smoothed_pwdb=%d\n", + p_entry->rssi_stat.rssi); + if (p_entry->rssi_stat.rssi < rssi_min[i]) + rssi_min[i] = p_entry->rssi_stat.rssi; + } + } + } + mcc_dm->mcc_rssi[0] = (u8)rssi_min[0]; + mcc_dm->mcc_rssi[1] = (u8)rssi_min[1]; + return _SUCCESS; +} + +void phydm_mcc_h2ccmd_rst(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + u8 i; + u8 regid; + u8 h2c_mcc[H2C_MAX_LENGTH]; + + /* RST MCC */ + for (i = 0; i < H2C_MAX_LENGTH; i++) + h2c_mcc[i] = 0xff; + h2c_mcc[0] = 0x00; + odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc); + PHYDM_DBG(dm, DBG_COMP_MCC, "MCC H2C RST\n"); +} + +void phydm_mcc_h2ccmd(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + u8 i; + u8 regid; + u8 h2c_mcc[H2C_MAX_LENGTH]; + + if (mcc_dm->mcc_rf_ch[0] == 0xff && mcc_dm->mcc_rf_ch[1] == 0xff) { + PHYDM_DBG(dm, DBG_COMP_MCC, "MCC channel Error\n"); + return; + } + /* Set Channel number */ + for (i = 0; i < H2C_MAX_LENGTH; i++) + h2c_mcc[i] = 0xff; + h2c_mcc[0] = 0xe0; + h2c_mcc[1] = (u8)(mcc_dm->mcc_rf_ch[0]); + h2c_mcc[2] = (u8)(mcc_dm->mcc_rf_ch[0] >> 8); + h2c_mcc[3] = (u8)(mcc_dm->mcc_rf_ch[1]); + h2c_mcc[4] = (u8)(mcc_dm->mcc_rf_ch[1] >> 8); + h2c_mcc[5] = 0xff; + h2c_mcc[6] = 0xff; + odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, h2c_mcc); + PHYDM_DBG(dm, DBG_COMP_MCC, + "MCC H2C SetCH: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], h2c_mcc[3], + h2c_mcc[4], h2c_mcc[5], h2c_mcc[6]); + + /* Set Reg and value*/ + for (i = 0; i < H2C_MAX_LENGTH; i++) + h2c_mcc[i] = 0xff; + + for (i = 0; i < MCC_DM_REG_NUM; i++) { + regid = mcc_dm->mcc_reg_id[i]; + if (regid != 0xff) { + h2c_mcc[0] = 0xa0 | (regid & 0x1f); + h2c_mcc[1] = (u8)(mcc_dm->mcc_dm_reg[i]); + h2c_mcc[2] = (u8)(mcc_dm->mcc_dm_reg[i] >> 8); + h2c_mcc[3] = mcc_dm->mcc_dm_val[i][0]; + h2c_mcc[4] = mcc_dm->mcc_dm_val[i][1]; + h2c_mcc[5] = 0xff; + h2c_mcc[6] = 0xff; + odm_fill_h2c_cmd(dm, PHYDM_H2C_MCC, H2C_MAX_LENGTH, + h2c_mcc); + PHYDM_DBG(dm, DBG_COMP_MCC, + "MCC H2C: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + h2c_mcc[0], h2c_mcc[1], h2c_mcc[2], + h2c_mcc[3], h2c_mcc[4], + h2c_mcc[5], h2c_mcc[6]); + } + } +} + +void phydm_mcc_ctrl(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + PHYDM_DBG(dm, DBG_COMP_MCC, "MCC status: %x\n", mcc_dm->mcc_status); + /*MCC stage no change*/ + if (mcc_dm->mcc_status == mcc_dm->mcc_pre_status) + return; + /*Not in MCC stage*/ + if (mcc_dm->mcc_status == 0) { + /* Enable normal Ant-weighting */ + dm->is_stop_dym_ant_weighting = 0; + /* Enable normal DIG */ + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, 0x20); + } else { + /* Disable normal Ant-weighting */ + dm->is_stop_dym_ant_weighting = 1; + /* Enable normal DIG */ + odm_pause_dig(dm, PHYDM_PAUSE_NO_SET, PHYDM_PAUSE_LEVEL_1, + 0x20); + } + if (mcc_dm->mcc_status == 0 && mcc_dm->mcc_pre_status != 0) + phydm_mcc_init(dm); + mcc_dm->mcc_pre_status = mcc_dm->mcc_status; + } + +void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add, + u8 val0, u8 val1) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + + mcc_dm->mcc_reg_id[regid] = regid; + mcc_dm->mcc_dm_reg[regid] = reg_add; + mcc_dm->mcc_dm_val[regid][0] = val0; + mcc_dm->mcc_dm_val[regid][1] = val1; +} + +void phydm_mcc_switch(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + s8 ret; + + phydm_mcc_ctrl(dm); + if (mcc_dm->mcc_status == 0) {/*Not in MCC stage*/ + phydm_mcc_h2ccmd_rst(dm); + return; + } + PHYDM_DBG(dm, DBG_COMP_MCC, "MCC switch\n"); + ret = phydm_check(dm); + if (ret == _FAIL) { + PHYDM_DBG(dm, DBG_COMP_MCC, "MCC check fail\n"); + return; + } + /* Set IGI*/ + phydm_mcc_igi_cal(dm); + + /* Set Antenna Gain*/ +#if (RTL8822B_SUPPORT == 1) + phydm_dynamic_ant_weighting_mcc_8822b(dm); +#endif + /* Set H2C Cmd*/ + phydm_mcc_h2ccmd(dm); +} +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_normal_driver_rx_sniffer( + struct dm_struct *dm, + u8 *desc, + PRT_RFD_STATUS rt_rfd_status, + u8 *drv_info, + u8 phy_status) +{ +#if (defined(CONFIG_PHYDM_RX_SNIFFER_PARSING)) + u32 *msg; + u16 seq_num; + + if (rt_rfd_status->packet_report_type != NORMAL_RX) + return; + + if (!dm->is_linked) { + if (rt_rfd_status->is_hw_error) + return; + } + + if (phy_status == true) { + if (dm->rx_pkt_type == type_block_ack || + dm->rx_pkt_type == type_rts || dm->rx_pkt_type == type_cts) + seq_num = 0; + else + seq_num = rt_rfd_status->seq_num; + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, + "%04d , %01s, rate=0x%02x, L=%04d , %s , %s", + seq_num, + /*rt_rfd_status->mac_id,*/ + (rt_rfd_status->is_crc ? "C" : + rt_rfd_status->is_ampdu ? "A" : "_"), + rt_rfd_status->data_rate, + rt_rfd_status->length, + ((rt_rfd_status->band_width == 0) ? "20M" : + ((rt_rfd_status->band_width == 1) ? "40M" : "80M")), + (rt_rfd_status->is_ldpc ? "LDP" : "BCC")); + + if (dm->rx_pkt_type == type_asoc_req) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_REQ"); + else if (dm->rx_pkt_type == type_asoc_rsp) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "AS_RSP"); + else if (dm->rx_pkt_type == type_probe_req) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_REQ"); + else if (dm->rx_pkt_type == type_probe_rsp) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "PR_RSP"); + else if (dm->rx_pkt_type == type_deauth) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "DEAUTH"); + else if (dm->rx_pkt_type == type_beacon) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BEACON"); + else if (dm->rx_pkt_type == type_block_ack_req) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "BA_REQ"); + else if (dm->rx_pkt_type == type_rts) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__RTS_"); + else if (dm->rx_pkt_type == type_cts) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__CTS_"); + else if (dm->rx_pkt_type == type_ack) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__ACK_"); + else if (dm->rx_pkt_type == type_block_ack) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "__BA__"); + else if (dm->rx_pkt_type == type_data) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "_DATA_"); + else if (dm->rx_pkt_type == type_data_ack) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "Data_Ack"); + else if (dm->rx_pkt_type == type_qos_data) + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [%s]", "QoS_Data"); + else + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [0x%x]", + dm->rx_pkt_type); + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, " , [RSSI=%d,%d,%d,%d ]", + dm->rssi_a, + dm->rssi_b, + dm->rssi_c, + dm->rssi_d); + + msg = (u32 *)drv_info; + + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, + " , P-STS[28:0]=%08x-%08x-%08x-%08x-%08x-%08x-%08x\n", + msg[6], msg[5], msg[4], msg[3], + msg[2], msg[1], msg[1]); + } else { + PHYDM_DBG_F(dm, ODM_COMP_SNIFFER, + "%04d , %01s, rate=0x%02x, L=%04d , %s , %s\n", + rt_rfd_status->seq_num, + /*rt_rfd_status->mac_id,*/ + (rt_rfd_status->is_crc ? "C" : + (rt_rfd_status->is_ampdu) ? "A" : "_"), + rt_rfd_status->data_rate, + rt_rfd_status->length, + ((rt_rfd_status->band_width == 0) ? "20M" : + ((rt_rfd_status->band_width == 1) ? "40M" : "80M")), + (rt_rfd_status->is_ldpc ? "LDP" : "BCC")); + } + +#endif +} + +#endif diff --git a/hal/phydm/phydm_api.h b/hal/phydm/phydm_api.h new file mode 100644 index 0000000..a27b725 --- /dev/null +++ b/hal/phydm/phydm_api.h @@ -0,0 +1,228 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_API_H__ +#define __PHYDM_API_H__ + +/* 2019.10.22 Add get/shift rxagc API for 8822C*/ +#define PHYDM_API_VERSION "2.3" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +#define N_IC_TX_OFFEST_5_BIT (ODM_RTL8188E | ODM_RTL8192E) + +#define N_IC_TX_OFFEST_6_BIT (ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B |\ + ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8195A |\ + ODM_RTL8188F) + +#define N_IC_TX_OFFEST_7_BIT (ODM_RTL8721D | ODM_RTL8710C) + +#define CN_CNT_MAX 10 /*@max condition number threshold*/ + +#define FUNC_ENABLE 1 +#define FUNC_DISABLE 2 + +/*@NBI API------------------------------------*/ +#define NBI_128TONE 27 /*register table size*/ +#define NBI_256TONE 59 /*register table size*/ + +#define NUM_START_CH_80M 7 +#define NUM_START_CH_40M 14 + +#define CH_OFFSET_40M 2 +#define CH_OFFSET_80M 6 + +#define FFT_128_TYPE 1 +#define FFT_256_TYPE 2 + +#define FREQ_POSITIVE 1 +#define FREQ_NEGATIVE 2 +/*@------------------------------------------------*/ + +enum phystat_rpt { + PHY_PWDB = 0, + PHY_EVM = 1, + PHY_CFO = 2, + PHY_RXSNR = 3, + PHY_LGAIN = 4, + PHY_HT_AAGC_GAIN = 5, +}; + +#ifndef PHYDM_COMMON_API_SUPPORT +#define INVALID_RF_DATA 0xffffffff +#define INVALID_TXAGC_DATA 0xff +#endif + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +struct phydm_api_stuc { + u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/ + u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/ + u8 tx_queue_bitmap; /*REG0x520[23:16]*/ + u8 ccktx_path; + u8 pri_ch_idx; +}; + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc); + +void phydm_reset_bb_hw_cnt(void *dm_void); + +void phydm_dynamic_ant_weighting(void *dm_void); + +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif + +void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path); + +void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path); + +void phydm_config_cck_rx_path(void *dm_void, enum bb_path path); + +void phydm_config_cck_rx_antenna_init(void *dm_void); + +void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path); + +void phydm_config_cck_tx_path(void *dm_void, enum bb_path path); + +void phydm_tx_2path(void *dm_void); + +void phydm_stop_3_wire(void *dm_void, u8 set_type); + +u8 phydm_stop_ic_trx(void *dm_void, u8 set_type); + +void phydm_dis_cck_trx(void *dm_void, u8 set_type); + +void phydm_bw_fixed_enable(void *dm_void, u8 enable); + +void phydm_bw_fixed_setting(void *dm_void); + +void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch); + +void phydm_nbi_enable(void *dm_void, u32 enable); + +u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch); + +u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch); + +void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_stop_ck320(void *dm_void, u8 enable); + +boolean +phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db); + +boolean phydm_spur_case_mapping(void *dm_void); + +enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch); +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx); + +u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, + u32 f_intf, u32 sec_ch, u8 wgt); + +void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 wgt); + +u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf, + u32 sec_ch, u8 path); + +void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction, + u8 path); + +void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path); + +u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info, + enum rf_path ant_path); +void phydm_user_position_for_sniffer(void *dm_void, u8 user_position); + +#endif + +#ifdef PHYDM_COMMON_API_SUPPORT +void phydm_reset_txagc(void *dm_void); + +boolean +phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path, + boolean is_positive); +boolean +phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path, + u8 hw_rate, boolean is_single_rate); + +u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate); + +#if (RTL8822C_SUPPORT) +void phydm_shift_rxagc_table(void *dm_void, boolean shift_up, u8 shift); +#endif + +boolean +phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx, + enum channel_width bandwidth); + +boolean +phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path, + enum bb_path tx_path_ctrl); + +#endif + +#ifdef PHYDM_COMMON_API_NOT_SUPPORT +u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate); +#endif + +#ifdef CONFIG_MCC_DM +#ifdef DYN_ANT_WEIGHTING_SUPPORT +void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void); +#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/ +void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add, + u8 val0, u8 val1); +u8 phydm_check(void *dm_void); +void phydm_mcc_init(void *dm_void); +void phydm_mcc_switch(void *dm_void); +#endif /*#ifdef CONFIG_MCC_DM*/ + +#endif diff --git a/hal/phydm/phydm_auto_dbg.c b/hal/phydm/phydm_auto_dbg.c new file mode 100644 index 0000000..203764d --- /dev/null +++ b/hal/phydm/phydm_auto_dbg.c @@ -0,0 +1,725 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_AUTO_DEGBUG + +void phydm_check_hang_reset( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + + atd_t->dbg_step = 0; + atd_t->auto_dbg_type = AUTO_DBG_STOP; + phydm_pause_dm_watchdog(dm, PHYDM_RESUME); + dm->debug_components &= (~ODM_COMP_API); +} + +void phydm_check_hang_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + + atd_t->dbg_step = 0; + atd_t->auto_dbg_type = AUTO_DBG_STOP; + phydm_pause_dm_watchdog(dm, PHYDM_RESUME); +} + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) +void phydm_auto_check_hang_engine_n( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + struct n_dbgport_803 dbgport_803 = {0}; + u32 value32_tmp = 0, value32_tmp_2 = 0; + u8 i; + u32 curr_dbg_port_val[DBGPORT_CHK_NUM] = {0, 0, 0, 0, 0, 0}; + u16 curr_ofdm_t_cnt; + u16 curr_ofdm_r_cnt; + u16 curr_cck_t_cnt; + u16 curr_cck_r_cnt; + u16 curr_ofdm_crc_error_cnt; + u16 curr_cck_crc_error_cnt; + u16 diff_ofdm_t_cnt; + u16 diff_ofdm_r_cnt; + u16 diff_cck_t_cnt; + u16 diff_cck_r_cnt; + u16 diff_ofdm_crc_error_cnt; + u16 diff_cck_crc_error_cnt; + u8 rf_mode; + + if (atd_t->auto_dbg_type == AUTO_DBG_STOP) + return; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_check_hang_reset(dm); + return; + } + + if (atd_t->dbg_step == 0) { + pr_debug("dbg_step=0\n\n"); + + /*Reset all packet counter*/ + odm_set_bb_reg(dm, R_0xf14, BIT(16), 1); + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0); + + } else if (atd_t->dbg_step == 1) { + pr_debug("dbg_step=1\n\n"); + + /*Check packet counter Register*/ + atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD); + atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD); + atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, + MASKHWORD); + + atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD); + atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD); + atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84, + 0x3fff); + + /*Check Debug Port*/ + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, + (u32)atd_t->dbg_port_table[i]) + ) { + atd_t->dbg_port_val[i] = + phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } + } + + } else if (atd_t->dbg_step == 2) { + pr_debug("dbg_step=2\n\n"); + + /*Check packet counter Register*/ + curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD); + curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD); + curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, + MASKHWORD); + + curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD); + curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD); + curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84, + 0x3fff); + + /*Check Debug Port*/ + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, + (u32)atd_t->dbg_port_table[i]) + ) { + curr_dbg_port_val[i] = + phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } + } + + /*=== Make check hang decision ===============================*/ + pr_debug("Check Hang Decision\n\n"); + + /* ----- Check RF Register -----------------------------------*/ + for (i = 0; i < dm->num_rf_path; i++) { + rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000); + pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode); + if (rf_mode > 3) { + pr_debug("Incorrect RF mode\n"); + pr_debug("ReasonCode:RHN-1\n"); + } + } + value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000); + if (dm->support_ic_type == ODM_RTL8188E) { + if (value32_tmp != 0xff8c8) { + pr_debug("ReasonCode:RHN-3\n"); + } + } + /* ----- Check BB Register ----------------------------------*/ + /*BB mode table*/ + value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe); + value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe); + pr_debug("BB TX mode table {A, B}= {%d, %d}\n", + value32_tmp, value32_tmp_2); + + if (value32_tmp > 3 || value32_tmp_2 > 3) { + pr_debug("ReasonCode:RHN-2\n"); + } + + value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000); + value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000); + pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp, + value32_tmp_2); + + if (value32_tmp > 3 || value32_tmp_2 > 3) { + pr_debug("ReasonCode:RHN-2\n"); + } + + /*BB HW Block*/ + value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD); + + if (!(value32_tmp & BIT(24))) { + pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n"); + pr_debug("ReasonCode: THN-3\n"); + } + + if (!(value32_tmp & BIT(25))) { + pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n"); + pr_debug("ReasonCode:THN-3\n"); + } + + /*BB Continue TX*/ + value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000); + pr_debug("Continue TX=%d\n", value32_tmp); + if (value32_tmp != 0) { + pr_debug("ReasonCode: THN-4\n"); + } + + /* ----- Check Packet Counter --------------------------------*/ + diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt; + diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt; + diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt - + atd_t->ofdm_crc_error_cnt; + + diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt; + diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt; + diff_cck_crc_error_cnt = curr_cck_crc_error_cnt - + atd_t->cck_crc_error_cnt; + + pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n", + atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt, + atd_t->ofdm_crc_error_cnt); + pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n", + curr_ofdm_t_cnt, curr_ofdm_r_cnt, + curr_ofdm_crc_error_cnt); + pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n", + diff_ofdm_t_cnt, diff_ofdm_r_cnt, + diff_ofdm_crc_error_cnt); + + pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n", + atd_t->cck_t_cnt, atd_t->cck_r_cnt, + atd_t->cck_crc_error_cnt); + pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n", + curr_cck_t_cnt, curr_cck_r_cnt, + curr_cck_crc_error_cnt); + pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n", + diff_cck_t_cnt, diff_cck_r_cnt, + diff_cck_crc_error_cnt); + + /* ----- Check Dbg Port --------------------------------*/ + + for (i = 0; i < DBGPORT_CHK_NUM; i++) { + pr_debug("Dbg_port=((0x%x))\n", + atd_t->dbg_port_table[i]); + pr_debug("Val{pre, curr}={0x%x, 0x%x}\n", + atd_t->dbg_port_val[i], curr_dbg_port_val[i]); + + if (atd_t->dbg_port_table[i] == 0) { + if (atd_t->dbg_port_val[i] == + curr_dbg_port_val[i]) { + pr_debug("BB state hang\n"); + pr_debug("ReasonCode:\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0x803) { + if (atd_t->dbg_port_val[i] == + curr_dbg_port_val[i]) { + /* dbgport_803 = */ + /* (struct n_dbgport_803 ) */ + /* (atd_t->dbg_port_val[i]); */ + odm_move_memory(dm, &dbgport_803, + &atd_t->dbg_port_val[i], + sizeof(struct n_dbgport_803)); + pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n", + dbgport_803.bb_rst_b, + dbgport_803.glb_rst_b, + dbgport_803.ofdm_rst_b); + pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n", + dbgport_803.ofdm_tx_en, + dbgport_803.cck_tx_en, + dbgport_803.phy_tx_on); + pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n", + dbgport_803.ofdm_cca_pp, + dbgport_803.cck_cca_pp); + + if (dbgport_803.phy_tx_on) + pr_debug("Maybe TX Hang\n"); + else if (dbgport_803.ofdm_cca_pp || + dbgport_803.cck_cca_pp) + pr_debug("Maybe RX Hang\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0x208) { + if ((atd_t->dbg_port_val[i] & BIT(30)) && + (curr_dbg_port_val[i] & BIT(30))) { + pr_debug("EDCCA Pause TX\n"); + pr_debug("ReasonCode: THN-2\n"); + } + + } else if (atd_t->dbg_port_table[i] == 0xab0) { + /* atd_t->dbg_port_val[i] & 0xffffff == 0 */ + /* curr_dbg_port_val[i] & 0xffffff == 0 */ + if (((atd_t->dbg_port_val[i] & + MASK24BITS) == 0) || + ((curr_dbg_port_val[i] & + MASK24BITS) == 0)) { + pr_debug("Wrong L-SIG formate\n"); + pr_debug("ReasonCode: THN-1\n"); + } + } + } + + phydm_check_hang_reset(dm); + } + + atd_t->dbg_step++; +} + +void phydm_bb_auto_check_hang_start_n( + void *dm_void, + u32 *_used, + char *output, + u32 *_out_len) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + return; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM auto check hang (N-series) is started, Please check the system log\n"); + + dm->debug_components |= ODM_COMP_API; + atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG; + atd_t->dbg_step = 0; + + phydm_pause_dm_watchdog(dm, PHYDM_PAUSE); + + *_used = used; + *_out_len = out_len; +} + +void phydm_dbg_port_dump_n(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + return; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "not support now\n"); + + *_used = used; + *_out_len = out_len; +} + +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) +void phydm_dbg_port_dump_ac(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + u32 value32 = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) + return; + + value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32); + + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7); + + /* dbg_port = basic state machine */ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "basic state machine", value32); + } + + /* dbg_port = state machine */ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "state machine", value32); + } + + /* dbg_port = CCA-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "CCA-related", value32); + } + + /* dbg_port = edcca/rxd*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "edcca/rxd", value32); + } + + /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", + "rx_state/mux_state/ADC_MASK_OFDM", value32); + } + + /* dbg_port = bf-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "bf-related", value32); + } + + /* dbg_port = bf-related*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "bf-related", value32); + } + + /* dbg_port = txon/rxd*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "txon/rxd", value32); + } + + /* dbg_port = l_rate/l_length*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "l_rate/l_length", value32); + } + + /* dbg_port = rxd/rxd_hit*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rxd/rxd_hit", value32); + } + + /* dbg_port = dis_cca*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "dis_cca", value32); + } + + /* dbg_port = tx*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "tx", value32); + } + + /* dbg_port = rx plcp*/ + { + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + + odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3); + value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "0x8fc", value32); + + value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = 0x%x", "rx plcp", value32); + } + *_used = used; + *_out_len = out_len; +} +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + /*u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};*/ + u32 val = 0; + u32 dbg_port_idx = 0; + u32 i = 0; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "%-17s = %s\n", "DbgPort index", "Value"); + +#if 0 + /*0x000/0x001/0x002*/ + for (i = 0; i < 3; i++) { + dbg_port_idx = dbg_port_idx_all[i]; + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) { + val = phydm_get_bb_dbg_port_val(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "0x%-15x = 0x%x\n", dbg_port_idx, val); + phydm_release_bb_dbg_port(dm); + } + } +#endif + for (dbg_port_idx = 0x0; dbg_port_idx <= 0xfff; dbg_port_idx++) { + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) { + val = phydm_get_bb_dbg_port_val(dm); + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, + "0x%-15x = 0x%x\n", dbg_port_idx, val); + phydm_release_bb_dbg_port(dm); + } + } + *_used = used; + *_out_len = out_len; +} +#endif + +void phydm_dbg_port_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "------ BB debug port start ------\n"); + + switch (dm->ic_ip_series) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + case PHYDM_IC_JGR3: + phydm_dbg_port_dump_jgr3(dm, &used, output, &out_len); + break; + #endif + + #if (ODM_IC_11AC_SERIES_SUPPORT == 1) + case PHYDM_IC_AC: + phydm_dbg_port_dump_ac(dm, &used, output, &out_len); + break; + #endif + + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + case PHYDM_IC_N: + phydm_dbg_port_dump_n(dm, &used, output, &out_len); + break; + #endif + + default: + break; + } + *_used = used; + *_out_len = out_len; +} + +void phydm_auto_dbg_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "hang: {1} {1:Show DbgPort, 2:Auto check hang}\n"); + return; + } else if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + if (var1[1] == 1) { + phydm_dbg_port_dump(dm, &used, output, &out_len); + } else if (var1[1] == 2) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + PDM_SNPF(out_len, used, output + used, + out_len - used, "Not support\n"); + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_bb_auto_check_hang_start_n(dm, &used, + output, + &out_len); + #else + PDM_SNPF(out_len, used, output + used, + out_len - used, "Not support\n"); + #endif + } + } + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_auto_dbg_engine(void *dm_void) +{ + u32 value32 = 0; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + + if (atd_t->auto_dbg_type == AUTO_DBG_STOP) + return; + + pr_debug("%s ======>\n", __func__); + + if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + pr_debug("Not Support\n"); + } else { + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + phydm_auto_check_hang_engine_n(dm); + #else + pr_debug("Not Support\n"); + #endif + } + + } else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) { + pr_debug("Not Support\n"); + } +} + +void phydm_auto_dbg_engine_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table; + u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0, + 0xab1, 0xab2}; + + PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__); + + odm_move_memory(dm, &atd_t->dbg_port_table[0], + &dbg_port_table[0], (DBGPORT_CHK_NUM * 2)); + + phydm_check_hang_init(dm); +} +#endif diff --git a/hal/phydm/phydm_auto_dbg.h b/hal/phydm/phydm_auto_dbg.h new file mode 100644 index 0000000..78bde62 --- /dev/null +++ b/hal/phydm/phydm_auto_dbg.h @@ -0,0 +1,115 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_AUTO_DBG_H__ +#define __PHYDM_AUTO_DBG_H__ + +#define AUTO_DBG_VERSION "1.0" /* @2017.05.015 Dino, Add phydm_auto_dbg.h*/ + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#define AUTO_CHK_HANG_STEP_MAX 3 +#define DBGPORT_CHK_NUM 6 + +#ifdef PHYDM_AUTO_DEGBUG + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +enum auto_dbg_type_e { + AUTO_DBG_STOP = 0, + AUTO_DBG_CHECK_HANG = 1, + AUTO_DBG_CHECK_RA = 2, + AUTO_DBG_CHECK_DIG = 3 +}; + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +struct n_dbgport_803 { + /*@BYTE 3*/ + u8 bb_rst_b : 1; + u8 glb_rst_b : 1; + u8 zero_1bit_1 : 1; + u8 ofdm_rst_b : 1; + u8 cck_txpe : 1; + u8 ofdm_txpe : 1; + u8 phy_tx_on : 1; + u8 tdrdy : 1; + /*@BYTE 2*/ + u8 txd : 8; + /*@BYTE 1*/ + u8 cck_cca_pp : 1; + u8 ofdm_cca_pp : 1; + u8 rx_rst : 1; + u8 rdrdy : 1; + u8 rxd_7_4 : 4; + /*@BYTE 0*/ + u8 rxd_3_0 : 4; + u8 ofdm_tx_en : 1; + u8 cck_tx_en : 1; + u8 zero_1bit_2 : 1; + u8 clk_80m : 1; +}; + +struct phydm_auto_dbg_struct { + enum auto_dbg_type_e auto_dbg_type; + u8 dbg_step; + u16 dbg_port_table[DBGPORT_CHK_NUM]; + u32 dbg_port_val[DBGPORT_CHK_NUM]; + u16 ofdm_t_cnt; + u16 ofdm_r_cnt; + u16 cck_t_cnt; + u16 cck_r_cnt; + u16 ofdm_crc_error_cnt; + u16 cck_crc_error_cnt; +}; + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ + +void phydm_dbg_port_dump(void *dm_void, u32 *used, char *output, u32 *out_len); + +void phydm_auto_dbg_console( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +void phydm_auto_dbg_engine(void *dm_void); + +void phydm_auto_dbg_engine_init(void *dm_void); +#endif +#endif diff --git a/hal/phydm/phydm_beamforming.c b/hal/phydm/phydm_beamforming.c new file mode 100644 index 0000000..1c055c8 --- /dev/null +++ b/hal/phydm/phydm_beamforming.c @@ -0,0 +1,1989 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if WPP_SOFTWARE_TRACE + #include "phydm_beamforming.tmh" + #endif +#endif + +#ifdef PHYDM_BEAMFORMING_SUPPORT + +void phydm_get_txbf_device_num( + void *dm_void, + u8 macid) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*@For BDC*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct bf_cmn_info *bf = NULL; + struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table; + u8 act_as_bfer = 0; + u8 act_as_bfee = 0; + + if (!(dm->support_ability & ODM_BB_ANT_DIV)) + return; + + if (is_sta_active(sta)) { + bf = &(sta->bf_info); + } else { + PHYDM_DBG(dm, DBG_TXBF, "[Warning] %s invalid sta_info\n", + __func__); + return; + } + + if (sta->support_wireless_set & WIRELESS_VHT) { + if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE) + act_as_bfer = 1; + + if (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMER_ENABLE) + act_as_bfee = 1; + + } else if (sta->support_wireless_set & WIRELESS_HT) { + if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) + act_as_bfer = 1; + + if (bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMER_ENABLE) + act_as_bfee = 1; + } + + if (act_as_bfer) + { /* Our Device act as BFer */ + dm_bdc_table->w_bfee_client[macid] = true; + dm_bdc_table->num_txbfee_client++; + } + else + dm_bdc_table->w_bfee_client[macid] = false; + + if (act_as_bfee) + { /* Our Device act as BFee */ + dm_bdc_table->w_bfer_client[macid] = true; + dm_bdc_table->num_txbfer_client++; + } + else + dm_bdc_table->w_bfer_client[macid] = false; + +#endif +#endif +} + +struct _RT_BEAMFORM_STAINFO * +phydm_sta_info_init(struct dm_struct *dm, u16 sta_idx, u8 *my_mac_addr) +{ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORM_STAINFO *entry = &beam_info->beamform_sta_info; + struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx]; + //void *adapter = dm->adapter; + ADAPTER * adapter = dm->adapter; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO p_MgntInfo = &((adapter)->MgntInfo); + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); +#endif + + if (!is_sta_active(cmn_sta)) { + PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n", + __func__, sta_idx); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_warn_on(1); + #endif + + return entry; + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*odm_move_memory(dm, (PVOID)(entry->my_mac_addr),*/ + /*(PVOID)(adapter->CurrentAddress), 6);*/ + odm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + /*odm_move_memory(dm, entry->my_mac_addr,*/ + /*adapter_mac_addr(sta->padapter), 6);*/ + odm_move_memory(dm, entry->my_mac_addr, my_mac_addr, 6); +#endif + + entry->aid = cmn_sta->aid; + entry->ra = cmn_sta->mac_addr; + entry->mac_id = cmn_sta->mac_id; + entry->bw = cmn_sta->bw_mode; + entry->cur_beamform = cmn_sta->bf_info.ht_beamform_cap; + entry->ht_beamform_cap = cmn_sta->bf_info.ht_beamform_cap; + +#if ODM_IC_11AC_SERIES_SUPPORT + if (cmn_sta->support_wireless_set & WIRELESS_VHT) { + entry->cur_beamform_vht = cmn_sta->bf_info.vht_beamform_cap; + entry->vht_beamform_cap = cmn_sta->bf_info.vht_beamform_cap; + } +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*To Be Removed */ + entry->ht_beamform_cap = p_ht_info->HtBeamformCap; /*To Be Removed*/ + entry->vht_beamform_cap = p_vht_info->VhtBeamformCap; /*To Be Removed*/ + + if (sta_idx == 0) { /*@client mode*/ + #if ODM_IC_11AC_SERIES_SUPPORT + if (cmn_sta->support_wireless_set & WIRELESS_VHT) + entry->cur_beamform_vht = p_vht_info->VhtCurBeamform; + #endif + } +#endif + + PHYDM_DBG(dm, DBG_TXBF, "wireless_set = 0x%x, staidx = %d\n", + cmn_sta->support_wireless_set, sta_idx); + PHYDM_DBG(dm, DBG_TXBF, + "entry->cur_beamform = 0x%x, entry->cur_beamform_vht = 0x%x\n", + entry->cur_beamform, entry->cur_beamform_vht); + return entry; +} +void phydm_sta_info_update( + struct dm_struct *dm, + u16 sta_idx, + struct _RT_BEAMFORMEE_ENTRY *beamform_entry) +{ + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + + if (!is_sta_active(sta)) + return; + + sta->bf_info.p_aid = beamform_entry->p_aid; + sta->bf_info.g_id = beamform_entry->g_id; +} + +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_bfee_entry_by_addr( + void *dm_void, + u8 *RA, + u8 *idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (beam_info->beamformee_entry[i].is_used && (eq_mac_addr(RA, beam_info->beamformee_entry[i].mac_addr))) { + *idx = i; + return &beam_info->beamformee_entry[i]; + } + } + + return NULL; +} + +struct _RT_BEAMFORMER_ENTRY * +phydm_beamforming_get_bfer_entry_by_addr( + void *dm_void, + u8 *TA, + u8 *idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + if (beam_info->beamformer_entry[i].is_used && (eq_mac_addr(TA, beam_info->beamformer_entry[i].mac_addr))) { + *idx = i; + return &beam_info->beamformer_entry[i]; + } + } + + return NULL; +} + +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_entry_by_mac_id( + void *dm_void, + u8 mac_id, + u8 *idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) { + *idx = i; + return &beam_info->beamformee_entry[i]; + } + } + + return NULL; +} + +enum beamforming_cap +phydm_beamforming_get_entry_beam_cap_by_mac_id( + void *dm_void, + u8 mac_id) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + enum beamforming_cap beamform_entry_cap = BEAMFORMING_CAP_NONE; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (beam_info->beamformee_entry[i].is_used && mac_id == beam_info->beamformee_entry[i].mac_id) { + beamform_entry_cap = beam_info->beamformee_entry[i].beamform_entry_cap; + i = BEAMFORMEE_ENTRY_NUM; + } + } + + return beamform_entry_cap; +} + +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_free_bfee_entry( + void *dm_void, + u8 *idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (beam_info->beamformee_entry[i].is_used == false) { + *idx = i; + return &beam_info->beamformee_entry[i]; + } + } + return NULL; +} + +struct _RT_BEAMFORMER_ENTRY * +phydm_beamforming_get_free_bfer_entry( + void *dm_void, + u8 *idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + PHYDM_DBG(dm, DBG_TXBF, "%s ===>\n", __func__); + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + if (beam_info->beamformer_entry[i].is_used == false) { + *idx = i; + return &beam_info->beamformer_entry[i]; + } + } + return NULL; +} + +/*@ + * Description: Get the first entry index of MU Beamformee. + * + * Return value: index of the first MU sta. + * + * 2015.05.25. Created by tynli. + * + */ +u8 phydm_beamforming_get_first_mu_bfee_entry_idx( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0xFF; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + boolean is_found = false; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (beam_info->beamformee_entry[idx].is_used && beam_info->beamformee_entry[idx].is_mu_sta) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] idx=%d!\n", __func__, + idx); + is_found = true; + break; + } + } + + if (!is_found) + idx = 0xFF; + + return idx; +} + +/*@Add SU BFee and MU BFee*/ +struct _RT_BEAMFORMEE_ENTRY * +beamforming_add_bfee_entry( + void *dm_void, + struct _RT_BEAMFORM_STAINFO *sta, + enum beamforming_cap beamform_cap, + u8 num_of_sounding_dim, + u8 comp_steering_num_of_bfer, + u8 *idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry = phydm_beamforming_get_free_bfee_entry(dm, idx); + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (entry != NULL) { + entry->is_used = true; + entry->aid = sta->aid; + entry->mac_id = sta->mac_id; + entry->sound_bw = sta->bw; + odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6); + + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { + /*@BSSID[44:47] xor BSSID[40:43]*/ + u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf); + /*@(dec(A) + dec(B)*32) mod 512*/ + entry->p_aid = (sta->aid + bssid * 32) & 0x1ff; + entry->g_id = 63; + PHYDM_DBG(dm, DBG_TXBF, + "%s: BFee P_AID addressed to STA=%d\n", + __func__, entry->p_aid); + } else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) { + /*@ad hoc mode*/ + entry->p_aid = 0; + entry->g_id = 63; + PHYDM_DBG(dm, DBG_TXBF, "%s: BFee P_AID as IBSS=%d\n", + __func__, entry->p_aid); + } else { + /*@client mode*/ + entry->p_aid = sta->ra[5]; + /*@BSSID[39:47]*/ + entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7); + entry->g_id = 0; + PHYDM_DBG(dm, DBG_TXBF, + "%s: BFee P_AID addressed to AP=0x%X\n", + __func__, entry->p_aid); + } + cp_mac_addr(entry->mac_addr, sta->ra); + entry->is_txbf = false; + entry->is_sound = false; + entry->sound_period = 400; + entry->beamform_entry_cap = beamform_cap; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + + /* @entry->log_seq = 0xff; Move to beamforming_add_bfer_entry*/ + /* @entry->log_retry_cnt = 0; Move to beamforming_add_bfer_entry*/ + /* @entry->LogSuccessCnt = 0; Move to beamforming_add_bfer_entry*/ + + entry->log_status_fail_cnt = 0; + + entry->num_of_sounding_dim = num_of_sounding_dim; + entry->comp_steering_num_of_bfer = comp_steering_num_of_bfer; + + if (beamform_cap & BEAMFORMER_CAP_VHT_MU) { + dm->beamforming_info.beamformee_mu_cnt += 1; + entry->is_mu_sta = true; + dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm); + } else if (beamform_cap & (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { + dm->beamforming_info.beamformee_su_cnt += 1; + entry->is_mu_sta = false; + } + + return entry; + } else + return NULL; +} + +/*@Add SU BFee and MU BFer*/ +struct _RT_BEAMFORMER_ENTRY * +beamforming_add_bfer_entry( + void *dm_void, + struct _RT_BEAMFORM_STAINFO *sta, + enum beamforming_cap beamform_cap, + u8 num_of_sounding_dim, + u8 *idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMER_ENTRY *entry = phydm_beamforming_get_free_bfer_entry(dm, idx); + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (entry != NULL) { + entry->is_used = true; + odm_move_memory(dm, entry->my_mac_addr, sta->my_mac_addr, 6); + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { + /*@BSSID[44:47] xor BSSID[40:43]*/ + u16 bssid = ((sta->my_mac_addr[5] & 0xf0) >> 4) ^ (sta->my_mac_addr[5] & 0xf); + + entry->p_aid = (sta->aid + bssid * 32) & 0x1ff; + entry->g_id = 63; + /*@(dec(A) + dec(B)*32) mod 512*/ + } else if (phydm_acting_determine(dm, phydm_acting_as_ibss)) { + entry->p_aid = 0; + entry->g_id = 63; + } else { + entry->p_aid = sta->ra[5]; + /*@BSSID[39:47]*/ + entry->p_aid = (entry->p_aid << 1) | (sta->ra[4] >> 7); + entry->g_id = 0; + PHYDM_DBG(dm, DBG_TXBF, + "%s: P_AID addressed to AP=0x%X\n", __func__, + entry->p_aid); + } + + cp_mac_addr(entry->mac_addr, sta->ra); + entry->beamform_entry_cap = beamform_cap; + + entry->pre_log_seq = 0; /*@Modified by Jeffery @2015-04-13*/ + entry->log_seq = 0; /*@Modified by Jeffery @2014-10-29*/ + entry->log_retry_cnt = 0; /*@Modified by Jeffery @2014-10-29*/ + entry->log_success = 0; /*@log_success is NOT needed to be accumulated, so LogSuccessCnt->log_success, 2015-04-13, Jeffery*/ + entry->clock_reset_times = 0; /*@Modified by Jeffery @2015-04-13*/ + + entry->num_of_sounding_dim = num_of_sounding_dim; + + if (beamform_cap & BEAMFORMEE_CAP_VHT_MU) { + dm->beamforming_info.beamformer_mu_cnt += 1; + entry->is_mu_ap = true; + entry->aid = sta->aid; + } else if (beamform_cap & (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { + dm->beamforming_info.beamformer_su_cnt += 1; + entry->is_mu_ap = false; + } + + return entry; + } else + return NULL; +} + +/* Used for beamforming_start_v1 */ +void phydm_beamforming_ndpa_rate( + void *dm_void, + enum channel_width BW, + u8 rate) +{ + u16 ndpa_rate = rate; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (ndpa_rate == 0) { + if (dm->rssi_min > 30) /* @link RSSI > 30% */ + ndpa_rate = ODM_RATE24M; + else + ndpa_rate = ODM_RATE6M; + } + + if (ndpa_rate < ODM_RATEMCS0) + BW = (enum channel_width)CHANNEL_WIDTH_20; + + ndpa_rate = (ndpa_rate << 8) | BW; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); +} + +/* Used for beamforming_start_sw and beamforming_start_fw */ +void phydm_beamforming_dym_ndpa_rate( + void *dm_void) +{ + u16 ndpa_rate = ODM_RATE6M, BW; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + ndpa_rate = ODM_RATE6M; + BW = CHANNEL_WIDTH_20; + + ndpa_rate = ndpa_rate << 8 | BW; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_RATE, (u8 *)&ndpa_rate); + PHYDM_DBG(dm, DBG_TXBF, "%s End, NDPA rate = 0x%X\n", __func__, + ndpa_rate); +} + +/*@ +* SW Sounding : SW Timer unit 1ms +* HW Timer unit (1/32000) s 32k is clock. +* FW Sounding : FW Timer unit 10ms +*/ +void beamforming_dym_period( + void *dm_void, + u8 status) +{ + u8 idx; + boolean is_change_period = false; + u16 sound_period_sw, sound_period_fw; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + struct _RT_BEAMFORMEE_ENTRY *beamform_entry; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; + + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + /* @3 TODO per-client throughput caculation. */ + + if ((*dm->current_tx_tp + *dm->current_rx_tp > 2) && (entry->log_status_fail_cnt <= 20 || status)) { + sound_period_sw = 40; /* @40ms */ + sound_period_fw = 40; /* @From H2C cmd, unit = 10ms */ + } else { + sound_period_sw = 4000; /* @4s */ + sound_period_fw = 400; + } + PHYDM_DBG(dm, DBG_TXBF, "[%s]sound_period_sw=%d, sound_period_fw=%d\n", + __func__, sound_period_sw, sound_period_fw); + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + beamform_entry = beam_info->beamformee_entry + idx; + + if (beamform_entry->default_csi_cnt > 20) { + /*@Modified by David*/ + sound_period_sw = 4000; + sound_period_fw = 400; + } + + PHYDM_DBG(dm, DBG_TXBF, "[%s] period = %d\n", __func__, + sound_period_sw); + if ((beamform_entry->beamform_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) == 0) + continue; + + if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) { + if (beamform_entry->sound_period != sound_period_fw) { + beamform_entry->sound_period = sound_period_fw; + is_change_period = true; /*Only FW sounding need to send H2C packet to change sound period. */ + } + } else if (beamform_entry->sound_period != sound_period_sw) + beamform_entry->sound_period = sound_period_sw; + } + + if (is_change_period) + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); +} + +boolean +beamforming_send_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW, + u8 q_idx) +{ + boolean ret = true; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (q_idx == BEACON_QUEUE) + ret = send_fw_ht_ndpa_packet(dm, RA, BW); + else + ret = send_sw_ht_ndpa_packet(dm, RA, BW); + + return ret; +} + +boolean +beamforming_send_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW, + u8 q_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + boolean ret = true; + + hal_com_txbf_set(dm, TXBF_SET_GET_TX_RATE, NULL); + + if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) + PHYDM_DBG(dm, DBG_TXBF, "@%s: 3SS VHT 789 don't sounding\n", + __func__); + + else { + if (q_idx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ + ret = send_fw_vht_ndpa_packet(dm, RA, AID, BW); + else { +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) + beam_info->is_mu_sounding = true; + ret = send_sw_vht_mu_ndpa_packet(dm, BW); +#else + beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW); +#endif +#else + beam_info->is_mu_sounding = false; + ret = send_sw_vht_ndpa_packet(dm, RA, AID, BW); +#endif + } + } + return ret; +} + +enum beamforming_notify_state +phydm_beamfomring_is_sounding( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + u8 *idx) +{ + enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + /*@if(( Beamforming_GetBeamCap(beam_info) & BEAMFORMER_CAP) == 0)*/ + /*@is_sounding = BEAMFORMING_NOTIFY_RESET;*/ + if (beam_oid_info.sound_oid_mode == sounding_stop_all_timer) { + is_sounding = BEAMFORMING_NOTIFY_RESET; + goto out; + } + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + PHYDM_DBG(dm, DBG_TXBF, + "@%s: BFee Entry %d is_used=%d, is_sound=%d\n", + __func__, i, beam_info->beamformee_entry[i].is_used, + beam_info->beamformee_entry[i].is_sound); + if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Add BFee entry %d\n", + __func__, i); + *idx = i; + if (beam_info->beamformee_entry[i].is_mu_sta) + is_sounding = BEAMFORMEE_NOTIFY_ADD_MU; + else + is_sounding = BEAMFORMEE_NOTIFY_ADD_SU; + } + + if (!beam_info->beamformee_entry[i].is_used && beam_info->beamformee_entry[i].is_sound) { + PHYDM_DBG(dm, DBG_TXBF, "%s: Delete BFee entry %d\n", + __func__, i); + *idx = i; + if (beam_info->beamformee_entry[i].is_mu_sta) + is_sounding = BEAMFORMEE_NOTIFY_DELETE_MU; + else + is_sounding = BEAMFORMEE_NOTIFY_DELETE_SU; + } + } + +out: + PHYDM_DBG(dm, DBG_TXBF, "%s End, is_sounding = %d\n", __func__, + is_sounding); + return is_sounding; +} + +/* This function is unused */ +u8 phydm_beamforming_sounding_idx( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) +{ + u8 idx = 0; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || + beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) + idx = beam_oid_info.sound_oid_idx; + else { + u8 i; + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (beam_info->beamformee_entry[i].is_used && !beam_info->beamformee_entry[i].is_sound) { + idx = i; + break; + } + } + } + + return idx; +} + +enum sounding_mode +phydm_beamforming_sounding_mode( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 support_interface = dm->support_interface; + + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + enum sounding_mode mode = beam_oid_info.sound_oid_mode; + + if (beam_oid_info.sound_oid_mode == SOUNDING_SW_VHT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_VHT_TIMER) { + if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) + mode = beam_oid_info.sound_oid_mode; + else + mode = sounding_stop_all_timer; + } else if (beam_oid_info.sound_oid_mode == SOUNDING_SW_HT_TIMER || beam_oid_info.sound_oid_mode == SOUNDING_HW_HT_TIMER) { + if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + mode = beam_oid_info.sound_oid_mode; + else + mode = sounding_stop_all_timer; + } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_VHT_SU) { + if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + mode = SOUNDING_FW_VHT_TIMER; + else + mode = SOUNDING_SW_VHT_TIMER; + } else if (beam_entry.beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) { + if (support_interface == ODM_ITRF_USB && !(dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B))) + mode = SOUNDING_FW_HT_TIMER; + else + mode = SOUNDING_SW_HT_TIMER; + } else + mode = sounding_stop_all_timer; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] support_interface=%d, mode=%d\n", + __func__, support_interface, mode); + + return mode; +} + +u16 phydm_beamforming_sounding_time( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + enum sounding_mode mode, + u8 idx) +{ + u16 sounding_time = 0xffff; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) + sounding_time = beam_oid_info.sound_oid_period * 32; + else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER) + /*@Modified by David*/ + sounding_time = beam_entry.sound_period; /*@beam_oid_info.sound_oid_period;*/ + else + sounding_time = beam_entry.sound_period; + + return sounding_time; +} + +enum channel_width +phydm_beamforming_sounding_bw( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info, + enum sounding_mode mode, + u8 idx) +{ + enum channel_width sounding_bw = CHANNEL_WIDTH_20; + struct _RT_BEAMFORMEE_ENTRY beam_entry = beam_info->beamformee_entry[idx]; + struct _RT_BEAMFORMING_OID_INFO beam_oid_info = beam_info->beamforming_oid_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_HW_VHT_TIMER) + sounding_bw = beam_oid_info.sound_oid_bw; + else if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_SW_VHT_TIMER) + /*@Modified by David*/ + sounding_bw = beam_entry.sound_bw; /*@beam_oid_info.sound_oid_bw;*/ + else + sounding_bw = beam_entry.sound_bw; + + PHYDM_DBG(dm, DBG_TXBF, "%s, sounding_bw=0x%X\n", __func__, + sounding_bw); + + return sounding_bw; +} + +boolean +phydm_beamforming_select_beam_entry( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) +{ + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@entry.is_sound is different between first and latter NDPA, and should not be used as BFee entry selection*/ + /*@BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed sound_idx.*/ + sound_info->sound_idx = phydm_beamforming_sounding_idx(dm, beam_info); + /*sound_info->sound_idx = 0;*/ + + if (sound_info->sound_idx < BEAMFORMEE_ENTRY_NUM) + sound_info->sound_mode = phydm_beamforming_sounding_mode(dm, beam_info, sound_info->sound_idx); + else + sound_info->sound_mode = sounding_stop_all_timer; + + if (sounding_stop_all_timer == sound_info->sound_mode) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] Return because of sounding_stop_all_timer\n", + __func__); + return false; + } else { + sound_info->sound_bw = phydm_beamforming_sounding_bw(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx); + sound_info->sound_period = phydm_beamforming_sounding_time(dm, beam_info, sound_info->sound_mode, sound_info->sound_idx); + return true; + } +} + +/*SU BFee Entry Only*/ +boolean +phydm_beamforming_start_period( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; + + phydm_beamforming_dym_ndpa_rate(dm); + + phydm_beamforming_select_beam_entry(dm, beam_info); /* @Modified */ + + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period); + else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) { + HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; + u32 val = (sound_info->sound_period | (timer_type << 16)); + + /* @HW timer stop: All IC has the same setting */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /* odm_write_1byte(dm, 0x15F, 0); */ + /* @HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_INIT, (u8 *)(&val)); + /* odm_write_1byte(dm, 0x164, 1); */ + /* odm_write_4byte(dm, 0x15C, val); */ + /* @HW timer start: All IC has the same setting */ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_START, (u8 *)(&timer_type)); + /* odm_write_1byte(dm, 0x15F, 0x5); */ + } else if (sound_info->sound_mode == SOUNDING_FW_VHT_TIMER || sound_info->sound_mode == SOUNDING_FW_HT_TIMER) + ret = beamforming_start_fw(dm, sound_info->sound_idx); + else + ret = false; + + PHYDM_DBG(dm, DBG_TXBF, + "[%s] sound_idx=%d, sound_mode=%d, sound_bw=%d, sound_period=%d\n", + __func__, sound_info->sound_idx, sound_info->sound_mode, + sound_info->sound_bw, sound_info->sound_period); + + return ret; +} + +/* Used after beamforming_leave, and will clear the setting of the "already deleted" entry + *SU BFee Entry Only*/ +void phydm_beamforming_end_period_sw( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*void *adapter = dm->adapter;*/ + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; + + HAL_HW_TIMER_TYPE timer_type = HAL_TIMER_TXBF; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_cancel_timer(dm, &beam_info->beamforming_timer); + else if (sound_info->sound_mode == SOUNDING_HW_VHT_TIMER || sound_info->sound_mode == SOUNDING_HW_HT_TIMER || + sound_info->sound_mode == SOUNDING_AUTO_VHT_TIMER || sound_info->sound_mode == SOUNDING_AUTO_HT_TIMER) + /*@HW timer stop: All IC has the same setting*/ + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_STOP, (u8 *)(&timer_type)); + /*odm_write_1byte(dm, 0x15F, 0);*/ +} + +void phydm_beamforming_end_period_fw( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0; + + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s]\n", __func__); +} + +/*SU BFee Entry Only*/ +void phydm_beamforming_clear_entry_sw( + void *dm_void, + boolean is_delete, + u8 delete_idx) +{ + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + if (is_delete) { + if (delete_idx < BEAMFORMEE_ENTRY_NUM) { + beamform_entry = beam_info->beamformee_entry + delete_idx; + if (!(!beamform_entry->is_used && beamform_entry->is_sound)) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] SW delete_idx is wrong!!!!!\n", + __func__); + return; + } + } + + PHYDM_DBG(dm, DBG_TXBF, "[%s] SW delete BFee entry %d\n", + __func__, delete_idx); + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) { + beamform_entry->is_beamforming_in_progress = false; + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + } else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&delete_idx); + } + beamform_entry->is_sound = false; + return; + } + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + beamform_entry = beam_info->beamformee_entry + idx; + + /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ + /*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ + + if (!beamform_entry->is_sound) + continue; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] SW reset BFee entry %d\n", + __func__, idx); + /*@ + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING) + phydm_beamforming_end_sw(dm, 0); + else if (beamform_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); + } + + beamform_entry->is_sound = false; + } +} + +void phydm_beamforming_clear_entry_fw( + void *dm_void, + boolean is_delete, + u8 delete_idx) +{ + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + if (is_delete) { + if (delete_idx < BEAMFORMEE_ENTRY_NUM) { + beamform_entry = beam_info->beamformee_entry + delete_idx; + + if (!(!beamform_entry->is_used && beamform_entry->is_sound)) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] FW delete_idx is wrong!!!!!\n", + __func__); + return; + } + } + PHYDM_DBG(dm, DBG_TXBF, "%s: FW delete BFee entry %d\n", + __func__, delete_idx); + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + beamform_entry->is_sound = false; + } else { + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + beamform_entry = beam_info->beamformee_entry + idx; + + /*Used after is_sounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "beam_oid_info.sound_oid_mode == sounding_stop_all_timer".*/ + /*@However, setting oid doesn't delete entries (is_used is still true), new entries may fail to be added in.*/ + + if (beamform_entry->is_sound) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s]FW reset BFee entry %d\n", + __func__, idx); + /*@ + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + beamform_entry->is_sound = false; + } + } + } +} + +/*@ +* Called : +* 1. Add and delete entry : beamforming_enter/beamforming_leave +* 2. FW trigger : Beamforming_SetTxBFen +* 3. Set OID_RT_BEAMFORMING_PERIOD : beamforming_control_v2 +*/ +void phydm_beamforming_notify( + void *dm_void) +{ + u8 idx = BEAMFORMEE_ENTRY_NUM; + enum beamforming_notify_state is_sounding = BEAMFORMING_NOTIFY_NONE; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_SOUNDING_INFO *sound_info = &beam_info->sounding_info; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + is_sounding = phydm_beamfomring_is_sounding(dm, beam_info, &idx); + + PHYDM_DBG(dm, DBG_TXBF, "%s, Before notify, is_sounding=%d, idx=%d\n", + __func__, is_sounding, idx); + PHYDM_DBG(dm, DBG_TXBF, "%s: beam_info->beamformee_su_cnt = %d\n", + __func__, beam_info->beamformee_su_cnt); + + switch (is_sounding) { + case BEAMFORMEE_NOTIFY_ADD_SU: + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_SU\n", + __func__); + phydm_beamforming_start_period(dm); + break; + + case BEAMFORMEE_NOTIFY_DELETE_SU: + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", + __func__); + if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(dm, true, idx); + if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_fw(dm); + PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n", + __func__); + } + } else { + phydm_beamforming_clear_entry_sw(dm, true, idx); + if (beam_info->beamformee_su_cnt == 0) { /* @For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_end_period_sw(dm); + PHYDM_DBG(dm, DBG_TXBF, "%s: No BFee left\n", + __func__); + } + } + break; + + case BEAMFORMEE_NOTIFY_ADD_MU: + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_ADD_MU\n", + __func__); + if (beam_info->beamformee_mu_cnt == 2) { + /*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period);*/ + odm_set_timer(dm, &beam_info->beamforming_timer, 1000); /*@Do MU sounding every 1sec*/ + } else + PHYDM_DBG(dm, DBG_TXBF, + "%s: Less or larger than 2 MU STAs, not to set timer\n", + __func__); + break; + + case BEAMFORMEE_NOTIFY_DELETE_MU: + PHYDM_DBG(dm, DBG_TXBF, "%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", + __func__); + if (beam_info->beamformee_mu_cnt == 1) { + /*@if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER)*/ { + odm_cancel_timer(dm, &beam_info->beamforming_timer); + PHYDM_DBG(dm, DBG_TXBF, + "%s: Less than 2 MU STAs, stop sounding\n", + __func__); + } + } + break; + + case BEAMFORMING_NOTIFY_RESET: + if (sound_info->sound_mode == SOUNDING_FW_HT_TIMER || sound_info->sound_mode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_clear_entry_fw(dm, false, idx); + phydm_beamforming_end_period_fw(dm); + } else { + phydm_beamforming_clear_entry_sw(dm, false, idx); + phydm_beamforming_end_period_sw(dm); + } + + break; + + default: + break; + } +} + +boolean +beamforming_init_entry(void *dm_void, u16 sta_idx, u8 *bfer_bfee_idx, + u8 *my_mac_addr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *cmn_sta = dm->phydm_sta_info[sta_idx]; + struct _RT_BEAMFORMEE_ENTRY *beamform_entry = NULL; + struct _RT_BEAMFORMER_ENTRY *beamformer_entry = NULL; + struct _RT_BEAMFORM_STAINFO *sta = NULL; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + u8 bfer_idx = 0xF, bfee_idx = 0xF; + u8 num_of_sounding_dim = 0, comp_steering_num_of_bfer = 0; + + if (!is_sta_active(cmn_sta)) { + PHYDM_DBG(dm, DBG_TXBF, "%s => sta_info(mac_id:%d) failed\n", + __func__, sta_idx); + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_warn_on(1); + #endif + return false; + } + + sta = phydm_sta_info_init(dm, sta_idx, my_mac_addr); + /*The current setting does not support Beaforming*/ + if (BEAMFORMING_CAP_NONE == sta->ht_beamform_cap && BEAMFORMING_CAP_NONE == sta->vht_beamform_cap) { + PHYDM_DBG(dm, DBG_TXBF, + "The configuration disabled Beamforming! Skip...\n"); + return false; + } + + if (!(cmn_sta->support_wireless_set & (WIRELESS_VHT | WIRELESS_HT))) + return false; + else { + if (cmn_sta->support_wireless_set & WIRELESS_HT) { /*@HT*/ + if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { /*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_HT_EXPLICIT); + num_of_sounding_dim = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP) >> 6; + } + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(sta->cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + TEST_FLAG(sta->ht_beamform_cap, BEAMFORMING_HT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT); + comp_steering_num_of_bfer = (sta->cur_beamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM) >> 4; + } + PHYDM_DBG(dm, DBG_TXBF, + "[%s] HT cur_beamform=0x%X, beamform_cap=0x%X\n", + __func__, sta->cur_beamform, beamform_cap); + PHYDM_DBG(dm, DBG_TXBF, + "[%s] HT num_of_sounding_dim=%d, comp_steering_num_of_bfer=%d\n", + __func__, num_of_sounding_dim, + comp_steering_num_of_bfer); + } +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if (cmn_sta->support_wireless_set & WIRELESS_VHT) { /*VHT*/ + + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_SU); + num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + } + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || + TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_SU); + comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; + } + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP_VHT_MU); + num_of_sounding_dim = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM) >> 12; + } + /* We are Beamformer because the STA is MU Beamformee*/ + if (phydm_acting_determine(dm, phydm_acting_as_ap)) { /* Only AP mode supports to act an MU beamformer */ + if (TEST_FLAG(sta->cur_beamform_vht, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || + TEST_FLAG(sta->vht_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP_VHT_MU); + comp_steering_num_of_bfer = (sta->cur_beamform_vht & BEAMFORMING_VHT_BEAMFORMER_STS_CAP) >> 8; + } + } + PHYDM_DBG(dm, DBG_TXBF, + "[%s]VHT cur_beamform_vht=0x%X, beamform_cap=0x%X\n", + __func__, sta->cur_beamform_vht, + beamform_cap); + PHYDM_DBG(dm, DBG_TXBF, + "[%s]VHT num_of_sounding_dim=0x%X, comp_steering_num_of_bfer=0x%X\n", + __func__, num_of_sounding_dim, + comp_steering_num_of_bfer); + } +#endif + } + + if (beamform_cap == BEAMFORMING_CAP_NONE) + return false; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Self BF Entry Cap = 0x%02X\n", __func__, + beamform_cap); + + /*We are BFee, so the entry is BFer*/ + if (beamform_cap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { + beamformer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, sta->ra, &bfer_idx); + + if (beamformer_entry == NULL) { + beamformer_entry = beamforming_add_bfer_entry(dm, sta, beamform_cap, num_of_sounding_dim, &bfer_idx); + if (beamformer_entry == NULL) + PHYDM_DBG(dm, DBG_TXBF, + "[%s]Not enough BFer entry!!!!!\n", + __func__); + } + } + + /*We are BFer, so the entry is BFee*/ + if (beamform_cap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { + beamform_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, sta->ra, &bfee_idx); + + /*@if BFeeIdx = 0xF, that represent for no matched MACID among all linked entrys */ + PHYDM_DBG(dm, DBG_TXBF, "[%s] Get BFee entry 0x%X by address\n", + __func__, bfee_idx); + if (beamform_entry == NULL) { + beamform_entry = beamforming_add_bfee_entry(dm, sta, beamform_cap, num_of_sounding_dim, comp_steering_num_of_bfer, &bfee_idx); + PHYDM_DBG(dm, DBG_TXBF, + "[%s]: sta->AID=%d, sta->mac_id=%d\n", + __func__, sta->aid, sta->mac_id); + + PHYDM_DBG(dm, DBG_TXBF, "[%s]: Add BFee entry %d\n", + __func__, bfee_idx); + + if (beamform_entry == NULL) + return false; + else + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } else { + /*@Entry has been created. If entry is initialing or progressing then errors occur.*/ + if (beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && + beamform_entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) + return false; + else + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } + beamform_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + phydm_sta_info_update(dm, sta_idx, beamform_entry); + } + + *bfer_bfee_idx = (bfer_idx << 4) | bfee_idx; + PHYDM_DBG(dm, DBG_TXBF, + "[%s] End: bfer_idx=0x%X, bfee_idx=0x%X, bfer_bfee_idx=0x%X\n", + __func__, bfer_idx, bfee_idx, *bfer_bfee_idx); + + return true; +} + +void beamforming_deinit_entry( + void *dm_void, + u8 *RA) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0; + + struct _RT_BEAMFORMER_ENTRY *bfer_entry = phydm_beamforming_get_bfer_entry_by_addr(dm, RA, &idx); + struct _RT_BEAMFORMEE_ENTRY *bfee_entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + boolean ret = false; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (bfee_entry != NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, bfee_entry\n", __func__); + bfee_entry->is_used = false; + bfee_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + bfee_entry->is_beamforming_in_progress = false; + if (bfee_entry->is_mu_sta) { + dm->beamforming_info.beamformee_mu_cnt -= 1; + dm->beamforming_info.first_mu_bfee_index = phydm_beamforming_get_first_mu_bfee_entry_idx(dm); + } else + dm->beamforming_info.beamformee_su_cnt -= 1; + ret = true; + } + + if (bfer_entry != NULL) { + PHYDM_DBG(dm, DBG_TXBF, "%s, bfer_entry\n", __func__); + bfer_entry->is_used = false; + bfer_entry->beamform_entry_cap = BEAMFORMING_CAP_NONE; + if (bfer_entry->is_mu_ap) + dm->beamforming_info.beamformer_mu_cnt -= 1; + else + dm->beamforming_info.beamformer_su_cnt -= 1; + ret = true; + } + + if (ret == true) + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_LEAVE, (u8 *)&idx); + + PHYDM_DBG(dm, DBG_TXBF, "%s End, idx = 0x%X\n", __func__, idx); +} + +boolean +beamforming_start_v1( + void *dm_void, + u8 *RA, + boolean mode, + enum channel_width BW, + u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 idx = 0; + struct _RT_BEAMFORMEE_ENTRY *entry; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + entry = phydm_beamforming_get_bfee_entry_by_addr(dm, RA, &idx); + + if (entry->is_used == false) { + entry->is_beamforming_in_progress = false; + return false; + } else { + if (entry->is_beamforming_in_progress) + return false; + + entry->is_beamforming_in_progress = true; + + if (mode == 1) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + entry->is_beamforming_in_progress = false; + return false; + } + } else if (mode == 0) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + entry->is_beamforming_in_progress = false; + return false; + } + } + + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + entry->is_beamforming_in_progress = false; + return false; + } else { + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; + } + } + + entry->sound_bw = BW; + beam_info->beamformee_cur_idx = idx; + phydm_beamforming_ndpa_rate(dm, BW, rate); + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, (u8 *)&idx); + + if (mode == 1) + ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE); + else + ret = beamforming_send_vht_ndpa_packet(dm, RA, entry->aid, BW, NORMAL_QUEUE); + + if (ret == false) { + beamforming_leave(dm, RA); + entry->is_beamforming_in_progress = false; + return false; + } + + PHYDM_DBG(dm, DBG_TXBF, "%s idx %d\n", __func__, idx); + return true; +} + +boolean +beamforming_start_sw( + void *dm_void, + u8 idx, + u8 mode, + enum channel_width BW) +{ + u8 *ra = NULL; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry; + boolean ret = true; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) + u8 i, poll_sta_cnt = 0; + boolean is_get_first_bfee = false; +#endif +#endif + + if (beam_info->is_mu_sounding) { + beam_info->is_mu_sounding_in_progress = true; + entry = &beam_info->beamformee_entry[idx]; + ra = entry->mac_addr; + + } else { + entry = &beam_info->beamformee_entry[idx]; + + if (entry->is_used == false) { + PHYDM_DBG(dm, DBG_TXBF, + "Skip Beamforming, no entry for idx =%d\n", + idx); + entry->is_beamforming_in_progress = false; + return false; + } + + if (entry->is_beamforming_in_progress) { + PHYDM_DBG(dm, DBG_TXBF, + "is_beamforming_in_progress, skip...\n"); + return false; + } + + entry->is_beamforming_in_progress = true; + ra = entry->mac_addr; + + if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, + "%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", + __func__); + return false; + } + } else if (mode == SOUNDING_SW_VHT_TIMER || mode == SOUNDING_HW_VHT_TIMER || mode == SOUNDING_AUTO_VHT_TIMER) { + if (!(entry->beamform_entry_cap & BEAMFORMER_CAP_VHT_SU)) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, + "%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", + __func__); + return false; + } + } + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + entry->is_beamforming_in_progress = false; + PHYDM_DBG(dm, DBG_TXBF, + "%s Return by incorrect beamform_entry_state(%d) <==\n", + __func__, entry->beamform_entry_state); + return false; + } else { + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; + } + + beam_info->beamformee_cur_idx = idx; + } + + /*@2014.12.22 Luke: Need to be checked*/ + /*@GET_TXBF_INFO(adapter)->fTxbfSet(adapter, TXBF_SET_SOUNDING_STATUS, (u8*)&idx);*/ + + if (mode == SOUNDING_SW_HT_TIMER || mode == SOUNDING_HW_HT_TIMER || mode == SOUNDING_AUTO_HT_TIMER) + ret = beamforming_send_ht_ndpa_packet(dm, ra, BW, NORMAL_QUEUE); + else + ret = beamforming_send_vht_ndpa_packet(dm, ra, entry->aid, BW, NORMAL_QUEUE); + + if (ret == false) { + beamforming_leave(dm, ra); + entry->is_beamforming_in_progress = false; + return false; + } + +/*@-------------------------- + * Send BF Report Poll for MU BF + --------------------------*/ +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) + if (beam_info->beamformee_mu_cnt <= 1) + goto out; + + /* @More than 1 MU STA*/ + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + entry = &beam_info->beamformee_entry[i]; + if (!entry->is_mu_sta) + continue; + + if (!is_get_first_bfee) { + is_get_first_bfee = true; + continue; + } + + poll_sta_cnt++; + if (poll_sta_cnt == (beam_info->beamformee_mu_cnt - 1)) /* The last STA*/ + send_sw_vht_bf_report_poll(dm, entry->mac_addr, true); + else + send_sw_vht_bf_report_poll(dm, entry->mac_addr, false); + } +out: +#endif +#endif + return true; +} + +boolean +beamforming_start_fw( + void *dm_void, + u8 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMEE_ENTRY *entry; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + entry = &beam_info->beamformee_entry[idx]; + if (entry->is_used == false) { + PHYDM_DBG(dm, DBG_TXBF, + "Skip Beamforming, no entry for idx =%d\n", idx); + return false; + } + + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + entry->is_sound = true; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_FW_NDPA, (u8 *)&idx); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] End, idx=0x%X\n", __func__, idx); + return true; +} + +void beamforming_check_sounding_success( + void *dm_void, + boolean status) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; + + PHYDM_DBG(dm, DBG_TXBF, "[David]@%s Start!\n", __func__); + + if (status == 1) { + if (entry->log_status_fail_cnt == 21) + beamforming_dym_period(dm, status); + entry->log_status_fail_cnt = 0; + } else if (entry->log_status_fail_cnt <= 20) { + entry->log_status_fail_cnt++; + PHYDM_DBG(dm, DBG_TXBF, "%s log_status_fail_cnt %d\n", __func__, + entry->log_status_fail_cnt); + } + if (entry->log_status_fail_cnt > 20) { + entry->log_status_fail_cnt = 21; + PHYDM_DBG(dm, DBG_TXBF, + "%s log_status_fail_cnt > 20, Stop SOUNDING\n", + __func__); + beamforming_dym_period(dm, status); + } +} + +void phydm_beamforming_end_sw( + void *dm_void, + boolean status) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMEE_ENTRY *entry = &beam_info->beamformee_entry[beam_info->beamformee_cur_idx]; + + if (beam_info->is_mu_sounding) { + PHYDM_DBG(dm, DBG_TXBF, "%s: MU sounding done\n", __func__); + beam_info->is_mu_sounding_in_progress = false; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); + } else { + if (entry->beamform_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSING) { + PHYDM_DBG(dm, DBG_TXBF, "[%s] BeamformStatus %d\n", + __func__, entry->beamform_entry_state); + return; + } + + if (beam_info->tx_bf_data_rate >= ODM_RATEVHTSS3MCS7 && beam_info->tx_bf_data_rate <= ODM_RATEVHTSS3MCS9 && !beam_info->snding3ss) { + PHYDM_DBG(dm, DBG_TXBF, + "[%s] VHT3SS 7,8,9, do not apply V matrix.\n", + __func__); + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); + } else if (status == 1) { + entry->log_status_fail_cnt = 0; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED; + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_STATUS, + (u8 *)&beam_info->beamformee_cur_idx); + } else { + entry->log_status_fail_cnt++; + entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + hal_com_txbf_set(dm, TXBF_SET_TX_PATH_RESET, + (u8 *)&beam_info->beamformee_cur_idx); + PHYDM_DBG(dm, DBG_TXBF, "[%s] log_status_fail_cnt %d\n", + __func__, entry->log_status_fail_cnt); + } + + if (entry->log_status_fail_cnt > 50) { + PHYDM_DBG(dm, DBG_TXBF, + "%s log_status_fail_cnt > 50, Stop SOUNDING\n", + __func__); + entry->is_sound = false; + beamforming_deinit_entry(dm, entry->mac_addr); + + /*@Modified by David - Every action of deleting entry should follow by Notify*/ + phydm_beamforming_notify(dm); + } + + entry->is_beamforming_in_progress = false; + } + PHYDM_DBG(dm, DBG_TXBF, "%s: status=%d\n", __func__, status); +} + +void beamforming_timer_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *dm_void +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *context +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct dm_struct *dm = (struct dm_struct *)dm_void; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *adapter = (void *)context; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->odmpriv; +#endif + boolean ret = false; + struct _RT_BEAMFORMING_INFO *beam_info = &(dm->beamforming_info); + struct _RT_BEAMFORMEE_ENTRY *entry = &(beam_info->beamformee_entry[beam_info->beamformee_cur_idx]); + struct _RT_SOUNDING_INFO *sound_info = &(beam_info->sounding_info); + boolean is_beamforming_in_progress; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (beam_info->is_mu_sounding) + is_beamforming_in_progress = beam_info->is_mu_sounding_in_progress; + else + is_beamforming_in_progress = entry->is_beamforming_in_progress; + + if (is_beamforming_in_progress) { + PHYDM_DBG(dm, DBG_TXBF, + "is_beamforming_in_progress, reset it\n"); + phydm_beamforming_end_sw(dm, 0); + } + + ret = phydm_beamforming_select_beam_entry(dm, beam_info); +#if (SUPPORT_MU_BF == 1) + if (ret && beam_info->beamformee_mu_cnt > 1) + ret = 1; + else + ret = 0; +#endif + if (ret) + ret = beamforming_start_sw(dm, sound_info->sound_idx, sound_info->sound_mode, sound_info->sound_bw); + else + PHYDM_DBG(dm, DBG_TXBF, + "%s, Error value return from BeamformingStart_V2\n", + __func__); + + if (beam_info->beamformee_su_cnt != 0 || beam_info->beamformee_mu_cnt > 1) { + if (sound_info->sound_mode == SOUNDING_SW_VHT_TIMER || sound_info->sound_mode == SOUNDING_SW_HT_TIMER) + odm_set_timer(dm, &beam_info->beamforming_timer, sound_info->sound_period); + else { + u32 val = (sound_info->sound_period << 16) | HAL_TIMER_TXBF; + phydm_set_hw_reg_handler_interface(dm, HW_VAR_HW_REG_TIMER_RESTART, (u8 *)(&val)); + } + } +} + +void beamforming_sw_timer_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct phydm_timer_list *timer +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *function_context +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + beamforming_timer_callback(dm); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + struct dm_struct *dm = (struct dm_struct *)function_context; + void *adapter = dm->adapter; + + if (*dm->is_net_closed == true) + return; + phydm_run_in_thread_cmd(dm, beamforming_timer_callback, adapter); +#endif +} + +void phydm_beamforming_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + +#ifdef BEAMFORMING_VERSION_1 + if (hal_data->beamforming_version != BEAMFORMING_VERSION_1) { + return; + } +#endif +#endif + + beam_oid_info->sound_oid_mode = SOUNDING_STOP_OID_TIMER; + PHYDM_DBG(dm, DBG_TXBF, "%s mode (%d)\n", __func__, + beam_oid_info->sound_oid_mode); + + beam_info->beamformee_su_cnt = 0; + beam_info->beamformer_su_cnt = 0; + beam_info->beamformee_mu_cnt = 0; + beam_info->beamformer_mu_cnt = 0; + beam_info->beamformee_mu_reg_maping = 0; + beam_info->mu_ap_index = 0; + beam_info->is_mu_sounding = false; + beam_info->first_mu_bfee_index = 0xFF; + beam_info->apply_v_matrix = true; + beam_info->snding3ss = false; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + beam_info->source_adapter = dm->adapter; +#endif + hal_com_txbf_beamform_init(dm); +} + +boolean +phydm_acting_determine( + void *dm_void, + enum phydm_acting_type type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = false; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->beamforming_info.source_adapter; +#else + struct _ADAPTER *adapter = dm->adapter; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (type == phydm_acting_as_ap) + ret = ACTING_AS_AP(adapter); + else if (type == phydm_acting_as_ibss) + ret = ACTING_AS_IBSS(((PADAPTER)(adapter))); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + if (type == phydm_acting_as_ap) + ret = check_fwstate(pmlmepriv, WIFI_AP_STATE); + else if (type == phydm_acting_as_ibss) + ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); +#endif + + return ret; +} + +void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 bfer_bfee_idx = 0xff; + + if (beamforming_init_entry(dm, sta_idx, &bfer_bfee_idx, my_mac_addr)) + hal_com_txbf_set(dm, TXBF_SET_SOUNDING_ENTER, (u8 *)&bfer_bfee_idx); + + PHYDM_DBG(dm, DBG_TXBF, "[%s] End!\n", __func__); +} + +void beamforming_leave( + void *dm_void, + u8 *RA) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (RA != NULL) { + beamforming_deinit_entry(dm, RA); + phydm_beamforming_notify(dm); + } + + PHYDM_DBG(dm, DBG_TXBF, "[%s] End!!\n", __func__); +} + +enum beamforming_cap +phydm_beamforming_get_beam_cap( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info) +{ + u8 i; + boolean is_self_beamformer = false; + boolean is_self_beamformee = false; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry; + struct _RT_BEAMFORMER_ENTRY beamformer_entry; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__); + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + beamformee_entry = beam_info->beamformee_entry[i]; + + if (beamformee_entry.is_used) { + is_self_beamformer = true; + PHYDM_DBG(dm, DBG_TXBF, + "[%s] BFee entry %d is_used=true\n", __func__, + i); + break; + } + } + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + beamformer_entry = beam_info->beamformer_entry[i]; + + if (beamformer_entry.is_used) { + is_self_beamformee = true; + PHYDM_DBG(dm, DBG_TXBF, + "[%s]: BFer entry %d is_used=true\n", + __func__, i); + break; + } + } + + if (is_self_beamformer) + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMER_CAP); + if (is_self_beamformee) + beamform_cap = (enum beamforming_cap)(beamform_cap | BEAMFORMEE_CAP); + + return beamform_cap; +} + +boolean +beamforming_control_v1( + void *dm_void, + u8 *RA, + u8 AID, + u8 mode, + enum channel_width BW, + u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret = true; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + PHYDM_DBG(dm, DBG_TXBF, "AID (%d), mode (%d), BW (%d)\n", AID, mode, + BW); + + switch (mode) { + case 0: + ret = beamforming_start_v1(dm, RA, 0, BW, rate); + break; + case 1: + ret = beamforming_start_v1(dm, RA, 1, BW, rate); + break; + case 2: + phydm_beamforming_ndpa_rate(dm, BW, rate); + ret = beamforming_send_vht_ndpa_packet(dm, RA, AID, BW, NORMAL_QUEUE); + break; + case 3: + phydm_beamforming_ndpa_rate(dm, BW, rate); + ret = beamforming_send_ht_ndpa_packet(dm, RA, BW, NORMAL_QUEUE); + break; + } + return ret; +} + +/*Only OID uses this function*/ +boolean +phydm_beamforming_control_v2( + void *dm_void, + u8 idx, + u8 mode, + enum channel_width BW, + u16 period) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + struct _RT_BEAMFORMING_OID_INFO *beam_oid_info = &beam_info->beamforming_oid_info; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + PHYDM_DBG(dm, DBG_TXBF, "idx (%d), mode (%d), BW (%d), period (%d)\n", + idx, mode, BW, period); + + beam_oid_info->sound_oid_idx = idx; + beam_oid_info->sound_oid_mode = (enum sounding_mode)mode; + beam_oid_info->sound_oid_bw = BW; + beam_oid_info->sound_oid_period = period; + + phydm_beamforming_notify(dm); + + return true; +} + +void phydm_beamforming_watchdog( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + + PHYDM_DBG(dm, DBG_TXBF, "%s Start!\n", __func__); + + if (beam_info->beamformee_su_cnt == 0) + return; + + beamforming_dym_period(dm, 0); +} +enum beamforming_cap +phydm_get_beamform_cap( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct bf_cmn_info *bf_info = NULL; + struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info; + void *adapter = dm->adapter; + enum beamforming_cap beamform_cap = BEAMFORMING_CAP_NONE; + u8 macid; + u8 ht_curbeamformcap = 0; + u16 vht_curbeamformcap = 0; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO p_MgntInfo = &(((PADAPTER)(adapter))->MgntInfo); + PRT_VERY_HIGH_THROUGHPUT p_vht_info = GET_VHT_INFO(p_MgntInfo); + PRT_HIGH_THROUGHPUT p_ht_info = GET_HT_INFO(p_MgntInfo); + + ht_curbeamformcap = p_ht_info->HtCurBeamform; + vht_curbeamformcap = p_vht_info->VhtCurBeamform; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[%s] WIN ht_curcap = %d ; vht_curcap = %d\n", __func__, + ht_curbeamformcap, vht_curbeamformcap); + + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP)); + + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP)); + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP)); + + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP)); + + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP)); +#endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + sta = dm->phydm_sta_info[macid]; + + if (!is_sta_active(sta)) + continue; + + bf_info = &sta->bf_info; + vht_curbeamformcap = bf_info->vht_beamform_cap; + ht_curbeamformcap = bf_info->ht_beamform_cap; + + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) /*We are Beamformee because the STA is Beamformer*/ + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_HT_EXPLICIT | BEAMFORMEE_CAP)); + + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(ht_curbeamformcap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP)); + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP)); + + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP)); + + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(vht_curbeamformcap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) + beamform_cap = (enum beamforming_cap)(beamform_cap | (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP)); +#endif + } + PHYDM_DBG(dm, DBG_ANT_DIV, "[%s] CE ht_curcap = %d ; vht_curcap = %d\n", + __func__, ht_curbeamformcap, vht_curbeamformcap); + +#endif + + return beamform_cap; +} + +#endif diff --git a/hal/phydm/phydm_beamforming.h b/hal/phydm/phydm_beamforming.h new file mode 100644 index 0000000..efb53e3 --- /dev/null +++ b/hal/phydm/phydm_beamforming.h @@ -0,0 +1,363 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __INC_PHYDM_BEAMFORMING_H +#define __INC_PHYDM_BEAMFORMING_H + +/*@Beamforming Related*/ +#include "txbf/halcomtxbf.h" +#include "txbf/haltxbfjaguar.h" +#include "txbf/haltxbf8192e.h" +#include "txbf/haltxbf8814a.h" +#include "txbf/haltxbf8822b.h" +#include "txbf/haltxbfinterface.h" + +#ifdef PHYDM_BEAMFORMING_SUPPORT + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) +#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) + +#endif + +#define MAX_BEAMFORMEE_SU 2 +#define MAX_BEAMFORMER_SU 2 +#if ((RTL8822B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1)) +#define MAX_BEAMFORMEE_MU 6 +#define MAX_BEAMFORMER_MU 1 +#else +#define MAX_BEAMFORMEE_MU 0 +#define MAX_BEAMFORMER_MU 0 +#endif + +#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) +#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*@for different naming between WIN and CE*/ +#define BEACON_QUEUE BCN_QUEUE_INX +#define NORMAL_QUEUE MGT_QUEUE_INX +#define RT_DISABLE_FUNC RTW_DISABLE_FUNC +#define RT_ENABLE_FUNC RTW_ENABLE_FUNC +#endif + +enum beamforming_entry_state { + BEAMFORMING_ENTRY_STATE_UNINITIALIZE, + BEAMFORMING_ENTRY_STATE_INITIALIZEING, + BEAMFORMING_ENTRY_STATE_INITIALIZED, + BEAMFORMING_ENTRY_STATE_PROGRESSING, + BEAMFORMING_ENTRY_STATE_PROGRESSED +}; + +enum beamforming_notify_state { + BEAMFORMING_NOTIFY_NONE, + BEAMFORMING_NOTIFY_ADD, + BEAMFORMING_NOTIFY_DELETE, + BEAMFORMEE_NOTIFY_ADD_SU, + BEAMFORMEE_NOTIFY_DELETE_SU, + BEAMFORMEE_NOTIFY_ADD_MU, + BEAMFORMEE_NOTIFY_DELETE_MU, + BEAMFORMING_NOTIFY_RESET +}; + +enum beamforming_cap { + BEAMFORMING_CAP_NONE = 0x0, + BEAMFORMER_CAP_HT_EXPLICIT = BIT(1), + BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2), + BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP = BIT(9), + BEAMFORMEE_CAP = BIT(10), +}; + +enum sounding_mode { + SOUNDING_SW_VHT_TIMER = 0x0, + SOUNDING_SW_HT_TIMER = 0x1, + sounding_stop_all_timer = 0x2, + SOUNDING_HW_VHT_TIMER = 0x3, + SOUNDING_HW_HT_TIMER = 0x4, + SOUNDING_STOP_OID_TIMER = 0x5, + SOUNDING_AUTO_VHT_TIMER = 0x6, + SOUNDING_AUTO_HT_TIMER = 0x7, + SOUNDING_FW_VHT_TIMER = 0x8, + SOUNDING_FW_HT_TIMER = 0x9, +}; + +struct _RT_BEAMFORM_STAINFO { + u8 *ra; + u16 aid; + u16 mac_id; + u8 my_mac_addr[6]; + /*WIRELESS_MODE wireless_mode;*/ + enum channel_width bw; + enum beamforming_cap beamform_cap; + u8 ht_beamform_cap; + u16 vht_beamform_cap; + u8 cur_beamform; + u16 cur_beamform_vht; +}; + +struct _RT_BEAMFORMEE_ENTRY { + boolean is_used; + boolean is_txbf; + boolean is_sound; + u16 aid; /*Used to construct AID field of NDPA packet.*/ + u16 mac_id; /*Used to Set Reg42C in IBSS mode. */ + u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u8 g_id; /*Used to fill Tx DESC*/ + u8 my_mac_addr[6]; + u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ + enum channel_width sound_bw; /*Sounding band_width*/ + u16 sound_period; + enum beamforming_cap beamform_entry_cap; + enum beamforming_entry_state beamform_entry_state; + boolean is_beamforming_in_progress; + /*@u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/ + /*@u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ + /*@u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ + u16 log_status_fail_cnt : 5; /* @0~21 */ + u16 default_csi_cnt : 5; /* @0~21 */ + u8 csi_matrix[327]; + u16 csi_matrix_len; + u8 num_of_sounding_dim; + u8 comp_steering_num_of_bfer; + u8 su_reg_index; + /*@For MU-MIMO*/ + boolean is_mu_sta; + u8 mu_reg_index; + u8 gid_valid[8]; + u8 user_position[16]; +}; + +struct _RT_BEAMFORMER_ENTRY { + boolean is_used; + /*P_AID of BFer entry is probably not used*/ + u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u8 g_id; + u8 my_mac_addr[6]; + u8 mac_addr[6]; + enum beamforming_cap beamform_entry_cap; + u8 num_of_sounding_dim; + u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/ + u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/ + u8 log_seq; /*@Modified by Jeffery @2014-10-29*/ + u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/ + u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/ + u8 su_reg_index; + /*@For MU-MIMO*/ + boolean is_mu_ap; + u8 gid_valid[8]; + u8 user_position[16]; + u16 aid; +}; + +struct _RT_SOUNDING_INFO { + u8 sound_idx; + enum channel_width sound_bw; + enum sounding_mode sound_mode; + u16 sound_period; +}; + +struct _RT_BEAMFORMING_OID_INFO { + u8 sound_oid_idx; + enum channel_width sound_oid_bw; + enum sounding_mode sound_oid_mode; + u16 sound_oid_period; +}; + +struct _RT_BEAMFORMING_INFO { + enum beamforming_cap beamform_cap; + struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM]; + struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM]; + struct _RT_BEAMFORM_STAINFO beamform_sta_info; + u8 beamformee_cur_idx; + struct phydm_timer_list beamforming_timer; + struct phydm_timer_list mu_timer; + struct _RT_SOUNDING_INFO sounding_info; + struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info; + struct _HAL_TXBF_INFO txbf_info; + u8 sounding_sequence; + u8 beamformee_su_cnt; + u8 beamformer_su_cnt; + u32 beamformee_su_reg_maping; + u32 beamformer_su_reg_maping; + /*@For MU-MINO*/ + u8 beamformee_mu_cnt; + u8 beamformer_mu_cnt; + u32 beamformee_mu_reg_maping; + u8 mu_ap_index; + boolean is_mu_sounding; + u8 first_mu_bfee_index; + boolean is_mu_sounding_in_progress; + boolean dbg_disable_mu_tx; + boolean apply_v_matrix; + boolean snding3ss; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *source_adapter; +#endif + /* @Control register */ + u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */ + u8 tx_bf_data_rate; + u8 last_usb_hub; +}; + +void phydm_get_txbf_device_num( + void *dm_void, + u8 macid); + +struct _RT_NDPA_STA_INFO { + u16 aid : 12; + u16 feedback_type : 1; + u16 nc_index : 3; +}; + +enum phydm_acting_type { + phydm_acting_as_ibss = 0, + phydm_acting_as_ap = 1 +}; + +enum beamforming_cap +phydm_beamforming_get_entry_beam_cap_by_mac_id( + void *dm_void, + u8 mac_id); + +struct _RT_BEAMFORMEE_ENTRY * +phydm_beamforming_get_bfee_entry_by_addr( + void *dm_void, + u8 *RA, + u8 *idx); + +struct _RT_BEAMFORMER_ENTRY * +phydm_beamforming_get_bfer_entry_by_addr( + void *dm_void, + u8 *TA, + u8 *idx); + +void phydm_beamforming_notify( + void *dm_void); + +boolean +phydm_acting_determine( + void *dm_void, + enum phydm_acting_type type); + +void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr); + +void beamforming_leave( + void *dm_void, + u8 *RA); + +boolean +beamforming_start_fw( + void *dm_void, + u8 idx); + +void beamforming_check_sounding_success( + void *dm_void, + boolean status); + +void phydm_beamforming_end_sw( + void *dm_void, + boolean status); + +void beamforming_timer_callback( + void *dm_void); + +void phydm_beamforming_init( + void *dm_void); + +enum beamforming_cap +phydm_beamforming_get_beam_cap( + void *dm_void, + struct _RT_BEAMFORMING_INFO *beam_info); + +enum beamforming_cap +phydm_get_beamform_cap( + void *dm_void); + +boolean +beamforming_control_v1( + void *dm_void, + u8 *RA, + u8 AID, + u8 mode, + enum channel_width BW, + u8 rate); + +boolean +phydm_beamforming_control_v2( + void *dm_void, + u8 idx, + u8 mode, + enum channel_width BW, + u16 period); + +void phydm_beamforming_watchdog( + void *dm_void); + +void beamforming_sw_timer_callback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct phydm_timer_list *timer +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + void *function_context +#endif + ); + +boolean +beamforming_send_ht_ndpa_packet( + void *dm_void, + u8 *RA, + enum channel_width BW, + u8 q_idx); + +boolean +beamforming_send_vht_ndpa_packet( + void *dm_void, + u8 *RA, + u16 AID, + enum channel_width BW, + u8 q_idx); + +#else +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) +#define beamforming_gid_paid(adapter, tcb) +#define phydm_acting_determine(dm, type) false +#define beamforming_enter(dm, sta_idx, my_mac_addr) +#define beamforming_leave(dm, RA) +#define beamforming_end_fw(dm) +#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true +#define beamforming_control_v2(dm, idx, mode, BW, period) true +#define phydm_beamforming_end_sw(dm, _status) +#define beamforming_timer_callback(dm) +#define phydm_beamforming_init(dm) +#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false +#define beamforming_watchdog(dm) +#define phydm_beamforming_watchdog(dm) +#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/ +#endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/ +#endif diff --git a/hal/phydm/phydm_cck_pd.c b/hal/phydm/phydm_cck_pd.c new file mode 100644 index 0000000..24e37dc --- /dev/null +++ b/hal/phydm/phydm_cck_pd.c @@ -0,0 +1,1918 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_SUPPORT_CCKPD +#ifdef PHYDM_COMPILE_CCKPD_TYPE1 +void phydm_write_cck_pd_type1(void *dm_void, u8 cca_th) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] cck_cca_th=((0x%x))\n", + __func__, cca_th); + + odm_write_1byte(dm, R_0xa0a, cca_th); + cckpd_t->cur_cck_cca_thres = cca_th; +} + +void phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 pd_th = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + if (cckpd_t->cck_pd_lv == lv) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + if (lv == CCK_PD_LV_4) + pd_th = 0xed; + else if (lv == CCK_PD_LV_3) + pd_th = 0xdd; + else if (lv == CCK_PD_LV_2) + pd_th = 0xcd; + else if (lv == CCK_PD_LV_1) + pd_th = 0x83; + else if (lv == CCK_PD_LV_0) + pd_th = 0x40; + + phydm_write_cck_pd_type1(dm, pd_th); +} + +void phydm_cckpd_type1(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv = CCK_PD_LV_INIT; + boolean is_update = true; + + if (dm->is_linked) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->rssi_min > 60) { + lv = CCK_PD_LV_3; + } else if (dm->rssi_min > 35) { + lv = CCK_PD_LV_2; + } else if (dm->rssi_min > 20) { + if (cckpd_t->cck_fa_ma > 500) + lv = CCK_PD_LV_2; + else if (cckpd_t->cck_fa_ma < 250) + lv = CCK_PD_LV_1; + else + is_update = false; + } else { /*RSSI < 20*/ + lv = CCK_PD_LV_1; + } + #else /*ODM_AP*/ + if (dig_t->cur_ig_value > 0x32) + lv = CCK_PD_LV_4; + else if (dig_t->cur_ig_value > 0x2a) + lv = CCK_PD_LV_3; + else if (dig_t->cur_ig_value > 0x24) + lv = CCK_PD_LV_2; + else + lv = CCK_PD_LV_1; + #endif + } else { + if (cckpd_t->cck_fa_ma > 1000) + lv = CCK_PD_LV_1; + else if (cckpd_t->cck_fa_ma < 500) + lv = CCK_PD_LV_0; + else + is_update = false; + } + + /*[Abnormal case] =================================================*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + /*@HP 22B LPS power consumption issue & [PCIE-1596]*/ + if (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n"); + } else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) && + cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) { + lv = CCK_PD_LV_1; + cckpd_t->cck_pd_lv = lv; + phydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/ + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case2\n"); + } + #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #ifdef MCR_WIRELESS_EXTEND + lv = CCK_PD_LV_2; + cckpd_t->cck_pd_lv = lv; + phydm_write_cck_pd_type1(dm, 0x43); + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case3\n"); + #endif + #endif + /*=================================================================*/ + + if (is_update) + phydm_set_cckpd_lv_type1(dm, lv); + + PHYDM_DBG(dm, DBG_CCKPD, "is_linked=%d, lv=%d, pd_th=0x%x\n\n", + dm->is_linked, cckpd_t->cck_pd_lv, + cckpd_t->cur_cck_cca_thres); +} +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/ + +#ifdef PHYDM_COMPILE_CCKPD_TYPE2 +void phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] pd_th=0x%x, cs_ratio=0x%x\n", + __func__, cca_th, cca_th_aaa); + + odm_set_bb_reg(dm, R_0xa08, 0x3f0000, cca_th); + odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa); + cckpd_t->cur_cck_cca_thres = cca_th; + cckpd_t->cck_cca_th_aaa = cca_th_aaa; +} + +void phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0; + u8 cck_n_rx = 1; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*@r_mrx & r_cca_mrc*/ + cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) && + odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1; + + if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + if (lv == CCK_PD_LV_4) { + cs_ratio = cckpd_t->aaa_default + 8; + cs_2r_offset = 5; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_3) { + cs_ratio = cckpd_t->aaa_default + 6; + cs_2r_offset = 4; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_2) { + cs_ratio = cckpd_t->aaa_default + 4; + cs_2r_offset = 3; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_1) { + cs_ratio = cckpd_t->aaa_default + 2; + cs_2r_offset = 1; + pd_th = 0x7; + } else if (lv == CCK_PD_LV_0) { + cs_ratio = cckpd_t->aaa_default; + cs_2r_offset = 0; + pd_th = 0x3; + } + + if (cckpd_t->cck_n_rx == 2) { + if (cs_ratio >= cs_2r_offset) + cs_ratio = cs_ratio - cs_2r_offset; + else + cs_ratio = 0; + } + phydm_write_cck_pd_type2(dm, pd_th, cs_ratio); +} + +#if 0 +void phydm_set_cckpd_lv_type2_bcn(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0; + u8 cck_n_rx = 1; + u8 cs_ratio_pre = 0; + u8 bcn_cnt = dm->phy_dbg_info.beacon_cnt_in_period; //BCN CNT + u8 ofst = 0; + u8 ofst_direc = 0; //0:+, 1:- + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*@r_mrx & r_cca_mrc*/ + cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) && + odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1; + cs_ratio_pre = (u8)((odm_get_bb_reg(dm, R_0xaa8, 0x1f0000))); + PHYDM_DBG(dm, DBG_CCKPD, "BCN: %d, pre CS ratio: 0x%x\n", bcn_cnt, + cs_ratio_pre); + + if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx && + (bcn_cnt >= 10 && bcn_cnt < 14)) { + PHYDM_DBG(dm, DBG_CCKPD, "BCN ok, stay lv=%d, cs ratio=0x%x\n", + lv, cs_ratio_pre); + return; + } + + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + if (lv == CCK_PD_LV_4) { + cs_ratio = cckpd_t->aaa_default + 8; + cs_2r_offset = 5; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_3) { + cs_ratio = cckpd_t->aaa_default + 6; + cs_2r_offset = 4; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_2) { + cs_ratio = cckpd_t->aaa_default + 4; + cs_2r_offset = 3; + pd_th = 0xd; + } else if (lv == CCK_PD_LV_1) { + cs_ratio = cckpd_t->aaa_default + 2; + cs_2r_offset = 1; + pd_th = 0x7; + } else if (lv == CCK_PD_LV_0) { + cs_ratio = cckpd_t->aaa_default; + cs_2r_offset = 0; + pd_th = 0x3; + } + + if (cckpd_t->cck_n_rx == 2) { + if (cs_ratio >= cs_2r_offset) + cs_ratio = cs_ratio - cs_2r_offset; + else + cs_ratio = 0; + } + + if (bcn_cnt >= 18) { + ofst_direc = 0; + ofst = 0x2; + } else if (bcn_cnt >= 14) { + ofst_direc = 0; + ofst = 0x1; + } else if (bcn_cnt >= 10) { + ofst_direc = 0; + ofst = 0x0; + } else if (bcn_cnt >= 5) { + ofst_direc = 1; + ofst = 0x3; + } else { + ofst_direc = 1; + ofst = 0x4; + } + PHYDM_DBG(dm, DBG_CCKPD, "bcn:(%d), ofst:(%s%d)\n", bcn_cnt, + ((ofst_direc) ? "-" : "+"), ofst); + + if (ofst_direc == 0) + cs_ratio = cs_ratio + ofst; + else + cs_ratio = cs_ratio - ofst; + + if (cs_ratio == cs_ratio_pre) { + PHYDM_DBG(dm, DBG_CCKPD, "Same cs ratio, lv=%d cs_ratio=0x%x\n", + lv, cs_ratio); + return; + } + phydm_write_cck_pd_type2(dm, pd_th, cs_ratio); +} +#endif + +void phydm_cckpd_type2(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv = CCK_PD_LV_INIT; + u8 igi = dig_t->cur_ig_value; + u8 rssi_min = dm->rssi_min; + boolean is_update = true; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (dm->is_linked) { + if (igi > 0x38 && rssi_min > 32) { + lv = CCK_PD_LV_4; + } else if (igi > 0x2a && rssi_min > 32) { + lv = CCK_PD_LV_3; + } else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) { + lv = CCK_PD_LV_2; + } else if (igi <= 0x24 || rssi_min < 22) { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + } else { + is_update = false; + } + } else { + is_update = false; + } + } else { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + } else { + is_update = false; + } + } + + /*[Abnormal case] =================================================*/ + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + /*@21C Miracast lag issue & [PCIE-3298]*/ + if (dm->support_ic_type & ODM_RTL8821C && rssi_min > 60) { + lv = CCK_PD_LV_4; + cckpd_t->cck_pd_lv = lv; + phydm_write_cck_pd_type2(dm, 0x1d, (cckpd_t->aaa_default + 8)); + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n"); + } + #endif + /*=================================================================*/ + + if (is_update) { + phydm_set_cckpd_lv_type2(dm, lv); + } + + PHYDM_DBG(dm, DBG_CCKPD, + "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\n\n", + dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx, + cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres); +} +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/ + +#ifdef PHYDM_COMPILE_CCKPD_TYPE3 +void phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio, + enum cckpd_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + PHYDM_DBG(dm, DBG_CCKPD, + "[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\n", __func__, + mode, pd_th, cs_ratio); + + switch (mode) { + case CCK_BW20_1R: /*RFBW20_1R*/ + { + cckpd_t->cur_cck_pd_20m_1r = pd_th; + cckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio; + odm_set_bb_reg(dm, R_0xac8, 0xff, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio); + } break; + case CCK_BW20_2R: /*RFBW20_2R*/ + { + cckpd_t->cur_cck_pd_20m_2r = pd_th; + cckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio; + odm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio); + } break; + case CCK_BW40_1R: /*RFBW40_1R*/ + { + cckpd_t->cur_cck_pd_40m_1r = pd_th; + cckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio; + odm_set_bb_reg(dm, R_0xacc, 0xff, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio); + } break; + case CCK_BW40_2R: /*RFBW40_2R*/ + { + cckpd_t->cur_cck_pd_40m_2r = pd_th; + cckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio; + odm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th); + odm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio); + } break; + + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } +} + +void phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_mode cck_mode = CCK_BW20_2R; + enum channel_width cck_bw = CHANNEL_WIDTH_20; + u8 cck_n_rx = 1; + u8 pd_th; + u8 cs_ratio; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*[Check Nrx]*/ + cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1; + + /*[Check BW]*/ + if (odm_get_bb_reg(dm, R_0x800, BIT(0))) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_20; + + /*[Check LV]*/ + if (cckpd_t->cck_pd_lv == lv && + cckpd_t->cck_n_rx == cck_n_rx && + cckpd_t->cck_bw == cck_bw) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_bw = cck_bw; + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + if (cck_n_rx == 2) { + if (cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cck_pd_20m_2r; + cs_ratio = cckpd_t->cck_cs_ratio_20m_2r; + cck_mode = CCK_BW20_2R; + } else { + pd_th = cckpd_t->cck_pd_40m_2r; + cs_ratio = cckpd_t->cck_cs_ratio_40m_2r; + cck_mode = CCK_BW40_2R; + } + } else { + if (cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cck_pd_20m_1r; + cs_ratio = cckpd_t->cck_cs_ratio_20m_1r; + cck_mode = CCK_BW20_1R; + } else { + pd_th = cckpd_t->cck_pd_40m_1r; + cs_ratio = cckpd_t->cck_cs_ratio_40m_1r; + cck_mode = CCK_BW40_1R; + } + } + + if (lv == CCK_PD_LV_4) { + if (cck_n_rx == 2) { + pd_th += 4; + cs_ratio += 2; + } else { + pd_th += 4; + cs_ratio += 3; + } + } else if (lv == CCK_PD_LV_3) { + if (cck_n_rx == 2) { + pd_th += 3; + cs_ratio += 1; + } else { + pd_th += 3; + cs_ratio += 2; + } + } else if (lv == CCK_PD_LV_2) { + pd_th += 2; + cs_ratio += 1; + } else if (lv == CCK_PD_LV_1) { + pd_th += 1; + cs_ratio += 1; + } + + phydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode); +} + +void phydm_cckpd_type3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv = CCK_PD_LV_INIT; + u8 igi = dm->dm_dig_table.cur_ig_value; + boolean is_update = true; + u8 pd_th = 0; + u8 cs_ratio = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (dm->is_linked) { + if (igi > 0x38 && dm->rssi_min > 32) { + lv = CCK_PD_LV_4; + } else if ((igi > 0x2a) && (dm->rssi_min > 32)) { + lv = CCK_PD_LV_3; + } else if ((igi > 0x24) || + (dm->rssi_min > 24 && dm->rssi_min <= 30)) { + lv = CCK_PD_LV_2; + } else if ((igi <= 0x24) || (dm->rssi_min < 22)) { + if (cckpd_t->cck_fa_ma > 1000) + lv = CCK_PD_LV_1; + else if (cckpd_t->cck_fa_ma < 500) + lv = CCK_PD_LV_0; + else + is_update = false; + } + if (igi >= 0x20 && dm->rssi_min >= 27) { + //printf(">>>>>TUYA CCK FA CNT = %d, RSSI = %d, IGI =%d \n", cckpd_t->cck_fa_ma, dm->rssi_min, igi); + is_update = false; + odm_set_bb_reg(dm, R_0xa08, BIT(21) | BIT(20), 0x2); + //odm_set_bb_reg(dm, R_0xac8, 0xff, 0x18); + } + else { + //printf("CCK FA CNT = %d, RSSI = %d, IGI =%d \n", cckpd_t->cck_fa_ma, dm->rssi_min, igi); + odm_set_bb_reg(dm, R_0xa08, BIT(21) | BIT(20), cckpd_t->cck_din_shift_opt); + //odm_set_bb_reg(dm, R_0xac8, 0xff, cckpd_t->cck_pd_20m_1r); + } + } else { + if (cckpd_t->cck_fa_ma > 1000) + lv = CCK_PD_LV_1; + else if (cckpd_t->cck_fa_ma < 500) + lv = CCK_PD_LV_0; + else + is_update = false; + } + + if (is_update) + phydm_set_cckpd_lv_type3(dm, lv); + + if (cckpd_t->cck_n_rx == 2) { + if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cur_cck_pd_20m_2r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r; + } else { + pd_th = cckpd_t->cur_cck_pd_40m_2r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r; + } + } else { + if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) { + pd_th = cckpd_t->cur_cck_pd_20m_1r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r; + } else { + pd_th = cckpd_t->cur_cck_pd_40m_1r; + cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r; + } + } + PHYDM_DBG(dm, DBG_CCKPD, + "[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\n\n", + cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked, + cckpd_t->cck_pd_lv, cs_ratio, pd_th); +} + +void phydm_cck_pd_init_type3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 reg_tmp = 0; + + /*Get Default value*/ + cckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff); + cckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00); + cckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff); + cckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00); + cckpd_t->cck_din_shift_opt = (u8)odm_get_bb_reg(dm, R_0xa08, BIT(21) | BIT(20)); + + reg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD); + cckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f); + cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5); + cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20); + cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25); +} +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/ + +#ifdef PHYDM_COMPILE_CCKPD_TYPE4 +void phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv, + enum cckpd_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 val = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n"); + switch (mode) { + case CCK_BW20_1R: /*RFBW20_1R*/ + { + val = cckpd_t->cckpd_jgr3[0][0][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff, val); + val = cckpd_t->cckpd_jgr3[0][0][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x1f, val); + } break; + case CCK_BW40_1R: /*RFBW40_1R*/ + { + val = cckpd_t->cckpd_jgr3[1][0][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff, val); + val = cckpd_t->cckpd_jgr3[1][0][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val); + } break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case CCK_BW20_2R: /*RFBW20_2R*/ + { + val = cckpd_t->cckpd_jgr3[0][1][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff00, val); + val = cckpd_t->cckpd_jgr3[0][1][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val); + } break; + case CCK_BW40_2R: /*RFBW40_2R*/ + { + val = cckpd_t->cckpd_jgr3[1][1][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff00, val); + val = cckpd_t->cckpd_jgr3[1][1][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val); + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case CCK_BW20_3R: /*RFBW20_3R*/ + { + val = cckpd_t->cckpd_jgr3[0][2][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val); + val = cckpd_t->cckpd_jgr3[0][2][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val); + } break; + case CCK_BW40_3R: /*RFBW40_3R*/ + { + val = cckpd_t->cckpd_jgr3[1][2][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff0000, val); + val = cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x3; + odm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val); + val = (cckpd_t->cckpd_jgr3[1][2][1][lv] & 0x1c) >> 2; + odm_set_bb_reg(dm, R_0x1ad4, 0x7, val); + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case CCK_BW20_4R: /*RFBW20_4R*/ + { + val = cckpd_t->cckpd_jgr3[0][3][0][lv]; + odm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val); + val = cckpd_t->cckpd_jgr3[0][3][1][lv]; + odm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val); + } break; + case CCK_BW40_4R: /*RFBW40_4R*/ + { + val = cckpd_t->cckpd_jgr3[1][3][0][lv]; + odm_set_bb_reg(dm, R_0x1acc, 0xff000000, val); + val = cckpd_t->cckpd_jgr3[1][3][1][lv]; + odm_set_bb_reg(dm, R_0x1ad4, 0xf8, val); + } break; + #endif + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } +} + +void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_mode cck_mode = CCK_BW20_2R; + enum channel_width cck_bw = CHANNEL_WIDTH_20; + u8 cck_n_rx = 0; + u32 val = 0; + /*u32 val_dbg = 0;*/ + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*[Check Nrx]*/ + cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1; + + /*[Check BW]*/ + val = odm_get_bb_reg(dm, R_0x9b0, 0xc); + if (val == 0) + cck_bw = CHANNEL_WIDTH_20; + else if (val == 1) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_80; + + /*[Check LV]*/ + if (cckpd_t->cck_pd_lv == lv && + cckpd_t->cck_n_rx == cck_n_rx && + cckpd_t->cck_bw == cck_bw) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + + cckpd_t->cck_bw = cck_bw; + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + switch (cck_n_rx) { + case 1: /*1R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_1R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_1R; + } break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: /*2R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_2R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_2R; + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: /*3R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_3R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_3R; + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: /*4R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_4R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_4R; + } break; + #endif + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } + phydm_write_cck_pd_type4(dm, lv, cck_mode); +} + +void phydm_read_cckpd_para_type4(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 bw = 0; /*r_RX_RF_BW*/ + u8 n_rx = 0; + u8 curr_cck_pd_t[2][4][2]; + u32 reg0 = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u32 reg3 = 0; + + if (!(dm->debug_components & DBG_CCKPD)) + return; + + bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc); + n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1; + + reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD); + reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD); + reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD); + reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD); + curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff); + curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff); + curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f); + curr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20); + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8); + curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8); + curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5); + curr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25); + } + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) { + curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16); + curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16); + curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10); + curr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) | + (u8)((reg3 & 0x00000007) << 2); + } + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24); + curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24); + curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15); + curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3); + } + #endif + + PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx); + PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=0x%x, PD th=0x%x\n", + cckpd_t->cck_pd_lv, + curr_cck_pd_t[bw][n_rx - 1][1], + curr_cck_pd_t[bw][n_rx - 1][0]); +} + +void phydm_cckpd_type4(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 igi = dm->dm_dig_table.cur_ig_value; + enum cckpd_lv lv = 0; + boolean is_update = true; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (dm->is_linked) { + PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n"); + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->rssi_min > 40) { + lv = CCK_PD_LV_4; + PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n"); + } else if (dm->rssi_min > 32) { + lv = CCK_PD_LV_3; + PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n"); + } else if (dm->rssi_min > 24) { + lv = CCK_PD_LV_2; + PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n"); + } else { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n"); + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n"); + } else { + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n"); + } + } + #else /*ODM_AP*/ + if (igi > 0x38 && dm->rssi_min > 32) { + lv = CCK_PD_LV_4; + PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n"); + } else if (igi > 0x2a && dm->rssi_min > 32) { + lv = CCK_PD_LV_3; + PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n"); + } else if (igi > 0x24 || dm->rssi_min > 24) { + lv = CCK_PD_LV_2; + PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n"); + } else { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n"); + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n"); + } else { + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n"); + } + } + #endif + } else { + PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n"); + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n"); + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n"); + } else { + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n"); + } + } + + if (is_update) { + phydm_set_cck_pd_lv_type4(dm, lv); + + PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n", + cckpd_t->cckpd_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][1][lv], + cckpd_t->cckpd_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][0][lv]); + } + phydm_read_cckpd_para_type4(dm); +} + +void phydm_cck_pd_init_type4(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 reg0 = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u32 reg3 = 0; + u8 pw_step = 0; + u8 cs_step = 0; + u8 cck_bw = 0; /*r_RX_RF_BW*/ + u8 cck_n_rx = 0; + u8 val = 0; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__); + + #if 0 + /*@ + *cckpd_t[0][0][0][0] = 1ac8[7:0] r_PD_lim_RFBW20_1R + *cckpd_t[0][1][0][0] = 1ac8[15:8] r_PD_lim_RFBW20_2R + *cckpd_t[0][2][0][0] = 1ac8[23:16] r_PD_lim_RFBW20_3R + *cckpd_t[0][3][0][0] = 1ac8[31:24] r_PD_lim_RFBW20_4R + *cckpd_t[1][0][0][0] = 1acc[7:0] r_PD_lim_RFBW40_1R + *cckpd_t[1][1][0][0] = 1acc[15:8] r_PD_lim_RFBW40_2R + *cckpd_t[1][2][0][0] = 1acc[23:16] r_PD_lim_RFBW40_3R + *cckpd_t[1][3][0][0] = 1acc[31:24] r_PD_lim_RFBW40_4R + * + * + *cckpd_t[0][0][1][0] = 1ad0[4:0] r_CS_ratio_RFBW20_1R[4:0] + *cckpd_t[0][1][1][0] = 1ad0[9:5] r_CS_ratio_RFBW20_2R[4:0] + *cckpd_t[0][2][1][0] = 1ad0[14:10] r_CS_ratio_RFBW20_3R[4:0] + *cckpd_t[0][3][1][0] = 1ad0[19:15] r_CS_ratio_RFBW20_4R[4:0] + *cckpd_t[1][0][1][0] = 1ad0[24:20] r_CS_ratio_RFBW40_1R[4:0] + *cckpd_t[1][1][1][0] = 1ad0[29:25] r_CS_ratio_RFBW40_2R[4:0] + *cckpd_t[1][2][1][0] = 1ad0[31:30] r_CS_ratio_RFBW40_3R[1:0] + * 1ad4[2:0] r_CS_ratio_RFBW40_3R[4:2] + *cckpd_t[1][3][1][0] = 1ad4[7:3] r_CS_ratio_RFBW40_4R[4:0] + */ + #endif + /*[Check Nrx]*/ + cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1; + + /*[Check BW]*/ + val = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc); + if (val == 0) + cck_bw = CHANNEL_WIDTH_20; + else if (val == 1) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_80; + + cckpd_t->cck_bw = cck_bw; + cckpd_t->cck_n_rx = cck_n_rx; + reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD); + reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD); + reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD); + reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD); + + for (i = 0 ; i < CCK_PD_LV_MAX ; i++) { + pw_step = i * 2; + cs_step = i * 2; + + #if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) { + pw_step = i; + cs_step = i; + if (i > CCK_PD_LV_3) { + pw_step = 3; + cs_step = 3; + } + } + #endif + + #if (RTL8822C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822C) { + if (i == CCK_PD_LV_1) { + pw_step = 9; /*IGI-19.2:0x11=d'17*/ + cs_step = 0; + } else if (i == CCK_PD_LV_2) { + pw_step = 12; /*IGI-15.5:0x14=d'20*/ + cs_step = 1; + } else if (i == CCK_PD_LV_3) { + pw_step = 14; /*IGI-14:0x16=d'22*/ + cs_step = 1; + } else if (i == CCK_PD_LV_4) { + pw_step = 17; /*IGI-12:0x19=d'25*/ + cs_step = 1; + } + } + #endif + + val = (u8)(reg0 & 0x000000ff) + pw_step; + PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val); + cckpd_t->cckpd_jgr3[0][0][0][i] = val; + + val = (u8)(reg1 & 0x000000ff) + pw_step; + cckpd_t->cckpd_jgr3[1][0][0][i] = val; + + val = (u8)(reg2 & 0x0000001f) + cs_step; + cckpd_t->cckpd_jgr3[0][0][1][i] = val; + + val = (u8)((reg2 & 0x01f00000) >> 20) + cs_step; + cckpd_t->cckpd_jgr3[1][0][1][i] = val; + + #ifdef PHYDM_COMPILE_ABOVE_2SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + val = (u8)((reg0 & 0x0000ff00) >> 8) + pw_step; + cckpd_t->cckpd_jgr3[0][1][0][i] = val; + + val = (u8)((reg1 & 0x0000ff00) >> 8) + pw_step; + cckpd_t->cckpd_jgr3[1][1][0][i] = val; + + val = (u8)((reg2 & 0x000003e0) >> 5) + cs_step; + cckpd_t->cckpd_jgr3[0][1][1][i] = val; + + val = (u8)((reg2 & 0x3e000000) >> 25) + cs_step; + cckpd_t->cckpd_jgr3[1][1][1][i] = val; + } + #endif + + #ifdef PHYDM_COMPILE_ABOVE_3SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) { + val = (u8)((reg0 & 0x00ff0000) >> 16) + pw_step; + cckpd_t->cckpd_jgr3[0][2][0][i] = val; + + val = (u8)((reg1 & 0x00ff0000) >> 16) + pw_step; + cckpd_t->cckpd_jgr3[1][2][0][i] = val; + val = (u8)((reg2 & 0x00007c00) >> 10) + cs_step; + cckpd_t->cckpd_jgr3[0][2][1][i] = val; + val = (u8)(((reg2 & 0xc0000000) >> 30) | + ((reg3 & 0x7) << 3)) + cs_step; + cckpd_t->cckpd_jgr3[1][2][1][i] = val; + } + #endif + + #ifdef PHYDM_COMPILE_ABOVE_4SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + val = (u8)((reg0 & 0xff000000) >> 24) + pw_step; + cckpd_t->cckpd_jgr3[0][3][0][i] = val; + + val = (u8)((reg1 & 0xff000000) >> 24) + pw_step; + cckpd_t->cckpd_jgr3[1][3][0][i] = val; + + val = (u8)((reg2 & 0x000f8000) >> 15) + cs_step; + cckpd_t->cckpd_jgr3[0][3][1][i] = val; + + val = (u8)((reg3 & 0x000000f8) >> 3) + cs_step; + cckpd_t->cckpd_jgr3[1][3][1][i] = val; + } + #endif + } +} + +void phydm_invalid_cckpd_type4(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 val = 0; + u8 i = 0; + u8 j = 0; + u8 k = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__); + + for (i = 0; i < CCK_PD_LV_MAX; i++) { + for (j = 0; j < 2; j++) { + for (k = 0; k < dm->num_rf_path; k++) { + val = cckpd_t->cckpd_jgr3[j][k][1][i]; + if (val == INVALID_CS_RATIO_0) + cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1c; + else if (val == INVALID_CS_RATIO_1) + cckpd_t->cckpd_jgr3[j][k][1][i] = 0x1e; + else if (val > MAXVALID_CS_RATIO) + cckpd_t->cckpd_jgr3[j][k][1][i] = + MAXVALID_CS_RATIO; + } + } + + #if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + val = cckpd_t->cckpd_jgr3[0][3][1][i]; + if (i == CCK_PD_LV_1 && val > 0x10) + cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10; + else if (i == CCK_PD_LV_2 && val > 0x10) + cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10; + else if (i == CCK_PD_LV_3 && val > 0x10) + cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10; + else if (i == CCK_PD_LV_4 && val > 0x10) + cckpd_t->cckpd_jgr3[0][3][1][i] = 0x10; + val = cckpd_t->cckpd_jgr3[1][3][1][i]; + if (i == CCK_PD_LV_1 && val > 0xF) + cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF; + else if (i == CCK_PD_LV_2 && val > 0xF) + cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF; + else if (i == CCK_PD_LV_3 && val > 0xF) + cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF; + else if (i == CCK_PD_LV_4 && val > 0xF) + cckpd_t->cckpd_jgr3[1][3][1][i] = 0xF; + } + #endif + } +} + +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/ + + +#ifdef PHYDM_COMPILE_CCKPD_TYPE5 +void phydm_write_cck_pd_type5(void *dm_void, enum cckpd_lv lv, + enum cckpd_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 val = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n"); + switch (mode) { + case CCK_BW20_1R: /*RFBW20_1R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][0][0][lv]; + odm_set_bb_reg(dm, R_0x1a30, 0x1f, val); + val = cckpd_t->cck_pd_table_jgr3[0][0][1][lv]; + odm_set_bb_reg(dm, R_0x1a20, 0x1f, val); + } break; + case CCK_BW40_1R: /*RFBW40_1R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][0][0][lv]; + odm_set_bb_reg(dm, R_0x1a34, 0x1f, val); + val = cckpd_t->cck_pd_table_jgr3[1][0][1][lv]; + odm_set_bb_reg(dm, R_0x1a24, 0x1f, val); + } break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case CCK_BW20_2R: /*RFBW20_2R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][1][0][lv]; + odm_set_bb_reg(dm, R_0x1a30, 0x3e0, val); + val = cckpd_t->cck_pd_table_jgr3[0][1][1][lv]; + odm_set_bb_reg(dm, R_0x1a20, 0x3e0, val); + } break; + case CCK_BW40_2R: /*RFBW40_2R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][1][0][lv]; + odm_set_bb_reg(dm, R_0x1a34, 0x3e0, val); + val = cckpd_t->cck_pd_table_jgr3[1][1][1][lv]; + odm_set_bb_reg(dm, R_0x1a24, 0x3e0, val); + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case CCK_BW20_3R: /*RFBW20_3R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][2][0][lv]; + odm_set_bb_reg(dm, R_0x1a30, 0x7c00, val); + val = cckpd_t->cck_pd_table_jgr3[0][2][1][lv]; + odm_set_bb_reg(dm, R_0x1a20, 0x7c00, val); + } break; + case CCK_BW40_3R: /*RFBW40_3R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][2][0][lv]; + odm_set_bb_reg(dm, R_0x1a34, 0x7c00, val); + val = cckpd_t->cck_pd_table_jgr3[1][2][1][lv]; + odm_set_bb_reg(dm, R_0x1a24, 0x7c00, val); + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case CCK_BW20_4R: /*RFBW20_4R*/ + { + val = cckpd_t->cck_pd_table_jgr3[0][3][0][lv]; + odm_set_bb_reg(dm, R_0x1a30, 0xF8000, val); + val = cckpd_t->cck_pd_table_jgr3[0][3][1][lv]; + odm_set_bb_reg(dm, R_0x1a20, 0xF8000, val); + } break; + case CCK_BW40_4R: /*RFBW40_4R*/ + { + val = cckpd_t->cck_pd_table_jgr3[1][3][0][lv]; + odm_set_bb_reg(dm, R_0x1a34, 0xF8000, val); + val = cckpd_t->cck_pd_table_jgr3[1][3][1][lv]; + odm_set_bb_reg(dm, R_0x1a24, 0xF8000, val); + } break; + #endif + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } +} + + +void phydm_set_cck_pd_lv_type5(void *dm_void, enum cckpd_lv lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_mode cck_mode = CCK_BW20_1R; + enum channel_width cck_bw = CHANNEL_WIDTH_20; + u8 cck_n_rx = 0; + u32 val = 0; + /*u32 val_dbg = 0;*/ + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv); + + /*[Check Nrx] for 8723F*/ + cck_n_rx = 1; + + /*[Check BW]*/ + val = odm_get_bb_reg(dm, R_0x9b0, 0xc); + if (val == 0) + cck_bw = CHANNEL_WIDTH_20; + else if (val == 1) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_80; + + /*[Check LV]*/ + if (cckpd_t->cck_pd_lv == lv && + cckpd_t->cck_n_rx == cck_n_rx && + cckpd_t->cck_bw == cck_bw) { + PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv); + return; + } + cckpd_t->cck_bw = cck_bw; + cckpd_t->cck_n_rx = cck_n_rx; + cckpd_t->cck_pd_lv = lv; + cckpd_t->cck_fa_ma = CCK_FA_MA_RESET; + + switch (cck_n_rx) { + case 1: /*1R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_1R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_1R; + } break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: /*2R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_2R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_2R; + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: /*3R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_3R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_3R; + } break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: /*4R*/ + { + if (cck_bw == CHANNEL_WIDTH_20) + cck_mode = CCK_BW20_4R; + else if (cck_bw == CHANNEL_WIDTH_40) + cck_mode = CCK_BW40_4R; + } break; + #endif + default: + /*@pr_debug("[%s] warning!\n", __func__);*/ + break; + } + + + +phydm_write_cck_pd_type5(dm, lv, cck_mode); +} + +void phydm_read_cckpd_para_type5(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 bw = 0; /*r_RX_RF_BW*/ + u8 n_rx = 0; + u8 curr_cck_pd_t[2][4][2]; + u32 reg0 = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u32 reg3 = 0; + + bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc); + + reg0 = odm_get_bb_reg(dm, R_0x1a30, MASKDWORD); + reg1 = odm_get_bb_reg(dm, R_0x1a34, MASKDWORD); + reg2 = odm_get_bb_reg(dm, R_0x1a20, MASKDWORD); + reg3 = odm_get_bb_reg(dm, R_0x1a24, MASKDWORD); + curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x0000001f); + curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x0000001f); + curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f); + curr_cck_pd_t[1][0][1] = (u8)(reg3 & 0x0000001f); + n_rx = 1; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x000003E0) >> 5); + curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x000003E0) >> 5); + curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5); + curr_cck_pd_t[1][1][1] = (u8)((reg3 & 0x000003E0) >> 5); + n_rx = 2; + } + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) { + curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00007C00) >> 10); + curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00007C00) >> 10); + curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10); + curr_cck_pd_t[1][2][1] = (u8)((reg3 & 0x00007C00) >> 10); + n_rx = 3; + } + #endif + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0x000F8000) >> 15); + curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0x000F8000) >> 15); + curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15); + curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000F8000) >> 15); + n_rx = 4; + } + #endif + + PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx); + PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=0x%x, PD th=0x%x\n", + cckpd_t->cck_pd_lv, + curr_cck_pd_t[bw][n_rx - 1][1], + curr_cck_pd_t[bw][n_rx - 1][0]); +} + +void phydm_cckpd_type5(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u8 igi = dm->dm_dig_table.cur_ig_value; + enum cckpd_lv lv = 0; + boolean is_update = true; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (dm->is_linked) { + PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n"); + if (dm->rssi_min > 40) { + lv = CCK_PD_LV_4; + PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n"); + } else if (dm->rssi_min > 32) { + lv = CCK_PD_LV_3; + PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n"); + } else if (dm->rssi_min > 24) { + lv = CCK_PD_LV_2; + PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n"); + } else { + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n"); + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n"); + } else { + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n"); + } + } + } else { + PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n"); + if (cckpd_t->cck_fa_ma > 1000) { + lv = CCK_PD_LV_1; + PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n"); + } else if (cckpd_t->cck_fa_ma < 500) { + lv = CCK_PD_LV_0; + PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n"); + } else { + is_update = false; + PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n"); + } + } + + if (is_update) { + phydm_set_cck_pd_lv_type5(dm, lv); + + PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n", + cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][1][lv], + cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][0][lv]); + } + + phydm_read_cckpd_para_type5(dm); +} + +void phydm_cck_pd_init_type5(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 reg0 = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u32 reg3 = 0; + u8 pw_step = 0; + u8 cs_step = 0; + u8 cck_bw = 0; /*r_RX_RF_BW*/ + u8 cck_n_rx = 0; + u8 val = 0; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__); + #if 0 + /*@ + *cckpd_t[0][0][0][0] = 1a30[4:0] r_PD_lim_RFBW20_1R + *cckpd_t[0][1][0][0] = 1a30[9:5] r_PD_lim_RFBW20_2R + *cckpd_t[0][2][0][0] = 1a30[14:10] r_PD_lim_RFBW20_3R + *cckpd_t[0][3][0][0] = 1a30[19:15] r_PD_lim_RFBW20_4R + *cckpd_t[1][0][0][0] = 1a34[4:0] r_PD_lim_RFBW40_1R + *cckpd_t[1][1][0][0] = 1a34[9:5] r_PD_lim_RFBW40_2R + *cckpd_t[1][2][0][0] = 1a34[14:10] r_PD_lim_RFBW40_3R + *cckpd_t[1][3][0][0] = 1a34[19:15] r_PD_lim_RFBW40_4R + * + * + *cckpd_t[0][0][1][0] = 1a20[4:0] r_CS_ratio_RFBW20_1R + *cckpd_t[0][1][1][0] = 1a20[9:5] r_CS_ratio_RFBW20_2R + *cckpd_t[0][2][1][0] = 1a20[14:10] r_CS_ratio_RFBW20_3R + *cckpd_t[0][3][1][0] = 1a20[19:15] r_CS_ratio_RFBW20_4R + *cckpd_t[1][0][1][0] = 1a24[4:0] r_CS_ratio_RFBW40_1R + *cckpd_t[1][1][1][0] = 1a24[9:5] r_CS_ratio_RFBW40_2R + *cckpd_t[1][2][1][0] = 1a24[14:10] r_CS_ratio_RFBW40_3R + *cckpd_t[1][3][1][0] = 1a24[19:15] r_CS_ratio_RFBW40_4R + */ + #endif + /*[Check Nrx]*/ + cck_n_rx = 1; + + /*[Check BW]*/ + val = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc); + if (val == 0) + cck_bw = CHANNEL_WIDTH_20; + else if (val == 1) + cck_bw = CHANNEL_WIDTH_40; + else + cck_bw = CHANNEL_WIDTH_80; + + cckpd_t->cck_bw = cck_bw; + reg0 = odm_get_bb_reg(dm, R_0x1a30, MASKDWORD); + reg1 = odm_get_bb_reg(dm, R_0x1a34, MASKDWORD); + reg2 = odm_get_bb_reg(dm, R_0x1a20, MASKDWORD); + reg3 = odm_get_bb_reg(dm, R_0x1a24, MASKDWORD); + + for (i = 0 ; i < CCK_PD_LV_MAX ; i++) { + pw_step = i * 2; + cs_step = i * 2; + + #if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) { + if (i == CCK_PD_LV_1) { + pw_step = 9; /*IGI-19.2:0x11=d'17*/ + cs_step = 0; + } else if (i == CCK_PD_LV_2) { + pw_step = 12; /*IGI-15.5:0x14=d'20*/ + cs_step = 1; + } else if (i == CCK_PD_LV_3) { + pw_step = 14; /*IGI-14:0x16=d'22*/ + cs_step = 1; + } else if (i == CCK_PD_LV_4) { + pw_step = 17; /*IGI-12:0x19=d'25*/ + cs_step = 1; + } + } + #endif + val = (u8)(reg0 & 0x0000001F) + pw_step; + PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val); + cckpd_t->cck_pd_table_jgr3[0][0][0][i] = val; + + val = (u8)(reg1 & 0x0000001F) + pw_step; + cckpd_t->cck_pd_table_jgr3[1][0][0][i] = val; + + val = (u8)(reg2 & 0x0000001F) + cs_step; + cckpd_t->cck_pd_table_jgr3[0][0][1][i] = val; + + val = (u8)(reg3 & 0x0000001F) + cs_step; + cckpd_t->cck_pd_table_jgr3[1][0][1][i] = val; + + #ifdef PHYDM_COMPILE_ABOVE_2SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) { + val = (u8)((reg0 & 0x000003E0) >> 5) + pw_step; + cckpd_t->cck_pd_table_jgr3[0][1][0][i] = val; + + val = (u8)((reg1 & 0x000003E0) >> 5) + pw_step; + cckpd_t->cck_pd_table_jgr3[1][1][0][i] = val; + + val = (u8)((reg2 & 0x000003E0) >> 5) + cs_step; + cckpd_t->cck_pd_table_jgr3[0][1][1][i] = val; + + val = (u8)((reg3 & 0x000003E0) >> 5) + cs_step; + cckpd_t->cck_pd_table_jgr3[1][1][1][i] = val; + + cck_n_rx = 2; + } + #endif + #ifdef PHYDM_COMPILE_ABOVE_3SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) { + val = (u8)((reg0 & 0x00007C00) >> 10) + pw_step; + cckpd_t->cck_pd_table_jgr3[0][2][0][i] = val; + + val = (u8)((reg1 & 0x00007C00) >> 10) + pw_step; + cckpd_t->cck_pd_table_jgr3[1][2][0][i] = val; + + val = (u8)((reg2 & 0x00007C00) >> 10) + cs_step; + cckpd_t->cck_pd_table_jgr3[0][2][1][i] = val; + + val = (u8)((reg3 & 0x00007C00) >> 10) + cs_step; + cckpd_t->cck_pd_table_jgr3[1][2][1][i] = val; + + cck_n_rx = 3; + } + #endif + + #ifdef PHYDM_COMPILE_ABOVE_4SS + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + val = (u8)((reg0 & 0x000F8000) >> 15) + pw_step; + cckpd_t->cck_pd_table_jgr3[0][3][0][i] = val; + + val = (u8)((reg1 & 0x000F8000) >> 15) + pw_step; + cckpd_t->cck_pd_table_jgr3[1][3][0][i] = val; + + val = (u8)((reg2 & 0x000F8000) >> 15) + cs_step; + cckpd_t->cck_pd_table_jgr3[0][3][1][i] = val; + + val = (u8)((reg3 & 0x000F8000) >> 15) + cs_step; + cckpd_t->cck_pd_table_jgr3[1][3][1][i] = val; + + cck_n_rx = 4; + } + #endif + } + cckpd_t->cck_n_rx = cck_n_rx; +} + + + + +#endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE5*/ + + + + +void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv; + + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=1\n"); + return; + } + + lv = (enum cckpd_lv)val_buf[0]; + + if (lv > CCK_PD_LV_4) { + pr_debug("[%s] warning! lv=%d\n", __func__, lv); + return; + } + + switch (cckpd_t->cckpd_hw_type) { + #ifdef PHYDM_COMPILE_CCKPD_TYPE1 + case 1: + phydm_set_cckpd_lv_type1(dm, lv); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + case 2: + phydm_set_cckpd_lv_type2(dm, lv); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + case 3: + phydm_set_cckpd_lv_type3(dm, lv); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + case 4: + phydm_set_cck_pd_lv_type4(dm, lv); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE5 + case 5: + phydm_set_cck_pd_lv_type5(dm, lv); + break; + #endif + default: + pr_debug("[%s]warning\n", __func__); + break; + } +} + +boolean +phydm_stop_cck_pd_th(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_FA_CNT)) { + PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_FA_CNT disable\n"); + return true; + } + + if (!(dm->support_ability & ODM_BB_CCK_PD)) { + PHYDM_DBG(dm, DBG_CCKPD, "Not Support:ODM_BB_CCK_PD disable\n"); + return true; + } + + if (dm->pause_ability & ODM_BB_CCK_PD) { + PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n", + dm->pause_lv_table.lv_cckpd); + return true; + } + + if (dm->is_linked && (*dm->channel > 36)) { + PHYDM_DBG(dm, DBG_CCKPD, "Return: 5G CH=%d\n", *dm->channel); + return true; + } + return false; +} + +void phydm_cck_pd_th(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + u32 cck_fa = fa_t->cnt_cck_fail; + #ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc; + #endif + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] ======>\n", __func__); + + if (phydm_stop_cck_pd_th(dm)) + return; + + #ifdef PHYDM_TDMA_DIG_SUPPORT + if (dm->original_dig_restore) + cck_fa = fa_t->cnt_cck_fail; + else + cck_fa = fa_acc_t->cnt_cck_fail_1sec; + #endif + + if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET) + cckpd_t->cck_fa_ma = cck_fa; + else + cckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2; + + PHYDM_DBG(dm, DBG_CCKPD, + "IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\n", + dm->dm_dig_table.cur_ig_value, dm->rssi_min, + cck_fa, cckpd_t->cck_fa_ma); + + switch (cckpd_t->cckpd_hw_type) { + #ifdef PHYDM_COMPILE_CCKPD_TYPE1 + case 1: + phydm_cckpd_type1(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + case 2: + phydm_cckpd_type2(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + case 3: + phydm_cckpd_type3(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + case 4: + #ifdef PHYDM_DCC_ENHANCE + if (dm->dm_dcc_info.dcc_en) + phydm_cckpd_type4_dcc(dm); + else + #endif + phydm_cckpd_type4(dm); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE5 + case 5: + phydm_cckpd_type5(dm); + break; + #endif + default: + pr_debug("[%s]warning\n", __func__); + break; + } +} + +void phydm_cck_pd_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + + if (*dm->mp_mode) + return; + + if (dm->support_ic_type & CCK_PD_IC_TYPE1) + cckpd_t->cckpd_hw_type = 1; + else if (dm->support_ic_type & CCK_PD_IC_TYPE2) + cckpd_t->cckpd_hw_type = 2; + else if (dm->support_ic_type & CCK_PD_IC_TYPE3) + cckpd_t->cckpd_hw_type = 3; + else if (dm->support_ic_type & CCK_PD_IC_TYPE4) + cckpd_t->cckpd_hw_type = 4; + + if (dm->support_ic_type & CCK_PD_IC_TYPE5) + cckpd_t->cckpd_hw_type = 5; + + PHYDM_DBG(dm, DBG_CCKPD, "[%s] cckpd_hw_type=%d\n", + __func__, cckpd_t->cckpd_hw_type); + + cckpd_t->cck_pd_lv = CCK_PD_LV_INIT; + cckpd_t->cck_n_rx = 0xff; + cckpd_t->cck_bw = CHANNEL_WIDTH_MAX; + cckpd_t->cck_fa_th[1] = 400; + cckpd_t->cck_fa_th[0] = 200; + + switch (cckpd_t->cckpd_hw_type) { + #ifdef PHYDM_COMPILE_CCKPD_TYPE1 + case 1: + phydm_set_cckpd_lv_type1(dm, CCK_PD_LV_1); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + case 2: + cckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f; + phydm_set_cckpd_lv_type2(dm, CCK_PD_LV_1); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + case 3: + phydm_cck_pd_init_type3(dm); + phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_1); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + case 4: + phydm_cck_pd_init_type4(dm); + phydm_invalid_cckpd_type4(dm); + phydm_set_cck_pd_lv_type4(dm, CCK_PD_LV_1); + break; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE5 + case 5: + phydm_cck_pd_init_type5(dm); + break; + #endif + default: + pr_debug("[%s]warning\n", __func__); + break; + } +} + +#ifdef PHYDM_DCC_ENHANCE + +void phydm_cckpd_type4_dcc(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + enum cckpd_lv lv_curr = cckpd_t->cck_pd_lv; + enum phydm_cck_pd_trend trend = CCKPD_STABLE; + u8 th_ofst = 0; + u16 lv_up_th, lv_down_th; + + PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__); + + if (!dm->is_linked) + th_ofst = 1; + + lv_up_th = (cckpd_t->cck_fa_th[1]) << th_ofst; + lv_down_th = (cckpd_t->cck_fa_th[0]) << th_ofst; + + PHYDM_DBG(dm, DBG_CCKPD, "th{Up, Down}: {%d, %d}\n", + lv_up_th, lv_down_th); + + if (cckpd_t->cck_fa_ma > lv_up_th) { + if (lv_curr <= CCK_PD_LV_3) { + lv_curr++; + trend = CCKPD_INCREASING; + } else { + lv_curr = CCK_PD_LV_4; + } + } else if (cckpd_t->cck_fa_ma < lv_down_th) { + if (lv_curr >= CCK_PD_LV_1) { + lv_curr--; + trend = CCKPD_DECREASING; + } else { + lv_curr = CCK_PD_LV_0; + } + } + + PHYDM_DBG(dm, DBG_CCKPD, "lv: %d->%d\n", cckpd_t->cck_pd_lv, lv_curr); +#if 1 + if (trend != CCKPD_STABLE) { + phydm_set_cck_pd_lv_type4(dm, lv_curr); + + PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n", + cckpd_t->cckpd_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][1][lv_curr], + cckpd_t->cckpd_jgr3[cckpd_t->cck_bw] + [cckpd_t->cck_n_rx - 1][0][lv_curr]); + } + phydm_read_cckpd_para_type4(dm); +#endif +} + +boolean phydm_do_cckpd(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (dig_t->igi_trend == DIG_INCREASING) + return false; + + return true; +} + +void phydm_dig_cckpd_coex(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dcc_struct *dcc = &dm->dm_dcc_info; + + if (*dm->channel > 36) { + phydm_dig(dm); + return; + } else if (!dcc->dcc_en) { + phydm_dig(dm); + phydm_cck_pd_th(dm); + return; + } + + dcc->dig_execute_cnt++; + PHYDM_DBG(dm, DBG_CCKPD, "DCC_cnt: %d\n", dcc->dig_execute_cnt); + + if (dcc->dig_execute_cnt % dcc->dcc_ratio) { + PHYDM_DBG(dm, DBG_CCKPD, "DCC: DIG\n"); + phydm_dig(dm); + } else { + if (phydm_do_cckpd(dm)) { + PHYDM_DBG(dm, DBG_CCKPD, "DCC: CCKPD\n"); + dcc->dcc_mode = DCC_CCK_PD; + phydm_cck_pd_th(dm); + } else { + PHYDM_DBG(dm, DBG_CCKPD, "DCC: Boost_DIG\n"); + dcc->dcc_mode = DCC_DIG; + phydm_dig(dm); + } + } +} + +void phydm_dig_cckpd_coex_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_dcc_struct *dcc = &dm->dm_dcc_info; + + dcc->dcc_mode = DCC_DIG; + dcc->dcc_en = false; + dcc->dig_execute_cnt = 0; + dcc->dcc_ratio = 2; +} + +void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table; + struct phydm_dcc_struct *dcc = &dm->dm_dcc_info; + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + for (i = 0; i < 3; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Enable: en {0/1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "DCC_ratio: ratio {x}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "threshold: th {Down_th} {Up_th}\n"); + } else if ((strcmp(input[1], "en") == 0)) { + dcc->dcc_en = (var[1]) ? true : false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "en=%d\n", dcc->dcc_en); + } else if ((strcmp(input[1], "ratio") == 0)) { + dcc->dcc_ratio = (u8)var[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Ratio=%d\n", dcc->dcc_ratio); + } else if ((strcmp(input[1], "th") == 0)) { + cckpd_t->cck_fa_th[1] = (u16)var[2]; + cckpd_t->cck_fa_th[0] = (u16)var[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "th{Down, Up}: {%d, %d}\n", + cckpd_t->cck_fa_th[0], cckpd_t->cck_fa_th[1]); + } + + *_used = used; + *_out_len = out_len; +} + +#endif +#endif /*#ifdef PHYDM_SUPPORT_CCKPD*/ + diff --git a/hal/phydm/phydm_cck_pd.h b/hal/phydm/phydm_cck_pd.h new file mode 100644 index 0000000..2a1d3ea --- /dev/null +++ b/hal/phydm/phydm_cck_pd.h @@ -0,0 +1,202 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_CCK_PD_H__ +#define __PHYDM_CCK_PD_H__ + +/* 2019.12.25 decrease CS_ratio in 8822C due to Lenovo test result(PCIE-5136).*/ +#define CCK_PD_VERSION "4.0" + +/*@ + * 1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +#define CCK_FA_MA_RESET 0xffffffff + +#define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/ +#define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/ +#define MAXVALID_CS_RATIO 0x1f +/*@Run time flag of CCK_PD HW type*/ +#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\ + ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\ + ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\ + ODM_RTL8195A | ODM_RTL8188F) + +#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\ + ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/ + +#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C) +/*@extend for different bw & path*/ + +#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/ +#define CCK_PD_IC_TYPE5 (ODM_RTL8723F) /*@extend for different CR*/ + +/*@Compile time flag of CCK_PD HW type*/ +#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\ + RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\ + RTL8195A_SUPPORT || RTL8188F_SUPPORT) + #define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/ +#endif + +#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\ + RTL8710B_SUPPORT || RTL8195B_SUPPORT) + #define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/ +#endif + +#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) + #define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/ +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + #define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/ +#endif +#if (RTL8723F_SUPPORT) + #define PHYDM_COMPILE_CCKPD_TYPE5 /*@extend for different & path*/ +#endif + +/*@ + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ +enum cckpd_lv { + CCK_PD_LV_INIT = 0xff, + CCK_PD_LV_0 = 0, + CCK_PD_LV_1 = 1, + CCK_PD_LV_2 = 2, + CCK_PD_LV_3 = 3, + CCK_PD_LV_4 = 4, + CCK_PD_LV_MAX = 5 +}; + +enum cckpd_mode { + CCK_BW20_1R = 0, + CCK_BW20_2R = 1, + CCK_BW20_3R = 2, + CCK_BW20_4R = 3, + CCK_BW40_1R = 4, + CCK_BW40_2R = 5, + CCK_BW40_3R = 6, + CCK_BW40_4R = 7 +}; + +enum dcc_mode { + DCC_DIG = 0, + DCC_CCK_PD = 1 +}; + +enum phydm_cck_pd_trend { + CCKPD_STABLE = 0, + CCKPD_INCREASING = 1, + CCKPD_DECREASING = 2 +}; + +/*@ + * 1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +#ifdef PHYDM_SUPPORT_CCKPD + +#ifdef PHYDM_DCC_ENHANCE +struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/ + boolean dcc_en; + enum dcc_mode dcc_mode; + u32 dig_execute_cnt; + u8 dcc_ratio; +}; +#endif + +struct phydm_cckpd_struct { + u8 cckpd_hw_type; + u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/ + u32 cck_fa_ma; + u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ + u8 pause_lv; + u8 cck_n_rx; + u16 cck_fa_th[2]; + enum channel_width cck_bw; + enum cckpd_lv cck_pd_lv; + #ifdef PHYDM_COMPILE_CCKPD_TYPE2 + u8 cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/ + u8 aaa_default; /*@Init cs_ratio value - 0xaaa*/ + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE3 + /*Default value*/ + u8 cck_pd_20m_1r; + u8 cck_pd_20m_2r; + u8 cck_pd_40m_1r; + u8 cck_pd_40m_2r; + u8 cck_cs_ratio_20m_1r; + u8 cck_cs_ratio_20m_2r; + u8 cck_cs_ratio_40m_1r; + u8 cck_cs_ratio_40m_2r; + u8 cck_din_shift_opt; + /*Current value*/ + u8 cur_cck_pd_20m_1r; + u8 cur_cck_pd_20m_2r; + u8 cur_cck_pd_40m_1r; + u8 cur_cck_pd_40m_2r; + u8 cur_cck_cs_ratio_20m_1r; + u8 cur_cck_cs_ratio_20m_2r; + u8 cur_cck_cs_ratio_40m_1r; + u8 cur_cck_cs_ratio_40m_2r; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE4 + /*@[bw][nrx][0:PD/1:CS][lv]*/ + u8 cckpd_jgr3[2][4][2][CCK_PD_LV_MAX]; + #endif + #ifdef PHYDM_COMPILE_CCKPD_TYPE5 + /*@[bw][nrx][0:PD/1:CS][lv]*/ + u8 cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX]; + #endif +}; +#endif + +/*@ + * 1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len); + +void phydm_cck_pd_th(void *dm_void); + +void phydm_cck_pd_init(void *dm_void); + +#ifdef PHYDM_DCC_ENHANCE +void phydm_cckpd_type4_dcc(void *dm_void); + +void phydm_dig_cckpd_coex(void *dm_void); + +void phydm_dig_cckpd_coex_init(void *dm_void); + +void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif +#endif diff --git a/hal/phydm/phydm_cck_rx_pathdiv.c b/hal/phydm/phydm_cck_rx_pathdiv.c new file mode 100644 index 0000000..3106f19 --- /dev/null +++ b/hal/phydm/phydm_cck_rx_pathdiv.c @@ -0,0 +1,163 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT /* @PHYDM-342*/ +void phydm_cck_rx_pathdiv_manaul(void *dm_void, boolean en_cck_rx_pathdiv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /* @Can not apply for 98F/14B/97G from DD YC*/ + if (en_cck_rx_pathdiv) { + odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x0); + odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x1); + } else { + odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x1); + odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x0); + } +} + +void phydm_cck_rx_pathdiv_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u8 rssi_th = 0; + u32 rssi_a = 0, rssi_b = 0, rssi_avg = 0; + + if (!cckrx_t->en_cck_rx_pathdiv) + return; + + rssi_a = PHYDM_DIV(cckrx_t->path_a_sum, cckrx_t->path_a_cnt); + rssi_b = PHYDM_DIV(cckrx_t->path_b_sum, cckrx_t->path_b_cnt); + rssi_avg = (rssi_a + rssi_b) >> 1; + + pr_debug("Rx-A:%d, Rx-B:%d, avg:%d\n", rssi_a, rssi_b, rssi_avg); + + cckrx_t->path_a_cnt = 0; + cckrx_t->path_a_sum = 0; + cckrx_t->path_b_cnt = 0; + cckrx_t->path_b_sum = 0; + + if (fa_t->cnt_all >= 100) + rssi_th = cckrx_t->rssi_fa_th; + else + rssi_th = cckrx_t->rssi_th; + + if (dm->phy_dbg_info.num_qry_beacon_pkt > 14 && rssi_avg <= rssi_th) + phydm_cck_rx_pathdiv_manaul(dm, true); + else + phydm_cck_rx_pathdiv_manaul(dm, false); +} + +void phydm_cck_rx_pathdiv_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table; + + cckrx_t->en_cck_rx_pathdiv = false; + cckrx_t->path_a_cnt = 0; + cckrx_t->path_a_sum = 0; + cckrx_t->path_b_cnt = 0; + cckrx_t->path_b_sum = 0; + cckrx_t->rssi_fa_th = 45; + cckrx_t->rssi_th = 25; +} + +void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void, + void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = NULL; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + + if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid)) + return; + + if (pktinfo->is_cck_rate) + return; + + cckrx_t->path_a_sum += phy_info->rx_mimo_signal_strength[0]; + cckrx_t->path_a_cnt++; + + cckrx_t->path_b_sum += phy_info->rx_mimo_signal_strength[1]; + cckrx_t->path_b_cnt++; +} + +void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + if (!(dm->support_ic_type & ODM_RTL8822C)) + return; + + for (i = 0; i < 3; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "CCK rx pathdiv manual on: {1} {En}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CCK rx pathdiv watchdog on: {2} {En}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CCK rx pathdiv rssi_th : {3} {th} {fa_th}\n"); + } else if (var1[0] == 1) { + if (var1[1] == 1) + phydm_cck_rx_pathdiv_manaul(dm, true); + else + phydm_cck_rx_pathdiv_manaul(dm, false); + } else if (var1[0] == 2) { + if (var1[1] == 1) { + cckrx_t->en_cck_rx_pathdiv = true; + } else { + cckrx_t->en_cck_rx_pathdiv = false; + phydm_cck_rx_pathdiv_manaul(dm, false); + } + } else if (var1[0] == 3) { + cckrx_t->rssi_th = (u8)var1[1]; + cckrx_t->rssi_fa_th = (u8)var1[2]; + } + *_used = used; + *_out_len = out_len; +} +#endif diff --git a/hal/phydm/phydm_cck_rx_pathdiv.h b/hal/phydm/phydm_cck_rx_pathdiv.h new file mode 100644 index 0000000..952bcf5 --- /dev/null +++ b/hal/phydm/phydm_cck_rx_pathdiv.h @@ -0,0 +1,67 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_CCK_RX_PATHDIV_H__ +#define __PHYDM_CCK_RX_PATHDIV_H__ + +#define CCK_RX_PATHDIV_VERSION "1.1" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct phydm_cck_rx_pathdiv { + boolean en_cck_rx_pathdiv; + u32 path_a_sum; + u32 path_b_sum; + u16 path_a_cnt; + u16 path_b_cnt; + u8 rssi_fa_th; + u8 rssi_th; +}; + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_cck_rx_pathdiv_watchdog(void *dm_void); + +void phydm_cck_rx_pathdiv_init(void *dm_void); + +void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void, + void *pkt_info_void); + +void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif diff --git a/hal/phydm/phydm_ccx.c b/hal/phydm/phydm_ccx.c new file mode 100644 index 0000000..6bc88ba --- /dev/null +++ b/hal/phydm/phydm_ccx.c @@ -0,0 +1,3468 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +u8 phydm_env_mntr_get_802_11_k_rsni(void *dm_void, s8 rcpi, s8 anpi) +{ + u8 rsni = 0; + u8 signal = 0; + u8 sig_to_rsni[13] = {0, 8, 15, 20, 24, 27, 30, 32, 35, 37, 39, 41, 43}; + + /*rcpi = signal + noise + interference = rssi*/ + /*anpi = noise + interferecne = nhm*/ + /*signal = rcpi - anpi*/ + + /*rsni = 2*(10*log10((rcpi_lin/anpi_lin)-1)+10), unit = 0.5dB*/ + /*rcpi_lin/anpi_lin=10^((rcpi_dB-anpi_db)/10)*/ + /*rsni is approximated as 2*((rcpi_db-anpi_db)+10) when signal >= 13*/ + + if (rcpi <= anpi) + signal = 0; + else if (rcpi - anpi >= 117) + signal = 117; + else + signal = rcpi - anpi; + + if (signal < 13) + rsni = sig_to_rsni[signal]; + else + rsni = 2 * (signal + 10); + + return rsni; +} + +void phydm_ccx_hw_restart(void *dm_void) + /*@Will Restart NHM/CLM/FAHM simultaneously*/ +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg1 = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + reg1 = R_0x1e60; + #endif + else + reg1 = R_0x890; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + /*@disable NHM,CLM, FAHM*/ + odm_set_bb_reg(dm, reg1, 0x7, 0x0); + odm_set_bb_reg(dm, reg1, BIT(8), 0x0); + odm_set_bb_reg(dm, reg1, BIT(8), 0x1); +} + +u8 phydm_ccx_get_rpt_ratio(void *dm_void, u16 rpt, u16 denom) +{ + u32 numer = 0; + + numer = rpt * 100 + (denom >> 1); + + return (u8)PHYDM_DIV(numer, denom); +} + +#ifdef NHM_SUPPORT + +void phydm_nhm_racing_release(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32 = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->nhm_set_lv); + + ccx->nhm_ongoing = false; + ccx->nhm_set_lv = NHM_RELEASE; + + if (!(ccx->nhm_app == NHM_BACKGROUND || ccx->nhm_app == NHM_ACS)) { + phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, + PHYDM_PAUSE_LEVEL_1, 1, &value32); + } + + ccx->nhm_app = NHM_BACKGROUND; +} + +u8 phydm_nhm_racing_ctrl(void *dm_void, enum phydm_nhm_level nhm_lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*@acquire to control NHM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->nhm_ongoing, ccx->nhm_set_lv, nhm_lv); + if (ccx->nhm_ongoing) { + if (nhm_lv <= ccx->nhm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ccx_hw_restart(dm); + ccx->nhm_ongoing = false; + } + } + + if (set_result) + ccx->nhm_set_lv = nhm_lv; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm racing success=%d\n", set_result); + return set_result; +} + +void phydm_nhm_trigger(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 nhm_reg1 = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + nhm_reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + nhm_reg1 = R_0x1e60; + #endif + else + nhm_reg1 = R_0x890; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /* @Trigger NHM*/ + pdm_set_reg(dm, nhm_reg1, BIT(1), 0); + pdm_set_reg(dm, nhm_reg1, BIT(1), 1); + ccx->nhm_trigger_time = dm->phydm_sys_up_time; + ccx->nhm_rpt_stamp++; + ccx->nhm_ongoing = true; +} + +boolean +phydm_nhm_check_rdy(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_ready = false; + u32 reg1 = 0, reg1_bit = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = R_0xfb4; + reg1_bit = 16; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = R_0x2d4c; + reg1_bit = 16; + #endif + } else { + reg1 = R_0x8b4; + if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D | + ODM_RTL8710C)) + reg1_bit = 25; + else + reg1_bit = 17; + } + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) + is_ready = true; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM rdy=%d\n", is_ready); + + return is_ready; +} + +void phydm_nhm_cal_wgt(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 i = 0; + + for (i = 0; i < NHM_RPT_NUM; i++) { + if (i == 0) + ccx->nhm_wgt[0] = (u8)(MAX_2(ccx->nhm_th[0] - 2, 0)); + else if (i == (NHM_RPT_NUM - 1)) + ccx->nhm_wgt[NHM_RPT_NUM - 1] = (u8)(ccx->nhm_th[NHM_TH_NUM - 1] + 2); + else + ccx->nhm_wgt[i] = (u8)((ccx->nhm_th[i - 1] + ccx->nhm_th[i]) >> 1); + } +} + +u8 phydm_nhm_cal_wgt_avg(void *dm_void, u8 start_i, u8 end_i, u8 n_sum) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 i = 0; + u32 noise_tmp = 0; + u8 noise = 0; + u32 nhm_valid = 0; + + if (n_sum == 0) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "n_sum = 0, don't need to update noise\n"); + return 0x0; + } else if (end_i > NHM_RPT_NUM - 1) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[WARNING]end_i is larger than 11!!\n"); + return 0x0; + } + + for (i = start_i; i <= end_i; i++) + noise_tmp += ccx->nhm_result[i] * ccx->nhm_wgt[i]; + + /* protection for the case of minus noise(RSSI)*/ + noise = (u8)(NTH_TH_2_RSSI(MAX_2(PHYDM_DIV(noise_tmp, n_sum), 20))); + nhm_valid = (n_sum * 100) >> 8; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "cal wgt_avg : valid: ((%d)) percent, noise(RSSI)=((%d))\n", + nhm_valid, noise); + + return noise; +} + +u8 phydm_nhm_cal_nhm_env(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 first_idx = 0; + u8 nhm_env = 0; + u8 i = 0; + + nhm_env = ccx->nhm_rpt_sum; + + /*search first cluster*/ + for (i = 0; i < NHM_RPT_NUM; i++) { + if (ccx->nhm_result[i]) { + first_idx = i; + break; + } + } + + /*exclude first cluster under -80dBm*/ + for (i = 0; i < 4; i++) { + if (((first_idx + i) < NHM_RPT_NUM) && + (ccx->nhm_wgt[first_idx + i] <= NHM_IC_NOISE_TH)) + nhm_env -= ccx->nhm_result[first_idx + i]; + } + + /*exclude nhm_rpt[0] above -80dBm*/ + if (ccx->nhm_wgt[0] > NHM_IC_NOISE_TH) + nhm_env -= ccx->nhm_result[0]; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "cal nhm_env: first_idx=%d, nhm_env=%d\n", + first_idx, nhm_env); + + return nhm_env; +} + +void phydm_nhm_get_utility(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 nhm_rpt_non_0 = 0; + u8 nhm_rpt_non_11 = 0; + u8 nhm_env = 0; + + if (ccx->nhm_rpt_sum >= ccx->nhm_result[0]) { + phydm_nhm_cal_wgt(dm); + + nhm_rpt_non_0 = ccx->nhm_rpt_sum - ccx->nhm_result[0]; + nhm_rpt_non_11 = ccx->nhm_rpt_sum - ccx->nhm_result[11]; + /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ + nhm_env = phydm_nhm_cal_nhm_env(dm); + ccx->nhm_ratio = phydm_ccx_get_rpt_ratio(dm, nhm_rpt_non_0, + NHM_RPT_MAX); + ccx->nhm_env_ratio = phydm_ccx_get_rpt_ratio(dm, nhm_env, + NHM_RPT_MAX); + ccx->nhm_level_valid = phydm_ccx_get_rpt_ratio(dm, + nhm_rpt_non_11, NHM_RPT_MAX); + ccx->nhm_level = phydm_nhm_cal_wgt_avg(dm, 0, NHM_RPT_NUM - 2, + nhm_rpt_non_11); + ccx->nhm_pwr = phydm_nhm_cal_wgt_avg(dm, 0, NHM_RPT_NUM - 1, + ccx->nhm_rpt_sum); + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] nhm_rpt_sum invalid\n"); + ccx->nhm_ratio = 0; + ccx->nhm_env_ratio = 0; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "nhm_ratio=%d, nhm_env_ratio=%d, nhm_level=%d, nhm_pwr=%d\n", + ccx->nhm_ratio, ccx->nhm_env_ratio, ccx->nhm_level, + ccx->nhm_pwr); +} + +boolean +phydm_nhm_get_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32 = 0; + u8 i = 0; + u32 nhm_reg1 = 0; + u16 nhm_rpt_sum_tmp = 0; + u16 nhm_duration = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + nhm_reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + nhm_reg1 = R_0x1e60; + #endif + else + nhm_reg1 = R_0x890; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G | ODM_RTL8723F))) + pdm_set_reg(dm, nhm_reg1, BIT(1), 0); + + if (!(phydm_nhm_check_rdy(dm))) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM report Fail\n"); + phydm_nhm_racing_release(dm); + return false; + } + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + value32 = odm_read_4byte(dm, R_0xfa8); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, R_0xfac); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_read_4byte(dm, R_0xfb0); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4); + + /*@Get NHM duration*/ + value32 = odm_read_4byte(dm, R_0xfb4); + nhm_duration = (u16)(value32 & MASKLWORD); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + value32 = odm_read_4byte(dm, R_0x2d40); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, R_0x2d44); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_read_4byte(dm, R_0x2d48); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 4); + + /*@Get NHM duration*/ + value32 = odm_read_4byte(dm, R_0x2d4c); + nhm_duration = (u16)(value32 & MASKLWORD); + #endif + } else { + value32 = odm_read_4byte(dm, R_0x8d8); + odm_move_memory(dm, &ccx->nhm_result[0], &value32, 4); + + value32 = odm_read_4byte(dm, R_0x8dc); + odm_move_memory(dm, &ccx->nhm_result[4], &value32, 4); + + value32 = odm_get_bb_reg(dm, R_0x8d0, 0xffff0000); + odm_move_memory(dm, &ccx->nhm_result[8], &value32, 2); + + value32 = odm_read_4byte(dm, R_0x8d4); + + ccx->nhm_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx->nhm_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + + /*@Get NHM duration*/ + nhm_duration = (u16)(value32 & MASKLWORD); + } + + /* sum all nhm_result */ + if (ccx->nhm_period >= 65530) + PHYDM_DBG(dm, DBG_ENV_MNTR, + "NHM valid time = %d, valid: %d percent\n", + nhm_duration, (nhm_duration * 100) >> 16); + + for (i = 0; i < NHM_RPT_NUM; i++) + nhm_rpt_sum_tmp = (u16)(nhm_rpt_sum_tmp + ccx->nhm_result[i]); + + ccx->nhm_rpt_sum = (u8)nhm_rpt_sum_tmp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "NHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->nhm_rpt_stamp, ccx->nhm_result[11], ccx->nhm_result[10], + ccx->nhm_result[9], ccx->nhm_result[8], ccx->nhm_result[7], + ccx->nhm_result[6], ccx->nhm_result[5], ccx->nhm_result[4], + ccx->nhm_result[3], ccx->nhm_result[2], ccx->nhm_result[1], + ccx->nhm_result[0]); + + phydm_nhm_racing_release(dm); + + if (nhm_rpt_sum_tmp > 255) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[Warning] Invalid NHM RPT, total=%d\n", + nhm_rpt_sum_tmp); + return false; + } + + return true; +} + +void phydm_nhm_set_th_reg(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg1 = 0, reg2 = 0, reg3 = 0, reg4 = 0, reg4_bit = 0; + u32 val = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = R_0x994; + reg2 = R_0x998; + reg3 = R_0x99c; + reg4 = R_0x9a0; + reg4_bit = MASKBYTE0; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = R_0x1e60; + reg2 = R_0x1e44; + reg3 = R_0x1e48; + reg4 = R_0x1e5c; + reg4_bit = MASKBYTE2; + #endif + } else { + reg1 = R_0x890; + reg2 = R_0x898; + reg3 = R_0x89c; + reg4 = R_0xe28; + reg4_bit = MASKBYTE0; + } + + /*Set NHM threshold*/ /*Unit: PWdB U(8,1)*/ + val = BYTE_2_DWORD(ccx->nhm_th[3], ccx->nhm_th[2], + ccx->nhm_th[1], ccx->nhm_th[0]); + pdm_set_reg(dm, reg2, MASKDWORD, val); + val = BYTE_2_DWORD(ccx->nhm_th[7], ccx->nhm_th[6], + ccx->nhm_th[5], ccx->nhm_th[4]); + pdm_set_reg(dm, reg3, MASKDWORD, val); + pdm_set_reg(dm, reg4, reg4_bit, ccx->nhm_th[8]); + val = BYTE_2_DWORD(0, 0, ccx->nhm_th[10], ccx->nhm_th[9]); + pdm_set_reg(dm, reg1, 0xffff0000, val); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update NHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->nhm_th[10], ccx->nhm_th[9], ccx->nhm_th[8], + ccx->nhm_th[7], ccx->nhm_th[6], ccx->nhm_th[5], + ccx->nhm_th[4], ccx->nhm_th[3], ccx->nhm_th[2], + ccx->nhm_th[1], ccx->nhm_th[0]); +} + +boolean +phydm_nhm_th_update_chk(void *dm_void, enum nhm_application nhm_app, u8 *nhm_th, + u32 *igi_new, boolean en_1db_mode, u8 nhm_th0_manual) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean is_update = false; + u8 igi_curr = phydm_get_igi(dm, BB_PATH_A); + u8 nhm_igi_th_11k_low[NHM_TH_NUM] = {0x12, 0x15, 0x18, 0x1b, 0x1e, + 0x23, 0x28, 0x2c, 0x78, + 0x78, 0x78}; + u8 nhm_igi_th_11k_high[NHM_TH_NUM] = {0x1e, 0x23, 0x28, 0x2d, 0x32, + 0x37, 0x78, 0x78, 0x78, 0x78, + 0x78}; + u8 nhm_igi_th_xbox[NHM_TH_NUM] = {0x1a, 0x2c, 0x2e, 0x30, 0x32, 0x34, + 0x36, 0x38, 0x3a, 0x3c, 0x3d}; + u8 i = 0; + u8 th_tmp = igi_curr - CCA_CAP; + u8 th_step = 2; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, nhm_igi=0x%x, igi_curr=0x%x\n", + nhm_app, ccx->nhm_igi, igi_curr); + + if (igi_curr < 0x10) /* Protect for invalid IGI*/ + return false; + + switch (nhm_app) { + case NHM_BACKGROUND: /* @Get IGI form driver parameter(cur_ig_value)*/ + if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + + #ifdef NHM_DYM_PW_TH_SUPPORT + if (ccx->nhm_dym_pw_th_en) { + th_tmp = MAX_2(igi_curr - DYM_PWTH_CCA_CAP, 0); + th_step = 3; + } + #endif + + nhm_th[0] = (u8)IGI_2_NHM_TH(th_tmp); + + for (i = 1; i <= 10; i++) + nhm_th[i] = nhm_th[0] + + IGI_2_NHM_TH(th_step * i); + + } + break; + + case NHM_ACS: + if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP); + for (i = 1; i <= 10; i++) + nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(2 * i); + } + break; + + case IEEE_11K_HIGH: + is_update = true; + *igi_new = 0x2c; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_high[i]); + break; + + case IEEE_11K_LOW: + is_update = true; + *igi_new = 0x20; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_11k_low[i]); + break; + + case INTEL_XBOX: + is_update = true; + *igi_new = 0x36; + for (i = 0; i < NHM_TH_NUM; i++) + nhm_th[i] = IGI_2_NHM_TH(nhm_igi_th_xbox[i]); + break; + + case NHM_DBG: /*@Get IGI form register*/ + igi_curr = phydm_get_igi(dm, BB_PATH_A); + if (ccx->nhm_igi != igi_curr || ccx->nhm_app != nhm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + if (en_1db_mode) { + nhm_th[0] = (u8)IGI_2_NHM_TH(nhm_th0_manual + + 10); + th_step = 1; + } else { + nhm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - + CCA_CAP); + } + + for (i = 1; i <= 10; i++) + nhm_th[i] = nhm_th[0] + IGI_2_NHM_TH(th_step * + i); + } + break; + } + + if (is_update) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update NHM_TH] igi_RSSI=%d\n", + IGI_2_RSSI(*igi_new)); + + for (i = 0; i < NHM_TH_NUM; i++) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM_th[%d](RSSI) = %d\n", + i, NTH_TH_2_RSSI(nhm_th[i])); + } + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update NHM_TH\n"); + } + return is_update; +} + +void phydm_nhm_set(void *dm_void, enum nhm_option_txon_all include_tx, + enum nhm_option_cca_all include_cca, + enum nhm_divider_opt_all divi_opt, + enum nhm_application nhm_app, u16 period, + boolean en_1db_mode, u8 nhm_th0_manual) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 nhm_th[NHM_TH_NUM] = {0}; + u32 igi = 0x20; + u32 reg1 = 0, reg2 = 0; + u32 val_tmp = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "incld{tx, cca}={%d, %d}, divi_opt=%d, period=%d\n", + include_tx, include_cca, divi_opt, period); + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = R_0x994; + reg2 = R_0x990; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = R_0x1e60; + reg2 = R_0x1e40; + #endif + } else { + reg1 = R_0x890; + reg2 = R_0x894; + } + + /*Set disable_ignore_cca, disable_ignore_txon, ccx_en*/ + if (include_tx != ccx->nhm_include_txon || + include_cca != ccx->nhm_include_cca || + divi_opt != ccx->nhm_divider_opt) { + /* some old ic is not supported on NHM divider option */ + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B | + ODM_RTL8195A | ODM_RTL8192E)) { + val_tmp = (u32)((include_tx << 2) | + (include_cca << 1) | 1); + pdm_set_reg(dm, reg1, 0x700, val_tmp); + } else { + val_tmp = (u32)BIT_2_BYTE(divi_opt, include_tx, + include_cca, 1); + pdm_set_reg(dm, reg1, 0xf00, val_tmp); + } + ccx->nhm_include_txon = include_tx; + ccx->nhm_include_cca = include_cca; + ccx->nhm_divider_opt = divi_opt; + } + + /*Set NHM period*/ + if (period != ccx->nhm_period) { + pdm_set_reg(dm, reg2, MASKHWORD, period); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update NHM period ((%d)) -> ((%d))\n", + ccx->nhm_period, period); + + ccx->nhm_period = period; + } + + /*Set NHM threshold*/ + if (phydm_nhm_th_update_chk(dm, nhm_app, &nhm_th[0], &igi, + en_1db_mode, nhm_th0_manual)) { + /*Pause IGI*/ + if (nhm_app == NHM_BACKGROUND || nhm_app == NHM_ACS) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n"); + } else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, + PHYDM_PAUSE_LEVEL_1, 1, &igi) + == PAUSE_FAIL) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n"); + return; + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi); + } + ccx->nhm_app = nhm_app; + ccx->nhm_igi = (u8)igi; + odm_move_memory(dm, &ccx->nhm_th[0], &nhm_th, NHM_TH_NUM); + + /*Set NHM th*/ + phydm_nhm_set_th_reg(dm); + } +} + +boolean +phydm_nhm_mntr_set(void *dm_void, struct nhm_para_info *nhm_para) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 nhm_time = 0; /*unit: 4us*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (nhm_para->mntr_time == 0) + return false; + + if (nhm_para->nhm_lv >= NHM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", nhm_para->nhm_lv); + return false; + } + + if (phydm_nhm_racing_ctrl(dm, nhm_para->nhm_lv) == PHYDM_SET_FAIL) + return false; + + if (nhm_para->mntr_time >= 262) + nhm_time = NHM_PERIOD_MAX; + else + nhm_time = nhm_para->mntr_time * MS_TO_4US_RATIO; + + phydm_nhm_set(dm, nhm_para->incld_txon, nhm_para->incld_cca, + nhm_para->div_opt, nhm_para->nhm_app, nhm_time, + nhm_para->en_1db_mode, nhm_para->nhm_th0_manual); + + return true; +} + +#ifdef NHM_DYM_PW_TH_SUPPORT +void +phydm_nhm_restore_pw_th(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + odm_set_bb_reg(dm, R_0x82c, 0x3f, ccx->pw_th_rf20_ori); +} + +void +phydm_nhm_set_pw_th(void *dm_void, u8 noise, boolean chk_succ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean not_update = false; + u8 pw_th_rf20_new = 0; + u8 pw_th_u_bnd = 0; + s8 noise_diff = 0; + u8 point_mean = 15; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (*dm->band_width != CHANNEL_WIDTH_20 || + *dm->band_type == ODM_BAND_5G) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "bandwidth=((%d)), band=((%d))\n", + *dm->band_width, *dm->band_type); + phydm_nhm_restore_pw_th(dm); + return; + } + + if (chk_succ) { + noise_diff = noise - (ccx->nhm_igi - 10); + pw_th_u_bnd = (u8)(noise_diff + 32 + point_mean); + + pw_th_u_bnd = MIN_2(pw_th_u_bnd, ccx->nhm_pw_th_max); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "noise_diff=((%d)), max=((%d)), pw_th_u_bnd=((%d))\n", + noise_diff, ccx->nhm_pw_th_max, pw_th_u_bnd); + + if (pw_th_u_bnd > ccx->pw_th_rf20_cur) { + pw_th_rf20_new = ccx->pw_th_rf20_cur + 1; + } else if (pw_th_u_bnd < ccx->pw_th_rf20_cur) { + if (ccx->pw_th_rf20_cur > ccx->pw_th_rf20_ori) + pw_th_rf20_new = ccx->pw_th_rf20_cur - 1; + else /*ccx->pw_th_rf20_cur == ccx->pw_th_ori*/ + not_update = true; + } else {/*pw_th_u_bnd == ccx->pw_th_rf20_cur*/ + not_update = true; + } + } else { + if (ccx->pw_th_rf20_cur > ccx->pw_th_rf20_ori) + pw_th_rf20_new = ccx->pw_th_rf20_cur - 1; + else /*ccx->pw_th_rf20_cur == ccx->pw_th_ori*/ + not_update = true; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "pw_th_cur=((%d)), pw_th_new=((%d))\n", + ccx->pw_th_rf20_cur, pw_th_rf20_new); + + if (!not_update) { + odm_set_bb_reg(dm, R_0x82c, 0x3f, pw_th_rf20_new); + ccx->pw_th_rf20_cur = pw_th_rf20_new; + } +} + +void +phydm_nhm_dym_pw_th(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 i = 0; + u8 n_sum = 0; + u8 noise = 0; + boolean chk_succ = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + for (i = 0; i < NHM_RPT_NUM - 3; i++) { + n_sum = ccx->nhm_result[i] + ccx->nhm_result[i + 1] + + ccx->nhm_result[i + 2] + ccx->nhm_result[i + 3]; + if (n_sum >= ccx->nhm_sl_pw_th) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Do sl[%d:%d]\n", i, i + 3); + chk_succ = true; + noise = phydm_nhm_cal_wgt_avg(dm, i, i + 3, n_sum); + break; + } + } + + if (!chk_succ) + PHYDM_DBG(dm, DBG_ENV_MNTR, "SL method failed!\n"); + + phydm_nhm_set_pw_th(dm, noise, chk_succ); +} + +boolean +phydm_nhm_dym_pw_th_en(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct phydm_iot_center *iot_table = &dm->iot_table; + + if (!(dm->support_ic_type & ODM_RTL8822C)) + return false; + + if (ccx->dym_pwth_manual_ctrl) + return true; + + if (dm->iot_table.phydm_patch_id == 0x100f0401 || + iot_table->patch_id_100f0401) { + return true; + } else if (ccx->nhm_dym_pw_th_en) { + phydm_nhm_restore_pw_th(dm); + return false; + } else { + return false; + } +} +#endif + +/*Environment Monitor*/ +boolean +phydm_nhm_mntr_racing_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 sys_return_time = 0; + + if (ccx->nhm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "NHM in manual ctrl\n"); + return true; + } + + sys_return_time = ccx->nhm_trigger_time + MAX_ENV_MNTR_TIME; + + if (ccx->nhm_app != NHM_BACKGROUND && + (sys_return_time > dm->phydm_sys_up_time)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "nhm_app=%d, trigger_time %d, sys_time=%d\n", + ccx->nhm_app, ccx->nhm_trigger_time, + dm->phydm_sys_up_time); + + return true; + } + + return false; +} + +boolean +phydm_nhm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct nhm_para_info nhm_para = {0}; + boolean nhm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (phydm_nhm_mntr_racing_chk(dm)) + return nhm_chk_result; + + /*[NHM trigger setting]------------------------------------------*/ + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_BACKGROUND; + nhm_para.nhm_lv = NHM_LV_1; + nhm_para.en_1db_mode = false; + nhm_para.mntr_time = monitor_time; + + #ifdef NHM_DYM_PW_TH_SUPPORT + if (ccx->nhm_dym_pw_th_en) { + nhm_para.div_opt = NHM_VALID; + nhm_para.mntr_time = monitor_time >> ccx->nhm_period_decre; + } + #endif + + nhm_chk_result = phydm_nhm_mntr_set(dm, &nhm_para); + + return nhm_chk_result; +} + +boolean +phydm_nhm_mntr_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean nhm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (phydm_nhm_mntr_racing_chk(dm)) + return nhm_chk_result; + + /*[NHM get result & calculate Utility]---------------------------*/ + if (phydm_nhm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n"); + phydm_nhm_get_utility(dm); + nhm_chk_result = true; + } + + #ifdef NHM_DYM_PW_TH_SUPPORT + ccx->nhm_dym_pw_th_en = phydm_nhm_dym_pw_th_en(dm); + if (ccx->nhm_dym_pw_th_en) { + if (nhm_chk_result) + phydm_nhm_dym_pw_th(dm); + else + phydm_nhm_set_pw_th(dm, 0x0, false); + } + #endif + + return nhm_chk_result; +} + +void phydm_nhm_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "cur_igi=0x%x\n", + dm->dm_dig_table.cur_ig_value); + + ccx->nhm_app = NHM_BACKGROUND; + ccx->nhm_igi = 0xff; + + /*Set NHM threshold*/ + ccx->nhm_ongoing = false; + ccx->nhm_set_lv = NHM_RELEASE; + + if (phydm_nhm_th_update_chk(dm, ccx->nhm_app, &ccx->nhm_th[0], + (u32 *)&ccx->nhm_igi, false, 0)) + phydm_nhm_set_th_reg(dm); + + ccx->nhm_period = 0; + + ccx->nhm_include_cca = NHM_CCA_INIT; + ccx->nhm_include_txon = NHM_TXON_INIT; + ccx->nhm_divider_opt = NHM_CNT_INIT; + + ccx->nhm_manual_ctrl = 0; + ccx->nhm_rpt_stamp = 0; + + #ifdef NHM_DYM_PW_TH_SUPPORT + if (dm->support_ic_type & ODM_RTL8822C) { + ccx->nhm_dym_pw_th_en = false; + ccx->pw_th_rf20_ori = (u8)odm_get_bb_reg(dm, R_0x82c, 0x3f); + ccx->pw_th_rf20_cur = ccx->pw_th_rf20_ori; + ccx->nhm_pw_th_max = 63; + ccx->nhm_sl_pw_th = 100; /*39%*/ + ccx->nhm_period_decre = 1; + ccx->dym_pwth_manual_ctrl = false; + } + #endif +} + +void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct nhm_para_info nhm_para = {0}; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 result_tmp = 0; + u8 i = 0; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM Basic-Trigger 262ms: {1}\n"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM Adv-Trigger: {2} {Include TXON} {Include CCA}\n{0:Cnt_all, 1:Cnt valid} {App:5 for dbg} {LV:1~4} {0~262ms}, 1dB mode :{en} {t[0](RSSI)}\n"); + #ifdef NHM_DYM_PW_TH_SUPPORT + if (dm->support_ic_type & ODM_RTL8822C) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM dym_pw_th: {3} {0:off}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM dym_pw_th: {3} {1:on} {max} {period_decre} {sl_th}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM dym_pw_th: {3} {2:fast on}\n"); + } + #endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM Get Result: {100}\n"); + } else if (var1[0] == 100) { /*Get NHM results*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi, + ccx->nhm_rpt_stamp); + + if (phydm_nhm_get_result(dm)) { + for (i = 0; i < NHM_RPT_NUM; i++) { + result_tmp = ccx->nhm_result[i]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "nhm_rpt[%d] = %d (%d percent)\n", + i, result_tmp, + (((result_tmp * 100) + 128) >> 8)); + } + phydm_nhm_get_utility(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM_noise: valid: %d percent, noise(RSSI) = %d\n", + ccx->nhm_level_valid, ccx->nhm_level); + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM_pwr: nhm_pwr (RSSI) = %d\n", ccx->nhm_pwr); + PDM_SNPF(out_len, used, output + used, out_len - used, + "ratio: nhm_ratio=%d, nhm_env_ratio=%d\n", + ccx->nhm_ratio, ccx->nhm_env_ratio); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Get NHM_rpt Fail\n"); + } + ccx->nhm_manual_ctrl = 0; + #ifdef NHM_DYM_PW_TH_SUPPORT + } else if (var1[0] == 3) { /*NMH dym_pw_th*/ + if (dm->support_ic_type & ODM_RTL8822C) { + for (i = 1; i < 7; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + + if (var1[1] == 1) { + ccx->nhm_dym_pw_th_en = true; + ccx->nhm_pw_th_max = (u8)var1[2]; + ccx->nhm_period_decre = (u8)var1[3]; + ccx->nhm_sl_pw_th = (u8)var1[4]; + ccx->dym_pwth_manual_ctrl = true; + } else if (var1[1] == 2) { + ccx->nhm_dym_pw_th_en = true; + ccx->nhm_pw_th_max = 63; + ccx->nhm_period_decre = 1; + ccx->nhm_sl_pw_th = 100; + ccx->dym_pwth_manual_ctrl = true; + } else { + ccx->nhm_dym_pw_th_en = false; + phydm_nhm_restore_pw_th(dm); + ccx->dym_pwth_manual_ctrl = false; + } + } + #endif + } else { /*NMH trigger*/ + ccx->nhm_manual_ctrl = 1; + + for (i = 1; i < 9; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + + if (var1[0] == 1) { + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_DBG; + nhm_para.nhm_lv = NHM_LV_4; + nhm_para.mntr_time = 262; + nhm_para.en_1db_mode = false; + nhm_para.nhm_th0_manual = 0; + } else { + nhm_para.incld_txon = (enum nhm_option_txon_all)var1[1]; + nhm_para.incld_cca = (enum nhm_option_cca_all)var1[2]; + nhm_para.div_opt = (enum nhm_divider_opt_all)var1[3]; + nhm_para.nhm_app = (enum nhm_application)var1[4]; + nhm_para.nhm_lv = (enum phydm_nhm_level)var1[5]; + nhm_para.mntr_time = (u16)var1[6]; + nhm_para.en_1db_mode = (boolean)var1[7]; + nhm_para.nhm_th0_manual = (u8)var1[8]; + + /*some old ic is not supported on NHM divider option */ + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8723B | + ODM_RTL8195A | ODM_RTL8192E)) { + nhm_para.div_opt = NHM_CNT_ALL; + } + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "txon=%d, cca=%d, dev=%d, app=%d, lv=%d, time=%d ms\n", + nhm_para.incld_txon, nhm_para.incld_cca, + nhm_para.div_opt, nhm_para.nhm_app, + nhm_para.nhm_lv, nhm_para.mntr_time); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "en_1db_mode=%d, th0(for 1db mode)=%d\n", + nhm_para.en_1db_mode, nhm_para.nhm_th0_manual); + + if (phydm_nhm_mntr_set(dm, &nhm_para)) + phydm_nhm_trigger(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=0x%x, rpt_stamp=%d\n", ccx->nhm_igi, + ccx->nhm_rpt_stamp); + + for (i = 0; i < NHM_TH_NUM; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "NHM_th[%d] RSSI = %d\n", i, + NTH_TH_2_RSSI(ccx->nhm_th[i])); + } + } + + *_used = used; + *_out_len = out_len; +} + +#endif /*@#ifdef NHM_SUPPORT*/ + +#ifdef CLM_SUPPORT + +void phydm_clm_racing_release(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "lv:(%d)->(0)\n", ccx->clm_set_lv); + + ccx->clm_ongoing = false; + ccx->clm_set_lv = CLM_RELEASE; + ccx->clm_app = CLM_BACKGROUND; +} + +u8 phydm_clm_racing_ctrl(void *dm_void, enum phydm_clm_level clm_lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*@acquire to control CLM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->clm_ongoing, ccx->clm_set_lv, clm_lv); + if (ccx->clm_ongoing) { + if (clm_lv <= ccx->clm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ccx_hw_restart(dm); + ccx->clm_ongoing = false; + } + } + + if (set_result) + ccx->clm_set_lv = clm_lv; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm racing success=%d\n", set_result); + return set_result; +} + +void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u8 clm_report = cmd_buf[0]; + /*@u8 clm_report_idx = cmd_buf[1];*/ + + if (cmd_len >= 12) + return; + + ccx_info->clm_fw_result_acc += clm_report; + ccx_info->clm_fw_result_cnt++; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%d] clm_report= %d\n", + ccx_info->clm_fw_result_cnt, clm_report); +} + +void phydm_clm_h2c(void *dm_void, u16 obs_time, u8 fw_clm_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; + u8 i = 0; + u8 obs_time_idx = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "obs_time_index=%d *4 us\n", obs_time); + + for (i = 1; i <= 16; i++) { + if (obs_time & BIT(16 - i)) { + obs_time_idx = 16 - i; + break; + } + } +#if 0 + obs_time = (2 ^ 16 - 1)~(2 ^ 15) => obs_time_idx = 15 (65535 ~32768) + obs_time = (2 ^ 15 - 1)~(2 ^ 14) => obs_time_idx = 14 + ... + ... + ... + obs_time = (2 ^ 1 - 1)~(2 ^ 0) => obs_time_idx = 0 + +#endif + + h2c_val[0] = obs_time_idx | (((fw_clm_en) ? 1 : 0) << 7); + h2c_val[1] = CLM_MAX_REPORT_TIME; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "PHYDM h2c[0x4d]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], + h2c_val[1], h2c_val[0]); + + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_CLM_MNTR, H2C_MAX_LENGTH, h2c_val); +} + +void phydm_clm_setting(void *dm_void, u16 clm_period /*@4us sample 1 time*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + if (ccx->clm_period != clm_period) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(dm, R_0x990, MASKLWORD, clm_period); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0x1e40, MASKLWORD, clm_period); + #endif + else if (dm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(dm, R_0x894, MASKLWORD, clm_period); + + ccx->clm_period = clm_period; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update CLM period ((%d)) -> ((%d))\n", + ccx->clm_period, clm_period); + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "Set CLM period=%d * 4us\n", + ccx->clm_period); +} + +void phydm_clm_trigger(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg1 = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + reg1 = R_0x1e60; + #endif + else + reg1 = R_0x890; + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + odm_set_bb_reg(dm, reg1, BIT(0), 0x0); + odm_set_bb_reg(dm, reg1, BIT(0), 0x1); + + ccx->clm_trigger_time = dm->phydm_sys_up_time; + ccx->clm_rpt_stamp++; + ccx->clm_ongoing = true; +} + +boolean +phydm_clm_check_rdy(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_ready = false; + u32 reg1 = 0, reg1_bit = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + reg1 = R_0xfa4; + reg1_bit = 16; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + reg1 = R_0x2d88; + reg1_bit = 16; + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (dm->support_ic_type & (ODM_RTL8710B | ODM_RTL8721D | + ODM_RTL8710C)) { + reg1 = R_0x8b4; + reg1_bit = 24; + } else { + reg1 = R_0x8b4; + reg1_bit = 16; + } + } + if (odm_get_bb_reg(dm, reg1, BIT(reg1_bit))) + is_ready = true; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM rdy=%d\n", is_ready); + + return is_ready; +} + +void phydm_clm_get_utility(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + if (ccx->clm_period == 0) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[warning] clm_period = 0\n"); + ccx->clm_ratio = 0; + } else { + ccx->clm_ratio = phydm_ccx_get_rpt_ratio(dm, ccx->clm_result, + ccx->clm_period); + } +} + +boolean +phydm_clm_get_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + u32 reg1 = 0; + u32 val = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + reg1 = R_0x994; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + reg1 = R_0x1e60; + #endif + else + reg1 = R_0x890; + if (!(dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G | ODM_RTL8723F))) + odm_set_bb_reg(dm, reg1, BIT(0), 0x0); + if (!(phydm_clm_check_rdy(dm))) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM report Fail\n"); + phydm_clm_racing_release(dm); + return false; + } + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + val = odm_get_bb_reg(dm, R_0xfa4, MASKLWORD); + ccx_info->clm_result = (u16)val; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + val = odm_get_bb_reg(dm, R_0x2d88, MASKLWORD); + ccx_info->clm_result = (u16)val; + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + val = odm_get_bb_reg(dm, R_0x8d0, MASKLWORD); + ccx_info->clm_result = (u16)val; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM result = %d *4 us\n", + ccx_info->clm_result); + phydm_clm_racing_release(dm); + return true; +} + +boolean +phydm_clm_mntr_set(void *dm_void, struct clm_para_info *clm_para) +{ + /*@Driver Monitor CLM*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u16 clm_period = 0; + + if (clm_para->mntr_time == 0) + return false; + + if (clm_para->clm_lv >= CLM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[WARNING] Wrong LV=%d\n", + clm_para->clm_lv); + return false; + } + + if (phydm_clm_racing_ctrl(dm, clm_para->clm_lv) == PHYDM_SET_FAIL) + return false; + + if (clm_para->mntr_time >= 262) + clm_period = CLM_PERIOD_MAX; + else + clm_period = clm_para->mntr_time * MS_TO_4US_RATIO; + + ccx->clm_app = clm_para->clm_app; + phydm_clm_setting(dm, clm_period); + + return true; +} + +boolean +phydm_clm_mntr_racing_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 sys_return_time = 0; + + if (ccx->clm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "CLM in manual ctrl\n"); + return true; + } + + sys_return_time = ccx->clm_trigger_time + MAX_ENV_MNTR_TIME; + + if (ccx->clm_app != CLM_BACKGROUND && + (sys_return_time > dm->phydm_sys_up_time)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "clm_app=%d, trigger_time %d, sys_time=%d\n", + ccx->clm_app, ccx->clm_trigger_time, + dm->phydm_sys_up_time); + + return true; + } + + return false; +} + +boolean +phydm_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct clm_para_info clm_para = {0}; + boolean clm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + + if (phydm_clm_mntr_racing_chk(dm)) + return clm_chk_result; + + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_1; + clm_para.mntr_time = monitor_time; + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + if (phydm_clm_mntr_set(dm, &clm_para)) + clm_chk_result = true; + } else { + if (monitor_time >= 262) + ccx->clm_period = 65535; + else + ccx->clm_period = monitor_time * MS_TO_4US_RATIO; + + phydm_clm_h2c(dm, ccx->clm_period, true); + } + + return clm_chk_result; +} + +boolean +phydm_clm_mntr_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean clm_chk_result = false; + u32 val = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + + if (phydm_clm_mntr_racing_chk(dm)) + return clm_chk_result; + + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + if (phydm_clm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n"); + phydm_clm_get_utility(dm); + clm_chk_result = true; + } + } else { + if (ccx->clm_fw_result_cnt != 0) { + val = ccx->clm_fw_result_acc / ccx->clm_fw_result_cnt; + ccx->clm_ratio = (u8)val; + clm_chk_result = true; + } else { + ccx->clm_ratio = 0; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt); + + ccx->clm_fw_result_acc = 0; + ccx->clm_fw_result_cnt = 0; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "clm_ratio=%d\n", ccx->clm_ratio); + + return clm_chk_result; +} + +void phydm_set_clm_mntr_mode(void *dm_void, enum clm_monitor_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx_info = &dm->dm_ccx_info; + + if (ccx_info->clm_mntr_mode != mode) { + ccx_info->clm_mntr_mode = mode; + phydm_ccx_hw_restart(dm); + + if (mode == CLM_DRIVER_MNTR) + phydm_clm_h2c(dm, CLM_PERIOD_MAX, 0); + } +} + +void phydm_clm_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + ccx->clm_ongoing = false; + ccx->clm_manual_ctrl = 0; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + ccx->clm_period = 0; + ccx->clm_rpt_stamp = 0; + phydm_clm_setting(dm, 65535); +} + +void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct clm_para_info clm_para = {0}; + u32 i; + + for (i = 0; i < 4; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM Driver Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM Driver Adv-Trigger: {2} {app} {LV} {0~262ms}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM FW Trigger: {3} {1:drv, 2:fw}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM Get Result: {100}\n"); + } else if (var1[0] == 100) { /* @Get CLM results */ + + if (phydm_clm_get_result(dm)) + phydm_clm_get_utility(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "clm_ratio:((%d percent)) = (%d us/ %d us)\n", + ccx->clm_ratio, ccx->clm_result << 2, + ccx->clm_period << 2); + + ccx->clm_manual_ctrl = 0; + } else if (var1[0] == 3) { + phydm_set_clm_mntr_mode(dm, (enum clm_monitor_mode)var1[1]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CLM mode: %s mode\n", + ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" : "Drv")); + } else { /* Set & trigger CLM */ + ccx->clm_manual_ctrl = 1; + + if (var1[0] == 1) { + clm_para.clm_app = CLM_BACKGROUND; + clm_para.clm_lv = CLM_LV_4; + clm_para.mntr_time = 262; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + } else if (var1[0] == 2) { + clm_para.clm_app = (enum clm_application)var1[1]; + clm_para.clm_lv = (enum phydm_clm_level)var1[2]; + ccx->clm_mntr_mode = CLM_DRIVER_MNTR; + clm_para.mntr_time = (u16)var1[3]; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, mode=%s, time=%d ms\n", + clm_para.clm_app, clm_para.clm_lv, + ((ccx->clm_mntr_mode == CLM_FW_MNTR) ? "FW" : + "driver"), clm_para.mntr_time); + + if (phydm_clm_mntr_set(dm, &clm_para)) + phydm_clm_trigger(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "clm_rpt_stamp=%d\n", ccx->clm_rpt_stamp); + } + + *_used = used; + *_out_len = out_len; +} + +#endif /*@#ifdef CLM_SUPPORT*/ + +u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct env_trig_rpt *trig_rpt) +{ + u8 trigger_result = 0; +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean nhm_set_ok = false; + boolean clm_set_ok = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + + /*@[NHM]*/ + nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para); + + /*@[CLM]*/ + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + clm_set_ok = phydm_clm_mntr_set(dm, clm_para); + } else if (ccx->clm_mntr_mode == CLM_FW_MNTR) { + phydm_clm_h2c(dm, CLM_PERIOD_MAX, true); + trigger_result |= CLM_SUCCESS; + } + + if (nhm_set_ok) { + phydm_nhm_trigger(dm); + trigger_result |= NHM_SUCCESS; + } + + if (clm_set_ok) { + phydm_clm_trigger(dm); + trigger_result |= CLM_SUCCESS; + } + + /*@monitor for the test duration*/ + ccx->start_time = odm_get_current_time(dm); + + trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n\n", + trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp); +#endif + return trigger_result; +} + +u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt) +{ + u8 env_mntr_rpt = 0; +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u64 progressing_time = 0; + u32 val_tmp = 0; + + /*@monitor for the test duration*/ + progressing_time = odm_get_progressing_time(dm, ccx->start_time); + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "env_time=%lld\n", progressing_time); + + /*@Get NHM result*/ + if (phydm_nhm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n"); + phydm_nhm_get_utility(dm); + rpt->nhm_ratio = ccx->nhm_ratio; + rpt->nhm_env_ratio = ccx->nhm_env_ratio; + rpt->nhm_noise_pwr = ccx->nhm_level; + rpt->nhm_pwr = ccx->nhm_pwr; + env_mntr_rpt |= NHM_SUCCESS; + + odm_move_memory(dm, &rpt->nhm_result[0], + &ccx->nhm_result[0], NHM_RPT_NUM); + } else { + rpt->nhm_ratio = ENV_MNTR_FAIL; + rpt->nhm_env_ratio = ENV_MNTR_FAIL; + } + + /*@Get CLM result*/ + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + if (phydm_clm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n"); + phydm_clm_get_utility(dm); + env_mntr_rpt |= CLM_SUCCESS; + rpt->clm_ratio = ccx->clm_ratio; + } else { + rpt->clm_ratio = ENV_MNTR_FAIL; + } + + } else { + if (ccx->clm_fw_result_cnt != 0) { + val_tmp = ccx->clm_fw_result_acc + / ccx->clm_fw_result_cnt; + ccx->clm_ratio = (u8)val_tmp; + } else { + ccx->clm_ratio = 0; + } + + rpt->clm_ratio = ccx->clm_ratio; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt); + + ccx->clm_fw_result_acc = 0; + ccx->clm_fw_result_cnt = 0; + env_mntr_rpt |= CLM_SUCCESS; + } + + rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "IGI=0x%x, nhm_ratio=%d, nhm_env_ratio=%d, clm_ratio=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n\n", + ccx->nhm_igi, rpt->nhm_ratio, rpt->nhm_env_ratio, + rpt->clm_ratio, rpt->nhm_rpt_stamp, rpt->clm_rpt_stamp); +#endif + return env_mntr_rpt; +} + +void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct clm_para_info clm_para = {0}; + struct nhm_para_info nhm_para = {0}; + struct env_mntr_rpt rpt = {0}; + struct env_trig_rpt trig_rpt = {0}; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = 0; + u8 i = 0; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Get Result: {100}\n"); + } else if (var1[0] == 100) { /* Get results */ + set_result = phydm_env_mntr_result(dm, &rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Result=%d\n nhm_ratio=%d nhm_env_ratio=%d clm_ratio=%d\n nhm_rpt_stamp=%d, clm_rpt_stamp=%d,\n", + set_result, rpt.nhm_ratio, rpt.nhm_env_ratio, + rpt.clm_ratio, rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp); + + for (i = 0; i <= 11; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "nhm_rpt[%d] = %d (%d percent)\n", i, + rpt.nhm_result[i], + (((rpt.nhm_result[i] * 100) + 128) >> 8)); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "[NHM] valid: %d percent, noise(RSSI) = %d\n", + ccx->nhm_level_valid, ccx->nhm_level); + } else { /* Set & trigger*/ + /*nhm para*/ + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_ACS; + nhm_para.nhm_lv = NHM_LV_2; + nhm_para.mntr_time = 262; + nhm_para.en_1db_mode = false; + + /*clm para*/ + clm_para.clm_app = CLM_ACS; + clm_para.clm_lv = CLM_LV_2; + clm_para.mntr_time = 262; + + set_result = phydm_env_mntr_trigger(dm, &nhm_para, + &clm_para, &trig_rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Result=%d, nhm_rpt_stamp=%d, clm_rpt_stamp=%d\n", + set_result, trig_rpt.nhm_rpt_stamp, + trig_rpt.clm_rpt_stamp); + } + + *_used = used; + *_out_len = out_len; +} + +#ifdef FAHM_SUPPORT + +void phydm_fahm_racing_release(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32 = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_racing_release : lv:(%d)->(0)\n", + ccx->fahm_set_lv); + + ccx->fahm_ongoing = false; + ccx->fahm_set_lv = FAHM_RELEASE; + + if (!(ccx->fahm_app == FAHM_BACKGROUND || ccx->fahm_app == FAHM_ACS)) + phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, + PHYDM_PAUSE_LEVEL_1, 1, &value32); + + ccx->fahm_app = FAHM_BACKGROUND; +} + +u8 phydm_fahm_racing_ctrl(void *dm_void, enum phydm_fahm_level lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*acquire to control FAHM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->fahm_ongoing, ccx->fahm_set_lv, lv); + if (ccx->fahm_ongoing) { + if (lv <= ccx->fahm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ccx_hw_restart(dm); + ccx->fahm_ongoing = false; + } + } + + if (set_result) + ccx->fahm_set_lv = lv; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm racing success=%d\n", set_result); + return set_result; +} + +void phydm_fahm_trigger(void *dm_void) +{ /*@unit (4us)*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + switch (dm->ic_ip_series) { + case PHYDM_IC_JGR3: + reg = R_0x1e60; + break; + case PHYDM_IC_AC: + reg = R_0x994; + break; + case PHYDM_IC_N: + reg = R_0x890; + break; + default: + break; + } + + odm_set_bb_reg(dm, reg, BIT(2), 0); + odm_set_bb_reg(dm, reg, BIT(2), 1); + + ccx->fahm_trigger_time = dm->phydm_sys_up_time; + ccx->fahm_rpt_stamp++; + ccx->fahm_ongoing = true; +} + +boolean +phydm_fahm_check_rdy(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean is_ready = false; + u32 reg = 0, reg_bit = 0; + + switch (dm->ic_ip_series) { + case PHYDM_IC_JGR3: + reg = R_0x2d84; + reg_bit = 31; + break; + case PHYDM_IC_AC: + reg = R_0x1f98; + reg_bit = 31; + break; + case PHYDM_IC_N: + reg = R_0x9f0; + reg_bit = 31; + break; + default: + break; + } + + if (odm_get_bb_reg(dm, reg, BIT(reg_bit))) + is_ready = true; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "FAHM rdy=%d\n", is_ready); + + return is_ready; +} + +u8 phydm_fahm_cal_wgt_avg(void *dm_void, u8 start_i, u8 end_i, u16 r_sum, + u16 period) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 i = 0; + u32 pwr_tmp = 0; + u8 pwr = 0; + u32 fahm_valid = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (r_sum == 0) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "rpt_sum = 0, don't need to update\n"); + return 0x0; + } else if (end_i > FAHM_RPT_NUM - 1) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[WARNING]end_i is larger than 11!!\n"); + return 0x0; + } + + for (i = start_i; i <= end_i; i++) { + if (i == 0) + pwr_tmp += ccx->fahm_result[0] * + MAX_2(ccx->fahm_th[0] - 2, 0); + else if (i == (FAHM_RPT_NUM - 1)) + pwr_tmp += ccx->fahm_result[FAHM_RPT_NUM - 1] * + (ccx->fahm_th[FAHM_TH_NUM - 1] + 2); + else + pwr_tmp += ccx->fahm_result[i] * + (ccx->fahm_th[i - 1] + ccx->fahm_th[i]) >> 1; + } + + /* protection for the case of minus pwr(RSSI)*/ + pwr = (u8)(NTH_TH_2_RSSI(MAX_2(PHYDM_DIV(pwr_tmp, r_sum), 20))); + fahm_valid = PHYDM_DIV(r_sum * 100, period); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "valid: ((%d)) percent, pwr(RSSI)=((%d))\n", + fahm_valid, pwr); + + return pwr; +} + +void phydm_fahm_get_utility(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + if (ccx->fahm_result_sum >= ccx->fahm_result[0]) { + ccx->fahm_pwr = phydm_fahm_cal_wgt_avg(dm, 0, FAHM_RPT_NUM - 1, + ccx->fahm_result_sum, + ccx->fahm_period); + ccx->fahm_ratio = phydm_ccx_get_rpt_ratio(dm, + ccx->fahm_result_sum, ccx->fahm_period); + ccx->fahm_denom_ratio = phydm_ccx_get_rpt_ratio(dm, + ccx->fahm_denom_result, + ccx->fahm_period); + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[warning] fahm_result_sum invalid\n"); + ccx->fahm_pwr = 0; + ccx->fahm_ratio = 0; + ccx->fahm_denom_ratio = 0; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "fahm_pwr=%d, fahm_ratio=%d, fahm_denom_ratio=%d\n", + ccx->fahm_pwr, ccx->fahm_ratio, ccx->fahm_denom_ratio); +} + +boolean +phydm_fahm_get_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32 = 0; + u32 reg1 = 0; + u32 reg2 = 0; + u8 i = 0; + u32 fahm_rpt_sum_tmp = 0; + + switch (dm->ic_ip_series) { + case PHYDM_IC_JGR3: + reg1 = R_0x2d6c; + reg2 = R_0x2d84; + break; + case PHYDM_IC_AC: + reg1 = R_0x1f80; + reg2 = R_0x1f98; + break; + case PHYDM_IC_N: + reg1 = R_0x9d8; + reg2 = R_0x9f0; + break; + default: + break; + } + + if (!(phydm_fahm_check_rdy(dm))) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get FAHM report Fail\n"); + phydm_fahm_racing_release(dm); + return false; + } + + /*Get FAHM numerator and sum all fahm_result*/ + for (i = 0; i < 6; i++) { + value32 = odm_get_bb_reg(dm, reg1 + (i << 2), MASKDWORD); + ccx->fahm_result[i * 2] = (u16)(value32 & MASKLWORD); + ccx->fahm_result[i * 2 + 1] = (u16)((value32 & MASKHWORD) >> 16); + fahm_rpt_sum_tmp = (u32)(fahm_rpt_sum_tmp + + ccx->fahm_result[i * 2] + + ccx->fahm_result[i * 2 + 1]); + } + ccx->fahm_result_sum = (u16)fahm_rpt_sum_tmp; + + /*Get FAHM Denominator*/ + ccx->fahm_denom_result = (u16)odm_get_bb_reg(dm, reg2, MASKLWORD); + + if (!(ccx->fahm_inclu_cck)) + PHYDM_DBG(dm, DBG_ENV_MNTR, + "===>The following fahm report does not count CCK pkt\n"); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "fahm_result_sum=%d, fahm_denom_result = %d\n", + ccx->fahm_result_sum, ccx->fahm_denom_result); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "FAHM_Rpt[%d](H->L)[%d %d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->fahm_rpt_stamp, ccx->fahm_result[11], + ccx->fahm_result[10], ccx->fahm_result[9], + ccx->fahm_result[8], ccx->fahm_result[7], ccx->fahm_result[6], + ccx->fahm_result[5], ccx->fahm_result[4], ccx->fahm_result[3], + ccx->fahm_result[2], ccx->fahm_result[1], + ccx->fahm_result[0]); + + phydm_fahm_racing_release(dm); + + if (fahm_rpt_sum_tmp > 0xffff) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[Warning] Invalid FAHM RPT, total=%d\n", + fahm_rpt_sum_tmp); + return false; + } + + return true; +} + +void phydm_fahm_set_th_reg(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 val = 0; + + /*Set FAHM threshold*/ /*Unit: PWdB U(8,1)*/ + switch (dm->ic_ip_series) { + case PHYDM_IC_JGR3: + val = BYTE_2_DWORD(ccx->fahm_th[3], ccx->fahm_th[2], + ccx->fahm_th[1], ccx->fahm_th[0]); + odm_set_bb_reg(dm, R_0x1e50, MASKDWORD, val); + val = BYTE_2_DWORD(ccx->fahm_th[7], ccx->fahm_th[6], + ccx->fahm_th[5], ccx->fahm_th[4]); + odm_set_bb_reg(dm, R_0x1e54, MASKDWORD, val); + val = BYTE_2_DWORD(0, ccx->fahm_th[10], ccx->fahm_th[9], + ccx->fahm_th[8]); + odm_set_bb_reg(dm, R_0x1e58, 0xffffff, val); + break; + case PHYDM_IC_AC: + val = BYTE_2_DWORD(0, ccx->fahm_th[2], ccx->fahm_th[1], + ccx->fahm_th[0]); + odm_set_bb_reg(dm, R_0x1c38, 0xffffff00, val); + val = BYTE_2_DWORD(0, ccx->fahm_th[5], ccx->fahm_th[4], + ccx->fahm_th[3]); + odm_set_bb_reg(dm, R_0x1c78, 0xffffff00, val); + val = BYTE_2_DWORD(0, 0, ccx->fahm_th[7], ccx->fahm_th[6]); + odm_set_bb_reg(dm, R_0x1c7c, 0xffff0000, val); + val = BYTE_2_DWORD(0, ccx->fahm_th[10], ccx->fahm_th[9], + ccx->fahm_th[8]); + odm_set_bb_reg(dm, R_0x1cb8, 0xffffff00, val); + break; + case PHYDM_IC_N: + val = BYTE_2_DWORD(ccx->fahm_th[3], ccx->fahm_th[2], + ccx->fahm_th[1], ccx->fahm_th[0]); + odm_set_bb_reg(dm, R_0x970, MASKDWORD, val); + val = BYTE_2_DWORD(ccx->fahm_th[7], ccx->fahm_th[6], + ccx->fahm_th[5], ccx->fahm_th[4]); + odm_set_bb_reg(dm, R_0x974, MASKDWORD, val); + val = BYTE_2_DWORD(0, ccx->fahm_th[10], ccx->fahm_th[9], + ccx->fahm_th[8]); + odm_set_bb_reg(dm, R_0x978, 0xffffff, val); + break; + default: + break; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update FAHM_th[H->L]=[%d %d %d %d %d %d %d %d %d %d %d]\n", + ccx->fahm_th[10], ccx->fahm_th[9], ccx->fahm_th[8], + ccx->fahm_th[7], ccx->fahm_th[6], ccx->fahm_th[5], + ccx->fahm_th[4], ccx->fahm_th[3], ccx->fahm_th[2], + ccx->fahm_th[1], ccx->fahm_th[0]); +} + +boolean +phydm_fahm_th_update_chk(void *dm_void, enum fahm_application fahm_app, + u8 *fahm_th, u32 *igi_new, boolean en_1db_mode, + u8 fahm_th0_manual) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean is_update = false; + u8 igi_curr = phydm_get_igi(dm, BB_PATH_A); + u8 i = 0; + u8 th_tmp = igi_curr - CCA_CAP; + u8 th_step = 2; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_th_update_chk : App=%d, fahm_igi=0x%x, igi_curr=0x%x\n", + fahm_app, ccx->fahm_igi, igi_curr); + + if (igi_curr < 0x10) /* Protect for invalid IGI*/ + return false; + + switch (fahm_app) { + case FAHM_BACKGROUND: /*Get IGI from driver parameter(cur_ig_value)*/ + if (ccx->fahm_igi != igi_curr || ccx->fahm_app != fahm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + + fahm_th[0] = (u8)IGI_2_NHM_TH(th_tmp); + + for (i = 1; i <= 10; i++) + fahm_th[i] = fahm_th[0] + + IGI_2_NHM_TH(th_step * i); + + } + break; + case FAHM_ACS: + if (ccx->fahm_igi != igi_curr || ccx->fahm_app != fahm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + fahm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - CCA_CAP); + for (i = 1; i <= 10; i++) + fahm_th[i] = fahm_th[0] + IGI_2_NHM_TH(2 * i); + } + break; + case FAHM_DBG: /*Get IGI from register*/ + igi_curr = phydm_get_igi(dm, BB_PATH_A); + if (ccx->fahm_igi != igi_curr || ccx->fahm_app != fahm_app) { + is_update = true; + *igi_new = (u32)igi_curr; + if (en_1db_mode) { + fahm_th[0] = (u8)IGI_2_NHM_TH(fahm_th0_manual + + 10); + th_step = 1; + } else { + fahm_th[0] = (u8)IGI_2_NHM_TH(igi_curr - + CCA_CAP); + } + + for (i = 1; i <= 10; i++) + fahm_th[i] = fahm_th[0] + + IGI_2_NHM_TH(th_step * i); + } + break; + } + + if (is_update) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update FAHM_TH] igi_RSSI=%d\n", + IGI_2_RSSI(*igi_new)); + + for (i = 0; i < FAHM_TH_NUM; i++) + PHYDM_DBG(dm, DBG_ENV_MNTR, "FAHM_th[%d](RSSI) = %d\n", + i, NTH_TH_2_RSSI(fahm_th[i])); + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update FAHM_TH\n"); + } + return is_update; +} + +void phydm_fahm_set(void *dm_void, u8 numer_opt, u8 denom_opt, + enum fahm_application app, u16 period, boolean en_1db_mode, + u8 th0_manual) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 fahm_th[FAHM_TH_NUM] = {0}; + u32 igi = 0x20; + u32 reg1 = 0, reg2 = 0, reg3 = 0; + u32 val_tmp = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "numer_opt=%d, denom_opt=%d, period=%d\n", + numer_opt, denom_opt, period); + + switch (dm->ic_ip_series) { + case PHYDM_IC_JGR3: + reg1 = R_0x1e60; + reg2 = R_0x1e58; + reg3 = R_0x1e5c; + break; + case PHYDM_IC_AC: + reg1 = R_0x994; + reg2 = R_0x1cf8; + break; + case PHYDM_IC_N: + reg1 = R_0x890; + reg2 = R_0x978; + reg3 = R_0x97c; + break; + default: + break; + } + + /*Set enable fa, ignore crc32 ok, ignore crc32 err*/ + if (numer_opt != ccx->fahm_numer_opt || + denom_opt != ccx->fahm_denom_opt) { + odm_set_bb_reg(dm, reg1, 0xe0, numer_opt); + odm_set_bb_reg(dm, reg1, 0x7000, denom_opt); + ccx->fahm_numer_opt = numer_opt; + ccx->fahm_denom_opt = denom_opt; + + /*[PHYDM-400]*/ + /*Counting B mode pkt for new B mode IP or fahm_opt is non-FA*/ + if ((dm->support_ic_type & ODM_RTL8723F) || + (((numer_opt | denom_opt) & FAHM_INCLU_FA) == 0)) + ccx->fahm_inclu_cck = true; + else + ccx->fahm_inclu_cck = false; + + odm_set_bb_reg(dm, reg1, BIT(4), ccx->fahm_inclu_cck); + PHYDM_DBG(dm, DBG_ENV_MNTR, "fahm_inclu_cck=%d\n", + ccx->fahm_inclu_cck); + } + + /*Set FAHM period*/ + if (period != ccx->fahm_period) { + switch (dm->ic_ip_series) { + case PHYDM_IC_AC: + odm_set_bb_reg(dm, reg2, 0xffff00, period); + break; + case PHYDM_IC_JGR3: + case PHYDM_IC_N: + odm_set_bb_reg(dm, reg2, 0xff000000, (period & 0xff)); + odm_set_bb_reg(dm, reg3, 0xff, (period & 0xff00) >> 8); + break; + default: + break; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update FAHM period ((%d)) -> ((%d))\n", + ccx->fahm_period, period); + + ccx->fahm_period = period; + } + + /*Set FAHM threshold*/ + if (phydm_fahm_th_update_chk(dm, app, &fahm_th[0], &igi, en_1db_mode, + th0_manual)) { + /*Pause IGI*/ + if (app == FAHM_BACKGROUND || app == FAHM_ACS) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "DIG Free Run\n"); + } else if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, + PHYDM_PAUSE_LEVEL_1, 1, &igi) + == PAUSE_FAIL) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG Fail\n"); + return; + } else { + PHYDM_DBG(dm, DBG_ENV_MNTR, "pause DIG=0x%x\n", igi); + } + ccx->fahm_app = app; + ccx->fahm_igi = (u8)igi; + odm_move_memory(dm, &ccx->fahm_th[0], &fahm_th, FAHM_TH_NUM); + + /*Set FAHM th*/ + phydm_fahm_set_th_reg(dm); + } +} + +boolean +phydm_fahm_mntr_set(void *dm_void, struct fahm_para_info *para) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 fahm_time = 0; /*unit: 4us*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (para->mntr_time == 0) + return false; + + if (para->lv >= FAHM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", para->lv); + return false; + } + + if (phydm_fahm_racing_ctrl(dm, para->lv) == PHYDM_SET_FAIL) + return false; + + if (para->mntr_time >= 262) + fahm_time = FAHM_PERIOD_MAX; + else + fahm_time = para->mntr_time * MS_TO_4US_RATIO; + + phydm_fahm_set(dm, para->numer_opt, para->denom_opt, para->app, + fahm_time, para->en_1db_mode, para->th0_manual); + + return true; +} + +boolean +phydm_fahm_mntr_racing_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 sys_return_time = 0; + + if (ccx->fahm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "FAHM in manual ctrl\n"); + return true; + } + + sys_return_time = ccx->fahm_trigger_time + MAX_ENV_MNTR_TIME; + + if (ccx->fahm_app != FAHM_BACKGROUND && + (sys_return_time > dm->phydm_sys_up_time)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "fahm_app=%d, trigger_time %d, sys_time=%d\n", + ccx->fahm_app, ccx->fahm_trigger_time, + dm->phydm_sys_up_time); + + return true; + } + + return false; +} + +boolean +phydm_fahm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct fahm_para_info para = {0}; + boolean fahm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (phydm_fahm_mntr_racing_chk(dm)) + return fahm_chk_result; + + /*[FAHM trigger setting]------------------------------------------*/ + para.numer_opt = FAHM_INCLU_FA; + para.denom_opt = FAHM_INCLU_CRC_ERR; + para.app = FAHM_BACKGROUND; + para.lv = FAHM_LV_1; + para.en_1db_mode = false; + para.mntr_time = monitor_time; + + fahm_chk_result = phydm_fahm_mntr_set(dm, ¶); + + return fahm_chk_result; +} + +boolean +phydm_fahm_mntr_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean fahm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (phydm_fahm_mntr_racing_chk(dm)) + return fahm_chk_result; + + /*[FAHM get result & calculate Utility]---------------------------*/ + if (phydm_fahm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get FAHM_rpt success\n"); + phydm_fahm_get_utility(dm); + fahm_chk_result = true; + } + + return fahm_chk_result; +} + +void phydm_fahm_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 reg = 0; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM)) + return; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + ccx->fahm_app = FAHM_BACKGROUND; + ccx->fahm_igi = 0xff; + + /*Set FAHM threshold*/ + ccx->fahm_ongoing = false; + ccx->fahm_set_lv = FAHM_RELEASE; + + if (phydm_fahm_th_update_chk(dm, ccx->fahm_app, &ccx->fahm_th[0], + (u32 *)&ccx->fahm_igi, false, 0)) + phydm_fahm_set_th_reg(dm); + + ccx->fahm_period = 0; + ccx->fahm_numer_opt = 0; + ccx->fahm_denom_opt = 0; + ccx->fahm_manual_ctrl = 0; + ccx->fahm_rpt_stamp = 0; + ccx->fahm_inclu_cck = false; + + switch (dm->ic_ip_series) { + case PHYDM_IC_JGR3: + reg = R_0x1e60; + break; + case PHYDM_IC_AC: + reg = R_0x994; + break; + case PHYDM_IC_N: + reg = R_0x890; + break; + default: + break; + } + + /*Counting OFDM pkt*/ + odm_set_bb_reg(dm, reg, BIT(3), 1); +} + +void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct fahm_para_info para = {0}; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u16 result_tmp = 0; + u8 i = 0; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM)) + return; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "FAHM Basic-Trigger 262ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "FAHM Adv-Trigger: {2} {numer_opt} {denom_opt}\n {App:1 for dbg} {LV:1~4} {0~262ms}, 1dB mode :{en} {t[0](RSSI)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "FAHM Get Result: {100}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "numer_opt/denom_opt: {BIT 0/1/2} = {FA/CRC32_OK/CRC32_ERR}\n"); + } else if (var1[0] == 100) { /*Get FAHM results*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=0x%x, rpt_stamp=%d\n", ccx->fahm_igi, + ccx->fahm_rpt_stamp); + + if (phydm_fahm_get_result(dm)) { + if (!(ccx->fahm_inclu_cck)) + PDM_SNPF(out_len, used, output + used, + out_len - used, + "===>The following fahm report does not count CCK pkt\n"); + + for (i = 0; i < FAHM_RPT_NUM; i++) { + result_tmp = ccx->fahm_result[i]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "fahm_rpt[%d] = %d (%d percent)\n", + i, result_tmp, + (((result_tmp * 100) + 32768) >> 16)); + } + phydm_fahm_get_utility(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "fahm_pwr=%d, fahm_ratio=%d, fahm_denom_ratio=%d\n", + ccx->fahm_pwr, ccx->fahm_ratio, + ccx->fahm_denom_ratio); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Get FAHM_rpt Fail\n"); + } + ccx->fahm_manual_ctrl = 0; + } else { /*FAMH trigger*/ + ccx->fahm_manual_ctrl = 1; + + for (i = 1; i < 9; i++) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + if (var1[0] == 1) { + para.numer_opt = FAHM_INCLU_FA; + para.denom_opt = FAHM_INCLU_CRC_ERR; + para.app = FAHM_DBG; + para.lv = FAHM_LV_4; + para.mntr_time = 262; + para.en_1db_mode = false; + para.th0_manual = 0; + } else { + para.numer_opt = (u8)var1[1]; + para.denom_opt = (u8)var1[2]; + para.app = (enum fahm_application)var1[3]; + para.lv = (enum phydm_fahm_level)var1[4]; + para.mntr_time = (u16)var1[5]; + para.en_1db_mode = (boolean)var1[6]; + para.th0_manual = (u8)var1[7]; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "numer_opt=%d, denom_opt=%d, app=%d, lv=%d, time=%d ms\n", + para.numer_opt, para.denom_opt,para.app, para.lv, + para.mntr_time); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "en_1db_mode=%d, th0(for 1db mode)=%d\n", + para.en_1db_mode, para.th0_manual); + + if (phydm_fahm_mntr_set(dm, ¶)) + phydm_fahm_trigger(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=0x%x, rpt_stamp=%d\n", ccx->fahm_igi, + ccx->fahm_rpt_stamp); + + for (i = 0; i < FAHM_TH_NUM; i++) + PDM_SNPF(out_len, used, output + used, out_len - used, + "FAHM_th[%d] RSSI = %d\n", i, + NTH_TH_2_RSSI(ccx->fahm_th[i])); + } + + *_used = used; + *_out_len = out_len; +} + +#endif /*#ifdef FAHM_SUPPORT*/ + +#ifdef IFS_CLM_SUPPORT +void phydm_ifs_clm_restart(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*restart IFS_CLM*/ + odm_set_bb_reg(dm, R_0x1ee4, BIT(29), 0x0); + odm_set_bb_reg(dm, R_0x1ee4, BIT(29), 0x1); +} + +void phydm_ifs_clm_racing_release(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "ifs clm lv:(%d)->(0)\n", + ccx->ifs_clm_set_lv); + + ccx->ifs_clm_ongoing = false; + ccx->ifs_clm_set_lv = IFS_CLM_RELEASE; + ccx->ifs_clm_app = IFS_CLM_BACKGROUND; +} + +u8 phydm_ifs_clm_racing_ctrl(void *dm_void, enum phydm_ifs_clm_level ifs_clm_lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = PHYDM_SET_SUCCESS; + /*acquire to control IFS CLM API*/ + + PHYDM_DBG(dm, DBG_ENV_MNTR, "ifs clm_ongoing=%d, lv:(%d)->(%d)\n", + ccx->ifs_clm_ongoing, ccx->ifs_clm_set_lv, ifs_clm_lv); + if (ccx->ifs_clm_ongoing) { + if (ifs_clm_lv <= ccx->ifs_clm_set_lv) { + set_result = PHYDM_SET_FAIL; + } else { + phydm_ifs_clm_restart(dm); + ccx->ifs_clm_ongoing = false; + } + } + + if (set_result) + ccx->ifs_clm_set_lv = ifs_clm_lv; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "ifs clm racing success=%d\n", set_result); + return set_result; +} + +void phydm_ifs_clm_trigger(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Trigger IFS_CLM*/ + pdm_set_reg(dm, R_0x1ee4, BIT(29), 0); + pdm_set_reg(dm, R_0x1ee4, BIT(29), 1); + ccx->ifs_clm_trigger_time = dm->phydm_sys_up_time; + ccx->ifs_clm_rpt_stamp++; + ccx->ifs_clm_ongoing = true; +} + +void phydm_ifs_clm_get_utility(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u16 denom = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + denom = ccx->ifs_clm_period; + ccx->ifs_clm_tx_ratio = phydm_ccx_get_rpt_ratio(dm, ccx->ifs_clm_tx, + denom); + ccx->ifs_clm_edcca_excl_cca_ratio = phydm_ccx_get_rpt_ratio(dm, + ccx->ifs_clm_edcca_excl_cca, + denom); + ccx->ifs_clm_cck_fa_ratio = phydm_ccx_get_rpt_ratio(dm, + ccx->ifs_clm_cckfa, denom); + ccx->ifs_clm_ofdm_fa_ratio = phydm_ccx_get_rpt_ratio(dm, + ccx->ifs_clm_ofdmfa, denom); + ccx->ifs_clm_cck_cca_excl_fa_ratio = phydm_ccx_get_rpt_ratio(dm, + ccx->ifs_clm_cckcca_excl_fa, + denom); + ccx->ifs_clm_ofdm_cca_excl_fa_ratio = phydm_ccx_get_rpt_ratio(dm, + ccx->ifs_clm_ofdmcca_excl_fa, + denom); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Tx_ratio = %d, EDCCA_exclude_CCA_ratio = %d \n", + ccx->ifs_clm_tx_ratio, ccx->ifs_clm_edcca_excl_cca_ratio); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "CCK : FA_ratio = %d, CCA_exclude_FA_ratio = %d \n", + ccx->ifs_clm_cck_fa_ratio, + ccx->ifs_clm_cck_cca_excl_fa_ratio); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "OFDM : FA_ratio = %d, CCA_exclude_FA_ratio = %d \n", + ccx->ifs_clm_ofdm_fa_ratio, + ccx->ifs_clm_ofdm_cca_excl_fa_ratio); +} + +void phydm_ifs_clm_get_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 value32 = 0; + u8 i = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Enhance CLM result*/ + value32 = odm_get_bb_reg(dm, R_0x2e60, MASKDWORD); + ccx->ifs_clm_tx = (u16)(value32 & MASKLWORD); + ccx->ifs_clm_edcca_excl_cca = (u16)((value32 & MASKHWORD) >> 16); + value32 = odm_get_bb_reg(dm, R_0x2e64, MASKDWORD); + ccx->ifs_clm_ofdmfa = (u16)(value32 & MASKLWORD); + ccx->ifs_clm_ofdmcca_excl_fa = (u16)((value32 & MASKHWORD) >> 16); + value32 = odm_get_bb_reg(dm, R_0x2e68, MASKDWORD); + ccx->ifs_clm_cckfa = (u16)(value32 & MASKLWORD); + ccx->ifs_clm_cckcca_excl_fa = (u16)((value32 & MASKHWORD) >> 16); + value32 = odm_get_bb_reg(dm, R_0x2e6c, MASKDWORD); + ccx->ifs_clm_total_cca = (u16)(value32 & MASKLWORD); + + /* IFS result */ + value32 = odm_get_bb_reg(dm, R_0x2e70, MASKDWORD); + odm_move_memory(dm, &ccx->ifs_clm_his[0], &value32, 4); + value32 = odm_get_bb_reg(dm, R_0x2e74, MASKDWORD); + ccx->ifs_clm_avg[0] = (u16)(value32 & MASKLWORD); + ccx->ifs_clm_avg[1] = (u16)((value32 & MASKHWORD) >> 16); + value32 = odm_get_bb_reg(dm, R_0x2e78, MASKDWORD); + ccx->ifs_clm_avg[2] = (u16)(value32 & MASKLWORD); + ccx->ifs_clm_avg[3] = (u16)((value32 & MASKHWORD) >> 16); + value32 = odm_get_bb_reg(dm, R_0x2e7c, MASKDWORD); + ccx->ifs_clm_avg_cca[0] = (u16)(value32 & MASKLWORD); + ccx->ifs_clm_avg_cca[1] = (u16)((value32 & MASKHWORD) >> 16); + value32 = odm_get_bb_reg(dm, R_0x2e80, MASKDWORD); + ccx->ifs_clm_avg_cca[2] = (u16)(value32 & MASKLWORD); + ccx->ifs_clm_avg_cca[3] = (u16)((value32 & MASKHWORD) >> 16); + + /* Print Result */ + PHYDM_DBG(dm, DBG_ENV_MNTR, + "ECLM_Rpt[%d]: \nTx = %d, EDCCA_exclude_CCA = %d \n", + ccx->ifs_clm_rpt_stamp, ccx->ifs_clm_tx, + ccx->ifs_clm_edcca_excl_cca); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[FA_cnt] {CCK, OFDM} = {%d, %d}\n", + ccx->ifs_clm_cckfa, ccx->ifs_clm_ofdmfa); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[CCA_exclude_FA_cnt] {CCK, OFDM} = {%d, %d}\n", + ccx->ifs_clm_cckcca_excl_fa, ccx->ifs_clm_ofdmcca_excl_fa); + PHYDM_DBG(dm, DBG_ENV_MNTR, "CCATotal = %d\n", ccx->ifs_clm_total_cca); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Time:[his, avg, avg_cca]\n"); + for (i = 0; i < IFS_CLM_NUM; i++) + PHYDM_DBG(dm, DBG_ENV_MNTR, + "T%d:[%d, %d, %d]\n", i + 1, + ccx->ifs_clm_his[i], ccx->ifs_clm_avg[i], + ccx->ifs_clm_avg_cca[i]); + + phydm_ifs_clm_racing_release(dm); + + return; +} + +void phydm_ifs_clm_set_th_reg(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 i = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + /*Set IFS period TH*/ + odm_set_bb_reg(dm, R_0x1ed4, BIT(31), ccx->ifs_clm_th_en[0]); + odm_set_bb_reg(dm, R_0x1ed8, BIT(31), ccx->ifs_clm_th_en[1]); + odm_set_bb_reg(dm, R_0x1edc, BIT(31), ccx->ifs_clm_th_en[2]); + odm_set_bb_reg(dm, R_0x1ee0, BIT(31), ccx->ifs_clm_th_en[3]); + odm_set_bb_reg(dm, R_0x1ed4, 0x7fff0000, ccx->ifs_clm_th_low[0]); + odm_set_bb_reg(dm, R_0x1ed8, 0x7fff0000, ccx->ifs_clm_th_low[1]); + odm_set_bb_reg(dm, R_0x1edc, 0x7fff0000, ccx->ifs_clm_th_low[2]); + odm_set_bb_reg(dm, R_0x1ee0, 0x7fff0000, ccx->ifs_clm_th_low[3]); + odm_set_bb_reg(dm, R_0x1ed4, MASKLWORD, ccx->ifs_clm_th_high[0]); + odm_set_bb_reg(dm, R_0x1ed8, MASKLWORD, ccx->ifs_clm_th_high[1]); + odm_set_bb_reg(dm, R_0x1edc, MASKLWORD, ccx->ifs_clm_th_high[2]); + odm_set_bb_reg(dm, R_0x1ee0, MASKLWORD, ccx->ifs_clm_th_high[3]); + + for (i = 0; i < IFS_CLM_NUM; i++) + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update IFS_CLM_th%d[High Low] : [%d %d]\n", i + 1, + ccx->ifs_clm_th_high[i], ccx->ifs_clm_th_low[i]); +} + +boolean phydm_ifs_clm_th_update_chk(void *dm_void, + enum ifs_clm_application ifs_clm_app, + boolean *ifs_clm_th_en, u16 *ifs_clm_th_low, + u16 *ifs_clm_th_high, s16 th_shift) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean is_update = false; + u16 ifs_clm_th_low_bg[IFS_CLM_NUM] = {12, 5, 2, 0}; + u16 ifs_clm_th_high_bg[IFS_CLM_NUM] = {64, 12, 5, 2}; + u8 i = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "App=%d, th_shift=%d\n", ifs_clm_app, + th_shift); + + switch (ifs_clm_app) { + case IFS_CLM_BACKGROUND: + case IFS_CLM_ACS: + case IFS_CLM_HP_TAS: + if (ccx->ifs_clm_app != ifs_clm_app || th_shift != 0) { + is_update = true; + + for (i = 0; i < IFS_CLM_NUM; i++) { + ifs_clm_th_en[i] = true; + ifs_clm_th_low[i] = ifs_clm_th_low_bg[i]; + ifs_clm_th_high[i] = ifs_clm_th_high_bg[i]; + } + } + break; + case IFS_CLM_DBG: + if (ccx->ifs_clm_app != ifs_clm_app || th_shift != 0) { + is_update = true; + + for (i = 0; i < IFS_CLM_NUM; i++) { + ifs_clm_th_en[i] = true; + ifs_clm_th_low[i] = MAX_2(ccx->ifs_clm_th_low[i] + + th_shift, 0); + ifs_clm_th_high[i] = MAX_2(ccx->ifs_clm_th_high[i] + + th_shift, 0); + } + } + break; + default: + break; + } + + if (is_update) + PHYDM_DBG(dm, DBG_ENV_MNTR, "[Update IFS_TH]\n"); + else + PHYDM_DBG(dm, DBG_ENV_MNTR, "No need to update IFS_TH\n"); + + return is_update; +} + +void phydm_ifs_clm_set(void *dm_void, enum ifs_clm_application ifs_clm_app, + u16 period, u8 ctrl_unit, s16 th_shift) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean ifs_clm_th_en[IFS_CLM_NUM] = {0}; + u16 ifs_clm_th_low[IFS_CLM_NUM] = {0}; + u16 ifs_clm_th_high[IFS_CLM_NUM] = {0}; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "period=%d, ctrl_unit=%d\n", period, + ctrl_unit); + + /*Set Unit*/ + if (ctrl_unit != ccx->ifs_clm_ctrl_unit) { + odm_set_bb_reg(dm, R_0x1ee4, 0xc0000000, ctrl_unit); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update IFS_CLM unit ((%d)) -> ((%d))\n", + ccx->ifs_clm_ctrl_unit, ctrl_unit); + ccx->ifs_clm_ctrl_unit = ctrl_unit; + } + + /*Set Duration*/ + if (period != ccx->ifs_clm_period) { + odm_set_bb_reg(dm, R_0x1eec, 0xc0000000, (period & 0x3)); + odm_set_bb_reg(dm, R_0x1ef0, 0xfe000000, ((period >> 2) & + 0x7f)); + odm_set_bb_reg(dm, R_0x1ef4, 0xc0000000, ((period >> 9) & + 0x3)); + odm_set_bb_reg(dm, R_0x1ef8, 0x3e000000, ((period >> 11) & + 0x1f)); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Update IFS_CLM period ((%d)) -> ((%d))\n", + ccx->ifs_clm_period, period); + ccx->ifs_clm_period = period; + } + + /*Set IFS CLM threshold*/ + if (phydm_ifs_clm_th_update_chk(dm, ifs_clm_app, &ifs_clm_th_en[0], + &ifs_clm_th_low[0], &ifs_clm_th_high[0], + th_shift)) { + + ccx->ifs_clm_app = ifs_clm_app; + odm_move_memory(dm, &ccx->ifs_clm_th_en[0], &ifs_clm_th_en, + IFS_CLM_NUM); + odm_move_memory(dm, &ccx->ifs_clm_th_low[0], &ifs_clm_th_low, + IFS_CLM_NUM); + odm_move_memory(dm, &ccx->ifs_clm_th_high[0], &ifs_clm_th_high, + IFS_CLM_NUM); + + phydm_ifs_clm_set_th_reg(dm); + } +} + +boolean +phydm_ifs_clm_mntr_set(void *dm_void, struct ifs_clm_para_info *ifs_clm_para) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 ifs_clm_time = 0; /*unit: 4/8/12/16us*/ + u8 unit = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (ifs_clm_para->mntr_time == 0) + return false; + + if (ifs_clm_para->ifs_clm_lv >= IFS_CLM_MAX_NUM) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Wrong LV=%d\n", + ifs_clm_para->ifs_clm_lv); + return false; + } + + if (phydm_ifs_clm_racing_ctrl(dm, ifs_clm_para->ifs_clm_lv) == PHYDM_SET_FAIL) + return false; + + if (ifs_clm_para->mntr_time >= 1048) { + unit = IFS_CLM_16; + ifs_clm_time = IFS_CLM_PERIOD_MAX; /*65535 * 16us = 1048ms*/ + } else if (ifs_clm_para->mntr_time >= 786) {/*65535 * 12us = 786 ms*/ + unit = IFS_CLM_16; + ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 16); + } else if (ifs_clm_para->mntr_time >= 524) { + unit = IFS_CLM_12; + ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 12); + } else if (ifs_clm_para->mntr_time >= 262) { + unit = IFS_CLM_8; + ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 8); + } else { + unit = IFS_CLM_4; + ifs_clm_time = PHYDM_DIV(ifs_clm_para->mntr_time * MS_TO_US, 4); + } + + phydm_ifs_clm_set(dm, ifs_clm_para->ifs_clm_app, ifs_clm_time, unit, + ifs_clm_para->th_shift); + + return true; +} + +boolean +phydm_ifs_clm_mntr_racing_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 sys_return_time = 0; + + if (ccx->ifs_clm_manual_ctrl) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "IFS_CLM in manual ctrl\n"); + return true; + } + + sys_return_time = ccx->ifs_clm_trigger_time + MAX_ENV_MNTR_TIME; + + if (ccx->ifs_clm_app != IFS_CLM_BACKGROUND && + (sys_return_time > dm->phydm_sys_up_time)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "ifs_clm_app=%d, trigger_time %d, sys_time=%d\n", + ccx->ifs_clm_app, ccx->ifs_clm_trigger_time, + dm->phydm_sys_up_time); + + return true; + } + + return false; +} + +boolean +phydm_ifs_clm_mntr_chk(void *dm_void, u16 monitor_time /*unit ms*/) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct ifs_clm_para_info ifs_clm_para = {0}; + boolean ifs_clm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (phydm_ifs_clm_mntr_racing_chk(dm)) + return ifs_clm_chk_result; + + /*[IFS CLM trigger setting]------------------------------------------*/ + ifs_clm_para.ifs_clm_app = IFS_CLM_BACKGROUND; + ifs_clm_para.ifs_clm_lv = IFS_CLM_LV_1; + ifs_clm_para.mntr_time = monitor_time; + ifs_clm_para.th_shift = 0; + + ifs_clm_chk_result = phydm_ifs_clm_mntr_set(dm, &ifs_clm_para); + + return ifs_clm_chk_result; +} + +boolean +phydm_ifs_clm_mntr_result(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean ifs_clm_chk_result = false; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + if (phydm_ifs_clm_mntr_racing_chk(dm)) + return ifs_clm_chk_result; + + /*[IFS CLM get result] ------------------------------------]*/ + phydm_ifs_clm_get_result(dm); + phydm_ifs_clm_get_utility(dm); + ifs_clm_chk_result = true; + + return ifs_clm_chk_result; +} + +void phydm_ifs_clm_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + ccx->ifs_clm_app = IFS_CLM_BACKGROUND; + + /*Set IFS threshold*/ + ccx->ifs_clm_ongoing = false; + ccx->ifs_clm_set_lv = IFS_CLM_RELEASE; + + if (phydm_ifs_clm_th_update_chk(dm, ccx->ifs_clm_app, + &ccx->ifs_clm_th_en[0], + &ccx->ifs_clm_th_low[0], + &ccx->ifs_clm_th_high[0], 0xffff)) + phydm_ifs_clm_set_th_reg(dm); + + ccx->ifs_clm_period = 0; + ccx->ifs_clm_ctrl_unit = IFS_CLM_INIT; + ccx->ifs_clm_manual_ctrl = 0; + ccx->ifs_clm_rpt_stamp = 0; +} + +void phydm_ifs_clm_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct ifs_clm_para_info ifs_clm_para; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 result_tmp = 0; + u8 i = 0; + u16 th_shift = 0; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM)) + return; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "IFS_CLM Basic-Trigger 960ms: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "IFS_CLM Adv-Trigger: {2} {App:3 for dbg} {LV:1~4} {0~2096ms} {th_shift}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "IFS_CLM Get Result: {100}\n"); + } else if (var1[0] == 100) { /*Get IFS_CLM results*/ + phydm_ifs_clm_get_result(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "ECLM_Rpt[%d]: \nTx = %d \nEDCCA_exclude_CCA = %d\n", + ccx->ifs_clm_rpt_stamp, ccx->ifs_clm_tx, + ccx->ifs_clm_edcca_excl_cca); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[FA_cnt] {CCK, OFDM} = {%d, %d}\n", + ccx->ifs_clm_cckfa, ccx->ifs_clm_ofdmfa); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[CCA_exclude_FA_cnt] {CCK, OFDM} = {%d, %d}\n", + ccx->ifs_clm_cckcca_excl_fa, + ccx->ifs_clm_ofdmcca_excl_fa); + PDM_SNPF(out_len, used, output + used, out_len - used, + "CCATotal = %d\n", ccx->ifs_clm_total_cca); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Time:[his, avg, avg_cca]\n"); + for (i = 0; i < IFS_CLM_NUM; i++) + PDM_SNPF(out_len, used, output + used, out_len - used, + "T%d:[%d, %d, %d]\n", i + 1, + ccx->ifs_clm_his[i], ccx->ifs_clm_avg[i], + ccx->ifs_clm_avg_cca[i]); + + phydm_ifs_clm_get_utility(dm); + + ccx->ifs_clm_manual_ctrl = 0; + } else { /*IFS_CLM trigger*/ + ccx->ifs_clm_manual_ctrl = 1; + + if (var1[0] == 1) { + ifs_clm_para.ifs_clm_app = IFS_CLM_DBG; + ifs_clm_para.ifs_clm_lv = IFS_CLM_LV_4; + ifs_clm_para.mntr_time = 960; + ifs_clm_para.th_shift = 0; + } else { + ifs_clm_para.ifs_clm_app = (enum ifs_clm_application)var1[1]; + ifs_clm_para.ifs_clm_lv = (enum phydm_ifs_clm_level)var1[2]; + ifs_clm_para.mntr_time = (u16)var1[3]; + ifs_clm_para.th_shift = (s16)var1[4]; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "app=%d, lv=%d, time=%d ms, th_shift=%s%d\n", + ifs_clm_para.ifs_clm_app, ifs_clm_para.ifs_clm_lv, + ifs_clm_para.mntr_time, + (ifs_clm_para.th_shift > 0) ? "+" : "-", + ifs_clm_para.th_shift); + + if (phydm_ifs_clm_mntr_set(dm, &ifs_clm_para) == PHYDM_SET_SUCCESS) + phydm_ifs_clm_trigger(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "rpt_stamp=%d\n", ccx->ifs_clm_rpt_stamp); + for (i = 0; i < IFS_CLM_NUM; i++) + PDM_SNPF(out_len, used, output + used, out_len - used, + "IFS_CLM_th%d[High Low] : [%d %d]\n", i + 1, + ccx->ifs_clm_th_high[i], + ccx->ifs_clm_th_low[i]); + } + + *_used = used; + *_out_len = out_len; +} +#endif + +u8 phydm_enhance_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct fahm_para_info *fahm_para, + struct ifs_clm_para_info *ifs_clm_para, + struct enhance_mntr_trig_rpt *trig_rpt) +{ + u8 trigger_result = 0; +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT) && defined(FAHM_SUPPORT) && defined(IFS_CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + boolean nhm_set_ok = false; + boolean clm_set_ok = false; + boolean fahm_set_ok = false; + boolean ifs_clm_set_ok = false; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) || + !(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM)) + return trigger_result; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + + nhm_set_ok = phydm_nhm_mntr_set(dm, nhm_para); + + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + clm_set_ok = phydm_clm_mntr_set(dm, clm_para); + } else if (ccx->clm_mntr_mode == CLM_FW_MNTR) { + phydm_clm_h2c(dm, CLM_PERIOD_MAX, true); + trigger_result |= CLM_SUCCESS; + } + + fahm_set_ok = phydm_fahm_mntr_set(dm, fahm_para); + + ifs_clm_set_ok = phydm_ifs_clm_mntr_set(dm, ifs_clm_para); + + if (nhm_set_ok) { + phydm_nhm_trigger(dm); + trigger_result |= NHM_SUCCESS; + } + + if (clm_set_ok) { + phydm_clm_trigger(dm); + trigger_result |= CLM_SUCCESS; + } + + if (fahm_set_ok) { + phydm_fahm_trigger(dm); + trigger_result |= FAHM_SUCCESS; + } + + if (ifs_clm_set_ok) { + phydm_ifs_clm_trigger(dm); + trigger_result |= IFS_CLM_SUCCESS; + } + + /*monitor for the test duration*/ + ccx->start_time = odm_get_current_time(dm); + + trig_rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + trig_rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; + trig_rpt->fahm_rpt_stamp = ccx->fahm_rpt_stamp; + trig_rpt->ifs_clm_rpt_stamp = ccx->ifs_clm_rpt_stamp; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "rpt_stamp{NHM, CLM, FAHM, IFS_CLM}={%d, %d, %d, %d}\n\n", + trig_rpt->nhm_rpt_stamp, trig_rpt->clm_rpt_stamp, + trig_rpt->fahm_rpt_stamp, trig_rpt->ifs_clm_rpt_stamp); + +#endif + return trigger_result; +} + +u8 phydm_enhance_mntr_result(void *dm_void, struct enhance_mntr_rpt *rpt) +{ + u8 enhance_mntr_rpt = 0; +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT) && defined(FAHM_SUPPORT) && defined(IFS_CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + u64 progressing_time = 0; + u32 val_tmp = 0; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) || + !(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM)) + return enhance_mntr_rpt; + + /*monitor for the test duration*/ + progressing_time = odm_get_progressing_time(dm, ccx->start_time); + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s] ======>\n", __func__); + PHYDM_DBG(dm, DBG_ENV_MNTR, "enhance_mntr_time=%lld\n", + progressing_time); + + /*Get NHM result*/ + if (phydm_nhm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get NHM_rpt success\n"); + phydm_nhm_get_utility(dm); + rpt->nhm_ratio = ccx->nhm_ratio; + rpt->nhm_env_ratio = ccx->nhm_env_ratio; + rpt->nhm_noise_pwr = ccx->nhm_level; + rpt->nhm_pwr = ccx->nhm_pwr; + enhance_mntr_rpt |= NHM_SUCCESS; + + odm_move_memory(dm, &rpt->nhm_result[0], + &ccx->nhm_result[0], NHM_RPT_NUM); + } else { + rpt->nhm_ratio = ENV_MNTR_FAIL; + rpt->nhm_env_ratio = ENV_MNTR_FAIL; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[NHM]rpt_stamp=%d, IGI=0x%x, ratio=%d, env_ratio=%d, noise_pwr=%d, pwr=%d\n", + rpt->nhm_rpt_stamp, ccx->nhm_igi, rpt->nhm_ratio, + rpt->nhm_env_ratio, rpt->nhm_noise_pwr, rpt->nhm_pwr); + + /*Get CLM result*/ + if (ccx->clm_mntr_mode == CLM_DRIVER_MNTR) { + if (phydm_clm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get CLM_rpt success\n"); + phydm_clm_get_utility(dm); + enhance_mntr_rpt |= CLM_SUCCESS; + rpt->clm_ratio = ccx->clm_ratio; + } else { + rpt->clm_ratio = ENV_MNTR_FAIL; + } + } else { + if (ccx->clm_fw_result_cnt != 0) { + val_tmp = ccx->clm_fw_result_acc + / ccx->clm_fw_result_cnt; + ccx->clm_ratio = (u8)val_tmp; + } else { + ccx->clm_ratio = 0; + } + rpt->clm_ratio = ccx->clm_ratio; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "clm_fw_result_acc=%d, clm_fw_result_cnt=%d\n", + ccx->clm_fw_result_acc, ccx->clm_fw_result_cnt); + + ccx->clm_fw_result_acc = 0; + ccx->clm_fw_result_cnt = 0; + enhance_mntr_rpt |= CLM_SUCCESS; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[CLM]rpt_stamp=%d, ratio=%d\n", + rpt->clm_rpt_stamp, rpt->clm_ratio); + + /*Get FAHM result*/ + if (phydm_fahm_get_result(dm)) { + PHYDM_DBG(dm, DBG_ENV_MNTR, "Get FAHM_rpt success\n"); + phydm_fahm_get_utility(dm); + rpt->fahm_pwr = ccx->fahm_pwr; + rpt->fahm_ratio = ccx->fahm_ratio; + rpt->fahm_denom_ratio = ccx->fahm_denom_ratio; + rpt->fahm_inclu_cck = ccx->fahm_inclu_cck; + enhance_mntr_rpt |= FAHM_SUCCESS; + + odm_move_memory(dm, &rpt->fahm_result[0], + &ccx->fahm_result[0], FAHM_RPT_NUM * 2); + } else { + rpt->fahm_pwr = 0; + rpt->fahm_ratio = 0; + rpt->fahm_denom_ratio = 0; + } + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[FAHM]stamp=%d, IGI=0x%x, fahm_inclu_cck=%d, fahm_pwr=%d, fahm_ratio=%d, fahm_denom_ratio=%d\n", + rpt->fahm_rpt_stamp, ccx->fahm_igi, rpt->fahm_inclu_cck, + rpt->fahm_pwr, rpt->fahm_ratio, rpt->fahm_denom_ratio); + + /*Get IFS_CLM result*/ + phydm_ifs_clm_get_result(dm); + phydm_ifs_clm_get_utility(dm); + rpt->ifs_clm_tx_ratio = ccx->ifs_clm_tx_ratio; + rpt->ifs_clm_edcca_excl_cca_ratio = ccx->ifs_clm_edcca_excl_cca_ratio; + rpt->ifs_clm_cck_fa_ratio = ccx->ifs_clm_cck_fa_ratio; + rpt->ifs_clm_cck_cca_excl_fa_ratio = ccx->ifs_clm_cck_cca_excl_fa_ratio; + rpt->ifs_clm_ofdm_fa_ratio = ccx->ifs_clm_ofdm_fa_ratio; + rpt->ifs_clm_ofdm_cca_excl_fa_ratio = ccx->ifs_clm_ofdm_cca_excl_fa_ratio; + rpt->ifs_clm_rpt_stamp = ccx->ifs_clm_rpt_stamp; + enhance_mntr_rpt |= IFS_CLM_SUCCESS; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[IFS_CLM]rpt_stamp = %d, Tx_ratio = %d, EDCCA_exclude_CCA_ratio = %d\n", + ccx->ifs_clm_rpt_stamp, ccx->ifs_clm_tx_ratio, + ccx->ifs_clm_edcca_excl_cca_ratio); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "CCK : FA_ratio = %d, CCA_exclude_FA_ratio = %d\n", + ccx->ifs_clm_cck_fa_ratio, ccx->ifs_clm_cck_cca_excl_fa_ratio); + PHYDM_DBG(dm, DBG_ENV_MNTR, + "OFDM : FA_ratio = %d, CCA_exclude_FA_ratio = %d\n", + ccx->ifs_clm_ofdm_fa_ratio, + ccx->ifs_clm_ofdm_cca_excl_fa_ratio); + + rpt->nhm_rpt_stamp = ccx->nhm_rpt_stamp; + rpt->clm_rpt_stamp = ccx->clm_rpt_stamp; + rpt->fahm_rpt_stamp = ccx->fahm_rpt_stamp; + rpt->ifs_clm_rpt_stamp = ccx->ifs_clm_rpt_stamp; +#endif + return enhance_mntr_rpt; +} + +void phydm_enhance_mntr_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT) && defined(FAHM_SUPPORT) && defined(IFS_CLM_SUPPORT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + struct nhm_para_info nhm_para = {0}; + struct clm_para_info clm_para = {0}; + struct fahm_para_info fahm_para = {0}; + struct ifs_clm_para_info ifs_clm_para = {0}; + struct enhance_mntr_rpt rpt = {0}; + struct enhance_mntr_trig_rpt trig_rpt = {0}; + struct ccx_info *ccx = &dm->dm_ccx_info; + u8 set_result = 0; + u8 i = 0; + + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) || + !(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM)) + return; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Basic-Trigger 960ms for ifs_clm, 262ms for others: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Get Result: {100}\n"); + } else if (var1[0] == 100) { /* Get results */ + set_result = phydm_enhance_mntr_result(dm, &rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Result=%d, rpt_stamp{NHM, CLM, FAHM, IFS_CLM}={%d, %d, %d, %d}\n", + set_result, rpt.nhm_rpt_stamp, rpt.clm_rpt_stamp, + rpt.fahm_rpt_stamp, rpt.ifs_clm_rpt_stamp); + PDM_SNPF(out_len, used, output + used, out_len - used, + "clm_ratio=%d\n", rpt.clm_ratio); + + for (i = 0; i < NHM_RPT_NUM; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "nhm_rpt[%d] = %d (%d percent)\n", i, + rpt.nhm_result[i], + (((rpt.nhm_result[i] * 100) + 128) >> 8)); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "nhm_IGI=0x%x, nhm_ratio=%d, nhm_env_ratio=%d, nhm_noise_pwr=%d, nhm_pwr=%d\n", + ccx->nhm_igi, rpt.nhm_ratio, rpt.nhm_env_ratio, + rpt.nhm_noise_pwr, rpt.nhm_pwr); + + if (!(rpt.fahm_inclu_cck)) + PDM_SNPF(out_len, used, output + used, + out_len - used, + "===>The following fahm report does not count CCK pkt\n"); + + for (i = 0; i < FAHM_RPT_NUM; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "fahm_rpt[%d] = %d (%d percent)\n", i, + rpt.fahm_result[i], + (((rpt.fahm_result[i] * 100) + 32768) >> 16)); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "fahm_IGI=0x%x, fahm_pwr=%d, fahm_ratio=%d, fahm_denom_ratio=%d\n", + ccx->fahm_igi, rpt.fahm_pwr, rpt.fahm_ratio, + rpt.fahm_denom_ratio); + PDM_SNPF(out_len, used, output + used, out_len - used, + "ifs_clm_Tx_ratio = %d, ifs_clm_EDCCA_exclude_CCA_ratio = %d \n", + rpt.ifs_clm_tx_ratio, + rpt.ifs_clm_edcca_excl_cca_ratio); + PDM_SNPF(out_len, used, output + used, out_len - used, + "ifs_clm_cck_fa_ratio = %d, ifs_clm_cck_cca_exclude_FA_ratio = %d \n", + rpt.ifs_clm_cck_fa_ratio, + rpt.ifs_clm_cck_cca_excl_fa_ratio); + PDM_SNPF(out_len, used, output + used, out_len - used, + "ifs_clm_ofdm_fa_ratio = %d, ifs_clm_ofdm_cca_exclude_FA_ratio = %d \n", + rpt.ifs_clm_ofdm_fa_ratio, + rpt.ifs_clm_ofdm_cca_excl_fa_ratio); + } else { /* Set & trigger*/ + /*nhm para*/ + nhm_para.incld_txon = NHM_EXCLUDE_TXON; + nhm_para.incld_cca = NHM_EXCLUDE_CCA; + nhm_para.div_opt = NHM_CNT_ALL; + nhm_para.nhm_app = NHM_ACS; + nhm_para.nhm_lv = NHM_LV_2; + nhm_para.mntr_time = 262; + nhm_para.en_1db_mode = false; + + /*clm para*/ + clm_para.clm_app = CLM_ACS; + clm_para.clm_lv = CLM_LV_2; + clm_para.mntr_time = 262; + + /*fahm para*/ + fahm_para.numer_opt = FAHM_INCLU_FA; + fahm_para.denom_opt = FAHM_INCLU_CRC_ERR; + fahm_para.app = FAHM_ACS; + fahm_para.lv = FAHM_LV_2; + fahm_para.mntr_time = 262; + fahm_para.en_1db_mode = false; + + ifs_clm_para.ifs_clm_app = IFS_CLM_ACS; + ifs_clm_para.ifs_clm_lv = IFS_CLM_LV_2; + ifs_clm_para.mntr_time = 960; + ifs_clm_para.th_shift = 0; + + set_result = phydm_enhance_mntr_trigger(dm, &nhm_para, + &clm_para, &fahm_para, + &ifs_clm_para, + &trig_rpt); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Result=%d, rpt_stamp{NHM, CLM, FAHM, IFS_CLM}={%d, %d ,%d, %d}\n", + set_result, trig_rpt.nhm_rpt_stamp, + trig_rpt.clm_rpt_stamp, trig_rpt.fahm_rpt_stamp, + trig_rpt.ifs_clm_rpt_stamp); + } + *_used = used; + *_out_len = out_len; +#endif +} + +/*Environment Monitor*/ +void phydm_env_mntr_result_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + ccx->ccx_watchdog_result = 0; + + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; + + #if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + if (phydm_nhm_mntr_result(dm)) + ccx->ccx_watchdog_result |= NHM_SUCCESS; + + if (phydm_clm_mntr_result(dm)) + ccx->ccx_watchdog_result |= CLM_SUCCESS; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Summary: nhm_ratio=((%d)) clm_ratio=((%d))\n\n", + ccx->nhm_ratio, ccx->clm_ratio); + #endif + + #ifdef FAHM_SUPPORT + if (dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) { + if (phydm_fahm_mntr_result(dm)) + ccx->ccx_watchdog_result |= FAHM_SUCCESS; + } + #endif + + #ifdef IFS_CLM_SUPPORT + if (dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM) { + if (phydm_ifs_clm_mntr_result(dm)) + ccx->ccx_watchdog_result |= IFS_CLM_SUCCESS; + } + #endif +} + +void phydm_env_mntr_set_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + + if (!(dm->support_ability & ODM_BB_ENV_MONITOR)) + return; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "[%s]===>\n", __func__); + + #if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + if (phydm_nhm_mntr_chk(dm, 262)) + phydm_nhm_trigger(dm); + + if (phydm_clm_mntr_chk(dm, 262)) + phydm_clm_trigger(dm); + #endif + + #ifdef FAHM_SUPPORT + if (dm->support_ic_type & PHYDM_IC_SUPPORT_FAHM) { + if (phydm_fahm_mntr_chk(dm, 262)) + phydm_fahm_trigger(dm); + } + #endif + + #ifdef IFS_CLM_SUPPORT + if (dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM) { + if (phydm_ifs_clm_mntr_chk(dm, 960)) + phydm_ifs_clm_trigger(dm); + } + #endif +} + +void phydm_env_monitor_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + #if (defined(NHM_SUPPORT) && defined(CLM_SUPPORT)) + phydm_ccx_hw_restart(dm); + phydm_nhm_init(dm); + phydm_clm_init(dm); + #endif + + #ifdef FAHM_SUPPORT + phydm_fahm_init(dm); + #endif + + #ifdef IFS_CLM_SUPPORT + if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_IFS_CLM)) + return; + + phydm_ifs_clm_restart(dm); + phydm_ifs_clm_init(dm); + #endif +} + diff --git a/hal/phydm/phydm_ccx.h b/hal/phydm/phydm_ccx.h new file mode 100644 index 0000000..95ec6fa --- /dev/null +++ b/hal/phydm/phydm_ccx.h @@ -0,0 +1,429 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMCCX_H__ +#define __PHYDMCCX_H__ + +/* 2020.08.12 split env_mntr api into set_env_mntr and result_env_mntr api for dig_fa_source*/ +#define CCX_VERSION "4.7" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +#define CCX_EN 1 + +#define MAX_ENV_MNTR_TIME 8 /*second*/ +#define MS_TO_US 1000 +#define MS_TO_4US_RATIO 250 +#define CCA_CAP 14 +/*CLM*/ +#define CLM_MAX_REPORT_TIME 10 +#define CLM_PERIOD_MAX 65535 +/*NHM*/ +#define NHM_PERIOD_MAX 65534 +#define NHM_TH_NUM 11 /*threshold number of NHM*/ +#define NHM_RPT_NUM 12 +#define NHM_IC_NOISE_TH 60 /*60/2 - 10 = 20 = -80 dBm*/ +#define NHM_RPT_MAX 255 +#ifdef NHM_DYM_PW_TH_SUPPORT +#define DYM_PWTH_CCA_CAP 24 +#endif +#define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM/FAHM threshold = IGI * 2*/ +#define NTH_TH_2_RSSI(th) ((th >> 1) - 10) +/*FAHM*/ +#define FAHM_INCLU_FA BIT(0) +#define FAHM_INCLU_CRC_OK BIT(1) +#define FAHM_INCLU_CRC_ERR BIT(2) +#define FAHM_PERIOD_MAX 65534 +#define FAHM_TH_NUM 11 /*threshold number of FAHM*/ +#define FAHM_RPT_NUM 12 +/*IFS-CLM*/ +#define IFS_CLM_PERIOD_MAX 65535 +#define IFS_CLM_NUM 4 + +#define NHM_SUCCESS BIT(0) +#define CLM_SUCCESS BIT(1) +#define FAHM_SUCCESS BIT(2) +#define IFS_CLM_SUCCESS BIT(3) +#define ENV_MNTR_FAIL 0xff + +/* @1 ============================================================ + * 1 enumrate + * 1 ============================================================ + */ +enum phydm_clm_level { + CLM_RELEASE = 0, + CLM_LV_1 = 1, /* @Low Priority function */ + CLM_LV_2 = 2, /* @Middle Priority function */ + CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ + CLM_LV_4 = 4, /* @Debug function (the highest priority) */ + CLM_MAX_NUM = 5 +}; + +enum phydm_nhm_level { + NHM_RELEASE = 0, + NHM_LV_1 = 1, /* @Low Priority function */ + NHM_LV_2 = 2, /* @Middle Priority function */ + NHM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ + NHM_LV_4 = 4, /* @Debug function (the highest priority) */ + NHM_MAX_NUM = 5 +}; + +enum phydm_fahm_level { + FAHM_RELEASE = 0, + FAHM_LV_1 = 1, /* Low Priority function */ + FAHM_LV_2 = 2, /* Middle Priority function */ + FAHM_LV_3 = 3, /* High priority function (ex: Check hang function) */ + FAHM_LV_4 = 4, /* Debug function (the highest priority) */ + FAHM_MAX_NUM = 5 +}; + +enum phydm_ifs_clm_level { + IFS_CLM_RELEASE = 0, + IFS_CLM_LV_1 = 1, /* @Low Priority function */ + IFS_CLM_LV_2 = 2, /* @Middle Priority function */ + IFS_CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ + IFS_CLM_LV_4 = 4, /* @Debug function (the highest priority) */ + IFS_CLM_MAX_NUM = 5 +}; + +enum nhm_divider_opt_all { + NHM_CNT_ALL = 0, /*nhm SUM report <= 255*/ + NHM_VALID = 1, /*nhm SUM report = 255*/ + NHM_CNT_INIT +}; + +enum nhm_setting { + SET_NHM_SETTING, + STORE_NHM_SETTING, + RESTORE_NHM_SETTING +}; + +enum nhm_option_cca_all { + NHM_EXCLUDE_CCA = 0, + NHM_INCLUDE_CCA = 1, + NHM_CCA_INIT +}; + +enum nhm_option_txon_all { + NHM_EXCLUDE_TXON = 0, + NHM_INCLUDE_TXON = 1, + NHM_TXON_INIT +}; + +enum nhm_application { + NHM_BACKGROUND = 0,/*@default*/ + NHM_ACS = 1, + IEEE_11K_HIGH = 2, + IEEE_11K_LOW = 3, + INTEL_XBOX = 4, + NHM_DBG = 5, /*@manual trigger*/ +}; + +enum clm_application { + CLM_BACKGROUND = 0,/*@default*/ + CLM_ACS = 1, +}; + +enum fahm_application { + FAHM_BACKGROUND = 0,/*default*/ + FAHM_ACS = 1, + FAHM_DBG = 2, /*manual trigger*/ +}; + +enum ifs_clm_application { + IFS_CLM_BACKGROUND = 0,/*default*/ + IFS_CLM_ACS = 1, + IFS_CLM_HP_TAS = 2, + IFS_CLM_DBG = 3, +}; + +enum clm_monitor_mode { + CLM_DRIVER_MNTR = 1, + CLM_FW_MNTR = 2 +}; + +enum phydm_ifs_clm_unit { + IFS_CLM_4 = 0, /*4us*/ + IFS_CLM_8 = 1, /*8us*/ + IFS_CLM_12 = 2, /*12us*/ + IFS_CLM_16 = 3, /*16us*/ + IFS_CLM_INIT +}; + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct env_trig_rpt { + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; +}; + +struct env_mntr_rpt { + u8 nhm_ratio; + u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ + u8 nhm_result[NHM_RPT_NUM]; + u8 clm_ratio; + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; + u8 nhm_noise_pwr; /*including r[0]~r[10]*/ + u8 nhm_pwr; /*including r[0]~r[11]*/ +}; + +struct enhance_mntr_trig_rpt { + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; + u8 fahm_rpt_stamp; + u8 ifs_clm_rpt_stamp; +}; + +struct enhance_mntr_rpt { + u8 nhm_ratio; + u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ + u8 nhm_result[NHM_RPT_NUM]; + u8 clm_ratio; + u8 nhm_rpt_stamp; + u8 clm_rpt_stamp; + u8 nhm_noise_pwr; /*including r[0]~r[10]*/ + u8 nhm_pwr; /*including r[0]~r[11]*/ + u16 fahm_result[NHM_RPT_NUM]; + u8 fahm_rpt_stamp; + u8 fahm_pwr; + u8 fahm_ratio; + u8 fahm_denom_ratio; + u8 fahm_inclu_cck; + u8 ifs_clm_rpt_stamp; + u8 ifs_clm_tx_ratio; + u8 ifs_clm_edcca_excl_cca_ratio; + u8 ifs_clm_cck_fa_ratio; + u8 ifs_clm_cck_cca_excl_fa_ratio; + u8 ifs_clm_ofdm_fa_ratio; + u8 ifs_clm_ofdm_cca_excl_fa_ratio; +}; + +struct nhm_para_info { + enum nhm_option_txon_all incld_txon; /*@Include TX on*/ + enum nhm_option_cca_all incld_cca; /*@Include CCA*/ + enum nhm_divider_opt_all div_opt; /*@divider option*/ + enum nhm_application nhm_app; + enum phydm_nhm_level nhm_lv; + u16 mntr_time; /*@0~262 unit ms*/ + boolean en_1db_mode; + u8 nhm_th0_manual; /* for 1-db mode*/ +}; + +struct clm_para_info { + enum clm_application clm_app; + enum phydm_clm_level clm_lv; + u16 mntr_time; /*@0~262 unit ms*/ +}; + +struct fahm_para_info { + enum fahm_application app; + enum phydm_fahm_level lv; + u16 mntr_time; /*0~262 unit ms*/ + u8 numer_opt; + u8 denom_opt; + boolean en_1db_mode; + u8 th0_manual;/* for 1-db mode*/ +}; + +struct ifs_clm_para_info { + enum ifs_clm_application ifs_clm_app; + enum phydm_ifs_clm_level ifs_clm_lv; + enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*unit*/ + u16 mntr_time; /*ms*/ + boolean ifs_clm_th_en[IFS_CLM_NUM]; + u16 ifs_clm_th_low[IFS_CLM_NUM]; + u16 ifs_clm_th_high[IFS_CLM_NUM]; + s16 th_shift; +}; + +struct ccx_info { + u32 nhm_trigger_time; + u32 clm_trigger_time; + u32 fahm_trigger_time; + u32 ifs_clm_trigger_time; + u64 start_time; /*@monitor for the test duration*/ + u8 ccx_watchdog_result; +#ifdef NHM_SUPPORT + enum nhm_application nhm_app; + enum nhm_option_txon_all nhm_include_txon; + enum nhm_option_cca_all nhm_include_cca; + enum nhm_divider_opt_all nhm_divider_opt; + /*Report*/ + u8 nhm_th[NHM_TH_NUM]; + u8 nhm_result[NHM_RPT_NUM]; + u8 nhm_wgt[NHM_RPT_NUM]; + u16 nhm_period; /* @4us per unit */ + u8 nhm_igi; + u8 nhm_manual_ctrl; + u8 nhm_ratio; /*@1% per nuit, it means the interference igi can't overcome.*/ + u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ + u8 nhm_rpt_sum; + u8 nhm_set_lv; + boolean nhm_ongoing; + u8 nhm_rpt_stamp; + u8 nhm_level; /*including r[0]~r[10]*/ + u8 nhm_level_valid; + u8 nhm_pwr; /*including r[0]~r[11]*/ +#ifdef NHM_DYM_PW_TH_SUPPORT + boolean nhm_dym_pw_th_en; + boolean dym_pwth_manual_ctrl; + u8 pw_th_rf20_ori; + u8 pw_th_rf20_cur; + u8 nhm_pw_th_max; + u8 nhm_period_decre; + u8 nhm_sl_pw_th; +#endif +#endif + +#ifdef CLM_SUPPORT + enum clm_application clm_app; + u8 clm_manual_ctrl; + u8 clm_set_lv; + boolean clm_ongoing; + u16 clm_period; /* @4us per unit */ + u16 clm_result; + u8 clm_ratio; + u32 clm_fw_result_acc; + u8 clm_fw_result_cnt; + enum clm_monitor_mode clm_mntr_mode; + u8 clm_rpt_stamp; +#endif +#ifdef FAHM_SUPPORT + enum fahm_application fahm_app; + boolean fahm_ongoing; + u8 fahm_numer_opt; + u8 fahm_denom_opt; + boolean fahm_inclu_cck; + u8 fahm_th[NHM_TH_NUM]; + u16 fahm_result[NHM_RPT_NUM]; + u16 fahm_result_sum; + u16 fahm_denom_result; + u16 fahm_period; /*unit: 4us*/ + u8 fahm_igi; + u8 fahm_manual_ctrl; + u8 fahm_set_lv; + u8 fahm_rpt_stamp; + u8 fahm_pwr; /*including r[0]~r[11]*/ + u8 fahm_ratio; + u8 fahm_denom_ratio; +#endif +#ifdef IFS_CLM_SUPPORT + enum ifs_clm_application ifs_clm_app; + /*Control*/ + enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*4,8,12,16us per unit*/ + u16 ifs_clm_period; + boolean ifs_clm_th_en[IFS_CLM_NUM]; + u16 ifs_clm_th_low[IFS_CLM_NUM]; + u16 ifs_clm_th_high[IFS_CLM_NUM]; + /*Flow control*/ + u8 ifs_clm_set_lv; + u8 ifs_clm_manual_ctrl; + boolean ifs_clm_ongoing; + /*Report*/ + u8 ifs_clm_rpt_stamp; + u16 ifs_clm_tx; + u16 ifs_clm_edcca_excl_cca; + u16 ifs_clm_ofdmfa; + u16 ifs_clm_ofdmcca_excl_fa; + u16 ifs_clm_cckfa; + u16 ifs_clm_cckcca_excl_fa; + u8 ifs_clm_his[IFS_CLM_NUM]; /*trx_neg_edge to CCA/FA posedge per times*/ + u16 ifs_clm_total_cca; + u16 ifs_clm_avg[IFS_CLM_NUM]; /*4,8,12,16us per unit*/ + u16 ifs_clm_avg_cca[IFS_CLM_NUM]; /*4,8,12,16us per unit*/ + u8 ifs_clm_tx_ratio; + u8 ifs_clm_edcca_excl_cca_ratio; + u8 ifs_clm_cck_fa_ratio; + u8 ifs_clm_cck_cca_excl_fa_ratio; + u8 ifs_clm_ofdm_fa_ratio; + u8 ifs_clm_ofdm_cca_excl_fa_ratio; +#endif +}; + +/* @1 ============================================================ + * 1 Function Prototype + * 1 ============================================================ + */ + +u8 phydm_env_mntr_get_802_11_k_rsni(void *dm_void, s8 rcpi, s8 anpi); + +#ifdef FAHM_SUPPORT +void phydm_fahm_init(void *dm_void); + +void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); +#endif + +#ifdef NHM_SUPPORT +void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); +u8 phydm_get_igi(void *dm_void, enum bb_path path); +#endif + +#ifdef CLM_SUPPORT +void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); +#endif + +u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct env_trig_rpt *rpt); + +u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt); + +void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +#ifdef IFS_CLM_SUPPORT +void phydm_ifs_clm_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif + +u8 phydm_enhance_mntr_trigger(void *dm_void, + struct nhm_para_info *nhm_para, + struct clm_para_info *clm_para, + struct fahm_para_info *fahm_para, + struct ifs_clm_para_info *ifs_clm_para, + struct enhance_mntr_trig_rpt *trig_rpt); + +u8 phydm_enhance_mntr_result(void *dm_void, struct enhance_mntr_rpt *rpt); + +void phydm_enhance_mntr_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_env_mntr_result_watchdog(void *dm_void); + +void phydm_env_mntr_set_watchdog(void *dm_void); + +void phydm_env_monitor_init(void *dm_void); + +#endif diff --git a/hal/phydm/phydm_cfotracking.c b/hal/phydm/phydm_cfotracking.c new file mode 100644 index 0000000..68731db --- /dev/null +++ b/hal/phydm/phydm_cfotracking.c @@ -0,0 +1,623 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +s32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num) +{ + s32 val_s = 0; + + val_s = phydm_cnvrt_2_sign(val, bit_num); + + if (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/ + val_s *= 305; + else if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/ + val_s *= 152; + else if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/ + val_s *= 76; + + return val_s; +} + +#if (ODM_IC_11AC_SERIES_SUPPORT) +void phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + u32 val[4] = {0}; + u32 val_1[4] = {0}; + u32 val_2[4] = {0}; + u32 val_tmp = 0; + + val[0] = odm_read_4byte(dm, R_0xd0c); + val_1[0] = odm_read_4byte(dm, R_0xd10); + val_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + val[1] = odm_read_4byte(dm, R_0xd4c); + val_1[1] = odm_read_4byte(dm, R_0xd50); + val_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + val[2] = odm_read_4byte(dm, R_0xd8c); + val_1[2] = odm_read_4byte(dm, R_0xd90); + val_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + val[3] = odm_read_4byte(dm, R_0xdcc); + val_1[3] = odm_read_4byte(dm, R_0xdd0); + val_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000); + #endif + + for (i = 0; i < dm->num_rf_path; i++) { + val_tmp = val[i] & 0xfff; /*@ Short CFO, S(12,11)*/ + cfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + + val_tmp = val[i] >> 16; /*@ Long CFO, S(13,12)*/ + cfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + + val_tmp = val_1[i] & 0x7ff; /*@ SCFO, S(11,10)*/ + cfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10); + + val_tmp = val_1[i] >> 16; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + + val_tmp = val_2[i]; /*@ End CFO, S(13,12)*/ + cfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + } +} +#endif + +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val[5] = {0}; + u32 val_tmp = 0; + + odm_set_bb_reg(dm, R_0xd00, BIT(26), 1); + + val[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/ + val[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/ + val[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/ + val[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/ + val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/ + + /*@[path-A]*/ + if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) { + val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/ + cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = (val[1] & 0x0fff0000) >> 16; /*@ Long CFO, S(12,11)*/ + cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = (val[2] & 0x0fff0000) >> 16; /*@ Sec CFO, S(12,11)*/ + cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = (val[3] & 0x0fff0000) >> 16; /*@ Acq CFO, S(12,11)*/ + cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = (val[4] & 0x0fff0000) >> 16; /*@ Acq CFO, S(12,11)*/ + cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + } else { + val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/ + cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = (val[1] & 0x1fff0000) >> 16; /*@ Long CFO, S(13,12)*/ + cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = (val[2] & 0x7ff0000) >> 16; /*@ Sec CFO, S(11,10)*/ + cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10); + val_tmp = (val[3] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = (val[4] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + } + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + /*@[path-B]*/ + val_tmp = val[0] & 0xfff; /*@ Short CFO, S(12,11)*/ + cfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11); + val_tmp = val[1] & 0x1fff; /*@ Long CFO, S(13,12)*/ + cfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = val[2] & 0x7ff; /*@ Sec CFO, S(11,10)*/ + cfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10); + val_tmp = val[3] & 0x1fff; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + val_tmp = val[4] & 0x1fff; /*@ Acq CFO, S(13,12)*/ + cfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12); + #endif +} + +void phydm_set_atc_status(void *dm_void, boolean atc_status) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + u32 reg_tmp = 0; + u32 mask_tmp = 0; + + PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]ATC_en=%d\n", __func__, atc_status); + + if (cfo_track->is_atc_status == atc_status) + return; + + reg_tmp = ODM_REG(BB_ATC, dm); + mask_tmp = ODM_BIT(BB_ATC, dm); + odm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status); + cfo_track->is_atc_status = atc_status; +} + +boolean +phydm_get_atc_status(void *dm_void) +{ + boolean atc_status = false; + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_tmp = 0; + u32 mask_tmp = 0; + + reg_tmp = ODM_REG(BB_ATC, dm); + mask_tmp = ODM_BIT(BB_ATC, dm); + + atc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp); + + PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]atc_status=%d\n", __func__, atc_status); + return atc_status; +} +#endif + +void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + switch (dm->ic_ip_series) { + #if (ODM_IC_11N_SERIES_SUPPORT) + case PHYDM_IC_N: + phydm_get_cfo_info_n(dm, cfo); + break; + #endif + #if (ODM_IC_11AC_SERIES_SUPPORT) + case PHYDM_IC_AC: + phydm_get_cfo_info_ac(dm, cfo); + break; + #endif + default: + break; + } +} + +boolean +phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + u32 reg_val = 0; + + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | + ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D | ODM_RTL8710C|ODM_RTL8723F)) { + crystal_cap &= 0x7F; + reg_val = crystal_cap | (crystal_cap << 7); + } else { + crystal_cap &= 0x3F; + reg_val = crystal_cap | (crystal_cap << 6); + } + + cfo_track->crystal_cap = crystal_cap; + + if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) { + #if (RTL8188E_SUPPORT || RTL8188F_SUPPORT) + /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */ + odm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val); + #endif + } + #if (RTL8812A_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8812) { + /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */ + odm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val); + } + #endif + #if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8821A_SUPPORT || RTL8723D_SUPPORT) + else if ((dm->support_ic_type & + (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | + ODM_RTL8723D))) { + /* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */ + odm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val); + } + #endif + #if (RTL8814A_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8814A) { + /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */ + odm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val); + } + #endif + #if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT || RTL8197G_SUPPORT || RTL8198F_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | + ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8197G | ODM_RTL8198F)) { + /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */ + odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap); + odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap); + } + #endif + #if (RTL8710B_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8710B)) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + /* write 0x60[29:24] = 0x60[23:18] = crystal_cap */ + HAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val); + #endif + } + #endif + #if (RTL8195B_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8195B) { + phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f)); + } + #endif + #if (RTL8721D_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8721D)) { + /* write 0x4800_0228[30:24] crystal_cap */ + /*HAL_SetSYSOnReg(dm->adapter, */ + /*REG_SYS_XTAL_8721d, 0x7F000000, crystal_cap);*/ + u32 temp_val = HAL_READ32(SYSTEM_CTRL_BASE_LP, + REG_SYS_EFUSE_SYSCFG2); + temp_val = ((crystal_cap << 24) & 0x7F000000) + | (temp_val & (~0x7F000000)); + HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG2, + temp_val); + } + #endif + #if (RTL8710C_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8710C)) { + /* write MAC reg 0x28[13:7][6:0] crystal_cap */ + phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f)); + } + #endif + #if (RTL8723F_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8723F) { + /* write 0x103c[23:17] = 0x103c[16:10] = crystal_cap */ + odm_set_mac_reg(dm, R_0x103c, 0x00FFFC00, reg_val); + } + #endif +#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | + ODM_RTL8812F)) { + /* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */ + odm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val); + } else { + return false; + } +#endif + return true; +} + +void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + + if (cfo_track->crystal_cap == crystal_cap) + return; + + if (phydm_set_crystal_cap_reg(dm, crystal_cap)) + PHYDM_DBG(dm, DBG_CFO_TRK, "Set crystal_cap = 0x%x\n", + cfo_track->crystal_cap); + else + PHYDM_DBG(dm, DBG_CFO_TRK, "Set fail\n"); +} + +void phydm_cfo_tracking_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + + PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__); + + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B | + ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F)) + cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7f; + else + cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f; + + cfo_track->is_adjust = true; + + if (cfo_track->crystal_cap > cfo_track->def_x_cap) { + phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1); + PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n", + cfo_track->crystal_cap); + + } else if (cfo_track->crystal_cap < cfo_track->def_x_cap) { + phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1); + PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n", + cfo_track->crystal_cap); + } + +#if ODM_IC_11N_SERIES_SUPPORT +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->support_ic_type & ODM_IC_11N_SERIES) + phydm_set_atc_status(dm, true); +#endif +#endif +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP)) + if (dm->support_ic_type & ODM_RTL8814B) { + /*Disable advance time for CFO residual*/ + odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0); + } +#endif +#endif +} + +void phydm_cfo_tracking_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + + PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__); + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B | + ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F)) + cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7f; + else + cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f; + + cfo_track->def_x_cap = cfo_track->crystal_cap; + cfo_track->is_adjust = true; + PHYDM_DBG(dm, DBG_CFO_TRK, "crystal_cap=0x%x\n", cfo_track->def_x_cap); + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + /* @Crystal cap. control by WiFi */ + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) + odm_set_mac_reg(dm, R_0x10, 0x40, 0x1); +#endif +} + +void phydm_cfo_tracking(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + s32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0; + u32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0}; + s8 crystal_cap = cfo_track->crystal_cap; + u8 i = 0, valid_path_cnt = 0; + + if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) + return; + + PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__); + + if (!dm->is_linked || !dm->is_one_entry_only) { + phydm_cfo_tracking_reset(dm); + PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked=%d, one_entry_only=%d\n", + dm->is_linked, dm->is_one_entry_only); + + } else { + /* No new packet */ + if (cfo_track->packet_count == cfo_track->packet_count_pre) { + PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n"); + return; + } + cfo_track->packet_count_pre = cfo_track->packet_count; + + /*@Calculate CFO */ + for (i = 0; i < dm->num_rf_path; i++) { + if (!(dm->rx_ant_status & BIT(i))) + continue; + + valid_path_cnt++; + + if (cfo_track->CFO_tail[i] < 0) + cfo_abs = 0 - cfo_track->CFO_tail[i]; + else + cfo_abs = cfo_track->CFO_tail[i]; + + cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs); + cfo_khz_avg[i] = PHYDM_DIV(cfo_rpt_sum, + cfo_track->CFO_cnt[i]); + + PHYDM_DBG(dm, DBG_CFO_TRK, + "[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n", + i, cfo_rpt_sum, cfo_track->CFO_cnt[i], + ((cfo_track->CFO_tail[i] < 0) ? "-" : " "), + cfo_khz_avg[i]); + + if (cfo_track->CFO_tail[i] < 0) + cfo_path_sum += (0 - (s32)cfo_khz_avg[i]); + else + cfo_path_sum += (s32)cfo_khz_avg[i]; + } + + if (valid_path_cnt >= 2) + cfo_avg = cfo_path_sum / valid_path_cnt; + else + cfo_avg = cfo_path_sum; + + cfo_track->CFO_ave_pre = cfo_avg; + + PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt=%d, CFO_avg_path=%d kHz\n", + valid_path_cnt, cfo_avg); + + /*reset counter*/ + for (i = 0; i < dm->num_rf_path; i++) { + cfo_track->CFO_tail[i] = 0; + cfo_track->CFO_cnt[i] = 0; + } + + /* To adjust crystal cap or not */ + if (!cfo_track->is_adjust) { + if (cfo_avg > CFO_TRK_ENABLE_TH || + cfo_avg < (-CFO_TRK_ENABLE_TH)) + cfo_track->is_adjust = true; + } else { + if (cfo_avg <= CFO_TRK_STOP_TH && + cfo_avg >= (-CFO_TRK_STOP_TH)) + cfo_track->is_adjust = false; + } + + #ifdef ODM_CONFIG_BT_COEXIST + /*@BT case: Disable CFO tracking */ + if (dm->bt_info_table.is_bt_enabled) { + cfo_track->is_adjust = false; + phydm_set_crystal_cap(dm, cfo_track->def_x_cap); + PHYDM_DBG(dm, DBG_CFO_TRK, "[BT]Disable CFO_track\n"); + } + #endif + + /*@Adjust Crystal Cap. */ + if (cfo_track->is_adjust) { + if (cfo_avg > CFO_TRK_STOP_TH) + crystal_cap += 1; + else if (cfo_avg < (-CFO_TRK_STOP_TH)) + crystal_cap -= 1; + + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | + ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F)) { + if (crystal_cap > 0x7F) + crystal_cap = 0x7F; + } else { + if (crystal_cap > 0x3F) + crystal_cap = 0x3F; + } + if (crystal_cap < 0) + crystal_cap = 0; + + phydm_set_crystal_cap(dm, (u8)crystal_cap); + } + + PHYDM_DBG(dm, DBG_CFO_TRK, "X_cap{Curr,Default}={0x%x,0x%x}\n", + cfo_track->crystal_cap, cfo_track->def_x_cap); + + /* @Dynamic ATC switch */ + #if ODM_IC_11N_SERIES_SUPPORT + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC) + phydm_set_atc_status(dm, false); + else + phydm_set_atc_status(dm, true); + + } + #endif + #endif + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP)) + if (dm->support_ic_type & ODM_RTL8814B) { + //Disable advance time for CFO residual + odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0); + } + #endif + #endif + } +} + +void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail, + u8 num_ss) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + boolean valid_info = false; + u8 i = 0; + + if (!(dm->support_ability & ODM_BB_CFO_TRACKING)) + return; + + pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT)) + if (pktinfo->is_packet_match_bssid) + valid_info = true; +#else + if (dm->number_active_client == 1) + valid_info = true; +#endif + if (valid_info) { + if (num_ss > dm->num_rf_path) /*@For fool proof*/ + num_ss = dm->num_rf_path; + #if 0 + PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss=%d, num_rf_path=%d\n", + num_ss, dm->num_rf_path); + #endif + + /* @ Update CFO report for path-A & path-B */ + /* Only paht-A and path-B have CFO tail and short CFO */ + for (i = 0; i < dm->num_rf_path; i++) { + if (!(dm->rx_ant_status & BIT(i))) + continue; + cfo_track->CFO_tail[i] += pcfotail[i]; + cfo_track->CFO_cnt[i]++; + #if 0 + PHYDM_DBG(dm, DBG_CFO_TRK, + "[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n", + pktinfo->station_id, i, pktinfo->data_rate, + pcfotail[i], cfo_track->CFO_tail[i], + cfo_track->CFO_cnt[i]); + #endif + } + + /* @ Update packet counter */ + if (cfo_track->packet_count == 0xffffffff) + cfo_track->packet_count = 0; + else + cfo_track->packet_count++; + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!phydm_set_crystal_cap_reg(dm, crystal_cap)) + RT_TRACE_F(COMP_INIT, DBG_SERIOUS, + ("Crystal is not initialized!\n")); +} +#endif + +void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "set Xcap: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "show Xcap: {100}\n"); + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + phydm_set_crystal_cap(dm, (u8)var1[1]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set X_cap=0x%x\n", cfo_track->crystal_cap); + } else if (var1[0] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "X_cap=0x%x\n", cfo_track->crystal_cap); + } + } + *_used = used; + *_out_len = out_len; +} + diff --git a/hal/phydm/phydm_cfotracking.h b/hal/phydm/phydm_cfotracking.h new file mode 100644 index 0000000..253f3ba --- /dev/null +++ b/hal/phydm/phydm_cfotracking.h @@ -0,0 +1,74 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMCFOTRACK_H__ +#define __PHYDMCFOTRACK_H__ + +/* 2019.03.28 fix 8197G crystal_cap register address*/ +#define CFO_TRACKING_VERSION "2.4" + +#define CFO_TRK_ENABLE_TH 20 /* @kHz enable CFO_Track threshold*/ +#define CFO_TRK_STOP_TH 10 /* @kHz disable CFO_Track threshold*/ +#define CFO_TH_ATC 80 /* @kHz */ + +struct phydm_cfo_track_struct { + boolean is_atc_status; + boolean is_adjust; /*@already modify crystal cap*/ + u8 crystal_cap; + u8 crystal_cap_default; + u8 def_x_cap; + s32 CFO_tail[4]; + u32 CFO_cnt[4]; + s32 CFO_ave_pre; + u32 packet_count; + u32 packet_count_pre; +}; + +struct phydm_cfo_rpt { + s32 cfo_rpt_s[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_l[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_acq[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_sec[PHYDM_MAX_RF_PATH]; + s32 cfo_rpt_end[PHYDM_MAX_RF_PATH]; +}; + +void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo); + +boolean phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap); + +void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap); + +void phydm_cfo_tracking_init(void *dm_void); + +void phydm_cfo_tracking(void *dm_void); + +void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail, + u8 num_ss); +void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap); +#endif +#endif diff --git a/hal/phydm/phydm_debug.c b/hal/phydm/phydm_debug.c new file mode 100644 index 0000000..6d47868 --- /dev/null +++ b/hal/phydm/phydm_debug.c @@ -0,0 +1,6177 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void phydm_init_debug_setting(struct dm_struct *dm) +{ + dm->fw_debug_components = 0; + dm->debug_components = + +#if DBG + /*@BB Functions*/ + /*@DBG_DIG |*/ + /*@DBG_RA_MASK |*/ + /*@DBG_DYN_TXPWR |*/ + /*@DBG_FA_CNT |*/ + /*@DBG_RSSI_MNTR |*/ + /*@DBG_CCKPD |*/ + /*@DBG_ANT_DIV |*/ + /*@DBG_SMT_ANT |*/ + /*@DBG_PWR_TRAIN |*/ + /*@DBG_RA |*/ + /*@DBG_PATH_DIV |*/ + /*@DBG_DFS |*/ + /*@DBG_DYN_ARFR |*/ + /*@DBG_ADPTVTY |*/ + /*@DBG_CFO_TRK |*/ + /*@DBG_ENV_MNTR |*/ + /*@DBG_PRI_CCA |*/ + /*@DBG_ADPTV_SOML |*/ + /*@DBG_LNA_SAT_CHK |*/ + /*@DBG_PHY_STATUS |*/ + /*@DBG_TMP |*/ + /*@DBG_FW_TRACE |*/ + /*@DBG_TXBF |*/ + /*@DBG_COMMON_FLOW |*/ + /*@ODM_PHY_CONFIG |*/ + /*@ODM_COMP_INIT |*/ + /*@DBG_CMN |*/ + /*@ODM_COMP_API |*/ +#endif + 0; + + dm->fw_buff_is_enpty = true; + dm->pre_c2h_seq = 0; + dm->c2h_cmd_start = 0; + dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD; + dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD; + phydm_reset_rx_rate_distribution(dm); +} + +void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x8f8, 0x3c00000, header_idx); + + /*@ + * header_idx: + * (0:) '{ofdm_dbg[31:0]}' + * (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}' + * (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}' + * (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}' + * (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}' + * (5:) '{dbg_iqk_anta}' + * (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}' + * (7:) '{dbg_iqk_antb}' + * (8:) '{DBGOUT_RFC_b[31:0]}' + * (9:) '{DBGOUT_RFC_a[31:0]}' + * (a:) '{dbg_ofdm}' + * (b:) '{dbg_cck}' + */ + } +} + +void phydm_bb_dbg_port_clock_en(void *dm_void, u8 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_value = 0; + + if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) { + /*@enable/disable debug port clock, for power saving*/ + reg_value = enable ? 0x7 : 0; + odm_set_bb_reg(dm, R_0x198c, 0x7, reg_value); + } +} + +u32 phydm_get_bb_dbg_port_idx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_bb_dbg_port_clock_en(dm, true); + val = odm_get_bb_reg(dm, R_0x8fc, MASKDWORD); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + val = odm_get_bb_reg(dm, R_0x1c3c, 0xfff00); + } else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ + val = odm_get_bb_reg(dm, R_0x908, MASKDWORD); + } + return val; +} + +u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 dbg_port_result = false; + + if (curr_dbg_priority > dm->pre_dbg_priority) { + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + phydm_bb_dbg_port_clock_en(dm, true); + + odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, debug_port); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0x1c3c, 0xfff00, debug_port); + } else { /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ + odm_set_bb_reg(dm, R_0x908, MASKDWORD, debug_port); + } + PHYDM_DBG(dm, ODM_COMP_API, + "DbgPort ((0x%x)) set success, Cur_priority=((%d)), Pre_priority=((%d))\n", + debug_port, curr_dbg_priority, dm->pre_dbg_priority); + dm->pre_dbg_priority = curr_dbg_priority; + dbg_port_result = true; + } + + return dbg_port_result; +} + +void phydm_release_bb_dbg_port(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_bb_dbg_port_clock_en(dm, false); + phydm_bb_dbg_port_header_sel(dm, 0); + + dm->pre_dbg_priority = DBGPORT_RELEASE; + PHYDM_DBG(dm, ODM_COMP_API, "Release BB dbg_port\n"); +} + +u32 phydm_get_bb_dbg_port_val(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 dbg_port_value = 0; + + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + dbg_port_value = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD); + else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + dbg_port_value = odm_get_bb_reg(dm, R_0x2dbc, MASKDWORD); + else /*@if (dm->support_ic_type & ODM_IC_11N_SERIES)*/ + dbg_port_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD); + + PHYDM_DBG(dm, ODM_COMP_API, "dbg_port_value = 0x%x\n", dbg_port_value); + return dbg_port_value; +} + +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_bb_hw_dbg_info_n(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 value32 = 0, value32_1 = 0; + u8 rf_gain_a = 0, rf_gain_b = 0, rf_gain_c = 0, rf_gain_d = 0; + u8 rx_snr_a = 0, rx_snr_b = 0, rx_snr_c = 0, rx_snr_d = 0; + s8 rxevm_0 = 0, rxevm_1 = 0; + #if 1 + struct phydm_cfo_rpt cfo; + u8 i = 0; + #else + s32 short_cfo_a = 0, short_cfo_b = 0, long_cfo_a = 0, long_cfo_b = 0; + s32 scfo_a = 0, scfo_b = 0, avg_cfo_a = 0, avg_cfo_b = 0; + s32 cfo_end_a = 0, cfo_end_b = 0, acq_cfo_a = 0, acq_cfo_b = 0; + #endif + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n", + "BB Report Info"); + + /*@AGC result*/ + value32 = odm_get_bb_reg(dm, R_0xdd0, MASKDWORD); + rf_gain_a = (u8)(value32 & 0x3f); + rf_gain_a = rf_gain_a << 1; + + rf_gain_b = (u8)((value32 >> 8) & 0x3f); + rf_gain_b = rf_gain_b << 1; + + rf_gain_c = (u8)((value32 >> 16) & 0x3f); + rf_gain_c = rf_gain_c << 1; + + rf_gain_d = (u8)((value32 >> 24) & 0x3f); + rf_gain_d = rf_gain_d << 1; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", + rf_gain_a, rf_gain_b, rf_gain_c, rf_gain_d); + + /*SNR report*/ + value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD); + rx_snr_a = (u8)(value32 & 0xff); + rx_snr_a = rx_snr_a >> 1; + + rx_snr_b = (u8)((value32 >> 8) & 0xff); + rx_snr_b = rx_snr_b >> 1; + + rx_snr_c = (u8)((value32 >> 16) & 0xff); + rx_snr_c = rx_snr_c >> 1; + + rx_snr_d = (u8)((value32 >> 24) & 0xff); + rx_snr_d = rx_snr_d >> 1; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", + rx_snr_a, rx_snr_b, rx_snr_c, rx_snr_d); + + /* PostFFT related info*/ + value32 = odm_get_bb_reg(dm, R_0xdd8, MASKDWORD); + + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 /= 2; + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 /= 2; + if (rxevm_1 < -63) + rxevm_1 = 0; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "RXEVM (1ss/2ss)", rxevm_0, rxevm_1); + +#if 1 + phydm_get_cfo_info(dm, &cfo); + for (i = 0; i < dm->num_rf_path; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}", + "CFO", i, "{S, L, Sec, Acq, End}", + cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i], + cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]); + } +#else + /*@CFO Report Info*/ + odm_set_bb_reg(dm, R_0xd00, BIT(26), 1); + + /*Short CFO*/ + value32 = odm_get_bb_reg(dm, R_0xdac, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xdb0, MASKDWORD); + + short_cfo_b = (s32)(value32 & 0xfff); /*S(12,11)*/ + short_cfo_a = (s32)((value32 & 0x0fff0000) >> 16); + + long_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + long_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); + + /*SFO 2's to dec*/ + if (short_cfo_a > 2047) + short_cfo_a = short_cfo_a - 4096; + if (short_cfo_b > 2047) + short_cfo_b = short_cfo_b - 4096; + + short_cfo_a = (short_cfo_a * 312500) / 2048; + short_cfo_b = (short_cfo_b * 312500) / 2048; + + /*@LFO 2's to dec*/ + + if (long_cfo_a > 4095) + long_cfo_a = long_cfo_a - 8192; + + if (long_cfo_b > 4095) + long_cfo_b = long_cfo_b - 8192; + + long_cfo_a = long_cfo_a * 312500 / 4096; + long_cfo_b = long_cfo_b * 312500 / 4096; + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s", + "CFO Report Info"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Short CFO(Hz) ", short_cfo_a, + short_cfo_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Long CFO(Hz) ", long_cfo_a, + long_cfo_b); + + /*SCFO*/ + value32 = odm_get_bb_reg(dm, R_0xdb8, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xdb4, MASKDWORD); + + scfo_b = (s32)(value32 & 0x7ff); /*S(11,10)*/ + scfo_a = (s32)((value32 & 0x07ff0000) >> 16); + + if (scfo_a > 1023) + scfo_a = scfo_a - 2048; + + if (scfo_b > 1023) + scfo_b = scfo_b - 2048; + + scfo_a = scfo_a * 312500 / 1024; + scfo_b = scfo_b * 312500 / 1024; + + avg_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + avg_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); + + if (avg_cfo_a > 4095) + avg_cfo_a = avg_cfo_a - 8192; + + if (avg_cfo_b > 4095) + avg_cfo_b = avg_cfo_b - 8192; + + avg_cfo_a = avg_cfo_a * 312500 / 4096; + avg_cfo_b = avg_cfo_b * 312500 / 4096; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "value SCFO(Hz) ", scfo_a, + scfo_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "Avg CFO(Hz) ", avg_cfo_a, + avg_cfo_b); + + value32 = odm_get_bb_reg(dm, R_0xdbc, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xde0, MASKDWORD); + + cfo_end_b = (s32)(value32 & 0x1fff); /*S(13,12)*/ + cfo_end_a = (s32)((value32 & 0x1fff0000) >> 16); + + if (cfo_end_a > 4095) + cfo_end_a = cfo_end_a - 8192; + + if (cfo_end_b > 4095) + cfo_end_b = cfo_end_b - 8192; + + cfo_end_a = cfo_end_a * 312500 / 4096; + cfo_end_b = cfo_end_b * 312500 / 4096; + + acq_cfo_b = (s32)(value32_1 & 0x1fff); /*S(13,12)*/ + acq_cfo_a = (s32)((value32_1 & 0x1fff0000) >> 16); + + if (acq_cfo_a > 4095) + acq_cfo_a = acq_cfo_a - 8192; + + if (acq_cfo_b > 4095) + acq_cfo_b = acq_cfo_b - 8192; + + acq_cfo_a = acq_cfo_a * 312500 / 4096; + acq_cfo_b = acq_cfo_b * 312500 / 4096; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "End CFO(Hz) ", cfo_end_a, + cfo_end_b); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "ACQ CFO(Hz) ", acq_cfo_a, + acq_cfo_b); +#endif +} +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT) +#if (RTL8822B_SUPPORT) +void phydm_bb_hw_dbg_info_8822b(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 condi_num = 0; + u8 i = 0; + + if (!(dm->support_ic_type == ODM_RTL8822B)) + return; + + condi_num = phydm_get_condi_num_8822b(dm); + phydm_get_condi_num_acc_8822b(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d.%.4d", "condi_num", + condi_num >> 4, phydm_show_fraction_num(condi_num & 0xf, 4)); + + for (i = 0; i < CN_CNT_MAX; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n Tone_num[CN>%d]%-21s = %d", + i, " ", dm->phy_dbg_info.condi_num_cdf[i]); + } + + *_used = used; + *_out_len = out_len; +} +#endif + +void phydm_bb_hw_dbg_info_ac(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + char *tmp_string = NULL; + u8 rx_ht_bw, rx_vht_bw, rxsc, rx_ht, bw_idx = 0; + static u8 v_rx_bw; + u32 value32, value32_1, value32_2, value32_3; + struct phydm_cfo_rpt cfo; + u8 i = 0; + static u8 tail, parity, rsv, vrsv, smooth, htsound, agg; + static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts; + static u8 vtxops, vrsv2, vbrsv, bf, vbcrc; + static u16 h_length, htcrc8, length; + static u16 vpaid; + static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail; + static u8 hmcss, hrx_bw; + u8 pwdb; + s8 rxevm_0, rxevm_1, rxevm_2; + u8 rf_gain[4]; + u8 rx_snr[4]; + s32 sig_power; + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n", + "BB Report Info"); + + /*@ [BW & Mode] =====================================================*/ + + value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD); + rx_ht = (u8)((value32 & 0x180) >> 7); + + if (rx_ht == AD_VHT_MODE) { + tmp_string = "VHT"; + bw_idx = (u8)((value32 >> 1) & 0x3); + } else if (rx_ht == AD_HT_MODE) { + tmp_string = "HT"; + bw_idx = (u8)(value32 & 0x1); + } else { + tmp_string = "Legacy"; + bw_idx = 0; + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s %s %dM", "mode", tmp_string, (20 << bw_idx)); + + if (rx_ht != AD_LEGACY_MODE) { + rxsc = (u8)(value32 & 0x78); + + if (rxsc == 0) + tmp_string = "duplicate/full bw"; + else if (rxsc == 1) + tmp_string = "usc20-1"; + else if (rxsc == 2) + tmp_string = "lsc20-1"; + else if (rxsc == 3) + tmp_string = "usc20-2"; + else if (rxsc == 4) + tmp_string = "lsc20-2"; + else if (rxsc == 9) + tmp_string = "usc40"; + else if (rxsc == 10) + tmp_string = "lsc40"; + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s", tmp_string); + } + + /*@ [RX signal power and AGC related info] ==========================*/ + + pwdb = (u8)odm_get_bb_reg(dm, R_0xf90, MASKBYTE1); + sig_power = -110 + (pwdb >> 1); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power); + + value32 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD); + rx_snr[RF_PATH_A] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_A] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); + + value32 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD); + rx_snr[RF_PATH_B] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_B] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); + + value32 = odm_get_bb_reg(dm, R_0xd94, MASKDWORD); + rx_snr[RF_PATH_C] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_C] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); + + value32 = odm_get_bb_reg(dm, R_0xdd4, MASKDWORD); + rx_snr[RF_PATH_D] = (u8)(value32 & 0xFF) >> 1; /*@ S(8,1)*/ + rf_gain[RF_PATH_D] = (s8)(((value32 & MASKBYTE1) >> 8) * 2); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", + rf_gain[RF_PATH_A], rf_gain[RF_PATH_B], + rf_gain[RF_PATH_C], rf_gain[RF_PATH_D]); + + /*@ [RX counter Info] ===============================================*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM CCA cnt", + odm_get_bb_reg(dm, R_0xf08, 0xFFFF0000)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM SBD Fail cnt", + odm_get_bb_reg(dm, R_0xfd0, 0xFFFF)); + + value32 = odm_get_bb_reg(dm, R_0xfc4, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "CCK CCA cnt", + odm_get_bb_reg(dm, R_0xfcc, 0xFFFF)); + + value32 = odm_get_bb_reg(dm, R_0xfbc, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", + "LSIG (parity Fail/rate Illegal) cnt", value32 & 0xFFFF, + ((value32 & 0xFFFF0000) >> 16)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt", + odm_get_bb_reg(dm, R_0xfc0, (0xFFFF0000 >> 16)), + odm_get_bb_reg(dm, R_0xfc8, 0xFFFF)); + + /*@ [PostFFT Info] =================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD); + rxevm_0 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_0 /= 2; + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((value32 & MASKBYTE3) >> 24); + rxevm_1 /= 2; + value32 = odm_get_bb_reg(dm, R_0xf88, MASKDWORD); + rxevm_2 = (s8)((value32 & MASKBYTE2) >> 16); + rxevm_2 /= 2; + + if (rxevm_1 < -63) + rxevm_1 = 0; + if (rxevm_2 < -63) + rxevm_2 = 0; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", rxevm_0, + rxevm_1, rxevm_2); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D dB)", + rx_snr[RF_PATH_A], rx_snr[RF_PATH_B], + rx_snr[RF_PATH_C], rx_snr[RF_PATH_D]); + + value32 = odm_get_bb_reg(dm, R_0xf8c, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32 & 0xFFFF, + ((value32 & 0xFFFF0000) >> 16)); + + /*@ [CFO Report Info] ===============================================*/ + phydm_get_cfo_info(dm, &cfo); + for (i = 0; i < dm->num_rf_path; i++) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %s[%d] %-28s = {%d, %d, %d, %d, %d}", + "CFO", i, "{S, L, Sec, Acq, End}", + cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], cfo.cfo_rpt_sec[i], + cfo.cfo_rpt_acq[i], cfo.cfo_rpt_end[i]); + } + + /*@ [L-SIG Content] =================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf20, MASKDWORD); + + tail = (u8)((value32 & 0xfc0000) >> 18);/*@[23:18]*/ + parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/ + length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/ + rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s", + "L-SIG"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d M", "rate", + phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f))); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length, + parity); + + if (rx_ht == AD_HT_MODE) { + /*@ [HT SIG 1] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD); + + hmcss = (u8)(value32 & 0x7F); + hrx_bw = (u8)((value32 & 0x80) >> 7); + h_length = (u16)((value32 & 0x0fff00) >> 8); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "HT-SIG1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d", "MCS/BW/length", + hmcss, hrx_bw, h_length); + /*@ [HT SIG 2] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD); + smooth = (u8)(value32 & 0x01); + htsound = (u8)((value32 & 0x02) >> 1); + rsv = (u8)((value32 & 0x04) >> 2); + agg = (u8)((value32 & 0x08) >> 3); + stbc = (u8)((value32 & 0x30) >> 4); + fec = (u8)((value32 & 0x40) >> 6); + sgi = (u8)((value32 & 0x80) >> 7); + htltf = (u8)((value32 & 0x300) >> 8); + htcrc8 = (u16)((value32 & 0x3fc00) >> 10); + tail = (u8)((value32 & 0xfc0000) >> 18); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "HT-SIG2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x", + "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", + smooth, htsound, rsv, agg, stbc, fec); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "SGI/E-HT-LTFs/CRC/tail", + sgi, htltf, htcrc8, tail); + } else if (rx_ht == AD_VHT_MODE) { + /*@ [VHT SIG A1] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf2c, MASKDWORD); + + v_rx_bw = (u8)(value32 & 0x03); + vrsv = (u8)((value32 & 0x04) >> 2); + vstbc = (u8)((value32 & 0x08) >> 3); + vgid = (u8)((value32 & 0x3f0) >> 4); + v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1); + vpaid = (u16)((value32 & 0x3fe000) >> 13); + vtxops = (u8)((value32 & 0x400000) >> 22); + vrsv2 = (u8)((value32 & 0x800000) >> 23); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "VHT-SIG-A1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", + "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, + vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2); + + /*@ [VHT SIG A2] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf30, MASKDWORD); + + /* @sgi=(u8)(value32&0x01); */ + sgiext = (u8)(value32 & 0x03); + /* @fec = (u8)(value32&0x04); */ + fecext = (u8)((value32 & 0x0C) >> 2); + + v_mcss = (u8)((value32 & 0xf0) >> 4); + bf = (u8)((value32 & 0x100) >> 8); + vrsv = (u8)((value32 & 0x200) >> 9); + vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10); + v_tail = (u8)((value32 & 0xfc0000) >> 18); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-A2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", + "SGI/FEC/MCS/BF/Rsv/CRC/tail", + sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail); + + /*@ [VHT SIG B] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0xf34, MASKDWORD); + + #if 0 + v_length = (u16)(value32 & 0x1fffff); + vbrsv = (u8)((value32 & 0x600000) >> 21); + vb_tail = (u16)((value32 & 0x1f800000) >> 23); + vbcrc = (u8)((value32 & 0x80000000) >> 31); + #endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-B"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x", + "Codeword", value32); + + #if 0 + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "length/Rsv/tail/CRC", + v_length, vbrsv, vb_tail, vbcrc); + #endif + } + + *_used = used; + *_out_len = out_len; +} +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_bb_hw_dbg_info_jgr3(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + char *tmp_string = NULL; + u8 rx_ht_bw = 0, rx_vht_bw = 0, rx_ht = 0; + static u8 v_rx_bw; + u32 value32 = 0; + u8 i = 0; + static u8 tail, parity, rsv, vrsv, smooth, htsound, agg; + static u8 stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, v_nsts; + static u8 vtxops, vrsv2, vbrsv, bf, vbcrc; + static u16 h_length, htcrc8, length; + static u16 vpaid; + static u16 v_length, vhtcrc8, v_mcss, v_tail, vb_tail; + static u8 hmcss, hrx_bw; + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s\n", + "BB Report Info"); + + /*@ [Mode] =====================================================*/ + + value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD); + rx_ht = (u8)((value32 & 0xC0000) >> 18); + if (rx_ht == AD_VHT_MODE) + tmp_string = "VHT"; + else if (rx_ht == AD_HT_MODE) + tmp_string = "HT"; + else + tmp_string = "Legacy"; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s %s", "mode", tmp_string); + /*@ [RX counter Info] ===============================================*/ + + if (dm->support_ic_type & ODM_RTL8723F) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "CCK CCA cnt", + odm_get_bb_reg(dm, R_0x2aa0, 0xFFFF)); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "CCK CCA cnt", + odm_get_bb_reg(dm, R_0x2c08, 0xFFFF)); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM CCA cnt", + odm_get_bb_reg(dm, R_0x2c08, 0xFFFF0000)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d", "OFDM SBD Fail cnt", + odm_get_bb_reg(dm, R_0x2d20, 0xFFFF0000)); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", + "LSIG (parity Fail/rate Illegal) cnt", + odm_get_bb_reg(dm, R_0x2d04, 0xFFFF0000), + odm_get_bb_reg(dm, R_0x2d08, 0xFFFF)); + + value32 = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT cnt", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); + + value32 = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail cnt", + value32 & 0xFFFF, ((value32 & 0xFFFF0000) >> 16)); + /*@ [L-SIG Content] =================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c20, MASKDWORD); + + parity = (u8)((value32 & 0x20000) >> 17);/*@[17]*/ + length = (u16)((value32 & 0x1ffe0) >> 5);/*@[16:5]*/ + rsv = (u8)((value32 & 0x10) >> 4);/*@[4]*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, "\r\n %-35s", + "L-SIG"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d M", "rate", + phydm_get_l_sig_rate(dm, (u8)(value32 & 0x0f))); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %d / %d", "Rsv/length/parity", rsv, length, + parity); + + if (rx_ht == AD_HT_MODE) { + /*@ [HT SIG 1] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD); + + hmcss = (u8)(value32 & 0x7F); + hrx_bw = (u8)((value32 & 0x80) >> 7); + h_length = (u16)((value32 & 0x0fff00) >> 8); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "HT-SIG1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %d / %d / %d", "MCS/BW/length", + hmcss, hrx_bw, h_length); + /*@ [HT SIG 2] ======================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD); + smooth = (u8)(value32 & 0x01); + htsound = (u8)((value32 & 0x02) >> 1); + rsv = (u8)((value32 & 0x04) >> 2); + agg = (u8)((value32 & 0x08) >> 3); + stbc = (u8)((value32 & 0x30) >> 4); + fec = (u8)((value32 & 0x40) >> 6); + sgi = (u8)((value32 & 0x80) >> 7); + htltf = (u8)((value32 & 0x300) >> 8); + htcrc8 = (u16)((value32 & 0x3fc00) >> 10); + tail = (u8)((value32 & 0xfc0000) >> 18); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "HT-SIG2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x", + "Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", + smooth, htsound, rsv, agg, stbc, fec); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "SGI/E-HT-LTFs/CRC/tail", + sgi, htltf, htcrc8, tail); + } else if (rx_ht == AD_VHT_MODE) { + /*@ [VHT SIG A1] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c2c, MASKDWORD); + + v_rx_bw = (u8)(value32 & 0x03); + vrsv = (u8)((value32 & 0x04) >> 2); + vstbc = (u8)((value32 & 0x08) >> 3); + vgid = (u8)((value32 & 0x3f0) >> 4); + v_nsts = (u8)(((value32 & 0x1c00) >> 10) + 1); + vpaid = (u16)((value32 & 0x3fe000) >> 13); + vtxops = (u8)((value32 & 0x400000) >> 22); + vrsv2 = (u8)((value32 & 0x800000) >> 23); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", + "VHT-SIG-A1"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x / %x", + "BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", v_rx_bw, + vrsv, vstbc, vgid, v_nsts, vpaid, vtxops, vrsv2); + + /*@ [VHT SIG A2] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c30, MASKDWORD); + + /* @sgi=(u8)(value32&0x01); */ + sgiext = (u8)(value32 & 0x03); + /* @fec = (u8)(value32&0x04); */ + fecext = (u8)((value32 & 0x0C) >> 2); + + v_mcss = (u8)((value32 & 0xf0) >> 4); + bf = (u8)((value32 & 0x100) >> 8); + vrsv = (u8)((value32 & 0x200) >> 9); + vhtcrc8 = (u16)((value32 & 0x3fc00) >> 10); + v_tail = (u8)((value32 & 0xfc0000) >> 18); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-A2"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x / %x / %x / %x", + "SGI/FEC/MCS/BF/Rsv/CRC/tail", + sgiext, fecext, v_mcss, bf, vrsv, vhtcrc8, v_tail); + + /*@ [VHT SIG B] ====================================================*/ + value32 = odm_get_bb_reg(dm, R_0x2c34, MASKDWORD); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s", "VHT-SIG-B"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x", + "Codeword", value32); + + if (v_rx_bw == 0) { + v_length = (u16)(value32 & 0x1ffff); + vbrsv = (u8)((value32 & 0xE0000) >> 17); + vb_tail = (u16)((value32 & 0x03F00000) >> 20); + } else if (v_rx_bw == 1) { + v_length = (u16)(value32 & 0x7FFFF); + vbrsv = (u8)((value32 & 0x180000) >> 19); + vb_tail = (u16)((value32 & 0x07E00000) >> 21); + } else if (v_rx_bw == 2) { + v_length = (u16)(value32 & 0x1fffff); + vbrsv = (u8)((value32 & 0x600000) >> 21); + vb_tail = (u16)((value32 & 0x1f800000) >> 23); + } + vbcrc = (u8)((value32 & 0x80000000) >> 31); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n %-35s = %x / %x / %x / %x", + "length/Rsv/tail/CRC", + v_length, vbrsv, vb_tail, vbcrc); + } + + *_used = used; + *_out_len = out_len; +} +#endif + +u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig) +{ + u8 rate_idx = 0xff; + + switch (rate_idx_l_sig) { + case 0x0b: + rate_idx = 6; + break; + case 0x0f: + rate_idx = 9; + break; + case 0x0a: + rate_idx = 12; + break; + case 0x0e: + rate_idx = 18; + break; + case 0x09: + rate_idx = 24; + break; + case 0x0d: + rate_idx = 36; + break; + case 0x08: + rate_idx = 48; + break; + case 0x0c: + rate_idx = 54; + break; + default: + rate_idx = 0xff; + break; + } + + return rate_idx; +} + +void phydm_bb_hw_dbg_info(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + switch (dm->ic_ip_series) { + #if (ODM_IC_11N_SERIES_SUPPORT) + case PHYDM_IC_N: + phydm_bb_hw_dbg_info_n(dm, &used, output, &out_len); + break; + #endif + + #if (ODM_IC_11AC_SERIES_SUPPORT) + case PHYDM_IC_AC: + phydm_bb_hw_dbg_info_ac(dm, &used, output, &out_len); + phydm_reset_bb_hw_cnt(dm); + #if (RTL8822B_SUPPORT) + phydm_bb_hw_dbg_info_8822b(dm, &used, output, &out_len); + #endif + break; + #endif + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + case PHYDM_IC_JGR3: + phydm_bb_hw_dbg_info_jgr3(dm, &used, output, &out_len); + phydm_reset_bb_hw_cnt(dm); + break; + #endif + default: + break; + } + + *_used = used; + *_out_len = out_len; +} + +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + +void phydm_dm_summary_cli_win(void *dm_void, char *buf, u8 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + struct dtp_info *dtp = NULL; + u64 comp = dm->support_ability; + u64 pause_comp = dm->pause_ability; + + if (!dm->is_linked) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "[%s]No Link !!!\n", __func__); + RT_PRINT(buf); + return; + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, fa_src=%d, FA_th={%d,%d,%d}\n", + ((comp & ODM_BB_DIG) ? + ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."), + "DIG", + dig_t->cur_ig_value, + dig_t->rx_gain_range_min, dig_t->rx_gain_range_max, + dig_t->fa_source, + dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]); + RT_PRINT(buf); + + sta = dm->phydm_sta_info[macid]; + if (is_sta_active(sta)) { + ra = &sta->ra_info; + dtp = &sta->dtp_stat; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n", + ((comp & ODM_BB_RA_MASK) ? + ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."), + "RaMask", + ra->rssi_level, ra->ramask); + RT_PRINT(buf); + + #ifdef CONFIG_DYNAMIC_TX_TWR + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "02.(%s) %-12s: pwr_lv=%d\n", + ((comp & ODM_BB_DYNAMIC_TXPWR) ? + ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."), + "DynTxPwr", + dtp->sta_tx_high_power_lvl); + RT_PRINT(buf); + #endif + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "05.(%s) %-12s: cck_pd_lv=%d\n", + ((comp & ODM_BB_CCK_PD) ? + ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."), + "CCK_PD", dm->dm_cckpd_table.cck_pd_lv); + RT_PRINT(buf); + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "06.(%s) %-12s: div_type=%d, curr_ant=%s\n", + ((comp & ODM_BB_ANT_DIV) ? + ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."), + "ANT_DIV", + dm->ant_div_type, + (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX"); + RT_PRINT(buf); +#endif + +#ifdef PHYDM_POWER_TRAINING_SUPPORT + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "08.(%s) %-12s: PT_score=%d, disable_PT=%d\n", + ((comp & ODM_BB_PWR_TRAIN) ? + ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."), + "PwrTrain", + dm->pow_train_table.pow_train_score, + dm->is_disable_power_training); + RT_PRINT(buf); +#endif + +#ifdef CONFIG_PHYDM_DFS_MASTER + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n", + ((comp & ODM_BB_DFS) ? + ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."), + "DFS", + dm->dfs.dbg_mode, dm->dfs_region_domain); + RT_PRINT(buf); +#endif +#ifdef PHYDM_SUPPORT_ADAPTIVITY + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n", + ((comp & ODM_BB_ADAPTIVITY) ? + ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."), + "Adaptivity", + dm->adaptivity.th_l2h, dm->adaptivity.th_h2l, + dm->false_alm_cnt.edcca_flag); + RT_PRINT(buf); +#endif + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n", + ((comp & ODM_BB_CFO_TRACKING) ? + ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."), + "CfoTrack", + cfo_t->CFO_ave_pre, + ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap)); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "15.(%s) %-12s: ratio{nhm, clm}={%d, %d}, level{valid, RSSI}={%d, %d}\n", + ((comp & ODM_BB_ENV_MONITOR) ? + ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."), + "EnvMntr", + dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio, + dm->dm_ccx_info.nhm_level_valid, dm->dm_ccx_info.nhm_level); + RT_PRINT(buf); +#ifdef PHYDM_PRIMARY_CCA + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "16.(%s) %-12s: CCA @ (%s SB)\n", + ((comp & ODM_BB_PRIMARY_CCA) ? + ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."), + "PriCCA", + ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" : + ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U"))); + RT_PRINT(buf); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "17.(%s) %-12s: soml_en = %s\n", + ((comp & ODM_BB_ADAPTIVE_SOML) ? + ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."), + "A-SOML", + (dm->dm_soml_table.soml_last_state == SOML_ON) ? + "ON" : "OFF"); + RT_PRINT(buf); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "18.(%s) %-12s:\n", + ((comp & ODM_BB_LNA_SAT_CHK) ? + ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."), + "LNA_SAT_CHK"); + RT_PRINT(buf); +#endif +} + +void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info_win_bkp; + struct phydm_phystatus_statistic *dbg_s = &dbg->physts_statistic_info; + struct phydm_phystatus_avg *dbg_avg = &dbg->phystatus_statistic_avg; + + char *rate_type = NULL; + u8 tmp_rssi_avg[4]; + u8 tmp_snr_avg[4]; + u8 tmp_evm_avg[4]; + u32 tmp_cnt = 0; + u8 macid, target_macid = 0; + u8 i = 0; + u8 rate_num = dm->num_rf_path; + u8 ss_ofst = 0; + struct cmn_sta_info *entry = NULL; + char dbg_buf[PHYDM_SNPRINT_SIZE] = {0}; + + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n PHYDM Common Dbg Msg --------->"); + RT_PRINT(buf); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n System up time=%d", dm->phydm_sys_up_time); + RT_PRINT(buf); + + if (dm->is_linked) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n ID=((%d)), BW=((%d)), fc=((CH-%d))", + dm->curr_station_id, 20 << *dm->band_width, *dm->channel); + RT_PRINT(buf); + + if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) && + (dm->support_ic_type & ODM_IC_11N_SERIES)) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Primary CCA at ((%s SB))", + (*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" : "L"); + RT_PRINT(buf); + } + + if (dm->cck_new_agc || dm->rx_rate > ODM_RATE11M) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}", + dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1], + dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]); + RT_PRINT(buf); + } else { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}", + dm->cck_lna_idx, dm->cck_vga_idx); + RT_PRINT(buf); + } + + phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)", + (dm->rssi_a == 0xff) ? 0 : dm->rssi_a, + (dm->rssi_b == 0xff) ? 0 : dm->rssi_b, + (dm->rssi_c == 0xff) ? 0 : dm->rssi_c, + (dm->rssi_d == 0xff) ? 0 : dm->rssi_d, + dbg_buf, dm->rx_rate); + RT_PRINT(buf); + + phydm_print_rate_2_buff(dm, dm->phy_dbg_info.beacon_phy_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Beacon_cnt=%d, rate_idx:%s (0x%x)", + dm->phy_dbg_info.beacon_cnt_in_period, + dbg_buf, + dm->phy_dbg_info.beacon_phy_rate); + RT_PRINT(buf); + + /*Show phydm_rx_rate_distribution;*/ + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [RxRate Cnt] =============>"); + RT_PRINT(buf); + + /*@======CCK=================================================*/ + if (*dm->channel <= 14) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * CCK = {%d, %d, %d, %d}", + dbg->num_qry_legacy_pkt[0], dbg->num_qry_legacy_pkt[1], + dbg->num_qry_legacy_pkt[2], dbg->num_qry_legacy_pkt[3]); + RT_PRINT(buf); + } + /*@======OFDM================================================*/ + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}", + dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5], + dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7], + dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9], + dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]); + RT_PRINT(buf); + + /*@======HT==================================================*/ + if (dbg->ht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_ht_pkt[ss_ofst + 0], dbg->num_qry_ht_pkt[ss_ofst + 1], + dbg->num_qry_ht_pkt[ss_ofst + 2], dbg->num_qry_ht_pkt[ss_ofst + 3], + dbg->num_qry_ht_pkt[ss_ofst + 4], dbg->num_qry_ht_pkt[ss_ofst + 5], + dbg->num_qry_ht_pkt[ss_ofst + 6], dbg->num_qry_ht_pkt[ss_ofst + 7]); + RT_PRINT(buf); + } + + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7]); + RT_PRINT(buf); + } + } + } + +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + /*@======VHT=================================================*/ + if (dbg->vht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n * VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}", + (i + 1), + dbg->num_qry_vht_pkt[ss_ofst + 0], dbg->num_qry_vht_pkt[ss_ofst + 1], + dbg->num_qry_vht_pkt[ss_ofst + 2], dbg->num_qry_vht_pkt[ss_ofst + 3], + dbg->num_qry_vht_pkt[ss_ofst + 4], dbg->num_qry_vht_pkt[ss_ofst + 5], + dbg->num_qry_vht_pkt[ss_ofst + 6], dbg->num_qry_vht_pkt[ss_ofst + 7], + dbg->num_qry_vht_pkt[ss_ofst + 8], dbg->num_qry_vht_pkt[ss_ofst + 9]); + RT_PRINT(buf); + } + + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}", + (i + 1), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], dbg->num_qry_pkt_sc_20m[ss_ofst + 7], + dbg->num_qry_pkt_sc_20m[ss_ofst + 8], dbg->num_qry_pkt_sc_20m[ss_ofst + 9]); + RT_PRINT(buf); + } + } + + if (dbg->low_bw_40_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n *[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}", + (i + 1), + dbg->num_qry_pkt_sc_40m[ss_ofst + 0], dbg->num_qry_pkt_sc_40m[ss_ofst + 1], + dbg->num_qry_pkt_sc_40m[ss_ofst + 2], dbg->num_qry_pkt_sc_40m[ss_ofst + 3], + dbg->num_qry_pkt_sc_40m[ss_ofst + 4], dbg->num_qry_pkt_sc_40m[ss_ofst + 5], + dbg->num_qry_pkt_sc_40m[ss_ofst + 6], dbg->num_qry_pkt_sc_40m[ss_ofst + 7], + dbg->num_qry_pkt_sc_40m[ss_ofst + 8], dbg->num_qry_pkt_sc_40m[ss_ofst + 9]); + RT_PRINT(buf); + } + } + } +#endif + + //1 Show phydm_avg_phystatus_val + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [Avg PHY Statistic] ==============>\n"); + RT_PRINT(buf); + + /*===[Beacon]===*/ + switch (dm->num_rf_path) { +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1], + dbg_avg->rssi_beacon_avg[2], + dbg_avg->rssi_beacon_avg[3]); + break; +#endif +#if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1], + dbg_avg->rssi_beacon_avg[2]); + break; +#endif +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1]); + break; +#endif + default: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0]); + break; + } + RT_PRINT(buf); + + /*===[CCK]===*/ + switch (dm->num_rf_path) { +#ifdef PHYSTS_3RD_TYPE_SUPPORT + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, + dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0], + dbg_avg->rssi_cck_avg_abv_2ss[1], + dbg_avg->rssi_cck_avg_abv_2ss[2]); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, + dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0], + dbg_avg->rssi_cck_avg_abv_2ss[1]); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, + dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0]); + break; + #endif +#endif + default: + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, + dbg_avg->rssi_cck_avg); + break; + } + RT_PRINT(buf); + + for (i = 0; i <= 4; i++) { + if (i > dm->num_rf_path) + break; + + odm_memory_set(dm, tmp_rssi_avg, 0, 4); + odm_memory_set(dm, tmp_snr_avg, 0, 4); + odm_memory_set(dm, tmp_evm_avg, 0, 4); + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (i == 4) { + rate_type = "[4-SS]"; + tmp_cnt = dbg_s->rssi_4ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_4ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_4ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg, 4); + } else + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (i == 3) { + rate_type = "[3-SS]"; + tmp_cnt = dbg_s->rssi_3ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_3ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_3ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_3ss_avg, 3); + } else + #endif + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (i == 2) { + rate_type = "[2-SS]"; + tmp_cnt = dbg_s->rssi_2ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_2ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_2ss_avg, 2); + } else + #endif + if (i == 1) { + rate_type = "[1-SS]"; + tmp_cnt = dbg_s->rssi_1ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_1ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_1ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_1ss_avg, 1); + } else { + rate_type = "[L-OFDM]"; + tmp_cnt = dbg_s->rssi_ofdm_cnt; + odm_move_memory(dm, tmp_rssi_avg, dbg_avg->rssi_ofdm_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_ofdm_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, &dbg_avg->evm_ofdm_avg, 1); + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n", + rate_type, tmp_cnt, + tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2], tmp_rssi_avg[3], + tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2], tmp_snr_avg[3], + tmp_evm_avg[0], tmp_evm_avg[1], tmp_evm_avg[2], tmp_evm_avg[3]); + RT_PRINT(buf); + } + /*@----------------------------------------------------------*/ + + /*Print TX rate*/ + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + entry = dm->phydm_sta_info[macid]; + + if (is_sta_active(entry)) { + phydm_print_rate_2_buff(dm, entry->ra_info.curr_tx_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n TxRate[%d]=%s (0x%x)", macid, dbg_buf, entry->ra_info.curr_tx_rate); + RT_PRINT(buf); + target_macid = macid; + break; + } + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))", + dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n CFO_avg=((%d kHz)), CFO_traking = ((%s%d))", + cfo_t->CFO_ave_pre, + ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap)); + RT_PRINT(buf); + + /* @Condition number */ + #if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Condi_Num=((%d.%.4d))", + dm->phy_dbg_info.condi_num >> 4, + phydm_show_fraction_num(dm->phy_dbg_info.condi_num & 0xf, 4)); + RT_PRINT(buf); + } + #endif + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT)) + /*STBC or LDPC pkt*/ + if (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC | + PHYSTS_3RD_TYPE_IC)) + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n Coding: LDPC=((%s)), STBC=((%s))", + (dm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N", + (dm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N"); + RT_PRINT(buf); +#endif + + } else { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n No Link !!!"); + RT_PRINT(buf); + } + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [Tx cnt] {CCK_TxEN, CCK_TxON, OFDM_TxEN, OFDM_TxON} = {%d, %d, %d, %d}", + fa_t->cnt_cck_txen, fa_t->cnt_cck_txon, fa_t->cnt_ofdm_txen, + fa_t->cnt_ofdm_txon); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}", + fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}", + fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [FA duration(us)] {exp, ifs_clm, fahm} = {%d, %d, %d}", + fa_t->time_fa_exp, fa_t->time_fa_ifs_clm, + fa_t->time_fa_fahm); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, "\r\n [HT FA] CRC8=%d, MCS=%d", + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail); + RT_PRINT(buf); + +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) { + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d", + fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb, + fa_t->cnt_mcs_fail_vht); + RT_PRINT(buf); + } +#endif + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}", + fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok, + fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok, + fa_t->cnt_crc32_ok_all); + RT_PRINT(buf); + + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}", + fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error, + fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error, + fa_t->cnt_crc32_error_all); + RT_PRINT(buf); + + if (fa_t->ofdm2_rate_idx) { + phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, + dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)", + dbg_buf, fa_t->cnt_ofdm2_crc32_error, + fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr); + RT_PRINT(buf); + } + + if (fa_t->ht2_rate_idx) { + phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf, + PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [HT :%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)", + dbg_buf, fa_t->cnt_ht2_crc32_error, + fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr); + RT_PRINT(buf); + } + +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) { + if (fa_t->vht2_rate_idx) { + phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx, + dbg_buf, PHYDM_SNPRINT_SIZE); + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n [VHT :%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)", + dbg_buf, fa_t->cnt_vht2_crc32_error, + fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr); + RT_PRINT(buf); + } + } +#endif + + if (dm->support_ic_type & (ODM_IC_11N_SERIES | ODM_IC_11AC_SERIES)) + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n", + dm->is_linked, dm->number_linked_client, dm->rssi_min, + dm->dm_dig_table.cur_ig_value, dm->noisy_decision); + else + RT_SPRINTF(buf, DBGM_CLI_BUF_SIZE, + "\r\n is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x\n", + dm->is_linked, dm->number_linked_client, dm->rssi_min, + dm->dm_dig_table.cur_ig_value); + + RT_PRINT(buf); + + phydm_dm_summary_cli_win(dm, buf, target_macid); +} + +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION +void phydm_sbd_check( + struct dm_struct *dm) +{ + static u32 pkt_cnt; + static boolean sbd_state; + u32 sym_count, count, value32; + + if (sbd_state == 0) { + pkt_cnt++; + /*read SBD conter once every 5 packets*/ + if (pkt_cnt % 5 == 0) { + odm_set_timer(dm, &dm->sbdcnt_timer, 0); /*@ms*/ + sbd_state = 1; + } + } else { /*read counter*/ + value32 = odm_get_bb_reg(dm, R_0xf98, MASKDWORD); + sym_count = (value32 & 0x7C000000) >> 26; + count = (value32 & 0x3F00000) >> 20; + pr_debug("#SBD# sym_count %d count %d\n", sym_count, count); + sbd_state = 0; + } +} +#endif + +void phydm_sbd_callback( + struct phydm_timer_list *timer) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + void *adapter = timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; + +#if USE_WORKITEM + odm_schedule_work_item(&dm->sbdcnt_workitem); +#else + phydm_sbd_check(dm); +#endif +#endif +} + +void phydm_sbd_workitem_callback( + void *context) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + phydm_sbd_check(dm); +#endif +} +#endif + +void phydm_reset_rx_rate_distribution(struct dm_struct *dm) +{ + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + + odm_memory_set(dm, &dbg->num_qry_legacy_pkt[0], 0, + (LEGACY_RATE_NUM * 2)); + odm_memory_set(dm, &dbg->num_qry_ht_pkt[0], 0, + (HT_RATE_NUM * 2)); + odm_memory_set(dm, &dbg->num_qry_pkt_sc_20m[0], 0, + (LOW_BW_RATE_NUM * 2)); + + dbg->ht_pkt_not_zero = false; + dbg->low_bw_20_occur = false; + +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + odm_memory_set(dm, &dbg->num_qry_vht_pkt[0], 0, VHT_RATE_NUM * 2); + odm_memory_set(dm, &dbg->num_qry_pkt_sc_40m[0], 0, LOW_BW_RATE_NUM * 2); + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) + odm_memory_set(dm, &dbg->num_mu_vht_pkt[0], 0, VHT_RATE_NUM * 2); + #endif + dbg->vht_pkt_not_zero = false; + dbg->low_bw_40_occur = false; +#endif +} + +void phydm_rx_rate_distribution(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u8 i = 0; + u8 rate_num = dm->num_rf_path, ss_ofst = 0; + + PHYDM_DBG(dm, DBG_CMN, "[RxRate Cnt] =============>\n"); + + /*@======CCK=========================================================*/ + if (*dm->channel <= 14) { + PHYDM_DBG(dm, DBG_CMN, "* CCK = {%d, %d, %d, %d}\n", + dbg->num_qry_legacy_pkt[0], + dbg->num_qry_legacy_pkt[1], + dbg->num_qry_legacy_pkt[2], + dbg->num_qry_legacy_pkt[3]); + } + /*@======OFDM========================================================*/ + PHYDM_DBG(dm, DBG_CMN, "* OFDM = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + dbg->num_qry_legacy_pkt[4], dbg->num_qry_legacy_pkt[5], + dbg->num_qry_legacy_pkt[6], dbg->num_qry_legacy_pkt[7], + dbg->num_qry_legacy_pkt[8], dbg->num_qry_legacy_pkt[9], + dbg->num_qry_legacy_pkt[10], dbg->num_qry_legacy_pkt[11]); + + /*@======HT==========================================================*/ + if (dbg->ht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + PHYDM_DBG(dm, DBG_CMN, + "* HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_ht_pkt[ss_ofst + 0], + dbg->num_qry_ht_pkt[ss_ofst + 1], + dbg->num_qry_ht_pkt[ss_ofst + 2], + dbg->num_qry_ht_pkt[ss_ofst + 3], + dbg->num_qry_ht_pkt[ss_ofst + 4], + dbg->num_qry_ht_pkt[ss_ofst + 5], + dbg->num_qry_ht_pkt[ss_ofst + 6], + dbg->num_qry_ht_pkt[ss_ofst + 7]); + } + + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = (i << 3); + + PHYDM_DBG(dm, DBG_CMN, + "* [Low BW 20M] HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_ofst), (ss_ofst + 7), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], + dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], + dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], + dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], + dbg->num_qry_pkt_sc_20m[ss_ofst + 7]); + } + } + } + +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + /*@======VHT==========================================================*/ + if (dbg->vht_pkt_not_zero) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + PHYDM_DBG(dm, DBG_CMN, + "* VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_vht_pkt[ss_ofst + 0], + dbg->num_qry_vht_pkt[ss_ofst + 1], + dbg->num_qry_vht_pkt[ss_ofst + 2], + dbg->num_qry_vht_pkt[ss_ofst + 3], + dbg->num_qry_vht_pkt[ss_ofst + 4], + dbg->num_qry_vht_pkt[ss_ofst + 5], + dbg->num_qry_vht_pkt[ss_ofst + 6], + dbg->num_qry_vht_pkt[ss_ofst + 7], + dbg->num_qry_vht_pkt[ss_ofst + 8], + dbg->num_qry_vht_pkt[ss_ofst + 9]); + } + + if (dbg->low_bw_20_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + PHYDM_DBG(dm, DBG_CMN, + "*[Low BW 20M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_pkt_sc_20m[ss_ofst + 0], + dbg->num_qry_pkt_sc_20m[ss_ofst + 1], + dbg->num_qry_pkt_sc_20m[ss_ofst + 2], + dbg->num_qry_pkt_sc_20m[ss_ofst + 3], + dbg->num_qry_pkt_sc_20m[ss_ofst + 4], + dbg->num_qry_pkt_sc_20m[ss_ofst + 5], + dbg->num_qry_pkt_sc_20m[ss_ofst + 6], + dbg->num_qry_pkt_sc_20m[ss_ofst + 7], + dbg->num_qry_pkt_sc_20m[ss_ofst + 8], + dbg->num_qry_pkt_sc_20m[ss_ofst + 9]); + } + } + + if (dbg->low_bw_40_occur) { + for (i = 0; i < rate_num; i++) { + ss_ofst = 10 * i; + + PHYDM_DBG(dm, DBG_CMN, + "*[Low BW 40M] VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + dbg->num_qry_pkt_sc_40m[ss_ofst + 0], + dbg->num_qry_pkt_sc_40m[ss_ofst + 1], + dbg->num_qry_pkt_sc_40m[ss_ofst + 2], + dbg->num_qry_pkt_sc_40m[ss_ofst + 3], + dbg->num_qry_pkt_sc_40m[ss_ofst + 4], + dbg->num_qry_pkt_sc_40m[ss_ofst + 5], + dbg->num_qry_pkt_sc_40m[ss_ofst + 6], + dbg->num_qry_pkt_sc_40m[ss_ofst + 7], + dbg->num_qry_pkt_sc_40m[ss_ofst + 8], + dbg->num_qry_pkt_sc_40m[ss_ofst + 9]); + } + } + } +#endif +} + +u16 phydm_rx_utility(void *dm_void, u16 avg_phy_rate, u8 rx_max_ss, + enum channel_width bw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u16 utility_primitive = 0, utility = 0; + + if (dbg->ht_pkt_not_zero) { + /*@ MCS7 20M: tp = 65, 1000/65 = 15.38, 65*15.5 = 1007*/ + utility_primitive = avg_phy_rate * 15 + (avg_phy_rate >> 1); + } +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + else if (dbg->vht_pkt_not_zero) { + /*@ VHT 1SS MCS9(fake) 20M: tp = 90, 1000/90 = 11.11, 65*11.125 = 1001*/ + utility_primitive = avg_phy_rate * 11 + (avg_phy_rate >> 3); + } +#endif + else { + /*@ 54M, 1000/54 = 18.5, 54*18.5 = 999*/ + utility_primitive = avg_phy_rate * 18 + (avg_phy_rate >> 1); + } + + utility = (utility_primitive / rx_max_ss) >> bw; + + if (utility > 1000) + utility = 1000; + + return utility; +} + +u16 phydm_rx_avg_phy_rate(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u8 i = 0, rate_num = 0, rate_base = 0; + u16 rate = 0, avg_phy_rate = 0; + u32 pkt_cnt = 0, phy_rate_sum = 0; + + if (dbg->ht_pkt_not_zero) { + rate_num = HT_RATE_NUM; + rate_base = ODM_RATEMCS0; + for (i = 0; i < rate_num; i++) { + rate = phy_rate_table[i + rate_base] << *dm->band_width; + phy_rate_sum += dbg->num_qry_ht_pkt[i] * rate; + pkt_cnt += dbg->num_qry_ht_pkt[i]; + } + } +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + else if (dbg->vht_pkt_not_zero) { + rate_num = VHT_RATE_NUM; + rate_base = ODM_RATEVHTSS1MCS0; + for (i = 0; i < rate_num; i++) { + rate = phy_rate_table[i + rate_base] << *dm->band_width; + phy_rate_sum += dbg->num_qry_vht_pkt[i] * rate; + pkt_cnt += dbg->num_qry_vht_pkt[i]; + } + } +#endif + else { + for (i = ODM_RATE1M; i <= ODM_RATE54M; i++) { + /*SKIP 1M & 6M for beacon case*/ + if (*dm->channel < 36 && i == ODM_RATE1M) + continue; + + if (*dm->channel >= 36 && i == ODM_RATE6M) + continue; + + rate = phy_rate_table[i]; + phy_rate_sum += dbg->num_qry_legacy_pkt[i] * rate; + pkt_cnt += dbg->num_qry_legacy_pkt[i]; + } + } + +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + if (dbg->low_bw_40_occur) { + for (i = 0; i < LOW_BW_RATE_NUM; i++) { + rate = phy_rate_table[i + rate_base] + << CHANNEL_WIDTH_40; + phy_rate_sum += dbg->num_qry_pkt_sc_40m[i] * rate; + pkt_cnt += dbg->num_qry_pkt_sc_40m[i]; + } + } +#endif + + if (dbg->low_bw_20_occur) { + for (i = 0; i < LOW_BW_RATE_NUM; i++) { + rate = phy_rate_table[i + rate_base]; + phy_rate_sum += dbg->num_qry_pkt_sc_20m[i] * rate; + pkt_cnt += dbg->num_qry_pkt_sc_20m[i]; + } + } + + avg_phy_rate = (pkt_cnt == 0) ? 0 : (u16)(phy_rate_sum / pkt_cnt); + + return avg_phy_rate; +} + +void phydm_print_hist_2_buf(void *dm_void, u16 *val, u16 len, char *buf, + u16 buf_size) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (len == PHY_HIST_SIZE) { + PHYDM_SNPRINTF(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10], val[11]); + } else if (len == (PHY_HIST_SIZE - 1)) { + PHYDM_SNPRINTF(buf, buf_size, + "[%.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d, %.2d]", + val[0], val[1], val[2], val[3], val[4], + val[5], val[6], val[7], val[8], val[9], + val[10]); + } +} + +void phydm_nss_hitogram(void *dm_void, enum PDM_RATE_TYPE rate_type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + char buf[PHYDM_SNPRINT_SIZE] = {0}; + u16 buf_size = PHYDM_SNPRINT_SIZE; + u16 h_size = PHY_HIST_SIZE; + u16 *evm_hist = &dbg_s->evm_1ss_hist[0]; + u16 *snr_hist = &dbg_s->snr_1ss_hist[0]; + u8 i = 0; + u8 ss = phydm_rate_type_2_num_ss(dm, rate_type); + + for (i = 0; i < ss; i++) { + if (rate_type == PDM_1SS) { + evm_hist = &dbg_s->evm_1ss_hist[0]; + snr_hist = &dbg_s->snr_1ss_hist[0]; + } else if (rate_type == PDM_2SS) { + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + evm_hist = &dbg_s->evm_2ss_hist[i][0]; + snr_hist = &dbg_s->snr_2ss_hist[i][0]; + #endif + } else if (rate_type == PDM_3SS) { + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + evm_hist = &dbg_s->evm_3ss_hist[i][0]; + snr_hist = &dbg_s->snr_3ss_hist[i][0]; + #endif + } else if (rate_type == PDM_4SS) { + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + evm_hist = &dbg_s->evm_4ss_hist[i][0]; + snr_hist = &dbg_s->snr_4ss_hist[i][0]; + #endif + } + + phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "[%d-SS][EVM][%d]=%s\n", ss, i, buf); + phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "[%d-SS][SNR][%d]=%s\n", ss, i, buf); + } +} + +#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH +void phydm_show_cn_hitogram(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + u16 th_tmp[PHY_HIST_TH_SIZE]; + char buf[PHYDM_SNPRINT_SIZE] = {0}; + u8 i = 0; + u16 *cn_hist = NULL; + u32 cn_avg = 0; + + if (!dm->pkt_proc_struct.physts_auto_swch_en) + return; + + if (dm->num_rf_path == 1) + return; + + PHYDM_DBG(dm, DBG_CMN, "[Condition number Histogram] ========>\n"); +/*@===[Threshold]=============================================================*/ + for (i = 0; i < PHY_HIST_TH_SIZE; i++) + th_tmp[i] = dbg_i->cn_hist_th[i] >> 1; + + phydm_print_hist_2_buf(dm, th_tmp, + PHY_HIST_TH_SIZE, buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_CMN, "%-24s=%s\n", "[CN_TH]", buf); + +/*@===[Histogram]=============================================================*/ + + for (i = 1; i <= dm->num_rf_path; i++) { + if (dbg_s->p4_cnt[i] == 0) + continue; + + cn_avg = PHYDM_DIV((dbg_s->cn_sum[i] + + (dbg_s->p4_cnt[i] >> 1)) << 2, + dbg_s->p4_cnt[i]); /*u(8,1)<<2 -> u(10,3)*/ + + cn_hist = &dbg_s->cn_hist[i][0]; + phydm_print_hist_2_buf(dm, cn_hist, + PHY_HIST_SIZE, buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_CMN, "[%d-SS]%s=(avg:%d.%4d)%s\n", + i + 1, "[CN]", cn_avg >> 3, + phydm_show_fraction_num(cn_avg & 0x7, 3), buf); + } +} +#endif + +void phydm_show_phy_hitogram(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + char buf[PHYDM_SNPRINT_SIZE] = {0}; + u16 buf_size = PHYDM_SNPRINT_SIZE; + u16 th_size = PHY_HIST_SIZE - 1; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CMN, "[PHY Histogram] ==============>\n"); +/*@===[Threshold]=============================================================*/ + phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[EVM_TH]", buf); + + phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-16s=%s\n", "[SNR_TH]", buf); +/*@===[OFDM]==================================================================*/ + if (dbg_s->rssi_ofdm_cnt) { + phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE, + buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][EVM]", buf); + + phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE, + buf, buf_size); + PHYDM_DBG(dm, DBG_CMN, "%-14s=%s\n", "[OFDM][SNR]", buf); + } +/*@===[1-SS]==================================================================*/ + if (dbg_s->rssi_1ss_cnt) + phydm_nss_hitogram(dm, PDM_1SS); +/*@===[2-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if ((dm->support_ic_type & PHYDM_IC_ABOVE_2SS) && dbg_s->rssi_2ss_cnt) + phydm_nss_hitogram(dm, PDM_2SS); + #endif +/*@===[3-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if ((dm->support_ic_type & PHYDM_IC_ABOVE_3SS) && dbg_s->rssi_3ss_cnt) + phydm_nss_hitogram(dm, PDM_3SS); + #endif +/*@===[4-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS && dbg_s->rssi_4ss_cnt) + phydm_nss_hitogram(dm, PDM_4SS); + #endif +} + +void phydm_avg_phy_val_nss(void *dm_void, u8 nss) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg; + char *rate_type = NULL; + u32 *tmp_cnt = NULL; + u8 *tmp_rssi_avg = NULL; + u32 *tmp_rssi_sum = NULL; + u8 *tmp_snr_avg = NULL; + u32 *tmp_snr_sum = NULL; + u8 *tmp_evm_avg = NULL; + u32 *tmp_evm_sum = NULL; + u8 evm_rpt_show[RF_PATH_MEM_SIZE]; + u8 i = 0; + + odm_memory_set(dm, &evm_rpt_show[0], 0, RF_PATH_MEM_SIZE); + + switch (nss) { + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + rate_type = "[4-SS]"; + tmp_cnt = &dbg_s->rssi_4ss_cnt; + tmp_rssi_avg = &dbg_avg->rssi_4ss_avg[0]; + tmp_snr_avg = &dbg_avg->snr_4ss_avg[0]; + tmp_rssi_sum = &dbg_s->rssi_4ss_sum[0]; + tmp_snr_sum = &dbg_s->snr_4ss_sum[0]; + tmp_evm_avg = &dbg_avg->evm_4ss_avg[0]; + tmp_evm_sum = &dbg_s->evm_4ss_sum[0]; + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + rate_type = "[3-SS]"; + tmp_cnt = &dbg_s->rssi_3ss_cnt; + tmp_rssi_avg = &dbg_avg->rssi_3ss_avg[0]; + tmp_snr_avg = &dbg_avg->snr_3ss_avg[0]; + tmp_rssi_sum = &dbg_s->rssi_3ss_sum[0]; + tmp_snr_sum = &dbg_s->snr_3ss_sum[0]; + tmp_evm_avg = &dbg_avg->evm_3ss_avg[0]; + tmp_evm_sum = &dbg_s->evm_3ss_sum[0]; + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + rate_type = "[2-SS]"; + tmp_cnt = &dbg_s->rssi_2ss_cnt; + tmp_rssi_avg = &dbg_avg->rssi_2ss_avg[0]; + tmp_snr_avg = &dbg_avg->snr_2ss_avg[0]; + tmp_rssi_sum = &dbg_s->rssi_2ss_sum[0]; + tmp_snr_sum = &dbg_s->snr_2ss_sum[0]; + tmp_evm_avg = &dbg_avg->evm_2ss_avg[0]; + tmp_evm_sum = &dbg_s->evm_2ss_sum[0]; + break; + #endif + case 1: + rate_type = "[1-SS]"; + tmp_cnt = &dbg_s->rssi_1ss_cnt; + tmp_rssi_avg = &dbg_avg->rssi_1ss_avg[0]; + tmp_snr_avg = &dbg_avg->snr_1ss_avg[0]; + tmp_rssi_sum = &dbg_s->rssi_1ss_sum[0]; + tmp_snr_sum = &dbg_s->snr_1ss_sum[0]; + tmp_evm_avg = &dbg_avg->evm_1ss_avg; + tmp_evm_sum = &dbg_s->evm_1ss_sum; + break; + case 0: + rate_type = "[L-OFDM]"; + tmp_cnt = &dbg_s->rssi_ofdm_cnt; + tmp_rssi_avg = &dbg_avg->rssi_ofdm_avg[0]; + tmp_snr_avg = &dbg_avg->snr_ofdm_avg[0]; + tmp_rssi_sum = &dbg_s->rssi_ofdm_sum[0]; + tmp_snr_sum = &dbg_s->snr_ofdm_sum[0]; + tmp_evm_avg = &dbg_avg->evm_ofdm_avg; + tmp_evm_sum = &dbg_s->evm_ofdm_sum; + break; + default: + PHYDM_DBG(dm, DBG_CMN, "[warning] %s\n", __func__); + return; + } + + if (*tmp_cnt != 0) { + for (i = 0; i < dm->num_rf_path; i++) { + tmp_rssi_avg[i] = (u8)(tmp_rssi_sum[i] / *tmp_cnt); + tmp_snr_avg[i] = (u8)(tmp_snr_sum[i] / *tmp_cnt); + } + + if (nss == 0 || nss == 1) { + *tmp_evm_avg = (u8)(*tmp_evm_sum / *tmp_cnt); + evm_rpt_show[0] = *tmp_evm_avg; + } else { + for (i = 0; i < nss; i++) { + tmp_evm_avg[i] = (u8)(tmp_evm_sum[i] / + *tmp_cnt); + evm_rpt_show[i] = tmp_evm_avg[i]; + } + } + } + +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n", + rate_type, *tmp_cnt, + tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2], + tmp_rssi_avg[3], tmp_snr_avg[0], tmp_snr_avg[1], + tmp_snr_avg[2], tmp_snr_avg[3], evm_rpt_show[0], + evm_rpt_show[1], evm_rpt_show[2], evm_rpt_show[3]); +#elif (defined(PHYDM_COMPILE_ABOVE_3SS)) + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d}\n", + rate_type, *tmp_cnt, + tmp_rssi_avg[0], tmp_rssi_avg[1], tmp_rssi_avg[2], + tmp_snr_avg[0], tmp_snr_avg[1], tmp_snr_avg[2], + evm_rpt_show[0], evm_rpt_show[1], evm_rpt_show[2]); +#elif (defined(PHYDM_COMPILE_ABOVE_2SS)) + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt= ((%.3d)) RSSI:{%.2d, %.2d} SNR:{%.2d, %.2d} EVM:{-%.2d, -%.2d}\n", + rate_type, *tmp_cnt, + tmp_rssi_avg[0], tmp_rssi_avg[1], + tmp_snr_avg[0], tmp_snr_avg[1], + evm_rpt_show[0], evm_rpt_show[1]); +#else + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt= ((%.3d)) RSSI:{%.2d} SNR:{%.2d} EVM:{-%.2d}\n", + rate_type, *tmp_cnt, + tmp_rssi_avg[0], tmp_snr_avg[0], evm_rpt_show[0]); +#endif +} + +void phydm_get_avg_phystatus_val(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg; + u32 avg_tmp = 0; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CMN, "[PHY Avg] ==============>\n"); + phydm_reset_phystatus_avg(dm); + + /*@===[Beacon]===*/ + if (dbg_s->rssi_beacon_cnt) { + for (i = 0; i < dm->num_rf_path; i++) { + avg_tmp = dbg_s->rssi_beacon_sum[i] / + dbg_s->rssi_beacon_cnt; + dbg_avg->rssi_beacon_avg[i] = (u8)avg_tmp; + } + } + + switch (dm->num_rf_path) { +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1], + dbg_avg->rssi_beacon_avg[2], + dbg_avg->rssi_beacon_avg[3]); + break; +#endif +#if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1], + dbg_avg->rssi_beacon_avg[2]); + break; +#endif +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1]); + break; +#endif + default: + PHYDM_DBG(dm, DBG_CMN, "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0]); + break; + } + + /*@===[CCK]===*/ + if (dbg_s->rssi_cck_cnt) { + dbg_avg->rssi_cck_avg = (u8)(dbg_s->rssi_cck_sum / + dbg_s->rssi_cck_cnt); + #if (defined(PHYSTS_3RD_TYPE_SUPPORT) && defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) { + for (i = 0; i < dm->num_rf_path - 1; i++) { + avg_tmp = dbg_s->rssi_cck_sum_abv_2ss[i] / + dbg_s->rssi_cck_cnt; + dbg_avg->rssi_cck_avg_abv_2ss[i] = (u8)avg_tmp; + } + } + #endif + } + + switch (dm->num_rf_path) { +#ifdef PHYSTS_3RD_TYPE_SUPPORT + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0], + dbg_avg->rssi_cck_avg_abv_2ss[1], + dbg_avg->rssi_cck_avg_abv_2ss[2]); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0], + dbg_avg->rssi_cck_avg_abv_2ss[1]); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + PHYDM_DBG(dm, DBG_CMN, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0]); + break; + #endif +#endif + default: + PHYDM_DBG(dm, DBG_CMN, "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg); + break; + } + + for (i = 0; i <= dm->num_rf_path; i++) + phydm_avg_phy_val_nss(dm, i); +} + +void phydm_get_phy_statistic(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[dm->one_entry_macid]; + enum channel_width bw; + u16 avg_phy_rate = 0; + u16 utility = 0; + u8 rx_ss = 1; + + avg_phy_rate = phydm_rx_avg_phy_rate(dm); + + if (dm->is_one_entry_only && is_sta_active(sta)) { + rx_ss = phydm_get_rx_stream_num(dm, sta->mimo_type); + bw = sta->bw_mode; + utility = phydm_rx_utility(dm, avg_phy_rate, rx_ss, bw); + } + PHYDM_DBG(dm, DBG_CMN, "Avg_rx_rate = %d, rx_utility=( %d / 1000 )\n", + avg_phy_rate, utility); + + phydm_rx_rate_distribution(dm); + phydm_reset_rx_rate_distribution(dm); + + phydm_show_phy_hitogram(dm); + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + phydm_show_cn_hitogram(dm); + #endif + phydm_get_avg_phystatus_val(dm); + phydm_reset_phystatus_statistic(dm); +}; + +void phydm_basic_dbg_msg_linked(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track; + struct odm_phy_dbg_info *dbg_t = &dm->phy_dbg_info; + u16 macid, client_cnt = 0; + u8 rate = 0; + struct cmn_sta_info *entry = NULL; + char dbg_buf[PHYDM_SNPRINT_SIZE] = {0}; + struct phydm_cfo_rpt cfo; + u8 i = 0; + + PHYDM_DBG(dm, DBG_CMN, "ID=((%d)), BW=((%d)), fc=((CH-%d))\n", + dm->curr_station_id, 20 << *dm->band_width, *dm->channel); + + #ifdef ODM_IC_11N_SERIES_SUPPORT + #ifdef PHYDM_PRIMARY_CCA + if (((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_40)) && + (dm->support_ic_type & ODM_IC_11N_SERIES) && + (dm->support_ability & ODM_BB_PRIMARY_CCA)) { + PHYDM_DBG(dm, DBG_CMN, "Primary CCA at ((%s SB))\n", + ((*dm->sec_ch_offset == SECOND_CH_AT_LSB) ? "U" : + "L")); + } + #endif + #endif + + if (dm->cck_new_agc || dm->rx_rate > ODM_RATE11M) { + PHYDM_DBG(dm, DBG_CMN, "[AGC Idx] {0x%x, 0x%x, 0x%x, 0x%x}\n", + dm->ofdm_agc_idx[0], dm->ofdm_agc_idx[1], + dm->ofdm_agc_idx[2], dm->ofdm_agc_idx[3]); + } else { + PHYDM_DBG(dm, DBG_CMN, "[CCK AGC Idx] {LNA,VGA}={0x%x, 0x%x}\n", + dm->cck_lna_idx, dm->cck_vga_idx); + } + + phydm_print_rate_2_buff(dm, dm->rx_rate, dbg_buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_CMN, "RSSI:{%d, %d, %d, %d}, RxRate:%s (0x%x)\n", + (dm->rssi_a == 0xff) ? 0 : dm->rssi_a, + (dm->rssi_b == 0xff) ? 0 : dm->rssi_b, + (dm->rssi_c == 0xff) ? 0 : dm->rssi_c, + (dm->rssi_d == 0xff) ? 0 : dm->rssi_d, + dbg_buf, dm->rx_rate); + + rate = dbg_t->beacon_phy_rate; + phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE); + + PHYDM_DBG(dm, DBG_CMN, "Beacon_cnt=%d, rate_idx=%s (0x%x)\n", + dbg_t->num_qry_beacon_pkt, dbg_buf, dbg_t->beacon_phy_rate); + + phydm_get_phy_statistic(dm); + + PHYDM_DBG(dm, DBG_CMN, + "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n", + dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80); + + /*Print TX rate*/ + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + entry = dm->phydm_sta_info[macid]; + + if (!is_sta_active(entry)) + continue; + + rate = entry->ra_info.curr_tx_rate; + phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_CMN, "TxRate[%d]=%s (0x%x)\n", + macid, dbg_buf, entry->ra_info.curr_tx_rate); + + client_cnt++; + + if (client_cnt >= dm->number_linked_client) + break; + } + + PHYDM_DBG(dm, DBG_CMN, + "TP {Tx, Rx, Total} = {%d, %d, %d}Mbps, Traffic_Load=(%d))\n", + dm->tx_tp, dm->rx_tp, dm->total_tp, dm->traffic_load); + + PHYDM_DBG(dm, DBG_CMN, "CFO_avg=((%d kHz)), CFO_traking = ((%s%d))\n", + cfo_t->CFO_ave_pre, + ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap)); + + /* @CFO report */ + switch (dm->ic_ip_series) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + case PHYDM_IC_JGR3: + PHYDM_DBG(dm, DBG_CMN, "cfo_tail = {%d, %d, %d, %d}\n", + dbg_t->cfo_tail[0], dbg_t->cfo_tail[1], + dbg_t->cfo_tail[2], dbg_t->cfo_tail[3]); + break; + #endif + default: + phydm_get_cfo_info(dm, &cfo); + for (i = 0; i < dm->num_rf_path; i++) { + PHYDM_DBG(dm, DBG_CMN, + "CFO[%d] {S, L, Sec, Acq, End} = {%d, %d, %d, %d, %d}\n", + i, cfo.cfo_rpt_s[i], cfo.cfo_rpt_l[i], + cfo.cfo_rpt_sec[i], cfo.cfo_rpt_acq[i], + cfo.cfo_rpt_end[i]); + } + break; + } + +/* @Condition number */ +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822B) { + PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%.4d)), %d\n", + dbg_t->condi_num >> 4, + phydm_show_fraction_num(dbg_t->condi_num & 0xf, 4), + dbg_t->condi_num); + } +#endif +#ifdef PHYSTS_3RD_TYPE_SUPPORT + if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) { + PHYDM_DBG(dm, DBG_CMN, "Condi_Num=((%d.%4d dB))\n", + dbg_t->condi_num >> 1, + phydm_show_fraction_num(dbg_t->condi_num & 0x1, 1)); + } +#endif + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT)) + /*STBC or LDPC pkt*/ + if (dm->support_ic_type & (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) + PHYDM_DBG(dm, DBG_CMN, "Coding: LDPC=((%s)), STBC=((%s))\n", + (dbg_t->is_ldpc_pkt) ? "Y" : "N", + (dbg_t->is_stbc_pkt) ? "Y" : "N"); +#endif + +#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT) + /*Beamformed pkt*/ + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F)) + PHYDM_DBG(dm, DBG_CMN, "Beamformed=((%s))\n", + (dm->is_beamformed) ? "Y" : "N"); +#endif +} + +void phydm_dm_summary(void *dm_void, u8 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_cfo_track_struct *cfo_t = &dm->dm_cfo_track; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + struct dtp_info *dtp = NULL; + u64 comp = dm->support_ability; + u64 pause_comp = dm->pause_ability; + + if (!(dm->debug_components & DBG_DM_SUMMARY)) + return; + + if (!dm->is_linked) { + pr_debug("[%s]No Link !!!\n", __func__); + return; + } + + sta = dm->phydm_sta_info[macid]; + + if (!is_sta_active(sta)) { + pr_debug("[Warning] %s invalid STA, macid=%d\n", + __func__, macid); + return; + } + + ra = &sta->ra_info; + dtp = &sta->dtp_stat; + pr_debug("[%s]===========>\n", __func__); + + pr_debug("00.(%s) %-12s: IGI=0x%x, Dyn_Rng=0x%x~0x%x, FA_th={%d,%d,%d}\n", + ((comp & ODM_BB_DIG) ? + ((pause_comp & ODM_BB_DIG) ? "P" : "V") : "."), + "DIG", + dig_t->cur_ig_value, + dig_t->rx_gain_range_min, dig_t->rx_gain_range_max, + dig_t->fa_th[0], dig_t->fa_th[1], dig_t->fa_th[2]); + + pr_debug("01.(%s) %-12s: rssi_lv=%d, mask=0x%llx\n", + ((comp & ODM_BB_RA_MASK) ? + ((pause_comp & ODM_BB_RA_MASK) ? "P" : "V") : "."), + "RaMask", + ra->rssi_level, ra->ramask); + +#ifdef CONFIG_DYNAMIC_TX_TWR + pr_debug("02.(%s) %-12s: pwr_lv=%d\n", + ((comp & ODM_BB_DYNAMIC_TXPWR) ? + ((pause_comp & ODM_BB_DYNAMIC_TXPWR) ? "P" : "V") : "."), + "DynTxPwr", + dtp->sta_tx_high_power_lvl); +#endif + + pr_debug("05.(%s) %-12s: cck_pd_lv=%d\n", + ((comp & ODM_BB_CCK_PD) ? + ((pause_comp & ODM_BB_CCK_PD) ? "P" : "V") : "."), + "CCK_PD", dm->dm_cckpd_table.cck_pd_lv); + +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + pr_debug("06.(%s) %-12s: div_type=%d, curr_ant=%s\n", + ((comp & ODM_BB_ANT_DIV) ? + ((pause_comp & ODM_BB_ANT_DIV) ? "P" : "V") : "."), + "ANT_DIV", + dm->ant_div_type, + (dm->dm_fat_table.rx_idle_ant == MAIN_ANT) ? "MAIN" : "AUX"); +#endif + +#ifdef PHYDM_POWER_TRAINING_SUPPORT + pr_debug("08.(%s) %-12s: PT_score=%d, disable_PT=%d\n", + ((comp & ODM_BB_PWR_TRAIN) ? + ((pause_comp & ODM_BB_PWR_TRAIN) ? "P" : "V") : "."), + "PwrTrain", + dm->pow_train_table.pow_train_score, + dm->is_disable_power_training); +#endif + +#ifdef CONFIG_PHYDM_DFS_MASTER + pr_debug("11.(%s) %-12s: dbg_mode=%d, region_domain=%d\n", + ((comp & ODM_BB_DFS) ? + ((pause_comp & ODM_BB_DFS) ? "P" : "V") : "."), + "DFS", + dm->dfs.dbg_mode, dm->dfs_region_domain); +#endif +#ifdef PHYDM_SUPPORT_ADAPTIVITY + pr_debug("13.(%s) %-12s: th{l2h, h2l}={%d, %d}, edcca_flag=%d\n", + ((comp & ODM_BB_ADAPTIVITY) ? + ((pause_comp & ODM_BB_ADAPTIVITY) ? "P" : "V") : "."), + "Adaptivity", + dm->adaptivity.th_l2h, dm->adaptivity.th_h2l, + dm->false_alm_cnt.edcca_flag); +#endif + pr_debug("14.(%s) %-12s: CFO_avg=%d kHz, CFO_traking=%s%d\n", + ((comp & ODM_BB_CFO_TRACKING) ? + ((pause_comp & ODM_BB_CFO_TRACKING) ? "P" : "V") : "."), + "CfoTrack", + cfo_t->CFO_ave_pre, + ((cfo_t->crystal_cap > cfo_t->def_x_cap) ? "+" : "-"), + DIFF_2(cfo_t->crystal_cap, cfo_t->def_x_cap)); + + pr_debug("15.(%s) %-12s: ratio{nhm, clm}={%d, %d}\n", + ((comp & ODM_BB_ENV_MONITOR) ? + ((pause_comp & ODM_BB_ENV_MONITOR) ? "P" : "V") : "."), + "EnvMntr", + dm->dm_ccx_info.nhm_ratio, dm->dm_ccx_info.clm_ratio); + +#ifdef PHYDM_PRIMARY_CCA + pr_debug("16.(%s) %-12s: CCA @ (%s SB)\n", + ((comp & ODM_BB_PRIMARY_CCA) ? + ((pause_comp & ODM_BB_PRIMARY_CCA) ? "P" : "V") : "."), + "PriCCA", + ((dm->dm_pri_cca.mf_state == MF_USC_LSC) ? "D" : + ((dm->dm_pri_cca.mf_state == MF_LSC) ? "L" : "U"))); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + pr_debug("17.(%s) %-12s: soml_en = %s\n", + ((comp & ODM_BB_ADAPTIVE_SOML) ? + ((pause_comp & ODM_BB_ADAPTIVE_SOML) ? "P" : "V") : "."), + "A-SOML", + (dm->dm_soml_table.soml_last_state == SOML_ON) ? + "ON" : "OFF"); +#endif +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + pr_debug("18.(%s) %-12s:\n", + ((comp & ODM_BB_LNA_SAT_CHK) ? + ((pause_comp & ODM_BB_LNA_SAT_CHK) ? "P" : "V") : "."), + "LNA_SAT_CHK"); +#endif +} + +void phydm_basic_dbg_message(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct odm_phy_dbg_info *dbg_b = &dm->phy_dbg_info_win_bkp; + #endif + #ifdef NHM_SUPPORT + struct ccx_info *ccx = &dm->dm_ccx_info; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* backup memory*/ + odm_move_memory(dm, dbg_b, dbg, sizeof(struct odm_phy_dbg_info)); + #endif + + if (!(dm->debug_components & DBG_CMN)) { + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* reset rx rate distribution*/ + phydm_reset_rx_rate_distribution(dm); + /* cal & reset avg of rssi/snr/evm*/ + phydm_get_avg_phystatus_val(dm); + /* reset sum of rssi/snr/evm*/ + phydm_reset_phystatus_statistic(dm); + #endif + return; + } + + if (dm->cmn_dbg_msg_cnt >= dm->cmn_dbg_msg_period) { + dm->cmn_dbg_msg_cnt = PHYDM_WATCH_DOG_PERIOD; + } else { + dm->cmn_dbg_msg_cnt += PHYDM_WATCH_DOG_PERIOD; + return; + } + + PHYDM_DBG(dm, DBG_CMN, "[%s] System up time: ((%d sec))---->\n", + __func__, dm->phydm_sys_up_time); + + if (dm->is_linked) + phydm_basic_dbg_msg_linked(dm); + else + PHYDM_DBG(dm, DBG_CMN, "No Link !!!\n"); + + PHYDM_DBG(dm, DBG_CMN, + "[Tx cnt] {CCK_TxEN, CCK_TxON, OFDM_TxEN, OFDM_TxON} = {%d, %d, %d, %d}\n", + fa_t->cnt_cck_txen, fa_t->cnt_cck_txon, fa_t->cnt_ofdm_txen, + fa_t->cnt_ofdm_txon); + PHYDM_DBG(dm, DBG_CMN, "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all); + PHYDM_DBG(dm, DBG_CMN, "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all); + PHYDM_DBG(dm, DBG_CMN, + "[FA duration(us)] {exp, ifs_clm, fahm} = {%d, %d, %d}\n", + fa_t->time_fa_exp, fa_t->time_fa_ifs_clm, + fa_t->time_fa_fahm); + PHYDM_DBG(dm, DBG_CMN, + "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail); + PHYDM_DBG(dm, DBG_CMN, "[HT FA] CRC8=%d, MCS=%d\n", + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail); +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) { + PHYDM_DBG(dm, DBG_CMN, + "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n", + fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb, + fa_t->cnt_mcs_fail_vht); + } +#endif + PHYDM_DBG(dm, DBG_CMN, + "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n", + fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok, + fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok, + fa_t->cnt_crc32_ok_all); + PHYDM_DBG(dm, DBG_CMN, + "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n", + fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error, + fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error, + fa_t->cnt_crc32_error_all); + + if (dm->support_ic_type & (ODM_IC_11N_SERIES | ODM_IC_11AC_SERIES)) + PHYDM_DBG(dm, DBG_CMN, + "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x, bNoisy=%d\n", + dm->is_linked, dm->number_linked_client, dm->rssi_min, + dm->dm_dig_table.cur_ig_value, dm->noisy_decision); + else + PHYDM_DBG(dm, DBG_CMN, + "is_linked = %d, Num_client = %d, rssi_min = %d, IGI = 0x%x\n", + dm->is_linked, dm->number_linked_client, dm->rssi_min, + dm->dm_dig_table.cur_ig_value); + +#ifdef NHM_SUPPORT + if (dm->support_ability & ODM_BB_ENV_MONITOR) { + PHYDM_DBG(dm, DBG_CMN, + "[NHM] valid: %d percent, noise(RSSI) = %d\n", + ccx->nhm_level_valid, ccx->nhm_level); + } +#endif +} + +void phydm_basic_profile(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; + char *cut = NULL; + char *ic_type = NULL; + u32 used = *_used; + u32 out_len = *_out_len; + u32 date = 0; + char *commit_by = NULL; + u32 release_ver = 0; + + PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n", + "% Basic Profile %"); + + if (dm->support_ic_type == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT) + ic_type = "RTL8188E"; + date = RELEASE_DATE_8188E; + commit_by = COMMIT_BY_8188E; + release_ver = RELEASE_VERSION_8188E; +#endif +#if (RTL8812A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8812) { + ic_type = "RTL8812A"; + date = RELEASE_DATE_8812A; + commit_by = COMMIT_BY_8812A; + release_ver = RELEASE_VERSION_8812A; +#endif +#if (RTL8821A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8821) { + ic_type = "RTL8821A"; + date = RELEASE_DATE_8821A; + commit_by = COMMIT_BY_8821A; + release_ver = RELEASE_VERSION_8821A; +#endif +#if (RTL8192E_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8192E) { + ic_type = "RTL8192E"; + date = RELEASE_DATE_8192E; + commit_by = COMMIT_BY_8192E; + release_ver = RELEASE_VERSION_8192E; +#endif +#if (RTL8723B_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8723B) { + ic_type = "RTL8723B"; + date = RELEASE_DATE_8723B; + commit_by = COMMIT_BY_8723B; + release_ver = RELEASE_VERSION_8723B; +#endif +#if (RTL8814A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8814A) { + ic_type = "RTL8814A"; + date = RELEASE_DATE_8814A; + commit_by = COMMIT_BY_8814A; + release_ver = RELEASE_VERSION_8814A; +#endif +#if (RTL8881A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8881A) { + ic_type = "RTL8881A"; +#endif +#if (RTL8822B_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8822B) { + ic_type = "RTL8822B"; + date = RELEASE_DATE_8822B; + commit_by = COMMIT_BY_8822B; + release_ver = RELEASE_VERSION_8822B; +#endif +#if (RTL8197F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8197F) { + ic_type = "RTL8197F"; + date = RELEASE_DATE_8197F; + commit_by = COMMIT_BY_8197F; + release_ver = RELEASE_VERSION_8197F; +#endif +#if (RTL8703B_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8703B) { + ic_type = "RTL8703B"; + date = RELEASE_DATE_8703B; + commit_by = COMMIT_BY_8703B; + release_ver = RELEASE_VERSION_8703B; +#endif +#if (RTL8195A_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8195A) { + ic_type = "RTL8195A"; +#endif +#if (RTL8188F_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8188F) { + ic_type = "RTL8188F"; + date = RELEASE_DATE_8188F; + commit_by = COMMIT_BY_8188F; + release_ver = RELEASE_VERSION_8188F; +#endif +#if (RTL8723D_SUPPORT) + } else if (dm->support_ic_type == ODM_RTL8723D) { + ic_type = "RTL8723D"; + date = RELEASE_DATE_8723D; + commit_by = COMMIT_BY_8723D; + release_ver = RELEASE_VERSION_8723D; +#endif + } + +/* @JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8710B) { + ic_type = "RTL8710B"; + date = RELEASE_DATE_8710B; + commit_by = COMMIT_BY_8710B; + release_ver = RELEASE_VERSION_8710B; + } +#endif + +#if (RTL8721D_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8721D) { + ic_type = "RTL8721D"; + date = RELEASE_DATE_8721D; + commit_by = COMMIT_BY_8721D; + release_ver = RELEASE_VERSION_8721D; + } +#endif + +#if (RTL8710C_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8710C) { + ic_type = "RTL8710C"; + date = RELEASE_DATE_8710C; + commit_by = COMMIT_BY_8710C; + release_ver = RELEASE_VERSION_8710C; + } +#endif + +#if (RTL8821C_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8821C) { + ic_type = "RTL8821C"; + date = RELEASE_DATE_8821C; + commit_by = COMMIT_BY_8821C; + release_ver = RELEASE_VERSION_8821C; + } +#endif + +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8192F) { + ic_type = "RTL8192F"; + date = RELEASE_DATE_8192F; + commit_by = COMMIT_BY_8192F; + release_ver = RELEASE_VERSION_8192F; + } +#endif + +#if (RTL8198F_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8198F) { + ic_type = "RTL8198F"; + date = RELEASE_DATE_8198F; + commit_by = COMMIT_BY_8198F; + release_ver = RELEASE_VERSION_8198F; + } +#endif + +#if (RTL8822C_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8822C) { + ic_type = "RTL8822C"; + date = RELEASE_DATE_8822C; + commit_by = COMMIT_BY_8822C; + release_ver = RELEASE_VERSION_8822C; + } +#endif + +#if (RTL8723F_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8723F) { + ic_type = "RTL8723F"; + date = RELEASE_DATE_8723F; + commit_by = COMMIT_BY_8723F; + release_ver = RELEASE_VERSION_8723F; + } +#endif +#if (RTL8812F_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8812F) { + ic_type = "RTL8812F"; + date = RELEASE_DATE_8812F; + commit_by = COMMIT_BY_8812F; + release_ver = RELEASE_VERSION_8812F; + } +#endif + +#if (RTL8197G_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8197G) { + ic_type = "RTL8197G"; + date = RELEASE_DATE_8197G; + commit_by = COMMIT_BY_8197G; + release_ver = RELEASE_VERSION_8197G; + } +#endif + +#if (RTL8814B_SUPPORT) + else if (dm->support_ic_type == ODM_RTL8814B) { + ic_type = "RTL8814B"; + date = RELEASE_DATE_8814B; + commit_by = COMMIT_BY_8814B; + release_ver = RELEASE_VERSION_8814B; + } +#endif + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s (MP Chip: %s)\n", "IC type", ic_type, + dm->is_mp_chip ? "Yes" : "No"); + + if (dm->cut_version == ODM_CUT_A) + cut = "A"; + else if (dm->cut_version == ODM_CUT_B) + cut = "B"; + else if (dm->cut_version == ODM_CUT_C) + cut = "C"; + else if (dm->cut_version == ODM_CUT_D) + cut = "D"; + else if (dm->cut_version == ODM_CUT_E) + cut = "E"; + else if (dm->cut_version == ODM_CUT_F) + cut = "F"; + else if (dm->cut_version == ODM_CUT_G) + cut = "G"; + else if (dm->cut_version == ODM_CUT_H) + cut = "H"; + else if (dm->cut_version == ODM_CUT_I) + cut = "I"; + else if (dm->cut_version == ODM_CUT_J) + cut = "J"; + else if (dm->cut_version == ODM_CUT_K) + cut = "K"; + else if (dm->cut_version == ODM_CUT_L) + cut = "L"; + else if (dm->cut_version == ODM_CUT_M) + cut = "M"; + else if (dm->cut_version == ODM_CUT_N) + cut = "N"; + else if (dm->cut_version == ODM_CUT_O) + cut = "O"; + else if (dm->cut_version == ODM_CUT_TEST) + cut = "TEST"; + else + cut = "UNKNOWN"; + + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "RFE type", dm->rfe_type); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "CART_Ver", cut); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "PHY Para Ver", odm_get_hw_img_version(dm)); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "PHY Para Commit date", date); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "PHY Para Commit by", commit_by); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %d\n", + "PHY Para Release Ver", release_ver); + + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %d (Subversion: %d)\n", "FW Ver", dm->fw_version, + dm->fw_sub_version); + + /* @1 PHY DM version List */ + PDM_SNPF(out_len, used, output + used, out_len - used, "%-35s\n", + "% PHYDM version %"); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Code base", PHYDM_CODE_BASE); +#ifdef PHYDM_SVN_REV + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "PHYDM SVN Ver", PHYDM_SVN_REV); +#endif + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Release Date", PHYDM_RELEASE_DATE); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Adaptivity", ADAPTIVITY_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "DIG", DIG_VERSION); + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "CFO Tracking", CFO_TRACKING_VERSION); +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "AntDiv", ANTDIV_VERSION); +#endif +#ifdef CONFIG_DYNAMIC_TX_TWR + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Dynamic TxPower", DYNAMIC_TXPWR_VERSION); +#endif + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "RA Info", RAINFO_VERSION); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "AntDetect", ANTDECT_VERSION); +#endif +#ifdef CONFIG_PATH_DIVERSITY + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "PathDiv", PATHDIV_VERSION); +#endif +#ifdef CONFIG_ADAPTIVE_SOML + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Adaptive SOML", ADAPTIVE_SOML_VERSION); +#endif +#if (PHYDM_LA_MODE_SUPPORT) + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "LA mode", DYNAMIC_LA_MODE); +#endif +#ifdef PHYDM_PRIMARY_CCA + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "Primary CCA", PRIMARYCCA_VERSION); +#endif + PDM_SNPF(out_len, used, output + used, out_len - used, " %-35s: %s\n", + "DFS", DFS_VERSION); + +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8822B", + PHY_CONFIG_VERSION_8822B); + +#endif +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8197F", + PHY_CONFIG_VERSION_8197F); +#endif + +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8192F", + PHY_CONFIG_VERSION_8192F); +#endif +#if (RTL8721D_SUPPORT) + if (dm->support_ic_type & ODM_RTL8721D) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8721D", + PHY_CONFIG_VERSION_8721D); +#endif + +#if (RTL8710C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8710C) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s: %s\n", "PHY config 8710C", + PHY_CONFIG_VERSION_8710C); +#endif + + *_used = used; + *_out_len = out_len; + +#endif /*@#if CONFIG_PHYDM_DEBUG_FUNCTION*/ +} + +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION +void phydm_fw_trace_en_h2c(void *dm_void, boolean enable, + u32 fw_dbg_comp, u32 monitor_mode, u32 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 h2c_parameter[7] = {0}; + u8 cmd_length; + + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + h2c_parameter[0] = enable; + h2c_parameter[1] = (u8)(fw_dbg_comp & MASKBYTE0); + h2c_parameter[2] = (u8)((fw_dbg_comp & MASKBYTE1) >> 8); + h2c_parameter[3] = (u8)((fw_dbg_comp & MASKBYTE2) >> 16); + h2c_parameter[4] = (u8)((fw_dbg_comp & MASKBYTE3) >> 24); + h2c_parameter[5] = (u8)monitor_mode; + h2c_parameter[6] = (u8)macid; + cmd_length = 7; + + } else { + h2c_parameter[0] = enable; + h2c_parameter[1] = (u8)monitor_mode; + h2c_parameter[2] = (u8)macid; + cmd_length = 3; + } + + PHYDM_DBG(dm, DBG_FW_TRACE, + "[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", + enable, monitor_mode, macid); + + odm_fill_h2c_cmd(dm, PHYDM_H2C_FW_TRACE_EN, cmd_length, h2c_parameter); +} + +void phydm_get_per_path_txagc(void *dm_void, u8 path, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_idx = 0; + u8 txagc = 0; + u32 used = *_used; + u32 out_len = *_out_len; + +#ifdef PHYDM_COMMON_API_SUPPORT + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) + return; + + if (dm->num_rf_path == 1 && path > RF_PATH_A) + return; + else if (dm->num_rf_path == 2 && path > RF_PATH_B) + return; + else if (dm->num_rf_path == 3 && path > RF_PATH_C) + return; + else if (dm->num_rf_path == 4 && path > RF_PATH_D) + return; + + for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { + if (!(dm->support_ic_type & PHYDM_IC_ABOVE_3SS) && + ((rate_idx >= ODM_RATEMCS16 && + rate_idx < ODM_RATEVHTSS1MCS0) || + rate_idx >= ODM_RATEVHTSS3MCS0)) + continue; + + if (rate_idx == ODM_RATE1M) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-35s\n", "CCK====>"); + else if (rate_idx == ODM_RATE6M) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "OFDM====>"); + else if (rate_idx == ODM_RATEMCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 1ss====>"); + else if (rate_idx == ODM_RATEMCS8) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 2ss====>"); + else if (rate_idx == ODM_RATEMCS16) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 3ss====>"); + else if (rate_idx == ODM_RATEMCS24) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "HT 4ss====>"); + else if (rate_idx == ODM_RATEVHTSS1MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 1ss====>"); + else if (rate_idx == ODM_RATEVHTSS2MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 2ss====>"); + else if (rate_idx == ODM_RATEVHTSS3MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 3ss====>"); + else if (rate_idx == ODM_RATEVHTSS4MCS0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n %-35s\n", "VHT 4ss====>"); + + txagc = phydm_api_get_txagc(dm, (enum rf_path)path, rate_idx); + if (config_phydm_read_txagc_check(txagc)) + PDM_SNPF(out_len, used, output + used, + out_len - used, " 0x%02x ", txagc); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, " 0x%s ", "xx"); + } +#endif + + *_used = used; + *_out_len = out_len; +} + +void phydm_get_txagc(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + #if (RTL8822C_SUPPORT) + PDM_SNPF(out_len, used, output + used, + out_len - used, "Disabled DPD rate mask: 0x%x\n", + dm->dis_dpd_rate); + #endif + + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if (i == RF_PATH_A) + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-35s\n", "path-A===================="); + else if (i == RF_PATH_B) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n%-35s\n", "path-B===================="); + else if (i == RF_PATH_C) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n%-35s\n", "path-C===================="); + else if (i == RF_PATH_D) + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n%-35s\n", "path-D===================="); + + phydm_get_per_path_txagc(dm, i, &used, output, &out_len); + } + *_used = used; + *_out_len = out_len; +} + +void phydm_set_txagc(void *dm_void, u32 *const val, u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u32 pow = 0; /*power index*/ + u8 vht_start_rate = ODM_RATEVHTSS1MCS0; + boolean rpt = true; + enum rf_path path = RF_PATH_A; + +/*@val[1] = path*/ +/*@val[2] = hw_rate*/ +/*@val[3] = power_index*/ + +#ifdef PHYDM_COMMON_API_SUPPORT + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) + return; + + path = (enum rf_path)val[1]; + + if (val[1] >= dm->num_rf_path) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d rate_idx-0x%x fail\n", val[1], val[2]); + } else if ((u8)val[2] != 0xff) { + if (phydm_api_set_txagc(dm, val[3], path, (u8)val[2], true)) + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d rate_idx-0x%x = 0x%x\n", + val[1], val[2], val[3]); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d rate index-0x%x fail\n", + val[1], val[2]); + } else { + + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) { + pow = (val[3] & 0x3f); + pow = BYTE_DUPLICATE_2_DWORD(pow); + + for (i = 0; i < ODM_RATEVHTSS2MCS9; i += 4) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F)) { + pow = (val[3] & 0x3f); + for (i = 0; i <= ODM_RATEMCS15; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type & ODM_RTL8198F) { + pow = (val[3] & 0x7f); + for (i = 0; i <= ODM_RATEVHTSS4MCS9; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type & + (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G)) { + pow = (val[3] & 0x7f); + for (i = 0; i <= ODM_RATEMCS15; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type & + (ODM_RTL8721D | ODM_RTL8710C)) { + pow = (val[3] & 0x3f); + for (i = 0; i <= ODM_RATEMCS7; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } else if (dm->support_ic_type &(ODM_RTL8723F)) { + pow = (val[3] & 0x7f); + for (i = 0; i <= ODM_RATEMCS7; i++) + rpt &= phydm_api_set_txagc(dm, pow, path, i, 0); + } + + if (rpt) + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write all TXAGC of path-%d = 0x%x\n", + val[1], val[3]); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write all TXAGC of path-%d fail\n", val[1]); + } + +#endif + *_used = used; + *_out_len = out_len; +} + +void phydm_shift_txagc(void *dm_void, u32 *const val, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u32 pow = 0; /*Power index*/ + boolean rpt = true; + u8 vht_start_rate = ODM_RATEVHTSS1MCS0; + enum rf_path path = RF_PATH_A; + +#ifdef PHYDM_COMMON_API_SUPPORT + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) + return; + + if (val[1] >= dm->num_rf_path) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Write path-%d fail\n", val[1]); + return; + } + + path = (enum rf_path)val[1]; + + if ((u8)val[2] == 0) { + /*@{0:-, 1:+} {Pwr Offset}*/ + if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) { + for (i = 0; i <= ODM_RATEMCS7; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & (ODM_RTL8822B)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + rpt &= phydm_api_shift_txagc(dm, val[3], path, 0); + } else if (dm->support_ic_type & + (ODM_RTL8721D | ODM_RTL8710C)) { + for (i = 0; i <= ODM_RATEMCS7; i++) { + pow = phydm_api_get_txagc(dm, path, i) - val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } + } else if ((u8)val[2] == 1) { + /*@{0:-, 1:+} {Pwr Offset}*/ + if (dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)) { + for (i = 0; i <= ODM_RATEMCS7; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS1MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & (ODM_RTL8822B)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + for (i = vht_start_rate; i <= ODM_RATEVHTSS2MCS9; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F)) { + for (i = 0; i <= ODM_RATEMCS15; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & (ODM_RTL8721D | + ODM_RTL8710C)) { + for (i = 0; i <= ODM_RATEMCS7; i++) { + pow = phydm_api_get_txagc(dm, path, i) + val[3]; + rpt &= phydm_api_set_txagc(dm, pow, path, i, 1); + } + } else if (dm->support_ic_type & + (ODM_RTL8822C | ODM_RTL8814B | + ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F)) { + rpt &= phydm_api_shift_txagc(dm, val[3], path, 1); + } + } + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + PDM_SNPF(out_len, used, output + used, out_len - used, + "[All rate] Set Path-%d Pow_idx: %s %d\n", + val[1], (val[2] ? "+" : "-"), val[3]); + else + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "[All rate] Set Path-%d Pow_idx: %s %d(%d.%s dB)\n", + val[1], (val[2] ? "+" : "-"), val[3], val[3] >> 1, + ((val[3] & 1) ? "5" : "0")); + +#endif + *_used = used; + *_out_len = out_len; +} + +void phydm_set_txagc_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[10] = {0}; + char help[] = "-h"; + u8 i = 0, input_idx = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{Dis:0, En:1} {pathA~D(0~3)} {rate_idx(Hex), All_rate:0xff} {txagc_idx (Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{Pwr Shift(All rate):2} {pathA~D(0~3)} {0:-, 1:+} {Pwr Offset(Hex)}\n"); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + PDM_SNPF(out_len, used, output + used, out_len - used, + "{reset all rate ref/diff to 0x0:0xff}\n"); + #endif + } else if (var1[0] == 0) { + dm->is_disable_phy_api = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable API debug mode\n"); + } else if (var1[0] == 1) { + dm->is_disable_phy_api = false; + #ifdef CONFIG_TXAGC_DEBUG_8822C + config_phydm_write_txagc_8822c(dm, var1[3], + (enum rf_path)var1[1], + (u8)var1[2]); + #elif (defined(CONFIG_TXAGC_DEBUG_8814B)) + config_phydm_write_txagc_8814b(dm, var1[3], + (enum rf_path)var1[1], + (u8)var1[2]); + #else + phydm_set_txagc(dm, (u32 *)var1, &used, output, &out_len); + #endif + dm->is_disable_phy_api = true; + } else if (var1[0] == 2) { + PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]); + dm->is_disable_phy_api = false; + phydm_shift_txagc(dm, (u32 *)var1, &used, output, &out_len); + dm->is_disable_phy_api = true; + } + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + else if (var1[0] == 0xff) { + dm->is_disable_phy_api = false; + phydm_reset_txagc(dm); + dm->is_disable_phy_api = true; + } + #endif + #ifdef CONFIG_TXAGC_DEBUG_8822C + else if (var1[0] == 3) { + dm->is_disable_phy_api = false; + phydm_txagc_tab_buff_show_8822c(dm); + dm->is_disable_phy_api = true; + } else if (var1[0] == 4) { + dm->is_disable_phy_api = false; + config_phydm_set_txagc_to_hw_8822c(dm); + dm->is_disable_phy_api = true; + } + #elif (defined(CONFIG_TXAGC_DEBUG_8814B)) + else if (var1[0] == 3) { + dm->is_disable_phy_api = false; + phydm_txagc_tab_buff_show_8814b(dm); + dm->is_disable_phy_api = true; + } else if (var1[0] == 4) { + dm->is_disable_phy_api = false; + config_phydm_set_txagc_to_hw_8814b(dm); + dm->is_disable_phy_api = true; + } + #endif + + *_used = used; + *_out_len = out_len; +} + +void phydm_cmn_msg_setting(void *dm_void, u32 *val, u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + if (val[1] == 1) { + dm->cmn_dbg_msg_period = (u8)val[2]; + + if (dm->cmn_dbg_msg_period < PHYDM_WATCH_DOG_PERIOD) + dm->cmn_dbg_msg_period = PHYDM_WATCH_DOG_PERIOD; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "cmn_dbg_msg_period=%d\n", dm->cmn_dbg_msg_period); + } + +#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + if (val[1] == 1) + phydm_physts_auto_switch_jgr3_set(dm, true, BIT(4) | BIT(1)); + else + phydm_physts_auto_switch_jgr3_set(dm, false, BIT(1)); +#endif + *_used = used; + *_out_len = out_len; +} + +void phydm_debug_trace(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u64 pre_debug_components, one = 1; + u64 comp = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + u8 i = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + } + comp = dm->debug_components; + pre_debug_components = dm->debug_components; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "\n================================\n"); + if (val[0] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[DBG MSG] Component Selection\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "00. (( %s ))DIG\n", + ((comp & DBG_DIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "01. (( %s ))RA_MASK\n", + ((comp & DBG_RA_MASK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "02. (( %s ))DYN_TXPWR\n", + ((comp & DBG_DYN_TXPWR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "03. (( %s ))FA_CNT\n", + ((comp & DBG_FA_CNT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "04. (( %s ))RSSI_MNTR\n", + ((comp & DBG_RSSI_MNTR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "05. (( %s ))CCKPD\n", + ((comp & DBG_CCKPD) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "06. (( %s ))ANT_DIV\n", + ((comp & DBG_ANT_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "07. (( %s ))SMT_ANT\n", + ((comp & DBG_SMT_ANT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "08. (( %s ))PWR_TRAIN\n", + ((comp & DBG_PWR_TRAIN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "09. (( %s ))RA\n", + ((comp & DBG_RA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "10. (( %s ))PATH_DIV\n", + ((comp & DBG_PATH_DIV) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "11. (( %s ))DFS\n", + ((comp & DBG_DFS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "12. (( %s ))DYN_ARFR\n", + ((comp & DBG_DYN_ARFR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "13. (( %s ))ADAPTIVITY\n", + ((comp & DBG_ADPTVTY) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "14. (( %s ))CFO_TRK\n", + ((comp & DBG_CFO_TRK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "15. (( %s ))ENV_MNTR\n", + ((comp & DBG_ENV_MNTR) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "16. (( %s ))PRI_CCA\n", + ((comp & DBG_PRI_CCA) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "17. (( %s ))ADPTV_SOML\n", + ((comp & DBG_ADPTV_SOML) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "18. (( %s ))LNA_SAT_CHK\n", + ((comp & DBG_LNA_SAT_CHK) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "20. (( %s ))PHY_STATUS\n", + ((comp & DBG_PHY_STATUS) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "21. (( %s ))TMP\n", + ((comp & DBG_TMP) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "22. (( %s ))FW_DBG_TRACE\n", + ((comp & DBG_FW_TRACE) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "23. (( %s ))TXBF\n", + ((comp & DBG_TXBF) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "24. (( %s ))COMMON_FLOW\n", + ((comp & DBG_COMMON_FLOW) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "28. (( %s ))PHY_CONFIG\n", + ((comp & ODM_PHY_CONFIG) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "29. (( %s ))INIT\n", + ((comp & ODM_COMP_INIT) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "30. (( %s ))COMMON\n", + ((comp & DBG_CMN) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "31. (( %s ))API\n", + ((comp & ODM_COMP_API) ? ("V") : ("."))); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + } else if (val[0] == 101) { + dm->debug_components = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable all debug components\n"); + } else { + if (val[1] == 1) /*@enable*/ + dm->debug_components |= (one << val[0]); + else if (val[1] == 2) /*@disable*/ + dm->debug_components &= ~(one << val[0]); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Warning] 1:on, 2:off\n"); + + if ((BIT(val[0]) == DBG_PHY_STATUS) && val[1] == 1) { + dm->phy_dbg_info.show_phy_sts_all_pkt = (u8)val[2]; + dm->phy_dbg_info.show_phy_sts_max_cnt = (u16)val[3]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "show_all_pkt=%d, show_max_num=%d\n\n", + dm->phy_dbg_info.show_phy_sts_all_pkt, + dm->phy_dbg_info.show_phy_sts_max_cnt); + + } else if (BIT(val[0]) == DBG_CMN) { + phydm_cmn_msg_setting(dm, val, &used, output, &out_len); + } + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "pre-DbgComponents = 0x%llx\n", pre_debug_components); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Curr-DbgComponents = 0x%llx\n", dm->debug_components); + PDM_SNPF(out_len, used, output + used, out_len - used, + "================================\n"); + + *_used = used; + *_out_len = out_len; +} + +void phydm_fw_debug_trace(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + u8 i, input_idx = 0; + char help[] = "-h"; + u32 pre_fw_debug_components = 0, one = 1; + u32 comp = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + pre_fw_debug_components = dm->fw_debug_components; + comp = dm->fw_debug_components; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{dbg_comp} {1:en, 2:dis} {mode} {macid}\n"); + } else { + if (val[0] == 101) { + dm->fw_debug_components = 0; + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s\n", "Clear all fw debug components"); + } else { + if (val[1] == 1) /*@enable*/ + dm->fw_debug_components |= (one << val[0]); + else if (val[1] == 2) /*@disable*/ + dm->fw_debug_components &= ~(one << val[0]); + else + PDM_SNPF(out_len, used, output + used, + out_len - used, "%s\n", + "[Warning!!!] 1:enable, 2:disable"); + } + + comp = dm->fw_debug_components; + + if (comp == 0) { + dm->debug_components &= ~DBG_FW_TRACE; + /*@H2C to enable C2H Msg*/ + phydm_fw_trace_en_h2c(dm, false, comp, val[2], val[3]); + } else { + dm->debug_components |= DBG_FW_TRACE; + /*@H2C to enable C2H Msg*/ + phydm_fw_trace_en_h2c(dm, true, comp, val[2], val[3]); + } + } +} + +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_dump_bb_reg_n(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + + /*@For Nseries IC we only need to dump page8 to pageF using 3 digits*/ + for (addr = 0x800; addr < 0xfff; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%03x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + } + + *_used = used; + *_out_len = out_len; +} +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT) +void phydm_dump_bb_reg_ac(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + + for (addr = 0x800; addr < 0xfff; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + } + + if (!(dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8814A | ODM_RTL8821C | ODM_RTL8195B))) + goto rpt_reg; + + if (dm->rf_type > RF_2T2R) { + for (addr = 0x1800; addr < 0x18ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + } + + if (dm->rf_type > RF_3T3R) { + for (addr = 0x1a00; addr < 0x1aff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + } + + for (addr = 0x1900; addr < 0x19ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + + for (addr = 0x1c00; addr < 0x1cff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + + for (addr = 0x1f00; addr < 0x1fff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + +rpt_reg: + + *_used = used; + *_out_len = out_len; +} + +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_dump_bb_reg_jgr3(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + for (addr = 0x800; addr < 0xdff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + + for (addr = 0x1800; addr < 0x1aff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + + for (addr = 0x1c00; addr < 0x1eff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + + #if (defined(RTL8723F_SUPPORT)) + if (dm->support_ic_type & ODM_RTL8723F) { + for (addr = 0x2a00; addr < 0x2a5c; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, + MASKDWORD)); + } + } + #endif + + for (addr = 0x4000; addr < 0x41ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + + #if (defined(RTL8723F_SUPPORT)) + if (dm->support_ic_type & ODM_RTL8723F) { + for (addr = 0x4300; addr < 0x43bf; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, + MASKDWORD)); + } + } + #endif + } + *_used = used; + *_out_len = out_len; +} + +void phydm_dump_bb_reg2_jgr3(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + for (addr = 0x5000; addr < 0x53ff; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + } + } + #endif + + /* @Do not change the order of page-2C/2D*/ + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "------ BB report-register start ------\n"); + + #if (defined(RTL8723F_SUPPORT)) + if (dm->support_ic_type & ODM_RTL8723F) { + for (addr = 0x2aa0; addr < 0x2aff; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%04x 0x%08x\n", + addr, + odm_get_bb_reg(dm, addr, MASKDWORD)); + } + } + #endif + + for (addr = 0x2c00; addr < 0x2dff; addr += 4) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_get_per_path_anapar_jgr3(void *dm_void, u8 path, u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 state = 0; + u8 state_bp = 0; + u32 control_bb = 0; + u32 control_pow = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 reg_idx = 0; + u32 dbgport_idx = 0; + u32 dbgport_val = 0; + + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "path-%d:\n", path); + + if (path == RF_PATH_A) { + reg_idx = R_0x1830; + dbgport_idx = 0x9F0; + } else if (path == RF_PATH_B) { + reg_idx = R_0x4130; + dbgport_idx = 0xBF0; + } else if (path == RF_PATH_C) { + reg_idx = R_0x5230; + dbgport_idx = 0xDF0; + } else if (path == RF_PATH_D) { + reg_idx = R_0x5330; + dbgport_idx = 0xFF0; + } + + state_bp = (u8)odm_get_bb_reg(dm, reg_idx, 0xf00000); + odm_set_bb_reg(dm, reg_idx, 0x38000000, 0x5); /* @read en*/ + + for (state = 0; state <= 0xf; state++) { + odm_set_bb_reg(dm, reg_idx, 0xF00000, state); + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbgport_idx)) { + dbgport_val = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } else { + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, + "state:0x%x = read dbg_port error!\n", + state); + } + control_bb = (dbgport_val & 0xFFFF0) >> 4; + control_pow = dbgport_val & 0xF; + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "state:0x%x = control_bb:0x%x pow_bb:0x%x\n", + state, control_bb, control_pow); + } + odm_set_bb_reg(dm, reg_idx, 0xf00000, state_bp); + odm_set_bb_reg(dm, reg_idx, 0x38000000, 0x6); /* @write en*/ + + *_used = used; + *_out_len = out_len; +} + +void phydm_get_csi_table_jgr3(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 table_idx = 0; + u8 table_val = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dbgport_idx = 0x39e; + u32 dbgport_val = 0; + + /*enable clk*/ + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x3); + /*enable read table*/ + odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x2); + + for (table_idx = 0; table_idx < 128; table_idx++) { + odm_set_bb_reg(dm, R_0x1d94, MASKBYTE2, table_idx); + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbgport_idx)) { + dbgport_val = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } else { + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, + "table_idx:0x%x = read dbg_port error!\n", + table_idx); + } + table_val = dbgport_val >> 24; + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "table_idx: 0x%x = 0x%x\n", + table_idx, table_val); + } + /*enable write table*/ + odm_set_bb_reg(dm, R_0x1d94, BIT(31) | BIT(30), 0x1); + /*disable clk*/ + odm_set_bb_reg(dm, R_0x1ee8, 0x3, 0x0); + + *_used = used; + *_out_len = out_len; +} + +#endif + +void phydm_dump_bb_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "BB==========\n"); + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "------ BB control register start ------\n"); + + switch (dm->ic_ip_series) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + case PHYDM_IC_JGR3: + phydm_dump_bb_reg_jgr3(dm, &used, output, &out_len); + break; + #endif + + #if (ODM_IC_11AC_SERIES_SUPPORT) + case PHYDM_IC_AC: + phydm_dump_bb_reg_ac(dm, &used, output, &out_len); + break; + #endif + + #if (ODM_IC_11N_SERIES_SUPPORT) + case PHYDM_IC_N: + phydm_dump_bb_reg_n(dm, &used, output, &out_len); + break; + #endif + + default: + break; + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_dump_rf_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + u32 reg = 0; + + /* @dump RF register */ + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-A==========\n"); + + for (addr = 0; addr <= 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_A, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%02x 0x%05x\n", addr, reg); + } + +#ifdef PHYDM_COMPILE_ABOVE_2SS + if (dm->rf_type > RF_1T1R) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-B==========\n"); + + for (addr = 0; addr <= 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_B, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%02x 0x%05x\n", + addr, reg); + } + } +#endif + +#ifdef PHYDM_COMPILE_ABOVE_3SS + if (dm->rf_type > RF_2T2R) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-C==========\n"); + + for (addr = 0; addr <= 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_C, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%02x 0x%05x\n", + addr, reg); + } + } +#endif + +#ifdef PHYDM_COMPILE_ABOVE_4SS + if (dm->rf_type > RF_3T3R) { + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "RF-D==========\n"); + + for (addr = 0; addr <= 0xFF; addr++) { + reg = odm_get_rf_reg(dm, RF_PATH_D, addr, RFREG_MASK); + PDM_VAST_SNPF(out_len, used, output + used, + out_len - used, "0x%02x 0x%05x\n", + addr, reg); + } + } +#endif + + *_used = used; + *_out_len = out_len; +} + +void phydm_dump_mac_reg(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 addr = 0; + u32 used = *_used; + u32 out_len = *_out_len; + + /* @dump MAC register */ + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "MAC==========\n"); + + for (addr = 0; addr < 0x7ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + + for (addr = 0x1000; addr < 0x17ff; addr += 4) + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "0x%04x 0x%08x\n", + addr, odm_get_bb_reg(dm, addr, MASKDWORD)); + + *_used = used; + *_out_len = out_len; +} + +void phydm_dump_reg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 addr = 0; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + PDM_SNPF(out_len, used, output + used, out_len - used, + "dumpreg {0:all, 1:BB, 2:RF, 3:MAC 4:BB2 for jgr3}\n"); + else + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "dumpreg {0:all, 1:BB, 2:RF, 3:MAC}\n"); + } else if (var1[0] == 0) { + phydm_dump_mac_reg(dm, &used, output, &out_len); + phydm_dump_bb_reg(dm, &used, output, &out_len); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->ic_ip_series == PHYDM_IC_JGR3) + phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len); + #endif + + phydm_dump_rf_reg(dm, &used, output, &out_len); + } else if (var1[0] == 1) { + phydm_dump_bb_reg(dm, &used, output, &out_len); + } else if (var1[0] == 2) { + phydm_dump_rf_reg(dm, &used, output, &out_len); + } else if (var1[0] == 3) { + phydm_dump_mac_reg(dm, &used, output, &out_len); + } else if (var1[0] == 4) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->ic_ip_series == PHYDM_IC_JGR3) + phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len); + #endif + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_enable_big_jump(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8822B_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u32 dm_value[10] = {0}; + u8 i, input_idx = 0; + u32 val; + + if (!(dm->support_ic_type & ODM_RTL8822B)) + return; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + if (dm_value[0] == 0) { + dm->dm_dig_table.enable_adjust_big_jump = false; + + val = (dig_t->big_jump_step3 << 5) | + (dig_t->big_jump_step2 << 3) | + dig_t->big_jump_step1; + + odm_set_bb_reg(dm, R_0x8c8, 0xfe, val); + } else { + dm->dm_dig_table.enable_adjust_big_jump = true; + } +#endif +} + +void phydm_show_rx_rate(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8814B_SUPPORT ||\ + RTL8195B_SUPPORT || RTL8822C_SUPPORT || RTL8723F_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[10] = {0}; + char help[] = "-h"; + u8 i, input_idx = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1: show Rx rate, 0:reset counter}\n"); + *_used = used; + *_out_len = out_len; + return; + + } else if (var1[0] == 0) { + phydm_reset_rx_rate_distribution(dm); + *_used = used; + *_out_len = out_len; + return; + } + + /* @==Show SU Rate====================================================*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "=====Rx SU rate Statistics=====\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_qry_vht_pkt[0], dbg->num_qry_vht_pkt[1], + dbg->num_qry_vht_pkt[2], dbg->num_qry_vht_pkt[3], + dbg->num_qry_vht_pkt[4], dbg->num_qry_vht_pkt[5], + dbg->num_qry_vht_pkt[6], dbg->num_qry_vht_pkt[7], + dbg->num_qry_vht_pkt[8], dbg->num_qry_vht_pkt[9]); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_qry_vht_pkt[10], dbg->num_qry_vht_pkt[11], + dbg->num_qry_vht_pkt[12], dbg->num_qry_vht_pkt[13], + dbg->num_qry_vht_pkt[14], dbg->num_qry_vht_pkt[15], + dbg->num_qry_vht_pkt[16], dbg->num_qry_vht_pkt[17], + dbg->num_qry_vht_pkt[18], dbg->num_qry_vht_pkt[19]); + } + #endif + /* @==Show MU Rate====================================================*/ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) || (defined(PHYSTS_3RD_TYPE_SUPPORT)) + PDM_SNPF(out_len, used, output + used, out_len - used, + "=====Rx MU rate Statistics=====\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[MU][1SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_mu_vht_pkt[0], dbg->num_mu_vht_pkt[1], + dbg->num_mu_vht_pkt[2], dbg->num_mu_vht_pkt[3], + dbg->num_mu_vht_pkt[4], dbg->num_mu_vht_pkt[5], + dbg->num_mu_vht_pkt[6], dbg->num_mu_vht_pkt[7], + dbg->num_mu_vht_pkt[8], dbg->num_mu_vht_pkt[9]); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_2SS)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[MU][2SS] {%d, %d, %d, %d | %d, %d, %d, %d | %d, %d}\n", + dbg->num_mu_vht_pkt[10], dbg->num_mu_vht_pkt[11], + dbg->num_mu_vht_pkt[12], dbg->num_mu_vht_pkt[13], + dbg->num_mu_vht_pkt[14], dbg->num_mu_vht_pkt[15], + dbg->num_mu_vht_pkt[16], dbg->num_mu_vht_pkt[17], + dbg->num_mu_vht_pkt[18], dbg->num_mu_vht_pkt[19]); + } + #endif +#endif + *_used = used; + *_out_len = out_len; +#endif +} + +void phydm_per_tone_evm(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i, j; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[4] = {0}; + u32 val, tone_num, round; + s8 rxevm_0, rxevm_1; + s32 avg_num, evm_tone_0[256] = {0}, evm_tone_1[256] = {0}; + s32 rxevm_sum_0, rxevm_sum_1; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + pr_debug("n series not support yet !\n"); + return; + } + + for (i = 0; i < 4; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + avg_num = var1[0]; + round = var1[1]; + + if (!dm->is_linked) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "No Link !!\n"); + + *_used = used; + *_out_len = out_len; + + return; + } + + pr_debug("ID=((%d)), BW=((%d)), fc=((CH-%d))\n", dm->curr_station_id, + 20 << *dm->band_width, *dm->channel); + pr_debug("avg_num =((%d)), round =((%d))\n", avg_num, round); +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + watchdog_stop(dm->priv); +#endif + for (j = 0; j < round; j++) { + pr_debug("\nround((%d))\n", (j + 1)); + if (*dm->band_width == CHANNEL_WIDTH_20) { + for (tone_num = 228; tone_num <= 255; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n", + (256 - tone_num), evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + + for (tone_num = 1; tone_num <= 28; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n", + tone_num, evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + } else if (*dm->band_width == CHANNEL_WIDTH_40) { + for (tone_num = 198; tone_num <= 254; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n", + (256 - tone_num), evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + + for (tone_num = 2; tone_num <= 58; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(%-3d) RXEVM(1ss/2ss)=%d, %d\n", + tone_num, evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + } else if (*dm->band_width == CHANNEL_WIDTH_80) { + for (tone_num = 134; tone_num <= 254; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(-%-3d) RXEVM(1ss/2ss)=%d, %d\n", + (256 - tone_num), evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + + for (tone_num = 2; tone_num <= 122; tone_num++) { + odm_set_bb_reg(dm, R_0x8c4, 0xff8, tone_num); + rxevm_sum_0 = 0; + rxevm_sum_1 = 0; + for (i = 0; i < avg_num; i++) { + val = odm_read_4byte(dm, R_0xf8c); + + rxevm_0 = (s8)((val & MASKBYTE2) >> 16); + rxevm_0 = (rxevm_0 / 2); + if (rxevm_0 < -63) + rxevm_0 = 0; + + rxevm_1 = (s8)((val & MASKBYTE3) >> 24); + rxevm_1 = (rxevm_1 / 2); + if (rxevm_1 < -63) + rxevm_1 = 0; + rxevm_sum_0 += rxevm_0; + rxevm_sum_1 += rxevm_1; + ODM_delay_ms(1); + } + evm_tone_0[tone_num] = (rxevm_sum_0 / avg_num); + evm_tone_1[tone_num] = (rxevm_sum_1 / avg_num); + pr_debug("Tone(%-3d) RXEVM (1ss/2ss)=%d, %d\n", + tone_num, evm_tone_0[tone_num], + evm_tone_1[tone_num]); + } + } + } + *_used = used; + *_out_len = out_len; +} + +void phydm_bw_ch_adjust(void *dm_void, char input[][16], + u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + boolean is_enable_dbg_mode; + u8 central_ch, primary_ch_idx; + enum channel_width bw; + +#ifdef PHYDM_COMMON_API_SUPPORT + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{en} {CH} {pr_ch_idx 1/2/3/4/9/10} {0:20M,1:40M,2:80M}\n"); + goto out; + } + + if (!(dm->support_ic_type & CMN_API_SUPPORT_IC)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Not support this API\n"); + goto out; + } + + for (i = 0; i < 4; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + is_enable_dbg_mode = (boolean)var1[0]; + central_ch = (u8)var1[1]; + primary_ch_idx = (u8)var1[2]; + bw = (enum channel_width)var1[3]; + + if (is_enable_dbg_mode) { + dm->is_disable_phy_api = false; + phydm_api_switch_bw_channel(dm, central_ch, primary_ch_idx, bw); + dm->is_disable_phy_api = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "central_ch = %d, primary_ch_idx = %d, bw = %d\n", + central_ch, primary_ch_idx, bw); + } +out: +#endif + + *_used = used; + *_out_len = out_len; +} + +void phydm_ext_rf_element_ctrl(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val[10] = {0}; + u8 i = 0, input_idx = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &val[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + if (val[0] == 1) /*@ext switch*/ { + phydm_set_ext_switch(dm, val[1]); + } +} + +void phydm_print_dbgport(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dbg_port_value = 0; + u8 val[32]; + u8 tmp = 0; + u8 i; + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{dbg_port_idx}\n"); + goto out; + } + + PHYDM_SSCANF(input[1], DCMD_HEX, &var1[0]); + + dm->debug_components |= ODM_COMP_API; + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, var1[0])) { + dbg_port_value = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + + for (i = 0; i < 32; i++) + val[i] = (u8)((dbg_port_value & BIT(i)) >> i); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dbg Port[0x%x] = ((0x%x))\n", var1[0], + dbg_port_value); + + for (i = 4; i != 0; i--) { + tmp = 8 * (i - 1); + PDM_SNPF(out_len, used, output + used, out_len - used, + "val[%d:%d] = 8b'%d %d %d %d %d %d %d %d\n", + tmp + 7, tmp, val[tmp + 7], val[tmp + 6], + val[tmp + 5], val[tmp + 4], val[tmp + 3], + val[tmp + 2], val[tmp + 1], val[tmp + 0]); + } + } + dm->debug_components &= (~ODM_COMP_API); +out: + *_used = used; + *_out_len = out_len; +} + +void phydm_get_anapar_table(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + enum rf_path i = RF_PATH_A; + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "------ Analog parameters start ------\n"); + + for (i = RF_PATH_A; i < (enum rf_path)dm->num_rf_path; i++) + phydm_get_per_path_anapar_jgr3(dm, i, &used, output, &out_len); +#endif + + *_used = used; + *_out_len = out_len; +} + +void phydm_get_csi_table(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + PDM_VAST_SNPF(out_len, used, output + used, out_len - used, + "------ CSI Table Parsing start ------\n"); + + phydm_get_csi_table_jgr3(dm, &used, output, &out_len); +#endif + + *_used = used; + *_out_len = out_len; +} + +void phydm_dd_dbg_dump(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "dump: {1}\n"); + return; + } else if (var1[0] == 1) { + /*[Reg]*/ + phydm_dump_mac_reg(dm, &used, output, &out_len); + phydm_dump_bb_reg(dm, &used, output, &out_len); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->ic_ip_series == PHYDM_IC_JGR3) + phydm_dump_bb_reg2_jgr3(dm, &used, output, &out_len); + #endif + + phydm_dump_rf_reg(dm, &used, output, &out_len); + /*[Dbg Port]*/ + #ifdef PHYDM_AUTO_DEGBUG + phydm_dbg_port_dump(dm, &used, output, &out_len); + #endif + /*[Analog Parameters]*/ + phydm_get_anapar_table(dm, &used, output, &out_len); + } +} + +void phydm_nss_hitogram_mp(void *dm_void, enum PDM_RATE_TYPE rate_type, + u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + u32 used = *_used; + u32 out_len = *_out_len; + char buf[PHYDM_SNPRINT_SIZE] = {0}; + u16 buf_size = PHYDM_SNPRINT_SIZE; + u16 h_size = PHY_HIST_SIZE; + u16 *evm_hist = &dbg_s->evm_1ss_hist[0]; + u16 *snr_hist = &dbg_s->snr_1ss_hist[0]; + u8 i = 0; + u8 ss = phydm_rate_type_2_num_ss(dm, rate_type); + + if (rate_type == PDM_OFDM) { + phydm_print_hist_2_buf(dm, dbg_s->evm_ofdm_hist, PHY_HIST_SIZE, + buf, buf_size); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-14s=%s\n", "[OFDM][EVM]", buf); + + phydm_print_hist_2_buf(dm, dbg_s->snr_ofdm_hist, PHY_HIST_SIZE, + buf, buf_size); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-14s=%s\n", "[OFDM][SNR]", buf); + + *_used = used; + *_out_len = out_len; + return; + } + + for (i = 0; i < ss; i++) { + if (rate_type == PDM_1SS) { + evm_hist = &dbg_s->evm_1ss_hist[0]; + snr_hist = &dbg_s->snr_1ss_hist[0]; + } else if (rate_type == PDM_2SS) { + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + evm_hist = &dbg_s->evm_2ss_hist[i][0]; + snr_hist = &dbg_s->snr_2ss_hist[i][0]; + #endif + } else if (rate_type == PDM_3SS) { + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + evm_hist = &dbg_s->evm_3ss_hist[i][0]; + snr_hist = &dbg_s->snr_3ss_hist[i][0]; + #endif + } else if (rate_type == PDM_4SS) { + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + evm_hist = &dbg_s->evm_4ss_hist[i][0]; + snr_hist = &dbg_s->snr_4ss_hist[i][0]; + #endif + } + + phydm_print_hist_2_buf(dm, evm_hist, h_size, buf, buf_size); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[%d-SS][EVM][%d]=%s\n", ss, i, buf); + phydm_print_hist_2_buf(dm, snr_hist, h_size, buf, buf_size); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[%d-SS][SNR][%d]=%s\n", ss, i, buf); + } + *_used = used; + *_out_len = out_len; +} + +void phydm_mp_dbg(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + struct phydm_phystatus_avg *dbg_avg = &dbg_i->phystatus_statistic_avg; + char *rate_type = NULL; + u8 tmp_rssi_avg[4]; + u8 tmp_snr_avg[4]; + u8 tmp_evm_avg[4]; + u32 tmp_cnt = 0; + char buf[PHYDM_SNPRINT_SIZE] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[10] = {0}; + u16 buf_size = PHYDM_SNPRINT_SIZE; + u16 th_size = PHY_HIST_SIZE - 1; + u8 i = 0; + + if (!(*dm->mp_mode)) + return; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "BW=((%d)), fc=((CH-%d))\n", + 20 << *dm->band_width, *dm->channel); + + /*@===[PHY Histogram]================================================*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "[PHY Histogram] ==============>\n"); + /*@===[Threshold]===*/ + phydm_print_hist_2_buf(dm, dbg_i->evm_hist_th, th_size, buf, buf_size); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-16s=%s\n", "[EVM_TH]", buf); + phydm_print_hist_2_buf(dm, dbg_i->snr_hist_th, th_size, buf, buf_size); + PDM_SNPF(out_len, used, output + used, out_len - used, + "%-16s=%s\n", "[SNR_TH]", buf); + /*@===[OFDM]===*/ + phydm_nss_hitogram_mp(dm, PDM_OFDM, &used, output, &out_len); + /*@===[1-SS]===*/ + phydm_nss_hitogram_mp(dm, PDM_1SS, &used, output, &out_len); + /*@===[2-SS]===*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) + phydm_nss_hitogram_mp(dm, PDM_2SS, &used, output, &out_len); + #endif + /*@===[3-SS]===*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) + phydm_nss_hitogram_mp(dm, PDM_3SS, &used, output, &out_len); + #endif + /*@===[4-SS]===*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) + phydm_nss_hitogram_mp(dm, PDM_4SS, &used, output, &out_len); + #endif + /*@===[PHY Avg]======================================================*/ + phydm_get_avg_phystatus_val(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[PHY Avg] ==============>\n"); + + phydm_get_avg_phystatus_val(dm); + + switch (dm->num_rf_path) { +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1], + dbg_avg->rssi_beacon_avg[2], + dbg_avg->rssi_beacon_avg[3]); + break; +#endif +#if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1], + dbg_avg->rssi_beacon_avg[2]); + break; +#endif +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0], + dbg_avg->rssi_beacon_avg[1]); + break; +#endif + default: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n", + "[Beacon]", dbg_s->rssi_beacon_cnt, + dbg_avg->rssi_beacon_avg[0]); + break; + } + + switch (dm->num_rf_path) { +#ifdef PHYSTS_3RD_TYPE_SUPPORT + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, + dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0], + dbg_avg->rssi_cck_avg_abv_2ss[1], + dbg_avg->rssi_cck_avg_abv_2ss[2]); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, + dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0], + dbg_avg->rssi_cck_avg_abv_2ss[1]); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, + dbg_avg->rssi_cck_avg, + dbg_avg->rssi_cck_avg_abv_2ss[0]); + break; + #endif +#endif + default: + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d}\n", + "[CCK]", dbg_s->rssi_cck_cnt, dbg_avg->rssi_cck_avg); + break; + } + + for (i = 0; i <= 4; i++) { + if (i > dm->num_rf_path) + break; + + odm_memory_set(dm, tmp_rssi_avg, 0, 4); + odm_memory_set(dm, tmp_snr_avg, 0, 4); + odm_memory_set(dm, tmp_evm_avg, 0, 4); + + switch (i) { + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case 4: + rate_type = "[4-SS]"; + tmp_cnt = dbg_s->rssi_4ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, + dbg_avg->rssi_4ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, + dbg_avg->snr_4ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, dbg_avg->evm_4ss_avg, + 4); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case 3: + rate_type = "[3-SS]"; + tmp_cnt = dbg_s->rssi_3ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, + dbg_avg->rssi_3ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, + dbg_avg->snr_3ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, + dbg_avg->evm_3ss_avg, 3); + break; + #endif + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case 2: + rate_type = "[2-SS]"; + tmp_cnt = dbg_s->rssi_2ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, + dbg_avg->rssi_2ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, dbg_avg->snr_2ss_avg, + dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, + dbg_avg->evm_2ss_avg, 2); + break; + #endif + case 1: + rate_type = "[1-SS]"; + tmp_cnt = dbg_s->rssi_1ss_cnt; + odm_move_memory(dm, tmp_rssi_avg, + dbg_avg->rssi_1ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, + dbg_avg->snr_1ss_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, + &dbg_avg->evm_1ss_avg, 1); + break; + default: + rate_type = "[L-OFDM]"; + tmp_cnt = dbg_s->rssi_ofdm_cnt; + odm_move_memory(dm, tmp_rssi_avg, + dbg_avg->rssi_ofdm_avg, + dm->num_rf_path); + odm_move_memory(dm, tmp_snr_avg, + dbg_avg->snr_ofdm_avg, dm->num_rf_path); + odm_move_memory(dm, tmp_evm_avg, + &dbg_avg->evm_ofdm_avg, 1); + break; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "* %-8s Cnt=((%.3d)) RSSI:{%.2d, %.2d, %.2d, %.2d} SNR:{%.2d, %.2d, %.2d, %.2d} EVM:{-%.2d, -%.2d, -%.2d, -%.2d}\n", + rate_type, tmp_cnt, + tmp_rssi_avg[0], tmp_rssi_avg[1], + tmp_rssi_avg[2], tmp_rssi_avg[3], + tmp_snr_avg[0], tmp_snr_avg[1], + tmp_snr_avg[2], tmp_snr_avg[3], + tmp_evm_avg[0], tmp_evm_avg[1], + tmp_evm_avg[2], tmp_evm_avg[3]); + } + + phydm_reset_phystatus_statistic(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "rxsc_idx {Legacy, 20, 40, 80} = {%d, %d, %d, %d}\n", + dm->rxsc_l, dm->rxsc_20, dm->rxsc_40, dm->rxsc_80); + + *_used = used; + *_out_len = out_len; +} + +void phydm_reg_monitor(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + boolean en_mntr = false; + u8 i = 0; + + for (i = 0; i < 7; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "reg_mntr {en} {0:all, 1:BB, 2:RF, 3:MAC 4:1/2/4 byte}\n"); + } else { + if (var1[0] == 1) + en_mntr = true; + else + en_mntr = false; + + if (var1[1] == 0) { + dm->en_reg_mntr_bb = en_mntr; + dm->en_reg_mntr_rf = en_mntr; + dm->en_reg_mntr_mac = en_mntr; + dm->en_reg_mntr_byte = en_mntr; + } else if (var1[1] == 1) { + dm->en_reg_mntr_bb = en_mntr; + } else if (var1[1] == 2) { + dm->en_reg_mntr_rf = en_mntr; + } else if (var1[1] == 3) { + dm->en_reg_mntr_mac = en_mntr; + } else if (var1[1] == 4) { + dm->en_reg_mntr_byte = en_mntr; + } + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "en: BB:%d, RF:%d, MAC:%d, byte:%d\n", dm->en_reg_mntr_bb, + dm->en_reg_mntr_rf, dm->en_reg_mntr_mac, dm->en_reg_mntr_byte); + + *_used = used; + *_out_len = out_len; +} + +#if (RTL8822C_SUPPORT) +u16 phydm_get_agc_rf_gain(void *dm_void, boolean is_mod, u8 tab, u8 mp_gain_i) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 rf_gain = 0x0; + + if (is_mod) + rf_gain = dm->agc_rf_gain[tab][mp_gain_i]; + else + rf_gain = dm->agc_rf_gain_ori[tab][mp_gain_i]; + + return rf_gain; +} +#endif + +void phydm_get_rxagc_table_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 tab = 0; + boolean is_modified = false; + u8 mp_gain = 0; + u16 rf_gain = 0; + u8 i = 0; + +#if (RTL8822C_SUPPORT) + if (!(dm->support_ic_type & ODM_RTL8822C)) + return; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "get rxagc table : {0:ori, 1:modified} {table:0~15} {mp_gain_idx:0~63, all:0xff}\n"); + } else { + for (i = 0; i < 3; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + + is_modified = (boolean)var1[0]; + tab = (u8)var1[1]; + mp_gain = (u8)var1[2]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "agc_table_cnt:%d, is_agc_tab_pos_shift:%d, agc_table_shift:%d\n", + dm->agc_table_cnt, dm->is_agc_tab_pos_shift, + dm->agc_table_shift); + + if (mp_gain == 0xff) { + for (i = 0; i < 64; i++) { + rf_gain = phydm_get_agc_rf_gain(dm, is_modified, + tab, i); + + PDM_SNPF(out_len, used, output + used, + out_len - used, + "agc_table:%d, mp_gain_idx:0x%x, rf_gain_idx:0x%x\n", + tab, i, rf_gain); + } + } else { + rf_gain = phydm_get_agc_rf_gain(dm, is_modified, tab, + mp_gain); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "agc_table:%d, mp_gain_idx:0x%x, rf_gain_idx:0x%x\n", + tab, mp_gain, rf_gain); + } + } +#endif + *_used = used; + *_out_len = out_len; +} + +void phydm_shift_rxagc_table_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u16 value_db = 0; + +#if (RTL8822C_SUPPORT) + if (!(dm->support_ic_type & ODM_RTL8822C)) + return; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "shift rxagc table : {0:-, 1:+} {value(0~63, unit:2dB)}\n"); + } else { + for (i = 0; i < 3; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + + if ((u8)var1[1] > 63) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Do not enter the value larger than 63!\n"); + } else { + phydm_shift_rxagc_table(dm, (boolean)var1[0], + (u8)var1[1]); + + value_db = (u8)var1[1] << 1; + PDM_SNPF(out_len, used, output + used, out_len - used, + "shift %s%d dB gain\n", + (((boolean)var1[0]) ? "+" : "-"), value_db); + } + } +#endif +} + +#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT) +void phydm_spur_detect_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0: Auto spur detect(NBI+CSI), 1:NBI always ON/ CSI Auto,"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "2: CSI always On/ NBI Auto, 3: Disable, 4: CSI & NBI ON}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{If CSI always ON (Mode 2 or 4) -> CSI wgt manual(0~7)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{5: Adjust CSI weight threshold} {0:-,1:+} {th offset}\n"); + } else { + for (i = 0; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + + if (var1[0] == 1) { + dm->dsde_sel = DET_NBI; + } else if (var1[0] == 2) { + dm->dsde_sel = DET_CSI; + } else if (var1[0] == 3) { + dm->dsde_sel = DET_DISABLE; + } else if (var1[0] == 4) { + dm->dsde_sel = DET_CSI_NBI_EN; + } else if (var1[0] == 0) { + dm->dsde_sel = DET_AUTO; + } else if (var1[0] == 5) { + if (var1[1] == 0) + for (i = 0; i < 5; i++) + dm->csi_wgt_th_db[i] -= (u8)var1[2]; + else if (var1[1] == 1) + for (i = 0; i < 5; i++) + dm->csi_wgt_th_db[i] += (u8)var1[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, "current csi weight threshold:\n"); + for (i = 0; i < 5; i++) + PDM_SNPF(out_len, used, output + used, + out_len - used, "----%2d", + dm->csi_wgt_th_db[i]); + PDM_SNPF(out_len, used, output + used, out_len - used, "\n"); + for (i = 0; i < 5; i++) + PDM_SNPF(out_len, used, output + used, + out_len - used, "--%d--|", i); + PDM_SNPF(out_len, used, output + used, out_len - used, "\n"); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Spur detection mode invalid!\n"); + return; + } + if (var1[0] < 5) + PDM_SNPF(out_len, used, output + used, out_len - used, + "spur detect mode = %d\n", dm->dsde_sel); + + if (dm->dsde_sel == DET_CSI_NBI_EN) { + if (var1[1] < 8) { + dm->csi_wgt = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, + out_len - used, "CSI wgt %d\n", + dm->csi_wgt); + } else { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "CSI wgt setting invalid. Please set the correct wgt!\n"); + return; + } + } + } + + *_used = used; + *_out_len = out_len; +} +#endif + +struct phydm_command { + char name[16]; + u8 id; +}; + +enum PHYDM_CMD_ID { + PHYDM_HELP, + PHYDM_DEMO, + PHYDM_RF_CMD, + PHYDM_DIG, + PHYDM_RA, + PHYDM_PROFILE, + PHYDM_ANTDIV, + PHYDM_PATHDIV, + PHYDM_DEBUG, + PHYDM_MP_DEBUG, + PHYDM_FW_DEBUG, + PHYDM_SUPPORT_ABILITY, + PHYDM_GET_TXAGC, + PHYDM_SET_TXAGC, + PHYDM_SMART_ANT, + PHYDM_CH_BW, + PHYDM_TRX_PATH, + PHYDM_LA_MODE, + PHYDM_DUMP_REG, + PHYDM_AUTO_DBG, + PHYDM_DD_DBG, + PHYDM_BIG_JUMP, + PHYDM_SHOW_RXRATE, + PHYDM_NBI_EN, + PHYDM_CSI_MASK_EN, + PHYDM_DFS_DEBUG, + PHYDM_DFS_HIST, + PHYDM_NHM, + PHYDM_CLM, + PHYDM_FAHM, + PHYDM_ENV_MNTR, + PHYDM_BB_INFO, + //PHYDM_TXBF, + PHYDM_H2C, + PHYDM_EXT_RF_E_CTRL, + PHYDM_ADAPTIVE_SOML, + PHYDM_PSD, + PHYDM_DEBUG_PORT, + PHYDM_DIS_HTSTF_CONTROL, + PHYDM_CFO_TRK, + PHYDM_ADAPTIVITY_DEBUG, + PHYDM_DIS_DYM_ANT_WEIGHTING, + PHYDM_FORECE_PT_STATE, + PHYDM_STA_INFO, + PHYDM_PAUSE_FUNC, + PHYDM_PER_TONE_EVM, + PHYDM_DYN_TXPWR, + PHYDM_LNA_SAT, + PHYDM_ANAPAR, + PHYDM_CCK_RX_PATHDIV, + PHYDM_BEAM_FORMING, + PHYDM_REG_MONITOR, +#if RTL8814B_SUPPORT + PHYDM_SPUR_DETECT, +#endif + PHYDM_PHY_STATUS, + PHYDM_CRC32_CNT, + PHYDM_DCC, +#ifdef PHYDM_HW_IGI + PHYDM_HWIGI, +#endif +#ifdef PHYDM_HW_SWITCH_AGC_TAB + PHYDM_HW_AGCTAB, +#endif + PHYDM_PMAC_TX, + PHYDM_GET_RXAGC, + PHYDM_SHIFT_RXAGC, + PHYDM_IFS_CLM, + PHYDM_ENHANCE_MNTR, + PHYDM_CSI_DBG +}; + +struct phydm_command phy_dm_ary[] = { + {"-h", PHYDM_HELP}, /*@do not move this element to other position*/ + {"demo", PHYDM_DEMO}, /*@do not move this element to other position*/ + {"rf", PHYDM_RF_CMD}, + {"dig", PHYDM_DIG}, + {"ra", PHYDM_RA}, + {"profile", PHYDM_PROFILE}, + {"antdiv", PHYDM_ANTDIV}, + {"pathdiv", PHYDM_PATHDIV}, + {"dbg", PHYDM_DEBUG}, + {"mp_dbg", PHYDM_MP_DEBUG}, + {"fw_dbg", PHYDM_FW_DEBUG}, + {"ability", PHYDM_SUPPORT_ABILITY}, + {"get_txagc", PHYDM_GET_TXAGC}, + {"set_txagc", PHYDM_SET_TXAGC}, + {"smtant", PHYDM_SMART_ANT}, + {"ch_bw", PHYDM_CH_BW}, + {"trxpath", PHYDM_TRX_PATH}, + {"lamode", PHYDM_LA_MODE}, + {"dumpreg", PHYDM_DUMP_REG}, + {"auto_dbg", PHYDM_AUTO_DBG}, + {"dd_dbg", PHYDM_DD_DBG}, + {"bigjump", PHYDM_BIG_JUMP}, + {"rxrate", PHYDM_SHOW_RXRATE}, + {"nbi", PHYDM_NBI_EN}, + {"csi_mask", PHYDM_CSI_MASK_EN}, + {"dfs", PHYDM_DFS_DEBUG}, + {"dfs_hist", PHYDM_DFS_HIST}, + {"nhm", PHYDM_NHM}, + {"clm", PHYDM_CLM}, + {"fahm", PHYDM_FAHM}, + {"env_mntr", PHYDM_ENV_MNTR}, + {"bbinfo", PHYDM_BB_INFO}, + /*{"txbf", PHYDM_TXBF},*/ + {"h2c", PHYDM_H2C}, + {"ext_rfe", PHYDM_EXT_RF_E_CTRL}, + {"soml", PHYDM_ADAPTIVE_SOML}, + {"psd", PHYDM_PSD}, + {"dbgport", PHYDM_DEBUG_PORT}, + {"dis_htstf", PHYDM_DIS_HTSTF_CONTROL}, + {"cfo_trk", PHYDM_CFO_TRK}, + {"adapt_debug", PHYDM_ADAPTIVITY_DEBUG}, + {"dis_dym_ant_wgt", PHYDM_DIS_DYM_ANT_WEIGHTING}, + {"force_pt_state", PHYDM_FORECE_PT_STATE}, + {"sta_info", PHYDM_STA_INFO}, + {"pause", PHYDM_PAUSE_FUNC}, + {"evm", PHYDM_PER_TONE_EVM}, + {"dyn_txpwr", PHYDM_DYN_TXPWR}, + {"lna_sat", PHYDM_LNA_SAT}, + {"anapar", PHYDM_ANAPAR}, + {"cck_rx_pathdiv", PHYDM_CCK_RX_PATHDIV}, + {"bf", PHYDM_BEAM_FORMING}, + {"reg_mntr", PHYDM_REG_MONITOR}, +#if RTL8814B_SUPPORT + {"spur_detect", PHYDM_SPUR_DETECT}, +#endif + {"physts", PHYDM_PHY_STATUS}, + {"crc32_cnt", PHYDM_CRC32_CNT}, +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT + {"pmac_tx", PHYDM_PMAC_TX}, +#endif +#ifdef PHYDM_HW_IGI + {"hwigi", PHYDM_HWIGI}, +#endif +#ifdef PHYDM_HW_SWITCH_AGC_TAB + {"hw_agctab", PHYDM_HW_AGCTAB}, +#endif + {"dcc", PHYDM_DCC}, + {"get_rxagc", PHYDM_GET_RXAGC}, + {"shift_rxagc", PHYDM_SHIFT_RXAGC}, + {"ifs_clm", PHYDM_IFS_CLM}, + {"enh_mntr", PHYDM_ENHANCE_MNTR}, + {"csi_dbg", PHYDM_CSI_DBG} + }; + +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ + +void phydm_cmd_parser(struct dm_struct *dm, char input[][MAX_ARGV], + u32 input_num, u8 flag, char *output, u32 out_len) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + u32 used = 0; + u8 id = 0; + u32 var1[10] = {0}; + u32 i; + u32 phydm_ary_size = sizeof(phy_dm_ary) / sizeof(struct phydm_command); + + if (flag == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "GET, nothing to print\n"); + return; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, "\n"); + + /* Parsing Cmd ID */ + if (input_num) { + for (i = 0; i < phydm_ary_size; i++) { + if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { + id = phy_dm_ary[i].id; + break; + } + } + if (i == phydm_ary_size) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "PHYDM command not found!\n"); + return; + } + } + + switch (id) { + case PHYDM_HELP: { + PDM_SNPF(out_len, used, output + used, out_len - used, + "BB cmd ==>\n"); + + for (i = 0; i < phydm_ary_size - 2; i++) + PDM_SNPF(out_len, used, output + used, out_len - used, + " %-5d: %s\n", i, phy_dm_ary[i + 2].name); + } break; + + case PHYDM_DEMO: { /*@echo demo 10 0x3a z abcde >cmd*/ + u32 directory = 0; + + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) + char char_temp; + #else + u32 char_temp = ' '; + #endif + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Decimal value = %d\n", directory); + PHYDM_SSCANF(input[2], DCMD_HEX, &directory); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Hex value = 0x%x\n", directory); + PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Char = %c\n", char_temp); + PDM_SNPF(out_len, used, output + used, out_len - used, + "String = %s\n", input[4]); + } break; + case PHYDM_RF_CMD: + halrf_cmd_parser(dm, input, &used, output, &out_len, input_num); + break; + + case PHYDM_DIG: + phydm_dig_debug(dm, input, &used, output, &out_len); + break; + + case PHYDM_RA: + phydm_ra_debug(dm, input, &used, output, &out_len); + break; + + case PHYDM_ANTDIV: + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + phydm_antdiv_debug(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_PATHDIV: + #if (defined(CONFIG_PATH_DIVERSITY)) + phydm_pathdiv_debug(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_DEBUG: + phydm_debug_trace(dm, input, &used, output, &out_len); + break; + + case PHYDM_MP_DEBUG: + phydm_mp_dbg(dm, input, &used, output, &out_len); + break; + + case PHYDM_FW_DEBUG: + phydm_fw_debug_trace(dm, input, &used, output, &out_len); + break; + + case PHYDM_SUPPORT_ABILITY: + phydm_supportability_en(dm, input, &used, output, &out_len); + break; + + case PHYDM_SMART_ANT: + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + phydm_hl_smt_ant_dbg_type2(dm, input, &used, output, &out_len); + #elif (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + phydm_hl_smart_ant_debug(dm, input, &used, output, &out_len); + #endif + + #elif (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + phydm_cumitek_smt_ant_debug(dm, input, &used, output, &out_len); + #endif + + break; + + case PHYDM_CH_BW: + phydm_bw_ch_adjust(dm, input, &used, output, &out_len); + break; + + case PHYDM_PROFILE: + phydm_basic_profile(dm, &used, output, &out_len); + break; + + case PHYDM_GET_TXAGC: + phydm_get_txagc(dm, &used, output, &out_len); + break; + + case PHYDM_SET_TXAGC: + phydm_set_txagc_dbg(dm, input, &used, output, &out_len); + break; + + case PHYDM_TRX_PATH: + phydm_config_trx_path(dm, input, &used, output, &out_len); + break; + + case PHYDM_LA_MODE: + #if (PHYDM_LA_MODE_SUPPORT) + phydm_la_cmd(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_DUMP_REG: + phydm_dump_reg(dm, input, &used, output, &out_len); + break; + + case PHYDM_BIG_JUMP: + phydm_enable_big_jump(dm, input, &used, output, &out_len); + break; + + case PHYDM_AUTO_DBG: + #ifdef PHYDM_AUTO_DEGBUG + phydm_auto_dbg_console(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_DD_DBG: + phydm_dd_dbg_dump(dm, input, &used, output, &out_len); + break; + + case PHYDM_SHOW_RXRATE: + phydm_show_rx_rate(dm, input, &used, output, &out_len); + break; + + case PHYDM_NBI_EN: + phydm_nbi_debug(dm, input, &used, output, &out_len); + break; + + case PHYDM_CSI_MASK_EN: + phydm_csi_debug(dm, input, &used, output, &out_len); + break; + + #ifdef CONFIG_PHYDM_DFS_MASTER + case PHYDM_DFS_DEBUG: + phydm_dfs_debug(dm, input, &used, output, &out_len); + break; + + case PHYDM_DFS_HIST: + phydm_dfs_hist_dbg(dm, input, &used, output, &out_len); + break; + #endif + + case PHYDM_NHM: + #ifdef NHM_SUPPORT + phydm_nhm_dbg(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_CLM: + #ifdef CLM_SUPPORT + phydm_clm_dbg(dm, input, &used, output, &out_len); + #endif + break; + + #ifdef FAHM_SUPPORT + case PHYDM_FAHM: + phydm_fahm_dbg(dm, input, &used, output, &out_len); + break; + #endif + + case PHYDM_ENV_MNTR: + phydm_env_mntr_dbg(dm, input, &used, output, &out_len); + break; + + case PHYDM_BB_INFO: + phydm_bb_hw_dbg_info(dm, input, &used, output, &out_len); + break; + /* + case PHYDM_TXBF: { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #ifdef PHYDM_BEAMFORMING_SUPPORT + struct _RT_BEAMFORMING_INFO *beamforming_info = NULL; + + beamforming_info = &dm->beamforming_info; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + if (var1[0] == 0) { + beamforming_info->apply_v_matrix = false; + beamforming_info->snding3ss = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n dont apply V matrix and 3SS 789 snding\n"); + } else if (var1[0] == 1) { + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n apply V matrix and 3SS 789 snding\n"); + } else if (var1[0] == 2) { + beamforming_info->apply_v_matrix = true; + beamforming_info->snding3ss = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n default txbf setting\n"); + } else + PDM_SNPF(out_len, used, output + used, out_len - used, + "\r\n unknown cmd!!\n"); + #endif + #endif + } break; + */ + case PHYDM_H2C: + phydm_h2C_debug(dm, input, &used, output, &out_len); + break; + + case PHYDM_EXT_RF_E_CTRL: + phydm_ext_rf_element_ctrl(dm, input, &used, output, &out_len); + break; + + case PHYDM_ADAPTIVE_SOML: + #ifdef CONFIG_ADAPTIVE_SOML + phydm_soml_debug(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_PSD: + + #ifdef CONFIG_PSD_TOOL + phydm_psd_debug(dm, input, &used, output, &out_len); + #endif + + break; + + case PHYDM_DEBUG_PORT: + phydm_print_dbgport(dm, input, &used, output, &out_len); + break; + + case PHYDM_DIS_HTSTF_CONTROL: { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 1) { + /* setting being false is for debug */ + dm->bhtstfdisabled = true; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dynamic HT-STF Gain Control is Disable\n"); + } else { + /* @default setting should be true, + * always be dynamic control + */ + dm->bhtstfdisabled = false; + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dynamic HT-STF Gain Control is Enable\n"); + } + } break; + + case PHYDM_CFO_TRK: + phydm_cfo_tracking_debug(dm, input, &used, output, &out_len); + break; + + case PHYDM_ADAPTIVITY_DEBUG: + #ifdef PHYDM_SUPPORT_ADAPTIVITY + phydm_adaptivity_debug(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_DIS_DYM_ANT_WEIGHTING: + #ifdef DYN_ANT_WEIGHTING_SUPPORT + phydm_ant_weight_dbg(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_FORECE_PT_STATE: + #ifdef PHYDM_POWER_TRAINING_SUPPORT + phydm_pow_train_debug(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_STA_INFO: + phydm_show_sta_info(dm, input, &used, output, &out_len); + break; + + case PHYDM_PAUSE_FUNC: + phydm_pause_func_console(dm, input, &used, output, &out_len); + break; + + case PHYDM_PER_TONE_EVM: + phydm_per_tone_evm(dm, input, &used, output, &out_len); + break; + + #ifdef CONFIG_DYNAMIC_TX_TWR + case PHYDM_DYN_TXPWR: + phydm_dtp_debug(dm, input, &used, output, &out_len); + break; + #endif + + case PHYDM_LNA_SAT: + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + phydm_lna_sat_debug(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_ANAPAR: + phydm_get_anapar_table(dm, &used, output, &out_len); + break; + case PHYDM_CCK_RX_PATHDIV: + #ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT + phydm_cck_rx_pathdiv_dbg(dm, input, &used, output, &out_len); + #endif + break; + + case PHYDM_BEAM_FORMING: + #ifdef CONFIG_BB_TXBF_API + phydm_bf_debug(dm, input, &used, output, &out_len); + #endif + break; + case PHYDM_REG_MONITOR: + phydm_reg_monitor(dm, input, &used, output, &out_len); + break; + +#if RTL8814B_SUPPORT + case PHYDM_SPUR_DETECT: + phydm_spur_detect_dbg(dm, input, &used, output, &out_len); + break; +#endif + case PHYDM_CRC32_CNT: + phydm_crc32_cnt_dbg(dm, input, &used, output, &out_len); + break; + case PHYDM_PHY_STATUS: + phydm_physts_dbg(dm, input, &used, output, &out_len); + break; +#ifdef PHYDM_DCC_ENHANCE + case PHYDM_DCC: + phydm_dig_cckpd_coex_dbg(dm, input, &used, output, &out_len); + break; +#endif +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT + case PHYDM_PMAC_TX: + phydm_pmac_tx_dbg(dm, input, &used, output, &out_len); + break; +#endif +#ifdef PHYDM_HW_IGI + case PHYDM_HWIGI: + phydm_hwigi_dbg(dm, input, &used, output, &out_len); + break; +#endif +#ifdef PHYDM_HW_SWITCH_AGC_TAB + case PHYDM_HW_AGCTAB: + phydm_auto_agc_tab_debug(dm, input, &used, output, &out_len); + break; +#endif + case PHYDM_GET_RXAGC: + phydm_get_rxagc_table_dbg(dm, input, &used, output, &out_len); + break; + case PHYDM_SHIFT_RXAGC: + phydm_shift_rxagc_table_dbg(dm, input, &used, output, &out_len); + break; + case PHYDM_IFS_CLM: + #ifdef IFS_CLM_SUPPORT + phydm_ifs_clm_dbg(dm, input, &used, output, &out_len); + #endif + break; + case PHYDM_ENHANCE_MNTR: + phydm_enhance_mntr_dbg(dm, input, &used, output, &out_len); + break; + case PHYDM_CSI_DBG: + phydm_get_csi_table(dm, &used, output, &out_len); + break; + default: + PDM_SNPF(out_len, used, output + used, out_len - used, + "Do not support this command\n"); + break; + } +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ +} + +#if defined __ECOS || defined __ICCARM__ +#ifndef strsep +char *strsep(char **s, const char *ct) +{ + char *sbegin = *s; + char *end; + + if (!sbegin) + return NULL; + + end = strpbrk(sbegin, ct); + if (end) + *end++ = '\0'; + *s = end; + return sbegin; +} +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP | ODM_IOT)) +s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag, + char *output, u32 out_len) +{ + char *token; + u32 argc = 0; + char argv[MAX_ARGC][MAX_ARGV]; + + do { + token = strsep(&input, ", "); + if (token) { + if (strlen(token) <= MAX_ARGV) + strcpy(argv[argc], token); + + argc++; + } else { + break; + } + } while (argc < MAX_ARGC); + + if (argc == 1) + argv[0][strlen(argv[0]) - 1] = '\0'; + + phydm_cmd_parser(dm, argv, argc, flag, output, out_len); + + return 0; +} +#endif + +void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@u8 debug_trace_11byte[60];*/ + u8 freg_num, c2h_seq, buf_0 = 0; + + if (!(dm->support_ic_type & PHYDM_IC_3081_SERIES)) + return; + + if (cmd_len > 12 || cmd_len == 0) { + pr_debug("[Warning] Error C2H cmd_len=%d\n", cmd_len); + return; + } + + buf_0 = cmd_buf[0]; + freg_num = (buf_0 & 0xf); + c2h_seq = (buf_0 & 0xf0) >> 4; + + #if 0 + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW debug message] freg_num = (( %d )), c2h_seq=(( %d ))\n", + freg_num, c2h_seq); + + strncpy(debug_trace_11byte, &cmd_buf[1], (cmd_len - 1)); + debug_trace_11byte[cmd_len - 1] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] %s\n", + debug_trace_11byte); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] cmd_len = (( %d ))\n", + cmd_len); + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW debug message] c2h_cmd_start=((%d))\n", + dm->c2h_cmd_start); + + PHYDM_DBG(dm, DBG_FW_TRACE, "pre_seq = (( %d )), current_seq=((%d))\n", + dm->pre_c2h_seq, c2h_seq); + PHYDM_DBG(dm, DBG_FW_TRACE, "fw_buff_is_enpty = (( %d ))\n", + dm->fw_buff_is_enpty); + #endif + + if (c2h_seq != dm->pre_c2h_seq && dm->fw_buff_is_enpty == false) { + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW Dbg Queue Overflow] %s\n", + dm->fw_debug_trace); + dm->c2h_cmd_start = 0; + } + + if ((cmd_len - 1) > (60 - dm->c2h_cmd_start)) { + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW Dbg Queue error: wrong C2H length] %s\n", + dm->fw_debug_trace); + dm->c2h_cmd_start = 0; + return; + } + + strncpy((char *)&dm->fw_debug_trace[dm->c2h_cmd_start], + (char *)&cmd_buf[1], (cmd_len - 1)); + dm->c2h_cmd_start += (cmd_len - 1); + dm->fw_buff_is_enpty = false; + + if (freg_num == 0 || dm->c2h_cmd_start >= 60) { + if (dm->c2h_cmd_start < 60) + dm->fw_debug_trace[dm->c2h_cmd_start] = '\0'; + else + dm->fw_debug_trace[59] = '\0'; + + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s\n", + dm->fw_debug_trace); + + dm->c2h_cmd_start = 0; + dm->fw_buff_is_enpty = true; + } + + dm->pre_c2h_seq = c2h_seq; +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ +} + +void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 function = buffer[0]; + u8 dbg_num = buffer[1]; + u16 content_0 = (((u16)buffer[3]) << 8) | ((u16)buffer[2]); + u16 content_1 = (((u16)buffer[5]) << 8) | ((u16)buffer[4]); + u16 content_2 = (((u16)buffer[7]) << 8) | ((u16)buffer[6]); + u16 content_3 = (((u16)buffer[9]) << 8) | ((u16)buffer[8]); + u16 content_4 = (((u16)buffer[11]) << 8) | ((u16)buffer[10]); + + if (cmd_len > 12) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW Msg] Invalid cmd length (( %d )) >12\n", + cmd_len); +/*@--------------------------------------------*/ +#ifdef CONFIG_RA_FW_DBG_CODE + if (function == RATE_DECISION) { + if (dbg_num == 0) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", + content_1, content_2); + else if (content_0 == 2) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 3) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", + content_1, content_2, content_3, + content_4); + } else if (dbg_num == 1) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RTY[0,1,2,3]=[ %d , %d , %d , %d ]\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 2) { + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RTY[4]=[ %d ], drop=(( %d )), total=(( %d )), current_rate=((0x %x ))", + content_1, content_2, content_3, + content_4); + phydm_print_rate(dm, (u8)content_4, + DBG_FW_TRACE); + } else if (content_0 == 3) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] penality_idx=(( %d ))\n", + content_1); + else if (content_0 == 4) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RSSI=(( %d )), ra_stage = (( %d ))\n", + content_1, content_2); + } else if (dbg_num == 3) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 2) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 3) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( UP )) ((rate Down Hold)) RA_CNT=((%d))\n", + content_1); + else if (content_0 == 4) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", + content_1); + else if (content_0 == 8) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", + content_1); + } else if (dbg_num == 4) { + if (content_0 == 3) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] RER_CNT PCR_ori =(( %d )), ratio_ori =(( %d )), pcr_updown_bitmap =(( 0x%x )), pcr_var_diff =(( %d ))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 4) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] pcr_shift_value =(( %s%d )), rate_down_threshold =(( %d )), rate_up_threshold =(( %d ))\n", + ((content_1) ? "+" : "-"), content_2, + content_3, content_4); + else if (content_0 == 5) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] pcr_mean =(( %d )), PCR_VAR =(( %d )), offset =(( %d )), decision_offset_p =(( %d ))\n", + content_1, content_2, content_3, + content_4); + } else if (dbg_num == 5) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] (( UP)) Nsc=(( %d )), N_High=(( %d )), RateUp_Waiting=(( %d )), RateUp_Fail=(( %d ))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 2) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((DOWN)) Nsc=(( %d )), N_Low=(( %d ))\n", + content_1, content_2); + else if (content_0 == 3) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", + content_1, content_2, content_3, + content_4); + } else if (dbg_num == 0x60) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", + content_1, content_2); + else if (content_0 == 4) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 5) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", + content_1, content_2, content_3, + content_4); + } + } else if (function == INIT_RA_TABLE) { + if (dbg_num == 3) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", + content_0); + } else if (function == RATE_UP) { + if (dbg_num == 2) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateUp] ((Highest rate->return)), macid=((%d)) Nsc=((%d))\n", + content_1, content_2); + } else if (dbg_num == 5) { + if (content_0 == 0) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateUp] ((rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", + content_1, content_2, content_3, + content_4); + else if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateUp] ((rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", + content_1, content_2, content_3, + content_4); + } + } else if (function == RATE_DOWN) { + if (dbg_num == 5) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][RateDownStep] ((rate Down)), macid=((%d)), rate1=((0x%x)), rate2=((0x%x)), BW=((%d))\n", + content_1, content_2, content_3, + content_4); + } + } else if (function == TRY_DONE) { + if (dbg_num == 1) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", + content_1, content_2); + } else if (dbg_num == 2) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][Try Done] ((try)) macid=((%d)), Try_Done_cnt=((%d)), rate_2=((%d)), try_succes=((%d))\n", + content_1, content_2, content_3, + content_4); + } + } else if (function == RA_H2C) { + if (dbg_num == 1) { + if (content_0 == 0) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][H2C=0x49] fw_trace_en=((%d)), mode =((%d)), macid=((%d))\n", + content_1, content_2, content_3); + } + } else if (function == F_RATE_AP_RPT) { + if (dbg_num == 1) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", + content_3); + } else if (dbg_num == 2) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] RTY_all=((%d))\n", + content_1); + } else if (dbg_num == 3) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", + content_3, content_1, content_2); + } else if (dbg_num == 4) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", + content_3, content_1, content_2); + } else if (dbg_num == 5) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", + content_3, content_1, content_2); + } else if (dbg_num == 6) { + if (content_0 == 1) + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", + content_3, content_1, content_2); + } + } else if (function == DBC_FW_CLM) { + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][CLM][%d, %d] = {%d, %d, %d, %d}\n", dbg_num, + content_0, content_1, content_2, content_3, + content_4); + } else { + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", + function, dbg_num, content_0, content_1, content_2, + content_3, content_4); + } +#else + PHYDM_DBG(dm, DBG_FW_TRACE, + "[FW][general][%d, %d, %d] = {%d, %d, %d, %d}\n", function, + dbg_num, content_0, content_1, content_2, content_3, + content_4); +#endif +/*@--------------------------------------------*/ + +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ +} + +void phydm_fw_trace_handler_8051(void *dm_void, u8 *buffer, u8 cmd_len) +{ +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION + struct dm_struct *dm = (struct dm_struct *)dm_void; + int i = 0; + u8 extend_c2h_sub_id = 0, extend_c2h_dbg_len = 0; + u8 extend_c2h_dbg_seq = 0; + u8 fw_debug_trace[128]; + u8 *extend_c2h_dbg_content = 0; + + if (cmd_len > 127) + return; + + extend_c2h_sub_id = buffer[0]; + extend_c2h_dbg_len = buffer[1]; + extend_c2h_dbg_content = buffer + 2; /*@DbgSeq+DbgContent for show HEX*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, extend_c2h_dbg_len=%d\n", + extend_c2h_sub_id, extend_c2h_dbg_len)); + + RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", extend_c2h_dbg_content, cmd_len - 2); +#endif + +go_backfor_aggre_dbg_pkt: + i = 0; + extend_c2h_dbg_seq = buffer[2]; + extend_c2h_dbg_content = buffer + 3; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", extend_c2h_dbg_seq)); +#endif + + for (;; i++) { + fw_debug_trace[i] = extend_c2h_dbg_content[i]; + if (extend_c2h_dbg_content[i + 1] == '\0') { + fw_debug_trace[i + 1] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s", + &fw_debug_trace[0]); + break; + } else if (extend_c2h_dbg_content[i] == '\n') { + fw_debug_trace[i + 1] = '\0'; + PHYDM_DBG(dm, DBG_FW_TRACE, "[FW DBG Msg] %s", + &fw_debug_trace[0]); + buffer = extend_c2h_dbg_content + i + 3; + goto go_backfor_aggre_dbg_pkt; + } + } +#endif /*@#ifdef CONFIG_PHYDM_DEBUG_FUNCTION*/ +} diff --git a/hal/phydm/phydm_debug.h b/hal/phydm/phydm_debug.h new file mode 100644 index 0000000..06e809b --- /dev/null +++ b/hal/phydm/phydm_debug.h @@ -0,0 +1,484 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + +/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/ +/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/ +/*#define DEBUG_VERSION "1.3"*/ /*2016.04.28 YuChen*/ +/*#define DEBUG_VERSION "1.4"*/ /*2017.03.13 Dino*/ +/*#define DEBUG_VERSION "2.0"*/ /*2018.01.10 Dino*/ +/*2020.07.03 fix cck report bug due to 8723F coding error*/ +#define DEBUG_VERSION "4.6" + +/*@ + * ============================================================ + * Definition + * ============================================================ + */ + +/*@FW DBG MSG*/ +#define RATE_DECISION 1 +#define INIT_RA_TABLE 2 +#define RATE_UP 4 +#define RATE_DOWN 8 +#define TRY_DONE 16 +#define RA_H2C 32 +#define F_RATE_AP_RPT 64 +#define DBC_FW_CLM 9 + +#define PHYDM_SNPRINT_SIZE 64 +/* @---------------------------------------------------------------------------- + * Define the tracing components + * + * ----------------------------------------------------------------------------- + * BB FW Functions + */ +#define PHYDM_FW_COMP_RA BIT(0) +#define PHYDM_FW_COMP_MU BIT(1) +#define PHYDM_FW_COMP_PATH_DIV BIT(2) +#define PHYDM_FW_COMP_PT BIT(3) + +/*@------------------------Export Marco Definition---------------------------*/ + +#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if (DBG_CMD_SUPPORT == 1) + extern VOID DCMD_Printf(const char *pMsg); + #else + #define DCMD_Printf(_pMsg) + #endif + + #if OS_WIN_FROM_WIN10(OS_VERSION) + #define pr_debug(fmt, ...) DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, fmt, ##__VA_ARGS__) + #else + #define pr_debug DbgPrint + #endif + + #define dcmd_printf DCMD_Printf + #define dcmd_scanf DCMD_Scanf + #define RT_PRINTK pr_debug + #define PRINT_MAX_SIZE 512 + #define PHYDM_SNPRINTF RT_SPRINTF + #define PHYDM_TRACE(_MSG_) EXhalPHYDMoutsrc_Print(_MSG_) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + #define PHYDM_SNPRINTF snprintf +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #undef pr_debug + #define pr_debug printk + #define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args) + #define RT_DISP(dbgtype, dbgflag, printstr) + #define RT_TRACE(adapter, comp, drv_level, fmt, args...) \ + RTW_INFO(fmt, ## args) + #define PHYDM_SNPRINTF snprintf +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #define pr_debug(fmt, args...) RTW_PRINT_MSG(fmt, ## args) + #define RT_DEBUG(comp, drv_level, fmt, args...) \ + RTW_PRINT_MSG(fmt, ## args) + #define PHYDM_SNPRINTF snprintf +#else + #define pr_debug panic_printk + /*@#define RT_PRINTK(fmt, args...) pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/ + #define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args) + #define PHYDM_SNPRINTF snprintf +#endif + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#if DBG +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + pr_debug("[PHYDM] "); \ + RT_PRINTK(fmt, ## args); \ + } \ + } while (0) + +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_PRINTK(fmt, ## args); \ + } \ + } while (0) + +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + if ((comp) & dm->debug_components) { \ + int __i; \ + u8 *__ptr = (u8 *)addr; \ + pr_debug("[PHYDM] "); \ + pr_debug(title_str); \ + pr_debug(" "); \ + for (__i = 0; __i < 6; __i++) \ + pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\ + pr_debug("\n"); \ + } \ + } while (0) +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->debug_components) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + DbgPrint("Failed (%d) to print message to buffer\n", rt_status); + return; + } + + #if OS_WIN_FROM_WIN10(OS_VERSION) + DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf); + #else + DbgPrint("%s", buf); + #endif +} + +static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->debug_components) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + /*@DbgPrint("DM Print Fail\n");*/ + return; + } + + #if OS_WIN_FROM_WIN10(OS_VERSION) + DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf); + #else + DbgPrint("%s", buf); + #endif +} + +#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) \ + do { \ + if ((comp) & p_dm->debug_components) { \ + \ + int __i; \ + u8 *__ptr = (u8 *)ptr; \ + pr_debug("[PHYDM] "); \ + pr_debug(title_str); \ + pr_debug(" "); \ + for (__i = 0; __i < 6; __i++) \ + pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ + pr_debug("\n"); \ + } \ + } while (0) +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_DEBUG(COMP_PHYDM, \ + DBG_DMESG, "[PHYDM] " fmt, ##args); \ + } \ + } while (0) + +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_DEBUG(COMP_PHYDM, \ + DBG_DMESG, fmt, ##args); \ + } \ + } while (0) + +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + if ((comp) & dm->debug_components) { \ + RT_DEBUG(COMP_PHYDM, \ + DBG_DMESG, "[PHYDM] " title_str "%pM\n", \ + addr); \ + } \ + } while (0) + +#elif defined(DM_ODM_CE_MAC80211_V2) + +#define PHYDM_DBG(dm, comp, fmt, args...) +#define PHYDM_DBG_F(dm, comp, fmt, args...) +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) + +#else + +#define PHYDM_DBG(dm, comp, fmt, args...) \ + do { \ + struct dm_struct *__dm = (dm); \ + if ((comp) & __dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)__dm->adapter),\ + COMP_PHYDM, DBG_DMESG, \ + "[PHYDM] " fmt, ##args); \ + } \ + } while (0) + +#define PHYDM_DBG_F(dm, comp, fmt, args...) \ + do { \ + struct dm_struct *__dm = (dm); \ + if ((comp) & __dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)__dm->adapter),\ + COMP_PHYDM, DBG_DMESG, fmt, ##args); \ + } \ + } while (0) + +#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \ + do { \ + struct dm_struct *__dm = (dm); \ + if ((comp) & __dm->debug_components) { \ + RT_TRACE(((struct rtl_priv *)__dm->adapter),\ + COMP_PHYDM, DBG_DMESG, \ + "[PHYDM] " title_str "%pM\n", addr);\ + } \ + } while (0) +#endif + +#else /*@#if DBG*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if ((comp & dm->debug_components) == 0) + return; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + DbgPrint("Failed (%d) to print message to buffer\n", rt_status); + return; + } + + PHYDM_TRACE(buf); +} +static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...) +{ +} +#else +#define PHYDM_DBG(dm, comp, fmt, args...) +#define PHYDM_DBG_F(dm, comp, fmt, args...) +#endif +#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr) + +#endif + +#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/ +#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/ +#define DBGPORT_PRI_1 1 /*Watch dog function*/ +#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/ + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define PHYDM_DBGPRINT 0 +#define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z) +#define PDM_VAST_SNPF PDM_SNPF +#if (PHYDM_DBGPRINT == 1) +#define PDM_SNPF(msg) \ + do {\ + rsprintf msg;\ + pr_debug("%s", output);\ + } while (0) +#else + +static __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len, + char *fmt, ...) +{ + RT_STATUS rt_status; + va_list args; + char buf[PRINT_MAX_SIZE] = {0}; + + if (fmt == NULL) + return; + + va_start(args, fmt); + rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args); + va_end(args); + + if (rt_status != RT_STATUS_SUCCESS) { + /*@DbgPrint("DM Print Fail\n");*/ + return; + } + + DCMD_Printf(buf); +} + + + +#endif /*@#if (PHYDM_DBGPRINT == 1)*/ +#else /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__) + #define PHYDM_DBGPRINT 0 + #else + #define PHYDM_DBGPRINT 1 + #endif +#define MAX_ARGC 20 +#define MAX_ARGV 16 +#define DCMD_DECIMAL "%d" +#define DCMD_CHAR "%c" +#define DCMD_HEX "%x" + +#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + RT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args); \ + } while (0) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) +#else +#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \ + RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \ + DBG_DMESG, fmt, ##args) +#endif + +#if (PHYDM_DBGPRINT == 1) +#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + snprintf(buff, len, fmt, ##args); \ + pr_debug("%s", output); \ + } while (0) +#else +#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \ + do { \ + u32 *__pdm_snpf_u = &(used); \ + if (out_len > *__pdm_snpf_u) \ + *__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\ + } while (0) +#endif +#endif +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +enum auto_detection_state { /*@Fast antenna training*/ + AD_LEGACY_MODE = 0, + AD_HT_MODE = 1, + AD_VHT_MODE = 2 +}; + +/*@ + * ============================================================ + * 1 structure + * ============================================================ + */ + +#ifdef CONFIG_PHYDM_DEBUG_FUNCTION +u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig); +#endif + +void phydm_init_debug_setting(struct dm_struct *dm); + +void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx); + +u32 phydm_get_bb_dbg_port_idx(void *dm_void); + +u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port); + +void phydm_release_bb_dbg_port(void *dm_void); + +u32 phydm_get_bb_dbg_port_val(void *dm_void); + +void phydm_reset_rx_rate_distribution(struct dm_struct *dm); + +void phydm_rx_rate_distribution(void *dm_void); + +u16 phydm_rx_avg_phy_rate(void *dm_void); + +void phydm_show_phy_hitogram(void *dm_void); + +void phydm_get_avg_phystatus_val(void *dm_void); + +void phydm_get_phy_statistic(void *dm_void); + +void phydm_dm_summary(void *dm_void, u8 macid); + +void phydm_basic_dbg_message(void *dm_void); + +void phydm_basic_profile(void *dm_void, u32 *_used, char *output, + u32 *_out_len); +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP)) +s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag, + char *output, u32 out_len); +#endif +void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num, + u8 flag, char *output, u32 out_len); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf); + +void phydm_sbd_check( + struct dm_struct *dm); + +void phydm_sbd_callback( + struct phydm_timer_list *timer); + +void phydm_sbd_workitem_callback( + void *context); +#endif + +void phydm_fw_trace_en_h2c(void *dm_void, boolean enable, + u32 fw_debug_component, u32 monitor_mode, u32 macid); + +void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len); + +void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +#endif /* @__ODM_DBG_H__ */ diff --git a/hal/phydm/phydm_dfs.c b/hal/phydm/phydm_dfs.c new file mode 100644 index 0000000..0384148 --- /dev/null +++ b/hal/phydm/phydm_dfs.c @@ -0,0 +1,2193 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@ + * ============================================================ + * include files + * ============================================================ + */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if defined(CONFIG_PHYDM_DFS_MASTER) + +boolean phydm_dfs_is_meteorology_channel(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + u8 ch = *dm->channel; + u8 bw = *dm->band_width; + + return ((bw == CHANNEL_WIDTH_80 && (ch) >= 116 && (ch) <= 128) || + (bw == CHANNEL_WIDTH_40 && (ch) >= 116 && (ch) <= 128) || + (bw == CHANNEL_WIDTH_20 && (ch) >= 120 && (ch) <= 128)); +} + +void phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & (ODM_RTL8814B))) + return; + if (syn_path == RF_SYN1) + dm->seg1_dfs_flag = 1; + else + dm->seg1_dfs_flag = 0; +} + +void phydm_dfs_segment_flag_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & (ODM_RTL8814B))) + return; + if (dm->seg1_dfs_flag) + dm->seg1_dfs_flag = 0; +} + +void phydm_radar_detect_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G | ODM_RTL8723F)) { + odm_set_bb_reg(dm, R_0xa40, BIT(15), 0); + odm_set_bb_reg(dm, R_0xa40, BIT(15), 1); + #if (RTL8721D_SUPPORT) + } else if (dm->support_ic_type & (ODM_RTL8721D)) { + odm_set_bb_reg(dm, R_0xf58, BIT(29), 0); + odm_set_bb_reg(dm, R_0xf58, BIT(29), 1); + #endif + } else if (dm->support_ic_type & (ODM_RTL8814B)) { + if (dm->seg1_dfs_flag == 1) { + odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0); + odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1); + return; + } + odm_set_bb_reg(dm, R_0xa40, BIT(15), 0); + odm_set_bb_reg(dm, R_0xa40, BIT(15), 1); + } else { + odm_set_bb_reg(dm, R_0x924, BIT(15), 0); + odm_set_bb_reg(dm, R_0x924, BIT(15), 1); + } +} + +void phydm_radar_detect_disable(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G | ODM_RTL8723F)) + odm_set_bb_reg(dm, R_0xa40, BIT(15), 0); + else if (dm->support_ic_type & (ODM_RTL8814B)) { + if (dm->seg1_dfs_flag == 1) { + odm_set_bb_reg(dm, R_0xa6c, BIT(0), 0); + dm->seg1_dfs_flag = 0; + return; + } + odm_set_bb_reg(dm, R_0xa40, BIT(15), 0); + } + #if (RTL8721D_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8721D)) + odm_set_bb_reg(dm, R_0xf58, BIT(29), 0); + #endif + else + odm_set_bb_reg(dm, R_0x924, BIT(15), 0); + + PHYDM_DBG(dm, DBG_DFS, "\n"); +} + +static void phydm_radar_detect_with_dbg_parm(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_RTL8721D) { + odm_set_bb_reg(dm, R_0xf54, MASKDWORD, + dm->radar_detect_reg_f54); + odm_set_bb_reg(dm, R_0xf58, MASKDWORD, + dm->radar_detect_reg_f58); + odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, + dm->radar_detect_reg_f5c); + odm_set_bb_reg(dm, R_0xf70, MASKDWORD, + dm->radar_detect_reg_f70); + odm_set_bb_reg(dm, R_0xf74, MASKDWORD, + dm->radar_detect_reg_f74); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + odm_set_bb_reg(dm, R_0xa40, MASKDWORD, + dm->radar_detect_reg_a40); + odm_set_bb_reg(dm, R_0xa44, MASKDWORD, + dm->radar_detect_reg_a44); + odm_set_bb_reg(dm, R_0xa48, MASKDWORD, + dm->radar_detect_reg_a48); + odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, + dm->radar_detect_reg_a4c); + odm_set_bb_reg(dm, R_0xa50, MASKDWORD, + dm->radar_detect_reg_a50); + odm_set_bb_reg(dm, R_0xa54, MASKDWORD, + dm->radar_detect_reg_a54); + } else { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + dm->radar_detect_reg_918); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + dm->radar_detect_reg_91c); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, + dm->radar_detect_reg_920); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, + dm->radar_detect_reg_924); + } +} + +/* @Init radar detection parameters, called after ch, bw is set */ + +void phydm_radar_detect_enable(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + u8 band_width = *dm->band_width; + u8 enable = 0, i; + u8 short_pw_upperbound = 0; + + PHYDM_DBG(dm, DBG_DFS, "test, region_domain = %d\n", region_domain); + if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) { + PHYDM_DBG(dm, DBG_DFS, "PHYDM_DFS_DOMAIN_UNKNOWN\n"); + goto exit; + } + + if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812 | ODM_RTL8881A)) { + odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06); + + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); + enable = 1; + goto exit; + } + + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c17ecdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fa21a20); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f69204); + + } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234); + + if (c_channel >= 52 && c_channel <= 64) { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c16ecdf); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x0f141a20); + } else { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c16acdf); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64721a20); + else + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x68721a20); + } + + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x01528500); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67231); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64741a20); + else + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x68741a20); + + } else { + /* not supported */ + PHYDM_DBG(dm, DBG_DFS, + "Unsupported dfs_region_domain:%d\n", + region_domain); + goto exit; + } + + } else if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + + odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10); + odm_set_bb_reg(dm, R_0x834, MASKBYTE0, 0x06); + + /* @8822B only, when BW = 20M, DFIR output is 40Mhz, + * but DFS input is 80MMHz, so it need to upgrade to 80MHz + */ + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x1984, BIT(26), 1); + else + odm_set_bb_reg(dm, R_0x1984, BIT(26), 0); + } + + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); + enable = 1; + goto exit; + } + + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c16acdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, 0x0fc01a1f); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0f57204); + + } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8500); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe0d67234); + + if (c_channel >= 52 && c_channel <= 64) { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c16ecdf); + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x0f141a1f); + } else { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, + 0x1c166cdf); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64721a1f); + else + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x68721a1f); + } + + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + odm_set_bb_reg(dm, R_0x918, MASKDWORD, 0x1c176cdf); + odm_set_bb_reg(dm, R_0x924, MASKDWORD, 0x095a8400); + odm_set_bb_reg(dm, R_0x920, MASKDWORD, 0xe076d231); + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x64901a1f); + else + odm_set_bb_reg(dm, R_0x91c, MASKDWORD, + 0x62901a1f); + + } else { + /* not supported */ + PHYDM_DBG(dm, DBG_DFS, + "Unsupported dfs_region_domain:%d\n", + region_domain); + goto exit; + } + /*RXHP low corner will extend the pulse width, + *so we need to increase the upper bound. + */ + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + if (odm_get_bb_reg(dm, 0x8d8, + BIT28 | BIT27 | BIT26) == 0) { + short_pw_upperbound = + (u8)odm_get_bb_reg(dm, 0x91c, + BIT23 | BIT22 | + BIT21 | BIT20); + if ((short_pw_upperbound + 4) > 15) + odm_set_bb_reg(dm, 0x91c, + BIT23 | BIT22 | + BIT21 | BIT20, 15); + else + odm_set_bb_reg(dm, 0x91c, + BIT23 | BIT22 | + BIT21 | BIT20, + short_pw_upperbound + 4); + } + /*@if peak index -1~+1, use original NB method*/ + odm_set_bb_reg(dm, 0x19e4, 0x003C0000, 13); + odm_set_bb_reg(dm, 0x924, 0x70000, 0); + } + + if (dm->support_ic_type & (ODM_RTL8881A)) + odm_set_bb_reg(dm, 0xb00, 0xc0000000, 3); + + /*@for 8814 new dfs mechanism setting*/ + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) { + /*Turn off dfs scaling factor*/ + odm_set_bb_reg(dm, 0x19e4, 0x1fff, 0x0c00); + /*NonDC peak_th = 2times DC peak_th*/ + odm_set_bb_reg(dm, 0x19e4, 0x30000, 1); + /*power for debug and auto test flow latch after ST*/ + odm_set_bb_reg(dm, 0x9f8, 0xc0000000, 3); + + /*@low pulse width radar pattern will cause wrong drop*/ + /*@disable peak index should the same + *during the same short pulse (new mechan) + */ + odm_set_bb_reg(dm, 0x9f4, 0x80000000, 0); + + /*@disable peak index should the same + *during the same short pulse (old mechan) + */ + odm_set_bb_reg(dm, 0x924, 0x20000000, 0); + + /*@if peak index diff >=2, then drop the result*/ + odm_set_bb_reg(dm, 0x19e4, 0xe000, 2); + if (region_domain == 2) { + if ((c_channel >= 52) && (c_channel <= 64)) { + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, + 0xff000000, 2); + /*th2 = 3*0.4us, th3 = 4*0.4us + *th4 = 7*0.4, th5 = 34*0.4 + */ + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0x22070403); + + /*PRI hist th setting*/ + /*th1=42*32us*/ + odm_set_bb_reg(dm, 0x19b8, + 0x00007f80, 42); + /*th2=47*32us, th3=115*32us, + *th4=123*32us, th5=130*32us + */ + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x827b732f); + } else { + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, + 0xff000000, 1); + /*th2 = 13*0.4us, th3 = 26*0.4us + *th4 = 75*0.4us, th5 = 255*0.4us + */ + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0xff4b1a0d); + /*PRI hist th setting*/ + /*th1=4*32us*/ + + odm_set_bb_reg(dm, 0x19b8, + 0x00007f80, 4); + /*th2=8*32us, th3=16*32us, + *th4=32*32us, th5=128*32=4096us + */ + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x80201008); + } + } + /*@ETSI*/ + else if (region_domain == 3) { + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, 0xff000000, 1); + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0x68260d06); + /*PRI hist th setting*/ + /*th1=7*32us*/ + odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 7); + /*th2=40*32us, th3=80*32us, + *th4=110*32us, th5=157*32=5024 + */ + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0xc06e2010); + } + /*@FCC*/ + else if (region_domain == 1) { + /*pulse width hist th setting*/ + /*th1=2*04us*/ + odm_set_bb_reg(dm, 0x19e4, 0xff000000, 2); + /*th2 = 13*0.4us, th3 = 26*0.4us, + *th4 = 75*0.4us, th5 = 255*0.4us + */ + odm_set_bb_reg(dm, 0x19e8, + MASKDWORD, 0xff4b1a0d); + + /*PRI hist th setting*/ + /*th1=4*32us*/ + odm_set_bb_reg(dm, 0x19b8, 0x00007f80, 4); + /*th2=8*32us, th3=21*32us, + *th4=32*32us, th5=96*32=3072 + */ + if (band_width == CHANNEL_WIDTH_20) + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x60282010); + else + odm_set_bb_reg(dm, 0x19ec, + MASKDWORD, 0x60282420); + } else { + } + } + } else if (dm->support_ic_type & + ODM_IC_JGR3_SERIES) { + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); + enable = 1; + goto exit; + } + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd); + if (dm->support_ic_type & (ODM_RTL8814B)) { + if (dm->seg1_dfs_flag == 1) + odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1); + } + odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd); + odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254); + odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345); + odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003); + odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8); + } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd); + if (dm->support_ic_type & (ODM_RTL8814B)) { + if (dm->seg1_dfs_flag == 1) + odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1); + } + odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd); + odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254); + odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345); + odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003); + odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8); + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + odm_set_bb_reg(dm, R_0xa40, MASKDWORD, 0xb359c5bd); + if (dm->support_ic_type & (ODM_RTL8814B)) { + if (dm->seg1_dfs_flag == 1) + odm_set_bb_reg(dm, R_0xa6c, BIT(0), 1); + } + odm_set_bb_reg(dm, R_0xa44, MASKDWORD, 0x3033bebd); + odm_set_bb_reg(dm, R_0xa48, MASKDWORD, 0x2a521254); + odm_set_bb_reg(dm, R_0xa4c, MASKDWORD, 0xa2533345); + odm_set_bb_reg(dm, R_0xa50, MASKDWORD, 0x605be003); + odm_set_bb_reg(dm, R_0xa54, MASKDWORD, 0x500089e8); + } else { + /* not supported */ + PHYDM_DBG(dm, DBG_DFS, + "Unsupported dfs_region_domain:%d\n", + region_domain); + goto exit; + } + #if (RTL8721D_SUPPORT) + } else if (dm->support_ic_type & ODM_RTL8721D) { + odm_set_bb_reg(dm, R_0x814, 0x3fffffff, 0x04cc4d10); + /*CCA MASK*/ + odm_set_bb_reg(dm, R_0xc38, 0x07c00000, 0x06); + /*CCA Threshold*/ + odm_set_bb_reg(dm, R_0xc3c, 0x00000007, 0x0); + + if (dm->radar_detect_dbg_parm_en) { + phydm_radar_detect_with_dbg_parm(dm); + enable = 1; + goto exit; + } + + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8); + odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x354cd7dd); + odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25); + odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fab98); + odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc45029f); + + } else if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8); + odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab25); + odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398); + odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc450e9d); + + if (c_channel >= 52 && c_channel <= 64) { + odm_set_bb_reg(dm, R_0xf58, MASKDWORD, + 0x354cd7fd); + } else { + odm_set_bb_reg(dm, R_0xf58, MASKDWORD, + 0x354cd7bd); + } + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + odm_set_bb_reg(dm, R_0xf54, MASKDWORD, 0x230006a8); + odm_set_bb_reg(dm, R_0xf58, MASKDWORD, 0x3558d7bd); + odm_set_bb_reg(dm, R_0xf5c, MASKDWORD, 0x9984ab35); + odm_set_bb_reg(dm, R_0xf70, MASKDWORD, 0xbd9fb398); + odm_set_bb_reg(dm, R_0xf74, MASKDWORD, 0xcc444e9d); + } else { + /* not supported */ + PHYDM_DBG(dm, DBG_DFS, + "Unsupported dfs_region_domain:%d\n", + region_domain); + goto exit; + } + + /*if peak index -1~+1, use original NB method*/ + odm_set_bb_reg(dm, R_0xf70, 0x00070000, 0x7); + odm_set_bb_reg(dm, R_0xf74, 0x000c0000, 0); + + /*Turn off dfs scaling factor*/ + odm_set_bb_reg(dm, R_0xf70, 0x00080000, 0x0); + /*NonDC peak_th = 2times DC peak_th*/ + odm_set_bb_reg(dm, R_0xf58, 0x00007800, 1); + + /*low pulse width radar pattern will cause wrong drop*/ + /*disable peak index should the same*/ + /*during the same short pulse (new mechan)*/ + odm_set_bb_reg(dm, R_0xf70, 0x00100000, 0x0); + /*if peak index diff >=2, then drop the result*/ + odm_set_bb_reg(dm, R_0xf70, 0x30000000, 0x2); + #endif + } else { + /*not supported IC type*/ + PHYDM_DBG(dm, DBG_DFS, "Unsupported IC type:%d\n", + dm->support_ic_type); + goto exit; + } + + enable = 1; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00); + dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xa50, 0x000000f0); + dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xa48, 0x00c00000); + dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa50, + 0x00f00000); + dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xa4c, + 0xf0000000); + dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00030000); + dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xa40, + 0x30000000); + dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, R_0xa44, + 0x00000007); + #if (RTL8721D_SUPPORT) + } else if (dm->support_ic_type & (ODM_RTL8721D)) { + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xf54, + 0x0000001f) << 2); + dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000); + dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0xf70, 0x03c00000); + dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0xf5c, 0x00000030); + dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf70, + 0x00007800); + dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0xf74, + 0x0000000f); + dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0xf58, 0x18000000); + dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, R_0xf58, + 0x00030000); + dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, + R_0xf58, 0x00007c00); + #endif + } else { + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff); + dfs->pwdb_th_cur = (u8)odm_get_bb_reg(dm, R_0x918, 0x00001f00); + dfs->peak_th = (u8)odm_get_bb_reg(dm, R_0x918, 0x00030000); + dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920, + 0x000f0000); + dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(dm, R_0x920, + 0x00f00000); + dfs->peak_window = (u8)odm_get_bb_reg(dm, R_0x920, 0x00000300); + dfs->three_peak_opt = (u8)odm_get_bb_reg(dm, 0x924, 0x00000180); + dfs->three_peak_th2 = (u8)odm_get_bb_reg(dm, 0x924, 0x00007000); + } + + phydm_dfs_parameter_init(dm); + +exit: + if (enable) { + phydm_radar_detect_reset(dm); + PHYDM_DBG(dm, DBG_DFS, "on cch:%u, bw:%u\n", c_channel, + band_width); + } else + phydm_radar_detect_disable(dm); +} + +void phydm_dfs_parameter_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + + u8 i; + for (i = 0; i < 5; i++) { + dfs->pulse_flag_hist[i] = 0; + dfs->pulse_type_hist[i] = 0; + dfs->radar_det_mask_hist[i] = 0; + dfs->fa_inc_hist[i] = 0; + } + + /*@for dfs mode*/ + dfs->force_TP_mode = 0; + dfs->sw_trigger_mode = 0; + dfs->det_print = 0; + dfs->det_print2 = 0; + dfs->print_hist_rpt = 0; + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + dfs->hist_cond_on = 1; + else + dfs->hist_cond_on = 0; + + /*@for dynamic dfs*/ + dfs->pwdb_th = 8; + dfs->fa_mask_th = 30 * (dfs->dfs_polling_time) / 100; + dfs->st_l2h_min = 0x20; + dfs->st_l2h_max = 0x4e; + dfs->pwdb_scalar_factor = 12; + + /*@for dfs histogram*/ + dfs->pri_hist_th = 5; + dfs->pri_sum_g1_th = 9; + dfs->pri_sum_g5_th = 5; + dfs->pri_sum_g1_fcc_th = 4; /*@FCC Type6*/ + dfs->pri_sum_g3_fcc_th = 6; + dfs->pri_sum_safe_th = 50; + dfs->pri_sum_safe_fcc_th = 110; /*@30 for AP*/ + dfs->pri_sum_type4_th = 16; + dfs->pri_sum_type6_th = 12; + dfs->pri_sum_g5_under_g1_th = 4; + dfs->pri_pw_diff_th = 4; + dfs->pri_pw_diff_fcc_th = 8; + dfs->pri_pw_diff_fcc_idle_th = 2; + dfs->pri_pw_diff_w53_th = 10; + dfs->pw_std_th = 7; /*@FCC Type4*/ + dfs->pw_std_idle_th = 10; + dfs->pri_std_th = 6; /*@FCC Type3,4,6*/ + dfs->pri_std_idle_th = 10; + dfs->pri_type1_upp_fcc_th = 110; + dfs->pri_type1_low_fcc_th = 50; + dfs->pri_type1_cen_fcc_th = 70; + dfs->pw_g0_th = 8; + dfs->pw_long_lower_th = 6; /*@7->6*/ + dfs->pri_long_upper_th = 30; + dfs->pw_long_lower_20m_th = 7; /*@7 for AP*/ + dfs->pw_long_sum_upper_th = 60; + dfs->type4_pw_max_cnt = 7; + dfs->type4_safe_pri_sum_th = 5; +} + +void phydm_dfs_dynamic_setting( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + + u8 peak_th_cur = 0, short_pulse_cnt_th_cur = 0; + u8 long_pulse_cnt_th_cur = 0, three_peak_opt_cur = 0; + u8 three_peak_th2_cur = 0; + u8 peak_window_cur = 0; + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + + if (dm->rx_tp + dm->tx_tp <= 2) { + dfs->idle_mode = 1; + if (dfs->force_TP_mode) + dfs->idle_mode = 0; + } else { + dfs->idle_mode = 0; + } + + if (dfs->idle_mode == 1) { /*@idle (no traffic)*/ + peak_th_cur = 3; + short_pulse_cnt_th_cur = 6; + long_pulse_cnt_th_cur = 9; + peak_window_cur = 2; + three_peak_opt_cur = 0; + three_peak_th2_cur = 2; + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if (c_channel >= 52 && c_channel <= 64) { + short_pulse_cnt_th_cur = 14; + long_pulse_cnt_th_cur = 15; + three_peak_th2_cur = 0; + } else { + short_pulse_cnt_th_cur = 6; + three_peak_th2_cur = 0; + long_pulse_cnt_th_cur = 10; + } + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + three_peak_th2_cur = 0; + } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + long_pulse_cnt_th_cur = 15; + if (phydm_dfs_is_meteorology_channel(dm)) { + /*need to add check cac end condition*/ + peak_th_cur = 2; + three_peak_opt_cur = 0; + three_peak_th2_cur = 0; + short_pulse_cnt_th_cur = 7; + } else { + three_peak_opt_cur = 0; + three_peak_th2_cur = 0; + short_pulse_cnt_th_cur = 7; + } + } else /*@default: FCC*/ + three_peak_th2_cur = 0; + + } else { /*@in service (with TP)*/ + peak_th_cur = 2; + short_pulse_cnt_th_cur = 6; + long_pulse_cnt_th_cur = 7; + peak_window_cur = 2; + three_peak_opt_cur = 0; + three_peak_th2_cur = 2; + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if (c_channel >= 52 && c_channel <= 64) { + long_pulse_cnt_th_cur = 15; + /*@for high duty cycle*/ + short_pulse_cnt_th_cur = 5; + three_peak_th2_cur = 0; + } else { + three_peak_opt_cur = 0; + three_peak_th2_cur = 0; + long_pulse_cnt_th_cur = 8; + } + } else if (region_domain == PHYDM_DFS_DOMAIN_FCC) { + long_pulse_cnt_th_cur = 5; /*for 80M FCC*/ + short_pulse_cnt_th_cur = 5; /*for 80M FCC*/ + } else if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + long_pulse_cnt_th_cur = 15; + short_pulse_cnt_th_cur = 5; + three_peak_opt_cur = 0; + } + } + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (dfs->peak_th != peak_th_cur) + odm_set_bb_reg(dm, R_0xa48, 0x00c00000, peak_th_cur); + if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur) + odm_set_bb_reg(dm, R_0xa50, 0x00f00000, + short_pulse_cnt_th_cur); + if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur) + odm_set_bb_reg(dm, R_0xa4c, 0xf0000000, + long_pulse_cnt_th_cur); + if (dfs->peak_window != peak_window_cur) + odm_set_bb_reg(dm, R_0xa40, 0x00030000, + peak_window_cur); + if (dfs->three_peak_opt != three_peak_opt_cur) + odm_set_bb_reg(dm, R_0xa40, 0x30000000, + three_peak_opt_cur); + if (dfs->three_peak_th2 != three_peak_th2_cur) + odm_set_bb_reg(dm, R_0xa44, 0x00000007, + three_peak_th2_cur); + #if (RTL8721D_SUPPORT) + } else if (dm->support_ic_type & (ODM_RTL8721D)) { + if (dfs->peak_th != peak_th_cur) + odm_set_bb_reg(dm, R_0xf5c, 0x00000030, peak_th_cur); + if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur) + odm_set_bb_reg(dm, R_0xf70, 0x00007800, + short_pulse_cnt_th_cur); + if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur) + odm_set_bb_reg(dm, R_0xf74, 0x0000000f, + long_pulse_cnt_th_cur); + if (dfs->peak_window != peak_window_cur) + odm_set_bb_reg(dm, R_0xf58, 0x18000000, + peak_window_cur); + if (dfs->three_peak_opt != three_peak_opt_cur) + odm_set_bb_reg(dm, R_0xf58, 0x00030000, + three_peak_opt_cur); + if (dfs->three_peak_th2 != three_peak_th2_cur) + odm_set_bb_reg(dm, R_0xf58, 0x00007c00, + three_peak_th2_cur); + #endif + } else { + if (dfs->peak_th != peak_th_cur) + odm_set_bb_reg(dm, R_0x918, 0x00030000, peak_th_cur); + if (dfs->short_pulse_cnt_th != short_pulse_cnt_th_cur) + odm_set_bb_reg(dm, R_0x920, 0x000f0000, + short_pulse_cnt_th_cur); + if (dfs->long_pulse_cnt_th != long_pulse_cnt_th_cur) + odm_set_bb_reg(dm, R_0x920, 0x00f00000, + long_pulse_cnt_th_cur); + if (dfs->peak_window != peak_window_cur) + odm_set_bb_reg(dm, R_0x920, 0x00000300, + peak_window_cur); + if (dfs->three_peak_opt != three_peak_opt_cur) + odm_set_bb_reg(dm, R_0x924, 0x00000180, + three_peak_opt_cur); + if (dfs->three_peak_th2 != three_peak_th2_cur) + odm_set_bb_reg(dm, R_0x924, 0x00007000, + three_peak_th2_cur); + } + + dfs->peak_th = peak_th_cur; + dfs->short_pulse_cnt_th = short_pulse_cnt_th_cur; + dfs->long_pulse_cnt_th = long_pulse_cnt_th_cur; + dfs->peak_window = peak_window_cur; + dfs->three_peak_opt = three_peak_opt_cur; + dfs->three_peak_th2 = three_peak_th2_cur; +} + +boolean +phydm_radar_detect_dm_check( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 region_domain = dm->dfs_region_domain, index = 0; + + u16 i = 0, j = 0, fa_count_cur = 0, fa_count_inc = 0; + u16 total_fa_in_hist = 0, total_pulse_count_inc = 0; + u16 short_pulse_cnt_inc = 0, short_pulse_cnt_cur = 0; + u16 long_pulse_cnt_inc = 0, long_pulse_cnt_cur = 0; + u32 regf98_value = 0, reg918_value = 0, reg91c_value = 0; + u32 reg920_value = 0, reg924_value = 0, radar_rpt_reg_value = 0; + u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0; + u32 regdf4_value = 0, regf70_value = 0, regf74_value = 0; + #if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT) + u32 rega40_value = 0, rega44_value = 0, rega48_value = 0; + u32 rega4c_value = 0, rega50_value = 0, rega54_value = 0; + #endif + #if (RTL8721D_SUPPORT) + u32 reg908_value = 0, regdf4_value = 0; + u32 regf54_value = 0, regf58_value = 0, regf5c_value = 0; + u32 regf70_value = 0, regf74_value = 0; + #endif + boolean tri_short_pulse = 0, tri_long_pulse = 0, radar_type = 0; + boolean fault_flag_det = 0, fault_flag_psd = 0, fa_flag = 0; + boolean radar_detected = 0; + u8 st_l2h_new = 0, fa_mask_th = 0, k = 0, sum = 0; + u8 c_channel = *dm->channel; + + /*@Get FA count during past 100ms, R_0xf48 for AC series*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + fa_count_cur = (u16)odm_get_bb_reg(dm, R_0x2d00, MASKLWORD); + #if (RTL8721D_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8721D)) { + fa_count_cur = (u16)odm_get_bb_reg(dm, + ODM_REG_OFDM_FA_TYPE2_11N, + MASKHWORD); + fa_count_cur += (u16)odm_get_bb_reg(dm, + ODM_REG_OFDM_FA_TYPE3_11N, + MASKLWORD); + fa_count_cur += (u16)odm_get_bb_reg(dm, + ODM_REG_OFDM_FA_TYPE3_11N, + MASKHWORD); + fa_count_cur += (u16)odm_get_bb_reg(dm, + ODM_REG_OFDM_FA_TYPE4_11N, + MASKLWORD); + fa_count_cur += (u16)odm_get_bb_reg(dm, + ODM_REG_OFDM_FA_TYPE1_11N, + MASKLWORD); + fa_count_cur += (u16)odm_get_bb_reg(dm, + ODM_REG_OFDM_FA_TYPE1_11N, + MASKHWORD); + } + #endif + else + fa_count_cur = (u16)odm_get_bb_reg(dm, R_0xf48, 0x0000ffff); + + if (dfs->fa_count_pre == 0) + fa_count_inc = 0; + else if (fa_count_cur >= dfs->fa_count_pre) + fa_count_inc = fa_count_cur - dfs->fa_count_pre; + else + fa_count_inc = fa_count_cur; + dfs->fa_count_pre = fa_count_cur; + + dfs->fa_inc_hist[dfs->mask_idx] = fa_count_inc; + + for (i = 0; i < 5; i++) + total_fa_in_hist = total_fa_in_hist + dfs->fa_inc_hist[i]; + + if (dfs->mask_idx >= 2) + index = dfs->mask_idx - 2; + else + index = 5 + dfs->mask_idx - 2; + + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G| ODM_RTL8723F)) { + radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, 0xffffffff); + short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800) + >> 11); + long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000) + >> 22); + #if (RTL8721D_SUPPORT) + } else if (dm->support_ic_type & (ODM_RTL8721D)) { + reg908_value = (u32)odm_get_bb_reg(dm, R_0x908, MASKDWORD); + odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x254); + regdf4_value = odm_get_bb_reg(dm, R_0xdf4, MASKDWORD); + short_pulse_cnt_cur = (u16)((regdf4_value & 0x000ff000) >> 12); + long_pulse_cnt_cur = (u16)((regdf4_value & 0x0fc00000) >> 22); + + tri_short_pulse = (regdf4_value & BIT(20)) ? 1 : 0; + tri_long_pulse = (regdf4_value & BIT(28)) ? 1 : 0; + if (tri_short_pulse || tri_long_pulse) { + odm_set_bb_reg(dm, R_0xf58, BIT(29), 0); + odm_set_bb_reg(dm, R_0xf58, BIT(29), 1); + } + #endif + } else if (dm->support_ic_type & (ODM_RTL8814B)) { + if (dm->seg1_dfs_flag == 1) + radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e20, + 0xffffffff); + else + radar_rpt_reg_value = odm_get_bb_reg(dm, R_0x2e00, + 0xffffffff); + short_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x000ff800) + >> 11); + long_pulse_cnt_cur = (u16)((radar_rpt_reg_value & 0x0fc00000) + >> 22); + } else { + regf98_value = odm_get_bb_reg(dm, R_0xf98, 0xffffffff); + short_pulse_cnt_cur = (u16)(regf98_value & 0x000000ff); + long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8); + } + + /*@Get short pulse count, need carefully handle the counter overflow*/ + if (short_pulse_cnt_cur >= dfs->short_pulse_cnt_pre) { + short_pulse_cnt_inc = short_pulse_cnt_cur - + dfs->short_pulse_cnt_pre; + } else { + short_pulse_cnt_inc = short_pulse_cnt_cur; + } + dfs->short_pulse_cnt_pre = short_pulse_cnt_cur; + + /*@Get long pulse count, need carefully handle the counter overflow*/ + if (long_pulse_cnt_cur >= dfs->long_pulse_cnt_pre) { + long_pulse_cnt_inc = long_pulse_cnt_cur - + dfs->long_pulse_cnt_pre; + } else { + long_pulse_cnt_inc = long_pulse_cnt_cur; + } + dfs->long_pulse_cnt_pre = long_pulse_cnt_cur; + + total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc; + + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, + "===============================================\n"); + PHYDM_DBG(dm, DBG_DFS, "FA_count_inc[%d]\n", fa_count_inc); + if (dm->support_ic_type & (ODM_RTL8721D)) { + PHYDM_DBG(dm, DBG_DFS, + "Init_Gain[%x] st_l2h_cur[%x] 0xdf4[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", + dfs->igi_cur, dfs->st_l2h_cur, regdf4_value, + short_pulse_cnt_inc, long_pulse_cnt_inc); + regf54_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD); + regf58_value = odm_get_bb_reg(dm, R_0xf58, MASKDWORD); + regf5c_value = odm_get_bb_reg(dm, R_0xf5c, MASKDWORD); + regf70_value = odm_get_bb_reg(dm, R_0xf70, MASKDWORD); + regf74_value = odm_get_bb_reg(dm, R_0xf74, MASKDWORD); + PHYDM_DBG(dm, DBG_DFS, + "0xf54[%08x] 0xf58[%08x] 0xf5c[%08x] 0xf70[%08x] 0xf74[%08x]\n", + regf54_value, regf58_value, regf5c_value, + regf70_value, regf74_value); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + PHYDM_DBG(dm, DBG_DFS, + "Init_Gain[%x] st_l2h_cur[%x] 0x2dbc[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", + dfs->igi_cur, dfs->st_l2h_cur, + radar_rpt_reg_value, short_pulse_cnt_inc, + long_pulse_cnt_inc); + #if (RTL8812F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT) + rega40_value = odm_get_bb_reg(dm, R_0xa40, MASKDWORD); + rega44_value = odm_get_bb_reg(dm, R_0xa44, MASKDWORD); + rega48_value = odm_get_bb_reg(dm, R_0xa48, MASKDWORD); + rega4c_value = odm_get_bb_reg(dm, R_0xa4c, MASKDWORD); + rega50_value = odm_get_bb_reg(dm, R_0xa50, MASKDWORD); + rega54_value = odm_get_bb_reg(dm, R_0xa54, MASKDWORD); + PHYDM_DBG(dm, DBG_DFS, + "0xa40[%08x] 0xa44[%08x] 0xa48[%08x] 0xa4c[%08x] 0xa50[%08x] 0xa54[%08x]\n", + rega40_value, rega44_value, rega48_value, + rega4c_value, rega50_value, rega54_value); + #endif + } else { + PHYDM_DBG(dm, DBG_DFS, + "Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n", + dfs->igi_cur, dfs->st_l2h_cur, regf98_value, + short_pulse_cnt_inc, long_pulse_cnt_inc); + reg918_value = odm_get_bb_reg(dm, R_0x918, + 0xffffffff); + reg91c_value = odm_get_bb_reg(dm, R_0x91c, + 0xffffffff); + reg920_value = odm_get_bb_reg(dm, R_0x920, + 0xffffffff); + reg924_value = odm_get_bb_reg(dm, R_0x924, + 0xffffffff); + PHYDM_DBG(dm, DBG_DFS, + "0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", + reg918_value, reg91c_value, + reg920_value, reg924_value); + } + PHYDM_DBG(dm, DBG_DFS, "Throughput: %dMbps\n", + (dm->rx_tp + dm->tx_tp)); + + PHYDM_DBG(dm, DBG_DFS, + "dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d, print_hist_rpt = %d, hist_cond_on = %d\n", + region_domain, dfs->dbg_mode, + dfs->idle_mode, dfs->print_hist_rpt, + dfs->hist_cond_on); + } + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + tri_short_pulse = (radar_rpt_reg_value & BIT(20)) ? 1 : 0; + tri_long_pulse = (radar_rpt_reg_value & BIT(28)) ? 1 : 0; + } else { + tri_short_pulse = (regf98_value & BIT(17)) ? 1 : 0; + tri_long_pulse = (regf98_value & BIT(19)) ? 1 : 0; + } + + if (tri_short_pulse) { + phydm_radar_detect_reset(dm); + } + if (tri_long_pulse) { + phydm_radar_detect_reset(dm); + if (region_domain == PHYDM_DFS_DOMAIN_MKK) { + if (c_channel >= 52 && c_channel <= 64) { + tri_long_pulse = 0; + } + } + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + tri_long_pulse = 0; + } + } + + st_l2h_new = dfs->st_l2h_cur; + dfs->pulse_flag_hist[dfs->mask_idx] = tri_short_pulse | tri_long_pulse; + dfs->pulse_type_hist[dfs->mask_idx] = (tri_long_pulse) ? 1 : 0; + + /* PSD(not ready) */ + + fault_flag_det = 0; + fault_flag_psd = 0; + fa_flag = 0; + if (region_domain == PHYDM_DFS_DOMAIN_ETSI) { + fa_mask_th = dfs->fa_mask_th + 20; + } else { + fa_mask_th = dfs->fa_mask_th; + } + if (total_fa_in_hist >= fa_mask_th || dfs->igi_cur >= 0x30) { + /* st_l2h_new = dfs->st_l2h_max; */ + dfs->radar_det_mask_hist[index] = 1; + if (dfs->pulse_flag_hist[index] == 1) { + dfs->pulse_flag_hist[index] = 0; + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, + "Radar is masked : FA mask\n"); + } + } + fa_flag = 1; + } else { + dfs->radar_det_mask_hist[index] = 0; + } + + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, "mask_idx: %d\n", dfs->mask_idx); + PHYDM_DBG(dm, DBG_DFS, "radar_det_mask_hist: "); + for (i = 0; i < 5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", + dfs->radar_det_mask_hist[i]); + PHYDM_DBG(dm, DBG_DFS, "pulse_flag_hist: "); + for (i = 0; i < 5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->pulse_flag_hist[i]); + PHYDM_DBG(dm, DBG_DFS, "fa_inc_hist: "); + for (i = 0; i < 5; i++) + PHYDM_DBG(dm, DBG_DFS, "%d ", dfs->fa_inc_hist[i]); + PHYDM_DBG(dm, DBG_DFS, + "\nfa_mask_th: %d, total_fa_in_hist: %d ", + fa_mask_th, total_fa_in_hist); + } + + sum = 0; + for (k = 0; k < 5; k++) { + if (dfs->radar_det_mask_hist[k] == 1) + sum++; + } + + if (dfs->mask_hist_checked <= 5) + dfs->mask_hist_checked++; + + if (dfs->mask_hist_checked >= 5 && dfs->pulse_flag_hist[index]) { + if (sum <= 2) { + if (dfs->hist_cond_on) { + /*return the value from hist_radar_detected*/ + radar_detected = phydm_dfs_hist_log(dm, index); + } else { + if (dfs->pulse_type_hist[index] == 0) + dfs->radar_type = 0; + else if (dfs->pulse_type_hist[index] == 1) + dfs->radar_type = 1; + radar_detected = 1; + PHYDM_DBG(dm, DBG_DFS, + "Detected type %d radar signal!\n", + dfs->radar_type); + } + } else { + fault_flag_det = 1; + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, + "Radar is masked : mask_hist large than thd\n"); + } + } + } + + dfs->mask_idx++; + if (dfs->mask_idx == 5) + dfs->mask_idx = 0; + + if (fault_flag_det == 0 && fault_flag_psd == 0 && fa_flag == 0) { + if (dfs->igi_cur < 0x30) { + st_l2h_new = dfs->st_l2h_min; + } + } + + if (st_l2h_new != dfs->st_l2h_cur) { + if (st_l2h_new < dfs->st_l2h_min) { + dfs->st_l2h_cur = dfs->st_l2h_min; + } else if (st_l2h_new > dfs->st_l2h_max) + dfs->st_l2h_cur = dfs->st_l2h_max; + else + dfs->st_l2h_cur = st_l2h_new; + /*odm_set_bb_reg(dm, R_0x91c, 0xff, dfs->st_l2h_cur);*/ + + dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur) + / 2 + dfs->pwdb_scalar_factor; + + /*@limit the pwdb value to absolute lower bound 8*/ + dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th); + + /*@limit the pwdb value to absolute upper bound 0x1f*/ + dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f); + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0xa50, 0x000000f0, + dfs->pwdb_th_cur); + #if (RTL8721D_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8721D) { + odm_set_bb_reg(dm, R_0xf54, 0x0000001f, + ((dfs->st_l2h_cur & 0x0000007c) >> 2)); + odm_set_bb_reg(dm, R_0xf58, 0xc0000000, + (dfs->st_l2h_cur & 0x00000003)); + odm_set_bb_reg(dm, R_0xf70, 0x03c00000, + dfs->pwdb_th_cur); + } + #endif + else + odm_set_bb_reg(dm, R_0x918, 0x00001f00, + dfs->pwdb_th_cur); + } + + if (dfs->det_print) { + PHYDM_DBG(dm, DBG_DFS, + "fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n", + fault_flag_det, fault_flag_psd, radar_detected); + } + #if (RTL8721D_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8721D)) + odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908_value); + #endif + + return radar_detected; +} + +#if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT) +void phydm_dfs_histogram_radar_distinguish( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 region_domain = dm->dfs_region_domain; + u8 c_channel = *dm->channel; + u8 band_width = *dm->band_width; + + u8 dfs_pw_thd1 = 0, dfs_pw_thd2 = 0, dfs_pw_thd3 = 0; + u8 dfs_pw_thd4 = 0, dfs_pw_thd5 = 0; + u8 dfs_pri_thd1 = 0, dfs_pri_thd2 = 0, dfs_pri_thd3 = 0; + u8 dfs_pri_thd4 = 0, dfs_pri_thd5 = 0; + u8 pri_th = 0, i = 0; + u8 max_pri_idx = 0, max_pw_idx = 0, max_pri_cnt_th = 0; + u8 max_pri_cnt_fcc_g1_th = 0, max_pri_cnt_fcc_g3_th = 0; + u8 safe_pri_pw_diff_th = 0, safe_pri_pw_diff_fcc_th = 0; + u8 safe_pri_pw_diff_w53_th = 0, safe_pri_pw_diff_fcc_idle_th = 0; + u8 j = 0; + u32 dfs_hist1_pw = 0, dfs_hist2_pw = 0, g_pw[6] = {0}; + u32 dfs_hist1_pri = 0, dfs_hist2_pri = 0, g_pri[6] = {0}; + u8 pw_sum_g0g5 = 0, pw_sum_g1g2g3g4 = 0; + u8 pri_sum_g0g5 = 0, pri_sum_g1g2g3g4 = 0; + u16 pw_sum_ss_g1g2g3g4 = 0, pri_sum_ss_g1g2g3g4 = 0; + u8 max_pri_cnt = 0, max_pw_cnt = 0; + #if (RTL8721D_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8721D)) + return; + #endif + + /*read pulse width hist report*/ + odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x1); + dfs_hist1_pw = odm_get_bb_reg(dm, 0xf5c, 0xffffffff); + dfs_hist2_pw = odm_get_bb_reg(dm, 0xf74, 0xffffffff); + + g_pw[0] = (unsigned int)((dfs_hist2_pw & 0xff000000) >> 24); + g_pw[1] = (unsigned int)((dfs_hist2_pw & 0x00ff0000) >> 16); + g_pw[2] = (unsigned int)((dfs_hist2_pw & 0x0000ff00) >> 8); + g_pw[3] = (unsigned int)dfs_hist2_pw & 0x000000ff; + g_pw[4] = (unsigned int)((dfs_hist1_pw & 0xff000000) >> 24); + g_pw[5] = (unsigned int)((dfs_hist1_pw & 0x00ff0000) >> 16); + + /*read pulse repetition interval hist report*/ + odm_set_bb_reg(dm, 0x19e4, BIT(22) | BIT(23), 0x3); + dfs_hist1_pri = odm_get_bb_reg(dm, 0xf5c, 0xffffffff); + dfs_hist2_pri = odm_get_bb_reg(dm, 0xf74, 0xffffffff); + odm_set_bb_reg(dm, 0x19b4, 0x10000000, 1); /*reset histo report*/ + odm_set_bb_reg(dm, 0x19b4, 0x10000000, 0); /*@continue histo report*/ + + g_pri[0] = (unsigned int)((dfs_hist2_pri & 0xff000000) >> 24); + g_pri[1] = (unsigned int)((dfs_hist2_pri & 0x00ff0000) >> 16); + g_pri[2] = (unsigned int)((dfs_hist2_pri & 0x0000ff00) >> 8); + g_pri[3] = (unsigned int)dfs_hist2_pri & 0x000000ff; + g_pri[4] = (unsigned int)((dfs_hist1_pri & 0xff000000) >> 24); + g_pri[5] = (unsigned int)((dfs_hist1_pri & 0x00ff0000) >> 16); + + dfs->pri_cond1 = 0; + dfs->pri_cond2 = 0; + dfs->pri_cond3 = 0; + dfs->pri_cond4 = 0; + dfs->pri_cond5 = 0; + dfs->pw_cond1 = 0; + dfs->pw_cond2 = 0; + dfs->pw_cond3 = 0; + dfs->pri_type3_4_cond1 = 0; /*@for ETSI*/ + dfs->pri_type3_4_cond2 = 0; /*@for ETSI*/ + dfs->pw_long_cond1 = 0; /*@for long radar*/ + dfs->pw_long_cond2 = 0; /*@for long radar*/ + dfs->pri_long_cond1 = 0; /*@for long radar*/ + dfs->pw_flag = 0; + dfs->pri_flag = 0; + dfs->pri_type3_4_flag = 0; /*@for ETSI*/ + dfs->long_radar_flag = 0; + dfs->pw_std = 0; /*The std(var) of reasonable num of pw group*/ + dfs->pri_std = 0; /*The std(var) of reasonable num of pri group*/ + + for (i = 0; i < 6; i++) { + dfs->pw_hold_sum[i] = 0; + dfs->pri_hold_sum[i] = 0; + } + + if (dfs->idle_mode == 1) + pri_th = dfs->pri_hist_th; + else + pri_th = dfs->pri_hist_th - 1; + + for (i = 0; i < 6; i++) { + dfs->pw_hold[dfs->hist_idx][i] = (u8)g_pw[i]; + dfs->pri_hold[dfs->hist_idx][i] = (u8)g_pri[i]; + /*@collect whole histogram report may take some time + *so we add the counter of 2 time slots in FCC and ETSI + */ + dfs->pw_hold_sum[i] = dfs->pw_hold_sum[i] + + dfs->pw_hold[(dfs->hist_idx + 1) % 3][i] + + dfs->pw_hold[(dfs->hist_idx + 2) % 3][i]; + dfs->pri_hold_sum[i] = dfs->pri_hold_sum[i] + + dfs->pri_hold[(dfs->hist_idx + 1) % 3][i] + + dfs->pri_hold[(dfs->hist_idx + 2) % 3][i]; + } + /*@For long radar type*/ + for (j = 1; j < 4; j++) { + dfs->pw_long_hold_sum[i] = dfs->pw_long_hold_sum[i] + + dfs->pw_hold[(dfs->hist_long_idx + j) % 4][i]; + dfs->pri_long_hold_sum[i] = dfs->pri_long_hold_sum[i] + + dfs->pri_hold[(dfs->hist_long_idx + j) % 4][i]; + } + + dfs->hist_idx++; + if (dfs->hist_idx == 3) + dfs->hist_idx = 0; + dfs->hist_long_idx++; + if (dfs->hist_long_idx == 4) + dfs->hist_long_idx = 0; + + max_pri_cnt = 0; + max_pri_idx = 0; + max_pw_cnt = 0; + max_pw_idx = 0; + max_pri_cnt_th = dfs->pri_sum_g1_th; + max_pri_cnt_fcc_g1_th = dfs->pri_sum_g1_fcc_th; + max_pri_cnt_fcc_g3_th = dfs->pri_sum_g3_fcc_th; + safe_pri_pw_diff_th = dfs->pri_pw_diff_th; + safe_pri_pw_diff_fcc_th = dfs->pri_pw_diff_fcc_th; + safe_pri_pw_diff_fcc_idle_th = dfs->pri_pw_diff_fcc_idle_th; + safe_pri_pw_diff_w53_th = dfs->pri_pw_diff_w53_th; + + /*@g1 to g4 is the reseasonable range of pri and pw*/ + for (i = 1; i <= 4; i++) { + if (dfs->pri_hold_sum[i] > max_pri_cnt) { + max_pri_cnt = dfs->pri_hold_sum[i]; + max_pri_idx = i; + } + if (dfs->pw_hold_sum[i] > max_pw_cnt) { + max_pw_cnt = dfs->pw_hold_sum[i]; + max_pw_idx = i; + } + if (dfs->pri_hold_sum[i] >= pri_th) + dfs->pri_cond1 = 1; + } + + pri_sum_g0g5 = dfs->pri_hold_sum[0]; + if (pri_sum_g0g5 == 0) + pri_sum_g0g5 = 1; + pri_sum_g1g2g3g4 = dfs->pri_hold_sum[1] + dfs->pri_hold_sum[2] + + dfs->pri_hold_sum[3] + dfs->pri_hold_sum[4]; + + /*pw will reduce because of dc, so we do not treat g0 as illegal group*/ + pw_sum_g0g5 = dfs->pw_hold_sum[5]; + if (pw_sum_g0g5 == 0) + pw_sum_g0g5 = 1; + pw_sum_g1g2g3g4 = dfs->pw_hold_sum[1] + dfs->pw_hold_sum[2] + + dfs->pw_hold_sum[3] + dfs->pw_hold_sum[4]; + + /*@Calculate the variation from g1 to g4*/ + for (i = 1; i < 5; i++) { + /*Sum of square*/ + pw_sum_ss_g1g2g3g4 = pw_sum_ss_g1g2g3g4 + + (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)) * + (dfs->pw_hold_sum[i] - (pw_sum_g1g2g3g4 / 4)); + pri_sum_ss_g1g2g3g4 = pri_sum_ss_g1g2g3g4 + + (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)) * + (dfs->pri_hold_sum[i] - (pri_sum_g1g2g3g4 / 4)); + } + /*The value may less than the normal variance, + *since the variable type is int (not float) + */ + dfs->pw_std = (u8)(pw_sum_ss_g1g2g3g4 / 4); + dfs->pri_std = (u8)(pri_sum_ss_g1g2g3g4 / 4); + + if (region_domain == 1) { + dfs->pri_type3_4_flag = 1; /*@ETSI flag*/ + + /*(OTA) Cancel long PRI case*/ + dfs->pri_cond2 = 1; + + /*reasonable group shouldn't large*/ + if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2 && + pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th) + dfs->pri_cond3 = 1; + + /*@Cancel the condition that the abs between pri and pw*/ + if (dfs->pri_std >= dfs->pri_std_th) + dfs->pri_cond4 = 1; + else if (max_pri_idx == 1 && + max_pri_cnt >= max_pri_cnt_fcc_g1_th) + dfs->pri_cond4 = 1; + + /*(OTA) Cancel the condition (type 3,4 distinction)*/ + dfs->pri_cond5 = 1; + + if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 && + dfs->pri_cond4 && dfs->pri_cond5) + dfs->pri_flag = 1; + + /* PW judgment conditions for short radar type */ + /*ratio of reasonable and illegal group && g5 should be zero*/ + if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) && + (dfs->pw_hold_sum[5] <= 1)) + dfs->pw_cond1 = 1; + /*unreasonable group*/ + if (dfs->pw_hold_sum[4] == 0 && dfs->pw_hold_sum[5] == 0) + dfs->pw_cond2 = 1; + /*pw's std (short radar) should be large(=7)*/ + if (dfs->pw_std >= dfs->pw_std_th) + dfs->pw_cond3 = 1; + if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3) + dfs->pw_flag = 1; + + /* @Judgment conditions of long radar type */ + if (band_width == CHANNEL_WIDTH_20) { + if (dfs->pw_long_hold_sum[4] >= + dfs->pw_long_lower_20m_th) + dfs->pw_long_cond1 = 1; + } else{ + if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th) + dfs->pw_long_cond1 = 1; + } + /* @Disable the condition that dfs->pw_long_hold_sum[1] */ + if (dfs->pw_long_hold_sum[2] + dfs->pw_long_hold_sum[3] + + dfs->pw_long_hold_sum[4] <= dfs->pw_long_sum_upper_th && + dfs->pw_long_hold_sum[2] <= dfs->pw_long_hold_sum[4] && + dfs->pw_long_hold_sum[3] <= dfs->pw_long_hold_sum[4]) + dfs->pw_long_cond2 = 1; + /*@g4 should be large for long radar*/ + if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th) + dfs->pri_long_cond1 = 1; + if (dfs->pw_long_cond1 && dfs->pw_long_cond2 && + dfs->pri_long_cond1) + dfs->long_radar_flag = 1; + } else if (region_domain == 2) { + dfs->pri_type3_4_flag = 1; /*@ETSI flag*/ + + /*PRI judgment conditions for short radar type*/ + if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2) + dfs->pri_cond2 = 1; + + /*reasonable group shouldn't too large*/ + if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_fcc_th) + dfs->pri_cond3 = 1; + + /*Cancel the abs diff between pri and pw for idle mode (thr=2)*/ + dfs->pri_cond4 = 1; + + if (dfs->idle_mode == 1) { + if (dfs->pri_std >= dfs->pri_std_idle_th) { + if (max_pw_idx == 3 && + pri_sum_g1g2g3g4 <= dfs->pri_sum_type4_th){ + /*To distinguish between type 4 radar and false detection*/ + dfs->pri_cond5 = 1; + } else if (max_pw_idx == 1 && + pri_sum_g1g2g3g4 >= + dfs->pri_sum_type6_th) { + /*To distinguish between type 6 radar and false detection*/ + dfs->pri_cond5 = 1; + } else { + /*pri variation of short radar should be large (idle mode)*/ + dfs->pri_cond5 = 1; + } + } + } else { + /*pri variation of short radar should be large (TP mode)*/ + if (dfs->pri_std >= dfs->pri_std_th) + dfs->pri_cond5 = 1; + } + + if (dfs->pri_cond1 && dfs->pri_cond2 && dfs->pri_cond3 && + dfs->pri_cond4 && dfs->pri_cond5) + dfs->pri_flag = 1; + + /* PW judgment conditions for short radar type */ + if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2) && + (dfs->pw_hold_sum[5] <= 1)) + /*ratio of reasonable and illegal group && g5 should be zero*/ + dfs->pw_cond1 = 1; + + if ((c_channel >= 52) && (c_channel <= 64)) + dfs->pw_cond2 = 1; + /*unreasonable group shouldn't too large*/ + else if (dfs->pw_hold_sum[0] <= dfs->pw_g0_th) + dfs->pw_cond2 = 1; + + if (dfs->idle_mode == 1) { + /*pw variation of short radar should be large (idle mode)*/ + if (dfs->pw_std >= dfs->pw_std_idle_th) + dfs->pw_cond3 = 1; + } else { + /*pw variation of short radar should be large (TP mode)*/ + if (dfs->pw_std >= dfs->pw_std_th) + dfs->pw_cond3 = 1; + } + if (dfs->pw_cond1 && dfs->pw_cond2 && dfs->pw_cond3) + dfs->pw_flag = 1; + + /* @Judgment conditions of long radar type */ + if (band_width == CHANNEL_WIDTH_20) { + if (dfs->pw_long_hold_sum[4] >= + dfs->pw_long_lower_20m_th) + dfs->pw_long_cond1 = 1; + } else{ + if (dfs->pw_long_hold_sum[4] >= dfs->pw_long_lower_th) + dfs->pw_long_cond1 = 1; + } + if (dfs->pw_long_hold_sum[1] + dfs->pw_long_hold_sum[2] + + dfs->pw_long_hold_sum[3] + dfs->pw_long_hold_sum[4] + <= dfs->pw_long_sum_upper_th) + dfs->pw_long_cond2 = 1; + /*@g4 should be large for long radar*/ + if (dfs->pri_long_hold_sum[4] <= dfs->pri_long_upper_th) + dfs->pri_long_cond1 = 1; + if (dfs->pw_long_cond1 && + dfs->pw_long_cond2 && dfs->pri_long_cond1) + dfs->long_radar_flag = 1; + } else if (region_domain == 3) { + /*ratio of reasonable group and illegal group */ + if ((pri_sum_g0g5 + pri_sum_g1g2g3g4) / pri_sum_g0g5 > 2) + dfs->pri_cond2 = 1; + + if (pri_sum_g1g2g3g4 <= dfs->pri_sum_safe_th) + dfs->pri_cond3 = 1; + + /*@Cancel the condition that the abs between pri and pw*/ + dfs->pri_cond4 = 1; + + if (dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_th) + dfs->pri_cond5 = 1; + + if (band_width == CHANNEL_WIDTH_40) { + if (max_pw_idx == 4) { + if (max_pw_cnt >= dfs->type4_pw_max_cnt && + pri_sum_g1g2g3g4 >= + dfs->type4_safe_pri_sum_th) { + dfs->pri_cond1 = 1; + dfs->pri_cond4 = 1; + dfs->pri_type3_4_cond1 = 1; + } + } + } + + if (dfs->pri_cond1 && dfs->pri_cond2 && + dfs->pri_cond3 && dfs->pri_cond4 && dfs->pri_cond5) + dfs->pri_flag = 1; + + if (((pw_sum_g0g5 + pw_sum_g1g2g3g4) / pw_sum_g0g5 > 2)) + dfs->pw_flag = 1; + + /*@max num pri group is g1 means radar type3 or type4*/ + if (max_pri_idx == 1) { + if (max_pri_cnt >= max_pri_cnt_th) + dfs->pri_type3_4_cond1 = 1; + if (dfs->pri_hold_sum[4] <= + dfs->pri_sum_g5_under_g1_th && + dfs->pri_hold_sum[5] <= dfs->pri_sum_g5_under_g1_th) + dfs->pri_type3_4_cond2 = 1; + } else { + dfs->pri_type3_4_cond1 = 1; + dfs->pri_type3_4_cond2 = 1; + } + if (dfs->pri_type3_4_cond1 && dfs->pri_type3_4_cond2) + dfs->pri_type3_4_flag = 1; + } else { + } + + if (dfs->print_hist_rpt) { + dfs_pw_thd1 = (u8)odm_get_bb_reg(dm, 0x19e4, 0xff000000); + dfs_pw_thd2 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x000000ff); + dfs_pw_thd3 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x0000ff00); + dfs_pw_thd4 = (u8)odm_get_bb_reg(dm, 0x19e8, 0x00ff0000); + dfs_pw_thd5 = (u8)odm_get_bb_reg(dm, 0x19e8, 0xff000000); + + dfs_pri_thd1 = (u8)odm_get_bb_reg(dm, 0x19b8, 0x7F80); + dfs_pri_thd2 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x000000ff); + dfs_pri_thd3 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x0000ff00); + dfs_pri_thd4 = (u8)odm_get_bb_reg(dm, 0x19ec, 0x00ff0000); + dfs_pri_thd5 = (u8)odm_get_bb_reg(dm, 0x19ec, 0xff000000); + + PHYDM_DBG(dm, DBG_DFS, "\ndfs_pw_thd=%d %d %d %d %d\n", + dfs_pw_thd1, dfs_pw_thd2, dfs_pw_thd3, + dfs_pw_thd4, dfs_pw_thd5); + PHYDM_DBG(dm, DBG_DFS, "-----pulse width hist-----\n"); + PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pw=%x %x\n", + dfs_hist1_pw, dfs_hist2_pw); + PHYDM_DBG(dm, DBG_DFS, "g_pw_hist = %x %x %x %x %x %x\n", + g_pw[0], g_pw[1], g_pw[2], g_pw[3], + g_pw[4], g_pw[5]); + PHYDM_DBG(dm, DBG_DFS, "dfs_pri_thd=%d %d %d %d %d\n", + dfs_pri_thd1, dfs_pri_thd2, dfs_pri_thd3, + dfs_pri_thd4, dfs_pri_thd5); + PHYDM_DBG(dm, DBG_DFS, "-----pulse interval hist-----\n"); + PHYDM_DBG(dm, DBG_DFS, "dfs_hist_pri=%x %x\n", + dfs_hist1_pri, dfs_hist2_pri); + PHYDM_DBG(dm, DBG_DFS, + "g_pri_hist = %x %x %x %x %x %x, pw_flag = %d, pri_flag = %d\n", + g_pri[0], g_pri[1], g_pri[2], g_pri[3], g_pri[4], + g_pri[5], dfs->pw_flag, dfs->pri_flag); + if (region_domain == 1 || region_domain == 3) { + PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n", + (dfs->hist_idx + 2) % 3); + } else { + PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n", + (dfs->hist_idx + 3) % 4); + } + PHYDM_DBG(dm, DBG_DFS, "hist_long_idx= %d\n", + (dfs->hist_long_idx + 299) % 300); + PHYDM_DBG(dm, DBG_DFS, + "pw_sum_g0g5 = %d, pw_sum_g1g2g3g4 = %d\n", + pw_sum_g0g5, pw_sum_g1g2g3g4); + PHYDM_DBG(dm, DBG_DFS, + "pri_sum_g0g5 = %d, pri_sum_g1g2g3g4 = %d\n", + pri_sum_g0g5, pri_sum_g1g2g3g4); + PHYDM_DBG(dm, DBG_DFS, "pw_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_hold_sum[0], dfs->pw_hold_sum[1], + dfs->pw_hold_sum[2], dfs->pw_hold_sum[3], + dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, "pri_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_hold_sum[0], dfs->pri_hold_sum[1], + dfs->pri_hold_sum[2], dfs->pri_hold_sum[3], + dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, "pw_long_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_long_hold_sum[0], dfs->pw_long_hold_sum[1], + dfs->pw_long_hold_sum[2], dfs->pw_long_hold_sum[3], + dfs->pw_long_hold_sum[4], dfs->pw_long_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, + "pri_long_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_long_hold_sum[0], dfs->pri_long_hold_sum[1], + dfs->pri_long_hold_sum[2], dfs->pri_long_hold_sum[3], + dfs->pri_long_hold_sum[4], dfs->pri_long_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", dfs->idle_mode); + PHYDM_DBG(dm, DBG_DFS, "pw_standard = %d\n", dfs->pw_std); + PHYDM_DBG(dm, DBG_DFS, "pri_standard = %d\n", dfs->pri_std); + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, + "pri_cond1 = %d, pri_cond2 = %d, pri_cond3 = %d, pri_cond4 = %d, pri_cond5 = %d\n", + dfs->pri_cond1, dfs->pri_cond2, dfs->pri_cond3, + dfs->pri_cond4, dfs->pri_cond5); + PHYDM_DBG(dm, DBG_DFS, + "bandwidth = %d, pri_th = %d, max_pri_cnt_th = %d, safe_pri_pw_diff_th = %d\n", + band_width, pri_th, max_pri_cnt_th, + safe_pri_pw_diff_th); + } +} +#endif +boolean phydm_dfs_hist_log(void *dm_void, u8 index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u8 i = 0, j = 0; + boolean hist_radar_detected = 0; + + if (dfs->pulse_type_hist[index] == 0) { + dfs->radar_type = 0; + if (dfs->pw_flag && dfs->pri_flag && + dfs->pri_type3_4_flag) { + hist_radar_detected = 1; + PHYDM_DBG(dm, DBG_DFS, + "Detected type %d radar signal!\n", + dfs->radar_type); + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, + "hist_idx= %d\n", + (dfs->hist_idx + 3) % 4); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) { + PHYDM_DBG(dm, DBG_DFS, + "pri_hold = %d ", + dfs->pri_hold[j][i]); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) { + PHYDM_DBG(dm, DBG_DFS, "pw_hold = %d ", + dfs->pw_hold[j][i]); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", + dfs->idle_mode); + PHYDM_DBG(dm, DBG_DFS, + "pw_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_hold_sum[0], + dfs->pw_hold_sum[1], + dfs->pw_hold_sum[2], + dfs->pw_hold_sum[3], + dfs->pw_hold_sum[4], + dfs->pw_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, + "pri_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_hold_sum[0], + dfs->pri_hold_sum[1], + dfs->pri_hold_sum[2], + dfs->pri_hold_sum[3], + dfs->pri_hold_sum[4], + dfs->pri_hold_sum[5]); + } + } else { + if (dfs->det_print2) { + if (dfs->pulse_flag_hist[index] && + dfs->pri_flag == 0) { + PHYDM_DBG(dm, DBG_DFS, "pri_variation = %d\n", + dfs->pri_std); + PHYDM_DBG(dm, DBG_DFS, + "PRI criterion is not satisfied!\n"); + if (dfs->pri_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond1 is not satisfied!\n"); + if (dfs->pri_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond2 is not satisfied!\n"); + if (dfs->pri_cond3 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond3 is not satisfied!\n"); + if (dfs->pri_cond4 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond4 is not satisfied!\n"); + if (dfs->pri_cond5 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_cond5 is not satisfied!\n"); + } + if (dfs->pulse_flag_hist[index] && + dfs->pw_flag == 0) { + PHYDM_DBG(dm, DBG_DFS, "pw_variation = %d\n", + dfs->pw_std); + PHYDM_DBG(dm, DBG_DFS, + "PW criterion is not satisfied!\n"); + if (dfs->pw_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pw_cond1 is not satisfied!\n"); + if (dfs->pw_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pw_cond2 is not satisfied!\n"); + if (dfs->pw_cond3 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pw_cond3 is not satisfied!\n"); + } + if (dfs->pulse_flag_hist[index] && + (dfs->pri_type3_4_flag == 0)) { + PHYDM_DBG(dm, DBG_DFS, + "pri_type3_4 criterion is not satisfied!\n"); + if (dfs->pri_type3_4_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_type3_4_cond1 is not satisfied!\n"); + if (dfs->pri_type3_4_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "pri_type3_4_cond2 is not satisfied!\n"); + } + PHYDM_DBG(dm, DBG_DFS, "hist_idx= %d\n", + (dfs->hist_idx + 3) % 4); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) { + PHYDM_DBG(dm, DBG_DFS, + "pri_hold = %d ", + dfs->pri_hold[j][i]); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + for (j = 0; j < 4; j++) { + for (i = 0; i < 6; i++) + PHYDM_DBG(dm, DBG_DFS, + "pw_hold = %d ", + dfs->pw_hold[j][i]); + PHYDM_DBG(dm, DBG_DFS, "\n"); + } + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", + dfs->idle_mode); + PHYDM_DBG(dm, DBG_DFS, + "pw_hold_sum = %d %d %d %d %d %d\n", + dfs->pw_hold_sum[0], dfs->pw_hold_sum[1], + dfs->pw_hold_sum[2], dfs->pw_hold_sum[3], + dfs->pw_hold_sum[4], dfs->pw_hold_sum[5]); + PHYDM_DBG(dm, DBG_DFS, + "pri_hold_sum = %d %d %d %d %d %d\n", + dfs->pri_hold_sum[0], dfs->pri_hold_sum[1], + dfs->pri_hold_sum[2], dfs->pri_hold_sum[3], + dfs->pri_hold_sum[4], dfs->pri_hold_sum[5]); + } + } + } else { + dfs->radar_type = 1; + if (dfs->det_print2) { + PHYDM_DBG(dm, DBG_DFS, "\n"); + PHYDM_DBG(dm, DBG_DFS, "idle_mode = %d\n", + dfs->idle_mode); + } + /* @Long radar should satisfy three conditions */ + if (dfs->long_radar_flag == 1) { + hist_radar_detected = 1; + PHYDM_DBG(dm, DBG_DFS, + "Detected type %d radar signal!\n", + dfs->radar_type); + } else { + if (dfs->det_print2) { + if (dfs->pw_long_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "--pw_long_cond1 is not satisfied!--\n"); + if (dfs->pw_long_cond2 == 0) + PHYDM_DBG(dm, DBG_DFS, + "--pw_long_cond2 is not satisfied!--\n"); + if (dfs->pri_long_cond1 == 0) + PHYDM_DBG(dm, DBG_DFS, + "--pri_long_cond1 is not satisfied!--\n"); + } + } + } + return hist_radar_detected; +} + +boolean phydm_radar_detect(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + boolean radar_detected = false; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0x1d70, 0x0000007f); + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0xa40, 0x00007f00); + #if (RTL8721D_SUPPORT) + } else if (dm->support_ic_type & (ODM_RTL8721D)) { + dfs->st_l2h_cur = (u8)(odm_get_bb_reg(dm, R_0xf54, + 0x0000001f) << 2); + dfs->st_l2h_cur += (u8)odm_get_bb_reg(dm, R_0xf58, 0xc0000000); + #endif + } else { + dfs->igi_cur = (u8)odm_get_bb_reg(dm, R_0xc50, 0x0000007f); + dfs->st_l2h_cur = (u8)odm_get_bb_reg(dm, R_0x91c, 0x000000ff); + } + + /* @dynamic pwdb calibration */ + if (dfs->igi_pre != dfs->igi_cur) { + dfs->pwdb_th_cur = ((int)dfs->st_l2h_cur - (int)dfs->igi_cur) + / 2 + dfs->pwdb_scalar_factor; + + /* @limit the pwdb value to absolute lower bound 0xa */ + dfs->pwdb_th_cur = MAX_2(dfs->pwdb_th_cur, (int)dfs->pwdb_th); + /* @limit the pwdb value to absolute upper bound 0x1f */ + dfs->pwdb_th_cur = MIN_2(dfs->pwdb_th_cur, 0x1f); + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + odm_set_bb_reg(dm, R_0xa50, 0x000000f0, + dfs->pwdb_th_cur); + #if (RTL8721D_SUPPORT) + else if (dm->support_ic_type & (ODM_RTL8721D)) + odm_set_bb_reg(dm, R_0xf70, 0x03c00000, + dfs->pwdb_th_cur); + #endif + else + odm_set_bb_reg(dm, R_0x918, 0x00001f00, + dfs->pwdb_th_cur); + } + dfs->igi_pre = dfs->igi_cur; + + phydm_dfs_dynamic_setting(dm); + #if (RTL8814A_SUPPORT || RTL8822B_SUPPORT || RTL8821C_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + phydm_dfs_histogram_radar_distinguish(dm); + #endif + radar_detected = phydm_radar_detect_dm_check(dm); + + if (radar_detected) { + PHYDM_DBG(dm, DBG_DFS, + "Radar detect: %d\n", radar_detected); + phydm_radar_detect_reset(dm); + if (dfs->dbg_mode == 1) { + PHYDM_DBG(dm, DBG_DFS, + "Radar is detected in DFS dbg mode.\n"); + radar_detected = 0; + } + } + + if (dfs->sw_trigger_mode) { + radar_detected = 1; + PHYDM_DBG(dm, DBG_DFS, + "Radar is detected in DFS SW trigger mode.\n"); + } + + return radar_detected; +} + +void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + char help[] = "-h"; + u32 argv[5] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} pri_hist_th = %d\n", dfs->pri_hist_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} pri_sum_g1_th = %d\n", dfs->pri_sum_g1_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} pri_sum_g5_th = %d\n", dfs->pri_sum_g5_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} pri_sum_g1_fcc_th = %d\n", + dfs->pri_sum_g1_fcc_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} pri_sum_g3_fcc_th = %d\n", + dfs->pri_sum_g3_fcc_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{5} pri_sum_safe_fcc_th = %d\n", + dfs->pri_sum_safe_fcc_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{6} pri_sum_type4_th = %d\n", dfs->pri_sum_type4_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{7} pri_sum_type6_th = %d\n", dfs->pri_sum_type6_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{8} pri_sum_safe_th = %d\n", dfs->pri_sum_safe_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{9} pri_sum_g5_under_g1_th = %d\n", + dfs->pri_sum_g5_under_g1_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{10} pri_pw_diff_th = %d\n", dfs->pri_pw_diff_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{11} pri_pw_diff_fcc_th = %d\n", + dfs->pri_pw_diff_fcc_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{12} pri_pw_diff_fcc_idle_th = %d\n", + dfs->pri_pw_diff_fcc_idle_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{13} pri_pw_diff_w53_th = %d\n", + dfs->pri_pw_diff_w53_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{14} pri_type1_low_fcc_th = %d\n", + dfs->pri_type1_low_fcc_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{15} pri_type1_upp_fcc_th = %d\n", + dfs->pri_type1_upp_fcc_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{16} pri_type1_cen_fcc_th = %d\n", + dfs->pri_type1_cen_fcc_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{17} pw_g0_th = %d\n", dfs->pw_g0_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{18} pw_long_lower_20m_th = %d\n", + dfs->pw_long_lower_20m_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{19} pw_long_lower_th = %d\n", + dfs->pw_long_lower_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{20} pri_long_upper_th = %d\n", + dfs->pri_long_upper_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{21} pw_long_sum_upper_th = %d\n", + dfs->pw_long_sum_upper_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{22} pw_std_th = %d\n", dfs->pw_std_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{23} pw_std_idle_th = %d\n", dfs->pw_std_idle_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{24} pri_std_th = %d\n", dfs->pri_std_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{25} pri_std_idle_th = %d\n", dfs->pri_std_idle_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{26} type4_pw_max_cnt = %d\n", dfs->type4_pw_max_cnt); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{27} type4_safe_pri_sum_th = %d\n", + dfs->type4_safe_pri_sum_th); + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &argv[0]); + + for (i = 1; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &argv[i]); + } + if (argv[0] == 0) { + dfs->pri_hist_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_hist_th = %d\n", + dfs->pri_hist_th); + } else if (argv[0] == 1) { + dfs->pri_sum_g1_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_g1_th = %d\n", + dfs->pri_sum_g1_th); + } else if (argv[0] == 2) { + dfs->pri_sum_g5_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_g5_th = %d\n", + dfs->pri_sum_g5_th); + } else if (argv[0] == 3) { + dfs->pri_sum_g1_fcc_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_g1_fcc_th = %d\n", + dfs->pri_sum_g1_fcc_th); + } else if (argv[0] == 4) { + dfs->pri_sum_g3_fcc_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_g3_fcc_th = %d\n", + dfs->pri_sum_g3_fcc_th); + } else if (argv[0] == 5) { + dfs->pri_sum_safe_fcc_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_safe_fcc_th = %d\n", + dfs->pri_sum_safe_fcc_th); + } else if (argv[0] == 6) { + dfs->pri_sum_type4_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_type4_th = %d\n", + dfs->pri_sum_type4_th); + } else if (argv[0] == 7) { + dfs->pri_sum_type6_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_type6_th = %d\n", + dfs->pri_sum_type6_th); + } else if (argv[0] == 8) { + dfs->pri_sum_safe_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_safe_th = %d\n", + dfs->pri_sum_safe_th); + } else if (argv[0] == 9) { + dfs->pri_sum_g5_under_g1_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_sum_g5_under_g1_th = %d\n", + dfs->pri_sum_g5_under_g1_th); + } else if (argv[0] == 10) { + dfs->pri_pw_diff_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_pw_diff_th = %d\n", + dfs->pri_pw_diff_th); + } else if (argv[0] == 11) { + dfs->pri_pw_diff_fcc_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_pw_diff_fcc_th = %d\n", + dfs->pri_pw_diff_fcc_th); + } else if (argv[0] == 12) { + dfs->pri_pw_diff_fcc_idle_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_pw_diff_fcc_idle_th = %d\n", + dfs->pri_pw_diff_fcc_idle_th); + } else if (argv[0] == 13) { + dfs->pri_pw_diff_w53_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_pw_diff_w53_th = %d\n", + dfs->pri_pw_diff_w53_th); + } else if (argv[0] == 14) { + dfs->pri_type1_low_fcc_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_type1_low_fcc_th = %d\n", + dfs->pri_type1_low_fcc_th); + } else if (argv[0] == 15) { + dfs->pri_type1_upp_fcc_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_type1_upp_fcc_th = %d\n", + dfs->pri_type1_upp_fcc_th); + } else if (argv[0] == 16) { + dfs->pri_type1_cen_fcc_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_type1_cen_fcc_th = %d\n", + dfs->pri_type1_cen_fcc_th); + } else if (argv[0] == 17) { + dfs->pw_g0_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pw_g0_th = %d\n", + dfs->pw_g0_th); + } else if (argv[0] == 18) { + dfs->pw_long_lower_20m_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pw_long_lower_20m_th = %d\n", + dfs->pw_long_lower_20m_th); + } else if (argv[0] == 19) { + dfs->pw_long_lower_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pw_long_lower_th = %d\n", + dfs->pw_long_lower_th); + } else if (argv[0] == 20) { + dfs->pri_long_upper_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_long_upper_th = %d\n", + dfs->pri_long_upper_th); + } else if (argv[0] == 21) { + dfs->pw_long_sum_upper_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pw_long_sum_upper_th = %d\n", + dfs->pw_long_sum_upper_th); + } else if (argv[0] == 22) { + dfs->pw_std_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pw_std_th = %d\n", + dfs->pw_std_th); + } else if (argv[0] == 23) { + dfs->pw_std_idle_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pw_std_idle_th = %d\n", + dfs->pw_std_idle_th); + } else if (argv[0] == 24) { + dfs->pri_std_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_std_th = %d\n", + dfs->pri_std_th); + } else if (argv[0] == 25) { + dfs->pri_std_idle_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "pri_std_idle_th = %d\n", + dfs->pri_std_idle_th); + } else if (argv[0] == 26) { + dfs->type4_pw_max_cnt = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "type4_pw_max_cnt = %d\n", + dfs->type4_pw_max_cnt); + } else if (argv[0] == 27) { + dfs->type4_safe_pri_sum_th = (u8)argv[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "type4_safe_pri_sum_th = %d\n", + dfs->type4_safe_pri_sum_th); + } + } + *_used = used; + *_out_len = out_len; +} + +void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + u32 used = *_used; + u32 out_len = *_out_len; + u32 argv[10] = {0}; + u8 i, input_idx = 0; + + for (i = 0; i < 7; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &argv[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + dfs->dbg_mode = (boolean)argv[0]; + dfs->sw_trigger_mode = (boolean)argv[1]; + dfs->force_TP_mode = (boolean)argv[2]; + dfs->det_print = (boolean)argv[3]; + dfs->det_print2 = (boolean)argv[4]; + dfs->print_hist_rpt = (boolean)argv[5]; + dfs->hist_cond_on = (boolean)argv[6]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "dbg_mode: %d, sw_trigger_mode: %d, force_TP_mode: %d, det_print: %d,det_print2: %d, print_hist_rpt: %d, hist_cond_on: %d\n", + dfs->dbg_mode, dfs->sw_trigger_mode, dfs->force_TP_mode, + dfs->det_print, dfs->det_print2, dfs->print_hist_rpt, + dfs->hist_cond_on); +} + +u8 phydm_dfs_polling_time(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _DFS_STATISTICS *dfs = &dm->dfs; + + if (dm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)) + dfs->dfs_polling_time = 40; + else + dfs->dfs_polling_time = 100; + + return dfs->dfs_polling_time; +} + +#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */ + +boolean +phydm_is_dfs_band(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (((*dm->channel >= 52) && (*dm->channel <= 64)) || + ((*dm->channel >= 100) && (*dm->channel <= 144))) + return true; + else + return false; +} + +boolean +phydm_dfs_master_enabled(void *dm_void) +{ +#ifdef CONFIG_PHYDM_DFS_MASTER + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean ret_val = false; + + if (dm->dfs_master_enabled) /*pointer protection*/ + ret_val = *dm->dfs_master_enabled ? true : false; + + return ret_val; +#else + return false; +#endif +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /* @Clear Radar Counter and Radar flag */ + odm_set_bb_reg(dm, R_0xa40, BIT(15), 0); + odm_set_bb_reg(dm, R_0xa40, BIT(15), 1); + + /* RT_TRACE(COMP_DFS, DBG_LOUD, ("[DFS], After reset radar counter, 0xcf8 = 0x%x, 0xcf4 = 0x%x\n", */ + /* PHY_QueryBBReg(Adapter, 0xcf8, bMaskDWord), */ + /* PHY_QueryBBReg(Adapter, 0xcf4, bMaskDWord))); */ +} +#endif +#endif diff --git a/hal/phydm/phydm_dfs.h b/hal/phydm/phydm_dfs.h new file mode 100644 index 0000000..fabc640 --- /dev/null +++ b/hal/phydm/phydm_dfs.h @@ -0,0 +1,191 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_DFS_H__ +#define __PHYDM_DFS_H__ + +#define DFS_VERSION "1.1" + +/*@ + * ============================================================ + * Definition + * ============================================================ + */ + +/*@ + * ============================================================ + * 1 structure + * ============================================================ + */ + +struct _DFS_STATISTICS { + u8 mask_idx; + u8 igi_cur; + u8 igi_pre; + u8 st_l2h_cur; + u16 fa_count_pre; + u16 fa_inc_hist[5]; + u16 short_pulse_cnt_pre; + u16 long_pulse_cnt_pre; + u8 pwdb_th; + u8 pwdb_th_cur; + u8 pwdb_scalar_factor; + u8 peak_th; + u8 short_pulse_cnt_th; + u8 long_pulse_cnt_th; + u8 peak_window; + u8 three_peak_opt; + u8 three_peak_th2; + u8 fa_mask_th; + u8 st_l2h_max; + u8 st_l2h_min; + u8 dfs_polling_time; + u8 mask_hist_checked : 3; + boolean pulse_flag_hist[5]; + boolean pulse_type_hist[5]; + boolean radar_det_mask_hist[5]; + boolean idle_mode; + boolean force_TP_mode; + boolean dbg_mode; + boolean sw_trigger_mode; + boolean det_print; + boolean det_print2; + boolean radar_type; + boolean print_hist_rpt; + boolean hist_cond_on; + /*@dfs histogram*/ + boolean pri_cond1; + boolean pri_cond2; + boolean pri_cond3; + boolean pri_cond4; + boolean pri_cond5; + boolean pw_cond1; + boolean pw_cond2; + boolean pw_cond3; + boolean pri_type3_4_cond1; /*@for ETSI*/ + boolean pri_type3_4_cond2; /*@for ETSI*/ + boolean pw_long_cond1; /*@for long radar*/ + boolean pw_long_cond2; /*@for long radar*/ + boolean pri_long_cond1; /*@for long radar*/ + boolean pw_flag; + boolean pri_flag; + boolean pri_type3_4_flag; /*@for ETSI*/ + boolean long_radar_flag; + u8 pri_hold_sum[6]; + u8 pw_hold_sum[6]; + u8 pri_long_hold_sum[6]; + u8 pw_long_hold_sum[6]; + u8 hist_idx; + u8 hist_long_idx; + u8 pw_hold[4][6]; + u8 pri_hold[4][6]; + u8 pw_std; /*@The std(var) of reasonable num of pw group*/ + u8 pri_std;/*@The std(var) of reasonable num of pri group*/ + /*@dfs histogram threshold*/ + u8 pri_hist_th : 3; + u8 pri_sum_g1_th : 4; + u8 pri_sum_g5_th : 4; + u8 pri_sum_g1_fcc_th : 3; + u8 pri_sum_g3_fcc_th : 3; + u8 pri_sum_safe_fcc_th : 7; + u8 pri_sum_type4_th : 5; + u8 pri_sum_type6_th : 5; + u8 pri_sum_safe_th : 6; + u8 pri_sum_g5_under_g1_th : 3; + u8 pri_pw_diff_th : 3; + u8 pri_pw_diff_fcc_th : 4; + u8 pri_pw_diff_fcc_idle_th : 2; + u8 pri_pw_diff_w53_th : 4; + u8 pri_type1_low_fcc_th : 7; + u8 pri_type1_upp_fcc_th : 7; + u8 pri_type1_cen_fcc_th : 7; + u8 pw_g0_th : 4; + u8 pw_long_lower_20m_th : 4; + u8 pw_long_lower_th : 3; + u8 pri_long_upper_th : 6; + u8 pw_long_sum_upper_th : 7; + u8 pw_std_th : 4; + u8 pw_std_idle_th : 4; + u8 pri_std_th : 4; + u8 pri_std_idle_th : 4; + u8 type4_pw_max_cnt : 4; + u8 type4_safe_pri_sum_th : 3; +}; + +/*@ + * ============================================================ + * enumeration + * ============================================================ + */ + +enum phydm_dfs_region_domain { + PHYDM_DFS_DOMAIN_UNKNOWN = 0, + PHYDM_DFS_DOMAIN_FCC = 1, + PHYDM_DFS_DOMAIN_MKK = 2, + PHYDM_DFS_DOMAIN_ETSI = 3, +}; + +/*@ + * ============================================================ + * function prototype + * ============================================================ + */ +#if defined(CONFIG_PHYDM_DFS_MASTER) +void phydm_radar_detect_reset(void *dm_void); +void phydm_radar_detect_disable(void *dm_void); +void phydm_radar_detect_enable(void *dm_void); +boolean phydm_radar_detect(void *dm_void); +void phydm_dfs_histogram_radar_distinguish(void *dm_void); +boolean phydm_dfs_hist_log(void *dm_void, u8 index); +void phydm_dfs_parameter_init(void *dm_void); +void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +u8 phydm_dfs_polling_time(void *dm_void); +#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */ + +boolean +phydm_dfs_is_meteorology_channel(void *dm_void); + +void +phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path); + +void +phydm_dfs_segment_flag_reset(void *dm_void); + +boolean +phydm_is_dfs_band(void *dm_void); + +boolean +phydm_dfs_master_enabled(void *dm_void); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void); +#endif +#endif + +#endif /*@#ifndef __PHYDM_DFS_H__ */ diff --git a/hal/phydm/phydm_dig.c b/hal/phydm/phydm_dig.c new file mode 100644 index 0000000..59637b3 --- /dev/null +++ b/hal/phydm/phydm_dig.c @@ -0,0 +1,3654 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + * ************************************************************ + */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CFG_DIG_DAMPING_CHK +void phydm_dig_recorder_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; + + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + odm_memory_set(dm, &dig_rc->igi_bitmap, 0, + sizeof(struct phydm_dig_recorder_strcut)); +} + +void phydm_dig_recorder(void *dm_void, u8 igi_curr, + u32 fa_metrics) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; + u8 igi_pre = dig_rc->igi_history[0]; + u8 igi_up = 0; + + if (!dm->is_linked) + return; + + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + if (dm->first_connect) { + phydm_dig_recorder_reset(dm); + dig_rc->igi_history[0] = igi_curr; + dig_rc->fa_history[0] = fa_metrics; + return; + } + + if (igi_curr % 2) + igi_curr--; + + igi_pre = dig_rc->igi_history[0]; + igi_up = (igi_curr > igi_pre) ? 1 : 0; + dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up; + + dig_rc->igi_history[3] = dig_rc->igi_history[2]; + dig_rc->igi_history[2] = dig_rc->igi_history[1]; + dig_rc->igi_history[1] = dig_rc->igi_history[0]; + dig_rc->igi_history[0] = igi_curr; + + dig_rc->fa_history[3] = dig_rc->fa_history[2]; + dig_rc->fa_history[2] = dig_rc->fa_history[1]; + dig_rc->fa_history[1] = dig_rc->fa_history[0]; + dig_rc->fa_history[0] = fa_metrics; + + PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n", + dig_rc->igi_history[3], dig_rc->igi_history[2], + dig_rc->igi_history[1], dig_rc->igi_history[0]); + PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n", + dig_rc->fa_history[3], dig_rc->fa_history[2], + dig_rc->fa_history[1], dig_rc->fa_history[0]); + PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n", + (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3), + (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2), + (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1), + (u8)(dig_rc->igi_bitmap & BIT(0)), + dig_rc->igi_bitmap); +} + +void phydm_dig_damping_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; + u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf; + u8 diff1 = 0, diff2 = 0; + u32 fa_low_th = dig_t->fa_th[0]; + u32 fa_high_th = dig_t->fa_th[1]; + u32 fa_high_th2 = dig_t->fa_th[2]; + u8 fa_pattern_match = 0; + u32 time_tmp = 0; + + if (!dm->is_linked) + return; + + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + /*@== Release Damping ================================================*/ + if (dig_rc->damping_limit_en) { + PHYDM_DBG(dm, DBG_DIG, + "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n", + dig_rc->limit_time, dm->phydm_sys_up_time); + + time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD; + + if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 || + time_tmp < dm->phydm_sys_up_time) { + dig_rc->damping_limit_en = 0; + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n", + dm->rssi_min, dig_rc->limit_rssi); + } + return; + } + + /*@== Damping Pattern Check===========================================*/ + PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th); + + switch (igi_bitmap_4bit) { + case 0x5: + /*@ 4b'0101 + * IGI:[3]down(0x24)->[2]up(0x26)->[1]down(0x24)->[0]up(0x26)->[new](Lock @ 0x26) + * FA: [3] >high1 ->[2] [1] >high1 ->[0] [new] [2]up(0x28)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28) + * FA: [3] >high2 ->[2] [1] >high2 ->[0] [new] igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[2] > dig_rc->igi_history[3]) + diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] > fa_high_th && + dig_rc->fa_history[2] < fa_low_th && + dig_rc->fa_history[3] > fa_high_th) { + /*@Check each fa element*/ + fa_pattern_match = 1; + } + break; + case 0x9: + /*@ 4b'1001 + * IGI:[3]up(0x28)->[2]down(0x26)->[1]down(0x24)->[0]up(0x28)->[new](Lock @ 0x28) + * FA: [3] [2] [1] >high2 ->[0] [new] igi_history[0] > dig_rc->igi_history[1]) + diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1]; + + if (dig_rc->igi_history[2] < dig_rc->igi_history[3]) + diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2]; + + if (dig_rc->fa_history[0] < fa_low_th && + dig_rc->fa_history[1] > fa_high_th2 && + dig_rc->fa_history[2] < fa_low_th && + dig_rc->fa_history[3] < fa_low_th) { + /*@Check each fa element*/ + fa_pattern_match = 1; + } + break; + default: + break; + } + + if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) { + dig_rc->damping_limit_en = 1; + dig_rc->damping_limit_val = dig_rc->igi_history[0]; + dig_rc->limit_time = dm->phydm_sys_up_time; + dig_rc->limit_rssi = dm->rssi_min; + + PHYDM_DBG(dm, DBG_DIG, + "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n", + dig_rc->damping_limit_val, + dig_rc->limit_time, dig_rc->limit_rssi); + } + + PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en); +} +#endif + +void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 i = 0; + + dig_t->dm_dig_fa_th1 = DM_DIG_FA_TH1; + + if (dig_t->is_dbg_fa_th) { + PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n"); + } else if (dm->is_linked) { + if (dm->rssi_min < 20) { /*@[PHYDM-252]*/ + dig_t->fa_th[0] = 500; + dig_t->fa_th[1] = 750; + dig_t->fa_th[2] = 1000; + } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/ + (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/ + dig_t->fa_th[0] = 125; + dig_t->fa_th[1] = 250; + dig_t->fa_th[2] = 500; + } else { + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 500; + dig_t->fa_th[2] = 750; + } + } else { + if (is_dfs_band) { /* @For DFS band and no link */ + + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 1000; + dig_t->fa_th[2] = 2000; + } else { + dig_t->fa_th[0] = 2000; + dig_t->fa_th[1] = 4000; + dig_t->fa_th[2] = 5000; + } + } + + if ((dig_t->fa_source >= 1) && (dig_t->fa_source <= 3)) { + for (i = 0; i < 3; i++) + dig_t->fa_th[i] *= OFDM_FA_EXP_DURATION; + + dig_t->dm_dig_fa_th1 *= OFDM_FA_EXP_DURATION; + } + + PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0], + dig_t->fa_th[1], dig_t->fa_th[2]); +} + +void phydm_set_big_jump_step(void *dm_void, u8 curr_igi) +{ +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90}; + u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx]; + u8 i; + + if (dig_t->enable_adjust_big_jump == 0) + return; + + for (i = 0; i <= dig_t->big_jump_step1; i++) { + if ((curr_igi + step1[i]) > big_jump_lmt) { + if (i != 0) + i = i - 1; + break; + } else if (i == dig_t->big_jump_step1) { + break; + } + } + if (dm->support_ic_type & ODM_RTL8822B) + odm_set_bb_reg(dm, R_0x8c8, 0xe, i); + else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i); + + PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i, + dig_t->big_jump_step1, big_jump_lmt); +#endif +} + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); + + /* Set IGI value */ + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi); + odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi); + } + #endif +} + +u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); + + /* Set IGI value */ + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return (u8)val; + + if (path == BB_PATH_A) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC); +#if (defined(PHYDM_COMPILE_ABOVE_2SS)) + else if (path == BB_PATH_B) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3); +#endif + +#if (defined(PHYDM_COMPILE_ABOVE_3SS)) + else if (path == BB_PATH_C) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3); +#endif + +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + else if (path == BB_PATH_D) + val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3); +#endif + return (u8)val; +} + +void phydm_fa_cnt_statistics_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 ret_value = 0; + u32 cck_enable = 0; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + ret_value = odm_get_bb_reg(dm, R_0x2de4, MASKDWORD); + fa_t->cnt_cck_txen = (ret_value & 0xffff); + fa_t->cnt_cck_txon = ((ret_value & 0xffff0000) >> 16); + ret_value = odm_get_bb_reg(dm, R_0x2de0, MASKDWORD); + fa_t->cnt_ofdm_txen = (ret_value & 0xffff); + fa_t->cnt_ofdm_txon = ((ret_value & 0xffff0000) >> 16); + + ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD); + fa_t->cnt_fast_fsync = ret_value & 0xffff; + fa_t->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD); + fa_t->cnt_parity_fail = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD); + fa_t->cnt_rate_illegal = ret_value & 0xffff; + fa_t->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD); + fa_t->cnt_mcs_fail = ret_value & 0xffff; + + /* read CCK CRC32 counter */ + if (dm->support_ic_type & ODM_RTL8723F) + ret_value = odm_get_bb_reg(dm, R_0x2aac, MASKDWORD); + else + ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD); + fa_t->cnt_cck_crc32_ok = ret_value & 0xffff; + fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; + + /* read OFDM CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD); + fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff; + fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + + /* read OFDM2 CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c1c, MASKDWORD); + fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff; + fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16; + + /* read HT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD); + fa_t->cnt_ht_crc32_ok = ret_value & 0xffff; + fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + + /* read HT2 CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c18, MASKDWORD); + fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff; + fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16; + + /*for VHT part */ + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8814B)) { + /*read VHT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD); + fa_t->cnt_vht_crc32_ok = ret_value & 0xffff; + fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; + + /*read VHT2 CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c54, MASKDWORD); + fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff; + fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD); + fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD); + fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff; + fa_t->cnt_crc8_fail_vhtb = (ret_value & 0xffff0000) >> 16; + } else { + fa_t->cnt_vht_crc32_error = 0; + fa_t->cnt_vht_crc32_ok = 0; + fa_t->cnt_vht2_crc32_error = 0; + fa_t->cnt_vht2_crc32_ok = 0; + fa_t->cnt_mcs_fail_vht = 0; + fa_t->cnt_crc8_fail_vhta = 0; + fa_t->cnt_crc8_fail_vhtb = 0; + } + + /* @calculate OFDM FA counter instead of reading brk_cnt*/ + fa_t->cnt_ofdm_fail = fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal + + fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail + + fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail + + fa_t->cnt_mcs_fail_vht + fa_t->cnt_crc8_fail_vhta; + + /* Read CCK FA counter */ + if (dm->support_ic_type & ODM_RTL8723F){ + ret_value= odm_get_bb_reg(dm, R_0x2aa8, MASKLWORD); + fa_t->cnt_cck_fail=(ret_value&0xffff)+((ret_value&0xffff0000)>>16); + } + else + fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD); + + /* read CCK/OFDM CCA counter */ + ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD); + fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16); + if (dm->support_ic_type & ODM_RTL8723F) + ret_value = odm_get_bb_reg(dm, R_0x2aa0, MASKDWORD); + fa_t->cnt_cck_cca = ret_value & 0xffff; + + /* @CCK RxIQ weighting = 1 => 0x1a14[9:8]=0x0 */ + if (dm->support_ic_type & ODM_RTL8723F) + cck_enable = odm_get_bb_reg(dm, R_0x2a24, BIT(13)); + else + cck_enable = odm_get_bb_reg(dm, R_0x1a14, 0x300); + + if (cck_enable == 0x0) { /* @if(*dm->band_type == ODM_BAND_2_4G) */ + fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail; + fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca; + } else { + fa_t->cnt_all = fa_t->cnt_ofdm_fail; + fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca; + } +} + +#endif + +void phydm_write_dig_reg_c50(void *dm_void, u8 igi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); + + odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi); + + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) + odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi); + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) { + odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi); + odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi); + } + #endif +} + +void phydm_write_dig_reg(void *dm_void, u8 igi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 rf_gain = 0; + + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_write_dig_reg_jgr3(dm, igi); + else + #endif + phydm_write_dig_reg_c50(dm, igi); + + #if (RTL8721D_SUPPORT) + if (dm->invalid_mode) { + if (igi <= 0x10) + rf_gain = 0xfa; + else if (igi <= 0x40) + rf_gain = 0xe3 + 0x20 - (igi >> 1); + else if (igi <= 0x50) + rf_gain = 0xcb - (igi >> 1); + else if (igi <= 0x5e) + rf_gain = 0x92 - (igi >> 1); + else if (igi <= 0x64) + rf_gain = 0x74 - (igi >> 1); + else + rf_gain = (0x3d > (igi >> 1)) ? (0x3d - (igi >> 1)) : 0; + odm_set_bb_reg(dm, R_0x850, 0x1fe0, rf_gain); + } + #endif + + if (igi == dig_t->cur_ig_value) + dig_t->igi_trend = DIG_STABLE; + else if (igi > dig_t->cur_ig_value) + dig_t->igi_trend = DIG_INCREASING; + else + dig_t->igi_trend = DIG_DECREASING; + + PHYDM_DBG(dm, DBG_DIG, "Update IGI:0x%x -> 0x%x\n", + dig_t->cur_ig_value, igi); + + dig_t->cur_ig_value = igi; +} + +void odm_write_dig(void *dm_void, u8 new_igi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); + + /* @1 Check IGI by upper bound */ + if (adaptivity->igi_lmt_en && + new_igi > adaptivity->adapt_igi_up && dm->is_linked) { + new_igi = adaptivity->adapt_igi_up; + + PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n", + new_igi); + } + + #if (RTL8192F_SUPPORT) + if ((dm->support_ic_type & ODM_RTL8192F) && + dm->cut_version == ODM_CUT_A && + new_igi > 0x38) { + new_igi = 0x38; + PHYDM_DBG(dm, DBG_DIG, + "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi); + } + #endif + + if (dig_t->cur_ig_value != new_igi) { + #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + /* @Modify big jump step for 8822B and 8197F */ + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) + phydm_set_big_jump_step(dm, new_igi); + #endif + + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) + /* Set IGI value of CCK for new CCK AGC */ + if (dm->cck_new_agc && + (dm->support_ic_type & PHYSTS_2ND_TYPE_IC)) + odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1)); + #endif + + /*@Add by YuChen for USB IO too slow issue*/ + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) { + if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) { + if (new_igi < dig_t->cur_ig_value || + dm->is_pause_dig) { + dig_t->cur_ig_value = new_igi; + phydm_adaptivity(dm); + } + } else { + if (new_igi > dig_t->cur_ig_value) { + dig_t->cur_ig_value = new_igi; + phydm_adaptivity(dm); + } + } + } + phydm_write_dig_reg(dm, new_igi); + } else { + dig_t->igi_trend = DIG_STABLE; + } + + PHYDM_DBG(dm, DBG_DIG, "[%s]New_igi=((0x%x))\n\n", + ((dig_t->igi_trend == DIG_STABLE) ? "=" : + ((dig_t->igi_trend == DIG_INCREASING) ? "+" : "-")), + new_igi); +} + +u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + u32 bit_map = ODM_BIT(IGI, dm); + + switch (path) { + case BB_PATH_A: + val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map); + break; + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + case BB_PATH_B: + val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map); + break; + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + case BB_PATH_C: + val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map); + break; + #endif + + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + case BB_PATH_D: + val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map); + break; + #endif + + default: + break; + } + + return (u8)val; +} + +u8 phydm_get_igi(void *dm_void, enum bb_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 val = 0; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + val = phydm_get_igi_reg_val_jgr3(dm, path); + else + #endif + val = phydm_get_igi_reg_val(dm, path); + + return val; +} + +void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n"); + return; + } + + odm_write_dig(dm, (u8)(*val_buf)); +} + +void odm_pause_dig(void *dm_void, enum phydm_pause_type type, + enum phydm_pause_level lv, u8 igi_input) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rpt = false; + u32 igi = (u32)igi_input; + + PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type, + lv, igi); + + switch (type) { + case PHYDM_PAUSE: + case PHYDM_PAUSE_NO_SET: { + dm->is_pause_dig = true; + rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi); + break; + } + + case PHYDM_RESUME: { + rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi); + dm->is_pause_dig = false; + break; + } + default: + PHYDM_DBG(dm, DBG_DIG, "Wrong type\n"); + break; + } + + PHYDM_DBG(dm, DBG_DIG, "DIG pause_result=%d\n", rpt); +} + +boolean +phydm_dig_abort(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; +#endif + + /* support_ability */ + if ((!(dm->support_ability & ODM_BB_FA_CNT)) || + (!(dm->support_ability & ODM_BB_DIG))) { + PHYDM_DBG(dm, DBG_DIG, "[DIG] Not Support\n"); + return true; + } + + if (dm->pause_ability & ODM_BB_DIG) { + PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n", + dm->pause_lv_table.lv_dig); + return true; + } + + if (*dm->is_scan_in_process) { + PHYDM_DBG(dm, DBG_DIG, "Return: Scan in process\n"); + return true; + } + + if (dm->dm_dig_table.fw_dig_enable) { + PHYDM_DBG(dm, DBG_DIG, "Return: FW DIG enable\n"); + return true; + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if OS_WIN_FROM_WIN7(OS_VERSION) + if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) { + PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n"); + return true; + } +#endif +#endif + + return false; +} + +#ifdef PHYDM_HW_IGI +#ifdef BB_RAM_SUPPORT +void phydm_rd_hwigi_pre_setting(void *dm_void, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u8 igi_ofst = 0x0; + u32 t1, t2, t3 = 0x0; + + igi_ofst = (u8)odm_get_bb_reg(dm, R_0x1e80, MASKBYTE0); + t1 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE1) * 400; + t2 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE2) * 400; + t3 = odm_get_bb_reg(dm, R_0x1e80, MASKBYTE3) * 400; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "igi_offset:0x%x, t1:%d(ns), t2:%d(ns), t3:%d(ns)\n", + igi_ofst, t1, t2, t3); +} + +void phydm_set_hwigi_pre_setting(void *dm_void, u8 igi_ofst, u8 t1, u8 t2, + u8 t3) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_0x1e80 = 0; + + reg_0x1e80 = igi_ofst + (t1 << 8) + (t2 << 16) + (t3 << 24); + odm_set_bb_reg(dm, R_0x1e80, MASKDWORD, reg_0x1e80); +} + +void phydm_rd_hwigi_table(void *dm_void, u8 macid, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + boolean hwigi_en = false; + u8 hwigi = 0x0; + u8 hwigi_rx_offset = 0x0; + u32 reg_0x1e84 = 0x0; + + reg_0x1e84 |= (macid & 0x3f) << 24; /*macid*/ + reg_0x1e84 |= BIT(31); /*read_en*/ + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84); + + hwigi_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(15)); + hwigi = (u8)odm_get_bb_reg(dm, R_0x2de8, 0x7f00); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, + "(macid:%d) hwigi_en:%d, hwigi:0x%x\n", macid, hwigi_en, + hwigi); + + *_used = used; + *_out_len = out_len; +} + +void phydm_wt_hwigi_table(void *dm_void, u8 macid, boolean hwigi_en, u8 hwigi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL; + u32 reg_0x1e84 = 0; + + if (macid > 63) + macid = 63; + + dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid]; + dm_ram_per_sta->hw_igi_en = hwigi_en; + dm_ram_per_sta->hw_igi = hwigi; + + reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) + + ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) + + (dm_ram_per_sta->tx_pwr_offset1_en << 23) + + ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16); + + reg_0x1e84 |= (hwigi_en << 7) + (hwigi & 0x7f); + reg_0x1e84 |= (macid & 0x3f) << 24;/*macid*/ + reg_0x1e84 |= BIT(30); /*write_en*/ + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /*read_en*/ + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /*disable rd/wt*/ +} + +void phydm_rst_hwigi(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL; + u32 reg_0x1e84 = 0; + u8 i = 0; + + PHYDM_DBG(dm, DBG_DIG, "reset hwigi!\n"); + + for (i = 0; i < 64; i++) { + dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i]; + dm_ram_per_sta->hw_igi_en = false; + dm_ram_per_sta->hw_igi = 0x0; + + reg_0x1e84 = (dm_ram_per_sta->tx_pwr_offset0_en << 15) + + ((dm_ram_per_sta->tx_pwr_offset0 & 0x7f) << 8) + + (dm_ram_per_sta->tx_pwr_offset1_en << 23) + + ((dm_ram_per_sta->tx_pwr_offset1 & 0x7f) << 16); + + reg_0x1e84 |= (i & 0x3f) << 24; + reg_0x1e84 |= BIT(30); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84); + } + + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); +} + +void phydm_hwigi_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl; + u8 igi_ofst = 0x0; + u8 t1 = 0x0; + u8 t2 = 0x0; + u8 t3 = 0x0; + + t1 = 0x55; /*34 us*/ + t3 = 0x55; /*34 us*/ + + bb_ctrl->hwigi_watchdog_en = false; + phydm_set_hwigi_pre_setting(dm, igi_ofst, t1, t2, t3); +} + +void phydm_hwigi(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL; + struct rssi_info *rssi = NULL; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl; + u8 sta_cnt = 0; + u8 i = 0; + u8 hwigi = 0x0; + u8 macid = 0; + u8 macid_cnt = 0; + u64 macid_cur = 0; + u64 macid_diff = 0; + u64 macid_mask = 0; + + if (!(bb_ctrl->hwigi_watchdog_en)) { + return; + } + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + if (sta->mac_id > 63) + macid = 63; + else + macid = sta->mac_id; + + dm_ram_per_sta = &bb_ctrl->pram_sta_ctrl[macid]; + rssi = &sta->rssi_stat; + macid_mask = (u64)BIT(sta->mac_id); + bb_ctrl->hwigi_macid_is_linked |= macid_mask; + macid_cur |= macid_mask; + PHYDM_DBG(dm, DBG_DIG, + "STA_id=%d, MACID=%d, RSSI=%d, hwigi_en=%d, hwigi=0x%x\n", + i, sta->mac_id, rssi->rssi, + dm_ram_per_sta->hw_igi_en, + dm_ram_per_sta->hw_igi); + + hwigi = MAX_2((u8)(rssi->rssi + 10), + dig_t->cur_ig_value); + + if (hwigi > DIG_MAX_PERFORMANCE_MODE) + hwigi = DIG_MAX_PERFORMANCE_MODE; + else if (hwigi < DIG_MIN_PERFORMANCE) + hwigi = DIG_MIN_PERFORMANCE; + + if (dm_ram_per_sta->hw_igi == hwigi) { + PHYDM_DBG(dm, DBG_DIG, + "hwigi not change!\n"); + } else { + + PHYDM_DBG(dm, DBG_DIG, + "hwigi update: ((0x%x)) -> ((0x%x))\n", + dm_ram_per_sta->hw_igi, hwigi); + + phydm_wt_hwigi_table(dm, sta->mac_id, true, hwigi); + } + + if (sta_cnt == dm->number_linked_client) + break; + } + } + macid_diff = bb_ctrl->hwigi_macid_is_linked ^ macid_cur; + if (macid_diff) + bb_ctrl->hwigi_macid_is_linked &= ~macid_diff; + while (macid_diff) { + if (macid_diff & 0x1) + phydm_wt_hwigi_table(dm, macid_cnt, false, 0x0); + macid_cnt++; + macid_diff >>= 1; + } +} + +void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl; + char help[] = "-h"; + u32 used = *_used; + u32 out_len = *_out_len; + u32 var1[7] = {0}; + u8 i = 0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Disable/Enable watchdog : {0/1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set hwigi pre-setting: {2} {IGI offset} {T1(after data tx)} {T2(after Rx)} {T3(after rsp tx)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set hwigi table: {3} {en} {value} {macid}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Read hwigi : {4} {macid(0~63), 255:all}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Reset all hwigi : {5}\n"); + } else { + for (i = 0; i < 7; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + switch (var1[0]) { + case 0: + case 1: + bb_ctrl->hwigi_watchdog_en = (var1[0]) ? true : false; + break; + case 2: + phydm_set_hwigi_pre_setting(dm, (u8)var1[1], + (u8)var1[2], (u8)var1[3], + (u8)var1[4]); + break; + case 3: + phydm_wt_hwigi_table(dm, (u8)var1[3], (boolean)var1[1], + (boolean)var1[2]); + break; + case 4: + phydm_rd_hwigi_pre_setting(dm, &used, output, &out_len); + if ((u8)var1[1] == 0xff) + for (i = 0; i < 64; i++) + phydm_rd_hwigi_table(dm, i, &used, + output, &out_len); + else + phydm_rd_hwigi_table(dm, (u8)var1[1], &used, + output, &out_len); + break; + case 5: + phydm_rst_hwigi(dm); + break; + } + } + *_used = used; + *_out_len = out_len; +} +#endif +#endif + +void phydm_dig_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt; +#endif + u32 ret_value = 0; + u8 i; + + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + + dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A); + + dig_t->fa_th[0] = 250; + dig_t->fa_th[1] = 500; + dig_t->fa_th[2] = 750; + dig_t->dm_dig_fa_th1 = DM_DIG_FA_TH1; + dig_t->is_dbg_fa_th = false; + dig_t->igi_dyn_up_hit = false; + dig_t->fw_dig_enable = false; + dig_t->fa_source = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + /* @For RTL8881A */ + false_alm_cnt->cnt_ofdm_fail_pre = 0; +#endif + + dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE; + dig_t->rx_gain_range_min = dig_t->cur_ig_value; + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) { + dig_t->enable_adjust_big_jump = 1; + + if (dm->support_ic_type & ODM_RTL8822B) + ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD); + else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD); + + dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1; + dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4; + dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6; + + for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) { + if (dig_t->big_jump_lmt[i] == 0) + dig_t->big_jump_lmt[i] = 0x64; + /* Set -10dBm as default value */ + } + } +#endif + +#ifdef PHYDM_TDMA_DIG_SUPPORT + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + dm->original_dig_restore = true; + dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES; + dm->tdma_dig_timer_ms = DIG_TIMER_MS; + #endif + dig_t->tdma_force_l_igi = 0xff; + dig_t->tdma_force_h_igi = 0xff; +#endif +#ifdef CFG_DIG_DAMPING_CHK + phydm_dig_recorder_reset(dm); + dig_t->dig_dl_en = 1; +#endif + +#ifdef PHYDM_HW_IGI + phydm_hwigi_init(dm); +#endif +} +void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_adaptivity_struct *adapt = &dm->adaptivity; + + if (is_dfs_band) { + if (*dm->band_width == CHANNEL_WIDTH_20){ + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){ + if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1) + dig_t->dm_dig_min = DIG_MIN_DFS + 2; + else + dig_t->dm_dig_min = DIG_MIN_DFS; + } + else + dig_t->dm_dig_min = DIG_MIN_DFS; + } + else + dig_t->dm_dig_min = DIG_MIN_DFS; + + dig_t->dig_max_of_min = DIG_MIN_DFS; + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + } else if (!dm->is_linked) { + dig_t->dm_dig_max = DIG_MAX_COVERAGR; + dig_t->dm_dig_min = DIG_MIN_COVERAGE; + } else { + if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) { + /*service > 2 devices*/ + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + #if (DIG_HW == 1) + dig_t->dig_max_of_min = DIG_MIN_COVERAGE; + #else + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + #endif + } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) { + /*service 1 devices*/ + if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && + dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + /*dig_max shouldn't be too high because of adaptivity*/ + dig_t->dm_dig_max = + MIN_2((adapt->th_l2h + 40), + DIG_MAX_PERFORMANCE_MODE); + else + dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE; + + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE; + } + + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)) + dig_t->dm_dig_min = 0x1c; + else if (dm->support_ic_type & ODM_RTL8197F) + dig_t->dm_dig_min = 0x1e; /*@For HW setting*/ + else + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; + } + + PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n", + dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min); +} + +void phydm_dig_dym_boundary_decision(struct dm_struct *dm, boolean is_dfs_band) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; +#endif + u8 offset = 15, tmp_max = 0; + u8 max_of_rssi_min = 0; + + PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__); + + if (!dm->is_linked) { + /*@if no link, always stay at lower bound*/ + dig_t->rx_gain_range_max = dig_t->dig_max_of_min; + dig_t->rx_gain_range_min = dig_t->dm_dig_min; + + PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); + return; + } + + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset); + + /* @DIG lower bound */ + if (is_dfs_band) + dig_t->rx_gain_range_min = dig_t->dm_dig_min; + else if (dm->rssi_min > dig_t->dig_max_of_min) + dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + else if (dm->rssi_min < dig_t->dm_dig_min) + dig_t->rx_gain_range_min = dig_t->dm_dig_min; + else + dig_t->rx_gain_range_min = dm->rssi_min; + +#ifdef CFG_DIG_DAMPING_CHK + /*@Limit Dyn min by damping*/ + if (dig_t->dig_dl_en && + dig_rc->damping_limit_en && + dig_t->rx_gain_range_min < dig_rc->damping_limit_val) { + PHYDM_DBG(dm, DBG_DIG, + "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n", + dig_t->rx_gain_range_min, dig_rc->damping_limit_val); + + dig_t->rx_gain_range_min = dig_rc->damping_limit_val; + } +#endif + + /* @DIG upper bound */ + tmp_max = dig_t->rx_gain_range_min + offset; + if (dig_t->rx_gain_range_min != dm->rssi_min) { + max_of_rssi_min = dm->rssi_min + offset; + if (tmp_max > max_of_rssi_min) + tmp_max = max_of_rssi_min; + } + + if (tmp_max > dig_t->dm_dig_max) + dig_t->rx_gain_range_max = dig_t->dm_dig_max; + else if (tmp_max < dig_t->dm_dig_min) + dig_t->rx_gain_range_max = dig_t->dm_dig_min; + else + dig_t->rx_gain_range_max = tmp_max; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + /* @1 Force Lower Bound for AntDiv */ + if (!dm->is_one_entry_only && + (dm->support_ability & ODM_BB_ANT_DIV) && + (dm->ant_div_type == CG_TRX_HW_ANTDIV || + dm->ant_div_type == CG_TRX_SMART_ANTDIV)) { + if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min) + dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + else + dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max; + + PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n", + dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max); + } + #endif + + PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); +} + +void phydm_dig_abnormal_case(struct dm_struct *dm) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + /* @Abnormal lower bound case */ + if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max) + dig_t->rx_gain_range_min = dig_t->rx_gain_range_max; + + PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n", + dig_t->rx_gain_range_max, dig_t->rx_gain_range_min); +} + +u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_metrics, + u8 *step_size) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (fa_metrics > dig_t->fa_th[2]) + igi = igi + step_size[0]; + else if (fa_metrics > dig_t->fa_th[1]) + igi = igi + step_size[1]; + else if (fa_metrics < dig_t->fa_th[0]) + igi = igi - step_size[2]; + + return igi; +} + +u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_metrics, + boolean is_dfs_band) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step[3] = {0}; + + if (dm->is_linked) { + if (dm->pre_rssi_min <= dm->rssi_min) { + PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n"); + step[0] = 2; + step[1] = 1; + step[2] = 2; + } else { + step[0] = 4; + step[1] = 2; + step[2] = 2; + } + } else { + step[0] = 2; + step[1] = 1; + step[2] = 2; + } + + PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1], + step[0]); + + if (dm->first_connect) { + if (is_dfs_band) { + if (dm->rssi_min > DIG_MAX_DFS) + igi = DIG_MAX_DFS; + else + igi = dm->rssi_min; + PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n", + dig_t->rx_gain_range_max); + } else { + igi = dig_t->rx_gain_range_min; + } + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (RTL8812A_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812) + odm_config_bb_with_header_file(dm, + CONFIG_BB_AGC_TAB_DIFF); + #endif + #endif + PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi); + } else if (dm->is_linked) { + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n"); + /* @4 Abnormal # beacon case */ + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 && + fa_metrics < dig_t->dm_dig_fa_th1 && dm->bsta_state && + dm->support_ic_type != ODM_RTL8723D && + dm->support_ic_type != ODM_RTL8822C) { + dig_t->rx_gain_range_min = 0x1c; + igi = dig_t->rx_gain_range_min; + PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n", + dm->phy_dbg_info.num_qry_beacon_pkt, igi); + } else { + igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step); + } + #else + igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step); + #endif + } else { + /* @2 Before link */ + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n"); + + if (dm->first_disconnect) { + igi = dig_t->dm_dig_min; + PHYDM_DBG(dm, DBG_DIG, + "First disconnect:foce IGI to lower bound\n"); + } else { + PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n", + igi, fa_metrics); + + igi = phydm_new_igi_by_fa(dm, igi, fa_metrics, step); + } + } + + /*@Check IGI by dyn-upper/lower bound */ + if (igi < dig_t->rx_gain_range_min) + igi = dig_t->rx_gain_range_min; + + if (igi >= dig_t->rx_gain_range_max) { + igi = dig_t->rx_gain_range_max; + dig_t->igi_dyn_up_hit = true; + } else { + dig_t->igi_dyn_up_hit = false; + } + PHYDM_DBG(dm, DBG_DIG, "igi_dyn_up_hit=%d\n", + dig_t->igi_dyn_up_hit); + + PHYDM_DBG(dm, DBG_DIG, "fa_metrics = %d, IGI: 0x%x -> 0x%x\n", + fa_metrics, dig_t->cur_ig_value, igi); + + return igi; +} + +boolean phydm_dig_dfs_mode_en(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean dfs_mode_en = false; + + /* @Modify lower bound for DFS band */ + if (dm->is_dfs_band) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + dfs_mode_en = true; + #else + if (phydm_dfs_master_enabled(dm)) + dfs_mode_en = true; + #endif + PHYDM_DBG(dm, DBG_DIG, "In DFS band\n"); + } + return dfs_mode_en; +} + +void phydm_dig_fa_source(void *dm_void, u8 fa_source, u32 *fa_metrics) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa = &dm->false_alm_cnt; + + switch (fa_source) { + case 1: + *fa_metrics = fa->time_fa_exp; + break; + #ifdef IFS_CLM_SUPPORT + case 2: + if (fa->time_fa_ifs_clm) { + *fa_metrics = fa->time_fa_ifs_clm; + } else { + fa_source = 1; + *fa_metrics = fa->time_fa_exp; + } + break; + #endif + #ifdef FAHM_SUPPORT + case 3: + if (fa->time_fa_fahm) { + *fa_metrics = fa->time_fa_fahm; + } else { + fa_source = 1; + *fa_metrics = fa->time_fa_exp; + } + break; + #endif + default: + break; + } + + PHYDM_DBG(dm, DBG_DIG, + "fa_source:%d, fa_cnt=%d ,time_fa_exp=%d, fa_metrics=%d\n", + fa_source, fa->cnt_all, fa->time_fa_exp, *fa_metrics); +} + +void phydm_dig(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *fa = &dm->false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; +#endif + u8 igi = dig_t->cur_ig_value; + u8 new_igi = 0x20; + u32 fa_metrics = fa->cnt_all; + boolean dfs_mode_en = false; + + PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__); + + #ifdef PHYDM_DCC_ENHANCE + if (dm->dm_dcc_info.dcc_en) { + fa_metrics = fa->cnt_ofdm_fail; /*OFDM FA only*/ + dig_t->fa_source = 0; + } + #endif + + #ifdef PHYDM_TDMA_DIG_SUPPORT + if (!(dm->original_dig_restore)) { + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; + + igi = dig_t->cur_ig_value_tdma; + fa_metrics = falm_cnt_acc->cnt_all_1sec; + dig_t->fa_source = 0; + } + #endif + + if (phydm_dig_abort(dm)) { + dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A); + return; + } + + if (dig_t->fa_source) + phydm_dig_fa_source(dm, dig_t->fa_source, &fa_metrics); + + PHYDM_DBG(dm, DBG_DIG, + "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n", + dm->is_linked, dm->rssi_min, + dm->first_connect, dm->first_disconnect); + + PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n", + (*dm->bb_op_mode ? "Balance" : "Performance")); + + /*@DFS mode enable check*/ + dfs_mode_en = phydm_dig_dfs_mode_en(dm); + +#ifdef CFG_DIG_DAMPING_CHK + /*Record IGI History*/ + phydm_dig_recorder(dm, igi, fa_metrics); + + /*@DIG Damping Check*/ + phydm_dig_damping_chk(dm); +#endif + + /*@Absolute Boundary Decision */ + phydm_dig_abs_boundary_decision(dm, dfs_mode_en); + + /*@Dynamic Boundary Decision*/ + phydm_dig_dym_boundary_decision(dm, dfs_mode_en); + + /*@Abnormal case check*/ + phydm_dig_abnormal_case(dm); + + /*@FA threshold decision */ + phydm_fa_threshold_check(dm, dfs_mode_en); + + /*Select new IGI by FA */ + new_igi = phydm_get_new_igi(dm, igi, fa_metrics, dfs_mode_en); + + /* @1 Update status */ + #ifdef PHYDM_TDMA_DIG_SUPPORT + if (!(dm->original_dig_restore)) { + dig_t->cur_ig_value_tdma = new_igi; + /*@It is possible fa_acc_1sec_tsf >= */ + /*@1sec while tdma_dig_state == 0*/ + if (dig_t->tdma_dig_state != 0) + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + } else + #endif + odm_write_dig(dm, new_igi); +} + +void phydm_dig_lps_32k(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 current_igi = dm->rssi_min; + + odm_write_dig(dm, current_igi); +} + +void phydm_dig_by_rssi_lps(void *dm_void) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT)) + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; + + u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */ + u8 current_igi = dm->rssi_min; + + falm_cnt = &dm->false_alm_cnt; + if (phydm_dig_abort(dm)) + return; + + current_igi = current_igi + RSSI_OFFSET_DIG_LPS; + PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__); + + /* Using FW PS mode to make IGI */ + /* @Adjust by FA in LPS MODE */ + if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS) + current_igi = current_igi + 4; + else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS) + current_igi = current_igi + 2; + else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS) + current_igi = current_igi - 2; + + /* @Lower bound checking */ + + /* RSSI Lower bound check */ + if ((dm->rssi_min - 10) > DIG_MIN_LPS) + rssi_lower = (dm->rssi_min - 10); + else + rssi_lower = DIG_MIN_LPS; + + /* Upper and Lower Bound checking */ + if (current_igi > DIG_MAX_LPS) + current_igi = DIG_MAX_LPS; + else if (current_igi < rssi_lower) + current_igi = rssi_lower; + + PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n", + falm_cnt->cnt_all, dm->rssi_min, current_igi); + odm_write_dig(dm, current_igi); +#endif +} + +void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min) +{ + *min = DIG_MIN_COVERAGE; + *max = DIG_MAX_PERFORMANCE_MODE; +} + +u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 igi = 0; + u8 max = 0; + u8 min = 0; + + igi = rssi + 10; + + phydm_get_dig_coverage(dm, &max, &min); + + if (igi > max) + igi = max; + else if (igi < min) + igi = min; + + return igi; +} + +/* @3============================================================ + * 3 FASLE ALARM CHECK + * 3============================================================ + */ +void phydm_false_alarm_counter_reg_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; +#ifdef PHYDM_TDMA_DIG_SUPPORT + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; +#endif + u32 false_alm_cnt = 0; + +#ifdef PHYDM_TDMA_DIG_SUPPORT + if (!(dm->original_dig_restore)) { + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; + + false_alm_cnt = falm_cnt_acc->cnt_all_1sec; + } else +#endif + { + false_alm_cnt = falm_cnt->cnt_all; + } + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (dm->support_ic_type & ODM_RTL8723F) { + /* @reset CCK FA and CCA counter */ + odm_set_bb_reg(dm, R_0x2a44, BIT(21), 0); + odm_set_bb_reg(dm, R_0x2a44, BIT(21), 1); + } else { + /* @reset CCK FA counter */ + odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0); + odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2); + + /* @reset CCK CCA counter */ + odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2); + } + /* @Disable common rx clk gating => WLANBB-1106*/ + odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 0); + /* @reset OFDM CCA counter, OFDM FA counter*/ + phydm_reset_bb_hw_cnt(dm); + /* @Enable common rx clk gating => WLANBB-1106*/ + odm_set_bb_reg(dm, R_0x1d2c, BIT(31), 1); + } +#endif +#if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /* @reset false alarm counter registers*/ + odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1); + odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0); + odm_set_bb_reg(dm, R_0xd00, BIT(27), 1); + odm_set_bb_reg(dm, R_0xd00, BIT(27), 0); + + /* @update ofdm counter*/ + /* @update page C counter*/ + odm_set_bb_reg(dm, R_0xc00, BIT(31), 0); + /* @update page D counter*/ + odm_set_bb_reg(dm, R_0xd00, BIT(31), 0); + + /* @reset CCK CCA counter*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2); + + /* @reset CCK FA counter*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0); + odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2); + + /* @reset CRC32 counter*/ + odm_set_bb_reg(dm, R_0xf14, BIT(16), 1); + odm_set_bb_reg(dm, R_0xf14, BIT(16), 0); + } +#endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */ + +#if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if (RTL8881A_SUPPORT) + /* @Reset FA counter by enable/disable OFDM */ + if ((dm->support_ic_type == ODM_RTL8881A) && + false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) { + /* reset OFDM */ + odm_set_bb_reg(dm, R_0x808, BIT(29), 0); + odm_set_bb_reg(dm, R_0x808, BIT(29), 1); + false_alm_cnt->cnt_ofdm_fail_pre = 0; + PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n"); + } + #endif /* @#if (RTL8881A_SUPPORT) */ + + /* @reset OFDM FA countner */ + odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1); + odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0); + + /* @reset CCK FA counter */ + odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0); + odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1); + + /* @reset CCA counter */ + phydm_reset_bb_hw_cnt(dm); + } +#endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */ +} + +void phydm_false_alarm_counter_reg_hold(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_RTL8723F) + return; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /* @hold cck counter */ + odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1); + odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1); + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + /*@hold ofdm counter*/ + /*@hold page C counter*/ + odm_set_bb_reg(dm, R_0xc00, BIT(31), 1); + /*@hold page D counter*/ + odm_set_bb_reg(dm, R_0xd00, BIT(31), 1); + + /*@hold cck counter*/ + odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1); + odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1); + } +} + +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_fa_cnt_statistics_n(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 reg = 0; + + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; + + /* @hold ofdm & cck counter */ + phydm_false_alarm_counter_reg_hold(dm); + + reg = odm_get_bb_reg(dm, R_0x9d0, MASKDWORD); + fa_t->cnt_cck_txon = (reg & 0xffff); + fa_t->cnt_cck_txen = ((reg & 0xffff0000) >> 16); + reg = odm_get_bb_reg(dm, R_0x9cc, MASKDWORD); + fa_t->cnt_ofdm_txon = (reg & 0xffff); + fa_t->cnt_ofdm_txen = ((reg & 0xffff0000) >> 16); + + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD); + fa_t->cnt_fast_fsync = (reg & 0xffff); + fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16); + + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD); + fa_t->cnt_ofdm_cca = (reg & 0xffff); + fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16); + + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD); + fa_t->cnt_rate_illegal = (reg & 0xffff); + fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16); + + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD); + fa_t->cnt_mcs_fail = (reg & 0xffff); + + fa_t->cnt_ofdm_fail = + fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal + + fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail + + fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail; + + /* read CCK CRC32 counter */ + fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD); + fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD); + + /* read OFDM CRC32 counter */ + reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD); + fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16; + fa_t->cnt_ofdm_crc32_ok = reg & 0xffff; + + /* read OFDM2 CRC32 counter */ + reg = odm_get_bb_reg(dm, R_0xf9c, MASKDWORD); + fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16; + fa_t->cnt_ofdm2_crc32_ok = reg & 0xffff; + + /* read HT CRC32 counter */ + reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD); + fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16; + fa_t->cnt_ht_crc32_ok = reg & 0xffff; + + /* read HT2 CRC32 counter */ + reg = odm_get_bb_reg(dm, R_0xf98, MASKDWORD); + fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16; + fa_t->cnt_ht2_crc32_ok = reg & 0xffff; + + /* read VHT CRC32 counter */ + fa_t->cnt_vht_crc32_error = 0; + fa_t->cnt_vht_crc32_ok = 0; + + #if (RTL8723D_SUPPORT) + if (dm->support_ic_type == ODM_RTL8723D) { + /* read HT CRC32 agg counter */ + reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD); + fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16; + fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff; + } + #endif + + #if (RTL8188E_SUPPORT) + if (dm->support_ic_type == ODM_RTL8188E) { + reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD); + fa_t->cnt_bw_lsc = (reg & 0xffff); + fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16); + } + #endif + + reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0); + fa_t->cnt_cck_fail = reg; + + reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3); + fa_t->cnt_cck_fail += (reg & 0xff) << 8; + + reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD); + fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8); + + fa_t->cnt_all_pre = fa_t->cnt_all; + + fa_t->cnt_all = fa_t->cnt_fast_fsync + + fa_t->cnt_sb_search_fail + + fa_t->cnt_parity_fail + + fa_t->cnt_rate_illegal + + fa_t->cnt_crc8_fail + + fa_t->cnt_mcs_fail + + fa_t->cnt_cck_fail; + + fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca; +} +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT) +void phydm_fa_cnt_statistics_ac(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 ret_value = 0; + u32 cck_enable = 0; + + if (!(dm->support_ic_type & ODM_IC_11AC_SERIES)) + return; + + ret_value = odm_get_bb_reg(dm, R_0xf50, MASKDWORD); + fa_t->cnt_cck_txen = (ret_value & 0xffff); + fa_t->cnt_ofdm_txen = ((ret_value & 0xffff0000) >> 16); + fa_t->cnt_cck_txon = (u16)odm_get_bb_reg(dm, R_0xfcc, MASKLWORD); + fa_t->cnt_ofdm_txon = (u16)odm_get_bb_reg(dm, R_0xfc8, MASKHWORD); + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD); + fa_t->cnt_fast_fsync = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD); + fa_t->cnt_sb_search_fail = ret_value & 0xffff; + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD); + fa_t->cnt_parity_fail = ret_value & 0xffff; + fa_t->cnt_rate_illegal = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD); + fa_t->cnt_crc8_fail = ret_value & 0xffff; + fa_t->cnt_mcs_fail = (ret_value & 0xffff0000) >> 16; + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD); + fa_t->cnt_crc8_fail_vhta = ret_value & 0xffff; + fa_t->cnt_crc8_fail_vhtb = ret_value & 0xffff0000 >> 16; + + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD); + fa_t->cnt_mcs_fail_vht = ret_value & 0xffff; + + /* read OFDM FA counter */ + fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD); + + /* Read CCK FA counter */ + fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD); + + /* read CCK/OFDM CCA counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD); + fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_cck_cca = ret_value & 0xffff; + + /* read CCK CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_cck_crc32_ok = ret_value & 0xffff; + + /* read OFDM CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff; + + /* read OFDM2 CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0xf1c, MASKDWORD); + fa_t->cnt_ofdm2_crc32_ok = ret_value & 0xffff; + fa_t->cnt_ofdm2_crc32_error = (ret_value & 0xffff0000) >> 16; + + /* read HT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_ht_crc32_ok = ret_value & 0xffff; + + /* read HT2 CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0xf18, MASKDWORD); + fa_t->cnt_ht2_crc32_ok = ret_value & 0xffff; + fa_t->cnt_ht2_crc32_error = (ret_value & 0xffff0000) >> 16; + + /* read VHT CRC32 counter */ + ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD); + fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; + fa_t->cnt_vht_crc32_ok = ret_value & 0xffff; + + /*read VHT2 CRC32 counter */ + ret_value = odm_get_bb_reg(dm, R_0xf54, MASKDWORD); + fa_t->cnt_vht2_crc32_ok = ret_value & 0xffff; + fa_t->cnt_vht2_crc32_error = (ret_value & 0xffff0000) >> 16; + + #if (RTL8881A_SUPPORT) + if (dm->support_ic_type == ODM_RTL8881A) { + u32 tmp = 0; + + if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) { + tmp = fa_t->cnt_ofdm_fail_pre; + fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail; + fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp; + } else { + fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail; + } + + PHYDM_DBG(dm, DBG_FA_CNT, + "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n", + fa_t->cnt_ofdm_fail_pre, tmp); + } + #endif + + cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28)); + + if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */ + fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail; + fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca; + } else { + fa_t->cnt_all = fa_t->cnt_ofdm_fail; + fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca; + } +} +#endif + +u32 phydm_get_edcca_report(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u32 dbg_port = dm->adaptivity.adaptivity_dbg_port; + u32 val = 0; + + if (dm->support_ic_type & ODM_RTL8723D) { + val = odm_get_bb_reg(dm, R_0x9a0, BIT(29)); + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + val = odm_get_bb_reg(dm, R_0x2d38, BIT(24)); + } else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) { + if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E)) + val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30; + else + val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29; + phydm_release_bb_dbg_port(dm); + } + + return val; +} + +void phydm_get_dbg_port_info(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + fa_t->dbg_port0 = odm_get_bb_reg(dm, R_0x2db4, MASKDWORD); + } else { + /*set debug port to 0x0*/ + if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) { + fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm); + phydm_release_bb_dbg_port(dm); + } + } + + fa_t->edcca_flag = (boolean)phydm_get_edcca_report(dm); + + PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n", + fa_t->dbg_port0, fa_t->edcca_flag); +} + +void phydm_set_crc32_cnt2_rate(void *dm_void, u8 rate_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + boolean is_ofdm_rate = phydm_is_ofdm_rate(dm, rate_idx); + boolean is_ht_rate = phydm_is_ht_rate(dm, rate_idx); + boolean is_vht_rate = phydm_is_vht_rate(dm, rate_idx); + u32 reg_addr = 0x0; + u32 ofdm_rate_bitmask = 0x0; + u32 ht_mcs_bitmask = 0x0; + u32 vht_mcs_bitmask = 0x0; + u32 vht_ss_bitmask = 0x0; + u8 rate = 0x0; + u8 ss = 0x0; + + if (!is_ofdm_rate && !is_ht_rate && !is_vht_rate) + PHYDM_DBG(dm, DBG_FA_CNT, + "[FA CNT] rate_idx = (0x%x) is not supported !\n", + rate_idx); + + switch (dm->ic_ip_series) { + case PHYDM_IC_N: + reg_addr = R_0xf04; + ofdm_rate_bitmask = 0x0000f000; + ht_mcs_bitmask = 0x007f0000; + break; + case PHYDM_IC_AC: + reg_addr = R_0xb04; + ofdm_rate_bitmask = 0x0000f000; + ht_mcs_bitmask = 0x007f0000; + vht_mcs_bitmask = 0x0f000000; + vht_ss_bitmask = 0x30000000; + break; + case PHYDM_IC_JGR3: + reg_addr = R_0x1eb8; + ofdm_rate_bitmask = 0x00000f00; + ht_mcs_bitmask = 0x007f0000; + vht_mcs_bitmask = 0x0000f000; + vht_ss_bitmask = 0x000000c0; + break; + default: + break; + } + + if (is_ofdm_rate) { + rate = phydm_legacy_rate_2_spec_rate(dm, rate_idx); + + odm_set_bb_reg(dm, reg_addr, ofdm_rate_bitmask, rate); + fa_t->ofdm2_rate_idx = rate_idx; + } else if (is_ht_rate) { + rate = phydm_rate_2_rate_digit(dm, rate_idx); + + odm_set_bb_reg(dm, reg_addr, ht_mcs_bitmask, rate); + fa_t->ht2_rate_idx = rate_idx; + } else if (is_vht_rate) { + rate = phydm_rate_2_rate_digit(dm, rate_idx); + ss = phydm_rate_to_num_ss(dm, rate_idx); + + odm_set_bb_reg(dm, reg_addr, vht_mcs_bitmask, rate); + odm_set_bb_reg(dm, reg_addr, vht_ss_bitmask, ss - 1); + fa_t->vht2_rate_idx = rate_idx; + } +} + +void phydm_fa_cnt_cal_fa_duration(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ccx_info *ccx = &dm->dm_ccx_info; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + u8 norm = 0; /*normalization*/ + boolean fahm_chk = false; + + fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 + + fa_t->cnt_sb_search_fail * 12 + + fa_t->cnt_parity_fail * 28 + + fa_t->cnt_rate_illegal * 28 + + fa_t->cnt_crc8_fail * 20 + + fa_t->cnt_crc8_fail_vhta * 28 + + fa_t->cnt_mcs_fail_vht * 36 + + fa_t->cnt_mcs_fail * 32 + + fa_t->cnt_cck_fail * 80; + + fa_t->time_fa_exp = fa_t->cnt_ofdm_fail * OFDM_FA_EXP_DURATION + + fa_t->cnt_cck_fail * CCK_FA_EXP_DURATION; + + fa_t->time_fa_ifs_clm = 0; + fa_t->time_fa_fahm = 0; + + #ifdef IFS_CLM_SUPPORT + if (ccx->ccx_watchdog_result & IFS_CLM_SUCCESS) { + norm = (u8)PHYDM_DIV(PHYDM_WATCH_DOG_PERIOD * S_TO_US, + ccx->ifs_clm_period); + fa_t->time_fa_ifs_clm = (ccx->ifs_clm_cckfa + + ccx->ifs_clm_ofdmfa) * norm; + } + #endif + + #ifdef FAHM_SUPPORT + if (ccx->ccx_watchdog_result & FAHM_SUCCESS) { + if (fa_t->cnt_cck_fail) { + if (ccx->fahm_inclu_cck) + fahm_chk = true; + } else { + fahm_chk = true; + } + } + + if (fahm_chk) { + norm = (u8)PHYDM_DIV(PHYDM_WATCH_DOG_PERIOD * S_TO_US, + ccx->fahm_period); + fa_t->time_fa_fahm = ccx->fahm_result_sum * norm; + } + #endif +} + +void phydm_false_alarm_counter_statistics(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *fa_t = &dm->false_alm_cnt; + char dbg_buf[PHYDM_SNPRINT_SIZE] = {0}; + u32 tmp = 0; + + if (!(dm->support_ability & ODM_BB_FA_CNT)) + return; + + PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__); + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + phydm_fa_cnt_statistics_jgr3(dm); + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + #if (ODM_IC_11N_SERIES_SUPPORT) + phydm_fa_cnt_statistics_n(dm); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if (ODM_IC_11AC_SERIES_SUPPORT) + phydm_fa_cnt_statistics_ac(dm); + #endif + } + + phydm_get_dbg_port_info(dm); + phydm_false_alarm_counter_reg_reset(dm_void); + + phydm_fa_cnt_cal_fa_duration(dm); + + fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error + + fa_t->cnt_ht_crc32_error + + fa_t->cnt_ofdm_crc32_error + + fa_t->cnt_cck_crc32_error; + + fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok + + fa_t->cnt_ht_crc32_ok + + fa_t->cnt_ofdm_crc32_ok + + fa_t->cnt_cck_crc32_ok; + + PHYDM_DBG(dm, DBG_FA_CNT, + "[Tx cnt] {CCK_TxEN, CCK_TxON, OFDM_TxEN, OFDM_TxON} = {%d, %d, %d, %d}\n", + fa_t->cnt_cck_txen, fa_t->cnt_cck_txon, fa_t->cnt_ofdm_txen, + fa_t->cnt_ofdm_txon); + PHYDM_DBG(dm, DBG_FA_CNT, + "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all); + PHYDM_DBG(dm, DBG_FA_CNT, + "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all); + PHYDM_DBG(dm, DBG_FA_CNT, + "[FA duration(us)] {exp, ifs_clm, fahm} = {%d, %d, %d}\n", + fa_t->time_fa_exp, fa_t->time_fa_ifs_clm, + fa_t->time_fa_fahm); + PHYDM_DBG(dm, DBG_FA_CNT, + "[OFDM FA] Parity=%d, Rate=%d, Fast_Fsync=%d, SBD=%d\n", + fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal, + fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail); + PHYDM_DBG(dm, DBG_FA_CNT, "[HT FA] CRC8=%d, MCS=%d\n", + fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail); +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) { + PHYDM_DBG(dm, DBG_FA_CNT, + "[VHT FA] SIGA_CRC8=%d, SIGB_CRC8=%d, MCS=%d\n", + fa_t->cnt_crc8_fail_vhta, fa_t->cnt_crc8_fail_vhtb, + fa_t->cnt_mcs_fail_vht); + } +#endif + + PHYDM_DBG(dm, DBG_FA_CNT, + "[CRC32 OK Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n", + fa_t->cnt_cck_crc32_ok, fa_t->cnt_ofdm_crc32_ok, + fa_t->cnt_ht_crc32_ok, fa_t->cnt_vht_crc32_ok, + fa_t->cnt_crc32_ok_all); + PHYDM_DBG(dm, DBG_FA_CNT, + "[CRC32 Err Cnt] {CCK, OFDM, HT, VHT, Total} = {%d, %d, %d, %d, %d}\n", + fa_t->cnt_cck_crc32_error, fa_t->cnt_ofdm_crc32_error, + fa_t->cnt_ht_crc32_error, fa_t->cnt_vht_crc32_error, + fa_t->cnt_crc32_error_all); + + if (fa_t->ofdm2_rate_idx) { + tmp = fa_t->cnt_ofdm2_crc32_error + fa_t->cnt_ofdm2_crc32_ok; + fa_t->ofdm2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ofdm2_crc32_ok * 100, + tmp); + phydm_print_rate_2_buff(dm, fa_t->ofdm2_rate_idx, dbg_buf, + PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_FA_CNT, + "[OFDM:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n", + dbg_buf, fa_t->cnt_ofdm2_crc32_error, + fa_t->cnt_ofdm2_crc32_ok, fa_t->ofdm2_pcr); + } else { + phydm_set_crc32_cnt2_rate(dm, ODM_RATE6M); + } + + if (fa_t->ht2_rate_idx) { + tmp = fa_t->cnt_ht2_crc32_error + fa_t->cnt_ht2_crc32_ok; + fa_t->ht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_ht2_crc32_ok * 100, + tmp); + phydm_print_rate_2_buff(dm, fa_t->ht2_rate_idx, dbg_buf, + PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_FA_CNT, + "[HT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n", + dbg_buf, fa_t->cnt_ht2_crc32_error, + fa_t->cnt_ht2_crc32_ok, fa_t->ht2_pcr); + } else { + phydm_set_crc32_cnt2_rate(dm, ODM_RATEMCS0); + } + +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + if (dm->support_ic_type & (ODM_IC_11AC_SERIES | ODM_IC_JGR3_SERIES)) { + if (fa_t->vht2_rate_idx) { + tmp = fa_t->cnt_vht2_crc32_error + + fa_t->cnt_vht2_crc32_ok; + fa_t->vht2_pcr = (u8)PHYDM_DIV(fa_t->cnt_vht2_crc32_ok * + 100, tmp); + phydm_print_rate_2_buff(dm, fa_t->vht2_rate_idx, + dbg_buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_FA_CNT, + "[VHT:%s CRC32 Cnt] {error, ok}= {%d, %d} (%d percent)\n", + dbg_buf, fa_t->cnt_vht2_crc32_error, + fa_t->cnt_vht2_crc32_ok, fa_t->vht2_pcr); + } else { + phydm_set_crc32_cnt2_rate(dm, ODM_RATEVHTSS1MCS0); + } + } +#endif +} + +void phydm_fill_fw_dig_info(void *dm_void, boolean *enable, + u8 *para4, u8 *para8) { + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + dig_t->fw_dig_enable = *enable; + para8[0] = dig_t->rx_gain_range_max; + para8[1] = dig_t->rx_gain_range_min; + para8[2] = dm->number_linked_client; + para4[0] = (u8)DIG_LPS_MODE; +} + +void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u8 rate = 0x0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[CRC32 Cnt] {rate_idx}\n"); + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + rate = (u8)var1[0]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "{rate}={0x%x}", rate); + + phydm_set_crc32_cnt2_rate(dm, rate); + } + *_used = used; + *_out_len = out_len; +} + +#ifdef PHYDM_TDMA_DIG_SUPPORT +void phydm_set_tdma_dig_timer(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 delta_time_us = dm->tdma_dig_timer_ms * 1000; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u32 timeout = 0; + u32 current_time_stamp, diff_time_stamp, regb0 = 0; + + /*some IC has no FREERUN_CUNT register, like 92E*/ + if (dm->support_ic_type & ODM_RTL8197F) + current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff); + else + return; + + timeout = current_time_stamp + delta_time_us; + + diff_time_stamp = current_time_stamp - dig_t->cur_timestamp; + dig_t->pre_timestamp = dig_t->cur_timestamp; + dig_t->cur_timestamp = current_time_stamp; + + /*@HIMR0, it shows HW interrupt mask*/ + regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff); + + PHYDM_DBG(dm, DBG_DIG, "Set next timer\n"); + PHYDM_DBG(dm, DBG_DIG, + "curr_time_stamp=%d, delta_time_us=%d\n", + current_time_stamp, delta_time_us); + PHYDM_DBG(dm, DBG_DIG, + "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n", + timeout, diff_time_stamp, regb0); + + if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/ + odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout); + else { + PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n"); + return; + } +} + +void phydm_tdma_dig_timer_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n", + dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt); + + if (dig_t->tdma_dig_cnt == 0 || + dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) { + if (dm->support_ability & ODM_BB_DIG) { +#ifdef IS_USE_NEW_TDMA + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B | + ODM_RTL8812F | ODM_RTL8822B | ODM_RTL8192F | + ODM_RTL8821C | ODM_RTL8197G | ODM_RTL8822C | + ODM_RTL8723D| ODM_RTL8723F)) { + PHYDM_DBG(dm, DBG_DIG, + "Check fail, Restart timer\n\n"); + phydm_false_alarm_counter_reset(dm); + odm_set_timer(dm, &dm->tdma_dig_timer, + dm->tdma_dig_timer_ms); + } else { + PHYDM_DBG(dm, DBG_DIG, + "Not support TDMADIG, no SW timer\n"); + } +#else + /*@if interrupt mask info is got.*/ + /*Reg0xb0 is no longer needed*/ +#if 0 + /*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/ +#endif + PHYDM_DBG(dm, DBG_DIG, + "Check fail, Mask[0]=0x%x, restart timer\n", + *dm->interrupt_mask); + + phydm_tdma_dig_add_interrupt_mask_handler(dm); + phydm_enable_rx_related_interrupt_handler(dm); + phydm_set_tdma_dig_timer(dm); +#endif + } + } else { + PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n"); + } + + dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt; +} + +/*@different IC/team may use different timer for tdma-dig*/ +void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (DM_ODM_SUPPORT_TYPE == (ODM_AP)) + if (dm->support_ic_type & ODM_RTL8197F) { + /*@HAL_INT_TYPE_PSTIMEOUT2*/ + phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2); + } +#elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN)) +#elif (DM_ODM_SUPPORT_TYPE == (ODM_CE)) +#endif +} + +/* will be triggered by HW timer*/ +void phydm_tdma_dig(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + u32 reg_c50 = 0; + +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT) +#ifdef IS_USE_NEW_TDMA + if (dm->support_ic_type & + (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8812F | ODM_RTL8822B | + ODM_RTL8192F | ODM_RTL8821C)) { + PHYDM_DBG(dm, DBG_DIG, "98F/14B/12F/22B/92F/21C, new tdma\n"); + return; + } +#endif +#endif + reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0); + + dig_t->tdma_dig_state = + dig_t->tdma_dig_cnt % dm->tdma_dig_state_number; + + PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n", + dig_t->tdma_dig_state, reg_c50); + + dig_t->tdma_dig_cnt++; + + if (dig_t->tdma_dig_state == 1) { + /* update IGI from tdma_dig_state == 0*/ + if (dig_t->cur_ig_value_tdma == 0) + dig_t->cur_ig_value_tdma = dig_t->cur_ig_value; + + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + phydm_tdma_false_alarm_counter_check(dm); + PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n", + dig_t->tdma_dig_state); + + } else if (dig_t->tdma_dig_state == 0) { + /* update dig_t->CurIGValue,*/ + /* @it may different from dig_t->cur_ig_value_tdma */ + /* TDMA IGI upperbond @ L-state = */ + /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */ + + if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond) + dig_t->low_ig_value = dm->tdma_dig_low_upper_bond; + else + dig_t->low_ig_value = dig_t->cur_ig_value; + + odm_write_dig(dm, dig_t->low_ig_value); + phydm_tdma_false_alarm_counter_check(dm); + } else { + phydm_tdma_false_alarm_counter_check(dm); + } +} + +/*@============================================================*/ +/*@FASLE ALARM CHECK*/ +/*@============================================================*/ +void phydm_tdma_false_alarm_counter_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + boolean rssi_dump_en = 0; + u32 timestamp = 0; + u8 tdma_dig_state_number = 0; + u32 start_th = 0; + + if (dig_t->tdma_dig_state == 1) + phydm_false_alarm_counter_reset(dm); + /* Reset FalseAlarmCounterStatistics */ + /* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */ + /* @fa_end_tsf = fa_start_tsf = TSF */ + else { + phydm_false_alarm_counter_statistics(dm); + if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/ + timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord); + else { + PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n"); + return; + } + dig_t->fa_end_timestamp = timestamp; + dig_t->fa_acc_1sec_timestamp += + (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp); + + /*prevent dumb*/ + if (dm->tdma_dig_state_number == 1) + dm->tdma_dig_state_number = 2; + + tdma_dig_state_number = dm->tdma_dig_state_number; + dig_t->sec_factor = + tdma_dig_state_number / (tdma_dig_state_number - 1); + + /*@1sec = 1000000us*/ + if (dig_t->sec_factor) + start_th = (u32)(1000000 / dig_t->sec_factor); + + if (dig_t->fa_acc_1sec_timestamp >= start_th) { + rssi_dump_en = 1; + phydm_false_alarm_counter_acc(dm, rssi_dump_en); + PHYDM_DBG(dm, DBG_DIG, + "sec_factor=%d, total FA=%d, is_linked=%d\n", + dig_t->sec_factor, falm_cnt_acc->cnt_all, + dm->is_linked); + + phydm_noisy_detection(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + phydm_dig(dm); + phydm_false_alarm_counter_acc_reset(dm); + + /* Reset FalseAlarmCounterStatistics */ + /* @fa_end_tsf = fa_start_tsf = TSF, keep */ + /* @fa_acc_1sec_tsf = 0 */ + phydm_false_alarm_counter_reset(dm); + } else { + phydm_false_alarm_counter_acc(dm, rssi_dump_en); + } + } +} + +void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail; + falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal; + falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail; + falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail; + falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail; + falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail; + falm_cnt_acc->cnt_all += falm_cnt->cnt_all; + falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync; + falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail; + falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca; + falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca; + falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all; + falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error; + falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok; + falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error; + falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok; + falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error; + falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok; + falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error; + falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok; + falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all; + falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all; + + if (rssi_dump_en == 1) { + falm_cnt_acc->cnt_all_1sec = + falm_cnt_acc->cnt_all * dig_t->sec_factor; + falm_cnt_acc->cnt_cca_all_1sec = + falm_cnt_acc->cnt_cca_all * dig_t->sec_factor; + falm_cnt_acc->cnt_cck_fail_1sec = + falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor; + } +} + +void phydm_false_alarm_counter_acc_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_acc_struct *falm_cnt_acc = NULL; + +#ifdef IS_USE_NEW_TDMA + struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL; + u32 tmp_cca_1sec = 0; + u32 tmp_fa_1sec = 0; + + /*@clear L-fa_acc struct*/ + falm_cnt_acc_low = &dm->false_alm_cnt_acc_low; + tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec; + tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec; + odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc)); + falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec; + falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec; + + /*@clear H-fa_acc struct*/ + falm_cnt_acc = &dm->false_alm_cnt_acc; + tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec; + tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec; + odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc)); + falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec; + falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec; +#else + falm_cnt_acc = &dm->false_alm_cnt_acc; + /* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */ + /* @do NOT need to be reset */ + odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc)); +#endif +} + +void phydm_false_alarm_counter_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt; + struct phydm_dig_struct *dig_t; + u32 timestamp; + + falm_cnt = &dm->false_alm_cnt; + dig_t = &dm->dm_dig_table; + + memset(falm_cnt, 0, sizeof(dm->false_alm_cnt)); + phydm_false_alarm_counter_reg_reset(dm); + +#ifdef IS_USE_NEW_TDMA + return; +#endif + if (dig_t->tdma_dig_state != 1) + dig_t->fa_acc_1sec_timestamp = 0; + else + dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp; + + /*REG_FREERUN_CNT*/ + timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord); + dig_t->fa_start_timestamp = timestamp; + dig_t->fa_end_timestamp = timestamp; +} + +void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + switch (type) { + case ENABLE_TDMA: + dm->original_dig_restore = !((boolean)input); + break; + case MODE_DECISION: + if (input == (u8)MODE_PERFORMANCE) + dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES + 2; + else if (input == (u8)MODE_COVERAGE) + dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES; + else + dm->tdma_dig_state_number = DIG_NUM_OF_TDMA_STATES; + break; + } +} + +#ifdef IS_USE_NEW_TDMA +#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) +static void pre_phydm_tdma_dig_cbk(unsigned long task_dm) +{ + struct dm_struct *dm = (struct dm_struct *)task_dm; + struct rtl8192cd_priv *priv = dm->priv; + struct priv_shared_info *pshare = priv->pshare; + + if (!(priv->drv_state & DRV_STATE_OPEN)) + return; + + if (pshare->bDriverStopped || pshare->bSurpriseRemoved) { + printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", + __FUNCTION__, pshare->bDriverStopped, + pshare->bSurpriseRemoved); + return; + } + + rtw_enqueue_timer_event(priv, &pshare->tdma_dig_event, + ENQUEUE_TO_TAIL); +} + +void phydm_tdma_dig_timers_usb(void *dm_void, u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (state == INIT_TDMA_DIG_TIMMER) { + struct rtl8192cd_priv *priv = dm->priv; + + init_timer(&dm->tdma_dig_timer); + dm->tdma_dig_timer.data = (unsigned long)dm; + dm->tdma_dig_timer.function = pre_phydm_tdma_dig_cbk; + INIT_TIMER_EVENT_ENTRY(&priv->pshare->tdma_dig_event, + phydm_tdma_dig_cbk, + (unsigned long)dm); + } else if (state == CANCEL_TDMA_DIG_TIMMER) { + odm_cancel_timer(dm, &dm->tdma_dig_timer); + } else if (state == RELEASE_TDMA_DIG_TIMMER) { + odm_release_timer(dm, &dm->tdma_dig_timer); + } +} +#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */ + +void phydm_tdma_dig_timers(void *dm_void, u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; +#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) + struct rtl8192cd_priv *priv = dm->priv; + + if (priv->hci_type == RTL_HCI_USB) { + phydm_tdma_dig_timers_usb(dm_void, state); + return; + } +#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */ + + if (state == INIT_TDMA_DIG_TIMMER) + odm_initialize_timer(dm, &dm->tdma_dig_timer, + (void *)phydm_tdma_dig_cbk, + NULL, "phydm_tdma_dig_timer"); + else if (state == CANCEL_TDMA_DIG_TIMMER) + odm_cancel_timer(dm, &dm->tdma_dig_timer); + else if (state == RELEASE_TDMA_DIG_TIMMER) + odm_release_timer(dm, &dm->tdma_dig_timer); +} + +u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max, + u8 *rx_gain_min, boolean is_dfs_band) +{ + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 step[3] = {0}; + u8 cur_igi = igi; + + if (dm->is_linked) { + if (dm->pre_rssi_min <= dm->rssi_min) { + PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n"); + step[0] = 2; + step[1] = 1; + step[2] = 2; + } else { + step[0] = 4; + step[1] = 2; + step[2] = 2; + } + } else { + step[0] = 2; + step[1] = 1; + step[2] = 2; + } + + PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1], + step[0]); + + if (dm->first_connect) { + if (is_dfs_band) { + if (dm->rssi_min > DIG_MAX_DFS) + igi = DIG_MAX_DFS; + else + igi = dm->rssi_min; + PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n", + *rx_gain_max); + } else { + igi = *rx_gain_min; + } + + #if 0 + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (RTL8812A_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812) + odm_config_bb_with_header_file(dm, + CONFIG_BB_AGC_TAB_DIFF); + #endif + #endif + #endif + PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi); + } else { + /* @2 Before link */ + PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n"); + + if (dm->first_disconnect) { + igi = dig_t->dm_dig_min; + PHYDM_DBG(dm, DBG_DIG, + "First disconnect:foce IGI to lower bound\n"); + } else { + PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n", + igi, fa_cnt); + + igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step); + } + } + /*@Check IGI by dyn-upper/lower bound */ + if (igi < *rx_gain_min) + igi = *rx_gain_min; + + if (igi > *rx_gain_max) + igi = *rx_gain_max; + + PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n", + fa_cnt, cur_igi, igi); + + return igi; +} + +void phydm_write_tdma_dig(void *dm_void, u8 new_igi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity; + + PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__); +#if 0 + /* @1 Check IGI by upper bound */ + if (adaptivity->igi_lmt_en && + new_igi > adaptivity->adapt_igi_up && dm->is_linked) { + new_igi = adaptivity->adapt_igi_up; + + PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n", + new_igi); + } +#endif + phydm_write_dig_reg(dm, new_igi); + + PHYDM_DBG(dm, DBG_DIG, "New %s-IGI=((0x%x))\n", + (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) ? "L" : "H", + new_igi); +} + +void phydm_tdma_dig_new(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (phydm_dig_abort(dm) || dm->original_dig_restore) + return; + /*@ + *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n"); + * dig_t->tdma_dig_state); + *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n", + * dig_t->cur_ig_value_tdma, + * dig_t->low_ig_value); + */ + phydm_tdma_fa_cnt_chk(dm); + + /*@prevent dumb*/ + if (dm->tdma_dig_state_number < 2) + dm->tdma_dig_state_number = 2; + + /*@update state*/ + dig_t->tdma_dig_cnt++; + dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number; + + /*@ + *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n", + * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt); + */ + + if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) + odm_write_dig(dm, dig_t->low_ig_value); + else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE) + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + + odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms); +} + +/*@callback function triggered by SW timer*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_tdma_dig_cbk(struct phydm_timer_list *timer) +{ + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrcs; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + #if USE_WORKITEM + odm_schedule_work_item(&dm->phydm_tdma_dig_workitem); + #else + phydm_tdma_dig_new(dm); + #endif + #else + odm_schedule_work_item(&dm->phydm_tdma_dig_workitem); + #endif +} + +void phydm_tdma_dig_workitem_callback(void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + phydm_tdma_dig_new(dm); +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_tdma_dig_cbk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *padapter = dm->adapter; + + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_tdma_dig_workitem_callback(dm); + /* @Can't do I/O in timer callback*/ + else + phydm_run_in_thread_cmd(dm, phydm_tdma_dig_workitem_callback, + dm); +} + +void phydm_tdma_dig_workitem_callback(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (phydm_dig_abort(dm) || (dm->original_dig_restore)) + return; + /*@ + *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n"); + * dig_t->tdma_dig_state); + *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n", + * dig_t->cur_ig_value_tdma, + * dig_t->low_ig_value); + */ + phydm_tdma_fa_cnt_chk(dm); + + /*@prevent dumb*/ + if (dm->tdma_dig_state_number < 2) + dm->tdma_dig_state_number = 2; + + /*@update state*/ + dig_t->tdma_dig_cnt++; + dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number; + + /*@ + *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n", + * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt); + */ + + if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) + odm_write_dig(dm, dig_t->low_ig_value); + else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE) + odm_write_dig(dm, dig_t->cur_ig_value_tdma); + + odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms); +} +#else +void phydm_tdma_dig_cbk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + + if (phydm_dig_abort(dm) || dm->original_dig_restore) + return; + /*@ + *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n"); + * dig_t->tdma_dig_state); + *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n", + * dig_t->cur_ig_value_tdma, + * dig_t->low_ig_value); + */ + phydm_tdma_fa_cnt_chk(dm); + + /*@prevent dumb*/ + if (dm->tdma_dig_state_number < 2) + dm->tdma_dig_state_number = 2; + + /*@update state*/ + dig_t->tdma_dig_cnt++; + dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number; + + /*@ + *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n", + * dig_t->tdma_dig_state, dig_t->tdma_dig_cnt); + */ + + if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) + phydm_write_tdma_dig(dm, dig_t->low_ig_value); + else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE) + phydm_write_tdma_dig(dm, dig_t->cur_ig_value_tdma); + + odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms); +} +#endif +/*@============================================================*/ +/*@FASLE ALARM CHECK*/ +/*@============================================================*/ +void phydm_tdma_fa_cnt_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *fa_t_acc = &dm->false_alm_cnt_acc; + struct phydm_fa_acc_struct *fa_t_acc_low = &dm->false_alm_cnt_acc_low; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + boolean tdma_dig_block_1sec_flag = false; + u32 timestamp = 0; + u8 states_per_block = dm->tdma_dig_state_number; + u8 cur_tdma_dig_state = 0; + u32 start_th = 0; + u8 state_diff = 0; + u32 tdma_dig_block_period_ms = 0; + u32 tdma_dig_block_cnt_thd = 0; + u32 timestamp_diff = 0; + + /*@calculate duration of a tdma block*/ + tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block; + + /*@ + *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms, + *or FA will be fewer. + */ + tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms; + + /*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/ + if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE) + cur_tdma_dig_state = TDMA_DIG_LOW_STATE; + else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE) + cur_tdma_dig_state = TDMA_DIG_HIGH_STATE; + /*@ + *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n", + * cur_tdma_dig_state, dig_t->tdma_dig_cnt); + */ + if (cur_tdma_dig_state == 0) { + /*@L-state indicates next block*/ + dig_t->tdma_dig_block_cnt++; + + /*@1sec dump check*/ + if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd) + tdma_dig_block_1sec_flag = true; + + /*@ + *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n", + * dig_t->tdma_dig_block_cnt); + */ + + /*@collect FA till this block end*/ + phydm_false_alarm_counter_statistics(dm); + phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag, + cur_tdma_dig_state); + /*@1s L-FA collect end*/ + + /*@1sec dump reached*/ + if (tdma_dig_block_1sec_flag) { + /*@L-DIG*/ + phydm_noisy_detection(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n"); + phydm_tdma_low_dig(dm); + PHYDM_DBG(dm, DBG_DIG, "\n\n"); + } + } else if (cur_tdma_dig_state == 1) { + /*@1sec dump check*/ + if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd) + tdma_dig_block_1sec_flag = true; + + /*@ + *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n", + * dig_t->tdma_dig_block_cnt); + */ + + /*@collect FA till this block end*/ + phydm_false_alarm_counter_statistics(dm); + phydm_fa_cnt_acc(dm, tdma_dig_block_1sec_flag, + cur_tdma_dig_state); + /*@1s H-FA collect end*/ + + /*@1sec dump reached*/ + state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state; + if (tdma_dig_block_1sec_flag && state_diff == 1) { + /*@H-DIG*/ + phydm_noisy_detection(dm); + #ifdef PHYDM_SUPPORT_CCKPD + phydm_cck_pd_th(dm); + #endif + PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n"); + phydm_tdma_high_dig(dm); + PHYDM_DBG(dm, DBG_DIG, "\n\n"); + PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n", + dm->is_linked); + PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n", + fa_t_acc_low->cnt_cca_all_1sec, + fa_t_acc_low->cnt_all_1sec); + PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n", + fa_t_acc->cnt_cca_all_1sec, + fa_t_acc->cnt_all_1sec); + PHYDM_DBG(dm, DBG_DIG, + "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n", + fa_t_acc->cnt_cca_all + + fa_t_acc_low->cnt_cca_all, + fa_t_acc->cnt_all + fa_t_acc_low->cnt_all); + + /*@Reset AccFalseAlarmCounterStatistics */ + phydm_false_alarm_counter_acc_reset(dm); + dig_t->tdma_dig_block_cnt = 0; + } + } + /*@Reset FalseAlarmCounterStatistics */ + phydm_false_alarm_counter_reset(dm); +} + +void phydm_tdma_low_dig(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low; +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; +#endif + u8 igi = dig_t->cur_ig_value; + u8 new_igi = 0x20; + u8 tdma_l_igi = dig_t->low_ig_value; + u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE]; + u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE]; + u32 fa_cnt = falm_cnt->cnt_all; + boolean dfs_mode_en = false, is_performance = true; + u8 rssi_min = dm->rssi_min; + u8 igi_upper_rssi_min = 0; + u8 offset = 15; + + if (!(dm->original_dig_restore)) { + if (tdma_l_igi == 0) + tdma_l_igi = igi; + + fa_cnt = falm_cnt_acc->cnt_all_1sec; + } + + if (phydm_dig_abort(dm)) { + dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A); + return; + } + + /*@Mode Decision*/ + dfs_mode_en = false; + is_performance = true; + + /* @Abs Boundary Decision*/ + dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26 + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20 + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22 + + if (dm->is_dfs_band) { + if (*dm->band_width == CHANNEL_WIDTH_20){ + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){ + if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1) + dig_t->dm_dig_min = DIG_MIN_DFS + 2; + else + dig_t->dm_dig_min = DIG_MIN_DFS; + } + else + dig_t->dm_dig_min = DIG_MIN_DFS; + } + else + dig_t->dm_dig_min = DIG_MIN_DFS; + + } else { + #if 0 + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)) + dig_t->dm_dig_min = 0x1c; + else if (dm->support_ic_type & ODM_RTL8197F) + dig_t->dm_dig_min = 0x1e; /*@For HW setting*/ + #endif + } + + PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n", + dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min); + + /* @Dyn Boundary by RSSI*/ + if (!dm->is_linked) { + /*@if no link, always stay at lower bound*/ + tdma_l_dym_max = 0x26; + tdma_l_dym_min = dig_t->dm_dig_min; + + PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_l_dym_max, tdma_l_dym_min); + } else { + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", + dm->rssi_min, offset); + + /* @DIG lower bound in L-state*/ + tdma_l_dym_min = dig_t->dm_dig_min; + if (dm->is_dfs_band) + tdma_l_dym_min = DIG_MIN_DFS; + /*@ + *#ifdef CFG_DIG_DAMPING_CHK + *@Limit Dyn min by damping + *if (dig_t->dig_dl_en && + * dig_rc->damping_limit_en && + * tdma_l_dym_min < dig_rc->damping_limit_val) { + * PHYDM_DBG(dm, DBG_DIG, + * "[Limit by Damping] dyn_min=0x%x -> 0x%x\n", + * tdma_l_dym_min, dig_rc->damping_limit_val); + * + * tdma_l_dym_min = dig_rc->damping_limit_val; + *} + *#endif + */ + + /*@DIG upper bound in L-state*/ + igi_upper_rssi_min = rssi_min + offset; + if (igi_upper_rssi_min > dig_t->dm_dig_max) + tdma_l_dym_max = dig_t->dm_dig_max; + else if (igi_upper_rssi_min < dig_t->dm_dig_min) + tdma_l_dym_max = dig_t->dm_dig_min; + else + tdma_l_dym_max = igi_upper_rssi_min; + + /* @1 Force Lower Bound for AntDiv */ + /*@ + *if (!dm->is_one_entry_only && + *(dm->support_ability & ODM_BB_ANT_DIV) && + *(dm->ant_div_type == CG_TRX_HW_ANTDIV || + *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) { + *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min) + * dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + *else + * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max; + * + *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n", + * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max); + *} + */ + + PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_l_dym_max, tdma_l_dym_min); + } + + /*@Abnormal Case Check*/ + /*@Abnormal lower bound case*/ + if (tdma_l_dym_min > tdma_l_dym_max) + tdma_l_dym_min = tdma_l_dym_max; + + PHYDM_DBG(dm, DBG_DIG, + "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n", + tdma_l_dym_max, tdma_l_dym_min); + + /*@False Alarm Threshold Decision*/ + phydm_fa_threshold_check(dm, dfs_mode_en); + + /*@Adjust Initial Gain by False Alarm*/ + /*Select new IGI by FA */ + if (!(dm->original_dig_restore)) { + tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt, + &tdma_l_dym_max, + &tdma_l_dym_min, + dfs_mode_en); + } else { + new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en); + } + + /*Update status*/ + if (!(dm->original_dig_restore)) { + if (dig_t->tdma_force_l_igi == 0xff) + dig_t->low_ig_value = tdma_l_igi; + else + dig_t->low_ig_value = dig_t->tdma_force_l_igi; + dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min; + dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max; +#if 0 + /*odm_write_dig(dm, tdma_l_igi);*/ +#endif + } else { + odm_write_dig(dm, new_igi); + } +} + +void phydm_tdma_high_dig(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc; +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t; +#endif + u8 igi = dig_t->cur_ig_value; + u8 new_igi = 0x20; + u8 tdma_h_igi = dig_t->cur_ig_value_tdma; + u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE]; + u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE]; + u32 fa_cnt = falm_cnt->cnt_all; + boolean dfs_mode_en = false, is_performance = true; + u8 rssi_min = dm->rssi_min; + u8 igi_upper_rssi_min = 0; + u8 offset = 15; + + if (!(dm->original_dig_restore)) { + if (tdma_h_igi == 0) + tdma_h_igi = igi; + + fa_cnt = falm_cnt_acc->cnt_all_1sec; + } + + if (phydm_dig_abort(dm)) { + dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A); + return; + } + + /*@Mode Decision*/ + dfs_mode_en = false; + is_performance = true; + + /*@Abs Boundary Decision*/ + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a + + if (!dm->is_linked) { + dig_t->dm_dig_max = DIG_MAX_COVERAGR; + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20 + } else if (dm->is_dfs_band) { + if (*dm->band_width == CHANNEL_WIDTH_20){ + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)){ + if (odm_get_bb_reg(dm, R_0x8d8, BIT(27)) == 1) + dig_t->dm_dig_min = DIG_MIN_DFS + 2; + else + dig_t->dm_dig_min = DIG_MIN_DFS; + } + else + dig_t->dm_dig_min = DIG_MIN_DFS; + } + else + dig_t->dm_dig_min = DIG_MIN_DFS; + + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + } else { + if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) { + /*service > 2 devices*/ + dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE; + #if (DIG_HW == 1) + dig_t->dig_max_of_min = DIG_MIN_COVERAGE; + #else + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; + #endif + } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) { + /*service 1 devices*/ + dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE; + dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE; + } + + #if 0 + if (dm->support_ic_type & + (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B)) + dig_t->dm_dig_min = 0x1c; + else if (dm->support_ic_type & ODM_RTL8197F) + dig_t->dm_dig_min = 0x1e; /*@For HW setting*/ + else + #endif + dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; + } + PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n", + dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min); + + /*@Dyn Boundary by RSSI*/ + if (!dm->is_linked) { + /*@if no link, always stay at lower bound*/ + tdma_h_dym_max = dig_t->dig_max_of_min; + tdma_h_dym_min = dig_t->dm_dig_min; + + PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_h_dym_max, tdma_h_dym_min); + } else { + PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", + dm->rssi_min, offset); + + /* @DIG lower bound in H-state*/ + if (dm->is_dfs_band) + tdma_h_dym_min = DIG_MIN_DFS; + else if (rssi_min < dig_t->dm_dig_min) + tdma_h_dym_min = dig_t->dm_dig_min; + else + tdma_h_dym_min = rssi_min; // turbo not considered yet + +#ifdef CFG_DIG_DAMPING_CHK + /*@Limit Dyn min by damping*/ + if (dig_t->dig_dl_en && + dig_rc->damping_limit_en && + tdma_h_dym_min < dig_rc->damping_limit_val) { + PHYDM_DBG(dm, DBG_DIG, + "[Limit by Damping] dyn_min=0x%x -> 0x%x\n", + tdma_h_dym_min, dig_rc->damping_limit_val); + + tdma_h_dym_min = dig_rc->damping_limit_val; + } +#endif + + /*@DIG upper bound in H-state*/ + igi_upper_rssi_min = rssi_min + offset; + if (igi_upper_rssi_min > dig_t->dm_dig_max) + tdma_h_dym_max = dig_t->dm_dig_max; + else + tdma_h_dym_max = igi_upper_rssi_min; + + /* @1 Force Lower Bound for AntDiv */ + /*@ + *if (!dm->is_one_entry_only && + *(dm->support_ability & ODM_BB_ANT_DIV) && + *(dm->ant_div_type == CG_TRX_HW_ANTDIV || + *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) { + * if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min) + * dig_t->rx_gain_range_min = dig_t->dig_max_of_min; + * else + * dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max; + */ + /*@ + *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n", + * dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max); + *} + */ + PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n", + tdma_h_dym_max, tdma_h_dym_min); + } + + /*@Abnormal Case Check*/ + /*@Abnormal low higher bound case*/ + if (tdma_h_dym_max < dig_t->dm_dig_min) + tdma_h_dym_max = dig_t->dm_dig_min; + /*@Abnormal lower bound case*/ + if (tdma_h_dym_min > tdma_h_dym_max) + tdma_h_dym_min = tdma_h_dym_max; + + PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n", + tdma_h_dym_max, tdma_h_dym_min); + + /*@False Alarm Threshold Decision*/ + phydm_fa_threshold_check(dm, dfs_mode_en); + + /*@Adjust Initial Gain by False Alarm*/ + /*Select new IGI by FA */ + if (!(dm->original_dig_restore)) { + tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt, + &tdma_h_dym_max, + &tdma_h_dym_min, + dfs_mode_en); + } else { + new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en); + } + + /*Update status*/ + if (!(dm->original_dig_restore)) { + if (dig_t->tdma_force_h_igi == 0xff) + dig_t->cur_ig_value_tdma = tdma_h_igi; + else + dig_t->cur_ig_value_tdma = dig_t->tdma_force_h_igi; + dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min; + dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max; +#if 0 + /*odm_write_dig(dm, tdma_h_igi);*/ +#endif + } else { + odm_write_dig(dm, new_igi); + } +} + +void phydm_fa_cnt_acc(void *dm_void, boolean tdma_dig_block_1sec_flag, + u8 cur_tdma_dig_state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt; + struct phydm_fa_acc_struct *falm_cnt_acc = NULL; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 factor_num = 0; + u8 factor_denum = 1; + u8 total_state_number = 0; + + if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) + falm_cnt_acc = &dm->false_alm_cnt_acc_low; + else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) + + falm_cnt_acc = &dm->false_alm_cnt_acc; + /*@ + *PHYDM_DBG(dm, DBG_DIG, + * "[%s] ==> dig_state=%d, one_sec=%d\n", __func__, + * cur_tdma_dig_state, tdma_dig_block_1sec_flag); + */ + falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail; + falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal; + falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail; + falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail; + falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail; + falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail; + falm_cnt_acc->cnt_all += falm_cnt->cnt_all; + falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync; + falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail; + falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca; + falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca; + falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all; + falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error; + falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok; + falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error; + falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok; + falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error; + falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok; + falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error; + falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok; + falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all; + falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all; + + /*@ + *PHYDM_DBG(dm, DBG_DIG, + * "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + * falm_cnt->cnt_cck_cca, + * falm_cnt->cnt_ofdm_cca, + * falm_cnt->cnt_cca_all); + *PHYDM_DBG(dm, DBG_DIG, + * "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + * falm_cnt->cnt_cck_fail, + * falm_cnt->cnt_ofdm_fail, + * falm_cnt->cnt_all); + */ + if (tdma_dig_block_1sec_flag) { + total_state_number = dm->tdma_dig_state_number; + + if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) { + factor_num = total_state_number; + factor_denum = total_state_number - 1; + } else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) { + factor_num = total_state_number; + factor_denum = 1; + } + + falm_cnt_acc->cnt_all_1sec = + falm_cnt_acc->cnt_all * factor_num / factor_denum; + falm_cnt_acc->cnt_cca_all_1sec = + falm_cnt_acc->cnt_cca_all * factor_num / factor_denum; + falm_cnt_acc->cnt_cck_fail_1sec = + falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum; + + PHYDM_DBG(dm, DBG_DIG, + "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + falm_cnt_acc->cnt_cck_cca, + falm_cnt_acc->cnt_ofdm_cca, + falm_cnt_acc->cnt_cca_all); + PHYDM_DBG(dm, DBG_DIG, + "[ACC FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n\n", + falm_cnt_acc->cnt_cck_fail, + falm_cnt_acc->cnt_ofdm_fail, + falm_cnt_acc->cnt_all); + + } +} +#endif /*@#ifdef IS_USE_NEW_TDMA*/ +#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ + +void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {Damping Limit en}\n"); + #ifdef PHYDM_TDMA_DIG_SUPPORT + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {original_dig_restore = %d}\n", + dm->original_dig_restore); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {tdma_dig_timer_ms = %d}\n", + dm->tdma_dig_timer_ms); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} {tdma_dig_state_number = %d}\n", + dm->tdma_dig_state_number); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{5} {0:L-state,1:H-state} {force IGI} (L,H)=(%2x,%2x)\n", + dig_t->tdma_force_l_igi, dig_t->tdma_force_h_igi); + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "{6} {fw_dig_en}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{7} FA source:{0:original/1:Experimental duration/2:IFS_CLM/3:FAHM}\n"); + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + for (i = 1; i < 10; i++) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + if (var1[0] == 0) { + if (var1[1] == 1) { + dig_t->is_dbg_fa_th = true; + dig_t->fa_th[0] = (u32)var1[2]; + dig_t->fa_th[1] = (u32)var1[3]; + dig_t->fa_th[2] = (u32)var1[4]; + + PDM_SNPF(out_len, used, output + used, + out_len - used, + "Set DIG fa_th[0:2]= {%d, %d, %d}\n", + dig_t->fa_th[0], dig_t->fa_th[1], + dig_t->fa_th[2]); + } else { + dig_t->is_dbg_fa_th = false; + } + #ifdef PHYDM_TDMA_DIG_SUPPORT + } else if (var1[0] == 2) { + dm->original_dig_restore = (u8)var1[1]; + if (dm->original_dig_restore == 1) { + PDM_SNPF(out_len, used, output + used, + out_len - used, "Disable TDMA-DIG\n"); + } else { + PDM_SNPF(out_len, used, output + used, + out_len - used, "Enable TDMA-DIG\n"); + } + } else if (var1[0] == 3) { + dm->tdma_dig_timer_ms = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, + out_len - used, "tdma_dig_timer_ms = %d\n", + dm->tdma_dig_timer_ms); + } else if (var1[0] == 4) { + dm->tdma_dig_state_number = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, + out_len - used, "tdma_dig_state_number = %d\n", + dm->tdma_dig_state_number); + } else if (var1[0] == 5) { + PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]); + if (var1[1] == 0) { + dig_t->tdma_force_l_igi = (u8)var1[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "force L-state IGI = %2x\n", + dig_t->tdma_force_l_igi); + } else if (var1[1] == 1) { + dig_t->tdma_force_h_igi = (u8)var1[2]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "force H-state IGI = %2x\n", + dig_t->tdma_force_h_igi); + } + #endif + } + + #ifdef CFG_DIG_DAMPING_CHK + else if (var1[0] == 1) { + dig_t->dig_dl_en = (u8)var1[1]; + /*@*/ + } + #endif + else if (var1[0] == 6) { + phydm_fw_dm_ctrl_en(dm, F00_DIG, (boolean)var1[1]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "fw_dig_enable = %2x\n", dig_t->fw_dig_enable); + } else if (var1[0] == 7) { + dig_t->fa_source = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "FA source = %d\n", dig_t->fa_source); + } + } + *_used = used; + *_out_len = out_len; +} + +#ifdef CONFIG_MCC_DM +#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT|| RTL8723F_SUPPORT) +void phydm_mcc_igi_clr(void *dm_void, u8 clr_port) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + + mcc_dm->mcc_rssi[clr_port] = 0xff; + mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */ + mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */ +} + +void phydm_mcc_igi_chk(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + + if (mcc_dm->mcc_dm_val[0][0] == 0xff && + mcc_dm->mcc_dm_val[0][1] == 0xff) { + mcc_dm->mcc_dm_reg[0] = 0xffff; + mcc_dm->mcc_reg_id[0] = 0xff; + } + if (mcc_dm->mcc_dm_val[1][0] == 0xff && + mcc_dm->mcc_dm_val[1][1] == 0xff) { + mcc_dm->mcc_dm_reg[1] = 0xffff; + mcc_dm->mcc_reg_id[1] = 0xff; + } +} + +void phydm_mcc_igi_cal(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + u8 shift = 0; + u8 igi_val0, igi_val1; + + if (mcc_dm->mcc_rssi[0] == 0xff) + phydm_mcc_igi_clr(dm, 0); + if (mcc_dm->mcc_rssi[1] == 0xff) + phydm_mcc_igi_clr(dm, 1); + phydm_mcc_igi_chk(dm); + igi_val0 = mcc_dm->mcc_rssi[0] - shift; + igi_val1 = mcc_dm->mcc_rssi[1] - shift; + + if (igi_val0 < DIG_MIN_PERFORMANCE) + igi_val0 = DIG_MIN_PERFORMANCE; + + if (igi_val1 < DIG_MIN_PERFORMANCE) + igi_val1 = DIG_MIN_PERFORMANCE; + + switch (dm->ic_ip_series) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + case PHYDM_IC_JGR3: + phydm_fill_mcccmd(dm, 0, R_0x1d70, igi_val0, igi_val1); + phydm_fill_mcccmd(dm, 1, R_0x1d70 + 1, igi_val0, igi_val1); + break; + #endif + default: + phydm_fill_mcccmd(dm, 0, R_0xc50, igi_val0, igi_val1); + phydm_fill_mcccmd(dm, 1, R_0xe50, igi_val0, igi_val1); + break; + } + + PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n", + mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1], + mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]); +} +#endif /*#if (RTL8822B_SUPPORT)*/ +#endif /*#ifdef CONFIG_MCC_DM*/ diff --git a/hal/phydm/phydm_dig.h b/hal/phydm/phydm_dig.h new file mode 100644 index 0000000..1ccfaa7 --- /dev/null +++ b/hal/phydm/phydm_dig.h @@ -0,0 +1,393 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMDIG_H__ +#define __PHYDMDIG_H__ + +/* 2020.08.13 Add IFS-CLM/FAHM in dig fa source for more accurate fa info*/ +#define DIG_VERSION "3.9" + +#define DIG_HW 0 +#define DIG_LIMIT_PERIOD 60 /*60 sec*/ + +/*@--------------------Define ---------------------------------------*/ + +/*@=== [DIG Boundary] ========================================*/ +/*@DIG coverage mode*/ +#define DIG_MAX_COVERAGR 0x26 +#define DIG_MIN_COVERAGE 0x1c +#define DIG_MAX_OF_MIN_COVERAGE 0x22 + +/*@[DIG Balance mode]*/ +#if (DIG_HW == 1) +#define DIG_MAX_BALANCE_MODE 0x32 +#else +#define DIG_MAX_BALANCE_MODE 0x3e +#endif +#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a + +/*@[DIG Performance mode]*/ +#define DIG_MAX_PERFORMANCE_MODE 0x5a +#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/ +#define DIG_MIN_PERFORMANCE 0x20 + +/*@DIG DFS function*/ +#define DIG_MAX_DFS 0x28 +#define DIG_MIN_DFS 0x20 + +/*@DIG LPS function*/ +#define DIG_MAX_LPS 0x3e +#define DIG_MIN_LPS 0x20 + +#ifdef PHYDM_TDMA_DIG_SUPPORT +#define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/ +#define DIG_TIMER_MS 250 +#define ONE_SEC_MS 1000 +#endif + +/*@=== [DIG FA Threshold] ======================================*/ + +/*Normal*/ +#define DM_DIG_FA_TH0 500 +#define DM_DIG_FA_TH1 750 + +/*@LPS*/ +#define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */ +#define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */ + +#define RSSI_OFFSET_DIG_LPS 5 +#define DIG_RECORD_NUM 4 + +/*==== [FA duration] =======================================*/ +/*[PHYDM-406]*/ +#define OFDM_FA_EXP_DURATION 12 /*us*/ +#define CCK_FA_EXP_DURATION 175 /*us*/ + +/*@--------------------Enum-----------------------------------*/ +enum phydm_dig_mode { + PHYDM_DIG_PERFORAMNCE_MODE = 0, + PHYDM_DIG_COVERAGE_MODE = 1, +}; + +enum phydm_dig_trend { + DIG_STABLE = 0, + DIG_INCREASING = 1, + DIG_DECREASING = 2 +}; + +enum phydm_fw_dig_mode_e { + DIG_PERFORMANCE_MODE = 0, + DIG_COVERAGE_MODE = 1, + DIG_LPS_MODE = 2 +}; + +#ifdef PHYDM_TDMA_DIG_SUPPORT +enum upd_type { + ENABLE_TDMA, + MODE_DECISION +}; + +enum tdma_opmode { + MODE_PERFORMANCE = 1, + MODE_COVERAGE = 2 +}; + +#ifdef IS_USE_NEW_TDMA +enum tdma_dig_timer { + INIT_TDMA_DIG_TIMMER, + CANCEL_TDMA_DIG_TIMMER, + RELEASE_TDMA_DIG_TIMMER +}; + +enum tdma_dig_state { + TDMA_DIG_LOW_STATE = 0, + TDMA_DIG_HIGH_STATE = 1, + NORMAL_DIG = 2 +}; +#endif +#endif + +/*@--------------------Define Struct-----------------------------------*/ +#ifdef CFG_DIG_DAMPING_CHK +struct phydm_dig_recorder_strcut { + u8 igi_bitmap; /*@Don't add any new parameter before this*/ + u8 igi_history[DIG_RECORD_NUM]; + u32 fa_history[DIG_RECORD_NUM]; + u8 damping_limit_en; + u8 damping_limit_val; /*@Limit IGI_dyn_min*/ + u32 limit_time; + u8 limit_rssi; +}; +#endif + +struct phydm_mcc_dig { + u8 mcc_rssi_A; + u8 mcc_rssi_B; +}; + +struct phydm_dig_struct { +#ifdef CFG_DIG_DAMPING_CHK + struct phydm_dig_recorder_strcut dig_recorder_t; + u8 dig_dl_en; /*@damping limit function enable*/ +#endif + boolean fw_dig_enable; + boolean is_dbg_fa_th; + u8 cur_ig_value; + boolean igi_dyn_up_hit; + u8 igi_trend; + u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ + u8 igi_backup; + u8 rx_gain_range_max; /*@dig_dynamic_max*/ + u8 rx_gain_range_min; /*@dig_dynamic_min*/ + u8 dm_dig_max; /*@Absolutly upper bound*/ + u8 dm_dig_min; /*@Absolutly lower bound*/ + u8 dig_max_of_min; /*@Absolutly max of min*/ + u32 ant_div_rssi_max; + u8 *is_p2p_in_process; + u32 fa_th[3]; + u32 dm_dig_fa_th1; + u8 fa_source; +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\ + RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT ||\ + RTL8723F_SUPPORT) + u8 rf_gain_idx; + u8 agc_table_idx; + u8 big_jump_lmt[16]; + u8 enable_adjust_big_jump:1; + u8 big_jump_step1:3; + u8 big_jump_step2:2; + u8 big_jump_step3:2; +#endif + u8 upcheck_init_val; + u8 lv0_ratio_reciprocal; + u8 lv1_ratio_reciprocal; +#ifdef PHYDM_TDMA_DIG_SUPPORT + u8 cur_ig_value_tdma; + u8 low_ig_value; + u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/ + u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/ + u8 pre_tdma_dig_cnt; + u8 sec_factor; + u32 cur_timestamp; + u32 pre_timestamp; + u32 fa_start_timestamp; + u32 fa_end_timestamp; + u32 fa_acc_1sec_timestamp; +#ifdef IS_USE_NEW_TDMA + u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/ + /*@dynamic upper bound for L/H state*/ + u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES]; + /*@dynamic lower bound for L/H state*/ + u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES]; + /*To distinguish current state(L-sate or H-state)*/ +#endif + u8 tdma_force_l_igi; + u8 tdma_force_h_igi; +#endif +}; + +struct phydm_fa_struct { + u32 cnt_parity_fail; + u32 cnt_rate_illegal; + u32 cnt_crc8_fail; + u32 cnt_crc8_fail_vhta; + u32 cnt_crc8_fail_vhtb; + u32 cnt_mcs_fail; + u32 cnt_mcs_fail_vht; + u32 cnt_ofdm_fail; + u32 cnt_ofdm_fail_pre; /* @For RTL8881A */ + u32 cnt_cck_fail; + u32 cnt_all; + u32 cnt_all_accumulated; + u32 cnt_all_pre; + u32 cnt_fast_fsync; + u32 cnt_sb_search_fail; + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_cca_all; + u32 cnt_bw_usc; + u32 cnt_bw_lsc; + u32 cnt_cck_crc32_error; + u32 cnt_cck_crc32_ok; + u32 cnt_ofdm_crc32_error; + u32 cnt_ofdm_crc32_ok; + u32 cnt_ht_crc32_error; + u32 cnt_ht_crc32_ok; + u32 cnt_ht_crc32_error_agg; + u32 cnt_ht_crc32_ok_agg; + u32 cnt_vht_crc32_error; + u32 cnt_vht_crc32_ok; + u32 cnt_crc32_error_all; + u32 cnt_crc32_ok_all; + u32 time_fa_all; + u32 time_fa_exp; /*FA duration, [PHYDM-406]*/ + u32 time_fa_ifs_clm; /*FA duration, [PHYDM-406]*/ + u32 time_fa_fahm; /*FA duration, [PHYDM-406]*/ + boolean cck_block_enable; + boolean ofdm_block_enable; + u32 dbg_port0; + boolean edcca_flag; + u8 ofdm2_rate_idx; + u32 cnt_ofdm2_crc32_error; + u32 cnt_ofdm2_crc32_ok; + u8 ofdm2_pcr; + u8 ht2_rate_idx; + u32 cnt_ht2_crc32_error; + u32 cnt_ht2_crc32_ok; + u8 ht2_pcr; + u8 vht2_rate_idx; + u32 cnt_vht2_crc32_error; + u32 cnt_vht2_crc32_ok; + u8 vht2_pcr; + u32 cnt_cck_txen; + u32 cnt_cck_txon; + u32 cnt_ofdm_txen; + u32 cnt_ofdm_txon; +}; + +#ifdef PHYDM_TDMA_DIG_SUPPORT +struct phydm_fa_acc_struct { + u32 cnt_parity_fail; + u32 cnt_rate_illegal; + u32 cnt_crc8_fail; + u32 cnt_mcs_fail; + u32 cnt_ofdm_fail; + u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/ + u32 cnt_cck_fail; + u32 cnt_all; + u32 cnt_all_pre; + u32 cnt_fast_fsync; + u32 cnt_sb_search_fail; + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_cca_all; + u32 cnt_cck_crc32_error; + u32 cnt_cck_crc32_ok; + u32 cnt_ofdm_crc32_error; + u32 cnt_ofdm_crc32_ok; + u32 cnt_ht_crc32_error; + u32 cnt_ht_crc32_ok; + u32 cnt_vht_crc32_error; + u32 cnt_vht_crc32_ok; + u32 cnt_crc32_error_all; + u32 cnt_crc32_ok_all; + u32 cnt_all_1sec; + u32 cnt_cca_all_1sec; + u32 cnt_cck_fail_1sec; +}; + +#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ + +/*@--------------------Function declaration-----------------------------*/ +void phydm_write_dig_reg(void *dm_void, u8 igi); + +void odm_write_dig(void *dm_void, u8 current_igi); + +u8 phydm_get_igi(void *dm_void, enum bb_path path); + +void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len); + +void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, u8 igi_value); + +#ifdef PHYDM_HW_IGI +void phydm_hwigi(void *dm_void); + +void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif + +void phydm_dig_init(void *dm_void); + +void phydm_dig(void *dm_void); + +void phydm_dig_lps_32k(void *dm_void); + +void phydm_dig_by_rssi_lps(void *dm_void); + +void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min); + +u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi); + +void phydm_false_alarm_counter_statistics(void *dm_void); + +u32 phydm_get_edcca_report(void * dm_void); + +#ifdef PHYDM_TDMA_DIG_SUPPORT +void phydm_set_tdma_dig_timer(void *dm_void); + +void phydm_tdma_dig_timer_check(void *dm_void); + +void phydm_tdma_dig(void *dm_void); + +void phydm_tdma_false_alarm_counter_check(void *dm_void); + +void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void); + +void phydm_false_alarm_counter_reset(void *dm_void); + +void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en); + +void phydm_false_alarm_counter_acc_reset(void *dm_void); + +void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input); + +#ifdef IS_USE_NEW_TDMA +void phydm_tdma_dig_timers(void *dm_void, u8 state); + +void phydm_tdma_dig_cbk(void *dm_void); + +void phydm_tdma_dig_workitem_callback(void *dm_void); + +void phydm_tdma_fa_cnt_chk(void *dm_void); + +void phydm_tdma_low_dig(void *dm_void); + +void phydm_tdma_high_dig(void *dm_void); + +void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en, + u8 cur_tdma_dig_state); +#endif /*@#ifdef IS_USE_NEW_TDMA*/ +#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/ + +void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel); + +void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); + +void phydm_fill_fw_dig_info(void *dm_void, boolean *enable, + u8 *para4, u8 *para8); + +void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +#ifdef CONFIG_MCC_DM +void phydm_mcc_igi_cal(void *dm_void); +#endif + +#endif diff --git a/hal/phydm/phydm_direct_bf.c b/hal/phydm/phydm_direct_bf.c new file mode 100644 index 0000000..55dd2f8 --- /dev/null +++ b/hal/phydm/phydm_direct_bf.c @@ -0,0 +1,366 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ***************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" +#ifdef CONFIG_DIRECTIONAL_BF +#ifdef PHYDM_COMPILE_IC_2SS +void phydm_iq_gen_en(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path i = RF_PATH_A; + enum rf_path path = RF_PATH_A; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) { + for (i = RF_PATH_A; i <= RF_PATH_B; i++) { + /*RF mode table write enable*/ + odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1); + /*Select RX mode*/ + odm_set_rf_reg(dm, path, RF_0x33, 0xF, 3); + /*Set Table data*/ + odm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036); + /*Set Table data*/ + odm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0); + } + } + #endif + + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) { + /*RF mode table write enable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); + /* Path A */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2); + /* Path B */ + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2); + /*RF mode table write disable*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); + } + #endif + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_RTL8197G) { + /*RF mode table write enable*/ + /* Path A */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x000cf); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2); + odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0); + + /* Path B */ + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000cf); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000ef); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042); + odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0); + } + #endif + +} + +void phydm_dis_cdd(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0); + odm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0); + odm_set_bb_reg(dm, R_0x9ac, BIT(13), 1); + } + #endif + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333); + /* Set Tx delay setting for CCK pathA,B*/ + odm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0); + /*Enable Tx CDD for HT part when spatial expansion is applied*/ + odm_set_bb_reg(dm, R_0xd00, BIT(8), 0); + /* Tx CDD for Legacy*/ + odm_set_bb_reg(dm, R_0xd04, 0xf0000, 0); + /* Tx CDD for non-HT*/ + odm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0); + /* Tx CDD for HT SS1*/ + odm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0); + } + #endif + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + /* Tx CDD for Legacy Preamble*/ + odm_set_bb_reg(dm, R_0x1cc0, 0xffffffff, 0x24800000); + /* Tx CDD for HT Preamble*/ + odm_set_bb_reg(dm, R_0x1cb0, 0xffffffff, 0); + } + #endif +} + +void phydm_pathb_q_matrix_rotate_en(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_iq_gen_en(dm); + + /*#ifdef PHYDM_COMMON_API_SUPPORT*/ + /*path selection is controlled by driver*/ + #if 0 + if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB)) + return; + #endif + + phydm_dis_cdd(dm); + phydm_pathb_q_matrix_rotate(dm, 0); + + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + /*Set Q matrix r_v11 =1*/ + odm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000); + /*Set Q matrix enable*/ + odm_set_bb_reg(dm, R_0x191c, BIT(7), 1); + } + #endif +} + +void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + #if (ODM_IC_11AC_SERIES_SUPPORT) + u32 phase_table_0[ANGLE_NUM] = {0x40000, 0x376CF, 0x20000, 0x00000, + 0xFE0000, 0xFC8930, 0xFC0000, + 0xFC8930, 0xFDFFFF, 0x000000, + 0x020000, 0x0376CF}; + u32 phase_table_1[ANGLE_NUM] = {0x00000, 0x1FFFF, 0x376CF, 0x40000, + 0x0376CF, 0x01FFFF, 0x000000, + 0xFDFFFF, 0xFC8930, 0xFC0000, + 0xFC8930, 0xFDFFFF}; + #endif + #if (ODM_IC_11N_SERIES_SUPPORT) + u32 phase_table_n_0[ANGLE_NUM] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02, + 0x04, 0x02, 0x0D, 0x09, 0x04, 0x0B}; + u32 phase_table_n_1[ANGLE_NUM] = {0x40000100, 0x377F00DD, 0x201D8880, + 0x00000000, 0xE01D8B80, 0xC8BF0322, + 0xC000FF00, 0xC8BF0322, 0xDFE2777F, + 0xFFC003FF, 0x20227480, 0x377F00DD}; + u32 phase_table_n_2[ANGLE_NUM] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E, + 0x0F, 0xD2, 0xC3, 0xC4, 0xC3, 0xD2}; + #endif + if (idx >= ANGLE_NUM) { + pr_debug("[%s]warning Phase Set Error: %d\n", __func__, idx); + return; + } + + switch (dm->ic_ip_series) { + #if (ODM_IC_11AC_SERIES_SUPPORT == 1) + case PHYDM_IC_AC: + /*Set Q matrix r_v21*/ + odm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]); + odm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]); + break; + #endif + + #if (ODM_IC_11N_SERIES_SUPPORT == 1) + case PHYDM_IC_N: + /*Set Q matrix r_v21*/ + odm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_n_0[idx]); + odm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_n_1[idx]); + odm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_n_2[idx]); + break; + #endif + + default: + break; + } +} + +/*Before use this API, Fill correct Tx Des. and Disable STBC in advance*/ +void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) { +#if 0 + u8 phi[13] = {0x0, 0x5, 0xa, 0xf, 0x15, 0x1a, 0x1f, 0x25, + 0x2a, 0x2f, 0x35, 0x3a, 0x0}; + u8 psi[13] = {0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, + 0x7, 0x7, 0x7, 0x7}; + u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da, + 0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa, + 0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360 +#endif + u16 ns[3] = {52, 108, 234}; //20/40/80 MHz subcarrier number + u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da, + 0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa, + 0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360 + u16 psiphiR; + u8 i; + u8 snr = 0x12; // for 1SS BF + u8 nc = 0x0; //bit 2-0 + u8 nr = 0x1; //bit 5-3 + u8 ng = 0x0; //bit 7-6 + u8 cb = 0x1; //bit 9-8; 1 => phi:6, psi:4; + u32 bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10 + u8 userid = su_idx; //bit 12 + u32 csi_report = 0x0; + u32 ndp_bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10 + u8 ndp_sc = 0; //bit 11-10 + u32 ndp_info = 0x0; + + u16 mem_num = 0; + u8 mem_move = 0; + u8 mem_sel = 0; + u16 mem_addr = 0; + u32 dw0, dw1; + u64 vm_info = 0; + u64 temp = 0; + u8 vm_cnt = 0; + + mem_num = ((8 + (6 + 4) * ns[bw]) >> 6) + 1; // SU codebook 1 + + /* setting NDP BW/SC info*/ + ndp_info = (ndp_bw & 0x3) | (ndp_bw & 0x3) << 6 | + (ndp_bw & 0x3) << 12 | (ndp_sc & 0xf) << 2 | + (ndp_sc & 0xf) << 8 | (ndp_sc & 0xf) << 14; + odm_set_bb_reg(dm, R_0xb58, 0x000FFFFC, ndp_info); + odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 1); + ODM_delay_ms(1); // delay 1ms + odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 0); + + /* setting CSI report info*/ + csi_report = (userid & 0x1) << 12 | (bw & 0x3) << 10 | + (cb & 0x3) << 8 | (ng & 0x3) << 6 | + (nr & 0x7) << 3 | (nc & 0x7); + odm_set_bb_reg(dm, R_0x72c, 0x1FFF, csi_report); + odm_set_bb_reg(dm, R_0x71c, 0x80000000, 1); + PHYDM_DBG(dm, DBG_TXBF, "[%s] direct BF csi report 0x%x\n", + __func__, csi_report); + /*========================*/ + + odm_set_bb_reg(dm, R_0x19b8, 0x40, 1); //0x19b8[6]:1 to csi_rpt + odm_set_bb_reg(dm, R_0x19e0, 0x3FC0, 0xFF); //gated_clk off + odm_set_bb_reg(dm, R_0x9e8, 0x2000000, 1); //abnormal txbf + odm_set_bb_reg(dm, R_0x9e8, 0x1000000, 0); //read phi psi + odm_set_bb_reg(dm, R_0x9e8, 0x70000000, su_idx); //SU user 0 + odm_set_bb_reg(dm, R_0x1910, 0x8000, 0); //BFer + + dw0 = 0; // for 0x9ec + dw1 = 0; // for 0x1900 + mem_addr = 0; + mem_sel = 0; + mem_move = 0; + vm_info = vm_info | (snr & 0xff); //V matrix info + vm_cnt = 8; // V matrix length counter + psiphiR = (psiphi[phs_idx] & 0x3ff); + + while (mem_addr < mem_num) { + while (vm_cnt <= 32) { + // shift only max. 32 bit + if (vm_cnt >= 20) { + temp = psiphiR << 20; + temp = temp << (vm_cnt - 20); + } else { + temp = psiphiR << vm_cnt; + } + vm_info |= temp; + vm_cnt += 10; + } + if (mem_sel == 0) { + dw0 = vm_info & 0xffffffff; + vm_info = vm_info >> 32; + vm_cnt -= 32; + mem_sel = 1; + mem_move = 0; + } else { + dw1 = vm_info & 0xffffffff; + vm_info = vm_info >> 32; + vm_cnt -= 32; + mem_sel = 0; + mem_move = 1; + } + if (mem_move == 1) { + odm_set_bb_reg(dm, 0x9e8, 0x1000000, 0); + //read phi psi + odm_set_bb_reg(dm, 0x1910, 0x3FF0000, + mem_addr); + odm_set_bb_reg(dm, 0x09ec, 0xFFFFFFFF, dw0); + odm_set_bb_reg(dm, 0x1900, 0xFFFFFFFF, dw1); + odm_set_bb_reg(dm, 0x9e8, 0x1000000, 1); + //write phi psi + mem_move = 0; + mem_addr += 1; + } + } + odm_set_bb_reg(dm, 0x9e8, 0x2000000, 0); //normal txbf + } +#endif +} //end function + +/*Before use this API, Disable STBC in advance*/ +/*only 1SS rate can improve performance*/ +void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) { + phydm_iq_gen_en(dm); + + /*#ifdef PHYDM_COMMON_API_SUPPORT*/ + /*path selection is controlled by driver, use 1ss 2Tx*/ + #if 0 + if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB)) + return; + #endif + + phydm_dis_cdd(dm); + if (enable) + odm_set_bb_reg(dm, R_0x1d90, 0x8000, 1); + else + odm_set_bb_reg(dm, R_0x1d90, 0x8000, 0); + } +#endif +} //end function +#endif +#endif diff --git a/hal/phydm/phydm_direct_bf.h b/hal/phydm/phydm_direct_bf.h new file mode 100644 index 0000000..c9c4c4b --- /dev/null +++ b/hal/phydm/phydm_direct_bf.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_DIR_BF_H__ +#define __PHYDM_DIR_BF_H__ + +#ifdef CONFIG_DIRECTIONAL_BF +#define ANGLE_NUM 12 + +/*@ + * ============================================================ + * function prototype + * ============================================================ + */ +void phydm_iq_gen_en(void *dm_void); +void phydm_dis_cdd(void *dm_void); +void phydm_pathb_q_matrix_rotate_en(void *dm_void); +void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx); +void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx); +void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable); +#endif +#endif diff --git a/hal/phydm/phydm_dynamictxpower.c b/hal/phydm/phydm_dynamictxpower.c new file mode 100644 index 0000000..2ccbd1a --- /dev/null +++ b/hal/phydm/phydm_dynamictxpower.c @@ -0,0 +1,795 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CONFIG_DYNAMIC_TX_TWR +#ifdef BB_RAM_SUPPORT +void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + boolean pwr_ofst0_en = false; + boolean pwr_ofst1_en = false; + s8 pwr_ofst0 = 0; + s8 pwr_ofst1 = 0; + + pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(23)); + pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(31)); + pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f0000); + pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f000000); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "reg0: en:%d, pwr_ofst:0x%x, reg1: en:%d, pwr_ofst:0x%x\n", + pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1); + + *_used = used; + *_out_len = out_len; +}; + +void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en, + s8 pwr_ofst) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl; + u8 reg_0x1e70 = 0; + + if (!is_ofst1) { + bb_ctrl->tx_pwr_ofst_reg0_en = pwr_ofst_en; + bb_ctrl->tx_pwr_ofst_reg0 = pwr_ofst; + + reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f); + odm_set_bb_reg(dm, R_0x1e70, 0x00ff0000, reg_0x1e70); + } else { + bb_ctrl->tx_pwr_ofst_reg1_en = pwr_ofst_en; + bb_ctrl->tx_pwr_ofst_reg1 = pwr_ofst; + + reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f); + odm_set_bb_reg(dm, R_0x1e70, 0xff000000, reg_0x1e70); + } +}; + +void phydm_rd_ram_pwr(void *dm_void, u8 macid, u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + boolean pwr_ofst0_en = false; + boolean pwr_ofst1_en = false; + s8 pwr_ofst0 = 0; + s8 pwr_ofst1 = 0; + u32 reg_0x1e84 = 0; + + reg_0x1e84 |= (macid & 0x3f) << 24; /* macid*/ + reg_0x1e84 |= BIT(31); /* read_en*/ + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84); + + pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(23)); + pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(31)); + pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f0000); + pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f000000); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/ + + PDM_SNPF(out_len, used, output + used, out_len - used, + "(macid:%d) ram0: en:%d, pwr_ofst:0x%x, ram1: en:%d, pwr_ofst:0x%x\n", + macid, pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1); + + *_used = used; + *_out_len = out_len; +}; + +void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1, + boolean pwr_ofst_en, s8 pwr_ofst) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL; + u32 reg_0x1e84 = 0; + boolean pwr_ofst_ano_en = false; + s8 pwr_ofst_ano = 0; + + if (macid > 63) + macid = 63; + + dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid]; + reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) + dm_ram_per_sta->hw_igi; + if (!is_ofst1) { + dm_ram_per_sta->tx_pwr_offset0_en = pwr_ofst_en; + dm_ram_per_sta->tx_pwr_offset0 = pwr_ofst; + + pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset1_en; + pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1; + + reg_0x1e84 |= (pwr_ofst_en << 15) + ((pwr_ofst & 0x7f) << 8) + + (pwr_ofst_ano_en << 23) + + ((pwr_ofst_ano & 0x7f) << 16); + } else { + dm_ram_per_sta->tx_pwr_offset1_en = pwr_ofst_en; + dm_ram_per_sta->tx_pwr_offset1 = pwr_ofst; + + pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset0_en; + pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset0; + + reg_0x1e84 |= (pwr_ofst_ano_en << 15) + + ((pwr_ofst_ano & 0x7f) << 8) + + (pwr_ofst_en << 23) + ((pwr_ofst & 0x7f) << 16); + } + reg_0x1e84 |= (macid & 0x3f) << 24;/* macid*/ + reg_0x1e84 |= BIT(30); /* write_en*/ + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /* read_en*/ + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/ +}; + +void phydm_rst_ram_pwr(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL; + u32 reg_0x1e84 = 0; + u8 i = 0; + + for (i = 0; i < 64; i++) { + dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i]; + dm_ram_per_sta->tx_pwr_offset0_en = false; + dm_ram_per_sta->tx_pwr_offset1_en = false; + dm_ram_per_sta->tx_pwr_offset0 = 0x0; + dm_ram_per_sta->tx_pwr_offset1 = 0x0; + reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) + + dm_ram_per_sta->hw_igi; + reg_0x1e84 |= (i & 0x3f) << 24; + reg_0x1e84 |= BIT(30); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84); + } + + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); + odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); +}; + +u8 phydm_pwr_lv_mapping_2nd(u8 tx_pwr_lv) +{ + if (tx_pwr_lv == tx_high_pwr_level_level3) + return PHYDM_2ND_OFFSET_MINUS_11DB; + else if (tx_pwr_lv == tx_high_pwr_level_level2) + return PHYDM_2ND_OFFSET_MINUS_7DB; + else if (tx_pwr_lv == tx_high_pwr_level_level1) + return PHYDM_2ND_OFFSET_MINUS_3DB; + else + return PHYDM_2ND_OFFSET_ZERO; +} + +void phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 pwr_offset = 0; + + if (tx_pwr_lv == tx_high_pwr_level_level3) + pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_11DB; + else if (tx_pwr_lv == tx_high_pwr_level_level2) + pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_7DB; + else if (tx_pwr_lv == tx_high_pwr_level_level1) + pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_3DB; + else + pwr_offset = PHYDM_BBRAM_OFFSET_ZERO; + + phydm_wt_ram_pwr(dm, macid, RAM_PWR_OFST0, true, pwr_offset); +} + +void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 sta_id, u8 dtp_lvl) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id]; + struct dtp_info *dtp = NULL; + + if (!is_sta_active(sta)) + return; + + dtp = &dm->phydm_sta_info[sta_id]->dtp_stat; + dtp->dyn_tx_power = phydm_pwr_lv_mapping_2nd(dtp_lvl); + phydm_pwr_lv_ctrl(dm, sta->mac_id, dtp_lvl); + + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n", + sta_id, sta->mac_id, dtp->dyn_tx_power); +} + +void phydm_dtp_init_2nd(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + + #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) { + phydm_rst_ram_pwr(dm); + /* rsp tx use type 0*/ + odm_set_mac_reg(dm, R_0x6d8, BIT(19) | BIT(18), RAM_PWR_OFST0); + } + #endif +}; +#endif + +boolean +phydm_check_rates(void *dm_void, u8 rate_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/ + u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/ + u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/ + u32 bitmap_result; + +#if (RTL8822B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8822B) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0xfffff000; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif +#if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif +#if (RTL8192E_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192E) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif +#if (RTL8192F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8192F) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x0fffffff; + } +#endif +#if (RTL8721D_SUPPORT) + if (dm->support_ic_type & ODM_RTL8721D) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0; + check_rate_bitmap0 &= 0x000fffff; + } +#endif +#if (RTL8821C_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821C) { + check_rate_bitmap2 &= 0; + check_rate_bitmap1 &= 0x003ff000; + check_rate_bitmap0 &= 0x000fffff; + } +#endif + if (rate_idx >= 64) + bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2; + else if (rate_idx >= 32) + bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1; + else if (rate_idx <= 31) + bitmap_result = BIT(rate_idx) & check_rate_bitmap0; + + if (bitmap_result != 0) + return true; + else + return false; +} + +enum rf_path +phydm_check_paths(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path max_path = RF_PATH_A; + + if (dm->num_rf_path == 1) + max_path = RF_PATH_A; + if (dm->num_rf_path == 2) + max_path = RF_PATH_B; + if (dm->num_rf_path == 3) + max_path = RF_PATH_C; + if (dm->num_rf_path == 4) + max_path = RF_PATH_D; + + return max_path; +} + +#ifdef PHYDM_COMMON_API_NOT_SUPPORT +u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 ret = 0xff; + + ret = config_phydm_read_txagc_n(dm, path, hw_rate); + + return ret; +} +#endif + +u8 phydm_search_min_power_index(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path path; + enum rf_path max_path; + u8 min_gain_index = 0x3f; + u8 gain_index = 0; + u8 i; + + PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__); + max_path = phydm_check_paths(dm); + for (path = 0; path <= max_path; path++) + for (i = 0; i < 84; i++) + if (phydm_check_rates(dm, i)) { + + if (dm->support_ic_type & PHYDM_COMMON_API_IC) { + #ifdef PHYDM_COMMON_API_SUPPORT + /*97F,8822B,92F,8821C*/ + gain_index = phydm_api_get_txagc(dm, path, i); + #endif + } else { + /*92E*/ + #ifdef PHYDM_COMMON_API_NOT_SUPPORT + gain_index = phydm_dtp_get_txagc(dm, path, i); + #endif + } + + if (gain_index == 0xff) { + min_gain_index = 0x20; + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Error Gain idx!! Rewite to: ((%d))\n", + min_gain_index); + break; + } + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Support Rate: ((%d)) -> Gain idx: ((%d))\n", + i, gain_index); + if (gain_index < min_gain_index) + min_gain_index = gain_index; + } + return min_gain_index; +} + +void phydm_dynamic_tx_power_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 i = 0; + + dm->last_dtp_lvl = tx_high_pwr_level_normal; + dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal; + + switch (dm->ic_ip_series) { + #ifdef BB_RAM_SUPPORT + case PHYDM_IC_JGR3: + dm->set_pwr_th[0] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL1; + dm->set_pwr_th[1] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL2; + dm->set_pwr_th[2] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL3; + phydm_dtp_init_2nd(dm); + break; + #endif + default: + for (i = 0; i < 3; i++) + dm->enhance_pwr_th[i] = 0xff; + + dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1; + dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2; + dm->set_pwr_th[2] = 0xff; + dm->min_power_index = phydm_search_min_power_index(dm); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n", + dm->min_power_index); + break; + } +} + +void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (noisy_state == 0) { + dm->enhance_pwr_th[0] = dm->set_pwr_th[0]; + dm->enhance_pwr_th[1] = dm->set_pwr_th[1]; + dm->enhance_pwr_th[2] = dm->set_pwr_th[2]; + } else { + dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8; + dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5; + dm->enhance_pwr_th[2] = dm->set_pwr_th[2]; + } + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "DTP hp_enhance_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n", + dm->enhance_pwr_th[0], dm->enhance_pwr_th[1], + dm->enhance_pwr_th[2]); +} + +u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi, u8 last_pwr_lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 th[DTP_POWER_LEVEL_SIZE]; + u8 i; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) + th[i] = dm->set_pwr_th[i]; + + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n", + th[0], th[1], th[2]); + + for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) { + if (i >= (last_pwr_lv)) + th[i] += DTP_FLOOR_UP_GAP; + } + + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n", + th[0], th[1], th[2]); + } else { + for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) + th[i] = dm->enhance_pwr_th[i]; + for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) { + if (i >= (last_pwr_lv)) + th[i] += DTP_FLOOR_UP_GAP; + } + } + + if (input_rssi >= th[2]) + return tx_high_pwr_level_level3; + else if (input_rssi < th[2] && input_rssi >= th[1]) + return tx_high_pwr_level_level2; + else if (input_rssi < th[1] && input_rssi >= th[0]) + return tx_high_pwr_level_level1; + else + return tx_high_pwr_level_normal; +} + +u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv) +{ + if (tx_pwr_lv == tx_high_pwr_level_level3) + return PHYDM_OFFSET_MINUS_11DB; + else if (tx_pwr_lv == tx_high_pwr_level_level2) + return PHYDM_OFFSET_MINUS_7DB; + else if (tx_pwr_lv == tx_high_pwr_level_level1) + return PHYDM_OFFSET_MINUS_3DB; + else + return PHYDM_OFFSET_ZERO; +} + +void phydm_dynamic_response_power(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rpwr = 0; + + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + + if (dm->dynamic_tx_high_power_lvl == dm->last_dtp_lvl) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n"); + return; + } + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl, + dm->dynamic_tx_high_power_lvl); + dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl; + rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl); + odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18), + rpwr); + PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n", + dm->dynamic_tx_high_power_lvl); +} + +void phydm_dtp_fill_cmninfo(void *dm_void, u8 sta_id, u8 dtp_lvl) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id]; + struct dtp_info *dtp = NULL; + + if (!is_sta_active(sta)) + return; + + dtp = &sta->dtp_stat; + dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl); + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n", + sta_id, sta->mac_id, dtp->dyn_tx_power); +} + +void phydm_dtp_per_sta(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct dtp_info *dtp = NULL; + struct rssi_info *rssi = NULL; + struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl; + u8 sta_cnt = 0; + u8 i = 0; + u8 curr_pwr_lv = 0; + u8 last_pwr_lv = 0; + u8 mac_id_cnt = 0; + u64 macid_cur = 0; + u64 macid_diff = 0; + u64 macid_mask = 0; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + dtp = &sta->dtp_stat; + rssi = &sta->rssi_stat; + macid_mask = (u64)BIT(sta->mac_id); + if (!(bb_ctrl->macid_is_linked & macid_mask)) + dtp->sta_last_dtp_lvl = tx_high_pwr_level_normal; + + last_pwr_lv = dtp->sta_last_dtp_lvl; + curr_pwr_lv = phydm_pwr_lvl_check(dm, rssi->rssi, + last_pwr_lv); + dtp->sta_tx_high_power_lvl = curr_pwr_lv; + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "STA_id=%d, MACID=%d , RSSI: %d , GetPwrLv: %d\n", + i, sta->mac_id, rssi->rssi, curr_pwr_lv); + + bb_ctrl->macid_is_linked |= macid_mask; + macid_cur |= macid_mask; + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "macid_is_linked: (0x%llx), macid_cur: (0x%llx)\n", + bb_ctrl->macid_is_linked, macid_cur); + + if (curr_pwr_lv == last_pwr_lv && dtp->sta_is_alive) { + dtp->sta_tx_high_power_lvl = last_pwr_lv; + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "DTP_lv not change: ((%d))\n", + curr_pwr_lv); + } else { + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "DTP_lv update: ((%d)) -> ((%d))\n", + last_pwr_lv, curr_pwr_lv); + + dtp->sta_last_dtp_lvl = curr_pwr_lv; + + switch (dm->ic_ip_series) { + #ifdef BB_RAM_SUPPORT + case PHYDM_IC_JGR3: + phydm_dtp_fill_cmninfo_2nd(dm, i, curr_pwr_lv); + break; + #endif + default: + phydm_dtp_fill_cmninfo(dm, i, curr_pwr_lv); + break; + } + if(!dtp->sta_is_alive) + dtp->sta_is_alive = true; + } + + if (sta_cnt == dm->number_linked_client) + break; + } + } + + macid_diff = bb_ctrl->macid_is_linked ^ macid_cur; + if (macid_diff) + bb_ctrl->macid_is_linked &= ~macid_diff; + while (macid_diff) { + if (macid_diff & 0x1) + phydm_pwr_lv_ctrl(dm, mac_id_cnt, tx_high_pwr_level_normal); + mac_id_cnt++; + macid_diff >>= 1; + } +} + +void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 sta_id) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id]; + struct dtp_info *dtp = NULL; + + if (!is_sta_active(sta)) + return; + dtp = &sta->dtp_stat; + + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + + if (dm->fill_desc_dyntxpwr) + dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power); + else + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "%s: fill_desc_dyntxpwr is null!\n", __func__); + + if (dtp->last_tx_power != dtp->dyn_tx_power) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "%s: last_offset=%d, txpwr_offset=%d\n", __func__, + dtp->last_tx_power, dtp->dyn_tx_power); + dtp->last_tx_power = dtp->dyn_tx_power; + } +} + +void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + u32 used = *_used; + u32 out_len = *_out_len; + + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[7] = {0}; + u8 set_pwr_th1, set_pwr_th2, set_pwr_th3; + u8 i = 0; + #ifdef BB_RAM_SUPPORT + s8 pwr_ofst_tmp = 0x0; + #endif + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set DTP threhosld: {1} {Lv1_th} {Lv2_th} {Lv3_th}\n"); + #ifdef BB_RAM_SUPPORT + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set pwr_tx_offset: {2} {0:reg 1:macid} {en} {offset 0/1} {0:-, 1:+} {Pwr Offset} {macid}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Read pwr_tx_offset : {3} {0:reg 1:macid} {macid(0~63), 255:all}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Reset all ram pwr_tx_offset : {4}\n"); + #endif + } else { + for (i = 0; i < 7; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + switch (var1[0]) { + case 1: + for (i = 0; i < 3; i++) { + if (var1[i] == 0 || var1[i] > 100) + dm->set_pwr_th[i] = 0xff; + else + dm->set_pwr_th[i] = (u8)var1[1 + i]; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "DTP_TH[0:2] = {%d, %d, %d}\n", + dm->set_pwr_th[0], dm->set_pwr_th[1], + dm->set_pwr_th[2]); + break; + #ifdef BB_RAM_SUPPORT + case 2: + if ((boolean)var1[4]) + pwr_ofst_tmp = (s8)var1[5]; + else + pwr_ofst_tmp = 0x0 - (s8)var1[5]; + + if ((boolean)var1[1]) + phydm_wt_ram_pwr(dm, (u8)var1[6], + (boolean)var1[3], + (boolean)var1[2], + pwr_ofst_tmp); + else + phydm_wt_reg_pwr(dm, (boolean)var1[3], + (boolean)var1[2], + pwr_ofst_tmp); + break; + case 3: + if ((boolean)var1[1]) { + if ((u8)var1[2] == 0xff) + for (i = 0; i < 64; i++) + phydm_rd_ram_pwr(dm, i, &used, + output, + &out_len); + else + phydm_rd_ram_pwr(dm, (u8)var1[2], &used, + output, &out_len); + } else { + phydm_rd_reg_pwr(dm, &used, output, &out_len); + } + break; + case 4: + phydm_rst_ram_pwr(dm); + break; + #endif + } + } + *_used = used; + *_out_len = out_len; +} + +void phydm_dynamic_tx_power(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + u8 i = 0; + + u8 rssi_min = dm->rssi_min; + u8 rssi_tmp = 0; + + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) { + PHYDM_DBG(dm, DBG_DYN_TXPWR, + "[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__, + rssi_min, dm->noisy_decision); + phydm_noisy_enhance_hp_th(dm, dm->noisy_decision); + /* Response Power */ + dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, + rssi_min, + dm->last_dtp_lvl); + phydm_dynamic_response_power(dm); + } + /* Per STA Tx power */ + phydm_dtp_per_sta(dm); +} +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void phydm_dynamic_tx_power_init_win(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter); + + mgnt_info->bDynamicTxPowerEnable = false; + #if DEV_BUS_TYPE == RT_USB_INTERFACE + if (RT_GetInterfaceSelection((PADAPTER)adapter) == + INTF_SEL1_USB_High_Power) { + mgnt_info->bDynamicTxPowerEnable = true; + } + #endif + + hal_data->LastDTPLvl = tx_high_pwr_level_normal; + hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal; + + PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__, + mgnt_info->bDynamicTxPowerEnable); +} + +void phydm_dynamic_tx_power_win(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR)) + return; + + #if (RTL8814A_SUPPORT) + if (dm->support_ic_type == ODM_RTL8814A) + odm_dynamic_tx_power_8814a(dm); + #endif + + #if (RTL8821A_SUPPORT) + if (dm->support_ic_type & ODM_RTL8821) { + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter); + + if (mgnt_info->RegRspPwr == 1) { + if (dm->rssi_min > 60) { + /*Resp TXAGC offset = -3dB*/ + odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 1); + } else if (dm->rssi_min < 55) { + /*Resp TXAGC offset = 0dB*/ + odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 0); + } + } + } + #endif +} +#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ +#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */ diff --git a/hal/phydm/phydm_dynamictxpower.h b/hal/phydm/phydm_dynamictxpower.h new file mode 100644 index 0000000..88be431 --- /dev/null +++ b/hal/phydm/phydm_dynamictxpower.h @@ -0,0 +1,142 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMDYNAMICTXPOWER_H__ +#define __PHYDMDYNAMICTXPOWER_H__ + +#ifdef CONFIG_DYNAMIC_TX_TWR +/* @============================================================ + * Definition + * ============================================================ + */ + +/* 2020.6.23, Let gain_idx be initialized to 0 for linux compile warning*/ +#define DYNAMIC_TXPWR_VERSION "2.1" + +#define DTP_POWER_LEVEL_SIZE 3 + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60 +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 80 +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 63 +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 55 +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90 +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85 +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80 +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90 +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85 +#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80 +#endif + +#define tx_high_pwr_level_normal 0 +#define tx_high_pwr_level_level1 1 +#define tx_high_pwr_level_level2 2 +#define tx_high_pwr_level_level3 3 +#define tx_high_pwr_level_unchange 4 +#define DTP_FLOOR_UP_GAP 3 + +/* @============================================================ + * enumrate + * ============================================================ + */ +enum phydm_dtp_power_offset { + PHYDM_OFFSET_ZERO = 0, + PHYDM_OFFSET_MINUS_3DB = 1, + PHYDM_OFFSET_MINUS_7DB = 2, + PHYDM_OFFSET_MINUS_11DB = 3, + PHYDM_OFFSET_ADD_3DB = 4, + PHYDM_OFFSET_ADD_6DB = 5 +}; + +enum phydm_dtp_power_offset_2nd { + PHYDM_2ND_OFFSET_ZERO = 0, + PHYDM_2ND_OFFSET_MINUS_3DB = 1, + PHYDM_2ND_OFFSET_MINUS_7DB = 2, + PHYDM_2ND_OFFSET_MINUS_11DB = 3 +}; + +enum phydm_dtp_power_offset_bbram { + /*@ HW min use 1dB*/ + PHYDM_BBRAM_OFFSET_ZERO = 0, + PHYDM_BBRAM_OFFSET_MINUS_3DB = -3, + PHYDM_BBRAM_OFFSET_MINUS_7DB = -7, + PHYDM_BBRAM_OFFSET_MINUS_11DB = -11 +}; + +enum phydm_dtp_power_pkt_type { + RAM_PWR_OFST0 = 0, + RAM_PWR_OFST1 = 1, + REG_PWR_OFST0 = 2, + REG_PWR_OFST1 = 3 +}; + +/* @============================================================ + * structure + * ============================================================ + */ + +/* @============================================================ + * Function Prototype + * ============================================================ + */ + +extern void +odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id); + +void phydm_dynamic_tx_power(void *dm_void); + +void phydm_dynamic_tx_power_init(void *dm_void); + +void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); + +void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len); + +void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en, + s8 pwr_ofst); + +void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1, + boolean pwr_ofst_en, s8 pwr_ofst); + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void odm_dynamic_tx_power_win(void *dm_void); +#endif + +#endif +#endif diff --git a/hal/phydm/phydm_features.h b/hal/phydm/phydm_features.h new file mode 100644 index 0000000..bbbc9ed --- /dev/null +++ b/hal/phydm/phydm_features.h @@ -0,0 +1,82 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_H__ +#define __PHYDM_FEATURES_H__ + +#define CONFIG_RUN_IN_DRV +#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | \ + ODM_RTL8710B | \ + ODM_RTL8192F | \ + ODM_RTL8821C | \ + ODM_RTL8822B | \ + ODM_RTL8721D | \ + ODM_RTL8723D | \ + ODM_RTL8710C) +#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) +#define ODM_DYM_BW_INDICATION_SUPPORT (ODM_RTL8821C | \ + ODM_RTL8822B | \ + ODM_RTL8822C) + +/*@20170103 YuChen add for FW API*/ +#define PHYDM_FW_API_ENABLE_8822B 1 +#define PHYDM_FW_API_FUNC_ENABLE_8822B 1 +#define PHYDM_FW_API_ENABLE_8821C 1 +#define PHYDM_FW_API_FUNC_ENABLE_8821C 1 +#define PHYDM_FW_API_ENABLE_8195B 1 +#define PHYDM_FW_API_FUNC_ENABLE_8195B 1 +#define PHYDM_FW_API_ENABLE_8198F 1 +#define PHYDM_FW_API_FUNC_ENABLE_8198F 1 +#define PHYDM_FW_API_ENABLE_8822C 1 +#define PHYDM_FW_API_FUNC_ENABLE_8822C 1 +#define PHYDM_FW_API_ENABLE_8814B 1 +#define PHYDM_FW_API_FUNC_ENABLE_8814B 1 +#define PHYDM_FW_API_ENABLE_8812F 1 +#define PHYDM_FW_API_FUNC_ENABLE_8812F 1 +#define PHYDM_FW_API_ENABLE_8197G 1 +#define PHYDM_FW_API_FUNC_ENABLE_8197G 1 +#define PHYDM_FW_API_ENABLE_8723F 1 +#define PHYDM_FW_API_FUNC_ENABLE_8723F 1 + +#define CONFIG_POWERSAVING 0 + +#ifdef BEAMFORMING_SUPPORT +#if (BEAMFORMING_SUPPORT) + #define PHYDM_BEAMFORMING_SUPPORT +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "phydm_features_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "phydm_features_ce.h" + /*@#include "phydm_features_ce2_kernel.h"*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "phydm_features_ap.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #include "phydm_features_iot.h" +#endif + +#endif diff --git a/hal/phydm/phydm_features_ap.h b/hal/phydm/phydm_features_ap.h new file mode 100644 index 0000000..38a0eeb --- /dev/null +++ b/hal/phydm/phydm_features_ap.h @@ -0,0 +1,227 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_AP_H__ +#define __PHYDM_FEATURES_AP_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\ + RTL8197G_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8198F_SUPPORT || RTL8814B_SUPPORT ||\ + RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT) + #define FAHM_SUPPORT +#endif + +#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT) + #define IFS_CLM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8812F_SUPPORT) + /*#define PHYDM_PHYSTAUS_AUTO_SWITCH*/ +#endif + +#if (RTL8197F_SUPPORT) + /*#define PHYDM_TDMA_DIG_SUPPORT*/ +#endif + +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\ + RTL8197G_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_TDMA_DIG_SUPPORT 1 + #ifdef PHYDM_TDMA_DIG_SUPPORT + #define IS_USE_NEW_TDMA /*new tdma dig test*/ + #endif +#endif + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT) + #define PHYDM_LNA_SAT_CHK_SUPPORT + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + + #if (RTL8197F_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT) + #define PHYDM_LNA_SAT_CHK_TYPE1 + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT) + /*#define PHYDM_POWER_TRAINING_SUPPORT*/ +#endif + +#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_PMAC_TX_SETTING_SUPPORT +#endif + +#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_MP_SUPPORT +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + /*#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +#if (RTL8192F_SUPPORT == 1) + /*#define CONFIG_8912F_SPUR_CALIBRATION*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + /* #define CONFIG_8822B_SPUR_CALIBRATION */ +#endif + +#if (RTL8197G_SUPPORT) + #define CONFIG_DIRECTIONAL_BF +#endif + +#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT) + #define CONFIG_DYNAMIC_TX_TWR +#endif + +#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT) + #define PHYDM_HW_IGI +#endif + +#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT) + #define CONFIG_DYNAMIC_TXCOLLISION_TH +#endif + +/*#define CONFIG_PSD_TOOL*/ +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +/*#define CONFIG_RA_DYNAMIC_RATE_ID*/ +#define CONFIG_BB_TXBF_API +/*#define ODM_CONFIG_BT_COEXIST*/ +#define PHYDM_SUPPORT_RSSI_MONITOR +#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION) + #define CONFIG_PHYDM_DEBUG_FUNCTION +#endif + +/* [ Configure Antenna Diversity ] */ +#if (RTL8188F_SUPPORT) + #ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif +#endif + +#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) || defined(CONFIG_RTL_8197G_ANT_SWITCH) + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define ODM_EVM_ENHANCE_ANTDIV + /*#define SKIP_EVM_ANTDIV_TRAINING_PATCH*/ + + /*----------*/ + #ifdef CONFIG_NO_2G_DIVERSITY_8197F + #define CONFIG_NO_2G_DIVERSITY + #elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F) + #define CONFIG_2G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F) + #define CONFIG_2G_CG_TRX_DIVERSITY + #endif + + /*----------*/ + #ifdef CONFIG_NO_2G_DIVERSITY_8197G + #define CONFIG_NO_2G_DIVERSITY + #elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197G) + #define CONFIG_2G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197G) + #define CONFIG_2G_CG_TRX_DIVERSITY + #endif + + #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_2G_DIVERSITY + #endif + + #ifdef CONFIG_NO_5G_DIVERSITY_8881A + #define CONFIG_NO_5G_DIVERSITY + #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) + #define CONFIG_5G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_5G_CG_TRX_DIVERSITY + #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_2G5G_CG_TRX_DIVERSITY + #endif + #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_5G_DIVERSITY + #endif + /*----------*/ + #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_NOT_SUPPORT_ANTDIV + #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_2G_SUPPORT_ANTDIV + #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_5G_SUPPORT_ANTDIV + #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) + #define CONFIG_2G5G_SUPPORT_ANTDIV + #endif + /*----------*/ +#endif /*Antenna Diveristy*/ + +/*[SmartAntenna]*/ +/*#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +#define CFG_DIG_DAMPING_CHK +/* --------------------------------------------------*/ +#ifdef PHYDM_BEAMFORMING_SUPPORT + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8814B_SUPPORT || RTL8812F_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#endif diff --git a/hal/phydm/phydm_features_ce.h b/hal/phydm/phydm_features_ce.h new file mode 100644 index 0000000..24f3772 --- /dev/null +++ b/hal/phydm/phydm_features_ce.h @@ -0,0 +1,245 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_CE_H__ +#define __PHYDM_FEATURES_CE_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8814B_SUPPORT || RTL8723F_SUPPORT) + #define FAHM_SUPPORT +#endif + +#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT) + #define IFS_CLM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822C_SUPPORT) + #define NHM_DYM_PW_TH_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + /*@#define PHYDM_PHYSTAUS_AUTO_SWITCH*/ +#endif + +/*@#define PHYDM_TDMA_DIG_SUPPORT*/ + +#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8723D_SUPPORT ) + #ifdef CONFIG_TDMADIG + #define PHYDM_TDMA_DIG_SUPPORT + #ifdef PHYDM_TDMA_DIG_SUPPORT + #define IS_USE_NEW_TDMA /*new tdma dig test*/ + #endif + #endif +#endif + +#if (RTL8814B_SUPPORT) + /*@#define PHYDM_TDMA_DIG_SUPPORT*/ + #ifdef PHYDM_TDMA_DIG_SUPPORT + /*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/ + #endif +#endif + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + + #if (RTL8197F_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + + #if (RTL8814B_SUPPORT) + /*@#define PHYDM_LNA_SAT_CHK_TYPE1*/ + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8723D_SUPPORT) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_PMAC_TX_SETTING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_MP_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + #define PHYDM_CCK_RX_PATHDIV_SUPPORT +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define CONFIG_RECEIVER_BLOCKING +#endif + +#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT) + #define CONFIG_BW_INDICATION +#endif + +#if (RTL8192F_SUPPORT) + /*#define CONFIG_8912F_SPUR_CALIBRATION*/ +#endif + +#if (RTL8822B_SUPPORT) + #define CONFIG_8822B_SPUR_CALIBRATION +#endif + +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR +#define CONFIG_DYNAMIC_TX_TWR +#endif +#if (RTL8822C_SUPPORT) +#define PHYDM_HW_IGI +#endif +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY + +/*@Antenna Diversity*/ +#ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\ + RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8723D_SUPPORT||RTL8723F_SUPPORT) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT) + /*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_PATH_DIVERSITY +#endif + +/*@[SmartAntenna]*/ +/*@#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*@#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +/* @--------------------------------------------------*/ + +#ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + /*@#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +#define CONFIG_PSD_TOOL +/*@#define CONFIG_ANT_DETECTION*/ +/*@#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_BB_TXBF_API +#define CONFIG_PHYDM_DEBUG_FUNCTION + +#ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST +#endif +#define PHYDM_SUPPORT_RSSI_MONITOR +#define PHYDM_AUTO_DEGBUG +#define CFG_DIG_DAMPING_CHK + + +#ifdef PHYDM_BEAMFORMING_SUPPORT + #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8814A_SUPPORT || RTL8881A_SUPPORT) + #define PHYDM_BEAMFORMING_VERSION1 + #endif + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT) + #ifdef CONFIG_MCC_MODE + #define CONFIG_MCC_DM + #endif +#endif + +#if (RTL8822B_SUPPORT) + #ifdef CONFIG_DYNAMIC_BYPASS_MODE + #define CONFIG_DYNAMIC_BYPASS + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_DIRECTIONAL_BF +#endif + +#if (RTL8822C_SUPPORT) + #define CONFIG_MU_RSOML +#endif + +#endif diff --git a/hal/phydm/phydm_features_ce2_kernel.h b/hal/phydm/phydm_features_ce2_kernel.h new file mode 100644 index 0000000..c206ea6 --- /dev/null +++ b/hal/phydm/phydm_features_ce2_kernel.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_CE_H__ +#define __PHYDM_FEATURES_CE_H__ + +#define PHYDM_LA_MODE_SUPPORT 0 + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8192F_SUPPORT == 1) + /*#define CONFIG_8912F_SPUR_CALIBRATION*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + /* #define CONFIG_8822B_SPUR_CALIBRATION */ +#endif + +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY + +#ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER +#endif + +#define CONFIG_BB_TXBF_API +#define CONFIG_PHYDM_DEBUG_FUNCTION + +#ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST +#endif +#define PHYDM_SUPPORT_RSSI_MONITOR +#define CFG_DIG_DAMPING_CHK + + +#ifdef PHYDM_BEAMFORMING_SUPPORT + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#endif diff --git a/hal/phydm/phydm_features_iot.h b/hal/phydm/phydm_features_iot.h new file mode 100644 index 0000000..ce8793e --- /dev/null +++ b/hal/phydm/phydm_features_iot.h @@ -0,0 +1,177 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_IOT_H__ +#define __PHYDM_FEATURES_IOT_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8195B_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT) + #define FAHM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +/*#define PHYDM_TDMA_DIG_SUPPORT*/ + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + #if (RTL8197F_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_PMAC_TX_SETTING_SUPPORT */ +#endif + +#if (RTL8822C_SUPPORT) + /* #define PHYDM_MP_SUPPORT */ +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8822B_SUPPORT) + /*#define CONFIG_DYNAMIC_RX_PATH*/ +#endif + +#if (RTL8822B_SUPPORT == 1) + /* #define CONFIG_8822B_SPUR_CALIBRATION */ +#endif + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define CONFIG_RECEIVER_BLOCKING +#endif + +#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR +#define CONFIG_DYNAMIC_TX_TWR +#endif +#define PHYDM_SUPPORT_CCKPD +#define PHYDM_SUPPORT_ADAPTIVITY + +/*Antenna Diversity*/ +#ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\ + RTL8188F_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8710C_SUPPORT) + //#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + #endif +#endif + +/*[SmartAntenna]*/ +/*#define CONFIG_SMART_ANTENNA*/ +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif +/* --------------------------------------------------*/ + +#ifdef CONFIG_DFS_MASTER + #define CONFIG_PHYDM_DFS_MASTER +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + /*#define CONFIG_RA_FW_DBG_CODE*/ +#endif + +#define CONFIG_PSD_TOOL +/*#define CONFIG_RA_DBG_CMD*/ +/*#define CONFIG_ANT_DETECTION*/ +/*#define CONFIG_PATH_DIVERSITY*/ +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +//#define CONFIG_BB_TXBF_API +#if DBG +#define CONFIG_PHYDM_DEBUG_FUNCTION +#endif + +#ifdef CONFIG_BT_COEXIST + #define ODM_CONFIG_BT_COEXIST +#endif +#define PHYDM_SUPPORT_RSSI_MONITOR +/*#define PHYDM_AUTO_DEGBUG*/ +#define CFG_DIG_DAMPING_CHK + +#ifdef PHYDM_BEAMFORMING_SUPPORT + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #define CONFIG_BB_TXBF_API + #endif +#endif + +#endif diff --git a/hal/phydm/phydm_features_win.h b/hal/phydm/phydm_features_win.h new file mode 100644 index 0000000..824699e --- /dev/null +++ b/hal/phydm/phydm_features_win.h @@ -0,0 +1,215 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#ifndef __PHYDM_FEATURES_WIN_H__ +#define __PHYDM_FEATURES_WIN_H__ + +#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_LA_MODE_SUPPORT 1 +#else + #define PHYDM_LA_MODE_SUPPORT 0 +#endif + +#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\ + RTL8192F_SUPPORT) + #define DYN_ANT_WEIGHTING_SUPPORT +#endif + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8814B_SUPPORT || RTL8723F_SUPPORT) + #define FAHM_SUPPORT +#endif + +#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT) + #define IFS_CLM_SUPPORT +#endif + #define NHM_SUPPORT + #define CLM_SUPPORT + +#if (RTL8822C_SUPPORT) + #define NHM_DYM_PW_TH_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + #define PHYDM_PHYSTAUS_AUTO_SWITCH +#endif + +/*#define PHYDM_TDMA_DIG_SUPPORT*/ + +#if (RTL8814B_SUPPORT) + /*#define PHYDM_TDMA_DIG_SUPPORT*/ + #ifdef PHYDM_TDMA_DIG_SUPPORT + /*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/ + #endif +#endif + +#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT*/ + #ifdef PHYDM_LNA_SAT_CHK_SUPPORT + + #if (RTL8197F_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/ + #endif + + #if (RTL8822B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE2*/ + #endif + + #if (RTL8814B_SUPPORT) + /*#define PHYDM_LNA_SAT_CHK_TYPE1*/ + #endif + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\ + RTL8192F_SUPPORT) + #define PHYDM_POWER_TRAINING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_PMAC_TX_SETTING_SUPPORT +#endif + +#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_MP_SUPPORT +#endif + +#if (RTL8822C_SUPPORT) + #define PHYDM_CCK_RX_PATHDIV_SUPPORT +#endif + +#if (RTL8822B_SUPPORT) + #define PHYDM_TXA_CALIBRATION +#endif + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define PHYDM_PRIMARY_CCA +#endif + +#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT) + #define PHYDM_DC_CANCELLATION +#endif + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_ADAPTIVE_SOML +#endif + +#if (RTL8192F_SUPPORT) + #define CONFIG_8912F_SPUR_CALIBRATION +#endif + +/*Antenna Diversity*/ +#define CONFIG_PHYDM_ANTENNA_DIVERSITY +#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\ + RTL8821C_SUPPORT || RTL8723D_SUPPORT) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8822B_SUPPORT) + /*#define ODM_EVM_ENHANCE_ANTDIV*/ + /*#define CONFIG_2T3R_ANTENNA*/ + /*#define CONFIG_2T4R_ANTENNA*/ + #endif + + /* --[SmtAnt]-----------------------------------------*/ + #if (RTL8821A_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #define CONFIG_FAT_PATCH + #endif + + #if (RTL8822B_SUPPORT) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/ + #endif + + #if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2)) + #define CONFIG_HL_SMART_ANTENNA + #endif + + /* --------------------------------------------------*/ + +#endif + +#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT) + #define CONFIG_PATH_DIVERSITY +#endif + +/*[SmartAntenna]*/ +#define CONFIG_SMART_ANTENNA +#ifdef CONFIG_SMART_ANTENNA + /*#define CONFIG_CUMITEK_SMART_ANTENNA*/ +#endif + /* --------------------------------------------------*/ + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT) + #define CONFIG_RECEIVER_BLOCKING +#endif + +#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT) + #define CONFIG_BW_INDICATION +#endif + +#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8192E_SUPPORT || RTL8723B_SUPPORT) + #define CONFIG_RA_FW_DBG_CODE +#endif + +/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */ +#define CONFIG_DYNAMIC_TX_TWR +/* #endif */ +#if (RTL8822C_SUPPORT) +#define PHYDM_HW_IGI +#endif +#define CONFIG_PSD_TOOL +#define PHYDM_SUPPORT_ADAPTIVITY +#define PHYDM_SUPPORT_CCKPD +#if (defined(PHYDM_SUPPORT_CCKPD) && RTL8822C_SUPPORT) + #define PHYDM_DCC_ENHANCE +#endif +/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ +#define CONFIG_ANT_DETECTION +#define CONFIG_BB_TXBF_API +#define ODM_CONFIG_BT_COEXIST +#define CONFIG_PHYDM_DFS_MASTER +#define PHYDM_SUPPORT_RSSI_MONITOR +#define PHYDM_AUTO_DEGBUG +#define CONFIG_PHYDM_DEBUG_FUNCTION +#define CFG_DIG_DAMPING_CHK + +#ifdef PHYDM_BEAMFORMING_SUPPORT + #if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8814A_SUPPORT || RTL8881A_SUPPORT) + #define PHYDM_BEAMFORMING_VERSION1 + #endif + #if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\ + RTL8822C_SUPPORT || RTL8814B_SUPPORT) + #define DRIVER_BEAMFORMING_VERSION2 + #endif +#endif + +#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT) + /*#define CONFIG_DIRECTIONAL_BF*/ +#endif + +#if (RTL8822C_SUPPORT) + #define CONFIG_MU_RSOML +#endif + +#endif diff --git a/hal/phydm/phydm_hwconfig.c b/hal/phydm/phydm_hwconfig.c new file mode 100644 index 0000000..d3153b5 --- /dev/null +++ b/hal/phydm/phydm_hwconfig.c @@ -0,0 +1,1681 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(dm)) +#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(dm)) + +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define READ_AND_CONFIG(ic, txt) \ + do { \ + if (dm->is_mp_chip) \ + READ_AND_CONFIG_MP(ic, txt); \ + else \ + READ_AND_CONFIG_TC(ic, txt); \ + } while (0) +#else +#define READ_AND_CONFIG READ_AND_CONFIG_MP +#endif + +#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt()) +#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt()) + +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define GET_VERSION(ic, txt) (dm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt)) +#else +#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt) +#endif + +enum hal_status +odm_config_rf_with_header_file(struct dm_struct *dm, + enum odm_rf_config_type config_type, + u8 e_rf_path) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; +#endif + enum hal_status result = HAL_STATUS_SUCCESS; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__, + (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); + +/* @1 AP doesn't use PHYDM power tracking table in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8812a, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8812a, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + if ((hal_data->EEPROMSVID == 0x17AA && hal_data->EEPROMSMID == 0xA811) || + (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0xA812) || + (hal_data->EEPROMSVID == 0x10EC && hal_data->EEPROMSMID == 0x8812)) + READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03); + else +#endif + READ_AND_CONFIG_MP(8812a, _txpwr_lmt); + } + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8821a, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (dm->support_interface == ODM_ITRF_USB) { + if (dm->ext_pa_5g || dm->ext_lna_5g) + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem); + else + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa); + } else { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB) + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm); + else if (mgnt_info->CustomerID == RT_CID_ASUS_NB) + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm); + else +#endif + READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a); + } + } + } +#endif +#if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192E) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8192e, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8192e, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ + HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + if ((hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8192) || + (hal_data->EEPROMSVID == 0x11AD && hal_data->EEPROMSMID == 0x8193)) + READ_AND_CONFIG_MP(8192e, _txpwr_lmt_8192e_sar_5mm); + else +#endif + READ_AND_CONFIG_MP(8192e, _txpwr_lmt); + } + } +#endif +#if (RTL8723D_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8723D) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8723d, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + READ_AND_CONFIG_MP(8723d, _txpwr_lmt); + } + } +#endif +/* @JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8710B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8710b, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8710b, _txpwr_lmt); + } +#endif + +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +/* @1 All platforms support */ +#if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8188e, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188e, _txpwr_lmt); + } +#endif +#if (RTL8723B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8723B) { + if (config_type == CONFIG_RF_RADIO) + READ_AND_CONFIG_MP(8723b, _radioa); + else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8723b, _txpwr_lmt); + } +#endif +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8814a, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8814a, _radiob); + else if (e_rf_path == RF_PATH_C) + READ_AND_CONFIG_MP(8814a, _radioc); + else if (e_rf_path == RF_PATH_D) + READ_AND_CONFIG_MP(8814a, _radiod); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type3); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type5); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type8); + else + READ_AND_CONFIG_MP(8814a, _txpwr_lmt); + } + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8703B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8703b, _radioa); + } + } +#endif +#if (RTL8188F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8188f, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188f, _txpwr_lmt); + } +#endif +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8822b, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8822b, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type5); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type4); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type12); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type18); + //else if (dm->rfe_type == 19) + //READ_AND_CONFIG_MP(8822b, _txpwr_lmt_type19); + else + READ_AND_CONFIG_MP(8822b, _txpwr_lmt); + } + } +#endif + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8197f, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8197f, _radiob); + } + } +#endif +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8192f, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8192f, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type5); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type6); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type8); + else if (dm->rfe_type == 9) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type9); + else if (dm->rfe_type == 10) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type10); + else if (dm->rfe_type == 11) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type11); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type18); + else if (dm->rfe_type == 19) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type19); + else if (dm->rfe_type == 20) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type20); + else if (dm->rfe_type == 21) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type21); + else if (dm->rfe_type == 22) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type22); + else if (dm->rfe_type == 23) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type23); + else if (dm->rfe_type == 24) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type24); + else if (dm->rfe_type == 25) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type25); + else if (dm->rfe_type == 26) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type26); + else if (dm->rfe_type == 27) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type27); + else if (dm->rfe_type == 28) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type28); + else if (dm->rfe_type == 29) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type29); + else if (dm->rfe_type == 30) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type30); + else if (dm->rfe_type == 31) + READ_AND_CONFIG_MP(8192f, _txpwr_lmt_type31); + else + READ_AND_CONFIG_MP(8192f, _txpwr_lmt); + } + } +#endif +#if (RTL8721D_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8721D) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8721d, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (dm->power_voltage == ODM_POWER_18V) + READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type0); + else + READ_AND_CONFIG_MP(8721d, _txpwr_lmt_type1); + } + } +#endif + +#if (RTL8710C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8710C) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8710c, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8710c, _txpwr_lmt); + } +#endif + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG(8821c, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + READ_AND_CONFIG(8821c, _txpwr_lmt); + } + } +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG(8195b, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + READ_AND_CONFIG(8195b, _txpwr_lmt); + } + } +#endif +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8198f, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8198f, _radiob); + else if (e_rf_path == RF_PATH_C) + READ_AND_CONFIG_MP(8198f, _radioc); + else if (e_rf_path == RF_PATH_D) + READ_AND_CONFIG_MP(8198f, _radiod); + } + } +#endif +/*#if (RTL8814B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8814b, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8814b, _radiob); + else if (e_rf_path == RF_PATH_C) + READ_AND_CONFIG_MP(8814b, _radioc); + else if (e_rf_path == RF_PATH_D) + READ_AND_CONFIG_MP(8814b, _radiod); + } + } +#endif +*/ +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822C) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8822c, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8822c, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8822c, _txpwr_lmt_type5); + else + READ_AND_CONFIG_MP(8822c, _txpwr_lmt); + } + } +#endif +#if (RTL8723F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8723F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8723f, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8723f, _radiob); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + READ_AND_CONFIG_MP(8723f, _txpwr_lmt); + } + } +#endif +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812F) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8812f, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8812f, _radiob); + } + } +#endif +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type == ODM_RTL8197G) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8197g, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8197g, _radiob); + } + } +#endif + + /*8814B need review, when phydm has related files*/ + #if (RTL8814B_SUPPORT) + if (dm->support_ic_type == ODM_RTL8814B) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == RF_PATH_A) + READ_AND_CONFIG_MP(8814b, _radioa); + else if (e_rf_path == RF_PATH_B) + READ_AND_CONFIG_MP(8814b, _radiob); + else if (e_rf_path == RF_PATH_C) + READ_AND_CONFIG_MP(8814b, _radioc); + else if (e_rf_path == RF_PATH_D) + READ_AND_CONFIG_MP(8814b, _radiod); + } + if (config_type == CONFIG_RF_SYN_RADIO) { + if (e_rf_path == RF_SYN0) + READ_AND_CONFIG_MP(8814b, _radiosyn0); + else if (e_rf_path == RF_SYN1) + READ_AND_CONFIG_MP(8814b, _radiosyn1); + } else if (config_type == CONFIG_RF_TXPWR_LMT) { + READ_AND_CONFIG_MP(8814b, _txpwr_lmt); + } + } + #endif + + if (config_type == CONFIG_RF_RADIO) { + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + (enum rf_path)0, + 0); + PHYDM_DBG(dm, ODM_COMP_INIT, + "rf param offload end!result = %d", result); + } + } + + return result; +} + +enum hal_status +odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm) +{ + PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__, + (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); + +/* @1 AP doesn't use PHYDM power tracking table in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if RTL8821A_SUPPORT + if (dm->support_ic_type == ODM_RTL8821) { + if (dm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie); + else if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8821a, _txpowertrack_usb); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio); + } +#endif +#if RTL8812A_SUPPORT + if (dm->support_ic_type == ODM_RTL8812) { + if (dm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie); + else if (dm->support_interface == ODM_ITRF_USB) { + if (dm->rfe_type == 3 && dm->is_mp_chip) + READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3); + else + READ_AND_CONFIG_MP(8812a, _txpowertrack_usb); + } + } +#endif +#if RTL8192E_SUPPORT + if (dm->support_ic_type == ODM_RTL8192E) { + if (dm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8192e, _txpowertrack_pcie); + else if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8192e, _txpowertrack_usb); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8192e, _txpowertrack_sdio); + } +#endif +#if RTL8723D_SUPPORT + if (dm->support_ic_type == ODM_RTL8723D) { + if (dm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8723d, _txpowertrack_pcie); + else if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8723d, _txpowertrack_usb); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8723d, _txpowertrack_sdio); + + READ_AND_CONFIG_MP(8723d, _txxtaltrack); + } +#endif +/* @JJ ADD 20161014 */ +#if RTL8710B_SUPPORT + if (dm->support_ic_type == ODM_RTL8710B) { + if (dm->package_type == 1) + READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_smic); + else if (dm->package_type == 5) + READ_AND_CONFIG_MP(8710b, _txpowertrack_qfn48m_umc); + + READ_AND_CONFIG_MP(8710b, _txxtaltrack); + } +#endif +#if RTL8188E_SUPPORT + if (dm->support_ic_type == ODM_RTL8188E) { + if (odm_get_mac_reg(dm, R_0xf0, 0xF000) >= 8) { /*@if 0xF0[15:12] >= 8, SMIC*/ + if (dm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie_icut); + else if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188e, _txpowertrack_usb_icut); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio_icut); + } else { /*@else 0xF0[15:12] < 8, TSMC*/ + if (dm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8188e, _txpowertrack_pcie); + else if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188e, _txpowertrack_usb); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188e, _txpowertrack_sdio); + } + } +#endif +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +/* @1 All platforms support */ +#if RTL8723B_SUPPORT + if (dm->support_ic_type == ODM_RTL8723B) { + if (dm->support_interface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8723b, _txpowertrack_pcie); + else if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8723b, _txpowertrack_usb); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8723b, _txpowertrack_sdio); + } +#endif +#if RTL8814A_SUPPORT + if (dm->support_ic_type == ODM_RTL8814A) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type0); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type2); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type5); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a, _txpowertrack_type8); + else + READ_AND_CONFIG_MP(8814a, _txpowertrack); + + READ_AND_CONFIG_MP(8814a, _txpowertssi); + } +#endif +#if RTL8703B_SUPPORT + if (dm->support_ic_type == ODM_RTL8703B) { + if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8703b, _txpowertrack_usb); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8703b, _txpowertrack_sdio); + + READ_AND_CONFIG_MP(8703b, _txxtaltrack); + } +#endif +#if RTL8188F_SUPPORT + if (dm->support_ic_type == ODM_RTL8188F) { + if (dm->support_interface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188f, _txpowertrack_usb); + else if (dm->support_interface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188f, _txpowertrack_sdio); + } +#endif +#if RTL8822B_SUPPORT + if (dm->support_ic_type == ODM_RTL8822B) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type2); + else if ((dm->rfe_type == 3) || (dm->rfe_type == 5)) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type3_type5); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type4); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type6); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type8); + else if (dm->rfe_type == 9) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type9); + else if (dm->rfe_type == 10) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type10); + else if (dm->rfe_type == 11) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type11); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8822b, _txpowertrack_type18); + //else if (dm->rfe_type == 19) + //READ_AND_CONFIG_MP(8822b, _txpowertrack_type19); + else + READ_AND_CONFIG_MP(8822b, _txpowertrack); + } +#endif +#if RTL8197F_SUPPORT + if (dm->support_ic_type == ODM_RTL8197F) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8197f, _txpowertrack_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8197f, _txpowertrack_type1); + else + READ_AND_CONFIG_MP(8197f, _txpowertrack); + } +#endif +/*@jj add 20170822*/ +#if RTL8192F_SUPPORT + if (dm->support_ic_type == ODM_RTL8192F) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type5); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type6); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type8); + else if (dm->rfe_type == 9) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type9); + else if (dm->rfe_type == 10) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type10); + else if (dm->rfe_type == 11) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type11); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type18); + else if (dm->rfe_type == 19) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type19); + else if (dm->rfe_type == 20) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type20); + else if (dm->rfe_type == 21) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type21); + else if (dm->rfe_type == 22) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type22); + else if (dm->rfe_type == 23) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type23); + else if (dm->rfe_type == 24) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type24); + else if (dm->rfe_type == 25) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type25); + else if (dm->rfe_type == 26) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type26); + else if (dm->rfe_type == 27) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type27); + else if (dm->rfe_type == 28) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type28); + else if (dm->rfe_type == 29) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type29); + else if (dm->rfe_type == 30) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type30); + else if (dm->rfe_type == 31) + READ_AND_CONFIG_MP(8192f, _txpowertrack_type31); + else + READ_AND_CONFIG_MP(8192f, _txpowertrack); + + READ_AND_CONFIG_MP(8192f, _txxtaltrack); + } +#endif + +#if RTL8721D_SUPPORT + if (dm->support_ic_type == ODM_RTL8721D) { + #if 0 + if (dm->package_type == 1) + READ_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_smic); + else if (dm->package_type == 5) + READ_AND_CONFIG_MP(8721d, _txpowertrack_qfn48m_umc); + #endif + READ_AND_CONFIG_MP(8721d, _txpowertrack); + READ_AND_CONFIG_MP(8721d, _txxtaltrack); + } +#endif + +#if RTL8710C_SUPPORT + if (dm->support_ic_type == ODM_RTL8710C) { + #if 0 + if (dm->package_type == 1) + READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_smic); + else if (dm->package_type == 5) + READ_AND_CONFIG_MP(8710c, _txpowertrack_qfn48m_umc); + #endif + READ_AND_CONFIG_MP(8710c, _txpowertrack); + READ_AND_CONFIG_MP(8710c, _txxtaltrack); + } +#endif + +#if RTL8821C_SUPPORT + if (dm->support_ic_type == ODM_RTL8821C) { + if (dm->rfe_type == 0x5) + READ_AND_CONFIG(8821c, _txpowertrack_type0x28); + else if (dm->rfe_type == 0x4) + READ_AND_CONFIG(8821c, _txpowertrack_type0x20); + else + READ_AND_CONFIG(8821c, _txpowertrack); + } +#endif + +#if RTL8198F_SUPPORT + if (dm->support_ic_type == ODM_RTL8198F) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8198f, _txpowertrack_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8198f, _txpowertrack_type1); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8198f, _txpowertrack_type3); + else + READ_AND_CONFIG_MP(8198f, _txpowertrack); + } +#endif + +#if RTL8195B_SUPPORT + if (dm->support_ic_type == ODM_RTL8195B) { + if (dm->package_type == 1) { + READ_AND_CONFIG_MP(8195b, _txpowertrack_pkg1); + READ_AND_CONFIG_MP(8195b, _txxtaltrack_pkg1); + } else { + READ_AND_CONFIG_MP(8195b, _txpowertrack); + READ_AND_CONFIG_MP(8195b, _txxtaltrack); + } + } +#endif + +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822C) { + if (dm->en_tssi_mode) + READ_AND_CONFIG_MP(8822c, _txpowertracktssi); + else + READ_AND_CONFIG_MP(8822c, _txpowertrack); + } +#endif + +#if (RTL8723F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8723F) { + if (dm->en_tssi_mode) + READ_AND_CONFIG_MP(8723f, _txpowertracktssi); + else + READ_AND_CONFIG_MP(8723f, _txpowertrack); + READ_AND_CONFIG_MP(8723f, _txxtaltrack); + } +#endif +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812F) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8812f, _txpowertrack_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8812f, _txpowertrack_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8812f, _txpowertrack_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8812f, _txpowertrack_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8812f, _txpowertrack_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8812f, _txpowertrack_type5); + else + READ_AND_CONFIG_MP(8812f, _txpowertrack); + } +#endif + +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type == ODM_RTL8197G) + READ_AND_CONFIG_MP(8197g, _txpowertrack); +#endif + +#if RTL8814B_SUPPORT + if (dm->support_ic_type == ODM_RTL8814B) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8814b, _txpowertrack_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8814b, _txpowertrack_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8814b, _txpowertrack_type2); +#if 0 + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8814b, _txpowertrack_type3); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8814b, _txpowertrack_type6); +#endif + else + READ_AND_CONFIG_MP(8814b, _txpowertrack); + } +#endif + + return HAL_STATUS_SUCCESS; +} + +enum hal_status +odm_config_bb_with_header_file(struct dm_struct *dm, + enum odm_bb_config_type config_type) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo; +#endif + enum hal_status result = HAL_STATUS_SUCCESS; + +/* @1 AP doesn't use PHYDM initialization in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8812a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8812a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 3 && dm->is_mp_chip) + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus); +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + else if (mgnt_info->CustomerID == RT_CID_WNC_NEC && dm->is_mp_chip) + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec); +#if RT_PLATFORM == PLATFORM_MACOSX + /*@{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/ + else if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni); + /* TP-Link T4UH, Isaiah 2015-03-16*/ + else if (mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) { + pr_debug("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n"); + READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink); + } +#endif +#endif + else + READ_AND_CONFIG_MP(8812a, _phy_reg_pg); + } else if (config_type == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG_MP(8812a, _phy_reg_mp); + else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { + dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + /*@AGC_TAB DIFF dont support FW offload*/ + if ((*dm->channel >= 36) && (*dm->channel <= 64)) + AGC_DIFF_CONFIG_MP(8812a, lb); + else if (*dm->channel >= 100) + AGC_DIFF_CONFIG_MP(8812a, hb); + } + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8821a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8821a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE * hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + if ((hal_data->EEPROMSVID == 0x1043 && hal_data->EEPROMSMID == 0x207F)) + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa); + else +#endif +#if (RT_PLATFORM == PLATFORM_MACOSX) + /*@ for BUFFALO pwr by rate table */ + if (mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) { + /*@ for BUFFALO pwr by rate table (JP/US)*/ + if (mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G) + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us); + else + READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp); + } else +#endif +#endif + READ_AND_CONFIG_MP(8821a, _phy_reg_pg); + } + } +#endif +#if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192E) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8192e, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8192e, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8192e, _phy_reg_pg); + } +#endif +#if (RTL8723D_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8723D) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8723d, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8723d, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8723d, _phy_reg_pg); + } +#endif +/* @JJ ADD 20161014 */ +#if (RTL8710B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8710B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8710b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8710b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8710b, _phy_reg_pg); + } +#endif + +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +/* @1 All platforms support */ +#if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188e, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188e, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188e, _phy_reg_pg); + } +#endif +#if (RTL8723B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8723B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8723b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8723b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8723b, _phy_reg_pg); + } +#endif +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8814a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8814a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type0); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type5); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type8); + else + READ_AND_CONFIG_MP(8814a, _phy_reg_pg); + } else if (config_type == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG_MP(8814a, _phy_reg_mp); + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8703B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8703b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8703b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8703b, _phy_reg_pg); + } +#endif +#if (RTL8188F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188F) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188f, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188f, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188f, _phy_reg_pg); + } +#endif +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + if (config_type == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8822b, _phy_reg); + } else if (config_type == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG_MP(8822b, _agc_tab); + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type5); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type12); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type18); + //else if (dm->rfe_type == 19) + //READ_AND_CONFIG_MP(8822b, _phy_reg_pg_type19); + else + READ_AND_CONFIG_MP(8822b, _phy_reg_pg); + } + } +#endif + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + if (config_type == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8197f, _phy_reg); + if (dm->cut_version == ODM_CUT_A) + phydm_phypara_a_cut(dm); + } else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8197f, _agc_tab); + } +#endif +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + if (config_type == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG_MP(8192f, _phy_reg); + } else if (config_type == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG_MP(8192f, _agc_tab); + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 0) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type0); + else if (dm->rfe_type == 1) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type1); + else if (dm->rfe_type == 2) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type2); + else if (dm->rfe_type == 3) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type3); + else if (dm->rfe_type == 4) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type4); + else if (dm->rfe_type == 5) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type5); + else if (dm->rfe_type == 6) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type6); + else if (dm->rfe_type == 7) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type7); + else if (dm->rfe_type == 8) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type8); + else if (dm->rfe_type == 9) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type9); + else if (dm->rfe_type == 10) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type10); + else if (dm->rfe_type == 11) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type11); + else if (dm->rfe_type == 12) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type12); + else if (dm->rfe_type == 13) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type13); + else if (dm->rfe_type == 14) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type14); + else if (dm->rfe_type == 15) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type15); + else if (dm->rfe_type == 16) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type16); + else if (dm->rfe_type == 17) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type17); + else if (dm->rfe_type == 18) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type18); + else if (dm->rfe_type == 19) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type19); + else if (dm->rfe_type == 20) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type20); + else if (dm->rfe_type == 21) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type21); + else if (dm->rfe_type == 22) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type22); + else if (dm->rfe_type == 23) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type23); + else if (dm->rfe_type == 24) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type24); + else if (dm->rfe_type == 25) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type25); + else if (dm->rfe_type == 26) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type26); + else if (dm->rfe_type == 27) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type27); + else if (dm->rfe_type == 28) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type28); + else if (dm->rfe_type == 29) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type29); + else if (dm->rfe_type == 30) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type30); + else if (dm->rfe_type == 31) + READ_AND_CONFIG_MP(8192f, _phy_reg_pg_type31); + else + READ_AND_CONFIG_MP(8192f, _phy_reg_pg); + } + } +#endif +#if (RTL8721D_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8721D) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8721d, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8721d, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->power_voltage == ODM_POWER_18V) + READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type0); + else + READ_AND_CONFIG_MP(8721d, _phy_reg_pg_type1); + } + } +#endif + +#if (RTL8710C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8710C) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8710c, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8710c, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8710c, _phy_reg_pg); + } +#endif + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG(8821c, _phy_reg); + } else if (config_type == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG(8821c, _agc_tab); + /* @According to RFEtype, choosing correct AGC table*/ + if (dm->default_rf_set_8821c == SWITCH_TO_BTG) + AGC_DIFF_CONFIG_MP(8821c, btg); + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 0x5) + READ_AND_CONFIG(8821c, _phy_reg_pg_type0x28); + else + READ_AND_CONFIG(8821c, _phy_reg_pg); + } else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { + dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD; + /*@AGC_TAB DIFF dont support FW offload*/ + if (dm->current_rf_set_8821c == SWITCH_TO_BTG) + AGC_DIFF_CONFIG_MP(8821c, btg); + else if (dm->current_rf_set_8821c == SWITCH_TO_WLG) + AGC_DIFF_CONFIG_MP(8821c, wlg); + } else if (config_type == CONFIG_BB_PHY_REG_MP) { + READ_AND_CONFIG(8821c, _phy_reg_mp); + } + } +#endif + +#if (RTL8195A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195A) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG(8195a, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG(8195a, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8195a, _phy_reg_pg); + } +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) { + if (config_type == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG(8195b, _phy_reg); + } else if (config_type == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG(8195b, _agc_tab); + } else if (config_type == CONFIG_BB_PHY_REG_PG) { + READ_AND_CONFIG(8195b, _phy_reg_pg); + } else if (config_type == CONFIG_BB_PHY_REG_MP) { + if (dm->package_type == 1) + odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x10); + else + odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, 0x12); + } + } +#endif +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8198f, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8198f, _agc_tab); + } +#endif +#if (RTL8814B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814B) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8814b, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8814b, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) { + if (dm->rfe_type == 1) + READ_AND_CONFIG(8814b, _phy_reg_pg_type1); + else + READ_AND_CONFIG(8814b, _phy_reg_pg); + } + } +#endif +#if (RTL8822C_SUPPORT) + if (dm->support_ic_type == ODM_RTL8822C) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8822c, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8822c, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8822c, _phy_reg_pg); + } +#endif +#if (RTL8723F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8723F) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8723f, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8723f, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8723f, _phy_reg_pg); + } +#endif +#if (RTL8812F_SUPPORT) + if (dm->support_ic_type == ODM_RTL8812F) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8812f, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8812f, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8812f, _phy_reg_pg); + } +#endif +#if (RTL8197G_SUPPORT) + if (dm->support_ic_type == ODM_RTL8197G) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8197g, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8197g, _agc_tab); + else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8197g, _phy_reg_pg); + } +#endif + + if (config_type == CONFIG_BB_PHY_REG || + config_type == CONFIG_BB_AGC_TAB) + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + (enum rf_path)0, + 0); + PHYDM_DBG(dm, ODM_COMP_INIT, + "phy param offload end!result = %d", result); + } + + return result; +} + +enum hal_status +odm_config_mac_with_header_file(struct dm_struct *dm) +{ + enum hal_status result = HAL_STATUS_SUCCESS; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===>%s (%s)\n", __func__, + (dm->is_mp_chip) ? "MPChip" : "TestChip"); + PHYDM_DBG(dm, ODM_COMP_INIT, + "support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n", + dm->support_platform, dm->support_interface, dm->board_type); + +#ifdef PHYDM_IC_HALMAC_PARAM_SUPPORT + if (dm->support_ic_type & PHYDM_IC_SUPPORT_HALMAC_PARAM_OFFLOAD) { + PHYDM_DBG(dm, ODM_COMP_INIT, "MAC para-package in HALMAC\n"); + return result; + } +#endif + +/* @1 AP doesn't use PHYDM initialization in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) + READ_AND_CONFIG_MP(8812a, _mac_reg); +#endif +#if (RTL8821A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821) + READ_AND_CONFIG_MP(8821a, _mac_reg); +#endif +#if (RTL8192E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192E) + READ_AND_CONFIG_MP(8192e, _mac_reg); +#endif +#if (RTL8723D_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8723D) + READ_AND_CONFIG_MP(8723d, _mac_reg); +#endif +#if (RTL8710B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8710B) + READ_AND_CONFIG_MP(8710b, _mac_reg); +#endif +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ + +/* @1 All platforms support */ +#if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + READ_AND_CONFIG_MP(8188e, _mac_reg); +#endif +#if (RTL8723B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8723B) + READ_AND_CONFIG_MP(8723b, _mac_reg); +#endif +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) + READ_AND_CONFIG_MP(8814a, _mac_reg); +#endif +#if (RTL8703B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8703B) + READ_AND_CONFIG_MP(8703b, _mac_reg); +#endif +#if (RTL8188F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188F) + READ_AND_CONFIG_MP(8188f, _mac_reg); +#endif +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + READ_AND_CONFIG_MP(8822b, _mac_reg); +#endif +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) + READ_AND_CONFIG_MP(8197f, _mac_reg); +#endif +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) + READ_AND_CONFIG_MP(8192f, _mac_reg); +#endif +#if (RTL8721D_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8721D) + READ_AND_CONFIG_MP(8721d, _mac_reg); +#endif + +#if (RTL8710C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8710C) + READ_AND_CONFIG_MP(8710c, _mac_reg); +#endif + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + READ_AND_CONFIG(8821c, _mac_reg); +#endif +#if (RTL8195A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195A) + READ_AND_CONFIG_MP(8195a, _mac_reg); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + READ_AND_CONFIG_MP(8195b, _mac_reg); +#endif +#if (RTL8198F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8198F) + READ_AND_CONFIG_MP(8198f, _mac_reg); +#endif +#if (RTL8197G_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197G) + READ_AND_CONFIG_MP(8197g, _mac_reg); +#endif + + if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) { + result = phydm_set_reg_by_fw(dm, + PHYDM_HALMAC_CMD_END, + 0, + 0, + 0, + (enum rf_path)0, + 0); + PHYDM_DBG(dm, ODM_COMP_INIT, + "mac param offload end!result = %d", result); + } + + return result; +} + +u32 odm_get_hw_img_version(struct dm_struct *dm) +{ + u32 version = 0; + + switch (dm->support_ic_type) { +/* @1 AP doesn't use PHYDM initialization in these ICs */ +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8821A_SUPPORT) + case ODM_RTL8821: + version = odm_get_version_mp_8821a_phy_reg(); + break; +#endif +#if (RTL8192E_SUPPORT) + case ODM_RTL8192E: + version = odm_get_version_mp_8192e_phy_reg(); + break; +#endif +#if (RTL8812A_SUPPORT) + case ODM_RTL8812: + version = odm_get_version_mp_8812a_phy_reg(); + break; +#endif +#endif /* @(DM_ODM_SUPPORT_TYPE != ODM_AP) */ +#if (RTL8723D_SUPPORT) + case ODM_RTL8723D: + version = odm_get_version_mp_8723d_phy_reg(); + break; +#endif +#if (RTL8710B_SUPPORT) + case ODM_RTL8710B: + version = odm_get_version_mp_8710b_phy_reg(); + break; +#endif +#if (RTL8188E_SUPPORT) + case ODM_RTL8188E: + version = odm_get_version_mp_8188e_phy_reg(); + break; +#endif +#if (RTL8723B_SUPPORT) + case ODM_RTL8723B: + version = odm_get_version_mp_8723b_phy_reg(); + break; +#endif +#if (RTL8814A_SUPPORT) + case ODM_RTL8814A: + version = odm_get_version_mp_8814a_phy_reg(); + break; +#endif +#if (RTL8703B_SUPPORT) + case ODM_RTL8703B: + version = odm_get_version_mp_8703b_phy_reg(); + break; +#endif +#if (RTL8188F_SUPPORT) + case ODM_RTL8188F: + version = odm_get_version_mp_8188f_phy_reg(); + break; +#endif +#if (RTL8822B_SUPPORT) + case ODM_RTL8822B: + version = odm_get_version_mp_8822b_phy_reg(); + break; +#endif +#if (RTL8197F_SUPPORT) + case ODM_RTL8197F: + version = odm_get_version_mp_8197f_phy_reg(); + break; +#endif + +#if (RTL8192F_SUPPORT) + case ODM_RTL8192F: + version = odm_get_version_mp_8192f_phy_reg(); + break; +#endif +#if (RTL8721D_SUPPORT) + case ODM_RTL8721D: + version = odm_get_version_mp_8721d_phy_reg(); + break; +#endif +#if (RTL8710C_SUPPORT) + case ODM_RTL8710C: + version = GET_VERSION_MP(8710c, _mac_reg); +#endif +#if (RTL8821C_SUPPORT) + case ODM_RTL8821C: + version = odm_get_version_mp_8821c_phy_reg(); + break; +#endif +#if (RTL8195B_SUPPORT) + case ODM_RTL8195B: + version = odm_get_version_mp_8195b_phy_reg(); + break; +#endif +#if (RTL8198F_SUPPORT) + case ODM_RTL8198F: + version = odm_get_version_mp_8198f_phy_reg(); + break; +#endif +#if (RTL8822C_SUPPORT) + case ODM_RTL8822C: + version = odm_get_version_mp_8822c_phy_reg(); + break; +#endif +#if (RTL8812F_SUPPORT) + case ODM_RTL8812F: + version = odm_get_version_mp_8812f_phy_reg(); + break; +#endif +#if (RTL8197G_SUPPORT) + case ODM_RTL8197G: + version = odm_get_version_mp_8197g_phy_reg(); + break; +#endif +#if (RTL8723F_SUPPORT) + case ODM_RTL8723F: + version = odm_get_version_mp_8723f_phy_reg(); + break; +#endif +#if (RTL8814B_SUPPORT) + case ODM_RTL8814B: + version = odm_get_version_mp_8814b_phy_reg(); + break; +#endif + } + + return version; +} + +u32 query_phydm_trx_capability(struct dm_struct *dm) +{ + u32 value32 = 0xFFFFFFFF; + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_trx_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_trx_capability_8195b(dm); +#endif + return value32; +} + +u32 query_phydm_stbc_capability(struct dm_struct *dm) +{ + u32 value32 = 0xFFFFFFFF; + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_stbc_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_stbc_capability_8195b(dm); +#endif + + return value32; +} + +u32 query_phydm_ldpc_capability(struct dm_struct *dm) +{ + u32 value32 = 0xFFFFFFFF; + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_ldpc_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_ldpc_capability_8195b(dm); +#endif + return value32; +} + +u32 query_phydm_txbf_parameters(struct dm_struct *dm) +{ + u32 value32 = 0xFFFFFFFF; + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_parameters_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_txbf_parameters_8195b(dm); +#endif + return value32; +} + +u32 query_phydm_txbf_capability(struct dm_struct *dm) +{ + u32 value32 = 0xFFFFFFFF; + +#if (RTL8821C_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_capability_8821c(dm); +#endif +#if (RTL8195B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8195B) + value32 = query_phydm_txbf_capability_8195b(dm); +#endif + return value32; +} diff --git a/hal/phydm/phydm_hwconfig.h b/hal/phydm/phydm_hwconfig.h new file mode 100644 index 0000000..7c4d1e3 --- /dev/null +++ b/hal/phydm/phydm_hwconfig.h @@ -0,0 +1,79 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + +/*@--------------------------Define -------------------------------------------*/ +#define AGC_DIFF_CONFIG_MP(ic, band) \ + (odm_read_and_config_mp_##ic##_agc_tab_diff(dm, \ + array_mp_##ic##_agc_tab_diff_##band, \ + sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32))) +#define AGC_DIFF_CONFIG_TC(ic, band) \ + (odm_read_and_config_tc_##ic##_agc_tab_diff(dm, \ + array_tc_##ic##_agc_tab_diff_##band, \ + sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32))) +#if defined(DM_ODM_CE_MAC80211) +#else +#define AGC_DIFF_CONFIG(ic, band) \ + do { \ + if (dm->is_mp_chip) \ + AGC_DIFF_CONFIG_MP(ic, band); \ + else \ + AGC_DIFF_CONFIG_TC(ic, band); \ + } while (0) +#endif +/*@************************************************************ + * structure and define + ************************************************************/ + +enum hal_status +odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm); + +enum hal_status +odm_config_rf_with_header_file(struct dm_struct *dm, + enum odm_rf_config_type config_type, + u8 e_rf_path); + +enum hal_status +odm_config_bb_with_header_file(struct dm_struct *dm, + enum odm_bb_config_type config_type); + +enum hal_status +odm_config_mac_with_header_file(struct dm_struct *dm); + +u32 odm_get_hw_img_version(struct dm_struct *dm); + +u32 query_phydm_trx_capability(struct dm_struct *dm); + +u32 query_phydm_stbc_capability(struct dm_struct *dm); + +u32 query_phydm_ldpc_capability(struct dm_struct *dm); + +u32 query_phydm_txbf_parameters(struct dm_struct *dm); + +u32 query_phydm_txbf_capability(struct dm_struct *dm); + +#endif /*@#ifndef __HALHWOUTSRC_H__*/ diff --git a/hal/phydm/phydm_interface.c b/hal/phydm/phydm_interface.c new file mode 100644 index 0000000..7a0c428 --- /dev/null +++ b/hal/phydm/phydm_interface.c @@ -0,0 +1,1480 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/*@ + * ODM IO Relative API. + */ + +u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct rtl8192cd_priv *priv = dm->priv; + return RTL_R8(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_read_byte(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read8(rtwdev, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + return rtw_read8(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + return PlatformEFIORead1Byte(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + return rtw_read8(adapter, reg_addr); +#endif +} + +u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct rtl8192cd_priv *priv = dm->priv; + return RTL_R16(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_read_word(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read16(rtwdev, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + return rtw_read16(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + return PlatformEFIORead2Byte(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + return rtw_read16(adapter, reg_addr); +#endif +} + +u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct rtl8192cd_priv *priv = dm->priv; + return RTL_R32(reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_read_dword(rtlpriv, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read32(rtwdev, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + return rtw_read32(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + return PlatformEFIORead4Byte(adapter, reg_addr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + return rtw_read32(adapter, reg_addr); +#endif +} + +void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct rtl8192cd_priv *priv = dm->priv; + RTL_W8(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_write_byte(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write8(rtwdev, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + rtw_write8(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformEFIOWrite1Byte(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + rtw_write8(adapter, reg_addr, data); +#endif + + if (dm->en_reg_mntr_byte) + pr_debug("1byte:addr=0x%x, data=0x%x\n", reg_addr, data); +} + +void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct rtl8192cd_priv *priv = dm->priv; + RTL_W16(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_write_word(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write16(rtwdev, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + rtw_write16(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformEFIOWrite2Byte(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + rtw_write16(adapter, reg_addr, data); +#endif + + if (dm->en_reg_mntr_byte) + pr_debug("2byte:addr=0x%x, data=0x%x\n", reg_addr, data); +} + +void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct rtl8192cd_priv *priv = dm->priv; + RTL_W32(reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_write_dword(rtlpriv, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write32(rtwdev, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + rtw_write32(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformEFIOWrite4Byte(adapter, reg_addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + rtw_write32(adapter, reg_addr, data); +#endif + + if (dm->en_reg_mntr_byte) + pr_debug("4byte:addr=0x%x, data=0x%x\n", reg_addr, data); +} + +void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PHY_SetBBReg(adapter, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); +#else + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); +#endif + + if (dm->en_reg_mntr_mac) + pr_debug("MAC:addr=0x%x, mask=0x%x, data=0x%x\n", + reg_addr, bit_mask, data); +} + +u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return phy_query_bb_reg(dm->priv, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PHY_QueryMacReg(dm->adapter, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask); +#else + return phy_query_mac_reg(dm->adapter, reg_addr, bit_mask); +#endif +} + +void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + phy_set_bb_reg(dm->priv, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PHY_SetBBReg(adapter, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_set_bbreg(rtlpriv->hw, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_set_reg_with_mask(rtwdev, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); +#else + phy_set_bb_reg(dm->adapter, reg_addr, bit_mask, data); +#endif + + if (dm->en_reg_mntr_bb) + pr_debug("BB:addr=0x%x, mask=0x%x, data=0x%x\n", + reg_addr, bit_mask, data); +} + +u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return phy_query_bb_reg(dm->priv, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + return PHY_QueryBBReg(adapter, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_get_bbreg(rtlpriv->hw, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_get_reg_with_mask(rtwdev, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask); +#else + return phy_query_bb_reg(dm->adapter, reg_addr, bit_mask); +#endif +} + +void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask, u32 data) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_set_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PHY_SetRFReg(adapter, e_rf_path, reg_addr, bit_mask, data); + ODM_delay_us(2); + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_set_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + rtw_write_rf(rtwdev, e_rf_path, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + phy_set_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask, data); + ODM_delay_us(2); +#endif + + if (dm->en_reg_mntr_rf) + pr_debug("RF:path=0x%x, addr=0x%x, mask=0x%x, data=0x%x\n", + e_rf_path, reg_addr, bit_mask, data); +} + +u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return phy_query_rf_reg(dm->priv, e_rf_path, reg_addr, bit_mask, 1); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + return PHY_QueryRFReg(adapter, e_rf_path, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + return rtl_get_rfreg(rtlpriv->hw, e_rf_path, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + return rtw_read_rf(rtwdev, e_rf_path, reg_addr, bit_mask); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask); +#else + return phy_query_rf_reg(dm->adapter, e_rf_path, reg_addr, bit_mask); +#endif +} + +enum hal_status +phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type, + u32 offset, u32 data, u32 mask, enum rf_path e_rf_path, + u32 delay_time) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + return HAL_MAC_Config_PHY_WriteNByte(dm, + config_type, + offset, + data, + mask, + e_rf_path, + delay_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return -ENOTSUPP; +#else + return rtw_phydm_cfg_phy_para(dm, + config_type, + offset, + data, + mask, + e_rf_path, + delay_time); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#endif +} + +/*@ + * ODM Memory relative API. + */ +void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + *ptr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + *ptr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + *ptr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + *ptr = rtw_zvmalloc(length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformAllocateMemory(adapter, ptr, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + *ptr = rtw_zvmalloc(length); +#endif +} + +/* @length could be ignored, used to detect memory leakage. */ +void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + kfree(ptr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + kfree(ptr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + kfree(ptr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_vmfree(ptr, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + /* struct void* adapter = dm->adapter; */ + PlatformFreeMemory(ptr, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_vmfree(ptr, length); +#endif +} + +void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + memcpy(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + memcpy(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + memcpy(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _rtw_memcpy(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformMoveMemory(dest, src, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_memcpy(dest, src, length); +#endif +} + +void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _rtw_memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFillMemory(pbuf, length, value); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_memset(pbuf, value, length); +#endif +} + +s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, u32 length) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return memcmp(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return memcmp(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return memcmp(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return _rtw_memcmp(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformCompareMemory(buf1, buf2, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return rtw_memcmp(buf1, buf2, length); +#endif +} + +/*@ + * ODM MISC relative API. + */ +void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_odm_acquirespinlock(rtlpriv, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + spin_lock(&rtwdev->hal.dm_lock); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + rtw_odm_acquirespinlock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformAcquireSpinLock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + rtw_odm_acquirespinlock(adapter, type); +#endif +} + +void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; + + rtl_odm_releasespinlock(rtlpriv, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + + spin_unlock(&rtwdev->hal.dm_lock); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + rtw_odm_releasespinlock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformReleaseSpinLock(adapter, type); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + rtw_odm_releasespinlock(adapter, type); +#endif +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +/*@ + * Work item relative API. FOr MP driver only~! + * */ +void odm_initialize_work_item( + struct dm_struct *dm, + PRT_WORK_ITEM work_item, + RT_WORKITEM_CALL_BACK callback, + void *context, + const char *id) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformInitializeWorkItem(adapter, work_item, callback, context, id); +#endif +} + +void odm_start_work_item( + PRT_WORK_ITEM p_rt_work_item) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStartWorkItem(p_rt_work_item); +#endif +} + +void odm_stop_work_item( + PRT_WORK_ITEM p_rt_work_item) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStopWorkItem(p_rt_work_item); +#endif +} + +void odm_free_work_item( + PRT_WORK_ITEM p_rt_work_item) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFreeWorkItem(p_rt_work_item); +#endif +} + +void odm_schedule_work_item( + PRT_WORK_ITEM p_rt_work_item) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformScheduleWorkItem(p_rt_work_item); +#endif +} + +boolean +odm_is_work_item_scheduled( + PRT_WORK_ITEM p_rt_work_item) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformIsWorkItemScheduled(p_rt_work_item); +#endif +} +#endif + +/*@ + * ODM Timer relative API. + */ + +void ODM_delay_ms(u32 ms) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + mdelay(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + mdelay(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_mdelay_os(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_mdelay_os(ms); +#endif +} + +void ODM_delay_us(u32 us) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + delay_us(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + udelay(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + udelay(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_udelay_os(us); +#endif +} + +void ODM_sleep_ms(u32 ms) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + msleep(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + msleep(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_msleep_os(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + delay_ms(ms); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_msleep_os(ms); +#endif +} + +void ODM_sleep_us(u32 us) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + delay_us(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + usleep_range(us, us + 1); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + usleep_range(us, us + 1); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_usleep_os(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(us); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_usleep_os(us); +#endif +} + +void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + u32 ms_delay) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + mod_timer(timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(ms_delay)); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + mod_timer(timer, jiffies + msecs_to_jiffies(ms_delay)); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + mod_timer(&timer->timer, jiffies + msecs_to_jiffies(ms_delay)); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _set_timer(timer, ms_delay); /* @ms */ +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformSetTimer(adapter, timer, ms_delay); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_set_timer(timer, ms_delay); /* @ms */ +#endif +} + +void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + void *call_back_func, void *context, + const char *sz_id) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + init_timer(timer); + timer->function = call_back_func; + timer->data = (unsigned long)dm; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + timer_setup(timer, call_back_func, 0); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct _ADAPTER *adapter = dm->adapter; + + _init_timer(timer, adapter->pnetdev, call_back_func, dm); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + + PlatformInitializeTimer(adapter, timer, (RT_TIMER_CALL_BACK)call_back_func, context, sz_id); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + struct _ADAPTER *adapter = dm->adapter; + + rtw_init_timer(timer, adapter->pnetdev, (TIMER_FUN)call_back_func, dm, NULL); +#endif +} + +void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + del_timer(timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + del_timer(timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + del_timer(&timer->timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _cancel_timer_ex(timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PlatformCancelTimer(adapter, timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_cancel_timer(timer); +#endif +} + +void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + void *adapter = dm->adapter; + + /* @<20120301, Kordan> If the initilization fails, + * InitializeAdapterXxx will return regardless of InitHalDm. + * Hence, uninitialized timers cause BSOD when the driver + * releases resources since the init fail. + */ + if (timer == 0) { + PHYDM_DBG(dm, ODM_COMP_INIT, + "[%s] Timer is NULL! Please check!\n", __func__); + return; + } + + PlatformReleaseTimer(adapter, timer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_del_timer(timer); +#endif +} + +u8 phydm_trans_h2c_id(struct dm_struct *dm, u8 phydm_h2c_id) +{ + u8 platform_h2c_id = phydm_h2c_id; + + switch (phydm_h2c_id) { + /* @1 [0] */ + case ODM_H2C_RSSI_REPORT: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (RTL8188E_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + platform_h2c_id = H2C_88E_RSSI_REPORT; + else + #endif + platform_h2c_id = H2C_RSSI_REPORT; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + platform_h2c_id = H2C_RSSI_SETTING; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/ + if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES)) + platform_h2c_id = H2C_88XX_RSSI_REPORT; + else +#endif +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_RSSI_REPORT; + else +#endif + { + } +#endif + + break; + + /* @1 [3] */ + case ODM_H2C_WIFI_CALIBRATION: +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id = H2C_WIFI_CALIBRATION; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (RTL8723B_SUPPORT == 1) + platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION; +#endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#endif + break; + + /* @1 [4] */ + case ODM_H2C_IQ_CALIBRATION: +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id = H2C_IQ_CALIBRATION; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + platform_h2c_id = H2C_8812_IQ_CALIBRATION; +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#endif + + break; + /* @1 [5] */ + case ODM_H2C_RA_PARA_ADJUST: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id = H2C_RA_PARA_ADJUST; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; +#elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + platform_h2c_id = H2C_RA_PARA_ADJUST; +#elif (RTL8192E_SUPPORT == 1) + platform_h2c_id = H2C_8192E_RA_PARA_ADJUST; +#elif (RTL8723B_SUPPORT == 1) + platform_h2c_id = H2C_8723B_RA_PARA_ADJUST; +#endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/ + if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES)) + platform_h2c_id = H2C_88XX_RA_PARA_ADJUST; + else +#endif +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; + else +#endif + { + } +#endif + + break; + + /* @1 [6] */ + case PHYDM_H2C_DYNAMIC_TX_PATH: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) + platform_h2c_id = H2C_8814A_DYNAMIC_TX_PATH; + #endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) + platform_h2c_id = H2C_DYNAMIC_TX_PATH; +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8814A) + platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; +#endif + +#endif + + break; + + /* @[7]*/ + case PHYDM_H2C_FW_TRACE_EN: + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + platform_h2c_id = H2C_FW_TRACE_EN; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + + platform_h2c_id = 0x49; + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) +#if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1) || (RTL8192F_SUPPORT == 1)) /*@jj add 20170822*/ + if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8192F | PHYDM_IC_3081_SERIES)) + platform_h2c_id = H2C_88XX_FW_TRACE_EN; + else +#endif +#if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) + platform_h2c_id = H2C_8812_FW_TRACE_EN; + else +#endif + { + } + +#endif + + break; + + case PHYDM_H2C_TXBF: +#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8812)) + platform_h2c_id = 0x41; /*@H2C_TxBF*/ +#endif + break; + + case PHYDM_H2C_MU: +#if (RTL8822B_SUPPORT == 1) + platform_h2c_id = 0x4a; /*@H2C_MU*/ +#endif + break; + + default: + platform_h2c_id = phydm_h2c_id; + break; + } + + return platform_h2c_id; +} + +/*@ODM FW relative API.*/ + +void odm_fill_h2c_cmd(struct dm_struct *dm, u8 phydm_h2c_id, u32 cmd_len, + u8 *cmd_buf) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + struct rtw_dev *rtwdev = dm->adapter; + u8 cmd_id, cmd_class; + u8 h2c_pkt[8]; +#else + void *adapter = dm->adapter; +#endif + u8 h2c_id = phydm_trans_h2c_id(dm, phydm_h2c_id); + + PHYDM_DBG(dm, DBG_RA, "[H2C] h2c_id=((0x%x))\n", h2c_id); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (dm->support_ic_type == ODM_RTL8188E) { + if (!dm->ra_support88e) + FillH2CCmd88E(adapter, h2c_id, cmd_len, cmd_buf); + } else if (dm->support_ic_type == ODM_RTL8814A) + FillH2CCmd8814A(adapter, h2c_id, cmd_len, cmd_buf); + else if (dm->support_ic_type == ODM_RTL8822B) + FillH2CCmd8822B(adapter, h2c_id, cmd_len, cmd_buf); + else + FillH2CCmd(adapter, h2c_id, cmd_len, cmd_buf); + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + + #ifdef DM_ODM_CE_MAC80211 + rtlpriv->cfg->ops->fill_h2c_cmd(rtlpriv->hw, h2c_id, cmd_len, cmd_buf); + #elif defined(DM_ODM_CE_MAC80211_V2) + cmd_id = phydm_h2c_id & 0x1f; + cmd_class = (phydm_h2c_id >> RTW_H2C_CLASS_OFFSET) & 0x7; + memcpy(h2c_pkt + 1, cmd_buf, 7); + h2c_pkt[0] = phydm_h2c_id; + rtw_fw_send_h2c_packet(rtwdev, h2c_pkt, cmd_id, cmd_class); + /* TODO: implement fill h2c command for rtwlan */ + #else + rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf); + #endif + +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + + #if (RTL8812A_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8812) { + fill_h2c_cmd8812(dm->priv, h2c_id, cmd_len, cmd_buf); + } else + #endif + { + GET_HAL_INTERFACE(dm->priv)->fill_h2c_cmd_handler(dm->priv, h2c_id, cmd_len, cmd_buf); + } + +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + rtw_hal_fill_h2c_cmd(adapter, h2c_id, cmd_len, cmd_buf); + +#endif +} + +u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, + u8 *tmp_buf) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; +#endif + u8 extend_c2h_sub_id = 0; + u8 find_c2h_cmd = true; + + if (c2h_cmd_len > 12 || c2h_cmd_len == 0) { + pr_debug("[Warning] Error C2H ID=%d, len=%d\n", + c2h_cmd_id, c2h_cmd_len); + + find_c2h_cmd = false; + return find_c2h_cmd; + } + + switch (c2h_cmd_id) { + case PHYDM_C2H_DBG: + phydm_fw_trace_handler(dm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_RA_RPT: + phydm_c2h_ra_report_handler(dm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_RA_PARA_RPT: + odm_c2h_ra_para_report_handler(dm, tmp_buf, c2h_cmd_len); + break; +#ifdef CONFIG_PATH_DIVERSITY + case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: + if (dm->support_ic_type & (ODM_RTL8814A)) + phydm_c2h_dtp_handler(dm, tmp_buf, c2h_cmd_len); + break; +#endif + + case PHYDM_C2H_IQK_FINISH: +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821)) { + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n")); + odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(dm, RT_IQK_SPINLOCK); + dm->rf_calibrate_info.iqk_progressing_time = 0; + dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time); + } + +#endif + break; + + case PHYDM_C2H_CLM_MONITOR: + phydm_clm_c2h_report_handler(dm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_DBG_CODE: + phydm_fw_trace_handler_code(dm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_EXTEND: + extend_c2h_sub_id = tmp_buf[0]; + if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT) + phydm_fw_trace_handler_8051(dm, tmp_buf, c2h_cmd_len); + + break; + + default: + find_c2h_cmd = false; + break; + } + + return find_c2h_cmd; +} + +u64 odm_get_current_time(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return (u64)rtw_get_current_time(); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return jiffies; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return jiffies; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_get_current_time(); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformGetCurrentTime(); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return rtw_get_current_time(); +#endif +} + +u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + return rtw_get_passing_time_ms((u32)start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + return jiffies_to_msecs(jiffies - start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return jiffies_to_msecs(jiffies - start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_get_passing_time_ms((systime)start_time); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return ((PlatformGetCurrentTime() - start_time) >> 10); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + return rtw_get_passing_time_ms(start_time); +#endif +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \ + (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2)) + +void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 RegName, + u8 *val) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _ADAPTER *adapter = dm->adapter; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + ((PADAPTER)adapter)->HalFunc.SetHwRegHandler(adapter, RegName, val); +#else + adapter->hal_func.set_hw_reg_handler(adapter, RegName, val); +#endif + +#endif +} + +void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm, + enum _HAL_DEF_VARIABLE e_variable, + void *value) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + struct _ADAPTER *adapter = dm->adapter; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + ((PADAPTER)adapter)->HalFunc.GetHalDefVarHandler(adapter, e_variable, value); +#else + adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, value); +#endif + +#endif +} + +#endif + +void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm, + enum rf_path path, u8 ch, + u8 section) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + phy_set_tx_power_index_by_rs(adapter, ch, path, section); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + phy_set_tx_power_index_by_rate_section(dm->adapter, path, ch, section); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + PHY_SetTxPowerIndexByRateSection(adapter, path, ch, section); +#endif +} + +u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 rate, + u8 bw, u8 ch) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + + return PHY_GetTxPowerIndex(dm->adapter, path, rate, (CHANNEL_WIDTH)bw, ch); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + return phy_get_tx_power_index(adapter, path, rate, bw, ch); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + void *adapter = dm->adapter; + + return phy_get_tx_power_index(adapter, path, rate, bw, ch); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return phy_get_tx_power_index(dm->adapter, path, rate, bw, ch); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + return PHY_GetTxPowerIndex(dm->adapter, path, rate, bw, ch); +#endif +} + +u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data, + boolean b_pseu_do_test) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + + return (u8)EFUSE_OneByteRead(adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + return rtl_efuse_onebyte_read(adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + return -1; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return efuse_onebyte_read(dm->adapter, addr, data, b_pseu_do_test); +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + return Efuse_OneByteRead(dm, addr, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + return (u8)efuse_OneByteRead(adapter, addr, data, b_pseu_do_test); +#endif +} + +void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset, + u32 *data) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + void *adapter = dm->adapter; + + EFUSE_ShadowRead(adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + rtl_efuse_logical_map_read(adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + efuse_logical_map_read(dm->adapter, type, offset, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + void *adapter = dm->adapter; + + EFUSE_ShadowRead(adapter, type, offset, data); +#endif +} + +enum hal_status +odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment) +{ + enum hal_status iqk_result = HAL_STATUS_FAILURE; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = dm->adapter; + + if (HAL_MAC_FWIQK_Trigger(&GET_HAL_MAC_INFO(adapter), clear, segment) == 0) + iqk_result = HAL_STATUS_SUCCESS; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + void *adapter = dm->adapter; + + iqk_result = rtl_phydm_fw_iqk(adapter, clear, segment); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#else + iqk_result = rtw_phydm_fw_iqk(dm, clear, segment); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT) + iqk_result = rtw_phydm_fw_iqk(dm, clear, segment); +#endif + return iqk_result; +} + +enum hal_status +odm_dpk_by_fw(struct dm_struct *dm) +{ + enum hal_status dpk_result = HAL_STATUS_FAILURE; +#if 0 + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = dm->adapter; + + if (hal_mac_fwdpk_trigger(&GET_HAL_MAC_INFO(adapter)) == 0) + dpk_result = HAL_STATUS_SUCCESS; +#else + dpk_result = rtw_phydm_fw_dpk(dm); +#endif + +#endif + return dpk_result; +} + +void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 mac_id, + struct cmn_sta_info *pcmn_sta_info) +{ + dm->phydm_sta_info[mac_id] = pcmn_sta_info; + + if (is_sta_active(pcmn_sta_info)) + dm->phydm_macid_table[pcmn_sta_info->mac_id] = mac_id; +} + +void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx, + struct cmn_sta_info *pcmn_sta_info) +{ + if (is_sta_active(pcmn_sta_info)) + dm->phydm_macid_table[pcmn_sta_info->mac_id] = entry_idx; +} + +void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct rtl8192cd_priv *priv = dm->priv; + + #if IS_EXIST_PCI || IS_EXIST_EMBEDDED + if (dm->support_interface == ODM_ITRF_PCIE) + GET_HAL_INTERFACE(priv)->AddInterruptMaskHandler(priv, + interrupt_type) + ; + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif +} + +void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + struct rtl8192cd_priv *priv = dm->priv; + + #if IS_EXIST_PCI || IS_EXIST_EMBEDDED + if (dm->support_interface == ODM_ITRF_PCIE) + GET_HAL_INTERFACE(priv)->EnableRxRelatedInterruptHandler(priv); + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#endif +} + +void phydm_iqk_wait(struct dm_struct *dm, u32 timeout) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#else + void *adapter = dm->adapter; + + rtl8812_iqk_wait(adapter, timeout); +#endif +#endif +} + +u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + return HwRateToMRate(rate); +#endif + return 0; +} + +void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + ROM_odm_SetCrystalCap(dm, crystal_cap); +#endif +} + +void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *), + void *context) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + PHYDM_DBG(dm, DBG_CMN, "Not support for CE MAC80211 driver!\n"); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + void *adapter = dm->adapter; + + rtw_run_in_thread_cmd(adapter, func, context); +#endif +} + +u8 phydm_get_tx_rate(struct dm_struct *dm) +{ + struct _hal_rf_ *rf = &dm->rf_table; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = dm->adapter; +#endif + u8 tx_rate = 0xff; + u8 mpt_rate_index = 0; + + if (*dm->mp_mode == 1) { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (MP_DRIVER == 1) + PMPT_CONTEXT p_mpt_ctx = &adapter->MptCtx; + + tx_rate = MptToMgntRate(p_mpt_ctx->MptRateIndex); +#endif +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) +#ifdef CONFIG_MP_INCLUDED + if (rf->mp_rate_index) + mpt_rate_index = *rf->mp_rate_index; + + tx_rate = mpt_to_mgnt_rate(mpt_rate_index); +#endif +#endif +#endif + } else { + u16 rate = *dm->forced_data_rate; + + if (!rate) { /*auto rate*/ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + struct _ADAPTER *adapter = dm->adapter; + + tx_rate = ((PADAPTER)adapter)->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211) + tx_rate = dm->tx_rate; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + if (dm->number_linked_client != 0) + tx_rate = hw_rate_to_m_rate(dm->tx_rate); + else + tx_rate = rf->p_rate_index; +#endif + } else { /*force rate*/ + tx_rate = (u8)rate; + } + } + + return tx_rate; +} + +u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path, + u8 rate, u8 bandwidth, u8 channel) +{ + u8 tx_power_dbm = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = dm->adapter; + tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(adapter, rf_path, rate, bandwidth, channel); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + tx_power_dbm = phy_get_tx_power_final_absolute_value(dm->adapter, rf_path, rate, bandwidth, channel); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValue(dm, rf_path, rate, bandwidth, channel); +#endif + return tx_power_dbm; +} + +s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path, + u8 rate, u8 bandwidth, u8 channel) +{ + s16 tx_power_dbm = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + struct _ADAPTER *adapter = dm->adapter; + tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuemdBm(adapter, rf_path, rate, bandwidth, channel); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + tx_power_dbm = rtw_odm_get_tx_power_mbm(dm, rf_path, rate, bandwidth, channel); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + tx_power_dbm = PHY_GetTxPowerFinalAbsoluteValuembm(dm, rf_path, rate, bandwidth, channel); +#endif + return tx_power_dbm; +} + +u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + return rtw_phydm_rfe_ctrl_gpio(dm->adapter, gpio_num); +#endif + return 0; +} + +u64 phydm_division64(u64 x, u64 y) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + do_div(x, y); + return x; +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + return x / y; +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_division64(x, y); +#endif +} diff --git a/hal/phydm/phydm_interface.h b/hal/phydm/phydm_interface.h new file mode 100644 index 0000000..2c75a23 --- /dev/null +++ b/hal/phydm/phydm_interface.h @@ -0,0 +1,328 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + +#define INTERFACE_VERSION "1.2" + +#define pdm_set_reg odm_set_bb_reg + +/*@=========== Constant/Structure/Enum/... Define*/ + +enum phydm_h2c_cmd { + PHYDM_H2C_RA_MASK = 0x40, + PHYDM_H2C_TXBF = 0x41, + ODM_H2C_RSSI_REPORT = 0x42, + ODM_H2C_IQ_CALIBRATION = 0x45, + PHYDM_RA_MASK_ABOVE_3SS = 0x46, + ODM_H2C_RA_PARA_ADJUST = 0x47, + PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, + PHYDM_H2C_FW_TRACE_EN = 0x49, + ODM_H2C_WIFI_CALIBRATION = 0x6d, + PHYDM_H2C_MU = 0x4a, + PHYDM_H2C_FW_GENERAL_INIT = 0x4c, + PHYDM_H2C_FW_CLM_MNTR = 0x4d, + PHYDM_H2C_MCC = 0x4f, + PHYDM_H2C_RESP_TX_PATH_CTRL = 0x50, + PHYDM_H2C_RESP_TX_ANT_CTRL = 0x51, + PHYDM_H2C_FW_DM_CTRL = 0x55, + ODM_MAX_H2CCMD +}; + +enum phydm_c2h_evt { + PHYDM_C2H_DBG = 0, + PHYDM_C2H_LB = 1, + PHYDM_C2H_XBF = 2, + PHYDM_C2H_TX_REPORT = 3, + PHYDM_C2H_INFO = 9, + PHYDM_C2H_BT_MP = 11, + PHYDM_C2H_RA_RPT = 12, + PHYDM_C2H_RA_PARA_RPT = 14, + PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, + PHYDM_C2H_IQK_FINISH = 17, /*@0x11*/ + PHYDM_C2H_CLM_MONITOR = 0x2a, + PHYDM_C2H_DBG_CODE = 0xFE, + PHYDM_C2H_EXTEND = 0xFF, +}; + +enum phydm_extend_c2h_evt { + PHYDM_EXTEND_C2H_DBG_PRINT = 0 + +}; + +enum phydm_halmac_param { + PHYDM_HALMAC_CMD_MAC_W8 = 0, + PHYDM_HALMAC_CMD_MAC_W16 = 1, + PHYDM_HALMAC_CMD_MAC_W32 = 2, + PHYDM_HALMAC_CMD_BB_W8, + PHYDM_HALMAC_CMD_BB_W16, + PHYDM_HALMAC_CMD_BB_W32, + PHYDM_HALMAC_CMD_RF_W, + PHYDM_HALMAC_CMD_DELAY_US, + PHYDM_HALMAC_CMD_DELAY_MS, + PHYDM_HALMAC_CMD_END = 0XFF, +}; + +/*@=========== Macro Define*/ + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +#if defined(DM_ODM_CE_MAC80211) +#define ODM_BIT(name, dm) \ + ((dm->support_ic_type & ODM_IC_11N_SERIES) ? \ + ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC) + +#define ODM_REG(name, dm) \ + ((dm->support_ic_type & ODM_IC_11N_SERIES) ? \ + ODM_REG_##name##_11N : ODM_REG_##name##_11AC) +#else +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + +#ifdef __ECOS +#define _rtk_cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name)) +#else + +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name)) +#endif +/*@ + * only sample code + *#define _cat(_name, _ic_type, _func) \ + * ( \ + * ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\ + * _func##_ic(_name, _8195) \ + * ) + */ + +/* @_name: name of register or bit. + * Example: "ODM_REG(R_A_AGC_CORE1, dm)" + * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", + * depends on support_ic_type. + */ +#ifdef __ECOS + #define ODM_REG(_name, _pdm_odm) \ + _rtk_cat(_name, _pdm_odm->support_ic_type, _reg) + #define ODM_BIT(_name, _pdm_odm) \ + _rtk_cat(_name, _pdm_odm->support_ic_type, _bit) +#else + #define ODM_REG(_name, _pdm_odm) \ + _cat(_name, _pdm_odm->support_ic_type, _reg) + #define ODM_BIT(_name, _pdm_odm) \ + _cat(_name, _pdm_odm->support_ic_type, _bit) +#endif + +#endif +/*@ + * =========== Extern Variable ??? It should be forbidden. + */ + +/*@ + * =========== EXtern Function Prototype + */ + +u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr); + +u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr); + +u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr); + +void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data); + +void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data); + +void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data); + +void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, + u32 data); + +u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask); + +void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data); + +u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask); + +void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask, u32 data); + +u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr, + u32 bit_mask); + +/*@ + * Memory Relative Function. + */ +void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length); +void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length); + +void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length); + +s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2, + u32 length); + +void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length); + +/*@ + * ODM MISC-spin lock relative API. + */ +void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type); + +void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +/*@ + * ODM MISC-workitem relative API. + */ +void odm_initialize_work_item( + struct dm_struct *dm, + PRT_WORK_ITEM p_rt_work_item, + RT_WORKITEM_CALL_BACK rt_work_item_callback, + void *context, + const char *sz_id); + +void odm_start_work_item( + PRT_WORK_ITEM p_rt_work_item); + +void odm_stop_work_item( + PRT_WORK_ITEM p_rt_work_item); + +void odm_free_work_item( + PRT_WORK_ITEM p_rt_work_item); + +void odm_schedule_work_item( + PRT_WORK_ITEM p_rt_work_item); + +boolean +odm_is_work_item_scheduled( + PRT_WORK_ITEM p_rt_work_item); +#endif + +/*@ + * ODM Timer relative API. + */ +void ODM_delay_ms(u32 ms); + +void ODM_delay_us(u32 us); + +void ODM_sleep_ms(u32 ms); + +void ODM_sleep_us(u32 us); + +void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + u32 ms_delay); + +void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer, + void *call_back_func, void *context, + const char *sz_id); + +void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer); + +void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer); + +/*ODM FW relative API.*/ + +enum hal_status +phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type, + u32 offset, u32 data, u32 mask, enum rf_path e_rf_path, + u32 delay_time); + +void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len, + u8 *cmd_buffer); + +u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, + u8 *tmp_buf); + +u64 odm_get_current_time(struct dm_struct *dm); +u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \ + (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2)) + +void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name, + u8 *val); + +void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm, + enum _HAL_DEF_VARIABLE e_variable, + void *value); + +#endif + +void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm, + enum rf_path path, u8 channel, + u8 rate_section); + +u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate, + u8 band_width, u8 channel); + +u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data, + boolean b_pseu_do_test); + +void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset, + u32 *data); + +enum hal_status +odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment); + +enum hal_status +odm_dpk_by_fw(struct dm_struct *dm); + +void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index, + struct cmn_sta_info *pcmn_sta_info); + +void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx, + struct cmn_sta_info *pcmn_sta_info); + +void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type); + +void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm); + +void phydm_iqk_wait(struct dm_struct *dm, u32 timeout); +u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate); + +void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap); +void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *), + void *context); +u8 phydm_get_tx_rate(struct dm_struct *dm); +u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path, + u8 rate, u8 bandwidth, u8 channel); + +s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path, + u8 rate, u8 bandwidth, u8 channel); + +u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num); + +u64 phydm_division64(u64 x, u64 y); + +#endif /* @__ODM_INTERFACE_H__ */ diff --git a/hal/phydm/phydm_lna_sat.c b/hal/phydm/phydm_lna_sat.c new file mode 100644 index 0000000..f48ae5c --- /dev/null +++ b/hal/phydm/phydm_lna_sat.c @@ -0,0 +1,1688 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + * *************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT + +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 +void phydm_lna_sat_chk_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc = 0; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd = 0; + #endif + lna_info->cur_sat_status = 0; + lna_info->pre_sat_status = 0; + lna_info->cur_timer_check_cnt = 0; + lna_info->pre_timer_check_cnt = 0; + + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_lna_sat_chk_bb_init(dm); + #endif +} + +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) +void phydm_lna_sat_chk_bb_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + boolean disable_bb_switch_tab = false; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + /*@set table switch mux r_6table_sel_anten*/ + odm_set_bb_reg(dm, 0x18ac, BIT(8), 0); + + /*@tab decision when idle*/ + odm_set_bb_reg(dm, 0x18ac, BIT(16), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x41ac, BIT(16), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x52ac, BIT(16), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x53ac, BIT(16), disable_bb_switch_tab); + /*@tab decision when ofdmcca*/ + odm_set_bb_reg(dm, 0x18ac, BIT(17), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x41ac, BIT(17), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x52ac, BIT(17), disable_bb_switch_tab); + odm_set_bb_reg(dm, 0x53ac, BIT(17), disable_bb_switch_tab); +} + +void phydm_set_ofdm_agc_tab_path( + void *dm_void, + u8 tab_sel, + enum rf_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "set AGC Tab%d\n", tab_sel); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "r_6table_sel_anten = 0x%x\n", + odm_get_bb_reg(dm, 0x18ac, BIT(8))); + } + + if (dm->support_ic_type & ODM_RTL8198F) { + /*@table sel:0/2, mapping 2 to 1 */ + if (tab_sel == OFDM_AGC_TAB_0) { + odm_set_bb_reg(dm, 0x18ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x41ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x52ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x53ac, BIT(4), 0); + } else if (tab_sel == OFDM_AGC_TAB_2) { + odm_set_bb_reg(dm, 0x18ac, BIT(4), 1); + odm_set_bb_reg(dm, 0x41ac, BIT(4), 1); + odm_set_bb_reg(dm, 0x52ac, BIT(4), 1); + odm_set_bb_reg(dm, 0x53ac, BIT(4), 1); + } else { + odm_set_bb_reg(dm, 0x18ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x41ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x52ac, BIT(4), 0); + odm_set_bb_reg(dm, 0x53ac, BIT(4), 0); + } + } else if (dm->support_ic_type & ODM_RTL8814B) { + if (tab_sel == OFDM_AGC_TAB_0) { + odm_set_bb_reg(dm, 0x18ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x41ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x52ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x53ac, 0xf0, 0); + } else if (tab_sel == OFDM_AGC_TAB_2) { + odm_set_bb_reg(dm, 0x18ac, 0xf0, 2); + odm_set_bb_reg(dm, 0x41ac, 0xf0, 2); + odm_set_bb_reg(dm, 0x52ac, 0xf0, 2); + odm_set_bb_reg(dm, 0x53ac, 0xf0, 2); + } else { + odm_set_bb_reg(dm, 0x18ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x41ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x52ac, 0xf0, 0); + odm_set_bb_reg(dm, 0x53ac, 0xf0, 0); + } + } +} + +u8 phydm_get_ofdm_agc_tab_path( + void *dm_void, + enum rf_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 tab_sel = 0; + + if (dm->support_ic_type & ODM_RTL8198F) { + tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, BIT(4)); + if (tab_sel == 0) + tab_sel = OFDM_AGC_TAB_0; + else if (tab_sel == 1) + tab_sel = OFDM_AGC_TAB_2; + } else if (dm->support_ic_type & ODM_RTL8814B) { + tab_sel = (u8)odm_get_bb_reg(dm, R_0x18ac, 0xf0); + if (tab_sel == 0) + tab_sel = OFDM_AGC_TAB_0; + else if (tab_sel == 2) + tab_sel = OFDM_AGC_TAB_2; + } + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "get path %d AGC Tab %d\n", + path, tab_sel); + return tab_sel; +} +#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/ + +void phydm_set_ofdm_agc_tab( + void *dm_void, + u8 tab_sel) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /*@table sel:0/2, 1 is used for CCK */ + if (tab_sel == OFDM_AGC_TAB_0) + odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0); + else if (tab_sel == OFDM_AGC_TAB_2) + odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_2); + else + odm_set_bb_reg(dm, R_0xc70, 0x1e00, OFDM_AGC_TAB_0); +} + +u8 phydm_get_ofdm_agc_tab( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + return (u8)odm_get_bb_reg(dm, R_0xc70, 0x1e00); +} + +void phydm_lna_sat_chk( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_dig_struct *dig_t = &dm->dm_dig_table; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + u8 igi_rssi_min; + u8 rssi_min = dm->rssi_min; + u32 sat_status_a, sat_status_b; + #ifdef PHYDM_IC_ABOVE_3SS + u32 sat_status_c; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + u32 sat_status_d; + #endif + u8 igi_restore = dig_t->cur_ig_value; + u8 i, chk_cnt = lna_info->chk_cnt; + u32 lna_sat_cnt_thd = 0; + u8 agc_tab; + u32 max_check_time = 0; + /*@use rssi_max if rssi_min is not stable;*/ + /*@rssi_min = dm->rssi_max;*/ + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__); + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Func disable\n"); + return; + } + + if (lna_info->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "disable_lna_sat_chk\n"); + return; + } + + /*@move igi to target pin of rssi_min */ + if (rssi_min == 0 || rssi_min == 0xff) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "rssi_min=%d, set AGC Tab0\n", rssi_min); + /*@adapt agc table 0*/ + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(dm); + return; + } else if (rssi_min % 2 != 0) { + igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI - 1; + } else { + igi_rssi_min = rssi_min + DIFF_RSSI_TO_IGI; + } + + if ((lna_info->chk_period > 0) && (lna_info->chk_period <= ONE_SEC_MS)) + max_check_time = chk_cnt * (ONE_SEC_MS / (lna_info->chk_period)) * 5; + else + max_check_time = chk_cnt * 5; + + lna_sat_cnt_thd = (max_check_time * lna_info->chk_duty_cycle) / 100; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "check_time=%d, rssi_min=%d, igi_rssi_min=0x%x\nchk_cnt=%d, chk_period=%d, max_check_time=%d, lna_sat_cnt_thd=%d\n", + lna_info->check_time, + rssi_min, + igi_rssi_min, + chk_cnt, + lna_info->chk_period, + max_check_time, + lna_sat_cnt_thd); + + odm_write_dig(dm, igi_rssi_min); + + /*@adapt agc table 0 check saturation status*/ + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, OFDM_AGC_TAB_0, RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + /*@open rf power detection ckt & set detection range */ +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + /*@set rf detection range (threshold)*/ + config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x85, + 0x3f, 0x3f); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x85, + 0x3f, 0x3f); + /*@open rf power detection ckt*/ + config_phydm_write_rf_reg_8198f(dm, RF_PATH_A, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_B, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_C, 0x86, 0x10, 1); + config_phydm_write_rf_reg_8198f(dm, RF_PATH_D, 0x86, 0x10, 1); + } +#elif (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + /*@set rf detection range (threshold)*/ + config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x3, 0x3); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x3, 0x3); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x3, 0x3); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x3, 0x3); + /*@open rf power detection ckt*/ + config_phydm_write_rf_reg_8814b(dm, RF_PATH_A, 0x8B, 0x4, 1); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_B, 0x8B, 0x4, 1); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_C, 0x8B, 0x4, 1); + config_phydm_write_rf_reg_8814b(dm, RF_PATH_D, 0x8B, 0x4, 1); + } +#else + odm_set_rf_reg(dm, RF_PATH_A, RF_0x86, 0x1f, 0x10); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x86, 0x1f, 0x10); + #ifdef PHYDM_IC_ABOVE_3SS + odm_set_rf_reg(dm, RF_PATH_C, RF_0x86, 0x1f, 0x10); + #endif + #ifdef PHYDM_IC_ABOVE_4SS + odm_set_rf_reg(dm, RF_PATH_D, RF_0x86, 0x1f, 0x10); + #endif +#endif + + /*@check saturation status*/ + for (i = 0; i < chk_cnt; i++) { +#if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) { + sat_status_a = config_phydm_read_rf_reg_8198f(dm, RF_PATH_A, + RF_0xae, + 0xe0000); + sat_status_b = config_phydm_read_rf_reg_8198f(dm, RF_PATH_B, + RF_0xae, + 0xe0000); + sat_status_c = config_phydm_read_rf_reg_8198f(dm, RF_PATH_C, + RF_0xae, + 0xe0000); + sat_status_d = config_phydm_read_rf_reg_8198f(dm, RF_PATH_D, + RF_0xae, + 0xe0000); + } +#elif (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + /*@read peak detector info from 8814B rf reg*/ + sat_status_a = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A, + RF_0xae, + 0xc0000); + sat_status_b = config_phydm_read_rf_reg_8814b(dm, RF_PATH_B, + RF_0xae, + 0xc0000); + sat_status_c = config_phydm_read_rf_reg_8814b(dm, RF_PATH_C, + RF_0xae, + 0xc0000); + sat_status_d = config_phydm_read_rf_reg_8814b(dm, RF_PATH_D, + RF_0xae, + 0xc0000); + } +#else + sat_status_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0xae, 0xc0000); + sat_status_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0xae, 0xc0000); + #ifdef PHYDM_IC_ABOVE_3SS + sat_status_c = odm_get_rf_reg(dm, RF_PATH_C, RF_0xae, 0xc0000); + #endif + #ifdef PHYDM_IC_ABOVE_4SS + sat_status_d = odm_get_rf_reg(dm, RF_PATH_D, RF_0xae, 0xc0000); + #endif +#endif + + if (sat_status_a != 0) + lna_info->sat_cnt_acc_patha++; + if (sat_status_b != 0) + lna_info->sat_cnt_acc_pathb++; + #ifdef PHYDM_IC_ABOVE_3SS + if (sat_status_c != 0) + lna_info->sat_cnt_acc_pathc++; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + if (sat_status_d != 0) + lna_info->sat_cnt_acc_pathd++; + #endif + + if (lna_info->sat_cnt_acc_patha >= lna_sat_cnt_thd || + lna_info->sat_cnt_acc_pathb >= lna_sat_cnt_thd || + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc >= lna_sat_cnt_thd || + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd >= lna_sat_cnt_thd || + #endif + 0) { + lna_info->cur_sat_status = 1; + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, check_time=%d\n", + lna_info->cur_sat_status, + lna_info->check_time); + break; + } + lna_info->cur_sat_status = 0; + } + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_patha=%d, sat_cnt_acc_pathb=%d\n", + lna_info->cur_sat_status, + lna_info->pre_sat_status, + lna_info->sat_cnt_acc_patha, + lna_info->sat_cnt_acc_pathb); + + #ifdef PHYDM_IC_ABOVE_4SS + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "cur_sat_status=%d, pre_sat_status=%d, sat_cnt_acc_pathc=%d, sat_cnt_acc_pathd=%d\n", + lna_info->cur_sat_status, + lna_info->pre_sat_status, + lna_info->sat_cnt_acc_pathc, + lna_info->sat_cnt_acc_pathd); + #endif + /*@agc table decision*/ + if (lna_info->cur_sat_status) { + if (!lna_info->dis_agc_table_swh) + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, + OFDM_AGC_TAB_2, + RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2); + else + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2); + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc = 0; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd = 0; + #endif + lna_info->pre_sat_status = lna_info->cur_sat_status; + + } else if (lna_info->check_time <= (max_check_time - 1)) { + if (lna_info->pre_sat_status && !lna_info->dis_agc_table_swh) + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, + OFDM_AGC_TAB_2, + RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_2); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time not reached\n"); + if (lna_info->dis_agc_table_swh) + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "disable set to AGC Tab%d\n", OFDM_AGC_TAB_2); + lna_info->check_time++; + + } else if (lna_info->check_time >= max_check_time) { + if (!lna_info->dis_agc_table_swh) + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + phydm_set_ofdm_agc_tab_path(dm, + OFDM_AGC_TAB_0, + RF_PATH_A); + else + #endif + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ckeck time reached\n"); + if (lna_info->dis_agc_table_swh) + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "disable set to AGC Tab%d\n", OFDM_AGC_TAB_0); + lna_info->check_time = 0; + lna_info->sat_cnt_acc_patha = 0; + lna_info->sat_cnt_acc_pathb = 0; + #ifdef PHYDM_IC_ABOVE_3SS + lna_info->sat_cnt_acc_pathc = 0; + #endif + #ifdef PHYDM_IC_ABOVE_4SS + lna_info->sat_cnt_acc_pathd = 0; + #endif + lna_info->pre_sat_status = lna_info->cur_sat_status; + } + + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A); + else + #endif + agc_tab = phydm_get_ofdm_agc_tab(dm); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "use AGC tab %d\n", agc_tab); + + /*@restore previous igi*/ + odm_write_dig(dm, igi_restore); + lna_info->cur_timer_check_cnt++; + odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer, + lna_info->chk_period); +} + +void phydm_lna_sat_chk_callback( + void *dm_void + + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n%s ==>\n", __func__); + phydm_lna_sat_chk(dm); +} + +void phydm_lna_sat_chk_timers( + void *dm_void, + u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + if (state == INIT_LNA_SAT_CHK_TIMMER) { + odm_initialize_timer(dm, + &lna_info->phydm_lna_sat_chk_timer, + (void *)phydm_lna_sat_chk_callback, NULL, + "phydm_lna_sat_chk_timer"); + } else if (state == CANCEL_LNA_SAT_CHK_TIMMER) { + odm_cancel_timer(dm, &lna_info->phydm_lna_sat_chk_timer); + } else if (state == RELEASE_LNA_SAT_CHK_TIMMER) { + odm_release_timer(dm, &lna_info->phydm_lna_sat_chk_timer); + } +} + +void phydm_lna_sat_chk_watchdog_type1( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_info = &dm->dm_lna_sat_info; + + u8 rssi_min = dm->rssi_min; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "func disable\n"); + return; + } + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "pre_timer_check_cnt=%d, cur_timer_check_cnt=%d\n", + lna_info->pre_timer_check_cnt, + lna_info->cur_timer_check_cnt); + + if (lna_info->is_disable_lna_sat_chk) { + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "is_disable_lna_sat_chk=%d, return\n", + lna_info->is_disable_lna_sat_chk); + return; + } + + if (rssi_min == 0 || rssi_min == 0xff) { + /*@adapt agc table 0 */ + phydm_set_ofdm_agc_tab(dm, OFDM_AGC_TAB_0); + phydm_lna_sat_chk_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "rssi_min=%d, return\n", rssi_min); + return; + } + + if (lna_info->cur_timer_check_cnt == lna_info->pre_timer_check_cnt) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "fail, restart timer\n"); + odm_set_timer(dm, &lna_info->phydm_lna_sat_chk_timer, + lna_info->chk_period); + } else { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Timer check pass\n"); + } + lna_info->pre_timer_check_cnt = lna_info->cur_timer_check_cnt; +} + +#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE1*/ + +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 + +void phydm_bubble_sort( + void *dm_void, + u8 *array, + u16 array_length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 i, j; + u8 temp; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + for (i = 0; i < (array_length - 1); i++) { + for (j = (i + 1); j < (array_length); j++) { + if (array[i] > array[j]) { + temp = array[i]; + array[i] = array[j]; + array[j] = temp; + } + } + } +} + +void phydm_lna_sat_chk_type2_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u8 real_shift = pinfo->total_bit_shift; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + pinfo->total_cnt_snr = 1 << real_shift; + pinfo->is_sm_done = TRUE; + pinfo->is_snr_done = FALSE; + pinfo->cur_snr_mean = 0; + pinfo->cur_snr_var = 0; + pinfo->cur_lower_snr_mean = 0; + pinfo->pre_snr_mean = 0; + pinfo->pre_snr_var = 0; + pinfo->pre_lower_snr_mean = 0; + pinfo->nxt_state = ORI_TABLE_MONITOR; + pinfo->pre_state = ORI_TABLE_MONITOR; +} + +void phydm_snr_collect( + void *dm_void, + u8 rx_snr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (pinfo->is_sm_done) { + /* @adapt only path-A for calculation */ + pinfo->snr_statistic[pinfo->cnt_snr_statistic] = rx_snr; + + if (pinfo->cnt_snr_statistic == (pinfo->total_cnt_snr - 1)) { + pinfo->is_snr_done = TRUE; + pinfo->cnt_snr_statistic = 0; + } else { + pinfo->cnt_snr_statistic++; + } + } else { + return; + } +} + +void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_t = &dm->dm_lna_sat_info; + struct phydm_perpkt_info_struct *pktinfo = NULL; + u8 target_macid = dm->rssi_min_macid; + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) + return; + + pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void; + + if (!pktinfo->is_packet_match_bssid) + return; + + if (lna_t->force_traget_macid != 0) + target_macid = lna_t->force_traget_macid; + + if (target_macid != pktinfo->station_id) + return; + + phydm_snr_collect(dm, rx_snr[0]); /*path-A B C D???*/ +} + +void phydm_snr_data_processing( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u8 real_shift = pinfo->total_bit_shift; + u16 total_snr_cnt = pinfo->total_cnt_snr; + u16 total_loop_cnt = (total_snr_cnt - 1), i; + u32 temp; + u32 sum_snr_statistic = 0; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "total_loop_cnt=%d\n", total_loop_cnt); + + for (i = 0; (i <= total_loop_cnt); i++) { + if (pinfo->is_snr_detail_en) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "snr[%d]=%d\n", i, pinfo->snr_statistic[i]); + } + + sum_snr_statistic += (u32)(pinfo->snr_statistic[i]); + + pinfo->snr_statistic_sqr[i] = (u16)(pinfo->snr_statistic[i] * pinfo->snr_statistic[i]); + } + + phydm_bubble_sort(dm, pinfo->snr_statistic, pinfo->total_cnt_snr); + + /*update SNR's cur mean*/ + pinfo->cur_snr_mean = (sum_snr_statistic >> real_shift); + + for (i = 0; (i <= total_loop_cnt); i++) { + if (pinfo->snr_statistic[i] >= pinfo->cur_snr_mean) + temp = pinfo->snr_statistic[i] - pinfo->cur_snr_mean; + else + temp = pinfo->cur_snr_mean - pinfo->snr_statistic[i]; + + pinfo->cur_snr_var += (temp * temp); + } + + /*update SNR's VAR*/ + pinfo->cur_snr_var = (pinfo->cur_snr_var >> real_shift); + + /*@acquire lower SNR's statistics*/ + temp = 0; + pinfo->cnt_lower_snr_statistic = (total_snr_cnt >> pinfo->lwr_snr_ratio_bit_shift); + pinfo->cnt_lower_snr_statistic = MAX_2(pinfo->cnt_lower_snr_statistic, SNR_RPT_MAX); + + for (i = 0; i < pinfo->cnt_lower_snr_statistic; i++) + temp += pinfo->snr_statistic[i]; + + pinfo->cur_lower_snr_mean = temp >> (real_shift - pinfo->lwr_snr_ratio_bit_shift); +} + +boolean phydm_is_snr_improve( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + boolean is_snr_improve; + u8 cur_state = pinfo->nxt_state; + u32 cur_mean = pinfo->cur_snr_mean; + u32 pre_mean = pinfo->pre_snr_mean; + u32 cur_lower_mean = pinfo->cur_lower_snr_mean; + u32 pre_lower_mean = pinfo->pre_lower_snr_mean; + u32 cur_var = pinfo->cur_snr_var; + + /*special case, zero VAR, interference is gone*/ + /*@make sure pre_var is larger enough*/ + if (cur_state == SAT_TABLE_MONITOR || + cur_state == ORI_TABLE_TRAINING) { + if (cur_mean >= pre_mean) { + if (cur_var == 0) + return true; + } + } +#if 0 + /*special case, mean degrade less than VAR improvement*/ + /*@make sure pre_var is larger enough*/ + if (cur_state == ORI_TABLE_MONITOR && + cur_mean < pre_mean && + cur_var < pre_var) { + diff_mean = pre_mean - cur_mean; + diff_var = pre_var - cur_var; + return (diff_var > (2 * diff_mean * diff_mean)) ? true : false; + } + +#endif + if (cur_lower_mean >= (pre_lower_mean + pinfo->delta_snr_mean)) + is_snr_improve = true; + else + is_snr_improve = false; +#if 0 +/* @condition refine, mean is bigger enough or VAR is smaller enough*/ +/* @1. from mean's view, mean improve delta_snr_mean(2), VAR not degrade lot*/ + if (cur_mean > (pre_mean + pinfo->delta_snr_mean)) { + is_mean_improve = TRUE; + is_var_improve = (cur_var <= pre_var + dm->delta_snr_var) + ? TRUE : FALSE; + + } else if (cur_var + dm->delta_snr_var <= pre_var) { + is_var_improve = TRUE; + is_mean_improve = ((cur_mean + 1) >= pre_mean) ? TRUE : FALSE; + } else { + return false; + } +#endif + return is_snr_improve; +} + +boolean phydm_is_snr_degrade( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u32 cur_lower_mean = pinfo->cur_lower_snr_mean; + u32 pre_lower_mean = pinfo->pre_lower_snr_mean; + boolean is_degrade; + + if (cur_lower_mean <= (pre_lower_mean - pinfo->delta_snr_mean)) + is_degrade = TRUE; + else + is_degrade = FALSE; +#if 0 + is_mean_dgrade = (pinfo->cur_snr_mean + pinfo->delta_snr_mean <= pinfo->pre_snr_mean) ? TRUE : FALSE; + is_var_degrade = (pinfo->cur_snr_var > (pinfo->pre_snr_var + pinfo->delta_snr_mean)) ? TRUE : FALSE; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d\n", + __func__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var); + + return (is_mean_dgrade & is_var_degrade); +#endif + return is_degrade; +} + +boolean phydm_is_large_var( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + boolean is_large_var = (pinfo->cur_snr_var >= pinfo->snr_var_thd) ? TRUE : FALSE; + + return is_large_var; +} + +void phydm_update_pre_status( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + pinfo->pre_lower_snr_mean = pinfo->cur_lower_snr_mean; + pinfo->pre_snr_mean = pinfo->cur_snr_mean; + pinfo->pre_snr_var = pinfo->cur_snr_var; +} + +void phydm_ori_table_monitor( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (phydm_is_large_var(dm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + /*switch to anti-sat table*/ + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } + phydm_update_pre_status(dm); + pinfo->pre_state = ORI_TABLE_MONITOR; +} + +void phydm_sat_table_training( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + #if 0 + if pre_state = ORI_TABLE_MONITOR || SAT_TABLE_TRY_FAIL, + /*@"pre" adapt ori-table, "cur" adapt sat-table*/ + /*@adapt ori table*/ + if (pinfo->pre_state == ORI_TABLE_MONITOR) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + #endif + if (phydm_is_snr_improve(dm)) { + pinfo->nxt_state = SAT_TABLE_MONITOR; + } else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } + /*@}*/ + + phydm_update_pre_status(dm); + pinfo->pre_state = SAT_TABLE_TRAINING; +} + +void phydm_sat_table_try_fail( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + /* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt ori-table */ + /* @if pre_state = SAT_TABLE_TRY_FAIL, "pre" adapt ori-table, "cur" adapt ori-table */ + + if (phydm_is_large_var(dm)) { + if (phydm_is_snr_degrade(dm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + } + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } + phydm_update_pre_status(dm); + pinfo->pre_state = SAT_TABLE_TRY_FAIL; +} + +void phydm_sat_table_monitor( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (phydm_is_snr_improve(dm)) { + pinfo->sat_table_monitor_times = 0; + + /* @if pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt sat-table */ + if (pinfo->pre_state == SAT_TABLE_MONITOR) { + pinfo->nxt_state = ORI_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + //phydm_update_pre_status(dm); + } else { + pinfo->nxt_state = SAT_TABLE_MONITOR; + } + + /* @if pre_state = SAT_TABLE_TRAINING, "pre" adapt sat-table, "cur" adapt sat-table */ + /* @if pre_state = ORI_TABLE_TRAINING, "pre" adapt ori-table, "cur" adapt sat-table */ + /*pre_state above is no need to update*/ + } else { + if (pinfo->sat_table_monitor_times == pinfo->force_change_period) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s: sat_table_monitor_times=%d\n", + __func__, pinfo->sat_table_monitor_times); + + pinfo->nxt_state = ORI_TABLE_TRAINING; + pinfo->sat_table_monitor_times = 0; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } else { + pinfo->nxt_state = SAT_TABLE_MONITOR; + pinfo->sat_table_monitor_times++; + } + } + phydm_update_pre_status(dm); + pinfo->pre_state = SAT_TABLE_MONITOR; +} + +void phydm_ori_table_training( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + /* pre_state = SAT_TABLE_MONITOR, "pre" adapt sat-table, "cur" adapt ori-table */ + + if (phydm_is_snr_degrade(dm) == FALSE) { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } else { + if (pinfo->pre_snr_var == 0) + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + else + pinfo->nxt_state = SAT_TABLE_MONITOR; + + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } + phydm_update_pre_status(dm); + pinfo->pre_state = ORI_TABLE_TRAINING; +} + +void phydm_ori_table_try_fail( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + + if (pinfo->pre_state == ORI_TABLE_TRY_FAIL) { + if (phydm_is_snr_improve(dm)) { + pinfo->nxt_state = ORI_TABLE_TRAINING; + pinfo->ori_table_try_fail_times = 0; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + } else { + if (pinfo->ori_table_try_fail_times == pinfo->force_change_period) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "%s: ori_table_try_fail_times=%d\n", __func__, pinfo->ori_table_try_fail_times); + + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times = 0; + phydm_update_pre_status(dm); + } else { + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times++; + phydm_update_pre_status(dm); + //config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } + } + } else { + pinfo->nxt_state = ORI_TABLE_TRY_FAIL; + pinfo->ori_table_try_fail_times = 0; + phydm_update_pre_status(dm); + //config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } + +#if 0 + if (phydm_is_large_var(dm)) { + if (phydm_is_snr_degrade(dm)) { + pinfo->nxt_state = SAT_TABLE_TRAINING; + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + } else { + pinfo->nxt_state = SAT_TABLE_TRY_FAIL; + } + } else { + pinfo->nxt_state = ORI_TABLE_MONITOR; + } + + phydm_update_pre_status(dm); +#endif + pinfo->pre_state = ORI_TABLE_TRY_FAIL; +} + +char *phydm_lna_sat_state_msg( + void *dm_void, + IN u8 state) +{ + char *dbg_message; + + switch (state) { + case ORI_TABLE_MONITOR: + dbg_message = "ORI_TABLE_MONITOR"; + break; + + case SAT_TABLE_TRAINING: + dbg_message = "SAT_TABLE_TRAINING"; + break; + + case SAT_TABLE_TRY_FAIL: + dbg_message = "SAT_TABLE_TRY_FAIL"; + break; + + case SAT_TABLE_MONITOR: + dbg_message = "SAT_TABLE_MONITOR"; + break; + + case ORI_TABLE_TRAINING: + dbg_message = "ORI_TABLE_TRAINING"; + break; + + case ORI_TABLE_TRY_FAIL: + dbg_message = "ORI_TABLE_TRY_FAIL"; + break; + + default: + dbg_message = "ORI_TABLE_MONITOR"; + break; + } + + return dbg_message; +} + +void phydm_lna_sat_type2_sm( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *pinfo = &dm->dm_lna_sat_info; + u8 state = pinfo->nxt_state; + u8 agc_tab = (u8)odm_get_bb_reg(dm, 0x958, 0x1f); + char *dbg_message, *nxt_dbg_message; + u8 real_shift = pinfo->total_bit_shift; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "\n\n%s ==>\n", __func__); + + if ((dm->support_ic_type & ODM_RTL8822B) == FALSE) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 only support 22B.\n"); + return; + } + + if ((dm->support_ability & ODM_BB_LNA_SAT_CHK) == FALSE) { + phydm_lna_sat_chk_type2_init(dm); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "ODM_BB_LNA_SAT_CHK_TYPE2 is NOT supported, cur table=%d\n", agc_tab); + return; + } + + if (pinfo->is_snr_done) + phydm_snr_data_processing(dm); + else + return; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "cur agc table %d\n", agc_tab); + + if (pinfo->is_force_lna_sat_table != AUTO_AGC_TABLE) { + /*reset state machine*/ + pinfo->nxt_state = ORI_TABLE_MONITOR; + if (pinfo->is_snr_done) { + if (pinfo->is_force_lna_sat_table == DEFAULT_AGC_TABLE) + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + else if (pinfo->is_force_lna_sat_table == LNA_SAT_AGC_TABLE) + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, LNA_SAT_AGC_TABLE); + else + config_phydm_switch_agc_tab_8822b(dm, *dm->channel, DEFAULT_AGC_TABLE); + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", + __func__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var, + pinfo->cur_lower_snr_mean, + pinfo->pre_lower_snr_mean, + pinfo->cnt_lower_snr_statistic); + + pinfo->is_snr_done = FALSE; + pinfo->is_sm_done = TRUE; + phydm_update_pre_status(dm); + } else { + return; + } + } else if (pinfo->is_snr_done) { + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "%s: cur_mean=%d, pre_mean=%d, cur_var=%d, pre_var=%d,cur_lower_mean=%d, pre_lower_mean=%d, cnt_lower_snr=%d\n", + __func__, + pinfo->cur_snr_mean, + pinfo->pre_snr_mean, + pinfo->cur_snr_var, + pinfo->pre_snr_var, + pinfo->cur_lower_snr_mean, + pinfo->pre_lower_snr_mean, + pinfo->cnt_lower_snr_statistic); + + switch (state) { + case ORI_TABLE_MONITOR: + dbg_message = "ORI_TABLE_MONITOR"; + phydm_ori_table_monitor(dm); + break; + + case SAT_TABLE_TRAINING: + dbg_message = "SAT_TABLE_TRAINING"; + phydm_sat_table_training(dm); + break; + + case SAT_TABLE_TRY_FAIL: + dbg_message = "SAT_TABLE_TRY_FAIL"; + phydm_sat_table_try_fail(dm); + break; + + case SAT_TABLE_MONITOR: + dbg_message = "SAT_TABLE_MONITOR"; + phydm_sat_table_monitor(dm); + break; + + case ORI_TABLE_TRAINING: + dbg_message = "ORI_TABLE_TRAINING"; + phydm_ori_table_training(dm); + break; + + case ORI_TABLE_TRY_FAIL: + dbg_message = "ORI_TABLE_TRAINING"; + phydm_ori_table_try_fail(dm); + break; + + default: + dbg_message = "ORI_TABLE_MONITOR"; + phydm_ori_table_monitor(dm); + break; + } + + dbg_message = phydm_lna_sat_state_msg(dm, state); + nxt_dbg_message = phydm_lna_sat_state_msg(dm, pinfo->nxt_state); + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "state: [%s]->[%s]\n", + dbg_message, nxt_dbg_message); + + pinfo->is_snr_done = FALSE; + pinfo->is_sm_done = TRUE; + pinfo->total_cnt_snr = 1 << real_shift; + + } else { + return; + } +} +#endif /*@#ifdef PHYDM_LNA_SAT_CHK_TYPE2*/ + +#ifdef PHYDM_HW_SWITCH_AGC_TAB +u32 phydm_get_lna_pd_reg(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 rf_pd_reg = RF_0x8b; + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + if (*dm->channel <= 14) + rf_pd_reg = RF_0x87; + else + rf_pd_reg = RF_0x8b; + } +#endif + return rf_pd_reg; +} + +u32 phydm_get_lna_pd_en_mask(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 rf_pd_en_msk = BIT(2); + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + if (*dm->channel <= 14) + rf_pd_en_msk = BIT(4); + else + rf_pd_en_msk = BIT(2); + } +#endif + return rf_pd_en_msk; +} + +boolean phydm_get_lna_pd_en(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 rf_pd_reg = RF_0x8b; + u32 rf_pd_en_msk = BIT(2); + u32 pd_en = 0; + + rf_pd_reg = phydm_get_lna_pd_reg(dm); + rf_pd_en_msk = phydm_get_lna_pd_en_mask(dm); + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) + pd_en = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A, + rf_pd_reg, + rf_pd_en_msk); +#endif + return (boolean)pd_en; +} + +void phydm_set_lna_pd_en(void *dm_void, boolean lna_pd_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path i = RF_PATH_A; + u32 rf_pd_reg = RF_0x8b; + u32 rf_pd_en_msk = BIT(2); + + rf_pd_reg = phydm_get_lna_pd_reg(dm); + rf_pd_en_msk = phydm_get_lna_pd_en_mask(dm); + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) + for (i = RF_PATH_A; i < MAX_PATH_NUM_8814B; i++) + config_phydm_write_rf_reg_8814b(dm, i, + rf_pd_reg, + rf_pd_en_msk, + (u8)lna_pd_en); +#endif +} + +u32 phydm_get_lna_pd_th_mask(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 rf_pd_th_msk = 0x3; + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) + rf_pd_th_msk = 0x3; +#endif + return rf_pd_th_msk; +} + +enum lna_pd_th_level phydm_get_lna_pd_th_lv(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 rf_pd_reg = RF_0x8b; + u32 rf_pd_th_msk = 0x3; + u32 pd_th_lv = 0x0; + + rf_pd_reg = phydm_get_lna_pd_reg(dm); + rf_pd_th_msk = phydm_get_lna_pd_th_mask(dm); + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) + pd_th_lv = config_phydm_read_rf_reg_8814b(dm, RF_PATH_A, + rf_pd_reg, + rf_pd_th_msk); +#endif + return (enum lna_pd_th_level)pd_th_lv; +} + +void phydm_set_lna_pd_th_lv(void *dm_void, + enum lna_pd_th_level lna_pd_th_lv) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + enum rf_path i = RF_PATH_A; + u32 rf_pd_reg = RF_0x8b; + u32 rf_pd_th_msk = 0x3; + + rf_pd_reg = phydm_get_lna_pd_reg(dm); + rf_pd_th_msk = phydm_get_lna_pd_th_mask(dm); + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) + for (i = RF_PATH_A; i < MAX_PATH_NUM_8814B; i++) + config_phydm_write_rf_reg_8814b(dm, i, + rf_pd_reg, + rf_pd_th_msk, + lna_pd_th_lv); +#endif +} + +u32 phydm_get_sat_agc_tab_version(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) + return odm_get_version_mp_8814b_extra_agc_tab(); +#endif + return 0; +} + +boolean phydm_get_auto_agc_config(void *dm_void, + enum agc_tab_switch_state state_sel) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 state_en = 0; +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + switch (state_sel) { + case AGC_SWH_IDLE: + state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(16)); + break; + case AGC_SWH_OFDM: + state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(17)); + break; + case AGC_SWH_CCK: + state_en = odm_get_bb_reg(dm, R_0x18ac, BIT(18)); + break; + default: + state_en = 0; + break; + } +#endif + return (boolean)state_en; +} + +boolean phydm_is_auto_agc_on(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + boolean state_on = false; + + state_on = ((phydm_get_auto_agc_config(dm, AGC_SWH_IDLE) || + phydm_get_auto_agc_config(dm, AGC_SWH_CCK) || + phydm_get_auto_agc_config(dm, AGC_SWH_OFDM)) && + phydm_get_lna_pd_en(dm)); + + return state_on; +} + +void phydm_config_auto_agc(void *dm_void, + boolean idle_en, + boolean cck_cca_en, + boolean ofdm_cca_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 hwagc_opt = 0; +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ~ODM_RTL8814B) + return; + + if (idle_en) + hwagc_opt |= BIT(0); + else + hwagc_opt &= ~BIT(0); + if (ofdm_cca_en) + hwagc_opt |= BIT(1); + else + hwagc_opt &= ~BIT(1); + if (cck_cca_en) + hwagc_opt |= BIT(2); + else + hwagc_opt &= ~BIT(2); + + odm_set_bb_reg(dm, R_0x18ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt); +#ifdef PHYDM_COMPILE_ABOVE_2SS + odm_set_bb_reg(dm, R_0x41ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt); +#endif +#ifdef PHYDM_COMPILE_ABOVE_3SS + odm_set_bb_reg(dm, R_0x52ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt); +#endif +#ifdef PHYDM_COMPILE_ABOVE_4SS + odm_set_bb_reg(dm, R_0x53ac, BIT(18) | BIT(17) | BIT(16), hwagc_opt); +#endif +#endif +} + +void phydm_auto_agc_tab_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_set_lna_pd_th_lv(dm, 0x0); + phydm_config_auto_agc(dm, true, false, true); + phydm_set_lna_pd_en(dm, true); +} + +void phydm_auto_agc_tab_off(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_config_auto_agc(dm, false, false, false); + phydm_set_lna_pd_en(dm, false); +} + +void phydm_switch_sat_agc_by_band(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + +#if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) + odm_config_mp_8814b_extra_agc_tab(dm, lna_sat->cur_rf_band); +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + pr_debug("%s ==> switch to band%d\n", __func__, lna_sat->cur_rf_band); +#else + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==> switch to band%d\n", + __func__, lna_sat->cur_rf_band); +#endif +} + +void phydm_auto_agc_tab_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + u8 channel = *dm->channel; + + lna_sat->cur_rf_band = phydm_ch_to_rf_band(dm, channel); + phydm_switch_sat_agc_by_band(dm); + + if ((dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + phydm_auto_agc_tab_reset(dm); + lna_sat->hw_swh_tab_on = true; + } else { + phydm_auto_agc_tab_off(dm); + lna_sat->hw_swh_tab_on = false; + } +} + +void phydm_auto_agc_tab_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + boolean hw_swh_on = false; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + if (!(dm->support_ability & ODM_BB_LNA_SAT_CHK)) { + if (lna_sat->hw_swh_tab_on) { + phydm_auto_agc_tab_off(dm); + lna_sat->hw_swh_tab_on = false; + } + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "Disabled LNA sat. check\n"); + return; + } + + if (!lna_sat->hw_swh_tab_on) + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, + "[WARNING] HW switch AGC Tab not fully enabled\n"); +} + +void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + u8 agc_tab = 0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "LNA sat. AGC Tab version : %d\n", + phydm_get_sat_agc_tab_version(dm)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Enable LNA peak detector : {0} {lna_pd_en = %d}\n", + phydm_get_lna_pd_en(dm)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set LNA peak detector lv : {1} {lna_pd_th_lv = %d}\n", + phydm_get_lna_pd_th_lv(dm)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Config hw switch AGC tab : {2} {hw_swh_en_rx_idle} {hw_swh_en_cck_cca} {hw_swh_en_ofdm_cca} = (%d, %d, %d)\n", + phydm_get_auto_agc_config(dm, AGC_SWH_IDLE), + phydm_get_auto_agc_config(dm, AGC_SWH_CCK), + phydm_get_auto_agc_config(dm, AGC_SWH_OFDM)); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Reset to default setting : {3}\n", + phydm_get_auto_agc_config(dm, AGC_SWH_IDLE), + phydm_get_auto_agc_config(dm, AGC_SWH_CCK), + phydm_get_auto_agc_config(dm, AGC_SWH_OFDM)); + + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + for (i = 1; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + + if (var1[0] == 0) { + phydm_set_lna_pd_en(dm, (boolean)var1[1]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "set lna_pd_en = %d\n", + (u8)phydm_get_lna_pd_en(dm)); + } else if (var1[0] == 1) { + phydm_set_lna_pd_th_lv(dm, (u8)var1[1]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "set lna_pd_th_lv = %d\n", + phydm_get_lna_pd_th_lv(dm)); + } else if (var1[0] == 2) { + phydm_config_auto_agc(dm, (boolean)var1[1], + (boolean)var1[2], + (boolean)var1[3]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "set hw switch agc tab en: (rx_idle, cck_cca, ofdm_cca) = (%d, %d, %d)\n", + phydm_get_auto_agc_config(dm, AGC_SWH_IDLE), + phydm_get_auto_agc_config(dm, AGC_SWH_CCK), + phydm_get_auto_agc_config(dm, AGC_SWH_OFDM)); + } else if (var1[0] == 3) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "reset to default settings\n"); + phydm_auto_agc_tab_reset(dm); + } + lna_sat->hw_swh_tab_on = phydm_is_auto_agc_on(dm); + } + *_used = used; + *_out_len = out_len; +} +#endif /*@#ifdef PHYDM_HW_SWITCH_AGC_TAB*/ + +void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_t = &dm->dm_lna_sat_info; + char help[] = "-h"; + char monitor[] = "-m"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + u8 agc_tab = 0; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "monitor: -m\n"); + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {lna_sat_chk_en}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {agc_table_switch_en}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {chk_cnt per callback}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {chk_period(ms)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} {chk_duty_cycle(%)}\n"); + #endif + } else if ((strcmp(input[1], monitor) == 0)) { +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8814B)) + agc_tab = phydm_get_ofdm_agc_tab_path(dm, RF_PATH_A); + else + #endif + agc_tab = phydm_get_ofdm_agc_tab(dm); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "%s%d, %s%d, %s%d, %s%d\n", + "check_time = ", lna_t->check_time, + "pre_sat_status = ", lna_t->pre_sat_status, + "cur_sat_status = ", lna_t->cur_sat_status, + "current AGC tab = ", agc_tab); +#endif + } else { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + for (i = 1; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + if (var1[0] == 0) { + if (var1[1] == 1) + lna_t->is_disable_lna_sat_chk = false; + else if (var1[1] == 0) + lna_t->is_disable_lna_sat_chk = true; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "dis_lna_sat_chk=%d\n", + lna_t->is_disable_lna_sat_chk); + } else if (var1[0] == 1) { + if (var1[1] == 1) + lna_t->dis_agc_table_swh = false; + else if (var1[1] == 0) + lna_t->dis_agc_table_swh = true; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "dis_agc_table_swh=%d\n", + lna_t->dis_agc_table_swh); + + } else if (var1[0] == 2) { + lna_t->chk_cnt = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "chk_cnt=%d\n", lna_t->chk_cnt); + } else if (var1[0] == 3) { + lna_t->chk_period = var1[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "chk_period=%d\n", lna_t->chk_period); + } else if (var1[0] == 4) { + lna_t->chk_duty_cycle = (u8)var1[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "chk_duty_cycle=%d\n", + lna_t->chk_duty_cycle); + } + #endif + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + if (var1[0] == 1) + lna_t->force_traget_macid = var1[1]; + #endif + } + *_used = used; + *_out_len = out_len; +} + +void phydm_lna_sat_chk_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "%s ==>\n", __func__); + + if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) { + #ifdef PHYDM_HW_SWITCH_AGC_TAB + if (dm->support_ic_type & ODM_RTL8814B) { + phydm_auto_agc_tab_watchdog(dm); + return; + } + #endif + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8814B)) { + phydm_lna_sat_chk_watchdog_type1(dm); + return; + } + #endif + } else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) { + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + return; + #endif + } + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "support_ic_type match fail, return\n"); +} + +void phydm_lna_sat_config(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + + lna_sat->lna_sat_type = 0; + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8822B)) + lna_sat->lna_sat_type = LNA_SAT_WITH_TRAIN; + #endif + + #if (RTL8197F_SUPPORT || RTL8192F_SUPPORT || \ + RTL8198F_SUPPORT || RTL8814B_SUPPORT) + if (dm->support_ic_type & + (ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8198F | ODM_RTL8814B)) + lna_sat->lna_sat_type = LNA_SAT_WITH_PEAK_DET; + #endif + + PHYDM_DBG(dm, DBG_LNA_SAT_CHK, "[%s] lna_sat_type=%d\n", + __func__, lna_sat->lna_sat_type); +} + +void phydm_lna_sat_check_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_lna_sat_t *lna_sat = &dm->dm_lna_sat_info; + + /*@2018.04.17 Johnson*/ + phydm_lna_sat_config(dm); + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + lna_sat->chk_period = LNA_CHK_PERIOD; + lna_sat->chk_cnt = LNA_CHK_CNT; + lna_sat->chk_duty_cycle = LNA_CHK_DUTY_CYCLE; + lna_sat->dis_agc_table_swh = false; + #endif + /*@2018.04.17 Johnson end*/ + + if (lna_sat->lna_sat_type == LNA_SAT_WITH_PEAK_DET) { + #ifdef PHYDM_HW_SWITCH_AGC_TAB + if (dm->support_ic_type & ODM_RTL8814B) { + phydm_auto_agc_tab_init(dm); + return; + } + #endif + #ifdef PHYDM_LNA_SAT_CHK_TYPE1 + phydm_lna_sat_chk_init(dm); + #endif + } else if (lna_sat->lna_sat_type == LNA_SAT_WITH_TRAIN) { + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + phydm_lna_sat_chk_type2_init(dm); + #endif + } +} + +#endif /*@#ifdef PHYDM_LNA_SAT_CHK_SUPPORT*/ diff --git a/hal/phydm/phydm_lna_sat.h b/hal/phydm/phydm_lna_sat.h new file mode 100644 index 0000000..69a9349 --- /dev/null +++ b/hal/phydm/phydm_lna_sat.h @@ -0,0 +1,196 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_LNA_SAT_H__ +#define __PHYDM_LNA_SAT_H__ +#ifdef PHYDM_LNA_SAT_CHK_SUPPORT +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#define LNA_SAT_VERSION "1.1" + +/*@LNA saturation check*/ +#define OFDM_AGC_TAB_0 0 +#define OFDM_AGC_TAB_2 2 + +#define DIFF_RSSI_TO_IGI 10 +#define ONE_SEC_MS 1000 + +#define LNA_CHK_PERIOD 100 /*@ms*/ +#define LNA_CHK_CNT 10 /*@checks per callback*/ +#define LNA_CHK_DUTY_CYCLE 5 /*@percentage*/ + +#define DELTA_STD 2 +#define DELTA_MEAN 2 +#define SNR_STATISTIC_SHIFT 8 +#define SNR_RPT_MAX 256 + +/* @1 ============================================================ + * 1 enumrate + * 1 ============================================================ + */ + +enum lna_sat_timer_state { + INIT_LNA_SAT_CHK_TIMMER, + CANCEL_LNA_SAT_CHK_TIMMER, + RELEASE_LNA_SAT_CHK_TIMMER +}; + +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 +enum lna_sat_chk_type2_status { + ORI_TABLE_MONITOR, + ORI_TABLE_TRAINING, + SAT_TABLE_MONITOR, + SAT_TABLE_TRAINING, + SAT_TABLE_TRY_FAIL, + ORI_TABLE_TRY_FAIL +}; + +#endif + +enum lna_sat_type { + LNA_SAT_WITH_PEAK_DET = 1, /*type1*/ + LNA_SAT_WITH_TRAIN = 2, /*type2*/ +}; + +#ifdef PHYDM_HW_SWITCH_AGC_TAB +enum lna_pd_th_level { + LNA_PD_TH_LEVEL0 = 0, + LNA_PD_TH_LEVEL1 = 1, + LNA_PD_TH_LEVEL2 = 2, + LNA_PD_TH_LEVEL3 = 3 +}; + +enum agc_tab_switch_state { + AGC_SWH_IDLE, + AGC_SWH_CCK, + AGC_SWH_OFDM +}; +#endif + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +struct phydm_lna_sat_t { +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 + u8 chk_cnt; + u8 chk_duty_cycle; + u32 chk_period;/*@ms*/ + boolean is_disable_lna_sat_chk; + boolean dis_agc_table_swh; +#endif +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 + u8 force_traget_macid; + u32 snr_var_thd; + u32 delta_snr_mean; + u16 ori_table_try_fail_times; + u16 cnt_lower_snr_statistic; + u16 sat_table_monitor_times; + u16 force_change_period; + u8 is_snr_detail_en; + u8 is_force_lna_sat_table; + u8 lwr_snr_ratio_bit_shift; + u8 cnt_snr_statistic; + u16 snr_statistic_sqr[SNR_RPT_MAX]; + u8 snr_statistic[SNR_RPT_MAX]; + u8 is_sm_done; + u8 is_snr_done; + u32 cur_snr_var; + u8 total_bit_shift; + u8 total_cnt_snr; + u32 cur_snr_mean; + u8 cur_snr_var0; + u32 cur_lower_snr_mean; + u32 pre_snr_mean; + u32 pre_snr_var; + u32 pre_lower_snr_mean; + u8 nxt_state; + u8 pre_state; +#endif + enum lna_sat_type lna_sat_type; + u32 sat_cnt_acc_patha; + u32 sat_cnt_acc_pathb; +#ifdef PHYDM_IC_ABOVE_3SS + u32 sat_cnt_acc_pathc; +#endif +#ifdef PHYDM_IC_ABOVE_4SS + u32 sat_cnt_acc_pathd; +#endif + u32 check_time; + boolean pre_sat_status; + boolean cur_sat_status; +#ifdef PHYDM_HW_SWITCH_AGC_TAB + boolean hw_swh_tab_on; + enum odm_rf_band cur_rf_band; +#endif + struct phydm_timer_list phydm_lna_sat_chk_timer; + u32 cur_timer_check_cnt; + u32 pre_timer_check_cnt; +}; + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_lna_sat_chk_init(void *dm_void); + +u8 phydm_get_ofdm_agc_tab(void *dm_void); + +void phydm_lna_sat_chk(void *dm_void); + +void phydm_lna_sat_chk_timers(void *dm_void, u8 state); + +#ifdef PHYDM_LNA_SAT_CHK_TYPE1 +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT) +void phydm_lna_sat_chk_bb_init(void *dm_void); + +void phydm_set_ofdm_agc_tab_path(void *dm_void, + u8 tab_sel, enum rf_path path); + +u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path); +#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/ +#endif + +#ifdef PHYDM_LNA_SAT_CHK_TYPE2 +void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr); +#endif + +void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_lna_sat_chk_watchdog(void *dm_void); + +void phydm_lna_sat_check_init(void *dm_void); + +#ifdef PHYDM_HW_SWITCH_AGC_TAB +void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif +#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/ +#endif diff --git a/hal/phydm/phydm_math_lib.c b/hal/phydm/phydm_math_lib.c new file mode 100644 index 0000000..c6c1035 --- /dev/null +++ b/hal/phydm/phydm_math_lib.c @@ -0,0 +1,290 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +const u32 db_invert_table[12][8] = { + {10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */ + {64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */ + {401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */ + {316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */ + {1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */ + {12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */ + {79433, 100000, 125893, 158489, 199526, 251189, 316228, + 398107}, /* @U(32,0) */ + {501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262, + 2511886}, /* @U(32,0) */ + {3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254, + 15848932}, /* @U(32,0) */ + {19952623, 25118864, 31622777, 39810717, 50118723, 63095734, + 79432823, 100000000}, /* @U(32,0) */ + {125892541, 158489319, 199526232, 251188643, 316227766, 398107171, + 501187234, 630957345}, /* @U(32,0) */ + {794328235, 1000000000, 1258925412, 1584893192, 1995262315, + 2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */ + +/*Y = 10*log(X)*/ +s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit) +{ + s32 Y, integer = 0, decimal = 0; + u32 i; + + if (X == 0) + X = 1; /* @log2(x), x can't be 0 */ + + for (i = (total_bit - 1); i > 0; i--) { + if (X & BIT(i)) { + integer = i; + if (i > 0) { + /*decimal is 0.5dB*3=1.5dB~=2dB */ + decimal = (X & BIT(i - 1)) ? 2 : 0; + } + break; + } + } + + Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */ + + return Y; +} + +s32 odm_sign_conversion(s32 value, u32 total_bit) +{ + if (value & BIT(total_bit - 1)) + value -= BIT(total_bit); + + return value; +} + +/*threshold must form low to high*/ +u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u16 i = 0; + u16 ret_val = 0; + u16 max_th = threshold[th_len - 1]; + + for (i = 0; i < th_len; i++) { + if (val < threshold[i]) { + ret_val = i; + break; + } else if (val >= max_th) { + ret_val = th_len; + break; + } + } + + return ret_val; +} + +void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out, + u8 seq_length) +{ + u8 i = 0, j = 0; + u32 tmp_a, tmp_b; + u32 tmp_idx_a, tmp_idx_b; + + for (i = 0; i < seq_length; i++) + rank_idx[i] = i; + + for (i = 0; i < (seq_length - 1); i++) { + for (j = 0; j < (seq_length - 1 - i); j++) { + tmp_a = value[j]; + tmp_b = value[j + 1]; + + tmp_idx_a = rank_idx[j]; + tmp_idx_b = rank_idx[j + 1]; + + if (tmp_a < tmp_b) { + value[j] = tmp_b; + value[j + 1] = tmp_a; + + rank_idx[j] = tmp_idx_b; + rank_idx[j + 1] = tmp_idx_a; + } + } + } + + for (i = 0; i < seq_length; i++) + idx_out[rank_idx[i]] = i + 1; +} + +u32 odm_convert_to_db(u64 value) +{ + u8 i; + u8 j; + u32 dB; + + if (value >= db_invert_table[11][7]) + return 96; /* @maximum 96 dB */ + + for (i = 0; i < 12; i++) { + if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][7]) + break; + else if (i > 2 && value <= db_invert_table[i][7]) + break; + } + + for (j = 0; j < 8; j++) { + if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][j]) + break; + else if (i > 2 && i < 12 && value <= db_invert_table[i][j]) + break; + } + + /*special cases*/ + if (j == 0 && i == 0) + goto end; + + if (i == 3 && j == 0) { + if (db_invert_table[3][0] - value > + value - (db_invert_table[2][7] >> FRAC_BITS)) { + i = 2; + j = 7; + } + goto end; + } + + if (i < 3) + value = value << FRAC_BITS; /*@elements of row 0~2 shift left*/ + + /*compare difference to get precise dB*/ + if (j == 0) { + if (db_invert_table[i][j] - value > + value - db_invert_table[i - 1][7]) { + i = i - 1; + j = 7; + } + } else { + if (db_invert_table[i][j] - value > + value - db_invert_table[i][j - 1]) { + j = j - 1; + } + } +end: + dB = (i << 3) + j + 1; + + return dB; +} + +u64 phydm_db_2_linear(u32 value) +{ + u8 i = 0; + u8 j = 0; + u64 linear = 0; + + value = value & 0xFF; + + /* @1dB~96dB */ + if (value > 96) { + value = 96; + } else if (value < 1) { + linear = 1; + return linear; + } + + i = (u8)((value - 1) >> 3); + j = (u8)(value - 1) - (i << 3); + + linear = db_invert_table[i][j]; + + if (i > 2) + linear = linear << FRAC_BITS; + + return linear; +} + +u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num) +{ + u8 i = 0; + u16 val = 0; + u16 base = 5000; + + for (i = bit_num; i > 0; i--) { + if (frac_val & BIT(i - 1)) + val += (base >> (bit_num - i)); + } + return val; +} + +u16 phydm_ones_num_in_bitmap(u64 val, u8 size) +{ + u8 i = 0; + u8 ones_num = 0; + + for (i = 0; i < size; i++) { + if (val & BIT(0)) + ones_num++; + + val = val >> 1; + } + + return ones_num; +} + +u64 phydm_gen_bitmask(u8 mask_num) +{ + u8 i = 0; + u64 bitmask = 0; + + if (mask_num > 64) + return 1; + + for (i = 0; i < mask_num; i++) + bitmask = (bitmask << 1) | BIT(0); + + return bitmask; +} + +s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num) +{ + if (bit_num >= 32) + return (s32)val; + + if (val & BIT(bit_num - 1)) /*Sign BIT*/ + val -= (1 << bit_num); /*@2's*/ + + return val; +} + +s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num) +{ + u64 one = 1; + s64 val_sign = (s64)val; + + if (bit_num >= 64) + return (s64)val; + + if (val & (one << (bit_num - 1))) /*Sign BIT*/ + val_sign = val - (one << bit_num); /*@2's*/ + + return val_sign; +} + diff --git a/hal/phydm/phydm_math_lib.h b/hal/phydm/phydm_math_lib.h new file mode 100644 index 0000000..a96ae5e --- /dev/null +++ b/hal/phydm/phydm_math_lib.h @@ -0,0 +1,120 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_MATH_LIB_H__ +#define __PHYDM_MATH_LIB_H__ + +/* @2019.01.24 remove linear2db debug log*/ +#define AUTO_MATH_LIB_VERSION "1.2" + +/*@ + * 1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +#define PHYDM_DIV(a, b) ((b) ? ((a) / (b)) : 0) +#define DIVIDED_2(X) ((X) >> 1) +/*@1/3 ~ 11/32*/ +#if defined(DM_ODM_CE_MAC80211) +#define DIVIDED_3(X) ({ \ + u32 div_3_tmp = (X); \ + (((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); }) +#else +#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5) +#endif +#define DIVIDED_4(X) ((X) >> 2) + +/*Store Ori Value*/ +#if defined(DM_ODM_CE_MAC80211) +#define WEIGHTING_AVG(v1, w1, v2, w2) \ + __WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \ + typeof(w2)) +#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4) ({ \ + t1 __w_a_v1 = (v1); \ + t2 __w_a_w1 = (w1); \ + t3 __w_a_v2 = (v2); \ + t4 __w_a_w2 = (w2); \ + ((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2)) \ + / ((__w_a_w2) + (__w_a_w1)); }) +#else +#define WEIGHTING_AVG(v1, w1, v2, w2) \ + (((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1))) +#endif + +/*Store 2^ma x Value*/ +#if defined(DM_ODM_CE_MAC80211) +#define MA_ACC(old, new_val, ma) ({ \ + s16 __ma_acc_o = (old); \ + (__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); }) +#define GET_MA_VAL(val, ma) ({ \ + s16 __get_ma_tmp = (ma);\ + ((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); }) +#else +#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val)) +#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma)) +#endif +#define FRAC_BITS 3 +/*@ + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +/*@ + * 1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +/*@ + * 1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ + +s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit); + +s32 odm_sign_conversion(s32 value, u32 total_bit); + +u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len); + +void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out, + u8 seq_length); + +u32 odm_convert_to_db(u64 value); + +u64 phydm_db_2_linear(u32 value); + +u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num); + +u16 phydm_ones_num_in_bitmap(u64 val, u8 size); + +u64 phydm_gen_bitmask(u8 mask_num); + +s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num); + +s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num); +#endif diff --git a/hal/phydm/phydm_mp.c b/hal/phydm/phydm_mp.c new file mode 100644 index 0000000..4b2bd52 --- /dev/null +++ b/hal/phydm/phydm_mp.c @@ -0,0 +1,408 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_MP_SUPPORT +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + +void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone, + u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + u8 start = RF_PATH_A, end = RF_PATH_A; + u8 i = 0; + u8 central_ch = 0; + boolean is_2g_ch = false; + + switch (path) { + case RF_PATH_A: + case RF_PATH_B: + case RF_PATH_C: + case RF_PATH_D: + start = path; + end = path; + break; + case RF_PATH_AB: + start = RF_PATH_A; + end = RF_PATH_B; + break; +#if (defined(PHYDM_COMPILE_IC_4SS)) + case RF_PATH_AC: + start = RF_PATH_A; + end = RF_PATH_C; + break; + case RF_PATH_AD: + start = RF_PATH_A; + end = RF_PATH_D; + break; + case RF_PATH_BC: + start = RF_PATH_B; + end = RF_PATH_C; + break; + case RF_PATH_BD: + start = RF_PATH_B; + end = RF_PATH_D; + break; + case RF_PATH_CD: + start = RF_PATH_C; + end = RF_PATH_D; + break; + case RF_PATH_ABC: + start = RF_PATH_A; + end = RF_PATH_C; + break; + case RF_PATH_ABD: + start = RF_PATH_A; + end = RF_PATH_D; + break; + case RF_PATH_ACD: + start = RF_PATH_A; + end = RF_PATH_D; + break; + case RF_PATH_BCD: + start = RF_PATH_B; + end = RF_PATH_D; + break; + case RF_PATH_ABCD: + start = RF_PATH_A; + end = RF_PATH_D; + break; +#endif + } + + central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff); + is_2g_ch = (central_ch <= 14) ? true : false; + + if (is_single_tone) { + /*Disable CCA*/ + if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/ + if(dm->support_ic_type & ODM_RTL8723F) { + odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1); /*CCK*/ + } else { + odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0); + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3); + } + } + odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*OFDM*/ + if (dm->support_ic_type & ODM_RTL8723F) { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x0); + for (i = start; i <= end; i++) { + mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK); + /*Tx mode: RF0x00[19:16]=4'b0010 */ + odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2); + /*Lowest RF gain index: RF_0x1[5:0] TX power*/ + mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK); + odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power + /*RF LO enabled */ + odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1); + } + } else { + for (i = start; i <= end; i++) { + mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK); + /*Tx mode: RF0x00[19:16]=4'b0010 */ + odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2); + /*Lowest RF gain index: RF_0x0[4:0] = 0*/ + odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0); + /*RF LO enabled */ + odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1); + } + } + + #if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b( + dm, RF_SYN0, RF_0x0, RFREG_MASK); + /*Lowest RF gain index: RF_0x0[4:0] = 0x0*/ + config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0, + 0x1f, 0x0); + /*RF LO enabled */ + config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58, + BIT(1), 0x1); + /*SYN1*/ + if (*dm->band_width == CHANNEL_WIDTH_80_80) { + mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b( + dm, RF_SYN1, RF_0x0, + RFREG_MASK); + config_phydm_write_rf_syn_8814b(dm, RF_SYN1, + RF_0x0, 0x1f, + 0x0); + config_phydm_write_rf_syn_8814b(dm, RF_SYN1, + RF_0x58, BIT(1), + 0x1); + } + } + #endif + } else { + /*Enable CCA*/ + if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/ + if(dm->support_ic_type & ODM_RTL8723F) { + odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0); /*CCK*/ + } else { + odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1); + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0); + } + } + odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0); /*OFDM*/ + + if(dm->support_ic_type & ODM_RTL8723F) { + for (i = start; i <= end; i++) { + odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]); + odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]); + /*RF LO disabled */ + odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0); + } + odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x1); + } else { + for (i = start; i <= end; i++) { + odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]); + /*RF LO disabled */ + odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0); + } + } + #if (RTL8814B_SUPPORT) + if (dm->support_ic_type & ODM_RTL8814B) { + config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0, + RFREG_MASK, + mp->rf0_syn[RF_SYN0]); + config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58, + BIT(1), 0x0); + /*SYN1*/ + if (*dm->band_width == CHANNEL_WIDTH_80_80) { + config_phydm_write_rf_syn_8814b(dm, RF_SYN1, + RF_0x0, + RFREG_MASK, + mp->rf0_syn[RF_SYN1]); + config_phydm_write_rf_syn_8814b(dm, RF_SYN1, + RF_0x58, BIT(1), + 0x0); + } + } + #endif + } +} + +void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp, + u32 rate_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + + if (is_carrier_supp) { + if (phydm_is_cck_rate(dm, (u8)rate_index)) { + /*if CCK block on? */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1); + + if(dm->support_ic_type & ODM_RTL8723F){ + /* @Carrier suppress tx */ + odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1); + /*turn off scramble setting */ + odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1); + /*Set CCK Tx Test Rate, set TxRate to 2Mbps */ + odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1); + /* BB and PMAC cont tx */ + odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1); + odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1); + /* TX CCK ON */ + odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0); + odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1); + } + else { + /*Turn Off All Test mode */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0); + + /*transmit mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); + /*turn off scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0); + /*Set CCK Tx Test Rate, set TxRate to 1Mbps */ + odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0); + } + } + } else { /*Stop Carrier Suppression. */ + if (phydm_is_cck_rate(dm, (u8)rate_index)) { + if(dm->support_ic_type & ODM_RTL8723F) { + /* TX Stop */ + odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1); + /* Clear BB cont tx */ + odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0); + /* Clear PMAC cont tx */ + odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0); + /* Clear TX Stop */ + odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0); + /* normal mode */ + odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0); + /* turn on scramble setting */ + odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); + } + else { + /*normal mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); + /*turn on scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); + } + /*BB Reset */ + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1); + } + } +} + +void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + + if (is_single_carrier) { + /*1. if OFDM block on? */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1); + + if (dm->support_ic_type & ODM_RTL8723F) { + /*3. turn on scramble setting */ + odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0); + /*4. Turn On single carrier. */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER); + } + else { + /*2. set CCK test mode off, set to CCK normal mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0); + /*3. turn on scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1); + /*4. Turn On single carrier. */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER); + } + } else { + /*Turn off all test modes. */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF); + + /*Delay 10 ms */ + ODM_delay_ms(10); + + /*BB Reset*/ + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1); + } +} + +void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + + if (phydm_is_cck_rate(dm, (u8)rate_index)) + mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD); + else + mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD); +} + +void phydm_mp_get_rx_ok_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_mp *mp = &dm->dm_mp_table; + + u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0; + u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0; + if(dm->support_ic_type & ODM_RTL8723F) + cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD); + else + cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD); + ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD); + ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD); + vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD); + if(dm->support_ic_type & ODM_RTL8723F) + cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD); + else + cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD); + ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD); + ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD); + vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD); + + mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok; + mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err; + mp->io_value = (u32)mp->rx_phy_ok_cnt; +} +#endif +void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_set_crystal_cap(dm, crystal_cap); +} + +void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path); +} + +void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp, + u32 rate_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index); +} + +void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier); +} +void phydm_mp_reset_rx_counters_phy(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_reset_bb_hw_cnt(dm); +} + +void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_mp_get_tx_ok_jgr3(dm, rate_index); +} + +void phydm_mp_get_rx_ok(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_mp_get_rx_ok_jgr3(dm); +} +#endif diff --git a/hal/phydm/phydm_mp.h b/hal/phydm/phydm_mp.h new file mode 100644 index 0000000..5805a03 --- /dev/null +++ b/hal/phydm/phydm_mp.h @@ -0,0 +1,83 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_MP_H__ +#define __PHYDM_MP_H__ + +/*2020.04.27 Refine single tone Tx flow*/ +#define MP_VERSION "1.5" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct phydm_mp { + /*Rx OK count, statistics used in Mass Production Test.*/ + u64 tx_phy_ok_cnt; + u64 rx_phy_ok_cnt; + /*Rx CRC32 error count, statistics used in Mass Production Test.*/ + u64 rx_phy_crc_err_cnt; + /*The Value of IO operation is depend of MptActType.*/ + u32 io_value; + u32 rf0[RF_PATH_MEM_SIZE]; + #if (RTL8814B_SUPPORT) + u32 rf0_syn[2]; + #endif + u32 rf1[RF_PATH_MEM_SIZE]; +}; + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ +enum TX_MODE_OFDM { + OFDM_OFF = 0, + OFDM_CONT_TX = 1, + OFDM_SINGLE_CARRIER = 2, + OFDM_SINGLE_TONE = 4, +}; +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap); + +void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path); + +void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp, + u32 rate_index); + +void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier); + +void phydm_mp_reset_rx_counters_phy(void *dm_void); + +void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index); + +void phydm_mp_get_rx_ok(void *dm_void); +#endif diff --git a/hal/phydm/phydm_noisemonitor.c b/hal/phydm/phydm_noisemonitor.c new file mode 100644 index 0000000..d2e95cf --- /dev/null +++ b/hal/phydm/phydm_noisemonitor.c @@ -0,0 +1,467 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/************************************************** + * This function is for inband noise test utility only + * To obtain the inband noise level(dbm), do the following. + * 1. disable DIG and Power Saving + * 2. Set initial gain = 0x1a + * 3. Stop updating idle time pwer report (for driver read) + * - 0x80c[25] + * + *************************************************/ + +void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path) +{ + u8 i = 0; + + for (i = RF_PATH_A; i < max_rf_path; i++) { + if (noise_data->valid_cnt[i]) + noise_data->sum[i] /= noise_data->valid_cnt[i]; + else + noise_data->sum[i] = 0; + } +} + +#if (ODM_IC_11N_SERIES_SUPPORT) +s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi, + u32 max_time) +{ + u32 tmp4b; + u8 max_rf_path = 0, i = 0; + u8 reg_c50, reg_c58, valid_done = 0; + struct noise_level noise_data; + u64 start = 0, func_start = 0, func_end = 0; + s8 val_s8 = 0; + + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; + + if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R) + max_rf_path = 2; + else + max_rf_path = 1; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "odm_DebugControlInbandNoise_Nseries() ==>\n"); + + odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level)); + /* step 1. Disable DIG && Set initial gain. */ + + if (is_pause_dig) + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi); + + /* step 3. Get noise power level */ + start = odm_get_current_time(dm); + while (1) { + /* Stop updating idle time pwer report (for driver read) */ + odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1); + + /* Read Noise Floor Report */ + tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD); + + /* update idle time pwer report per 5us */ + odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0); + + ODM_delay_us(5); + + noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + + for (i = RF_PATH_A; i < max_rf_path; i++) { + noise_data.sval[i] = (s8)noise_data.value[i]; + noise_data.sval[i] /= 2; + } + + for (i = RF_PATH_A; i < max_rf_path; i++) { + if (noise_data.valid_cnt[i] >= VALID_CNT) + continue; + + noise_data.valid_cnt[i]++; + noise_data.sum[i] += noise_data.sval[i]; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "rf_path:%d Valid sval=%d\n", i, + noise_data.sval[i]); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", + noise_data.sum[i]); + if (noise_data.valid_cnt[i] == VALID_CNT) + valid_done++; + } + if (valid_done == max_rf_path || + (odm_get_progressing_time(dm, start) > max_time)) { + phydm_set_noise_data_sum(&noise_data, max_rf_path); + break; + } + } + reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0); + reg_c50 &= ~BIT(7); + val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]); + dm->noise_level.noise[RF_PATH_A] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A]; + + if (max_rf_path == 2) { + reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0); + reg_c58 &= ~BIT(7); + val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]); + dm->noise_level.noise[RF_PATH_B] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B]; + } + dm->noise_level.noise_all /= max_rf_path; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "noise_a = %d, noise_b = %d, noise_all = %d\n", + dm->noise_level.noise[RF_PATH_A], + dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all); + + /* step 4. Recover the Dig */ + if (is_pause_dig) + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi); + func_end = odm_get_progressing_time(dm, func_start); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n"); + return dm->noise_level.noise_all; +} +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT) +s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig, + u8 igi, u32 max_time) +{ + u32 tmp4b; + u8 max_rf_path = 0, i = 0; + u8 reg_c50, reg_e50, valid_done = 0; + u64 start = 0, func_start = 0, func_end = 0; + struct noise_level noise_data; + s8 val_s8 = 0; + + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; + + if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R) + max_rf_path = 2; + else + max_rf_path = 1; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__); + + odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level)); + + /*Step 1. Disable DIG && Set initial gain.*/ + + if (pause_dig) + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi); + + /*Step 2. Get noise power level*/ + start = odm_get_current_time(dm); + + while (1) { + /*Stop updating idle time pwer report (for driver read)*/ + odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1); + + /*Read Noise Floor Report*/ + tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD); + + /*update idle time pwer report per 5us*/ + odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0); + + ODM_delay_us(5); + + noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff); + noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8); + + for (i = RF_PATH_A; i < max_rf_path; i++) { + noise_data.sval[i] = (s8)noise_data.value[i]; + noise_data.sval[i] = noise_data.sval[i] >> 1; + } + + for (i = RF_PATH_A; i < max_rf_path; i++) { + if (noise_data.valid_cnt[i] >= VALID_CNT) + continue; + + noise_data.valid_cnt[i]++; + noise_data.sum[i] += noise_data.sval[i]; + PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n", + i, noise_data.sval[i]); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n", + noise_data.sum[i]); + if (noise_data.valid_cnt[i] == VALID_CNT) + valid_done++; + } + + if (valid_done == max_rf_path || + (odm_get_progressing_time(dm, start) > max_time)) { + phydm_set_noise_data_sum(&noise_data, max_rf_path); + break; + } + } + reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0); + reg_c50 &= ~BIT(7); + val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]); + dm->noise_level.noise[RF_PATH_A] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A]; + + if (max_rf_path == 2) { + reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0); + reg_e50 &= ~BIT(7); + val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]); + dm->noise_level.noise[RF_PATH_B] = val_s8; + dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B]; + } + dm->noise_level.noise_all /= max_rf_path; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "noise_a = %d, noise_b = %d, noise_all = %d\n", + dm->noise_level.noise[RF_PATH_A], + dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all); + + /*Step 3. Recover the Dig*/ + if (pause_dig) + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi); + func_end = odm_get_progressing_time(dm, func_start); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n"); + return dm->noise_level.noise_all; +} + +s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi, + u32 max_time) +{ + s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ + s32 value32, pwdb_A = 0, sval, noise, sum = 0; + boolean pd_flag; + u8 valid_cnt = 0; + u8 invalid_cnt = 0; + u64 start = 0, func_start = 0, func_end = 0, proc_time = 0; + s32 val_s32 = 0; + s16 rpt = 0; + u8 val_u8 = 0; + + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time); + return rpt; + } + + if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A))) + return 0; + + func_start = odm_get_current_time(dm); + dm->noise_level.noise_all = 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__); + + /* step 1. Disable DIG && Set initial gain. */ + if (pause_dig) + odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi); + + /* step 3. Get noise power level */ + start = odm_get_current_time(dm); + + /* step 3. Get noise power level */ + while (1) { + /*Set IGI=0x1C */ + odm_write_dig(dm, 0x1C); + /*stop CK320&CK88 */ + odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1); + /*Read path-A */ + /*set debug port*/ + odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200); + /*read debug port*/ + value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD); + /*rxi_buf_anta=RegFA0[19:10]*/ + rxi_buf_anta = (value32 & 0xFFC00) >> 10; + rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/ + + pd_flag = (boolean)((value32 & BIT(31)) >> 31); + + /*Not in packet detection period or Tx state */ + if (!pd_flag || rxi_buf_anta != 0x200) { + /*sign conversion*/ + rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10); + rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10); + + val_s32 = rxi_buf_anta * rxi_buf_anta + + rxq_buf_anta * rxq_buf_anta; + /*S(10,9)*S(10,9)=S(20,18)*/ + pwdb_A = odm_pwdb_conversion(val_s32, 20, 18); + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", + pwdb_A, rxi_buf_anta & 0x3FF, + rxq_buf_anta & 0x3FF); + } + /*Start CK320&CK88*/ + odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0); + /*@BB Reset*/ + val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0)); + odm_write_1byte(dm, 0x02, val_u8); + val_u8 = odm_read_1byte(dm, 0x02) | BIT(0); + odm_write_1byte(dm, 0x02, val_u8); + /*PMAC Reset*/ + val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0)); + odm_write_1byte(dm, 0xB03, val_u8); + val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0); + odm_write_1byte(dm, 0xB03, val_u8); + /*@CCK Reset*/ + if (odm_read_1byte(dm, 0x80B) & BIT(4)) { + val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4)); + odm_write_1byte(dm, 0x80B, val_u8); + val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4); + odm_write_1byte(dm, 0x80B, val_u8); + } + + sval = pwdb_A; + + if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) { + valid_cnt++; + sum += sval; + PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval); + PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum); + if (valid_cnt >= VALID_CNT || + (odm_get_progressing_time(dm, start) > max_time)) { + sum /= VALID_CNT; + PHYDM_DBG(dm, DBG_ENV_MNTR, + "After divided, sum = %d\n", sum); + break; + } + } else { + /*Invalid sval and return -110 dBm*/ + invalid_cnt++; + PHYDM_DBG(dm, DBG_ENV_MNTR, "Invalid sval\n"); + if (invalid_cnt >= VALID_CNT + 5) { + PHYDM_DBG(dm, DBG_ENV_MNTR, + "Invalid count > TH, Return -110, Break!!\n"); + return -110; + } + } + } + + /*@ADC backoff is 12dB,*/ + /*Ptarget=0x1C-110=-82dBm*/ + noise = sum + 12 + 0x1C - 110; + + /*Offset*/ + noise = noise - 3; + PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise); + dm->noise_level.noise_all = (s16)noise; + + /* step 4. Recover the Dig*/ + if (pause_dig) + odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi); + + func_end = odm_get_progressing_time(dm, func_start); + + PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__); + + return dm->noise_level.noise_all; +} +#endif + +s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi, + u32 max_time) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s16 val = 0; + + igi = 0x32; + + /* since HW ability is about +15~-35, + * we fix IGI = -60 for maximum coverage + */ + #if (ODM_IC_11AC_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11AC_SERIES) + val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time); + #endif + + #if (ODM_IC_11N_SERIES_SUPPORT) + if (dm->support_ic_type & ODM_IC_11N_SERIES) + val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time); + #endif + + return val; +} + +void phydm_noisy_detection(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 total_fa_cnt, total_cca_cnt; + u32 score = 0, i, score_smooth; + + total_cca_cnt = dm->false_alm_cnt.cnt_cca_all; + total_fa_cnt = dm->false_alm_cnt.cnt_all; + +#if 0 + if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* @87.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* @75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* @56.25 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* @50 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* @43.75 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* @37.5 */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* @31.25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* @25% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* @18.75% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* @12.5% */ + ; + else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* @6.25% */ + ; +#endif + for (i = 0; i <= 16; i++) { + if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) { + score = 16 - i; + break; + } + } + + /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */ + dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) + + (score << 2); + + /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */ + if (total_cca_cnt >= 300) + score_smooth = (dm->noisy_decision_smooth + 3) >> 3; + else + score_smooth = 0; + + dm->noisy_decision = (score_smooth >= 3) ? 1 : 0; + + PHYDM_DBG(dm, DBG_ENV_MNTR, + "[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n", + total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score, + score_smooth, dm->noisy_decision); +} diff --git a/hal/phydm/phydm_noisemonitor.h b/hal/phydm/phydm_noisemonitor.h new file mode 100644 index 0000000..507285a --- /dev/null +++ b/hal/phydm/phydm_noisemonitor.h @@ -0,0 +1,48 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __ODMNOISEMONITOR_H__ +#define __ODMNOISEMONITOR_H__ + +#define VALID_CNT 5 + +struct noise_level { + u8 value[PHYDM_MAX_RF_PATH]; + s8 sval[PHYDM_MAX_RF_PATH]; + s32 sum[PHYDM_MAX_RF_PATH]; + u8 valid[PHYDM_MAX_RF_PATH]; + u8 valid_cnt[PHYDM_MAX_RF_PATH]; +}; + +struct odm_noise_monitor { + s8 noise[PHYDM_MAX_RF_PATH]; + s16 noise_all; +}; + +s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value, + u32 max_time); + +void phydm_noisy_detection(void *dm_void); + +#endif diff --git a/hal/phydm/phydm_pathdiv.c b/hal/phydm/phydm_pathdiv.c new file mode 100644 index 0000000..a6b347c --- /dev/null +++ b/hal/phydm/phydm_pathdiv.c @@ -0,0 +1,1113 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CONFIG_PATH_DIVERSITY +#if RTL8814A_SUPPORT +void phydm_dtp_fix_tx_path( + void *dm_void, + u8 path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u8 i, num_enable_path = 0; + + if (path == p_div->pre_tx_path) + return; + else + p_div->pre_tx_path = path; + + odm_set_bb_reg(dm, R_0x93c, BIT(18) | BIT(19), 3); + + for (i = 0; i < 4; i++) { + if (path & BIT(i)) + num_enable_path++; + } + PHYDM_DBG(dm, DBG_PATH_DIV, " number of turn-on path : (( %d ))\n", + num_enable_path); + + if (num_enable_path == 1) { + odm_set_bb_reg(dm, R_0x93c, 0xf00000, path); + + if (path == BB_PATH_A) { /* @1-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( A ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + } else if (path == BB_PATH_B) { /* @1-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( B ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + } else if (path == BB_PATH_C) { /* @1-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( C ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0); + + } else if (path == BB_PATH_D) { /* @1-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path (( D ))\n"); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 0); + } + + } else if (num_enable_path == 2) { + odm_set_bb_reg(dm, R_0x93c, 0xf00000, path); + odm_set_bb_reg(dm, R_0x940, 0xf0, path); + + if (path == (BB_PATH_AB)) { /* @2-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A B ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1); + } else if (path == BB_PATH_AC) { /* @2-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A C ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + } else if (path == BB_PATH_AD) { /* @2-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A D ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1); + } else if (path == BB_PATH_BC) { /* @2-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( B C ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + } else if (path == BB_PATH_BD) { /* @2-5 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( B D ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1); + } else if (path == BB_PATH_CD) { /* @2-6 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( C D ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 1); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 0); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 1); + } + + } else if (num_enable_path == 3) { + odm_set_bb_reg(dm, R_0x93c, 0xf00000, path); + odm_set_bb_reg(dm, R_0x940, 0xf0, path); + odm_set_bb_reg(dm, R_0x940, 0xf0000, path); + + if (path == BB_PATH_ABC) { /* @3-1 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A B C))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 2); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 2); + /* set for 3ss */ + odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 2); + } else if (path == BB_PATH_ABD) { /* @3-2 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A B D ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 1); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2); + /* set for 3ss */ + odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 1); + odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2); + + } else if (path == BB_PATH_ACD) { /* @3-3 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( A C D ))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(25) | BIT(24), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(9) | BIT(8), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2); + /* set for 3ss */ + odm_set_bb_reg(dm, R_0x940, BIT(21) | BIT(20), 0); + odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2); + } else if (path == BB_PATH_BCD) { /* @3-4 */ + PHYDM_DBG(dm, DBG_PATH_DIV, + " Turn on path (( B C D))\n"); + /* set for 1ss */ + odm_set_bb_reg(dm, R_0x93c, BIT(27) | BIT(26), 0); + odm_set_bb_reg(dm, R_0x93c, BIT(29) | BIT(28), 1); + odm_set_bb_reg(dm, R_0x93c, BIT(31) | BIT(30), 2); + /* set for 2ss */ + odm_set_bb_reg(dm, R_0x940, BIT(11) | BIT(10), 0); + odm_set_bb_reg(dm, R_0x940, BIT(13) | BIT(12), 1); + odm_set_bb_reg(dm, R_0x940, BIT(15) | BIT(14), 2); + /* set for 3ss */ + odm_set_bb_reg(dm, R_0x940, BIT(23) | BIT(22), 0); + odm_set_bb_reg(dm, R_0x940, BIT(25) | BIT(24), 1); + odm_set_bb_reg(dm, R_0x940, BIT(27) | BIT(26), 2); + } + } else if (num_enable_path == 4) + PHYDM_DBG(dm, DBG_PATH_DIV, " Turn on path ((A B C D))\n"); +} + +void phydm_find_default_path( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u32 rssi_a = 0, rssi_b = 0, rssi_c = 0, rssi_d = 0, rssi_bcd = 0; + u32 rssi_total_a = 0, rssi_total_b = 0; + u32 rssi_total_c = 0, rssi_total_d = 0; + + /* @2 Default path Selection By RSSI */ + + rssi_a = (p_div->path_a_cnt_all > 0) ? + (p_div->path_a_sum_all / p_div->path_a_cnt_all) : 0; + rssi_b = (p_div->path_b_cnt_all > 0) ? + (p_div->path_b_sum_all / p_div->path_b_cnt_all) : 0; + rssi_c = (p_div->path_c_cnt_all > 0) ? + (p_div->path_c_sum_all / p_div->path_c_cnt_all) : 0; + rssi_d = (p_div->path_d_cnt_all > 0) ? + (p_div->path_d_sum_all / p_div->path_d_cnt_all) : 0; + + p_div->path_a_sum_all = 0; + p_div->path_a_cnt_all = 0; + p_div->path_b_sum_all = 0; + p_div->path_b_cnt_all = 0; + p_div->path_c_sum_all = 0; + p_div->path_c_cnt_all = 0; + p_div->path_d_sum_all = 0; + p_div->path_d_cnt_all = 0; + + if (p_div->use_path_a_as_default_ant == 1) { + rssi_bcd = (rssi_b + rssi_c + rssi_d) / 3; + + if ((rssi_a + ANT_DECT_RSSI_TH) > rssi_bcd) { + p_div->is_path_a_exist = true; + p_div->default_path = PATH_A; + } else { + p_div->is_path_a_exist = false; + } + } else { + if (rssi_a >= rssi_b && + rssi_a >= rssi_c && + rssi_a >= rssi_d) + p_div->default_path = PATH_A; + else if ((rssi_b >= rssi_c) && (rssi_b >= rssi_d)) + p_div->default_path = PATH_B; + else if (rssi_c >= rssi_d) + p_div->default_path = PATH_C; + else + p_div->default_path = PATH_D; + } +} + +void phydm_candidate_dtp_update( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + p_div->num_candidate = 3; + + if (p_div->use_path_a_as_default_ant == 1) { + if (p_div->num_tx_path == 3) { + if (p_div->is_path_a_exist) { + p_div->ant_candidate_1 = BB_PATH_ABC; + p_div->ant_candidate_2 = BB_PATH_ABD; + p_div->ant_candidate_3 = BB_PATH_ACD; + } else { /* use path BCD */ + p_div->num_candidate = 1; + phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); + return; + } + } else if (p_div->num_tx_path == 2) { + if (p_div->is_path_a_exist) { + p_div->ant_candidate_1 = BB_PATH_AB; + p_div->ant_candidate_2 = BB_PATH_AC; + p_div->ant_candidate_3 = BB_PATH_AD; + } else { + p_div->ant_candidate_1 = BB_PATH_BC; + p_div->ant_candidate_2 = BB_PATH_BD; + p_div->ant_candidate_3 = BB_PATH_CD; + } + } + } else { + /* @2 3 TX mode */ + if (p_div->num_tx_path == 3) { /* @choose 3 ant form 4 */ + if (p_div->default_path == PATH_A) { + /* @choose 2 ant form 3 */ + p_div->ant_candidate_1 = BB_PATH_ABC; + p_div->ant_candidate_2 = BB_PATH_ABD; + p_div->ant_candidate_3 = BB_PATH_ACD; + } else if (p_div->default_path == PATH_B) { + p_div->ant_candidate_1 = BB_PATH_ABC; + p_div->ant_candidate_2 = BB_PATH_ABD; + p_div->ant_candidate_3 = BB_PATH_BCD; + } else if (p_div->default_path == PATH_C) { + p_div->ant_candidate_1 = BB_PATH_ABC; + p_div->ant_candidate_2 = BB_PATH_ACD; + p_div->ant_candidate_3 = BB_PATH_BCD; + } else if (p_div->default_path == PATH_D) { + p_div->ant_candidate_1 = BB_PATH_ABD; + p_div->ant_candidate_2 = BB_PATH_ACD; + p_div->ant_candidate_3 = BB_PATH_BCD; + } + } + + /* @2 2 TX mode */ + else if (p_div->num_tx_path == 2) { /* @choose 2 ant form 4 */ + if (p_div->default_path == PATH_A) { + /* @choose 2 ant form 3 */ + p_div->ant_candidate_1 = BB_PATH_AB; + p_div->ant_candidate_2 = BB_PATH_AC; + p_div->ant_candidate_3 = BB_PATH_AD; + } else if (p_div->default_path == PATH_B) { + p_div->ant_candidate_1 = BB_PATH_AB; + p_div->ant_candidate_2 = BB_PATH_BC; + p_div->ant_candidate_3 = BB_PATH_BD; + } else if (p_div->default_path == PATH_C) { + p_div->ant_candidate_1 = BB_PATH_AC; + p_div->ant_candidate_2 = BB_PATH_BC; + p_div->ant_candidate_3 = BB_PATH_CD; + } else if (p_div->default_path == PATH_D) { + p_div->ant_candidate_1 = BB_PATH_AD; + p_div->ant_candidate_2 = BB_PATH_BD; + p_div->ant_candidate_3 = BB_PATH_CD; + } + } + } +} + +void phydm_dynamic_tx_path( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + struct sta_info *entry; + u32 i; + u8 num_client = 0; + u8 h2c_parameter[6] = {0}; + + if (!dm->is_linked) { /* @is_linked==False */ + PHYDM_DBG(dm, DBG_PATH_DIV, "DTP_8814 [No Link!!!]\n"); + + if (p_div->is_become_linked) { + PHYDM_DBG(dm, DBG_PATH_DIV, "[Be disconnected]---->\n"); + p_div->is_become_linked = dm->is_linked; + } + return; + } else { + if (!p_div->is_become_linked) { + PHYDM_DBG(dm, DBG_PATH_DIV, " [Be Linked !!!]----->\n"); + p_div->is_become_linked = dm->is_linked; + } + } + + /* @2 [period CTRL] */ + if (p_div->dtp_period >= 2) { + p_div->dtp_period = 0; + } else { + p_div->dtp_period++; + return; + } + + /* @2 [Fix path] */ + if (dm->path_select != PHYDM_AUTO_PATH) + return; + +/* @2 [Check Bfer] */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#ifdef PHYDM_BEAMFORMING_SUPPORT + { + enum beamforming_cap beamform_cap = (dm->beamforming_info.beamform_cap); + + if (beamform_cap & BEAMFORMER_CAP) { /* @BFmer On && Div On->Div Off */ + if (p_div->fix_path_bfer == 0) { + PHYDM_DBG(dm, DBG_PATH_DIV, + "[ PathDiv : OFF ] BFmer ==1\n"); + p_div->fix_path_bfer = 1; + } + return; + } else { /* @BFmer Off && Div Off->Div On */ + if (p_div->fix_path_bfer == 1) { + PHYDM_DBG(dm, DBG_PATH_DIV, + "[ PathDiv : ON ] BFmer ==0\n"); + p_div->fix_path_bfer = 0; + } + } + } +#endif +#endif + + if (p_div->use_path_a_as_default_ant == 1) { + phydm_find_default_path(dm); + phydm_candidate_dtp_update(dm); + } else { + if (p_div->phydm_dtp_state == PHYDM_DTP_INIT) { + phydm_find_default_path(dm); + phydm_candidate_dtp_update(dm); + p_div->phydm_dtp_state = PHYDM_DTP_RUNNING_1; + } + + else if (p_div->phydm_dtp_state == PHYDM_DTP_RUNNING_1) { + p_div->dtp_check_patha_counter++; + + if (p_div->dtp_check_patha_counter >= + NUM_RESET_DTP_PERIOD) { + p_div->dtp_check_patha_counter = 0; + p_div->phydm_dtp_state = PHYDM_DTP_INIT; + } +#if 0 + /* @2 Search space update */ + else { + /* @1. find the worst candidate */ + + + /* @2. repalce the worst candidate */ + } +#endif + } + } + + /* @2 Dynamic path Selection H2C */ + + if (p_div->num_candidate == 1) { + return; + } else { + h2c_parameter[0] = p_div->num_candidate; + h2c_parameter[1] = p_div->num_tx_path; + h2c_parameter[2] = p_div->ant_candidate_1; + h2c_parameter[3] = p_div->ant_candidate_2; + h2c_parameter[4] = p_div->ant_candidate_3; + + odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, h2c_parameter); + } +} + +void phydm_dynamic_tx_path_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + void *adapter = dm->adapter; + u8 search_space_2[NUM_CHOOSE2_FROM4] = {BB_PATH_AB, BB_PATH_AC, BB_PATH_AD, BB_PATH_BC, BB_PATH_BD, BB_PATH_CD}; + u8 search_space_3[NUM_CHOOSE3_FROM4] = {BB_PATH_BCD, BB_PATH_ACD, BB_PATH_ABD, BB_PATH_ABC}; + +#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) && USB_SWITCH_SUPPORT) + p_div->is_u3_mode = (*dm->hub_usb_mode == 2) ? 1 : 0; + PHYDM_DBG(dm, DBG_PATH_DIV, "[WIN USB] is_u3_mode = (( %d ))\n", + p_div->is_u3_mode); +#else + p_div->is_u3_mode = 1; +#endif + PHYDM_DBG(dm, DBG_PATH_DIV, "Dynamic TX path Init 8814\n"); + + memcpy(&p_div->search_space_2[0], &search_space_2[0], + NUM_CHOOSE2_FROM4); + memcpy(&p_div->search_space_3[0], &search_space_3[0], + NUM_CHOOSE3_FROM4); + + p_div->use_path_a_as_default_ant = 1; + p_div->phydm_dtp_state = PHYDM_DTP_INIT; + dm->path_select = PHYDM_AUTO_PATH; + p_div->phydm_path_div_type = PHYDM_4R_PATH_DIV; + + if (p_div->is_u3_mode) { + p_div->num_tx_path = 3; + phydm_dtp_fix_tx_path(dm, BB_PATH_BCD); /* @3TX Set Init TX path*/ + + } else { + p_div->num_tx_path = 2; + phydm_dtp_fix_tx_path(dm, BB_PATH_BC); /* @2TX // Set Init TX path*/ + } +} + +void phydm_process_rssi_for_path_div_8814a(void *dm_void, void *phy_info_void, + void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = NULL; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + + if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid)) + return; + + if (pktinfo->data_rate <= ODM_RATE11M) + return; + + if (p_div->phydm_path_div_type == PHYDM_4R_PATH_DIV) { + p_div->path_a_sum_all += phy_info->rx_mimo_signal_strength[0]; + p_div->path_a_cnt_all++; + + p_div->path_b_sum_all += phy_info->rx_mimo_signal_strength[1]; + p_div->path_b_cnt_all++; + + p_div->path_c_sum_all += phy_info->rx_mimo_signal_strength[2]; + p_div->path_c_cnt_all++; + + p_div->path_d_sum_all += phy_info->rx_mimo_signal_strength[3]; + p_div->path_d_cnt_all++; + } +} + +void phydm_pathdiv_debug_8814a(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + u8 i, input_idx = 0; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + dm->path_select = (u8)(dm_value[0] & 0xf); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Path_select = (( 0x%x ))\n", dm->path_select); + + /* @2 [Fix path] */ + if (dm->path_select != PHYDM_AUTO_PATH) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Turn on path [%s%s%s%s]\n", + ((dm->path_select) & 0x1) ? "A" : "", + ((dm->path_select) & 0x2) ? "B" : "", + ((dm->path_select) & 0x4) ? "C" : "", + ((dm->path_select) & 0x8) ? "D" : ""); + + phydm_dtp_fix_tx_path(dm, dm->path_select); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, "%s\n", + "Auto path"); + } + + *_used = used; + *_out_len = out_len; +} + +#endif /* @#if RTL8814A_SUPPORT */ + +#if RTL8812A_SUPPORT +void phydm_update_tx_path_8812a(void *dm_void, enum bb_path path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + if (p_div->default_tx_path != path) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Need to Update Tx path\n"); + + if (path == BB_PATH_A) { + /*Tx by Reg*/ + odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111); + /*Resp Tx by Txinfo*/ + odm_set_bb_reg(dm, R_0x6d8, 0xc0, 1); + } else { + /*Tx by Reg*/ + odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x222); + /*Resp Tx by Txinfo*/ + odm_set_bb_reg(dm, R_0x6d8, 0xc0, 2); + } + } + p_div->default_tx_path = path; + + PHYDM_DBG(dm, DBG_PATH_DIV, "path=%s\n", + (path == BB_PATH_A) ? "A" : "B"); +} + +void phydm_path_diversity_init_8812a(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u32 i; + + odm_set_bb_reg(dm, R_0x80c, BIT(29), 1); /* Tx path from Reg */ + odm_set_bb_reg(dm, R_0x80c, 0xFFF0, 0x111); /* Tx by Reg */ + odm_set_bb_reg(dm, R_0x6d8, BIT(7) | BIT6, 1); /* Resp Tx by Txinfo */ + phydm_set_tx_path_by_bb_reg(dm, RF_PATH_A); + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + p_div->path_sel[i] = 1; /* TxInfo default at path-A */ +} +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_set_resp_tx_path_by_fw_jgr3(void *dm_void, u8 macid, + enum bb_path path, boolean enable) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u8 h2c_para[7] = {0}; + u8 path_map[4] = {0}; /* tx logic map*/ + u8 num_enable_path = 0; + u8 n_tx_path_ctrl_map = 0; + u8 i = 0, n_sts = 0; + + /*Response TX is controlled in FW ctrl info*/ + + PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] =====>\n", __func__); + + if (enable) { + n_tx_path_ctrl_map = path; + + for (i = 0; i < 4; i++) { + path_map[i] = 0; + if (path & BIT(i)) + num_enable_path++; + } + + for (i = 0; i < 4; i++) { + if (path & BIT(i)) { + path_map[i] = n_sts; + n_sts++; + + if (n_sts == num_enable_path) + break; + } + } + } + + PHYDM_DBG(dm, DBG_PATH_DIV, "ctrl_map=0x%x Map[D:A]={%d, %d, %d, %d}\n", + n_tx_path_ctrl_map, + path_map[3], path_map[2], path_map[1], path_map[0]); + + h2c_para[0] = macid; + h2c_para[1] = n_tx_path_ctrl_map; + h2c_para[2] = (path_map[3] << 6) | (path_map[2] << 4) | + (path_map[1] << 2) | path_map[0]; + + odm_fill_h2c_cmd(dm, PHYDM_H2C_DYNAMIC_TX_PATH, 7, h2c_para); +} + +void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid, + struct path_txdesc_ctrl *desc) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u8 ant_map_a = 0, ant_map_b = 0; + u8 ntx_map = 0; + + if (p_div->path_sel[macid] == BB_PATH_A) { + desc->ant_map_a = 0; /*offest24[23:22]*/ + desc->ant_map_b = 0; /*offest24[25:24]*/ + desc->ntx_map = BB_PATH_A; /*offest28[23:20]*/ + } else if (p_div->path_sel[macid] == BB_PATH_B) { + desc->ant_map_a = 0; /*offest24[23:22]*/ + desc->ant_map_b = 0; /*offest24[25:24]*/ + desc->ntx_map = BB_PATH_B; /*offest28[23:20]*/ + } else { + desc->ant_map_a = 0; /*offest24[23:22]*/ + desc->ant_map_b = 1; /*offest24[25:24]*/ + desc->ntx_map = BB_PATH_AB; /*offest28[23:20]*/ + } +} +#endif + +void phydm_tx_path_by_mac_or_reg(void *dm_void, enum phydm_path_ctrl ctrl) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ctrl=%s\n", + __func__, (ctrl == TX_PATH_BY_REG) ? "REG" : "DESC"); + + if (ctrl == p_div->tx_path_ctrl) + return; + + p_div->tx_path_ctrl = ctrl; + + switch (dm->support_ic_type) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + case ODM_RTL8822B: + case ODM_RTL8822C: + case ODM_RTL8812F: + case ODM_RTL8197G: + if (ctrl == TX_PATH_BY_REG) { + odm_set_bb_reg(dm, R_0x1e24, BIT(16), 0); /*OFDM*/ + odm_set_bb_reg(dm, R_0x1a84, 0xe0, 0); /*CCK*/ + } else { + odm_set_bb_reg(dm, R_0x1e24, BIT(16), 1); /*OFDM*/ + odm_set_bb_reg(dm, R_0x1a84, 0xe0, 7); /*CCK*/ + } + + break; + #endif + #if 0 /*(RTL8822B_SUPPORT)*/ /*@ HW Bug*/ + case ODM_RTL8822B: + if (ctrl == TX_PATH_BY_REG) { + odm_set_bb_reg(dm, R_0x93c, BIT(18), 0); + odm_set_bb_reg(dm, R_0xa84, 0xe0, 0); /*CCK*/ + } else { + odm_set_bb_reg(dm, R_0x93c, BIT(18), 1); + odm_set_bb_reg(dm, R_0xa84, 0xe0, 7); /*CCK*/ + } + + break; + #endif + default: + break; + } +} + +void phydm_fix_1ss_tx_path_by_bb_reg(void *dm_void, + enum bb_path tx_path_sel_1ss, + enum bb_path tx_path_sel_cck) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + if (tx_path_sel_1ss != BB_PATH_AUTO) { + p_div->ofdm_fix_path_en = true; + p_div->ofdm_fix_path_sel = tx_path_sel_1ss; + } else { + p_div->ofdm_fix_path_en = false; + p_div->ofdm_fix_path_sel = dm->tx_1ss_status; + } + + if (tx_path_sel_cck != BB_PATH_AUTO) { + p_div->cck_fix_path_en = true; + p_div->cck_fix_path_sel = tx_path_sel_cck; + } else { + p_div->cck_fix_path_en = false; + p_div->cck_fix_path_sel = dm->tx_1ss_status; + } + + p_div->force_update = true; + + PHYDM_DBG(dm, DBG_PATH_DIV, + "{OFDM_fix_en=%d, path=%d} {CCK_fix_en=%d, path=%d}\n", + p_div->ofdm_fix_path_en, p_div->ofdm_fix_path_sel, + p_div->cck_fix_path_en, p_div->cck_fix_path_sel); +} + +void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + enum bb_path tx_path_sel_cck = tx_path_sel_1ss; + + if (!p_div->force_update) { + if (tx_path_sel_1ss == p_div->default_tx_path) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Stay in TX path=%s\n", + (tx_path_sel_1ss == BB_PATH_A) ? "A" : "B"); + return; + } + } + p_div->force_update = false; + + p_div->default_tx_path = tx_path_sel_1ss; + + PHYDM_DBG(dm, DBG_PATH_DIV, "Switch TX path=%s\n", + (tx_path_sel_1ss == BB_PATH_A) ? "A" : "B"); + + /*Adv-ctrl mode*/ + if (p_div->cck_fix_path_en) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Fix CCK TX path=%d\n", + p_div->cck_fix_path_sel); + tx_path_sel_cck = p_div->cck_fix_path_sel; + } + + if (p_div->ofdm_fix_path_en) { + PHYDM_DBG(dm, DBG_PATH_DIV, "Fix OFDM TX path=%d\n", + p_div->ofdm_fix_path_sel); + tx_path_sel_1ss = p_div->ofdm_fix_path_sel; + } + + switch (dm->support_ic_type) { + #if RTL8822C_SUPPORT + case ODM_RTL8822C: + phydm_config_tx_path_8822c(dm, dm->tx_2ss_status, + tx_path_sel_1ss, tx_path_sel_cck); + break; + #endif + + #if RTL8822B_SUPPORT + case ODM_RTL8822B: + if (dm->tx_ant_status != BB_PATH_AB) + return; + + phydm_config_tx_path_8822b(dm, BB_PATH_AB, + tx_path_sel_1ss, tx_path_sel_cck); + break; + #endif + + #if RTL8192F_SUPPORT + case ODM_RTL8192F: + if (dm->tx_ant_status != BB_PATH_AB) + return; + + phydm_config_tx_path_8192f(dm, BB_PATH_AB, + tx_path_sel_1ss, tx_path_sel_cck); + break; + #endif + + #if RTL8812A_SUPPORT + case ODM_RTL8812: + phydm_update_tx_path_8812a(dm, tx_path_sel_1ss); + break; + #endif + default: + break; + } +} + +void phydm_tx_path_diversity_2ss(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + struct cmn_sta_info *sta; + enum bb_path default_tx_path = BB_PATH_A, path = BB_PATH_A; + u32 rssi_a = 0, rssi_b = 0; + u32 local_max_rssi, glb_min_rssi = 0xff; + u8 i = 0; + + PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] =======>\n", __func__); + + if (!dm->is_linked) { + if (dm->first_disconnect) + phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG); + + PHYDM_DBG(dm, DBG_PATH_DIV, "No Link\n"); + return; + } + + #if 0/*def PHYDM_IC_JGR3_SERIES_SUPPORT*/ + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + if (dm->is_one_entry_only || p_div->cck_fix_path_en || + p_div->ofdm_fix_path_en) + phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG); + else + phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_DESC); + } + #endif + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (!is_sta_active(sta)) + continue; + + /* 2 Caculate RSSI per path */ + rssi_a = PHYDM_DIV(p_div->path_a_sum[i], p_div->path_a_cnt[i]); + rssi_b = PHYDM_DIV(p_div->path_b_sum[i], p_div->path_b_cnt[i]); + + if (rssi_a == rssi_b) + path = p_div->default_tx_path; + else + path = (rssi_a > rssi_b) ? BB_PATH_A : BB_PATH_B; + + local_max_rssi = (rssi_a > rssi_b) ? rssi_a : rssi_b; + + PHYDM_DBG(dm, DBG_PATH_DIV, + "[%d]PathA sum=%d, cnt=%d, avg_rssi=%d\n", + i, p_div->path_a_sum[i], + p_div->path_a_cnt[i], rssi_a); + PHYDM_DBG(dm, DBG_PATH_DIV, + "[%d]PathB sum=%d, cnt=%d, avg_rssi=%d\n", + i, p_div->path_b_sum[i], + p_div->path_b_cnt[i], rssi_b); + + /*Select default Tx path */ + if (local_max_rssi < glb_min_rssi) { + glb_min_rssi = local_max_rssi; + default_tx_path = path; + } + + if (p_div->path_sel[i] != path) { + p_div->path_sel[i] = path; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_set_resp_tx_path_by_fw_jgr3(dm, i, + path, true); + #endif + } + + p_div->path_a_cnt[i] = 0; + p_div->path_a_sum[i] = 0; + p_div->path_b_cnt[i] = 0; + p_div->path_b_sum[i] = 0; + } + + /* 2 Update default Tx path */ + phydm_set_tx_path_by_bb_reg(dm, default_tx_path); + PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] end\n\n", __func__); +} + +void phydm_tx_path_diversity(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + p_div->path_div_in_progress = false; + + if (!(dm->support_ability & ODM_BB_PATH_DIV)) + return; + + if (p_div->stop_path_div) { + PHYDM_DBG(dm, DBG_PATH_DIV, + "stop_path_div=1, tx_1ss_status=%d\n", + dm->tx_1ss_status); + return; + } + + switch (dm->support_ic_type) { + #ifdef PHYDM_CONFIG_PATH_DIV_V2 + case ODM_RTL8822B: + case ODM_RTL8822C: + case ODM_RTL8192F: + case ODM_RTL8812F: + case ODM_RTL8197G: + if (dm->rx_ant_status != BB_PATH_AB) { + PHYDM_DBG(dm, DBG_PATH_DIV, + "[Return] tx_Path_en=%d, rx_Path_en=%d\n", + dm->tx_ant_status, dm->rx_ant_status); + return; + } + + p_div->path_div_in_progress = true; + phydm_tx_path_diversity_2ss(dm); + break; + #endif + + #if (RTL8812A_SUPPORT) + case ODM_RTL8812: + phydm_tx_path_diversity_2ss(dm); + break; + #endif + + #if RTL8814A_SUPPORT + case ODM_RTL8814A: + phydm_dynamic_tx_path(dm); + break; + #endif + } +} + +void phydm_tx_path_diversity_init_v2(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u32 i = 0; + + PHYDM_DBG(dm, DBG_PATH_DIV, "[%s] ====>\n", __func__); + + /*BB_PATH_AB is a invalid value used for init state*/ + p_div->default_tx_path = BB_PATH_A; + p_div->tx_path_ctrl = TX_PATH_CTRL_INIT; + p_div->path_div_in_progress = false; + + p_div->cck_fix_path_en = false; + p_div->ofdm_fix_path_en = false; + p_div->force_update = false; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + p_div->path_sel[i] = BB_PATH_A; /* TxInfo default at path-A */ + + phydm_tx_path_by_mac_or_reg(dm, TX_PATH_BY_REG); +} + +void phydm_tx_path_diversity_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_PATH_DIV)) + return; + + switch (dm->support_ic_type) { + #ifdef PHYDM_CONFIG_PATH_DIV_V2 + case ODM_RTL8822C: + case ODM_RTL8822B: + case ODM_RTL8192F: + case ODM_RTL8812F: + case ODM_RTL8197G: + phydm_tx_path_diversity_init_v2(dm); /*@ After 8822B*/ + break; + #endif + + #if RTL8812A_SUPPORT + case ODM_RTL8812: + phydm_path_diversity_init_8812a(dm); + break; + #endif + + #if RTL8814A_SUPPORT + case ODM_RTL8814A: + phydm_dynamic_tx_path_init(dm); + break; + #endif + } +} + +void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void, + void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = NULL; + struct phydm_perpkt_info_struct *pktinfo = NULL; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + u8 id = 0; + + phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + + if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid)) + return; + + if (pktinfo->is_cck_rate) + return; + + id = pktinfo->station_id; + p_div->path_a_sum[id] += phy_info->rx_mimo_signal_strength[0]; + p_div->path_a_cnt[id]++; + + p_div->path_b_sum[id] += phy_info->rx_mimo_signal_strength[1]; + p_div->path_b_cnt[id]++; +} + +void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + char help[] = "-h"; + u32 used = *_used; + u32 out_len = *_out_len; + u32 val[10] = {0}; + u8 i, input_idx = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &val[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + PHYDM_SSCANF(input[1], DCMD_HEX, &val[0]); + PHYDM_SSCANF(input[2], DCMD_HEX, &val[1]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1:TX Ctrl Sig} {0:BB, 1:MAC}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2:BB Default TX REG} {path}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3:MAC DESC TX} {path} {macid}\n"); + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4:MAC Resp TX} {path} {macid}\n"); + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "{5:Fix 1ss path} {ofdm path} {cck path}\n"); + } else if (val[0] == 1) { + phydm_tx_path_by_mac_or_reg(dm, (enum phydm_path_ctrl)val[1]); + } else if (val[0] == 2) { + phydm_set_tx_path_by_bb_reg(dm, (enum bb_path)val[1]); + } else if (val[0] == 3) { + p_div->path_sel[val[2]] = (enum bb_path)val[1]; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + } else if (val[0] == 4) { + phydm_set_resp_tx_path_by_fw_jgr3(dm, (u8)val[2], + (enum bb_path)val[1], true); + #endif + } else if (val[0] == 5) { + phydm_fix_1ss_tx_path_by_bb_reg(dm, (enum bb_path)val[1], + (enum bb_path)val[2]); + } + *_used = used; + *_out_len = out_len; +} + +void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct _ODM_PATH_DIVERSITY_ *p_div = &dm->dm_path_div; + + u8 macid = cmd_buf[0]; + u8 target = cmd_buf[1]; + u8 nsc_1 = cmd_buf[2]; + u8 nsc_2 = cmd_buf[3]; + u8 nsc_3 = cmd_buf[4]; + + PHYDM_DBG(dm, DBG_PATH_DIV, "Target_candidate = (( %d ))\n", target); +/*@ + if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3)) + { + phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_1); + } + else if( nsc_2 >= nsc_3) + { + phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_2); + } + else + { + phydm_dtp_fix_tx_path(dm, p_div->ant_candidate_3); + } + */ +} + +#endif /* @#ifdef CONFIG_PATH_DIVERSITY */ diff --git a/hal/phydm/phydm_pathdiv.h b/hal/phydm/phydm_pathdiv.h new file mode 100644 index 0000000..ee34382 --- /dev/null +++ b/hal/phydm/phydm_pathdiv.h @@ -0,0 +1,145 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMPATHDIV_H__ +#define __PHYDMPATHDIV_H__ + +#ifdef CONFIG_PATH_DIVERSITY +/* @2019.03.07 open resp tx path h2c only for 1ss status*/ +#define PATHDIV_VERSION "4.4" + +#if (RTL8192F_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8197G_SUPPORT) + #define PHYDM_CONFIG_PATH_DIV_V2 +#endif + +#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */ + +#define NUM_RESET_DTP_PERIOD 5 +#define ANT_DECT_RSSI_TH 3 + +#define PATH_A 1 +#define PATH_B 2 +#define PATH_C 3 +#define PATH_D 4 + +#define PHYDM_AUTO_PATH 0 +#define PHYDM_FIX_PATH 1 + +#define NUM_CHOOSE2_FROM4 6 +#define NUM_CHOOSE3_FROM4 4 + +enum phydm_dtp_state { + PHYDM_DTP_INIT = 1, + PHYDM_DTP_RUNNING_1 +}; + +enum phydm_path_div_type { + PHYDM_2R_PATH_DIV = 1, + PHYDM_4R_PATH_DIV = 2 +}; + +enum phydm_path_ctrl { + TX_PATH_BY_REG = 0, + TX_PATH_BY_DESC = 1, + TX_PATH_CTRL_INIT +}; + +struct path_txdesc_ctrl { + u8 ant_map_a : 2; + u8 ant_map_b : 2; + u8 ntx_map : 4; +}; + +struct _ODM_PATH_DIVERSITY_ { + boolean stop_path_div; /*@Limit by enabled path number*/ + boolean path_div_in_progress; + boolean cck_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/ + boolean ofdm_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/ + enum bb_path cck_fix_path_sel; /*@ BB Reg for Adv-Ctrl (or debug mode)*/ + enum bb_path ofdm_fix_path_sel;/*@ BB Reg for Adv-Ctrl (or debug mode)*/ + enum phydm_path_ctrl tx_path_ctrl; + enum bb_path default_tx_path; + enum bb_path path_sel[ODM_ASSOCIATE_ENTRY_NUM]; + u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u32 path_b_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u8 phydm_path_div_type; + boolean force_update; +#if RTL8814A_SUPPORT + + u32 path_a_sum_all; + u32 path_b_sum_all; + u32 path_c_sum_all; + u32 path_d_sum_all; + + u32 path_a_cnt_all; + u32 path_b_cnt_all; + u32 path_c_cnt_all; + u32 path_d_cnt_all; + + u8 dtp_period; + boolean is_become_linked; + boolean is_u3_mode; + u8 num_tx_path; + u8 default_path; + u8 num_candidate; + u8 ant_candidate_1; + u8 ant_candidate_2; + u8 ant_candidate_3; + u8 phydm_dtp_state; + u8 dtp_check_patha_counter; + boolean fix_path_bfer; + u8 search_space_2[NUM_CHOOSE2_FROM4]; + u8 search_space_3[NUM_CHOOSE3_FROM4]; + + u8 pre_tx_path; + u8 use_path_a_as_default_ant; + boolean is_path_a_exist; + +#endif +}; + +void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss); + +void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid, + struct path_txdesc_ctrl *desc); + +void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +void phydm_tx_path_diversity_init(void *dm_void); + +void phydm_tx_path_diversity(void *dm_void); + +void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void, + void *pkt_info_void); + +void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +#endif /* @#ifdef CONFIG_PATH_DIVERSITY */ +#endif /* @#ifndef __PHYDMPATHDIV_H__ */ + diff --git a/hal/phydm/phydm_phystatus.c b/hal/phydm/phydm_phystatus.c new file mode 100644 index 0000000..7d7ecd7 --- /dev/null +++ b/hal/phydm/phydm_phystatus.c @@ -0,0 +1,3245 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_COMPILE_MU +u8 phydm_get_gid(struct dm_struct *dm, u8 *phy_status_inf) +{ +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) + struct phy_sts_rpt_jgr2_type1 *rpt_jgr2 = NULL; +#endif +#ifdef PHYSTS_3RD_TYPE_SUPPORT + struct phy_sts_rpt_jgr3_type1 *rpt_jgr3 = NULL; +#endif + u8 gid = 0; + + if (dm->ic_phy_sts_type == PHYDM_PHYSTS_TYPE_1) + return 0; + + if ((*phy_status_inf & 0xf) != 1) + return 0; + + switch (dm->ic_phy_sts_type) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) + case PHYDM_PHYSTS_TYPE_2: + rpt_jgr2 = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf; + gid = rpt_jgr2->gid; + break; + #endif + #ifdef PHYSTS_3RD_TYPE_SUPPORT + case PHYDM_PHYSTS_TYPE_3: + rpt_jgr3 = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf; + gid = rpt_jgr3->gid; + break; + #endif + default: + break; + } + + return gid; +} +#endif + +void phydm_rx_statistic_cal(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo) +{ + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + struct phydm_bf_rate_info_jgr3 *bfrateinfo = &dm->bf_rate_info_jgr3; +#endif + + u8 rate = (pktinfo->data_rate & 0x7f); + u8 bw_idx = phy_info->band_width; + u8 offset = 0; + u8 gid = 0; +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT)) + u8 val = 0; +#endif + #ifdef PHYDM_COMPILE_MU + u8 is_mu_pkt = 0; + #endif + + if (rate <= ODM_RATE54M) { + dbg_i->num_qry_legacy_pkt[rate]++; + } else if (rate <= ODM_RATEMCS31) { + dbg_i->ht_pkt_not_zero = true; + offset = rate - ODM_RATEMCS0; + + if (offset > (HT_RATE_NUM - 1)) + offset = HT_RATE_NUM - 1; + + if (dm->support_ic_type & + (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) { + if (bw_idx == *dm->band_width) { + dbg_i->num_qry_ht_pkt[offset]++; + + } else if (bw_idx == CHANNEL_WIDTH_20) { + dbg_i->num_qry_pkt_sc_20m[offset]++; + dbg_i->low_bw_20_occur = true; + } + } else { + dbg_i->num_qry_ht_pkt[offset]++; + } + } +#if (ODM_IC_11AC_SERIES_SUPPORT || defined(PHYSTS_3RD_TYPE_SUPPORT)) + else if (rate <= ODM_RATEVHTSS4MCS9) { + offset = rate - ODM_RATEVHTSS1MCS0; + + if (offset > (VHT_RATE_NUM - 1)) + offset = VHT_RATE_NUM - 1; + + #ifdef PHYDM_COMPILE_MU + gid = phydm_get_gid(dm, phy_status_inf); + + if (gid != 0 && gid != 63) + is_mu_pkt = true; + + if (is_mu_pkt) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\ + (defined(PHYSTS_3RD_TYPE_SUPPORT))) + dbg_i->num_mu_vht_pkt[offset]++; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + bfrateinfo->num_mu_vht_pkt[offset]++; + #endif + #else + dbg_i->num_qry_vht_pkt[offset]++; /*@for debug*/ + #endif + } else + #endif + { + dbg_i->vht_pkt_not_zero = true; + + if (dm->support_ic_type & + (PHYSTS_2ND_TYPE_IC | PHYSTS_3RD_TYPE_IC)) { + if (bw_idx == *dm->band_width) { + dbg_i->num_qry_vht_pkt[offset]++; + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + bfrateinfo->num_qry_vht_pkt[offset]++; + #endif + + } else if (bw_idx == CHANNEL_WIDTH_20) { + dbg_i->num_qry_pkt_sc_20m[offset]++; + dbg_i->low_bw_20_occur = true; + } else {/*@if (bw_idx == CHANNEL_WIDTH_40)*/ + dbg_i->num_qry_pkt_sc_40m[offset]++; + dbg_i->low_bw_40_occur = true; + } + } else { + dbg_i->num_qry_vht_pkt[offset]++; + } + } + + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT ||\ + (defined(PHYSTS_3RD_TYPE_SUPPORT))) + if (pktinfo->ppdu_cnt < 4) { + val = rate; + + #ifdef PHYDM_COMPILE_MU + if (is_mu_pkt) + val |= BIT(7); + #endif + + dbg_i->num_of_ppdu[pktinfo->ppdu_cnt] = val; + dbg_i->gid_num[pktinfo->ppdu_cnt] = gid; + } + #endif + } +#endif +} + +void phydm_reset_phystatus_avg(struct dm_struct *dm) +{ + struct phydm_phystatus_avg *dbg_avg = NULL; + + dbg_avg = &dm->phy_dbg_info.phystatus_statistic_avg; + odm_memory_set(dm, &dbg_avg->rssi_cck_avg, 0, + sizeof(struct phydm_phystatus_avg)); +} + +void phydm_reset_phystatus_statistic(struct dm_struct *dm) +{ + struct phydm_phystatus_statistic *dbg_s = NULL; + + dbg_s = &dm->phy_dbg_info.physts_statistic_info; + + odm_memory_set(dm, &dbg_s->rssi_cck_sum, 0, + sizeof(struct phydm_phystatus_statistic)); +} + +void phydm_reset_phy_info(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info) +{ + u8 i = 0; + + odm_memory_set(dm, &phy_info->physts_rpt_valid, 0, + sizeof(struct phydm_phyinfo_struct)); + + phy_info->rx_power = -110; + phy_info->recv_signal_power = -110; + + for (i = 0; i < dm->num_rf_path; i++) + phy_info->rx_pwr[i] = -110; +} + +void phydm_avg_rssi_evm_snr(void *dm_void, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + u8 *rssi = phy_info->rx_mimo_signal_strength; + u8 *evm = phy_info->rx_mimo_evm_dbm; + s8 *snr = phy_info->rx_snr; + u32 size = PHYSTS_PATH_NUM; /*size of path=4*/ + u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/ + u16 val = 0, intvl = 0; + u8 i = 0; + + if (pktinfo->is_packet_beacon) { + for (i = 0; i < dm->num_rf_path; i++) + dbg_s->rssi_beacon_sum[i] += rssi[i]; + + dbg_s->rssi_beacon_cnt++; + } + + if (pktinfo->data_rate <= ODM_RATE11M) { + /*RSSI*/ + dbg_s->rssi_cck_sum += rssi[0]; + #if (defined(PHYSTS_3RD_TYPE_SUPPORT) && defined(PHYDM_COMPILE_ABOVE_2SS)) + if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) { + for (i = 1; i < dm->num_rf_path; i++) + dbg_s->rssi_cck_sum_abv_2ss[i - 1] += rssi[i]; + } + #endif + dbg_s->rssi_cck_cnt++; + } else if (pktinfo->data_rate <= ODM_RATE54M) { + for (i = 0; i < dm->num_rf_path; i++) { + /*SNR & RSSI*/ + dbg_s->snr_ofdm_sum[i] += snr[i]; + dbg_s->rssi_ofdm_sum[i] += rssi[i]; + } + /*@evm*/ + dbg_s->evm_ofdm_sum += evm[0]; + dbg_s->rssi_ofdm_cnt++; + + val = (u16)evm[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th); + dbg_s->evm_ofdm_hist[intvl]++; + + val = (u16)snr[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th); + dbg_s->snr_ofdm_hist[intvl]++; + + } else if (pktinfo->rate_ss == 1) { +/*@===[1-SS]==================================================================*/ + for (i = 0; i < dm->num_rf_path; i++) { + /*SNR & RSSI*/ + dbg_s->snr_1ss_sum[i] += snr[i]; + dbg_s->rssi_1ss_sum[i] += rssi[i]; + } + + /*@evm*/ + dbg_s->evm_1ss_sum += evm[0]; + /*@EVM Histogram*/ + val = (u16)evm[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, size_th); + dbg_s->evm_1ss_hist[intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[0]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, size_th); + dbg_s->snr_1ss_hist[intvl]++; + + dbg_s->rssi_1ss_cnt++; + } else if (pktinfo->rate_ss == 2) { +/*@===[2-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_2SS)) + for (i = 0; i < dm->num_rf_path; i++) { + /*SNR & RSSI*/ + dbg_s->snr_2ss_sum[i] += snr[i]; + dbg_s->rssi_2ss_sum[i] += rssi[i]; + } + + for (i = 0; i < pktinfo->rate_ss; i++) { + /*@evm*/ + dbg_s->evm_2ss_sum[i] += evm[i]; + /*@EVM Histogram*/ + val = (u16)evm[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, + size_th); + dbg_s->evm_2ss_hist[i][intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, + size_th); + dbg_s->snr_2ss_hist[i][intvl]++; + } + dbg_s->rssi_2ss_cnt++; + #endif + } else if (pktinfo->rate_ss == 3) { +/*@===[3-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + for (i = 0; i < dm->num_rf_path; i++) { + /*SNR & RSSI*/ + dbg_s->snr_3ss_sum[i] += snr[i]; + dbg_s->rssi_3ss_sum[i] += rssi[i]; + } + + for (i = 0; i < pktinfo->rate_ss; i++) { + /*@evm*/ + dbg_s->evm_3ss_sum[i] += evm[i]; + /*@EVM Histogram*/ + val = (u16)evm[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, + size_th); + dbg_s->evm_3ss_hist[i][intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, + size_th); + dbg_s->snr_3ss_hist[i][intvl]++; + } + dbg_s->rssi_3ss_cnt++; + #endif + } else if (pktinfo->rate_ss == 4) { +/*@===[4-SS]==================================================================*/ + #if (defined(PHYDM_COMPILE_ABOVE_4SS)) + for (i = 0; i < dm->num_rf_path; i++) { + /*SNR & RSSI*/ + dbg_s->snr_4ss_sum[i] += snr[i]; + dbg_s->rssi_4ss_sum[i] += rssi[i]; + } + + for (i = 0; i < pktinfo->rate_ss; i++) { + /*@evm*/ + dbg_s->evm_4ss_sum[i] += evm[i]; + + /*@EVM Histogram*/ + val = (u16)evm[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->evm_hist_th, + size_th); + dbg_s->evm_4ss_hist[i][intvl]++; + + /*SNR Histogram*/ + val = (u16)snr[i]; + intvl = phydm_find_intrvl(dm, val, dbg_i->snr_hist_th, + size_th); + dbg_s->snr_4ss_hist[i][intvl]++; + } + dbg_s->rssi_4ss_cnt++; + #endif + } +} + +void phydm_avg_phystatus_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + u16 snr_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26, + 29, 32, 35}; + u16 evm_hist_th[PHY_HIST_TH_SIZE] = {5, 8, 11, 14, 17, 20, 23, 26, + 29, 32, 35}; + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + u16 cn_hist_th[PHY_HIST_TH_SIZE] = {2, 3, 4, 5, 6, 8, 10, + 12, 14, 16, 18}; + #endif + u32 size = PHY_HIST_TH_SIZE * 2; + u8 i = 0; + + odm_move_memory(dm, dbg_i->snr_hist_th, snr_hist_th, size); + odm_move_memory(dm, dbg_i->evm_hist_th, evm_hist_th, size); + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + dm->pkt_proc_struct.physts_auto_swch_en = false; + for (i = 0; i < PHY_HIST_TH_SIZE; i++) + dbg_i->cn_hist_th[i] = cn_hist_th[i] << 1; + #endif +} + +u8 phydm_get_signal_quality(struct phydm_phyinfo_struct *phy_info, + struct dm_struct *dm, + struct phy_status_rpt_8192cd *phy_sts) +{ + u8 sq_rpt; + u8 result = 0; + + if (phy_info->rx_pwdb_all > 40 && !dm->is_in_hct_test) { + result = 100; + } else { + sq_rpt = phy_sts->cck_sig_qual_ofdm_pwdb_all; + + if (sq_rpt > 64) + result = 0; + else if (sq_rpt < 20) + result = 100; + else + result = ((64 - sq_rpt) * 100) / 44; + } + + return result; +} + +u8 phydm_pw_2_percent(s8 ant_power) +{ + if ((ant_power <= -100) || ant_power >= 20) + return 0; + else if (ant_power >= 0) + return 100; + else + return 100 + ant_power; +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +void phydm_process_signal_strength(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + boolean is_cck_rate = 0; + u8 avg_rssi = 0, tmp_rssi = 0, best_rssi = 0, second_rssi = 0; + u8 ss = 0; /*signal strenth after scale mapping*/ + u8 pwdb = phy_info->rx_pwdb_all; + u8 i; + + is_cck_rate = (pktinfo->data_rate <= ODM_RATE11M) ? true : false; + + /*use the best two RSSI only*/ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + tmp_rssi = phy_info->rx_mimo_signal_strength[i]; + + /*@Get the best two RSSI*/ + if (tmp_rssi > best_rssi && tmp_rssi > second_rssi) { + second_rssi = best_rssi; + best_rssi = tmp_rssi; + } else if (tmp_rssi > second_rssi && tmp_rssi <= best_rssi) { + second_rssi = tmp_rssi; + } + } + + if (best_rssi == 0) + return; + + if (pktinfo->rate_ss == 1) + avg_rssi = best_rssi; + else + avg_rssi = (best_rssi + second_rssi) >> 1; + + /* Update signal strength to UI, + * and phy_info->rx_pwdb_all is the maximum RSSI of all path + */ + if (dm->support_ic_type & (PHYSTS_3RD_TYPE_IC | PHYSTS_2ND_TYPE_IC)) + ss = SignalScaleProc(dm->adapter, pwdb, false, false); + else + ss = SignalScaleProc(dm->adapter, pwdb, true, is_cck_rate); + + phy_info->signal_strength = ss; +} + +static u8 phydm_sq_patch_lenovo( + struct dm_struct *dm, + u8 is_cck_rate, + u8 pwdb_all, + u8 path, + u8 RSSI) +{ + u8 sq = 0; + + if (is_cck_rate) { + if (dm->support_ic_type & ODM_RTL8192E) { +/*@ + * + * Expected signal strength and bars indication at Lenovo lab. 2013.04.11 + * 802.11n, 802.11b, 802.11g only at channel 6 + * + * Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) + * 50 5 -49 + * 55 5 -49 + * 60 5 -50 + * 65 5 -51 + * 70 5 -52 + * 75 5 -54 + * 80 5 -55 + * 85 4 -60 + * 90 3 -63 + * 95 3 -65 + * 100 2 -67 + * 102 2 -67 + * 104 1 -70 + */ + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 31 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 22 && pwdb_all < 31) + sq = 40; + else if (pwdb_all >= 18 && pwdb_all < 22) + sq = 20; + else + sq = 10; + } else { + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 22 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 18 && pwdb_all < 22) + sq = 40; + else + sq = 10; + } + + } else { + /* OFDM rate */ + + if (dm->support_ic_type & ODM_RTL8192E) { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } else { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } + } + return sq; +} + +static u8 phydm_sq_patch_rt_cid_819x_acer( + struct dm_struct *dm, + u8 is_cck_rate, + u8 pwdb_all, + u8 path, + u8 RSSI) +{ + u8 sq = 0; + + if (is_cck_rate) { +#if OS_WIN_FROM_WIN8(OS_VERSION) + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 30 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 25 && pwdb_all < 30) + sq = 40; + else if (pwdb_all >= 20 && pwdb_all < 25) + sq = 20; + else + sq = 10; +#else + if (pwdb_all >= 50) + sq = 100; + else if (pwdb_all >= 35 && pwdb_all < 50) + sq = 80; + else if (pwdb_all >= 30 && pwdb_all < 35) + sq = 60; + else if (pwdb_all >= 25 && pwdb_all < 30) + sq = 40; + else if (pwdb_all >= 20 && pwdb_all < 25) + sq = 20; + else + sq = 10; + + /* @Abnormal case, do not indicate the value above 20 on Win7 */ + if (pwdb_all == 0) + sq = 20; +#endif + + } else { + /* OFDM rate */ + if (dm->support_ic_type & ODM_RTL8192E) { + if (RSSI >= 45) + sq = 100; + else if (RSSI >= 22 && RSSI < 45) + sq = 80; + else if (RSSI >= 18 && RSSI < 22) + sq = 40; + else + sq = 20; + } else { + if (RSSI >= 35) + sq = 100; + else if (RSSI >= 30 && RSSI < 35) + sq = 80; + else if (RSSI >= 25 && RSSI < 30) + sq = 40; + else + sq = 20; + } + } + return sq; +} +#endif + +static u8 +phydm_evm_2_percent(s8 value) +{ + /* @-33dB~0dB to 0%~99% */ + s8 ret_val; + + ret_val = value; + ret_val /= 2; + +/*@dbg_print("value=%d\n", value);*/ +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -40) + ret_val = -40; + + ret_val = 0 - ret_val; + ret_val *= 3; +#else + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -33) + ret_val = -33; + + ret_val = 0 - ret_val; + ret_val *= 3; + + if (ret_val == 99) + ret_val = 100; +#endif + + return (u8)ret_val; +} + +s8 phydm_cck_rssi_convert(struct dm_struct *dm, u16 lna_idx, u8 vga_idx) +{ + /*@phydm_get_cck_rssi_table_from_reg*/ + return (dm->cck_lna_gain_table[lna_idx] - (vga_idx << 1)); +} + +void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm) +{ + u8 used_lna_idx_tmp; + u32 reg_0xa80 = 0x7431, reg_0xabc = 0xcbe5edfd; + u32 val = 0; + u8 i; + + /*@example: {-53, -43, -33, -27, -19, -13, -3, 1}*/ + /*@{0xCB, 0xD5, 0xDF, 0xE5, 0xED, 0xF3, 0xFD, 0x2}*/ + + PHYDM_DBG(dm, ODM_COMP_INIT, "CCK LNA Gain table init\n"); + + if (!(dm->support_ic_type & ODM_RTL8197F)) + return; + + reg_0xa80 = odm_get_bb_reg(dm, R_0xa80, 0xFFFF); + reg_0xabc = odm_get_bb_reg(dm, R_0xabc, MASKDWORD); + + PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xa80 = 0x%x\n", reg_0xa80); + PHYDM_DBG(dm, ODM_COMP_INIT, "reg_0xabc = 0x%x\n", reg_0xabc); + + for (i = 0; i <= 3; i++) { + used_lna_idx_tmp = (u8)((reg_0xa80 >> (4 * i)) & 0x7); + val = (reg_0xabc >> (8 * i)) & 0xff; + dm->cck_lna_gain_table[used_lna_idx_tmp] = (s8)val; + } + + PHYDM_DBG(dm, ODM_COMP_INIT, + "cck_lna_gain_table = {%d,%d,%d,%d,%d,%d,%d,%d}\n", + dm->cck_lna_gain_table[0], dm->cck_lna_gain_table[1], + dm->cck_lna_gain_table[2], dm->cck_lna_gain_table[3], + dm->cck_lna_gain_table[4], dm->cck_lna_gain_table[5], + dm->cck_lna_gain_table[6], dm->cck_lna_gain_table[7]); +} + +s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + s8 rx_pow = 0; + + switch (dm->support_ic_type) { + #if (RTL8197F_SUPPORT) + case ODM_RTL8197F: + rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8723D_SUPPORT) + case ODM_RTL8723D: + rx_pow = phydm_cckrssi_8723d(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8710B_SUPPORT) + case ODM_RTL8710B: + rx_pow = phydm_cckrssi_8710b(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8721D_SUPPORT) + case ODM_RTL8721D: + rx_pow = phydm_cckrssi_8721d(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8710C_SUPPORT) + case ODM_RTL8710C: + rx_pow = phydm_cckrssi_8710c(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8192F_SUPPORT) + case ODM_RTL8192F: + rx_pow = phydm_cckrssi_8192f(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8821C_SUPPORT) + case ODM_RTL8821C: + rx_pow = phydm_cck_rssi_8821c(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8195B_SUPPORT) + case ODM_RTL8195B: + rx_pow = phydm_cck_rssi_8195B(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8188E_SUPPORT) + case ODM_RTL8188E: + rx_pow = phydm_cck_rssi_8188e(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8192E_SUPPORT) + case ODM_RTL8192E: + rx_pow = phydm_cck_rssi_8192e(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8723B_SUPPORT) + case ODM_RTL8723B: + rx_pow = phydm_cck_rssi_8723b(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8703B_SUPPORT) + case ODM_RTL8703B: + rx_pow = phydm_cck_rssi_8703b(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8188F_SUPPORT) + case ODM_RTL8188F: + rx_pow = phydm_cck_rssi_8188f(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8195A_SUPPORT) + case ODM_RTL8195A: + rx_pow = phydm_cck_rssi_8195a(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8812A_SUPPORT) + case ODM_RTL8812: + rx_pow = phydm_cck_rssi_8812a(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8821A_SUPPORT || RTL8881A_SUPPORT) + case ODM_RTL8821: + case ODM_RTL8881A: + rx_pow = phydm_cck_rssi_8821a(dm, lna_idx, vga_idx); + break; + #endif + + #if (RTL8814A_SUPPORT) + case ODM_RTL8814A: + rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx); + break; + #endif + + default: + break; + } + + return rx_pow; +} + +#if (ODM_IC_11N_SERIES_SUPPORT) +void phydm_phy_sts_n_parsing(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo) +{ + u8 i = 0; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM, pwdb_all = 0, pwdb_all_bt = 0; + u8 RSSI, total_rssi = 0; + u8 rf_rx_num = 0; + u8 lna_idx = 0; + u8 vga_idx = 0; + u8 cck_agc_rpt; + s8 evm_tmp = 0; + u8 sq = 0; + u8 val_tmp = 0; + s8 val_s8 = 0; + struct phy_status_rpt_8192cd *phy_sts = NULL; + + phy_sts = (struct phy_status_rpt_8192cd *)phy_status_inf; + + if (pktinfo->is_cck_rate) { + cck_agc_rpt = phy_sts->cck_agc_rpt_ofdm_cfosho_a; + + /*@3 bit LNA*/ + lna_idx = ((cck_agc_rpt & 0xE0) >> 5); + vga_idx = (cck_agc_rpt & 0x1F); + + #if (RTL8703B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8703B) && + dm->cck_agc_report_type == 1) { + /*@4 bit LNA*/ + if (phy_sts->cck_rpt_b_ofdm_cfosho_b & BIT(7)) + val_tmp = 1; + else + val_tmp = 0; + lna_idx = (val_tmp << 3) | lna_idx; + } + #endif + + rx_pwr_all = phydm_get_cck_rssi(dm, lna_idx, vga_idx); + + PHYDM_DBG(dm, DBG_RSSI_MNTR, + "ext_lna_gain (( %d )), lna_idx: (( 0x%x )), vga_idx: (( 0x%x )), rx_pwr_all: (( %d ))\n", + dm->ext_lna_gain, lna_idx, vga_idx, rx_pwr_all); + + if (dm->board_type & ODM_BOARD_EXT_LNA) + rx_pwr_all -= dm->ext_lna_gain; + + pwdb_all = phydm_pw_2_percent(rx_pwr_all); + + if (pktinfo->is_to_self) { + dm->cck_lna_idx = lna_idx; + dm->cck_vga_idx = vga_idx; + } + + phy_info->rx_pwdb_all = pwdb_all; + phy_info->bt_rx_rssi_percentage = pwdb_all; + phy_info->recv_signal_power = rx_pwr_all; + + /* @(3) Get Signal Quality (EVM) */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) + sq = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0); + else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER) + sq = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, 0); + else + #endif + sq = phydm_get_signal_quality(phy_info, dm, phy_sts); + + /* @dbg_print("cck sq = %d\n", sq); */ + + phy_info->signal_quality = sq; + phy_info->rx_mimo_signal_quality[RF_PATH_A] = sq; + phy_info->rx_mimo_signal_quality[RF_PATH_B] = -1; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (i == 0) + phy_info->rx_mimo_signal_strength[0] = pwdb_all; + else + phy_info->rx_mimo_signal_strength[i] = 0; + } + } else { /* @2 is OFDM rate */ + + /* @(1)Get RSSI for HT rate */ + + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if (dm->rf_path_rx_enable & BIT(i)) + rf_rx_num++; + + val_s8 = phy_sts->path_agc[i].gain & 0x3F; + rx_pwr[i] = (val_s8 * 2) - 110; + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = val_s8; + + phy_info->rx_pwr[i] = rx_pwr[i]; + RSSI = phydm_pw_2_percent(rx_pwr[i]); + total_rssi += RSSI; + + phy_info->rx_mimo_signal_strength[i] = (u8)RSSI; + + /* @Get Rx snr value in DB */ + val_s8 = (s8)(phy_sts->path_rxsnr[i] / 2); + phy_info->rx_snr[i] = val_s8; + + /* Record Signal Strength for next packet */ + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (i == RF_PATH_A) { + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + phy_info->signal_quality = phydm_sq_patch_lenovo(dm, pktinfo->is_cck_rate, pwdb_all, i, RSSI); + } else if (dm->iot_table.win_patch_id == RT_CID_819X_ACER) + phy_info->signal_quality = phydm_sq_patch_rt_cid_819x_acer(dm, pktinfo->is_cck_rate, pwdb_all, 0, RSSI); + } + #endif + } + + /* @(2)PWDB, Average PWDB calculated by hardware (for RA) */ + val_s8 = phy_sts->cck_sig_qual_ofdm_pwdb_all >> 1; + rx_pwr_all = (val_s8 & 0x7f) - 110; + + pwdb_all = phydm_pw_2_percent(rx_pwr_all); + pwdb_all_bt = pwdb_all; + + phy_info->rx_pwdb_all = pwdb_all; + phy_info->bt_rx_rssi_percentage = pwdb_all_bt; + phy_info->rx_power = rx_pwr_all; + phy_info->recv_signal_power = rx_pwr_all; + + /* @(3)EVM of HT rate */ + for (i = 0; i < pktinfo->rate_ss; i++) { + /* @Do not use shift operation like "rx_evmX >>= 1" + * because the compilor of free build environment + * fill most significant bit to "zero" when doing shifting + * operation which may change a negative + * value to positive one, then the dbm value + * (which is supposed to be negative) is not correct anymore. + */ + if (i >= PHYDM_MAX_RF_PATH_N) + break; + + EVM = phydm_evm_2_percent(phy_sts->stream_rxevm[i]); + + /*@Fill value in RFD, Get the 1st spatial stream only*/ + if (i == RF_PATH_A) + phy_info->signal_quality = (u8)(EVM & 0xff); + + phy_info->rx_mimo_signal_quality[i] = (u8)(EVM & 0xff); + + if (phy_sts->stream_rxevm[i] < 0) + evm_tmp = 0 - phy_sts->stream_rxevm[i]; + + if (evm_tmp == 64) + evm_tmp = 0; + + phy_info->rx_mimo_evm_dbm[i] = (u8)evm_tmp; + } + phydm_parsing_cfo(dm, pktinfo, + phy_sts->path_cfotail, pktinfo->rate_ss); + } + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->ant_sel; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->ant_sel_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antsel_rx_keep_2; + #endif +} +#endif + +#if ODM_IC_11AC_SERIES_SUPPORT +static s16 +phydm_cfo(s8 value) +{ + s16 ret_val; + + if (value < 0) { + ret_val = 0 - value; + ret_val = (ret_val << 1) + (ret_val >> 1); /*@2.5~=312.5/2^7 */ + ret_val = ret_val | BIT(12); /*set bit12 as 1 for negative cfo*/ + } else { + ret_val = value; + ret_val = (ret_val << 1) + (ret_val >> 1); /* @*2.5~=312.5/2^7*/ + } + return ret_val; +} + +static u8 +phydm_evm_dbm(s8 value) +{ + s8 ret_val = value; + + /* @-33dB~0dB to 33dB ~ 0dB */ + if (ret_val == -128) + ret_val = 127; + else if (ret_val < 0) + ret_val = 0 - ret_val; + + ret_val = ret_val >> 1; + return (u8)ret_val; +} + +void phydm_rx_physts_bw_parsing(struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct * + pktinfo, + struct phy_status_rpt_8812 * + phy_sts) +{ + if (pktinfo->data_rate > ODM_RATE54M) { + switch (phy_sts->r_RFMOD) { + case 1: + if (phy_sts->sub_chnl == 0) + phy_info->band_width = 1; + else + phy_info->band_width = 0; + break; + + case 2: + if (phy_sts->sub_chnl == 0) + phy_info->band_width = 2; + else if (phy_sts->sub_chnl == 9 || + phy_sts->sub_chnl == 10) + phy_info->band_width = 1; + else + phy_info->band_width = 0; + break; + + default: + case 0: + phy_info->band_width = 0; + break; + } + } +} + +void phydm_get_sq(struct dm_struct *dm, struct phydm_phyinfo_struct *phy_info, + u8 is_cck_rate) +{ + u8 sq = 0; + u8 pwdb_all = phy_info->rx_pwdb_all; /*precentage*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + u8 rssi = phy_info->rx_mimo_signal_strength[0]; + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (dm->iot_table.win_patch_id == RT_CID_819X_LENOVO) { + if (is_cck_rate) + sq = phydm_sq_patch_lenovo(dm, 1, pwdb_all, 0, 0); + else + sq = phydm_sq_patch_lenovo(dm, 0, pwdb_all, 0, rssi); + } else + #endif + { + if (is_cck_rate) { + if (pwdb_all > 40 && !dm->is_in_hct_test) { + sq = 100; + } else { + if (pwdb_all > 64) + sq = 0; + else if (pwdb_all < 20) + sq = 100; + else + sq = ((64 - pwdb_all) * 100) / 44; + } + } else { + sq = phy_info->rx_mimo_signal_quality[0]; + } + } + +#if 0 + /* @dbg_print("cck sq = %d\n", sq); */ +#endif + phy_info->signal_quality = sq; +} + +void phydm_rx_physts_1st_type(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo) +{ + u8 i = 0; + s8 rx_pwr_db = 0; + u8 val = 0; /*tmp value*/ + s8 val_s8 = 0; /*tmp value*/ + u8 rssi = 0; /*pre path RSSI*/ + u8 rf_rx_num = 0; + u8 lna_idx = 0, vga_idx = 0; + u8 cck_agc_rpt = 0; + struct phy_status_rpt_8812 *phy_sts = NULL; + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + #endif + + phy_sts = (struct phy_status_rpt_8812 *)phy_status_inf; + phydm_rx_physts_bw_parsing(phy_info, pktinfo, phy_sts); + + /* @== [CCK rate] ====================================================*/ + if (pktinfo->is_cck_rate) { + cck_agc_rpt = phy_sts->cfosho[0]; + lna_idx = (cck_agc_rpt & 0xE0) >> 5; + vga_idx = cck_agc_rpt & 0x1F; + + rx_pwr_db = phydm_get_cck_rssi(dm, lna_idx, vga_idx); + rssi = phydm_pw_2_percent(rx_pwr_db); + + if (dm->support_ic_type == ODM_RTL8812 && + !dm->is_cck_high_power) { + if (rssi >= 80) { + rssi = ((rssi - 80) << 1) + + ((rssi - 80) >> 1) + 80; + } else if ((rssi <= 78) && (rssi >= 20)) { + rssi += 3; + } + } + dm->cck_lna_idx = lna_idx; + dm->cck_vga_idx = vga_idx; + + phy_info->rx_pwdb_all = rssi; + phy_info->rx_mimo_signal_strength[0] = rssi; + } else { + /* @== [OFDM rate] ===================================================*/ + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + /*@[RSSI]*/ + if (dm->rf_path_rx_enable & BIT(i)) + rf_rx_num++; + + if (i < RF_PATH_C) + val = phy_sts->gain_trsw[i]; + else + val = phy_sts->gain_trsw_cd[i - 2]; + + phy_info->rx_pwr[i] = (val & 0x7F) - 110; + rssi = phydm_pw_2_percent(phy_info->rx_pwr[i]); + phy_info->rx_mimo_signal_strength[i] = rssi; + + /*@[SNR]*/ + if (i < RF_PATH_C) + val_s8 = phy_sts->rxsnr[i]; + else if (dm->support_ic_type & (ODM_RTL8814A)) + val_s8 = (s8)phy_sts->csi_current[i - 2]; + + phy_info->rx_snr[i] = val_s8 >> 1; + + /*@[CFO_short & CFO_tail]*/ + if (i < RF_PATH_C) { + val_s8 = phy_sts->cfosho[i]; + phy_info->cfo_short[i] = phydm_cfo(val_s8); + val_s8 = phy_sts->cfotail[i]; + phy_info->cfo_tail[i] = phydm_cfo(val_s8); + } + + if (i < RF_PATH_C && pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->gain_trsw[i]; + } + + /* @== [PWDB] ========================================================*/ + + /*@(Avg PWDB calculated by hardware*/ + if (!dm->is_mp_chip) /*@8812, 8821*/ + val = phy_sts->pwdb_all; + else + val = phy_sts->pwdb_all >> 1; /*old fomula*/ + + rx_pwr_db = (val & 0x7f) - 110; + phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db); + + /*@(4)EVM of OFDM rate*/ + for (i = 0; i < pktinfo->rate_ss; i++) { + if (!pktinfo->is_cck_rate && + pktinfo->data_rate <= ODM_RATE54M) { + val_s8 = phy_sts->sigevm; + } else if (i < RF_PATH_C) { + if (phy_sts->rxevm[i] == -128) + phy_sts->rxevm[i] = -25; + + val_s8 = phy_sts->rxevm[i]; + } else { + if (phy_sts->rxevm_cd[i - 2] == -128) + phy_sts->rxevm_cd[i - 2] = -25; + + val_s8 = phy_sts->rxevm_cd[i - 2]; + } + /*@[EVM to 0~100%]*/ + val = phydm_evm_2_percent(val_s8); + phy_info->rx_mimo_signal_quality[i] = val; + /*@[EVM dBm]*/ + phy_info->rx_mimo_evm_dbm[i] = phydm_evm_dbm(val_s8); + } + phydm_parsing_cfo(dm, pktinfo, + phy_sts->cfotail, pktinfo->rate_ss); + } + + /* @== [General Info] ================================================*/ + + phy_info->rx_power = rx_pwr_db; + phy_info->bt_rx_rssi_percentage = phy_info->rx_pwdb_all; + phy_info->recv_signal_power = phy_info->rx_power; + phydm_get_sq(dm, phy_info, pktinfo->is_cck_rate); + + dm->rx_pwdb_ave = dm->rx_pwdb_ave + phy_info->rx_pwdb_all; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + fat_tab->hw_antsw_occur = phy_sts->hw_antsw_occur; + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_anta; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_antb; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_antc; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_antd; + #endif +} + +#endif + +void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id) +{ + struct cmn_sta_info *sta; + + sta = dm->phydm_sta_info[station_id]; + + if (!is_sta_active(sta)) + return; + PHYDM_DBG(dm, DBG_RSSI_MNTR, "Reset RSSI for macid = (( %d ))\n", + station_id); + + sta->rssi_stat.rssi_cck = -1; + sta->rssi_stat.rssi_ofdm = -1; + sta->rssi_stat.rssi = -1; + sta->rssi_stat.ofdm_pkt_cnt = 0; + sta->rssi_stat.cck_pkt_cnt = 0; + sta->rssi_stat.cck_sum_power = 0; + sta->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT; + sta->rssi_stat.packet_map = 0; + sta->rssi_stat.valid_bit = 0; +} + +#if (ODM_IC_11N_SERIES_SUPPORT || ODM_IC_11AC_SERIES_SUPPORT) + +s32 phydm_get_rssi_8814_ofdm(struct dm_struct *dm, u8 *rssi_in) +{ + s32 rssi_avg; + u8 rx_count = 0; + u64 rssi_linear = 0; + + if (dm->rx_ant_status & BB_PATH_A) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_A]); + } + + if (dm->rx_ant_status & BB_PATH_B) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_B]); + } + + if (dm->rx_ant_status & BB_PATH_C) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_C]); + } + + if (dm->rx_ant_status & BB_PATH_D) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_in[RF_PATH_D]); + } + + /* @Rounding and removing fractional bits */ + rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; + + /* @Calculate average RSSI */ + switch (rx_count) { + case 2: + rssi_linear = DIVIDED_2(rssi_linear); + break; + case 3: + rssi_linear = DIVIDED_3(rssi_linear); + break; + case 4: + rssi_linear = DIVIDED_4(rssi_linear); + break; + } + rssi_avg = odm_convert_to_db(rssi_linear); + + return rssi_avg; +} + +void phydm_process_rssi_for_dm(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + s32 rssi_ave = 0; /*@average among all paths*/ + s8 rssi_all = 0; /*@average value of CCK & OFDM*/ + s8 rssi_cck_tmp = 0, rssi_ofdm_tmp = 0; + u8 i = 0; + u8 rssi_max = 0, rssi_min = 0; + u32 w1 = 0, w2 = 0; /*weighting*/ + u8 send_rssi_2_fw = 0; + u8 *rssi_tmp = NULL; + struct cmn_sta_info *sta = NULL; + struct rssi_info *rssi_t = NULL; + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + #endif + #endif + + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(dm, phy_info, pktinfo); + #endif + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) + return; + + rssi_t = &sta->rssi_stat; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ((dm->support_ability & ODM_BB_ANT_DIV) && + fat_tab->enable_ctrl_frame_antdiv) { + if (pktinfo->is_packet_match_bssid) + dm->data_frame_num++; + + if (fat_tab->use_ctrl_frame_antdiv) { + if (!pktinfo->is_to_self) /*@data frame + CTRL frame*/ + return; + } else { + /*@data frame only*/ + if (!pktinfo->is_packet_match_bssid) + return; + } + } else + #endif + #endif + { + if (!pktinfo->is_packet_match_bssid) /*@data frame only*/ + return; + } + + if (pktinfo->is_packet_beacon) { + dm->phy_dbg_info.num_qry_beacon_pkt++; + dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate; + } + + /* @--------------Statistic for antenna/path diversity--------------- */ + #ifdef ODM_EVM_ENHANCE_ANTDIV + if (dm->antdiv_evm_en) + phydm_rx_rate_for_antdiv(dm, pktinfo); + #endif + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + if (dm->support_ability & ODM_BB_ANT_DIV) + odm_process_rssi_for_ant_div(dm, phy_info, pktinfo); + #endif + + #if (defined(CONFIG_PATH_DIVERSITY)) + if (dm->support_ability & ODM_BB_PATH_DIV) + phydm_process_rssi_for_path_div(dm, phy_info, pktinfo); + #endif + /* @----------------------------------------------------------------- */ + + rssi_cck_tmp = rssi_t->rssi_cck; + rssi_ofdm_tmp = rssi_t->rssi_ofdm; + rssi_all = rssi_t->rssi; + + if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_beacon)) + return; + + if (!pktinfo->is_cck_rate) { +/* @=== [ofdm RSSI] ======================================================== */ + rssi_tmp = phy_info->rx_mimo_signal_strength; + + #if (RTL8814A_SUPPORT == 1) + if (dm->support_ic_type & (ODM_RTL8814A)) { + rssi_ave = phydm_get_rssi_8814_ofdm(dm, rssi_tmp); + } else + #endif + { + if (rssi_tmp[RF_PATH_B] == 0) { + rssi_ave = rssi_tmp[RF_PATH_A]; + } else { + if (rssi_tmp[RF_PATH_A] > rssi_tmp[RF_PATH_B]) { + rssi_max = rssi_tmp[RF_PATH_A]; + rssi_min = rssi_tmp[RF_PATH_B]; + } else { + rssi_max = rssi_tmp[RF_PATH_B]; + rssi_min = rssi_tmp[RF_PATH_A]; + } + if ((rssi_max - rssi_min) < 3) + rssi_ave = rssi_max; + else if ((rssi_max - rssi_min) < 6) + rssi_ave = rssi_max - 1; + else if ((rssi_max - rssi_min) < 10) + rssi_ave = rssi_max - 2; + else + rssi_ave = rssi_max - 3; + } + } + + /* OFDM MA RSSI */ + if (rssi_ofdm_tmp <= 0) { /* @initialize */ + rssi_ofdm_tmp = (s8)phy_info->rx_pwdb_all; + } else { + rssi_ofdm_tmp = (s8)WEIGHTING_AVG(rssi_ofdm_tmp, + (1 << RSSI_MA) - 1, + rssi_ave, 1); + if (phy_info->rx_pwdb_all > (u32)rssi_ofdm_tmp) + rssi_ofdm_tmp++; + } + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_ofdm=%d\n", rssi_ofdm_tmp); + } else { +/* @=== [cck RSSI] ========================================================= */ + rssi_ave = phy_info->rx_pwdb_all; + + if (rssi_t->cck_pkt_cnt <= 63) + rssi_t->cck_pkt_cnt++; + + /* @1 Process CCK RSSI */ + if (rssi_cck_tmp <= 0) { /* @initialize */ + rssi_cck_tmp = (s8)phy_info->rx_pwdb_all; + rssi_t->cck_sum_power = (u16)phy_info->rx_pwdb_all; + rssi_t->cck_pkt_cnt = 1; /*reset*/ + PHYDM_DBG(dm, DBG_RSSI_MNTR, "[1]CCK_INIT\n"); + } else if (rssi_t->cck_pkt_cnt <= CCK_RSSI_INIT_COUNT) { + rssi_t->cck_sum_power = rssi_t->cck_sum_power + + (u16)phy_info->rx_pwdb_all; + + rssi_cck_tmp = rssi_t->cck_sum_power / + rssi_t->cck_pkt_cnt; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, + "[2]SumPow=%d, cck_pkt=%d\n", + rssi_t->cck_sum_power, rssi_t->cck_pkt_cnt); + } else { + rssi_cck_tmp = (s8)WEIGHTING_AVG(rssi_cck_tmp, + (1 << RSSI_MA) - 1, + phy_info->rx_pwdb_all, + 1); + if (phy_info->rx_pwdb_all > (u32)rssi_cck_tmp) + rssi_cck_tmp++; + } + PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi_cck=%d\n", rssi_cck_tmp); + } + +/* @=== [ofdm + cck weighting RSSI] ========================================= */ + if (!pktinfo->is_cck_rate) { + if (rssi_t->ofdm_pkt_cnt < 8 && !(rssi_t->packet_map & BIT(7))) + rssi_t->ofdm_pkt_cnt++; /*OFDM packet cnt in bitmap*/ + + rssi_t->packet_map = (rssi_t->packet_map << 1) | BIT(0); + } else { + if (rssi_t->ofdm_pkt_cnt > 0 && rssi_t->packet_map & BIT(7)) + rssi_t->ofdm_pkt_cnt--; + + rssi_t->packet_map = rssi_t->packet_map << 1; + } + + if (rssi_t->ofdm_pkt_cnt == 8) { + rssi_all = rssi_ofdm_tmp; + } else { + if (rssi_t->valid_bit < 8) + rssi_t->valid_bit++; + + if (rssi_t->valid_bit == 8) { + if (rssi_t->ofdm_pkt_cnt > 4) + w1 = 64; + else + w1 = (u32)(rssi_t->ofdm_pkt_cnt << 4); + + w2 = 64 - w1; + + rssi_all = (s8)((w1 * (u32)rssi_ofdm_tmp + + w2 * (u32)rssi_cck_tmp) >> 6); + } else if (rssi_t->valid_bit != 0) { /*@(valid_bit > 8)*/ + w1 = (u32)rssi_t->ofdm_pkt_cnt; + w2 = (u32)(rssi_t->valid_bit - rssi_t->ofdm_pkt_cnt); + rssi_all = (s8)WEIGHTING_AVG((u32)rssi_ofdm_tmp, w1, + (u32)rssi_cck_tmp, w2); + } else { + rssi_all = 0; + } + } + PHYDM_DBG(dm, DBG_RSSI_MNTR, "rssi=%d,w1=%d,w2=%d\n", rssi_all, w1, w2); + + if ((rssi_t->ofdm_pkt_cnt >= 1 || rssi_t->cck_pkt_cnt >= 5) && + rssi_t->is_send_rssi == RA_RSSI_STATE_INIT) { + send_rssi_2_fw = 1; + rssi_t->is_send_rssi = RA_RSSI_STATE_SEND; + } + + rssi_t->rssi_cck = rssi_cck_tmp; + rssi_t->rssi_ofdm = rssi_ofdm_tmp; + rssi_t->rssi = rssi_all; + + if (send_rssi_2_fw) { /* Trigger init rate by RSSI */ + if (rssi_t->ofdm_pkt_cnt != 0) + rssi_t->rssi = rssi_ofdm_tmp; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, + "[Send to FW] PWDB=%d, ofdm_pkt=%d, cck_pkt=%d\n", + rssi_all, rssi_t->ofdm_pkt_cnt, rssi_t->cck_pkt_cnt); + } + +#if 0 + /* @dbg_print("ofdm_pkt=%d, weighting=%d\n", ofdm_pkt_cnt, weighting);*/ + /* @dbg_print("rssi_ofdm_tmp=%d, rssi_all=%d, rssi_cck_tmp=%d\n", */ + /* rssi_ofdm_tmp, rssi_all, rssi_cck_tmp); */ +#endif +} +#endif + +#ifdef PHYSTS_3RD_TYPE_SUPPORT +#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH +void phydm_physts_auto_switch_jgr3_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct; + + pkt_proc->phy_ppdu_cnt = 0xff; + pkt_proc->mac_ppdu_cnt = 0xff; + pkt_proc->page_bitmap_record = 0; +} + +boolean phydm_physts_auto_switch_jgr3(void *dm_void, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct; + boolean is_skip_physts_parsing = false; + u8 phy_sts_byte0 = (*phy_sts & 0xff); + u8 phy_ppdu_cnt_pre = 0, mac_ppdu_cnt_pre = 0; + u8 ppdu_phy_rate_pre = 0, ppdu_macid_pre = 0; + u8 page = phy_sts_byte0 & 0xf; + + if (!pkt_proc->physts_auto_swch_en) + return is_skip_physts_parsing; + + phy_ppdu_cnt_pre = pkt_proc->phy_ppdu_cnt; + mac_ppdu_cnt_pre = pkt_proc->mac_ppdu_cnt; + ppdu_phy_rate_pre = pkt_proc->ppdu_phy_rate; + ppdu_macid_pre = pkt_proc->ppdu_macid; + + pkt_proc->phy_ppdu_cnt = (phy_sts_byte0 & 0x30) >> 4; + pkt_proc->mac_ppdu_cnt = pktinfo->ppdu_cnt; + pkt_proc->ppdu_phy_rate = pktinfo->data_rate; + pkt_proc->ppdu_macid = pktinfo->station_id; + + PHYDM_DBG(dm, DBG_PHY_STATUS, + "[rate:0x%x] PPDU mac{pre, curr}= {%d, %d}, phy{pre, curr}= {%d, %d}\n", + pktinfo->data_rate, mac_ppdu_cnt_pre, pkt_proc->mac_ppdu_cnt, + phy_ppdu_cnt_pre, pkt_proc->phy_ppdu_cnt); + + if (pktinfo->data_rate < ODM_RATEMCS0) { + pkt_proc->page_bitmap_record = 0; + return is_skip_physts_parsing; + } + + if (ppdu_macid_pre == pkt_proc->ppdu_macid && + ppdu_phy_rate_pre == pkt_proc->ppdu_phy_rate && + phy_ppdu_cnt_pre == pkt_proc->phy_ppdu_cnt && + mac_ppdu_cnt_pre == pkt_proc->mac_ppdu_cnt) { + if (pkt_proc->page_bitmap_record & BIT(page)) { + /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect page-%d enough\n", page);*/ + is_skip_physts_parsing = true; + } else if (pkt_proc->page_bitmap_record == + pkt_proc->page_bitmap_target) { + /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "collect all enough\n");*/ + is_skip_physts_parsing = true; + } else { + /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "update page-%d\n", page);*/ + pkt_proc->page_bitmap_record |= BIT(page); + } + pkt_proc->is_1st_mpdu = false; + } else { + /*@PHYDM_DBG(dm, DBG_PHY_STATUS, "[New Pkt] update page-%d\n", page);*/ + pkt_proc->page_bitmap_record = BIT(page); + pkt_proc->is_1st_mpdu = true; + } + + PHYDM_DBG(dm, DBG_PHY_STATUS, + "bitmap{record, target}= {0x%x, 0x%x}\n", + pkt_proc->page_bitmap_record, + pkt_proc->page_bitmap_target); + + return is_skip_physts_parsing; +} + +void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable, + u8 bitmap_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct; + u16 en_page_num = 1; + + if (!(dm->support_ic_type & PHYSTS_AUTO_SWITCH_IC)) + return; +#if 0 + if (!(dm->support_ic_type & PHYSTS_3RD_TYPE_IC)) + return; +#endif + pkt_proc->physts_auto_swch_en = enable; + pkt_proc->page_bitmap_target = bitmap_en; + phydm_physts_auto_switch_jgr3_reset(dm); + en_page_num = phydm_ones_num_in_bitmap((u64)bitmap_en, 8); + + PHYDM_DBG(dm, DBG_CMN, "[%s]en=%d, bitmap_en=%d, en_page_num=%d\n", + __func__, enable, bitmap_en, en_page_num); + + if (enable) { + /*@per MPDU latch & update phy-staatus*/ + odm_set_mac_reg(dm, R_0x60c, BIT(31), 1); + /*@Update Period (OFDM Symbol)*/ + odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 3); + /*@switchin bitmap*/ + odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, bitmap_en); + /*@mode 3*/ + odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 3); + } else { + odm_set_mac_reg(dm, R_0x60c, BIT(31), 0); + odm_set_bb_reg(dm, R_0x8c0, 0xfc000, 0x1); + odm_set_bb_reg(dm, R_0x8c4, 0x7f80000, 0x2); + odm_set_bb_reg(dm, R_0x8c4, (BIT(28) | BIT(27)), 0); + } +} + +void phydm_avg_condi_num(void *dm_void, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + struct phydm_phystatus_statistic *dbg_s = &dbg_i->physts_statistic_info; + u16 size_th = PHY_HIST_SIZE - 1; /*size of threshold*/ + u16 val = 0, intvl = 0; + u8 arry_idx = 0; + + if (pktinfo->rate_ss == 1) + return; + + arry_idx = pktinfo->rate_ss - 1; + + dbg_s->p4_cnt[arry_idx]++; + dbg_s->cn_sum[arry_idx] += dbg_i->condition_num_seg0; + + /*CN Histogram*/ + val = (u16)dbg_i->condition_num_seg0; + intvl = phydm_find_intrvl(dm, val, dbg_i->cn_hist_th, size_th); + dbg_s->cn_hist[arry_idx][intvl]++; + + dbg_i->condi_num = (u32)dbg_i->condition_num_seg0; /*will remove*/ +} +#endif + +void phydm_print_phystat_jgr3(struct dm_struct *dm, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_sts_rpt_jgr3_type0 *rpt0 = NULL; + struct phy_sts_rpt_jgr3_type1 *rpt1 = NULL; + struct phy_sts_rpt_jgr3_type2_3 *rpt2 = NULL; + struct phy_sts_rpt_jgr3_type4 *rpt3 = NULL; + struct phy_sts_rpt_jgr3_type5 *rpt4 = NULL; + struct phy_sts_rpt_jgr3_type6 *rpt5 = NULL; + + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u8 phy_status_page_num = (*phy_sts & 0xf); + u32 *phy_status_tmp = NULL; + u8 i = 0; + /*u32 size = PHY_STATUS_JRGUAR3_DW_LEN << 2;*/ + + if (!(dm->debug_components & DBG_PHY_STATUS)) + return; + + rpt0 = (struct phy_sts_rpt_jgr3_type0 *)phy_sts; + rpt1 = (struct phy_sts_rpt_jgr3_type1 *)phy_sts; + rpt2 = (struct phy_sts_rpt_jgr3_type2_3 *)phy_sts; + rpt3 = (struct phy_sts_rpt_jgr3_type4 *)phy_sts; + rpt4 = (struct phy_sts_rpt_jgr3_type5 *)phy_sts; + + if (dm->support_ic_type & ODM_RTL8723F) { + rpt5 = (struct phy_sts_rpt_jgr3_type6 *)phy_sts; + + if (pktinfo->is_cck_rate) + phy_status_page_num = 0; + } + + phy_status_tmp = (u32 *)phy_sts; + + if (dbg->show_phy_sts_all_pkt == 0) { + if (!pktinfo->is_packet_match_bssid) + return; + } + + dbg->show_phy_sts_cnt++; + + if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) { + if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt) + return; + } + + if (phy_status_page_num == 0) + pr_debug("Phy Status Rpt: CCK\n"); + else + pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num); + + pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d, ppdu_cnt=%d\n", + pktinfo->station_id, pktinfo->data_rate, + pktinfo->is_packet_match_bssid, pktinfo->ppdu_cnt); + + for (i = 0; i < PHY_STATUS_JRGUAR3_DW_LEN; i++) + pr_debug("Offset[%d:%d] = 0x%x\n", + ((4 * i) + 3), (4 * i), phy_status_tmp[i]); + + if (phy_status_page_num == 0) { /* @CCK(default) */ + if (dm->support_ic_type & ODM_RTL8723F) { + #if (RTL8723F_SUPPORT) + pr_debug("[0] Pop_idx=%d, Pkt_cnt=%d, Channel_msb=%d, AGC_table_path0=%d, TRSW_mux_keep=%d, HW_AntSW_occur_keep_cck=%d, Gnt_BT_keep_cnt=%d,Rssi_msb=%d\n", + rpt5->pop_idx, rpt5->pkt_cnt, + rpt5->channel_msb, rpt5->agc_table_a, + rpt5->trsw, rpt5->hw_antsw_occur_keep_cck, + rpt5->gnt_bt_keep_cck, rpt5->rssi_msb); + pr_debug("[4] Channel=%d, Antidx_CCK_keep=%d, Cck_mp_gain_idx_keep=%d\n", + rpt5->channel, rpt5->antidx_a, + rpt5->mp_gain_idx_a); + pr_debug("[8] Rssi=%d\n",rpt5->rssi); + pr_debug("[12] Avg_cfo=%d\n",rpt5->avg_cfo); + pr_debug("[16] Coarse_cfo=%d, Coarse_cfo_msb=%d, Avg_cfo_msb=%d, Evm_hdr=%d\n", + rpt5->coarse_cfo, rpt5->coarse_cfo_msb, + rpt5->avg_cfo_msb, rpt5->evm_hdr); + pr_debug("[20] Evm_pld=%d\n",rpt5->evm_pld); + #endif + } else { + pr_debug("[0] Pkt_cnt=%d, Channel_msb=%d, Pwdb_a=%d, Gain_a=%d, TRSW=%d, AGC_table_b=%d, AGC_table_c=%d,\n", + rpt0->pkt_cnt, rpt0->channel_msb, rpt0->pwdb_a, + rpt0->gain_a, rpt0->trsw, rpt0->agc_table_b, + rpt0->agc_table_c); + pr_debug("[4] Path_Sel_o=%d, Gnt_BT_keep_cnt=%d, HW_AntSW_occur_keep_cck=%d,\n Band=%d, Channel=%d, AGC_table_a=%d, l_RXSC=%d, AGC_table_d=%d\n", + rpt0->path_sel_o, rpt0->gnt_bt_keep_cck, + rpt0->hw_antsw_occur_keep_cck, rpt0->band, + rpt0->channel, rpt0->agc_table_a, rpt0->l_rxsc, + rpt0->agc_table_d); + pr_debug("[8] AntIdx={%d, %d, %d, %d}, Length=%d\n", + rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b, + rpt0->antidx_a, rpt0->length); + pr_debug("[12] MF_off=%d, SQloss=%d, lockbit=%d, raterr=%d, rxrate=%d, lna_h_a=%d, CCK_BB_power_a=%d, lna_l_a=%d, vga_a=%d, sq=%d\n", + rpt0->mf_off, rpt0->sqloss, rpt0->lockbit, + rpt0->raterr, rpt0->rxrate, rpt0->lna_h_a, + rpt0->bb_power_a, rpt0->lna_l_a, rpt0->vga_a, + rpt0->signal_quality); + pr_debug("[16] Gain_b=%d, lna_h_b=%d, CCK_BB_power_b=%d, lna_l_b=%d, vga_b=%d, Pwdb_b=%d\n", + rpt0->gain_b, rpt0->lna_h_b, rpt0->bb_power_b, + rpt0->lna_l_b, rpt0->vga_b, rpt0->pwdb_b); + pr_debug("[20] Gain_c=%d, lna_h_c=%d, CCK_BB_power_c=%d, lna_l_c=%d, vga_c=%d, Pwdb_c=%d\n", + rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c, + rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c); + pr_debug("[24] Gain_d=%d, lna_h_d=%d, CCK_BB_power_d=%d, lna_l_d=%d, vga_d=%d, Pwdb_d=%d\n", + rpt0->gain_c, rpt0->lna_h_c, rpt0->bb_power_c, + rpt0->lna_l_c, rpt0->vga_c, rpt0->pwdb_c); + } + } else if (phy_status_page_num == 1) { + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_pri_msb=%d, Pkt_cnt=%d,\n", + rpt1->pwdb_c, rpt1->pwdb_b, rpt1->pwdb_a, + rpt1->channel_pri_msb, rpt1->pkt_cnt); + pr_debug("[4] BF: %d, stbc=%d, ldpc=%d, gnt_bt=%d, band=%d, Ch_pri_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb[D]=%d\n", + rpt1->beamformed, rpt1->stbc, rpt1->ldpc, rpt1->gnt_bt, + rpt1->band, rpt1->channel_pri_lsb, rpt1->ht_rxsc, + rpt1->l_rxsc, rpt1->pwdb_d); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Channel_sec[msb,lsb]={%d, %d}\n", + rpt1->antidx_d, rpt1->antidx_c, + rpt1->antidx_b, rpt1->antidx_a, + rpt1->hw_antsw_occur_d, rpt1->hw_antsw_occur_c, + rpt1->hw_antsw_occur_b, rpt1->hw_antsw_occur_a, + rpt1->channel_sec_msb, rpt1->channel_sec_lsb); + pr_debug("[12] GID=%d, PAID[msb,lsb]={%d,%d}\n", + rpt1->gid, rpt1->paid_msb, rpt1->paid); + pr_debug("[16] RX_EVM[D:A]={%d, %d, %d, %d}\n", + rpt1->rxevm[3], rpt1->rxevm[2], + rpt1->rxevm[1], rpt1->rxevm[0]); + pr_debug("[20] CFO_tail[D:A]={%d, %d, %d, %d}\n", + rpt1->cfo_tail[3], rpt1->cfo_tail[2], + rpt1->cfo_tail[1], rpt1->cfo_tail[0]); + pr_debug("[24] RX_SNR[D:A]={%d, %d, %d, %d}\n\n", + rpt1->rxsnr[3], rpt1->rxsnr[2], + rpt1->rxsnr[1], rpt1->rxsnr[0]); + } else if (phy_status_page_num == 2 || phy_status_page_num == 3) { + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n", + rpt2->pwdb[2], rpt2->pwdb[1], rpt2->pwdb[0], + rpt2->channel_msb, rpt2->pkt_cnt); + pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, Gnt_BT=%d, band=%d, CH_lsb=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n", + rpt2->beamformed, rpt2->stbc, rpt2->ldpc, rpt2->gnt_bt, + rpt2->band, rpt2->channel_lsb, + rpt2->ht_rxsc, rpt2->l_rxsc, rpt2->pwdb[3]); + pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, pwed_th=%d, shift_l_map=%d\n", + rpt2->agc_table_d, rpt2->agc_table_c, + rpt2->agc_table_b, rpt2->agc_table_a, + rpt2->pwed_th, rpt2->shift_l_map); + pr_debug("[12] AvgNoisePowerdB=%d, mp_gain_c[msb, lsb]={%d, %d}, mp_gain_b[msb, lsb]={%d, %d}, mp_gain_a=%d, cnt_cca2agc_rdy=%d\n", + rpt2->avg_noise_pwr_lsb, rpt2->mp_gain_c_msb, + rpt2->mp_gain_c_lsb, rpt2->mp_gain_b_msb, + rpt2->mp_gain_b_lsb, rpt2->mp_gain_a, + rpt2->cnt_cca2agc_rdy); + pr_debug("[16] HT AAGC gain[B:A]={%d, %d}, AAGC step[D:A]={%d, %d, %d, %d}, IsFreqSelectFadimg=%d, mp_gain_d=%d\n", + rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0], + rpt2->aagc_step_d, rpt2->aagc_step_c, + rpt2->aagc_step_b, rpt2->aagc_step_a, + rpt2->is_freq_select_fading, rpt2->mp_gain_d); + pr_debug("[20] DAGC gain ant[B:A]={%d, %d}, HT AAGC gain[D:C]={%d, %d}\n", + rpt2->dagc_gain[1], rpt2->dagc_gain[0], + rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2]); + pr_debug("[24] AvgNoisePwerdB=%d, syn_count[msb, lsb]={%d, %d}, counter=%d, DAGC gain ant[D:C]={%d, %d}\n", + rpt2->avg_noise_pwr_msb, rpt2->syn_count_msb, + rpt2->syn_count_lsb, rpt2->counter, + rpt2->dagc_gain[3], rpt2->dagc_gain[2]); + } else if (phy_status_page_num == 4) { /*type 4*/ + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n", + rpt3->pwdb[2], rpt3->pwdb[1], rpt3->pwdb[0], + rpt3->channel_msb, rpt3->pkt_cnt); + pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n", + rpt3->beamformed, rpt3->stbc, rpt3->ldpc, rpt3->gnt_bt, + rpt3->band, rpt3->channel_lsb, rpt3->ht_rxsc, + rpt3->l_rxsc, rpt3->pwdb[3]); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}, Training_done[D:A]={%d, %d, %d, %d},\n BadToneCnt_CN_excess_0=%d, BadToneCnt_min_eign_0=%d\n", + rpt3->antidx_d, rpt3->antidx_c, + rpt3->antidx_b, rpt3->antidx_a, + rpt3->hw_antsw_occur_d, rpt3->hw_antsw_occur_c, + rpt3->hw_antsw_occur_b, rpt3->hw_antsw_occur_a, + rpt3->training_done_d, rpt3->training_done_c, + rpt3->training_done_b, rpt3->training_done_a, + rpt3->bad_tone_cnt_cn_excess_0, + rpt3->bad_tone_cnt_min_eign_0); + pr_debug("[12] avg_cond_num_1=%d, avg_cond_num_0=%d, bad_tone_cnt_cn_excess_1=%d,\n bad_tone_cnt_min_eign_1=%d, Tx_pkt_cnt=%d\n", + ((rpt3->avg_cond_num_1_msb << 1) | + rpt3->avg_cond_num_1_lsb), + rpt3->avg_cond_num_0, rpt3->bad_tone_cnt_cn_excess_1, + rpt3->bad_tone_cnt_min_eign_1, rpt3->tx_pkt_cnt); + pr_debug("[16] Stream RXEVM[D:A]={%d, %d, %d, %d}\n", + rpt3->rxevm[3], rpt3->rxevm[2], + rpt3->rxevm[1], rpt3->rxevm[0]); + pr_debug("[20] Eigenvalue[D:A]={%d, %d, %d, %d}\n", + rpt3->eigenvalue[3], rpt3->eigenvalue[2], + rpt3->eigenvalue[1], rpt3->eigenvalue[0]); + pr_debug("[24] RX SNR[D:A]={%d, %d, %d, %d}\n", + rpt3->rxsnr[3], rpt3->rxsnr[2], + rpt3->rxsnr[1], rpt3->rxsnr[0]); + } else if (phy_status_page_num == 5) { /*type 5*/ + pr_debug("[0] pwdb[C:A]={%d, %d, %d}, Channel_mdb=%d, Pkt_cnt=%d\n", + rpt4->pwdb[2], rpt4->pwdb[1], rpt4->pwdb[0], + rpt4->channel_msb, rpt4->pkt_cnt); + pr_debug("[4] BF=%d, STBC=%d, LDPC=%d, GNT_BT=%d, band=%d, CH_pri=%d, rxsc[ht, l]={%d, %d}, pwdb_D=%d\n", + rpt4->beamformed, rpt4->stbc, rpt4->ldpc, rpt4->gnt_bt, + rpt4->band, rpt4->channel_lsb, rpt4->ht_rxsc, + rpt4->l_rxsc, rpt4->pwdb[3]); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, HW_AntSW_occur[D:A]={%d, %d, %d, %d}\n", + rpt4->antidx_d, rpt4->antidx_c, + rpt4->antidx_b, rpt4->antidx_a, + rpt4->hw_antsw_occur_d, rpt4->hw_antsw_occur_c, + rpt4->hw_antsw_occur_b, rpt4->hw_antsw_occur_a); + pr_debug("[12] Inf_posD[1,0]={%d, %d}, Inf_posC[1,0]={%d, %d}, Inf_posB[1,0]={%d, %d}, Inf_posA[1,0]={%d, %d}, Tx_pkt_cnt=%d\n", + rpt4->inf_pos_1_D_flg, rpt4->inf_pos_0_D_flg, + rpt4->inf_pos_1_C_flg, rpt4->inf_pos_0_C_flg, + rpt4->inf_pos_1_B_flg, rpt4->inf_pos_0_B_flg, + rpt4->inf_pos_1_A_flg, rpt4->inf_pos_0_A_flg, + rpt4->tx_pkt_cnt); + pr_debug("[16] Inf_pos_B[1,0]={%d, %d}, Inf_pos_A[1,0]={%d, %d}\n", + rpt4->inf_pos_1_b, rpt4->inf_pos_0_b, + rpt4->inf_pos_1_a, rpt4->inf_pos_0_a); + pr_debug("[20] Inf_pos_D[1,0]={%d, %d}, Inf_pos_C[1,0]={%d, %d}\n", + rpt4->inf_pos_1_d, rpt4->inf_pos_0_d, + rpt4->inf_pos_1_c, rpt4->inf_pos_0_c); + } +} + +void phydm_reset_phy_info_jgr3(struct dm_struct *phydm, + struct phydm_phyinfo_struct *phy_info) +{ + u8 i; + + phy_info->rx_pwdb_all = 0; + phy_info->signal_quality = 0; + phy_info->band_width = 0; + phy_info->rx_count = 0; + phy_info->rx_power = -110; + phy_info->recv_signal_power = -110; + phy_info->bt_rx_rssi_percentage = 0; + phy_info->signal_strength = 0; + phy_info->channel = 0; + phy_info->is_mu_packet = 0; + phy_info->is_beamformed = 0; + phy_info->rxsc = 0; + + for (i = 0; i < 4; i++) { + phy_info->rx_mimo_signal_strength[i] = 0; + phy_info->rx_mimo_signal_quality[i] = 0; + phy_info->rx_mimo_evm_dbm[i] = 0; + phy_info->cfo_short[i] = 0; + phy_info->cfo_tail[i] = 0; + phy_info->rx_pwr[i] = -110; + phy_info->rx_snr[i] = 0; + } +} + +#if 0 +void phydm_per_path_info_3rd(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail, + s8 rx_snr, struct phydm_phyinfo_struct *phy_info) +{ + u8 evm_dbm = 0; + u8 evm_percentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + evm_dbm = (rx_evm == -128) ? 0 : ((u8)(0 - rx_evm) >> 1); + evm_percentage = (evm_dbm >= 34) ? 100 : evm_dbm * 3; + + phy_info->rx_pwr[rx_path] = pwr; + + /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/ + phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1; + phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; + phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr); + phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; + phy_info->rx_snr[rx_path] = rx_snr >> 1; +} + +void phydm_common_phy_info_jgr3(s8 rx_power, u8 channel, boolean is_beamformed, + boolean is_mu_packet, u8 bandwidth, + u8 signal_quality, u8 rxsc, + struct phydm_phyinfo_struct *phy_info) +{ + phy_info->rx_power = rx_power; /* RSSI in dB */ + phy_info->recv_signal_power = rx_power; /* RSSI in dB */ + phy_info->channel = channel; /* @channel number */ + phy_info->is_beamformed = is_beamformed; /* @apply BF */ + phy_info->is_mu_packet = is_mu_packet; /* @MU packet */ + phy_info->rxsc = rxsc; + + phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power); /*percentage */ + phy_info->signal_quality = signal_quality; /* signal quality */ + phy_info->band_width = bandwidth; /* @bandwidth */ +} +#endif + +void phydm_get_physts_0_jgr3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 0 is used for cck packet */ + struct phy_sts_rpt_jgr3_type0 *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + u8 sq = 0, i, rx_cnt = 0; + s8 rx_power[4], pwdb; + s8 rx_pwr_db_max = -120; + + phy_sts = (struct phy_sts_rpt_jgr3_type0 *)phy_status_inf; + + #if (RTL8197G_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197G) { + if (dm->rx_ant_status == BB_PATH_B) { + phy_sts->pwdb_b = phy_sts->pwdb_a; + phy_sts->gain_b = phy_sts->gain_a; + phy_sts->pwdb_a = 0; + phy_sts->gain_a = 0; + } + } + #endif + + rx_power[0] = phy_sts->pwdb_a; + rx_power[1] = phy_sts->pwdb_b; + rx_power[2] = phy_sts->pwdb_c; + rx_power[3] = phy_sts->pwdb_d; + + #if (RTL8822C_SUPPORT || RTL8197G_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8197G)) { + struct phydm_physts *physts_table = &dm->dm_physts_table; + if (phy_sts->gain_a < physts_table->cck_gi_l_bnd) + rx_power[0] += ((physts_table->cck_gi_l_bnd - + phy_sts->gain_a) << 1); + else if (phy_sts->gain_a > physts_table->cck_gi_u_bnd) + rx_power[0] -= ((phy_sts->gain_a - + physts_table->cck_gi_u_bnd) << 1); + + if (phy_sts->gain_b < physts_table->cck_gi_l_bnd) + rx_power[1] += ((physts_table->cck_gi_l_bnd - + phy_sts->gain_b) << 1); + else if (phy_sts->gain_b > physts_table->cck_gi_u_bnd) + rx_power[1] -= ((phy_sts->gain_b - + physts_table->cck_gi_u_bnd) << 1); + } + #endif + + /* @Update per-path information */ + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if ((dm->rx_ant_status & BIT(i)) == 0) + continue; + + rx_cnt++; /* @check the number of the ant */ + + if (rx_cnt > dm->num_rf_path) + break; + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = rx_power[i]; + + /* @Setting the RX power: agc_idx -110 dBm*/ + pwdb = rx_power[i] - 110; + + phy_info->rx_pwr[i] = pwdb; + phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb); + + /* search maximum pwdb */ + if (pwdb > rx_pwr_db_max) + rx_pwr_db_max = pwdb; + } + + /* @Calculate Signal Quality*/ + if (phy_sts->signal_quality >= 64) { + sq = 0; + } else if (phy_sts->signal_quality <= 20) { + sq = 100; + } else { + /* @mapping to 2~99% */ + sq = 64 - phy_sts->signal_quality; + sq = ((sq << 3) + sq) >> 2; + } + + /* @Modify CCK PWDB if old AGC */ + if (!dm->cck_new_agc) { + u8 lna_idx[4], vga_idx[4]; + + lna_idx[0] = ((phy_sts->lna_h_a << 3) | phy_sts->lna_l_a); + vga_idx[0] = phy_sts->vga_a; + lna_idx[1] = ((phy_sts->lna_h_b << 3) | phy_sts->lna_l_b); + vga_idx[1] = phy_sts->vga_b; + lna_idx[2] = ((phy_sts->lna_h_c << 3) | phy_sts->lna_l_c); + vga_idx[2] = phy_sts->vga_c; + lna_idx[3] = ((phy_sts->lna_h_d << 3) | phy_sts->lna_l_d); + vga_idx[3] = phy_sts->vga_d; + } + + /*@CCK no STBC and LDPC*/ + dbg_i->is_ldpc_pkt = false; + dbg_i->is_stbc_pkt = false; + + /*cck channel has hw bug, [WLANBB-1429]*/ + phy_info->channel = 0; + phy_info->rx_power = rx_pwr_db_max; + phy_info->recv_signal_power = rx_pwr_db_max; + phy_info->is_beamformed = false; + phy_info->is_mu_packet = false; + phy_info->rxsc = phy_sts->l_rxsc; + phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max); + phy_info->signal_quality = sq; + phy_info->band_width = CHANNEL_WIDTH_20; + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; + #endif +} + +void phydm_get_physts_1_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_sts_rpt_jgr3_type1 *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + s8 evm = 0; + u8 i; + s8 sq = 0; + + phy_sts = (struct phy_sts_rpt_jgr3_type1 *)phy_status_inf; + + /* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */ + + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if ((dm->rx_ant_status & BIT(i)) == 0) + continue; + + evm = phy_sts->rxevm[i]; + evm = (evm == -128) ? 0 : ((0 - evm) >> 1); + sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/ + + phy_info->rx_mimo_evm_dbm[i] = (u8)evm; + phy_info->rx_mimo_signal_quality[i] = sq; + phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1; + /*@CFO(kHz) = CFO_tail*312.5(kHz)/2^7 ~= CFO tail * 5/2 (kHz)*/ + phy_info->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1; + dbg_i->cfo_tail[i] = (phy_sts->cfo_tail[i] * 5) >> 1; + } + phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0]; + + if (phy_sts->gid != 0 && phy_sts->gid != 63) { + phy_info->is_mu_packet = true; + dbg_i->num_qry_mu_pkt++; + } else { + phy_info->is_mu_packet = false; + } + + phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss); + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; +#endif +} + +void phydm_get_physts_2_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 2 & 3 is used for ofdm packet */ + struct phy_sts_rpt_jgr3_type2_3 *phy_sts = NULL; +} + +void phydm_get_physts_4_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_sts_rpt_jgr3_type4 *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + s8 evm = 0; + u8 i; + s8 sq = 0; + + phy_sts = (struct phy_sts_rpt_jgr3_type4 *)phy_status_inf; + + /* SNR: S(8,1), EVM: S(8,1), CFO: S(8,7) */ + + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if ((dm->rx_ant_status & BIT(i)) == 0) + continue; + + evm = phy_sts->rxevm[i]; + evm = (evm == -128) ? 0 : ((0 - evm) >> 1); + sq = (evm >= 34) ? 100 : evm * 3; /* @Convert EVM to 0~100%*/ + + phy_info->rx_mimo_evm_dbm[i] = (u8)evm; + phy_info->rx_mimo_signal_quality[i] = sq; + phy_info->rx_snr[i] = phy_sts->rxsnr[i] >> 1; + } + phy_info->signal_quality = phy_info->rx_mimo_signal_quality[0]; +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; +#endif + odm_move_memory(dm, dbg_i->eigen_val, phy_sts->eigenvalue, 4); + dbg_i->condition_num_seg0 = phy_sts->avg_cond_num_0; +} + +void phydm_get_physts_5_others_jgr3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_sts_rpt_jgr3_type5 *phy_sts = NULL; + +} +#if (RTL8723F_SUPPORT) +void phydm_get_physts_6_jgr3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 0 is used for cck packet */ + struct phy_sts_rpt_jgr3_type6 *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + u8 sq = 0, i, rx_cnt = 0; + s8 rx_power[4], pwdb; + s8 rx_pwr_db_max = -120; + u8 evm = 0; + phy_sts = (struct phy_sts_rpt_jgr3_type6 *)phy_status_inf; + /* judy_add_8723F_0512 */ + /* rssi S(11,3) */ + rx_power[0] = (s8)((phy_sts->rssi_msb << 5) + (phy_sts->rssi >> 3)); + /* @Update per-path information */ + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if ((dm->rx_ant_status & BIT(i)) == 0) + continue; + + rx_cnt++; /* @check the number of the ant */ + + if (rx_cnt > dm->num_rf_path) + break; + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = rx_power[i]+110; + + /* @Setting the RX power: agc_idx dBm*/ + pwdb = rx_power[i]; + + phy_info->rx_pwr[i] = pwdb; + phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb); + + /* search maximum pwdb */ + if (pwdb > rx_pwr_db_max) + rx_pwr_db_max = pwdb; + } + + /* @Calculate EVM U(8,2)*/ + evm = phy_sts->evm_pld >> 2; + if (pktinfo->data_rate > ODM_RATE2M) + phy_info->rx_cck_evm = (u8)(evm - 10);/* @5_5M/11M*/ + else + phy_info->rx_cck_evm = (u8)(evm - 12);/* @1M/2M*/ + + sq = (phy_info->rx_cck_evm >= 34) ? 100 : phy_info->rx_cck_evm * 3; + phy_info->signal_quality = sq; + /*@CCK no STBC and LDPC*/ + dbg_i->is_ldpc_pkt = false; + dbg_i->is_stbc_pkt = false; + + /*cck channel has hw bug, [WLANBB-1429]*/ + phy_info->channel = 0; + phy_info->rx_power = rx_pwr_db_max; + phy_info->recv_signal_power = rx_pwr_db_max; + phy_info->is_beamformed = false; + phy_info->is_mu_packet = false; + phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max); + phy_info->band_width = CHANNEL_WIDTH_20; + + //phydm_parsing_cfo(dm, pktinfo, phy_sts->avg_cfo, pktinfo->rate_ss); + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = 0; + dm->dm_fat_table.antsel_rx_keep_2 = 0; + dm->dm_fat_table.antsel_rx_keep_3 = 0; + #endif +} +#endif +void phydm_get_physts_ofdm_cmn_jgr3(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_sts_rpt_jgr3_ofdm_cmn *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + s8 rx_pwr_db_max = -120; + s8 pwdb = 0; + u8 i, rx_cnt = 0; + + phy_sts = (struct phy_sts_rpt_jgr3_ofdm_cmn *)phy_status_inf; + + /* Parsing Offset0 & 4*/ + for (i = RF_PATH_A; i < dm->num_rf_path; i++) { + if ((dm->rx_ant_status & BIT(i)) == 0) + continue; + + rx_cnt++; /* @check the number of the ant */ + + pwdb = (s8)phy_sts->pwdb[i] - 110; /*@dB*/ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->pwdb[i]; + + /* search maximum pwdb */ + if (pwdb > rx_pwr_db_max) + rx_pwr_db_max = pwdb; + + phy_info->rx_pwr[i] = pwdb; + phy_info->rx_mimo_signal_strength[i] = phydm_pw_2_percent(pwdb); + } + + phy_info->rx_count = (rx_cnt > 0) ? rx_cnt - 1 : 0; /*from 1~4 to 0~3 */ + phy_info->rx_power = rx_pwr_db_max; + phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_pwr_db_max); + phy_info->recv_signal_power = rx_pwr_db_max; + phy_info->channel = phy_sts->channel_lsb; + phy_info->is_beamformed = (boolean)phy_sts->beamformed; + phy_info->rxsc = (PHYDM_IS_LEGACY_RATE(pktinfo->data_rate)) ? + phy_sts->l_rxsc : phy_sts->ht_rxsc; + phy_info->band_width = phydm_rxsc_2_bw(dm, phy_info->rxsc); + + dbg_i->is_ldpc_pkt = phy_sts->ldpc; + dbg_i->is_stbc_pkt = phy_sts->stbc; + dbg_i->num_qry_bf_pkt += phy_sts->beamformed; +} + +void phydm_process_dm_rssi_jgr3(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo) +{ + struct cmn_sta_info *sta = NULL; + struct rssi_info *rssi_t = NULL; + u8 rssi_tmp = 0; + u64 rssi_linear = 0; + s16 rssi_db = 0; + u8 i = 0; + u8 rx_count = 0; + + #if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT)) + struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table; + #endif + + /*@[Step4]*/ + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) + return; + + if (!pktinfo->is_packet_match_bssid) /*@data frame only*/ + return; + + if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon)) + return; + + if (pktinfo->is_packet_beacon) { + dm->phy_dbg_info.num_qry_beacon_pkt++; + dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate; + } + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + if (dm->support_ability & ODM_BB_ANT_DIV) + odm_process_rssi_for_ant_div(dm, phy_info, pktinfo); + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + phydm_rx_rate_for_antdiv(dm, pktinfo); + #endif + + #if (defined(CONFIG_PATH_DIVERSITY)) + if (dm->support_ability & ODM_BB_PATH_DIV) + phydm_process_rssi_for_path_div(dm, phy_info, pktinfo); + #endif + + #if (defined(PHYDM_CCK_RX_PATHDIV_SUPPORT)) + if (cckrx_t->en_cck_rx_pathdiv) + phydm_process_rssi_for_cck_rx_pathdiv(dm, phy_info, pktinfo); + #endif + + rssi_t = &sta->rssi_stat; + + for (i = 0; i < dm->num_rf_path; i++) { + rssi_tmp = phy_info->rx_mimo_signal_strength[i]; + if (rssi_tmp != 0) { + rx_count++; + rssi_linear += phydm_db_2_linear(rssi_tmp); + } + } + /* @Rounding and removing fractional bits */ + rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; + + switch (rx_count) { + case 2: + rssi_linear = DIVIDED_2(rssi_linear); + break; + case 3: + rssi_linear = DIVIDED_3(rssi_linear); + break; + case 4: + rssi_linear = DIVIDED_4(rssi_linear); + break; + } + + rssi_db = (s16)odm_convert_to_db(rssi_linear); + + if (rssi_t->rssi_acc == 0) { + rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA); + rssi_t->rssi = (s8)(rssi_db); + } else { + rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA); + rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA); + } + + if (pktinfo->is_cck_rate) + rssi_t->rssi_cck = (s8)rssi_db; + else + rssi_t->rssi_ofdm = (s8)rssi_db; +} + +void phydm_rx_physts_jgr3(void *dm_void, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 phy_status_type = (*phy_sts & 0xf); + if (dm->support_ic_type & ODM_RTL8723F) { + if (pktinfo->data_rate <= ODM_RATE11M) + phy_status_type = 6; + } + /*@[Step 2]*/ + /*phydm_reset_phy_info_jgr3(dm, phy_info);*/ /* @Memory reset */ + + /* Phy status parsing */ + switch (phy_status_type) { + case 0: /*@CCK*/ + phydm_get_physts_0_jgr3(dm, phy_sts, pktinfo, phy_info); + break; + case 1: + phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info); + phydm_get_physts_1_others_jgr3(dm, phy_sts, pktinfo, phy_info); + break; + case 2: + case 3: + phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info); + phydm_get_physts_2_others_jgr3(dm, phy_sts, pktinfo, phy_info); + break; + case 4: + phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info); + phydm_get_physts_4_others_jgr3(dm, phy_sts, pktinfo, phy_info); + break; + case 5: + phydm_get_physts_ofdm_cmn_jgr3(dm, phy_sts, pktinfo, phy_info); + phydm_get_physts_5_others_jgr3(dm, phy_sts, pktinfo, phy_info); + break; +#if (RTL8723F_SUPPORT) + case 6: + phydm_get_physts_6_jgr3(dm, phy_sts, pktinfo, phy_info); + break; +#endif + default: + break; + } + +#if 0 + PHYDM_DBG(dm, DBG_PHY_STATUS, "RSSI: {%d, %d}\n", + phy_info->rx_mimo_signal_strength[0], + phy_info->rx_mimo_signal_strength[1]); + PHYDM_DBG(dm, DBG_PHY_STATUS, "rxdb: {%d, %d}\n", + phy_info->rx_pwr[0], phy_info->rx_pwr[1]); + PHYDM_DBG(dm, DBG_PHY_STATUS, "EVM: {%d, %d}\n", + phy_info->rx_mimo_evm_dbm[0], phy_info->rx_mimo_evm_dbm[1]); + PHYDM_DBG(dm, DBG_PHY_STATUS, "SQ: {%d, %d}\n", + phy_info->rx_mimo_signal_quality[0], + phy_info->rx_mimo_signal_quality[1]); + PHYDM_DBG(dm, DBG_PHY_STATUS, "SNR: {%d, %d}\n", + phy_info->rx_snr[0], phy_info->rx_snr[1]); + PHYDM_DBG(dm, DBG_PHY_STATUS, "CFO: {%d, %d}\n", + phy_info->cfo_tail[0], phy_info->cfo_tail[1]); + PHYDM_DBG(dm, DBG_PHY_STATUS, + "rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", + phy_info->rx_pwdb_all, phy_info->rx_power, + phy_info->recv_signal_power); + PHYDM_DBG(dm, DBG_PHY_STATUS, "signal_quality = %d\n", + phy_info->signal_quality); + PHYDM_DBG(dm, DBG_PHY_STATUS, + "is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", + phy_info->is_beamformed, phy_info->is_mu_packet, + phy_info->rx_count); + PHYDM_DBG(dm, DBG_PHY_STATUS, + "channel = %d, rxsc = %d, band_width = %d\n", + phy_info->channel, phy_info->rxsc, phy_info->band_width); +#endif + + /*@[Step 1]*/ + phydm_print_phystat_jgr3(dm, phy_sts, pktinfo, phy_info); +} + +#endif + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) +/* @For 8822B only!! need to move to FW finally */ +/*@==============================================*/ + +boolean +phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate, + u8 *p_gid) +{ + u8 data_rate = 0, gid = 0; + boolean is_mu = false; + + data_rate = phydm->phy_dbg_info.num_of_ppdu[ppdu_idx]; + gid = phydm->phy_dbg_info.gid_num[ppdu_idx]; + + if (data_rate & BIT(7)) { + is_mu = true; + data_rate = data_rate & ~(BIT(7)); + } else { + is_mu = false; + } + + *p_data_rate = data_rate; + *p_gid = gid; + + return is_mu; +} + +void phydm_print_phy_sts_jgr2(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_sts_rpt_jgr2_type0 *rpt0 = NULL; + struct phy_sts_rpt_jgr2_type1 *rpt = NULL; + struct phy_sts_rpt_jgr2_type2 *rpt2 = NULL; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + u8 phy_status_page_num = (*phy_status_inf & 0xf); + u32 phy_status[PHY_STATUS_JRGUAR2_DW_LEN] = {0}; + u8 i; + u32 size = PHY_STATUS_JRGUAR2_DW_LEN << 2; + + rpt0 = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf; + rpt = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf; + rpt2 = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf; + + odm_move_memory(dm, phy_status, phy_status_inf, size); + + if (!(dm->debug_components & DBG_PHY_STATUS)) + return; + + if (dbg->show_phy_sts_all_pkt == 0) { + if (!pktinfo->is_packet_match_bssid) + return; + } + + dbg->show_phy_sts_cnt++; + #if 0 + dbg_print("cnt=%d, max=%d\n", + dbg->show_phy_sts_cnt, dbg->show_phy_sts_max_cnt); + #endif + + if (dbg->show_phy_sts_max_cnt != SHOW_PHY_STATUS_UNLIMITED) { + if (dbg->show_phy_sts_cnt > dbg->show_phy_sts_max_cnt) + return; + } + + pr_debug("Phy Status Rpt: OFDM_%d\n", phy_status_page_num); + pr_debug("StaID=%d, RxRate = 0x%x match_bssid=%d\n", + pktinfo->station_id, pktinfo->data_rate, + pktinfo->is_packet_match_bssid); + + for (i = 0; i < PHY_STATUS_JRGUAR2_DW_LEN; i++) + pr_debug("Offset[%d:%d] = 0x%x\n", + ((4 * i) + 3), (4 * i), phy_status[i]); + + if (phy_status_page_num == 0) { + pr_debug("[0] TRSW=%d, MP_gain_idx=%d, pwdb=%d\n", + rpt0->trsw, rpt0->gain, rpt0->pwdb); + pr_debug("[4] band=%d, CH=%d, agc_table = %d, rxsc = %d\n", + rpt0->band, rpt0->channel, + rpt0->agc_table, rpt0->rxsc); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n", + rpt0->antidx_d, rpt0->antidx_c, rpt0->antidx_b, + rpt0->antidx_a, rpt0->length); + pr_debug("[12] lna_h=%d, bb_pwr=%d, lna_l=%d, vga=%d, sq=%d\n", + rpt0->lna_h, rpt0->bb_power, rpt0->lna_l, + rpt0->vga, rpt0->signal_quality); + + } else if (phy_status_page_num == 1) { + pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n", + rpt->pwdb[3], rpt->pwdb[2], + rpt->pwdb[1], rpt->pwdb[0]); + pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht, l]={%d, %d}\n", + rpt->beamformed, rpt->ldpc, rpt->stbc, rpt->gnt_bt, + rpt->hw_antsw_occu, rpt->band, rpt->channel, + rpt->ht_rxsc, rpt->l_rxsc); + pr_debug("[8] AntIdx[D:A]={%d, %d, %d, %d}, LSIG_len=%d\n", + rpt->antidx_d, rpt->antidx_c, rpt->antidx_b, + rpt->antidx_a, rpt->lsig_length); + pr_debug("[12] rf_mode=%d, NBI=%d, Intf_pos=%d, GID=%d, PAID=%d\n", + rpt->rf_mode, rpt->nb_intf_flag, + (rpt->intf_pos + (rpt->intf_pos_msb << 8)), rpt->gid, + (rpt->paid + (rpt->paid_msb << 8))); + pr_debug("[16] EVM[D:A]={%d, %d, %d, %d}\n", + rpt->rxevm[3], rpt->rxevm[2], + rpt->rxevm[1], rpt->rxevm[0]); + pr_debug("[20] CFO[D:A]={%d, %d, %d, %d}\n", + rpt->cfo_tail[3], rpt->cfo_tail[2], rpt->cfo_tail[1], + rpt->cfo_tail[0]); + pr_debug("[24] SNR[D:A]={%d, %d, %d, %d}\n\n", + rpt->rxsnr[3], rpt->rxsnr[2], rpt->rxsnr[1], + rpt->rxsnr[0]); + + } else if (phy_status_page_num == 2) { + pr_debug("[0] pwdb[D:A]={%d, %d, %d, %d}\n", + rpt2->pwdb[3], rpt2->pwdb[2], rpt2->pwdb[1], + rpt2->pwdb[0]); + pr_debug("[4] BF: %d, ldpc=%d, stbc=%d, g_bt=%d, antsw=%d, band=%d, CH=%d, rxsc[ht,l]={%d, %d}\n", + rpt2->beamformed, rpt2->ldpc, rpt2->stbc, rpt2->gnt_bt, + rpt2->hw_antsw_occu, rpt2->band, rpt2->channel, + rpt2->ht_rxsc, rpt2->l_rxsc); + pr_debug("[8] AgcTab[D:A]={%d, %d, %d, %d}, cnt_pw2cca=%d, shift_l_map=%d\n", + rpt2->agc_table_d, rpt2->agc_table_c, + rpt2->agc_table_b, rpt2->agc_table_a, + rpt2->cnt_pw2cca, rpt2->shift_l_map); + pr_debug("[12] (TRSW|Gain)[D:A]={%d %d, %d %d, %d %d, %d %d}, cnt_cca2agc_rdy=%d\n", + rpt2->trsw_d, rpt2->gain_d, rpt2->trsw_c, rpt2->gain_c, + rpt2->trsw_b, rpt2->gain_b, rpt2->trsw_a, + rpt2->gain_a, rpt2->cnt_cca2agc_rdy); + pr_debug("[16] AAGC step[D:A]={%d, %d, %d, %d} HT AAGC gain[D:A]={%d, %d, %d, %d}\n", + rpt2->aagc_step_d, rpt2->aagc_step_c, + rpt2->aagc_step_b, rpt2->aagc_step_a, + rpt2->ht_aagc_gain[3], rpt2->ht_aagc_gain[2], + rpt2->ht_aagc_gain[1], rpt2->ht_aagc_gain[0]); + pr_debug("[20] DAGC gain[D:A]={%d, %d, %d, %d}\n", + rpt2->dagc_gain[3], + rpt2->dagc_gain[2], rpt2->dagc_gain[1], + rpt2->dagc_gain[0]); + pr_debug("[24] syn_cnt: %d, Cnt=%d\n\n", + rpt2->syn_count, rpt2->counter); + } +} + +void phydm_set_per_path_phy_info(u8 rx_path, s8 pwr, s8 rx_evm, s8 cfo_tail, + s8 rx_snr, u8 ant_idx, + struct phydm_phyinfo_struct *phy_info) +{ + u8 evm_dbm = 0; + u8 evm_percentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + if (rx_evm < 0) { + /* @Calculate EVM in dBm */ + evm_dbm = ((u8)(0 - rx_evm) >> 1); + + if (evm_dbm == 64) + evm_dbm = 0; /*@if 1SS rate, evm_dbm [2nd stream] =64*/ + + if (evm_dbm != 0) { + /* @Convert EVM to 0%~100% percentage */ + if (evm_dbm >= 34) + evm_percentage = 100; + else + evm_percentage = (evm_dbm << 1) + (evm_dbm); + } + } + + phy_info->rx_pwr[rx_path] = pwr; + + /*@CFO(kHz) = CFO_tail * 312.5(kHz) / 2^7 ~= CFO tail * 5/2 (kHz)*/ + phy_info->cfo_tail[rx_path] = (cfo_tail * 5) >> 1; + phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; + phy_info->rx_mimo_signal_strength[rx_path] = phydm_pw_2_percent(pwr); + phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; + phy_info->rx_snr[rx_path] = rx_snr >> 1; + phy_info->ant_idx[rx_path] = ant_idx; + +#if 0 + if (!pktinfo->is_packet_match_bssid) + return; + + dbg_print("path (%d)--------\n", rx_path); + dbg_print("rx_pwr = %d, Signal strength = %d\n", + phy_info->rx_pwr[rx_path], + phy_info->rx_mimo_signal_strength[rx_path]); + dbg_print("evm_dbm = %d, Signal quality = %d\n", + phy_info->rx_mimo_evm_dbm[rx_path], + phy_info->rx_mimo_signal_quality[rx_path]); + dbg_print("CFO = %d, SNR = %d\n", + phy_info->cfo_tail[rx_path], phy_info->rx_snr[rx_path]); + +#endif +} + +void phydm_set_common_phy_info(s8 rx_power, u8 channel, boolean is_beamformed, + boolean is_mu_packet, u8 bandwidth, + u8 signal_quality, u8 rxsc, + struct phydm_phyinfo_struct *phy_info) +{ + phy_info->rx_power = rx_power; /* RSSI in dB */ + phy_info->recv_signal_power = rx_power; /* RSSI in dB */ + phy_info->channel = channel; /* @channel number */ + phy_info->is_beamformed = is_beamformed; /* @apply BF */ + phy_info->is_mu_packet = is_mu_packet; /* @MU packet */ + phy_info->rxsc = rxsc; + + /* RSSI in percentage */ + phy_info->rx_pwdb_all = phydm_pw_2_percent(rx_power); + phy_info->signal_quality = signal_quality; /* signal quality */ + phy_info->band_width = bandwidth; /* @bandwidth */ + +#if 0 + if (!pktinfo->is_packet_match_bssid) + return; + + dbg_print("rx_pwdb_all = %d, rx_power = %d, recv_signal_power = %d\n", + phy_info->rx_pwdb_all, phy_info->rx_power, + phy_info->recv_signal_power); + dbg_print("signal_quality = %d\n", phy_info->signal_quality); + dbg_print("is_beamformed = %d, is_mu_packet = %d, rx_count = %d\n", + phy_info->is_beamformed, phy_info->is_mu_packet, + phy_info->rx_count + 1); + dbg_print("channel = %d, rxsc = %d, band_width = %d\n", channel, + rxsc, bandwidth); + +#endif +} + +void phydm_get_phy_sts_type0(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 0 is used for cck packet */ + struct phy_sts_rpt_jgr2_type0 *phy_sts = NULL; + u8 sq = 0; + s8 rx_pow = 0; + u8 lna_idx = 0, vga_idx = 0; + u8 ant_idx; + + phy_sts = (struct phy_sts_rpt_jgr2_type0 *)phy_status_inf; + rx_pow = phy_sts->pwdb - 110; + + /* Fill in per-path antenna index */ + ant_idx = phy_sts->antidx_a; + + if (dm->support_ic_type & ODM_RTL8723D) { + #if (RTL8723D_SUPPORT) + rx_pow = phy_sts->pwdb - 97; + #endif + } + #if (RTL8821C_SUPPORT) + else if (dm->support_ic_type & ODM_RTL8821C) { + if (phy_sts->pwdb >= -57) + rx_pow = phy_sts->pwdb - 100; + else + rx_pow = phy_sts->pwdb - 102; + } + #endif + + if (pktinfo->is_to_self) { + dm->ofdm_agc_idx[0] = phy_sts->pwdb; + dm->ofdm_agc_idx[1] = 0; + dm->ofdm_agc_idx[2] = 0; + dm->ofdm_agc_idx[3] = 0; + } + + /* @Calculate Signal Quality*/ + if (phy_sts->signal_quality >= 64) { + sq = 0; + } else if (phy_sts->signal_quality <= 20) { + sq = 100; + } else { + /* @mapping to 2~99% */ + sq = 64 - phy_sts->signal_quality; + sq = ((sq << 3) + sq) >> 2; + } + + /* @Get RSSI for old CCK AGC */ + if (!dm->cck_new_agc) { + vga_idx = phy_sts->vga; + + if (dm->support_ic_type & ODM_RTL8197F) { + /*@3bit LNA*/ + lna_idx = phy_sts->lna_l; + } else { + /*@4bit LNA*/ + lna_idx = (phy_sts->lna_h << 3) | phy_sts->lna_l; + } + rx_pow = phydm_get_cck_rssi(dm, lna_idx, vga_idx); + } + + /* @Confirm CCK RSSI */ + #if (RTL8197F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8197F) { + u8 bb_pwr_th_l = 5; /* round( 31*0.15 ) */ + u8 bb_pwr_th_h = 27; /* round( 31*0.85 ) */ + + if (phy_sts->bb_power < bb_pwr_th_l || + phy_sts->bb_power > bb_pwr_th_h) + rx_pow = 0; /* @Error RSSI for CCK ; set 100*/ + } + #endif + + /*@CCK no STBC and LDPC*/ + dm->phy_dbg_info.is_ldpc_pkt = false; + dm->phy_dbg_info.is_stbc_pkt = false; + + /* Update Common information */ + phydm_set_common_phy_info(rx_pow, phy_sts->channel, false, + false, CHANNEL_WIDTH_20, sq, + phy_sts->rxsc, phy_info); + /* Update CCK pwdb */ + phydm_set_per_path_phy_info(RF_PATH_A, rx_pow, 0, 0, 0, ant_idx, + phy_info); + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; + #endif +} + +void phydm_get_phy_sts_type1(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + /* type 1 is used for ofdm packet */ + struct phy_sts_rpt_jgr2_type1 *phy_sts = NULL; + struct odm_phy_dbg_info *dbg_i = &dm->phy_dbg_info; + s8 rx_pwr_db = -120; + s8 rx_pwr = 0; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + boolean is_mu; + u8 ant_idx[4]; + + phy_sts = (struct phy_sts_rpt_jgr2_type1 *)phy_status_inf; + + /* Fill in per-path antenna index */ + ant_idx[0] = phy_sts->antidx_a; + ant_idx[1] = phy_sts->antidx_b; + ant_idx[2] = phy_sts->antidx_c; + ant_idx[3] = phy_sts->antidx_d; + + /* Update per-path information */ + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (!(dm->rx_ant_status & BIT(i))) + continue; + rx_count++; + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information + * (RSSI_dB RSSI_percentage EVM SNR CFO sq) + */ + /* @EVM report is reported by stream, not path */ + rx_pwr = phy_sts->pwdb[i] - 110; /* per-path pwdb(dB)*/ + + if (pktinfo->is_to_self) + dm->ofdm_agc_idx[i] = phy_sts->pwdb[i]; + + phydm_set_per_path_phy_info(i, rx_pwr, + phy_sts->rxevm[rx_count - 1], + phy_sts->cfo_tail[i], + phy_sts->rxsnr[i], + ant_idx[i], phy_info); + /* search maximum pwdb */ + if (rx_pwr > rx_pwr_db) + rx_pwr_db = rx_pwr; + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* @Check if MU packet or not */ + if (phy_sts->gid != 0 && phy_sts->gid != 63) { + is_mu = true; + dbg_i->num_qry_mu_pkt++; + } else { + is_mu = false; + } + + /* @count BF packet */ + dbg_i->num_qry_bf_pkt = dbg_i->num_qry_bf_pkt + phy_sts->beamformed; + + /*STBC or LDPC pkt*/ + dbg_i->is_ldpc_pkt = phy_sts->ldpc; + dbg_i->is_stbc_pkt = phy_sts->stbc; + + /* @Check sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; + else + rxsc = phy_sts->ht_rxsc; + + /* @Check RX bandwidth */ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + else + bw = phy_sts->rf_mode; + + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (phy_sts->rf_mode == 0) + bw = CHANNEL_WIDTH_20; + else if ((rxsc == 1) || (rxsc == 2)) + bw = CHANNEL_WIDTH_20; + else + bw = CHANNEL_WIDTH_40; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db, phy_sts->channel, + (boolean)phy_sts->beamformed, is_mu, bw, + phy_info->rx_mimo_signal_quality[0], + rxsc, phy_info); + + phydm_parsing_cfo(dm, pktinfo, phy_sts->cfo_tail, pktinfo->rate_ss); + #ifdef PHYDM_LNA_SAT_CHK_TYPE2 + phydm_parsing_snr(dm, pktinfo, phy_sts->rxsnr); + #endif + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + dm->dm_fat_table.antsel_rx_keep_0 = phy_sts->antidx_a; + dm->dm_fat_table.antsel_rx_keep_1 = phy_sts->antidx_b; + dm->dm_fat_table.antsel_rx_keep_2 = phy_sts->antidx_c; + dm->dm_fat_table.antsel_rx_keep_3 = phy_sts->antidx_d; + #endif +} + +void phydm_get_phy_sts_type2(struct dm_struct *dm, u8 *phy_status_inf, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct phy_sts_rpt_jgr2_type2 *phy_sts = NULL; + s8 rx_pwr_db_max = -120; + s8 rx_pwr = 0; + u8 i, rxsc, bw = CHANNEL_WIDTH_20, rx_count = 0; + + phy_sts = (struct phy_sts_rpt_jgr2_type2 *)phy_status_inf; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + if (!(dm->rx_ant_status & BIT(i))) + continue; + rx_count++; + + if (rx_count > dm->num_rf_path) + break; + + /* Update per-path information*/ + /* RSSI_dB, RSSI_percentage, EVM, SNR, CFO, sq */ + #if (RTL8197F_SUPPORT) + if ((dm->support_ic_type & ODM_RTL8197F) && + phy_sts->pwdb[i] == 0x7f) { /*@97f workaround*/ + + if (i == RF_PATH_A) { + rx_pwr = (phy_sts->gain_a) << 1; + rx_pwr = rx_pwr - 110; + } else if (i == RF_PATH_B) { + rx_pwr = (phy_sts->gain_b) << 1; + rx_pwr = rx_pwr - 110; + } else { + rx_pwr = 0; + } + } else + #endif + rx_pwr = phy_sts->pwdb[i] - 110; /*@dBm*/ + + phydm_set_per_path_phy_info(i, rx_pwr, 0, 0, 0, 0, phy_info); + + if (rx_pwr > rx_pwr_db_max) /* search max pwdb */ + rx_pwr_db_max = rx_pwr; + } + + /* @mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + phy_info->rx_count = rx_count - 1; + + /* @Check RX sub-channel */ + if (pktinfo->data_rate > ODM_RATE11M && + pktinfo->data_rate < ODM_RATEMCS0) + rxsc = phy_sts->l_rxsc; + else + rxsc = phy_sts->ht_rxsc; + + /*STBC or LDPC pkt*/ + dm->phy_dbg_info.is_ldpc_pkt = phy_sts->ldpc; + dm->phy_dbg_info.is_stbc_pkt = phy_sts->stbc; + + /* @Check RX bandwidth */ + /* @BW information of sc=0 is useless, + *because there is no information of RF mode + */ + if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + if (rxsc >= 1 && rxsc <= 8) + bw = CHANNEL_WIDTH_20; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = CHANNEL_WIDTH_40; + else if (rxsc >= 13) + bw = CHANNEL_WIDTH_80; + + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (rxsc == 3) + bw = CHANNEL_WIDTH_40; + else if ((rxsc == 1) || (rxsc == 2)) + bw = CHANNEL_WIDTH_20; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db_max, phy_sts->channel, + (boolean)phy_sts->beamformed, + false, bw, 0, rxsc, phy_info); +} + +void phydm_process_rssi_for_dm_2nd_type(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + struct phydm_perpkt_info_struct *pktinfo + ) +{ + struct cmn_sta_info *sta = NULL; + struct rssi_info *rssi_t = NULL; + u8 rssi_tmp = 0; + u64 rssi_linear = 0; + s16 rssi_db = 0; + u8 i = 0; + + if (pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + sta = dm->phydm_sta_info[pktinfo->station_id]; + + if (!is_sta_active(sta)) + return; + + if (!pktinfo->is_packet_match_bssid) /*@data frame only*/ + return; + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + if (dm->support_ability & ODM_BB_ANT_DIV) + odm_process_rssi_for_ant_div(dm, phy_info, pktinfo); +#endif + +#if (defined(CONFIG_PATH_DIVERSITY)) + if (dm->support_ability & ODM_BB_PATH_DIV) + phydm_process_rssi_for_path_div(dm, phy_info, pktinfo); +#endif + +#ifdef CONFIG_ADAPTIVE_SOML + phydm_rx_qam_for_soml(dm, pktinfo); + phydm_rx_rate_for_soml(dm, pktinfo); +#endif + + if (!(pktinfo->is_packet_to_self) && !(pktinfo->is_packet_beacon)) + return; + + if (pktinfo->is_packet_beacon) { + dm->phy_dbg_info.num_qry_beacon_pkt++; + dm->phy_dbg_info.beacon_phy_rate = pktinfo->data_rate; + } + + rssi_t = &sta->rssi_stat; + + for (i = RF_PATH_A; i < PHYDM_MAX_RF_PATH; i++) { + rssi_tmp = phy_info->rx_mimo_signal_strength[i]; + if (rssi_tmp != 0) + rssi_linear += phydm_db_2_linear(rssi_tmp); + } + /* @Rounding and removing fractional bits */ + rssi_linear = (rssi_linear + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; + + switch (phy_info->rx_count + 1) { + case 2: + rssi_linear = DIVIDED_2(rssi_linear); + break; + case 3: + rssi_linear = DIVIDED_3(rssi_linear); + break; + case 4: + rssi_linear = DIVIDED_4(rssi_linear); + break; + } + + rssi_db = (s16)odm_convert_to_db(rssi_linear); + + if (rssi_t->rssi_acc == 0) { + rssi_t->rssi_acc = (s16)(rssi_db << RSSI_MA); + rssi_t->rssi = (s8)(rssi_db); + } else { + rssi_t->rssi_acc = MA_ACC(rssi_t->rssi_acc, rssi_db, RSSI_MA); + rssi_t->rssi = (s8)GET_MA_VAL(rssi_t->rssi_acc, RSSI_MA); + } + + if (pktinfo->is_cck_rate) + rssi_t->rssi_cck = (s8)rssi_db; + else + rssi_t->rssi_ofdm = (s8)rssi_db; +} + +void phydm_rx_physts_2nd_type(void *dm_void, u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo, + struct phydm_phyinfo_struct *phy_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 page = (*phy_sts & 0xf); + + /* Phy status parsing */ + switch (page) { + case 0: /*@CCK*/ + phydm_get_phy_sts_type0(dm, phy_sts, pktinfo, phy_info); + break; + case 1: + phydm_get_phy_sts_type1(dm, phy_sts, pktinfo, phy_info); + break; + case 2: + phydm_get_phy_sts_type2(dm, phy_sts, pktinfo, phy_info); + break; + default: + break; + } + +#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8195B)) + phydm_print_phy_sts_jgr2(dm, phy_sts, pktinfo, phy_info); +#endif +} + +/*@==============================================*/ +#endif + +boolean odm_phy_status_query(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo) +{ +#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + struct pkt_process_info *pkt_proc = &dm->pkt_proc_struct; + boolean auto_swch_en = dm->pkt_proc_struct.physts_auto_swch_en; +#endif + u8 rate = pktinfo->data_rate; + u8 page = (*phy_sts & 0xf); + + pktinfo->is_cck_rate = PHYDM_IS_CCK_RATE(rate); + pktinfo->rate_ss = phydm_rate_to_num_ss(dm, rate); + dm->rate_ss = pktinfo->rate_ss; /*@For AP EVM SW antenna diversity use*/ + + if (pktinfo->is_cck_rate) + dm->phy_dbg_info.num_qry_phy_status_cck++; + else + dm->phy_dbg_info.num_qry_phy_status_ofdm++; + + /*Reset phy_info*/ + phydm_reset_phy_info(dm, phy_info); + + if (dm->support_ic_type & PHYSTS_3RD_TYPE_IC) { + #ifdef PHYSTS_3RD_TYPE_SUPPORT + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + if (phydm_physts_auto_switch_jgr3(dm, phy_sts, pktinfo)) { + PHYDM_DBG(dm, DBG_PHY_STATUS, "SKIP parsing\n"); + phy_info->physts_rpt_valid = false; + return false; + } + #endif + phydm_rx_physts_jgr3(dm, phy_sts, pktinfo, phy_info); + phydm_process_dm_rssi_jgr3(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & PHYSTS_2ND_TYPE_IC) { + #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT) + phydm_rx_physts_2nd_type(dm, phy_sts, pktinfo, phy_info); + phydm_process_rssi_for_dm_2nd_type(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + #if ODM_IC_11AC_SERIES_SUPPORT + phydm_rx_physts_1st_type(dm, phy_info, phy_sts, pktinfo); + phydm_process_rssi_for_dm(dm, phy_info, pktinfo); + #endif + } else if (dm->support_ic_type & ODM_IC_11N_SERIES) { + #if ODM_IC_11N_SERIES_SUPPORT + phydm_phy_sts_n_parsing(dm, phy_info, phy_sts, pktinfo); + phydm_process_rssi_for_dm(dm, phy_info, pktinfo); + #endif + } + phy_info->signal_strength = phy_info->rx_pwdb_all; + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + phydm_process_signal_strength(dm, phy_info, pktinfo); + #endif + + /*For basic debug message*/ + if (pktinfo->is_packet_match_bssid || *dm->mp_mode) { + dm->curr_station_id = pktinfo->station_id; + dm->rx_rate = rate; + dm->rssi_a = phy_info->rx_mimo_signal_strength[RF_PATH_A]; + dm->rssi_b = phy_info->rx_mimo_signal_strength[RF_PATH_B]; + dm->rssi_c = phy_info->rx_mimo_signal_strength[RF_PATH_C]; + dm->rssi_d = phy_info->rx_mimo_signal_strength[RF_PATH_D]; + + if (rate >= ODM_RATE6M && rate <= ODM_RATE54M) + dm->rxsc_l = (s8)phy_info->rxsc; + else if (phy_info->band_width == CHANNEL_WIDTH_20) + dm->rxsc_20 = (s8)phy_info->rxsc; + else if (phy_info->band_width == CHANNEL_WIDTH_40) + dm->rxsc_40 = (s8)phy_info->rxsc; + else if (phy_info->band_width == CHANNEL_WIDTH_80) + dm->rxsc_80 = (s8)phy_info->rxsc; + + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + if (auto_swch_en && page == 4 && pktinfo->rate_ss > 1) + phydm_avg_condi_num(dm, phy_info, pktinfo); + + if (!auto_swch_en || + (pkt_proc->is_1st_mpdu || PHYDM_IS_LEGACY_RATE(rate))) + #endif + { + phydm_avg_rssi_evm_snr(dm, phy_info, pktinfo); + phydm_rx_statistic_cal(dm, phy_info, phy_sts, pktinfo); + } + } + + phy_info->physts_rpt_valid = true; + return true; +} + +void phydm_rx_phy_status_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct odm_phy_dbg_info *dbg = &dm->phy_dbg_info; + + dbg->show_phy_sts_all_pkt = 0; + dbg->show_phy_sts_max_cnt = 1; + dbg->show_phy_sts_cnt = 0; + + phydm_avg_phystatus_init(dm); + + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + dm->pkt_proc_struct.physts_auto_swch_en = false; + #endif +} + +void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + boolean enable; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + for (i = 0; i < 3; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Page Auto Switching: swh {en} {bitmap(hex)}\n"); + } else if ((strcmp(input[1], "swh") == 0)) { + #ifdef PHYDM_PHYSTAUS_AUTO_SWITCH + PHYDM_SSCANF(input[3], DCMD_HEX, &var[2]); + enable = (boolean)var[1]; + phydm_physts_auto_switch_jgr3_set(dm, enable, (u8)var[2]); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Page Auto Switching: en=%d, bitmap=0x%x\n", + enable, var[2]); + #endif + } + *_used = used; + *_out_len = out_len; +} diff --git a/hal/phydm/phydm_phystatus.h b/hal/phydm/phydm_phystatus.h new file mode 100644 index 0000000..c65b624 --- /dev/null +++ b/hal/phydm/phydm_phystatus.h @@ -0,0 +1,1250 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_PHYSTATUS_H__ +#define __PHYDM_PHYSTATUS_H__ + +/* 2020.07.03 fix cck report bug due to 8723F coding error*/ +#define PHYSTS_VERSION "1.2" + +/*@--------------------------Define ------------------------------------------*/ +#define CCK_RSSI_INIT_COUNT 5 + +#define RA_RSSI_STATE_INIT 0 +#define RA_RSSI_STATE_SEND 1 +#define RA_RSSI_STATE_HOLD 2 + +#if defined(DM_ODM_CE_MAC80211) +#define CFO_HW_RPT_2_KHZ(val) ({ \ + s32 cfo_hw_rpt_2_khz_tmp = (val); \ + (cfo_hw_rpt_2_khz_tmp << 1) + (cfo_hw_rpt_2_khz_tmp >> 1); \ + }) +#else +#define CFO_HW_RPT_2_KHZ(val) ((val << 1) + (val >> 1)) +#endif + +/* @(X* 312.5 Khz)>>7 ~= X*2.5 Khz= (X<<1 + X>>1)Khz */ + +#define IGI_2_RSSI(igi) (igi - 10) + +#define PHY_STATUS_JRGUAR2_DW_LEN 7 /* @7*4 = 28 Byte */ +#define PHY_STATUS_JRGUAR3_DW_LEN 7 /* @7*4 = 28 Byte */ +#define SHOW_PHY_STATUS_UNLIMITED 0 +#define RSSI_MA 4 /*moving average factor for RSSI: 2^4=16 */ + +#define PHYSTS_PATH_NUM 4 + +/*@************************************************************ + * structure and define + ************************************************************/ + +__PACK struct phy_rx_agc_info { +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain : 7, trsw : 1; +#else + u8 trsw : 1, gain : 7; +#endif +}; + +__PACK struct phy_status_rpt_8192cd { + struct phy_rx_agc_info path_agc[2]; + u8 ch_corr[2]; + u8 cck_sig_qual_ofdm_pwdb_all; + u8 cck_agc_rpt_ofdm_cfosho_a; + u8 cck_rpt_b_ofdm_cfosho_b; + u8 rsvd_1;/*@ch_corr_msb;*/ + u8 noise_power_db_msb; + s8 path_cfotail[2]; + u8 pcts_mask[2]; + s8 stream_rxevm[2]; + u8 path_rxsnr[2]; + u8 noise_power_db_lsb; + u8 rsvd_2[3]; + u8 stream_csi[2]; + u8 stream_target_csi[2]; + s8 sig_evm; + u8 rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antsel_rx_keep_2: 1; /*@ex_intf_flg:1;*/ + u8 sgi_en: 1; + u8 rxsc: 2; + u8 idle_long: 1; + u8 r_ant_train_en: 1; + u8 ant_sel_b: 1; + u8 ant_sel: 1; +#else /*@_BIG_ENDIAN_ */ + u8 ant_sel: 1; + u8 ant_sel_b: 1; + u8 r_ant_train_en: 1; + u8 idle_long: 1; + u8 rxsc: 2; + u8 sgi_en: 1; + u8 antsel_rx_keep_2: 1;/*@ex_intf_flg:1;*/ +#endif +}; + +struct phy_status_rpt_8812 { + /* @DWORD 0*/ + u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u8 chl_num_LSB; /*@channel number[7:0]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 chl_num_MSB : 2; /*@channel number[9:8]*/ + u8 sub_chnl : 4; /*sub-channel location[3:0]*/ + u8 r_RFMOD : 2; /*RF mode[1:0]*/ +#else /*@_BIG_ENDIAN_ */ + u8 r_RFMOD : 2; + u8 sub_chnl : 4; + u8 chl_num_MSB : 2; +#endif + + /* @DWORD 1*/ + u8 pwdb_all; /*@CCK signal quality / OFDM pwdb all*/ + s8 cfosho[2]; /*@CCK AGC report and CCK_BB_Power*/ + /*OFDM path-A and path-B short CFO*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 resvd_0 : 6; + u8 bt_RF_ch_MSB : 2; /*@8812A:2'b0 8814A: bt rf channel keep[7:6]*/ +#else /*@_BIG_ENDIAN_*/ + u8 bt_RF_ch_MSB : 2; + u8 resvd_0 : 6; +#endif + +/* @DWORD 2*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 ant_div_sw_a : 1; /*@8812A: ant_div_sw_a 8814A: 1'b0*/ + u8 ant_div_sw_b : 1; /*@8812A: ant_div_sw_b 8814A: 1'b0*/ + u8 bt_RF_ch_LSB : 6; /*@8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ +#else /*@_BIG_ENDIAN_ */ + u8 bt_RF_ch_LSB : 6; + u8 ant_div_sw_b : 1; + u8 ant_div_sw_a : 1; +#endif + s8 cfotail[2]; /*@DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + + /* @DWORD 3*/ + s8 rxevm[2]; /*@DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s8 rxsnr[2]; /*@DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + + /* @DWORD 4*/ + u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/ + u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/ + u8 resvd_1 : 1; /*@1'b0*/ +#else /*@_BIG_ENDIAN_*/ + u8 resvd_1 : 1; + u8 pcts_rpt_valid : 1; + u8 PCTS_MSK_RPT_3 : 6; +#endif + s8 rxevm_cd[2]; /*@8812A: 16'b0*/ + /*@8814A: stream 3 and stream 4 RX EVM*/ + /* @DWORD 5*/ + u8 csi_current[2]; /*@8812A: stream 1 and 2 CSI*/ + /*@8814A: path-C and path-D RX SNR*/ + u8 gain_trsw_cd[2]; /*path-C and path-D {TRSW, gain[6:0] }*/ + + /* @DWORD 6*/ + s8 sigevm; /*signal field EVM*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_antc : 3; /*@8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u8 antidx_antd : 3; /*@8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u8 dpdt_ctrl_keep : 1; /*@8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u8 GNT_BT_keep : 1; /*@8812A: 1'b0 8814A: GNT_BT_keep*/ +#else /*@_BIG_ENDIAN_*/ + u8 GNT_BT_keep : 1; + u8 dpdt_ctrl_keep : 1; + u8 antidx_antd : 3; + u8 antidx_antc : 3; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_anta : 3; /*@antidx_anta[2:0]*/ + u8 antidx_antb : 3; /*@antidx_antb[2:0]*/ + u8 hw_antsw_occur : 2; /*@1'b0*/ +#else /*@_BIG_ENDIAN_*/ + u8 hw_antsw_occur : 2; + u8 antidx_antb : 3; + u8 antidx_anta : 3; +#endif +}; + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) + +__PACK struct phy_sts_rpt_jgr2_type0 { + /* @DW0 */ + u8 page_num; + u8 pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain : 6; + u8 rsvd_0 : 1; + u8 trsw : 1; +#else + u8 trsw : 1; + u8 rsvd_0 : 1; + u8 gain : 6; +#endif + u8 rsvd_1; + + /* @DW1 */ + u8 rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rxsc : 4; + u8 agc_table : 4; +#else + u8 agc_table : 4; + u8 rxsc : 4; +#endif + u8 channel; + u8 band; + + /* @DW2 */ + u16 length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 3; + u8 antidx_b : 3; + u8 rsvd_3 : 2; + u8 antidx_c : 3; + u8 antidx_d : 3; + u8 rsvd_4 : 2; +#else + u8 rsvd_3 : 2; + u8 antidx_b : 3; + u8 antidx_a : 3; + u8 rsvd_4 : 2; + u8 antidx_d : 3; + u8 antidx_c : 3; +#endif + + /* @DW3 */ + u8 signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga : 5; + u8 lna_l : 3; + u8 bb_power : 6; + u8 rsvd_9 : 1; + u8 lna_h : 1; +#else + u8 lna_l : 3; + u8 vga : 5; + u8 lna_h : 1; + u8 rsvd_9 : 1; + u8 bb_power : 6; +#endif + u8 rsvd_5; + + /* @DW4 */ + u32 rsvd_6; + + /* @DW5 */ + u32 rsvd_7; + + /* @DW6 */ + u32 rsvd_8; +}; + +__PACK struct phy_sts_rpt_jgr2_type1 { + /* @DW0 and DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 1; + u8 hw_antsw_occu : 1; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 hw_antsw_occu : 1; + u8 rsvd_0 : 1; + u8 band : 2; +#endif + + /* @DW2 */ + u16 lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 3; + u8 antidx_b : 3; + u8 rsvd_1 : 2; + u8 antidx_c : 3; + u8 antidx_d : 3; + u8 rsvd_2 : 2; +#else + u8 rsvd_1 : 2; + u8 antidx_b : 3; + u8 antidx_a : 3; + u8 rsvd_2 : 2; + u8 antidx_d : 3; + u8 antidx_c : 3; +#endif + + /* @DW3 */ + u8 paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 paid_msb : 1; + u8 gid : 6; + u8 rsvd_3 : 1; +#else + u8 rsvd_3 : 1; + u8 gid : 6; + u8 paid_msb : 1; +#endif + u8 intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 intf_pos_msb : 1; + u8 rsvd_4 : 2; + u8 nb_intf_flag : 1; + u8 rf_mode : 2; + u8 rsvd_5 : 2; +#else + u8 rsvd_5 : 2; + u8 rf_mode : 2; + u8 nb_intf_flag : 1; + u8 rsvd_4 : 2; + u8 intf_pos_msb : 1; +#endif + + /* @DW4 */ + s8 rxevm[4]; /* s(8,1) */ + + /* @DW5 */ + s8 cfo_tail[4]; /* s(8,7) */ + + /* @DW6 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct phy_sts_rpt_jgr2_type2 { + /* @DW0 ane DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 1; + u8 hw_antsw_occu : 1; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 hw_antsw_occu : 1; + u8 rsvd_0 : 1; + u8 band : 2; +#endif + +/* @DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 shift_l_map : 6; + u8 rsvd_1 : 2; +#else + u8 rsvd_1 : 2; + u8 shift_l_map : 6; +#endif + u8 cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a : 4; + u8 agc_table_b : 4; + u8 agc_table_c : 4; + u8 agc_table_d : 4; +#else + u8 agc_table_b : 4; + u8 agc_table_a : 4; + u8 agc_table_d : 4; + u8 agc_table_c : 4; +#endif + + /* @DW3 ~ DW6*/ + u8 cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_a : 6; + u8 rsvd_2 : 1; + u8 trsw_a : 1; + u8 gain_b : 6; + u8 rsvd_3 : 1; + u8 trsw_b : 1; + u8 gain_c : 6; + u8 rsvd_4 : 1; + u8 trsw_c : 1; + u8 gain_d : 6; + u8 rsvd_5 : 1; + u8 trsw_d : 1; + u8 aagc_step_a : 2; + u8 aagc_step_b : 2; + u8 aagc_step_c : 2; + u8 aagc_step_d : 2; +#else + u8 trsw_a : 1; + u8 rsvd_2 : 1; + u8 gain_a : 6; + u8 trsw_b : 1; + u8 rsvd_3 : 1; + u8 gain_b : 6; + u8 trsw_c : 1; + u8 rsvd_4 : 1; + u8 gain_c : 6; + u8 trsw_d : 1; + u8 rsvd_5 : 1; + u8 gain_d : 6; + u8 aagc_step_d : 2; + u8 aagc_step_c : 2; + u8 aagc_step_b : 2; + u8 aagc_step_a : 2; +#endif + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 counter : 6; + u8 rsvd_6 : 2; + u8 syn_count : 5; + u8 rsvd_7 : 3; +#else + u8 rsvd_6 : 2; + u8 counter : 6; + u8 rsvd_7 : 3; + u8 syn_count : 5; +#endif +}; +#endif + +/*@==============================================*/ +#ifdef PHYSTS_3RD_TYPE_SUPPORT +__PACK struct phy_sts_rpt_jgr3_type0 { +/* @DW0 : Offset 0 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb_a; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_a : 6; + u8 rsvd_0 : 1; + u8 trsw : 1; +#else + u8 trsw : 1; + u8 rsvd_0 : 1; + u8 gain_a : 6; +#endif + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_b : 4; + u8 agc_table_c : 4; +#else + u8 agc_table_c : 4; + u8 agc_table_b : 4; +#endif + +/* @DW1 : Offset 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_1 : 4; + u8 agc_table_d : 4; +#else + u8 agc_table_d : 4; + u8 rsvd_1 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 agc_table_a : 4; +#else + u8 agc_table_a : 4; + u8 l_rxsc : 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_2_1 : 1; + u8 hw_antsw_occur_keep_cck : 1; + u8 gnt_bt_keep_cck : 1; + u8 rsvd_2_2 : 1; + u8 path_sel_o : 2; +#else + u8 path_sel_o : 2; + u8 rsvd_2_2 : 1; + u8 gnt_bt_keep_cck : 1; + u8 hw_antsw_occur_keep_cck : 1; + u8 rsvd_2_1 : 1; + u8 band : 2; +#endif + + /* @DW2 : Offset 8 */ + u16 length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif + + /* @DW3 : Offset 12 */ + u8 signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_a : 5; + u8 lna_l_a : 3; +#else + u8 lna_l_a : 3; + u8 vga_a : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_a : 6; + u8 rsvd_3_1 : 1; + u8 lna_h_a : 1; +#else + + u8 lna_h_a : 1; + u8 rsvd_3_1 : 1; + u8 bb_power_a : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rxrate : 2; + u8 raterr : 1; + u8 lockbit : 1; + u8 sqloss : 1; + u8 mf_off : 1; + u8 rsvd_3_2 : 2; +#else + u8 rsvd_3_2 : 2; + u8 mf_off : 1; + u8 sqloss : 1; + u8 lockbit : 1; + u8 raterr : 1; + u8 rxrate : 2; +#endif + + /* @DW4 : Offset 16 */ + u8 pwdb_b; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_b : 5; + u8 lna_l_b : 3; +#else + u8 lna_l_b : 3; + u8 vga_b : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_b : 6; + u8 rsvd_4_1 : 1; + u8 lna_h_b : 1; +#else + u8 lna_h_b : 1; + u8 rsvd_4_1 : 1; + u8 bb_power_b : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_b : 6; + u8 rsvd_4_2 : 2; +#else + u8 rsvd_4_2 : 2; + u8 gain_b : 6; +#endif + + /* @DW5 : Offset 20 */ + u8 pwdb_c; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_c : 5; + u8 lna_l_c : 3; +#else + u8 lna_l_c : 3; + u8 vga_c : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_c : 6; + u8 rsvd_5_1 : 1; + u8 lna_h_c : 1; +#else + u8 lna_h_c : 1; + u8 rsvd_5_1 : 1; + u8 bb_power_c : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_c : 6; + u8 rsvd_5_2 : 2; +#else + u8 rsvd_5_2 : 2; + u8 gain_c : 6; +#endif + + /* @DW6 : Offset 24 */ + u8 pwdb_d; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga_d : 5; + u8 lna_l_d : 3; +#else + u8 lna_l_d : 3; + u8 vga_d : 5; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bb_power_d : 6; + u8 rsvd_6_1 : 1; + u8 lna_h_d : 1; +#else + u8 lna_h_d : 1; + u8 rsvd_6_1 : 1; + u8 bb_power_d : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_d : 6; + u8 rsvd_6_2 : 2; +#else + u8 rsvd_6_2 : 2; + u8 gain_d : 6; +#endif +}; +#if(RTL8723F_SUPPORT) +__PACK struct phy_sts_rpt_jgr3_type6 { + /* judy_add_8723F_0512 */ +/* @DW0 : Offset 0 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 pop_idx : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 pop_idx : 4; +#endif + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a : 4; + u8 rsvd_0 : 4; +#else + u8 rsvd_0 : 4; + u8 agc_table_a : 4; +#endif + u8 rsvd_1 : 8; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 trsw : 1; + u8 hw_antsw_occur_keep_cck : 1; + u8 gnt_bt_keep_cck : 1; + u8 rssi_msb : 3; + u8 rsvd_2 : 2; +#else + u8 rsvd_2 : 2; + u8 rssi_msb : 3; + u8 gnt_bt_keep_cck : 1; + u8 hw_antsw_occur_keep_cck : 1; + u8 trsw : 1; +#endif + +/* @DW1 : Offset 4 */ + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 rsvd_2_1 : 4; +#else + u8 rsvd_2_1 : 4; + u8 antidx_a : 4; +#endif + u8 rsvd_2_2; + u8 mp_gain_idx_a; + +/* @DW2 : Offset 8 */ + u16 rsvd_3_1; + u8 rsvd_4_1; + u8 rssi; + +/* @DW3 : Offset 12 */ + u16 rsvd_4_2; + u8 rsvd_5_1; + u8 avg_cfo; +/* @DW4 : Offset 16 */ + u8 coarse_cfo; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 coarse_cfo_msb : 4; + u8 avg_cfo_msb : 4; +#else + u8 avg_cfo_msb : 4; + u8 coarse_cfo_msb : 4; +#endif + u8 evm_hdr; + u8 evm_pld; +/* @DW5 : Offset 20 */ + u32 rsvd_6_1; + u32 rsvd_7_1; +}; +#endif +__PACK struct phy_sts_rpt_jgr3_type1 { +/* @DW0 : Offset 0 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_pri_msb : 2; +#else + u8 channel_pri_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb_a; + u8 pwdb_b; + u8 pwdb_c; + + /* @DW1 : Offset 4 */ + u8 pwdb_d; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_pri_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 2; + u8 band : 2; +#endif + + /* @DW2 : Offset 8 */ + u8 channel_sec_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 channel_sec_msb : 2; + u8 rsvd_1 : 2; + u8 hw_antsw_occur_a : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_d : 1; +#else + u8 hw_antsw_occur_d : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_a : 1; + u8 rsvd_1 : 2; + u8 channel_sec_msb : 2; + +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif + + /* @DW3 : Offset 12 */ + u8 paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 paid_msb : 1; + u8 gid : 6; + u8 rsvd_3 : 1; +#else + u8 rsvd_3 : 1; + u8 gid : 6; + u8 paid_msb : 1; +#endif + u16 rsvd_4; +#if 0 + /*@ + u8 rsvd_4; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_5: 6; + u8 rf_mode: 2; +#else + u8 rf_mode: 2; + u8 rsvd_5: 6; +#endif +*/ +#endif + /* @DW4 : Offset 16 */ + s8 rxevm[4]; /* s(8,1) */ + + /* @DW5 : Offset 20 */ + s8 cfo_tail[4]; /* s(8,7) */ + + /* @DW6 : Offset 24 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct phy_sts_rpt_jgr3_type2_3 { +/* Type2 is primary channel & type3 is secondary channel */ +/* @DW0 and DW1: Offest 0 and Offset 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 2; + u8 band : 2; +#endif + +/* @DW2 : Offset 8 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 shift_l_map : 6; + u8 rsvd_1 : 2; +#else + u8 rsvd_1 : 2; + u8 shift_l_map : 6; +#endif + s8 pwed_th; /* @dynamic energy threshold S(8,2) */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a : 4; + u8 agc_table_b : 4; +#else + u8 agc_table_b : 4; + u8 agc_table_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_c : 4; + u8 agc_table_d : 4; +#else + u8 agc_table_d : 4; + u8 agc_table_c : 4; +#endif + + /* @DW3 : Offset 12 */ + u8 cnt_cca2agc_rdy; /* Time(ns) = cnt_cca2agc_ready*25 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_a : 6; + u8 mp_gain_b_lsb : 2; +#else + u8 mp_gain_b_lsb : 2; + u8 mp_gain_a : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_b_msb : 4; + u8 mp_gain_c_lsb : 4; +#else + u8 mp_gain_c_lsb : 4; + u8 mp_gain_b_msb : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_c_msb : 2; + u8 avg_noise_pwr_lsb : 4; + u8 rsvd_3 : 2; + /* u8 r_rfmod:2; */ +#else + /* u8 r_rfmod:2; */ + u8 rsvd_3 : 2; + u8 avg_noise_pwr_lsb : 4; + u8 mp_gain_c_msb : 2; +#endif + /* @DW4 ~ 5: offset 16 ~20 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 mp_gain_d : 6; + u8 is_freq_select_fading : 1; + u8 rsvd_2 : 1; +#else + u8 rsvd_2 : 1; + u8 is_freq_select_fading : 1; + u8 mp_gain_d : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 aagc_step_a : 2; + u8 aagc_step_b : 2; + u8 aagc_step_c : 2; + u8 aagc_step_d : 2; +#else + u8 aagc_step_d : 2; + u8 aagc_step_c : 2; + u8 aagc_step_b : 2; + u8 aagc_step_a : 2; +#endif + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 counter : 6; + u8 syn_count_lsb : 2; +#else + u8 syn_count_lsb : 2; + u8 counter : 6; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 syn_count_msb : 3; + u8 avg_noise_pwr_msb : 5; +#else + u8 avg_noise_pwr_msb : 5; + u8 syn_count_msb : 3; +#endif +}; + +__PACK struct phy_sts_rpt_jgr3_type4 { +/* smart antenna */ +/* @DW0 and DW1 : offset 0 and 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 1; + u8 band : 2; +#endif + +/* @DW2 : offset 8 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bad_tone_cnt_min_eign_0 : 4; + u8 bad_tone_cnt_cn_excess_0 : 4; +#else + u8 bad_tone_cnt_cn_excess_0 : 4; + u8 bad_tone_cnt_min_eign_0 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 training_done_a : 1; + u8 training_done_b : 1; + u8 training_done_c : 1; + u8 training_done_d : 1; + u8 hw_antsw_occur_a : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_d : 1; +#else + u8 hw_antsw_occur_d : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_a : 1; + u8 training_done_d : 1; + u8 training_done_c : 1; + u8 training_done_b : 1; + u8 training_done_a : 1; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif +/* @DW3 : offset 12 */ + u8 tx_pkt_cnt; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 bad_tone_cnt_min_eign_1 : 4; + u8 bad_tone_cnt_cn_excess_1 : 4; +#else + u8 bad_tone_cnt_cn_excess_1 : 4; + u8 bad_tone_cnt_min_eign_1 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 avg_cond_num_0 : 7; + u8 avg_cond_num_1_lsb : 1; +#else + u8 avg_cond_num_1_lsb : 1; + u8 avg_cond_num_0 : 7; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 avg_cond_num_1_msb : 6; + u8 rsvd_1 : 2; +#else + u8 rsvd_1 : 2; + u8 avg_cond_num_1_msb : 6; +#endif + + /* @DW4 : offset 16 */ + s8 rxevm[4]; /* s(8,1) */ + + /* @DW5 : offset 20 */ + u8 eigenvalue[4]; /* @eigenvalue or eigenvalue of seg0 (in dB) */ + + /* @DW6 : ofset 24 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +__PACK struct phy_sts_rpt_jgr3_type5 { +/* @Debug */ +/* @DW0 ane DW1 : offset 0 and 4 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; +#else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; +#endif + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; +#else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; +#endif + u8 channel_lsb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; +#else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 2; + u8 band : 2; +#endif + /* @DW2 : offset 8 */ + u8 rsvd_1; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rsvd_2 : 4; + u8 hw_antsw_occur_a : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_d : 1; +#else + u8 hw_antsw_occur_d : 1; + u8 hw_antsw_occur_c : 1; + u8 hw_antsw_occur_b : 1; + u8 hw_antsw_occur_a : 1; + u8 rsvd_2 : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a : 4; + u8 antidx_b : 4; +#else + u8 antidx_b : 4; + u8 antidx_a : 4; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_c : 4; + u8 antidx_d : 4; +#else + u8 antidx_d : 4; + u8 antidx_c : 4; +#endif + /* @DW3 : offset 12 */ + u8 tx_pkt_cnt; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 inf_pos_0_A_flg : 1; + u8 inf_pos_1_A_flg : 1; + u8 inf_pos_0_B_flg : 1; + u8 inf_pos_1_B_flg : 1; + u8 inf_pos_0_C_flg : 1; + u8 inf_pos_1_C_flg : 1; + u8 inf_pos_0_D_flg : 1; + u8 inf_pos_1_D_flg : 1; +#else + u8 inf_pos_1_D_flg : 1; + u8 inf_pos_0_D_flg : 1; + u8 inf_pos_1_C_flg : 1; + u8 inf_pos_0_C_flg : 1; + u8 inf_pos_1_B_flg : 1; + u8 inf_pos_0_B_flg : 1; + u8 inf_pos_1_A_flg : 1; + u8 inf_pos_0_A_flg : 1; +#endif + u8 rsvd_3; + u8 rsvd_4; + /* @DW4 : offset 16 */ + u8 inf_pos_0_a; + u8 inf_pos_1_a; + u8 inf_pos_0_b; + u8 inf_pos_1_b; + /* @DW5 : offset 20 */ + u8 inf_pos_0_c; + u8 inf_pos_1_c; + u8 inf_pos_0_d; + u8 inf_pos_1_d; +}; + +__PACK struct phy_sts_rpt_jgr3_ofdm_cmn { + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 page_num : 4; + u8 pkt_cnt : 2; + u8 channel_msb : 2; + #else + u8 channel_msb : 2; + u8 pkt_cnt : 2; + u8 page_num : 4; + #endif + u8 pwdb[4]; + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc : 4; + u8 ht_rxsc : 4; + #else + u8 ht_rxsc : 4; + u8 l_rxsc : 4; + #endif + u8 channel_lsb; + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band : 2; + u8 rsvd_0 : 2; + u8 gnt_bt : 1; + u8 ldpc : 1; + u8 stbc : 1; + u8 beamformed : 1; + #else + u8 beamformed : 1; + u8 stbc : 1; + u8 ldpc : 1; + u8 gnt_bt : 1; + u8 rsvd_0 : 1; + u8 band : 2; + #endif +}; +#endif /*@#ifdef PHYSTS_3RD_TYPE_SUPPORT*/ + +#ifdef PHYDM_PHYSTAUS_AUTO_SWITCH +void phydm_physts_auto_switch_jgr3_set(void *dm_void, boolean enable, + u8 bitmap_en); +#endif + +#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1) +boolean +phydm_query_is_mu_api(struct dm_struct *phydm, u8 ppdu_idx, u8 *p_data_rate, + u8 *p_gid); +#endif + +void phydm_reset_phystatus_avg(struct dm_struct *dm); + +void phydm_reset_phystatus_statistic(struct dm_struct *dm); + +void phydm_reset_rssi_for_dm(struct dm_struct *dm, u8 station_id); + +void phydm_get_cck_rssi_table_from_reg(struct dm_struct *dm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_normal_driver_rx_sniffer( + struct dm_struct *dm, + u8 *desc, + PRT_RFD_STATUS rt_rfd_status, + u8 *drv_info, + u8 phy_status); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +s32 phydm_signal_scale_mapping(struct dm_struct *dm, s32 curr_sig); +#endif + +boolean odm_phy_status_query(struct dm_struct *dm, + struct phydm_phyinfo_struct *phy_info, + u8 *phy_sts, + struct phydm_perpkt_info_struct *pktinfo); + +void phydm_rx_phy_status_init(void *dm_void); + +void phydm_physts_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +#endif /*@#ifndef __HALHWOUTSRC_H__*/ diff --git a/hal/phydm/phydm_pmac_tx_setting.c b/hal/phydm/phydm_pmac_tx_setting.c new file mode 100644 index 0000000..296f39c --- /dev/null +++ b/hal/phydm/phydm_pmac_tx_setting.c @@ -0,0 +1,584 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_start_cck_cont_tx_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u8 rate = tx_info->tx_rate; /* HW rate */ + + /* if CCK block on? */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1); + if (dm->support_ic_type & ODM_RTL8723F) { + odm_set_bb_reg(dm, R_0x2a08, BIT(21)|BIT(20), rate); + odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/ + } else { + /* Turn Off All Test mode */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0); + + odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate); + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */ + odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/ + + /* Fix rate selection issue */ + odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1); + /* set RX weighting for path I & Q to 0 */ + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3); + /* set loopback mode */ + odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1); + } + pmac_tx->cck_cont_tx = true; + pmac_tx->ofdm_cont_tx = false; +} + +void phydm_stop_cck_cont_tx_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + pmac_tx->cck_cont_tx = false; + pmac_tx->ofdm_cont_tx = false; + + if (dm->support_ic_type & ODM_RTL8723F) { + /* @Disable pmac tx_en*/ + odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/ + } else { + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */ + odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/ + + /* back to default */ + odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0); + odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0); + odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0); + } + /* BB Reset */ + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1); +} + +void phydm_start_ofdm_cont_tx_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + /* 1. if OFDM block on */ + if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0))) + odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1); + if (!(dm->support_ic_type & ODM_RTL8723F)) { + + /* 2. set CCK test mode off, set to CCK normal mode */ + odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); + + /* 3. turn on scramble setting */ + odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); + } + /* 4. Turn On Continue Tx and turn off the other test modes. */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1); + + pmac_tx->cck_cont_tx = false; + pmac_tx->ofdm_cont_tx = true; +} + +void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + pmac_tx->cck_cont_tx = false; + pmac_tx->ofdm_cont_tx = false; + + /* Turn Off All Test mode */ + odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0); + + /* Delay 10 ms */ + ODM_delay_ms(10); + + /* BB Reset */ + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0); + odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1); +} + +void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + + odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */ + if (dm->support_ic_type & ODM_RTL8723F) { + if (tx_info->mode == CONT_TX) { + if (pmac_tx->is_cck_rate) { + /* TX Stop */ + odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1); + /* Clear BB cont tx */ + odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0); + /* Clear PMAC cont tx */ + odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0); + /* Clear TX Stop */ + odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0); + phydm_stop_cck_cont_tx_jgr3(dm); + } else + phydm_stop_ofdm_cont_tx_jgr3(dm); + } else { + if (pmac_tx->is_cck_rate) { + /* packet_count = 0x1 */ + odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, 0x1); + /* @Disable pmac tx_en*/ + odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0); + /* @Enable pmac tx_en*/ + odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1); + phydm_stop_cck_cont_tx_jgr3(dm); + } + } + }else { + if (tx_info->mode == CONT_TX) { + if (pmac_tx->is_cck_rate) + phydm_stop_cck_cont_tx_jgr3(dm); + else + phydm_stop_ofdm_cont_tx_jgr3(dm); + } + } +} + +void phydm_set_mac_phy_txinfo_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + + odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate); + + /*0x900[1] ndp_sound */ + odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound); + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + tx_info->m_stbc = tx_info->m_stbc - 1; + #endif + /*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */ + tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) | + ((tx_info->m_stbc) << 6); + odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp); + + if (tx_info->tx_sc == 1) /*upper*/ + odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5); + else if (tx_info->tx_sc == 2) /*lower*/ + odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6); + else /* duplicate*/ + odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0); + + if (pmac_tx->is_ht_rate) { + odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1); + odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0); + } else if (pmac_tx->is_vht_rate) { + odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0); + odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1); + } else { + odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0); + odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0); + } + + /* for TX interval */ + odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period); +} + +void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + + if (pmac_tx->is_cck_rate) + return; + + odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count); + + /* L-SIG */ + tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1], + tx_info->lsig[0]); + odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp); + if (pmac_tx->is_ht_rate) { + /* HT SIG */ + tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1], + tx_info->ht_sig[0]); + odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp); + tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4], + tx_info->ht_sig[3]); + odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp); + } else if (pmac_tx->is_vht_rate) { + /* VHT SIG A/B/serv_field/delimiter */ + tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2], + tx_info->vht_sig_a[1], + tx_info->vht_sig_a[0]); + odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp); + tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5], + tx_info->vht_sig_a[4], + tx_info->vht_sig_a[3]); + odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp); + tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2], + tx_info->vht_sig_b[1], + tx_info->vht_sig_b[0]); + odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp); + odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc); + + tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3], + tx_info->vht_delimiter[2], + tx_info->vht_delimiter[1], + tx_info->vht_delimiter[0]); + odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp); + } +} + +void phydm_set_cck_preamble_hdr_jgr3(void *dm_void, + struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + u32 tmp = 0; + u8 rate = tx_info->tx_rate; /* HW rate */ + + if (!pmac_tx->is_cck_rate) + return; + + if (dm->support_ic_type & ODM_RTL8723F) { + #if (RTL8723F_SUPPORT) + odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, tx_info->packet_count); + odm_set_bb_reg(dm, R_0x2a08, BIT(22), tx_info->service_field_bit2); + odm_set_bb_reg(dm, R_0x2a08, BIT(21) | BIT(20), rate); + odm_set_bb_reg(dm, R_0x2a08, 0x1ffff, tx_info->packet_length); + /* turn on scrambler */ + odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); + + if (tx_info->is_short_preamble) + odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x1); + else + odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x0); + #endif + } else { + tmp = tx_info->packet_count | (tx_info->sfd << 16); + odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp); + tmp = tx_info->signal_field | (tx_info->service_field << 8) | + (tx_info->length << 16); + odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp); + tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]); + odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp); + + if (tx_info->is_short_preamble) + odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0); + else + odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1); + } +} + +void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info, + enum phydm_pmac_mode mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + if (mode == CONT_TX) { + tx_info->packet_count = 1; + + if (pmac_tx->is_cck_rate) + phydm_start_cck_cont_tx_jgr3(dm, tx_info); + else + phydm_start_ofdm_cont_tx_jgr3(dm); + } +} + +void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */ + + if (dm->support_ic_type & ODM_RTL8723F) { + if (pmac_tx->is_cck_rate) { + if (tx_info->mode == CONT_TX) { + /* BB and PMAC cont tx */ + odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1); + odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1); + } + /* TX CCK ON */ + odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0); + odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1); + } else { + odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x0); /*TX Ofdm OFF */ + odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */ + } + } else { + /*mac scramble seed setting, only in 8198F */ + #if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) + if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16))) + odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1); + #endif + + if (pmac_tx->is_cck_rate){ + odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */ + odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0); + } else { + odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */ + } + } +} + +void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info, + enum rf_path mpt_rf_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table; + + pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate); + pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate); + pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate); + pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate); + pmac_tx->path = mpt_rf_path; + + if (!tx_info->en_pmac_tx) { + phydm_stop_pmac_tx_jgr3(dm, tx_info); + return; + } + + phydm_set_mode_jgr3(dm, tx_info, tx_info->mode); + + if (pmac_tx->is_cck_rate) + phydm_set_cck_preamble_hdr_jgr3(dm, tx_info); + else + phydm_set_sig_jgr3(dm, tx_info); + + phydm_set_mac_phy_txinfo_jgr3(dm, tx_info); + phydm_set_pmac_txon_jgr3(dm, tx_info); +} + +void phydm_set_tmac_tx_jgr3(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + /* Turn on TMAC */ + if (odm_get_bb_reg(dm, R_0x1d08, BIT(0))) + odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0); + + /* mac scramble seed setting, only in 8198F */ + #if (RTL8198F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8198F) + if (odm_get_bb_reg(dm, R_0x1d10, BIT(16))) + odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0); + #endif + + /* Turn on TMAC CCK */ + if (!(dm->support_ic_type & ODM_RTL8723F)) { + if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31))) + odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1); + } +} +#endif + +void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_start_cck_cont_tx_jgr3(dm, tx_info); + #endif +} + +void phydm_stop_cck_cont_tx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_stop_cck_cont_tx_jgr3(dm); + #endif +} + +void phydm_start_ofdm_cont_tx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_start_ofdm_cont_tx_jgr3(dm); + #endif +} + +void phydm_stop_ofdm_cont_tx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_stop_ofdm_cont_tx_jgr3(dm); + #endif +} + +void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info, + enum rf_path mpt_rf_path) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path); + #endif +} + +void phydm_set_tmac_tx(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + phydm_set_tmac_tx_jgr3(dm); + #endif +} + +void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pmac_info tx_info; + char help[] = "-h"; + char dbg_buf[PHYDM_SNPRINT_SIZE] = {0}; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + u32 tx_cnt = 0x0; + u8 poll_cnt = 0x0; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]); + + if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) + return; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n"); + } else { + for (i = 1; i < 7; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var[i]); + } + } + + tx_info.en_pmac_tx = true; + tx_info.mode = PKTS_TX; + tx_info.ndp_sound = false; + tx_info.bw = CHANNEL_WIDTH_20; + tx_info.tx_sc = 0x0; /*duplicate*/ + tx_info.m_stbc = 0x0; /*disable*/ + tx_info.packet_period = 2000; /*d'500 us*/ + tx_info.tx_rate = (u8)var[1]; + tx_info.packet_count = (u32)var[2]; + + if (tx_info.tx_rate == ODM_RATE1M) { + tx_info.signal_field = 0xa; /*rate = 1M*/ + tx_info.service_field = 0x0; + if (dm->support_ic_type & ODM_RTL8723F) { + tx_info.service_field_bit2= 0x1; + tx_info.packet_length = 1000; /*1000 bytes*/ + } + tx_info.length = 8000; /*d'8000 us=1000 bytes*/ + tx_info.crc16[0] = 0x60; + tx_info.crc16[1] = 0x8e; + /*long preamble*/ + tx_info.is_short_preamble = false; + tx_info.sfd = 0xf3a0; + } else if (tx_info.tx_rate == ODM_RATE6M) { + /*l-sig[3:0] = rate = 6M = 0xb*/ + /*l-sig[16:5] = length = 1000 bytes*/ + /*l-sig[17] = parity = 1*/ + tx_info.lsig[0] = 0xb; + tx_info.lsig[1] = 0x7d; + tx_info.lsig[2] = 0x2; + } + phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf, + PHYDM_SNPRINT_SIZE); + PDM_SNPF(out_len, used, output + used, out_len - used, + "rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n", + dbg_buf, tx_info.packet_count); + + if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "check trx idle failed, please try again.\n"); + return; + } + + phydm_reset_bb_hw_cnt(dm); + phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "pmac_tx enabled, please wait for tx_cnt = %d\n", + tx_info.packet_count); + while (1) { + if (phydm_is_cck_rate(dm, tx_info.tx_rate)) + tx_cnt = odm_get_bb_reg(dm, R_0x2de4, + MASKLWORD); + else + tx_cnt = odm_get_bb_reg(dm, R_0x2de0, + MASKLWORD); + + if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10) + break; + + ODM_delay_ms(100); + poll_cnt++; + } + + if (tx_cnt < tx_info.packet_count) + PDM_SNPF(out_len, used, output + used, out_len - used, + "polling time out(1s), tx_cnt = %d\n", tx_cnt); + else + PDM_SNPF(out_len, used, output + used, out_len - used, + "pmac_tx finished, poll_cnt = %d\n", poll_cnt); + + tx_info.en_pmac_tx = false; + phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A); + phydm_set_tmac_tx(dm); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Stop pmac_tx and turn on true mac mode.\n"); + + phydm_stop_ic_trx(dm, PHYDM_REVERT); + } + *_used = used; + *_out_len = out_len; +} +#endif \ No newline at end of file diff --git a/hal/phydm/phydm_pmac_tx_setting.h b/hal/phydm/phydm_pmac_tx_setting.h new file mode 100644 index 0000000..532219b --- /dev/null +++ b/hal/phydm/phydm_pmac_tx_setting.h @@ -0,0 +1,111 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_PMAC_TX_SETTING_H__ +#define __PHYDM_PMAC_TX_SETTING_H__ + +/*2020.03.16 Fix TxInfo content in B mode*/ +#define PMAC_TX_SETTING_VERSION "2.1" + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct phydm_pmac_info { + u8 en_pmac_tx:1; /*0: disable pmac 1: enable pmac */ + u8 mode:3; /*0: Packet TX 3:Continuous TX */ + u8 tx_rate; /*should be HW rate*/ + u8 tx_sc; + u8 is_short_preamble:1; + u8 ndp_sound:1; + u8 bw:3; /* 0:20 1:40 2:80Mhz */ + u8 m_stbc; /* bSTBC + 1 for WIN/CE, bSTBC for others*/ + u16 packet_period; + u32 packet_count; + u32 packet_length; + u8 packet_pattern; + u16 sfd; + u8 signal_field; + u8 service_field; + u8 service_field_bit2:1; + u16 length; + u8 crc16[2]; + u8 lsig[3]; + u8 ht_sig[6]; + u8 vht_sig_a[6]; + u8 vht_sig_b[4]; + u8 vht_sig_b_crc; + u8 vht_delimiter[4]; +}; + +struct phydm_pmac_tx { + boolean is_cck_rate; + boolean is_ofdm_rate; + boolean is_ht_rate; + boolean is_vht_rate; + boolean cck_cont_tx; + boolean ofdm_cont_tx; + u8 path; +}; + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +enum phydm_pmac_mode { + NONE_TEST, + PKTS_TX, + PKTS_RX, + CONT_TX, + OFDM_SINGLE_TONE_TX, + CCK_CARRIER_SIPPRESSION_TX +}; + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ +void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info); + +void phydm_stop_cck_cont_tx(void *dm_void); + +void phydm_start_ofdm_cont_tx(void *dm_void); + +void phydm_stop_ofdm_cont_tx(void *dm_void); + +void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info, + enum rf_path mpt_rf_path); + +void phydm_set_tmac_tx(void *dm_void); + +void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); +#endif diff --git a/hal/phydm/phydm_pow_train.c b/hal/phydm/phydm_pow_train.c new file mode 100644 index 0000000..56bc241 --- /dev/null +++ b/hal/phydm/phydm_pow_train.c @@ -0,0 +1,171 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_POWER_TRAINING_SUPPORT +void phydm_reset_pt_para(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table; + + pt_t->pow_train_score = 0; +} + +void phydm_update_power_training_state(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table; + struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt; + struct ccx_info *ccx = &dm->dm_ccx_info; + u32 pt_score_tmp = ENABLE_PT_SCORE; + u32 crc_ok_cnt = 0; + u32 cca_cnt = 0; + + /*@is_disable_power_training is the key to H2C to disable/enable PT*/ + /*@if is_disable_power_training == 1, it will use largest power*/ + if (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) { + dm->is_disable_power_training = true; + phydm_reset_pt_para(dm); + return; + } + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __func__); + + if (pt_t->pt_state == DISABLE_POW_TRAIN) { + dm->is_disable_power_training = true; + phydm_reset_pt_para(dm); + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n"); + return; + + } else if (pt_t->pt_state == ENABLE_POW_TRAIN) { + dm->is_disable_power_training = false; + phydm_reset_pt_para(dm); + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n"); + return; + + } else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) { + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n"); + + /* @Compute score */ + crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm + + dm->phy_dbg_info.num_qry_phy_status_cck; + cca_cnt = fa_cnt->cnt_cca_all; +#if 0 + if (crc_ok_cnt > cca_cnt) { /*invalid situation*/ + pt_score_tmp = KEEP_PRE_PT_SCORE; + return; + } else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) { + /* @???crc_ok <= (2/3)*cca */ + pt_score_tmp = DISABLE_PT_SCORE; + dm->is_disable_power_training = true; + } else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) { + /* @???crc_ok <= (4/5)*cca */ + pt_score_tmp = KEEP_PRE_PT_SCORE; + } else { + /* @???crc_ok > (4/5)*cca */ + pt_score_tmp = ENABLE_PT_SCORE; + dm->is_disable_power_training = false; + } +#endif + if (ccx->nhm_ratio > 10) { + pt_score_tmp = DISABLE_PT_SCORE; + dm->is_disable_power_training = true; + } else if (ccx->nhm_ratio < 5) { + pt_score_tmp = ENABLE_PT_SCORE; + dm->is_disable_power_training = false; + } else { + pt_score_tmp = KEEP_PRE_PT_SCORE; + } + + PHYDM_DBG(dm, DBG_PWR_TRAIN, + "pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\n", + dm->phy_dbg_info.num_qry_phy_status_ofdm, + dm->phy_dbg_info.num_qry_phy_status_cck, + crc_ok_cnt, cca_cnt); + + PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp=%d\n", pt_score_tmp); + + /* smoothing */ + pt_t->pow_train_score = (pt_score_tmp << 4) + + (pt_t->pow_train_score >> 1) + + (pt_t->pow_train_score >> 2); + + pt_score_tmp = (pt_t->pow_train_score + 32) >> 6; + + PHYDM_DBG(dm, DBG_PWR_TRAIN, + "pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\n", + pt_t->pow_train_score, pt_score_tmp, + dm->is_disable_power_training); + } else { + PHYDM_DBG(dm, DBG_PWR_TRAIN, "[%s]warning\n", __func__); + } +} + +void phydm_pow_train_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i; + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0: Auto PT, 1:enable, 2: disable}\n"); + } else { + for (i = 0; i < 10; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + } + + if (var1[0] == 0) + pt_t->pt_state = DYNAMIC_POW_TRAIN; + else if (var1[0] == 1) + pt_t->pt_state = ENABLE_POW_TRAIN; + else if (var1[0] == 2) + pt_t->pt_state = DISABLE_POW_TRAIN; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "PT state = %d\n", pt_t->pt_state); + } + + *_used = used; + *_out_len = out_len; +} + +#endif diff --git a/hal/phydm/phydm_pow_train.h b/hal/phydm/phydm_pow_train.h new file mode 100644 index 0000000..f966607 --- /dev/null +++ b/hal/phydm/phydm_pow_train.h @@ -0,0 +1,84 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_POW_TRAIN_H__ +#define __PHYDM_POW_TRAIN_H__ + +#define POW_TRAIN_VERSION "1.0" /* @2017.07.0141 Dino, Add phydm_pow_train.h*/ + +/**************************************************************** + * 1 ============================================================ + * 1 Definition + * 1 ============================================================ + ***************************************************************/ + +#ifdef PHYDM_POWER_TRAINING_SUPPORT +/**************************************************************** + * 1 ============================================================ + * 1 structure + * 1 ============================================================ + ***************************************************************/ + +struct phydm_pow_train_stuc { + u8 pt_state; + u32 pow_train_score; +}; + +/**************************************************************** + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + ***************************************************************/ + +enum pow_train_state { + DYNAMIC_POW_TRAIN = 0, + ENABLE_POW_TRAIN = 1, + DISABLE_POW_TRAIN = 2 +}; + +enum power_training_score { + DISABLE_PT_SCORE = 0, + KEEP_PRE_PT_SCORE = 1, + ENABLE_PT_SCORE = 2 +}; + +/**************************************************************** + * 1 ============================================================ + * 1 function prototype + * 1 ============================================================ + ***************************************************************/ + +void phydm_update_power_training_state( + void *dm_void); + +void phydm_pow_train_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +#endif +#endif diff --git a/hal/phydm/phydm_pre_define.h b/hal/phydm/phydm_pre_define.h new file mode 100644 index 0000000..fa1a0df --- /dev/null +++ b/hal/phydm/phydm_pre_define.h @@ -0,0 +1,1020 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMPREDEFINE_H__ +#define __PHYDMPREDEFINE_H__ + +/**************************************************************** + * 1 ============================================================ + * 1 Definition + * 1 ============================================================ + ***************************************************************/ + +#define PHYDM_CODE_BASE "PHYDM_V050" +#define PHYDM_RELEASE_DATE "20201019.0" + +/*PHYDM API status*/ +#define PHYDM_SET_FAIL 0 +#define PHYDM_SET_SUCCESS 1 +#define PHYDM_SET_NO_NEED 3 + +/*PHYDM Set/Revert*/ +#define PHYDM_SET 1 +#define PHYDM_REVERT 2 + +/* @Max path of IC */ +/*N-IC*/ +#define MAX_PATH_NUM_8188E 1 +#define MAX_PATH_NUM_8188F 1 +#define MAX_PATH_NUM_8710B 1 +#define MAX_PATH_NUM_8723B 1 +#define MAX_PATH_NUM_8723D 1 +#define MAX_PATH_NUM_8703B 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8192F 2 +#define MAX_PATH_NUM_8197F 2 +#define MAX_PATH_NUM_8198F 4 +#define MAX_PATH_NUM_8197G 2 +#define MAX_PATH_NUM_8721D 1 +#define MAX_PATH_NUM_8710C 1 +#define MAX_PATH_NUM_8723F 2 + +/*@AC-IC*/ +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8881A 1 +#define MAX_PATH_NUM_8821C 1 +#define MAX_PATH_NUM_8195B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8822B 2 +#define MAX_PATH_NUM_8822C 2 +#define MAX_PATH_NUM_8814A 4 +#define MAX_PATH_NUM_8814B 4 +#define MAX_PATH_NUM_8814C 4 +#define MAX_PATH_NUM_8195B 1 +#define MAX_PATH_NUM_8812F 2 + +/* @Max RF path */ +#define PHYDM_MAX_RF_PATH_N 2 /*@For old N-series IC*/ +#define PHYDM_MAX_RF_PATH 4 + +/* number of entry */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #ifdef DM_ODM_CE_MAC80211 + /* @defined in wifi.h (32+1) */ + #else + #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* @Max size of asoc_entry[].*/ + #endif + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #define ASSOCIATE_ENTRY_NUM NUM_STAT + #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM + 1) +#elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) + #ifdef CONFIG_CONCURRENT_MODE + #define ASSOCIATE_ENTRY_NUM NUM_STA + 2 /*@2 is for station mod*/ + #else + #define ASSOCIATE_ENTRY_NUM NUM_STA /*@8 is for max size of asoc_entry[].*/ + #endif + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#else + #define ODM_ASSOCIATE_ENTRY_NUM (((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1) +#endif + +/* @-----MGN rate--------------------------------- */ + +enum PDM_RATE_TYPE { + PDM_1SS = 1, /*VHT/HT 1SS*/ + PDM_2SS = 2, /*VHT/HT 2SS*/ + PDM_3SS = 3, /*VHT/HT 3SS*/ + PDM_4SS = 4, /*VHT/HT 4SS*/ + PDM_CCK = 11, /*@B*/ + PDM_OFDM = 12 /*@G*/ +}; + +enum ODM_MGN_RATE { + ODM_MGN_1M = 0x02, + ODM_MGN_2M = 0x04, + ODM_MGN_5_5M = 0x0B, + ODM_MGN_6M = 0x0C, + ODM_MGN_9M = 0x12, + ODM_MGN_11M = 0x16, + ODM_MGN_12M = 0x18, + ODM_MGN_18M = 0x24, + ODM_MGN_24M = 0x30, + ODM_MGN_36M = 0x48, + ODM_MGN_48M = 0x60, + ODM_MGN_54M = 0x6C, + ODM_MGN_MCS32 = 0x7F, + ODM_MGN_MCS0 = 0x80, + ODM_MGN_MCS1, + ODM_MGN_MCS2, + ODM_MGN_MCS3, + ODM_MGN_MCS4, + ODM_MGN_MCS5, + ODM_MGN_MCS6, + ODM_MGN_MCS7 = 0x87, + ODM_MGN_MCS8, + ODM_MGN_MCS9, + ODM_MGN_MCS10, + ODM_MGN_MCS11, + ODM_MGN_MCS12, + ODM_MGN_MCS13, + ODM_MGN_MCS14, + ODM_MGN_MCS15, + ODM_MGN_MCS16 = 0x90, + ODM_MGN_MCS17, + ODM_MGN_MCS18, + ODM_MGN_MCS19, + ODM_MGN_MCS20, + ODM_MGN_MCS21, + ODM_MGN_MCS22, + ODM_MGN_MCS23, + ODM_MGN_MCS24 = 0x98, + ODM_MGN_MCS25, + ODM_MGN_MCS26, + ODM_MGN_MCS27, + ODM_MGN_MCS28, + ODM_MGN_MCS29, + ODM_MGN_MCS30, + ODM_MGN_MCS31, + ODM_MGN_VHT1SS_MCS0 = 0xa0, + ODM_MGN_VHT1SS_MCS1, + ODM_MGN_VHT1SS_MCS2, + ODM_MGN_VHT1SS_MCS3, + ODM_MGN_VHT1SS_MCS4, + ODM_MGN_VHT1SS_MCS5, + ODM_MGN_VHT1SS_MCS6, + ODM_MGN_VHT1SS_MCS7, + ODM_MGN_VHT1SS_MCS8, + ODM_MGN_VHT1SS_MCS9, + ODM_MGN_VHT2SS_MCS0 = 0xaa, + ODM_MGN_VHT2SS_MCS1 = 0xab, + ODM_MGN_VHT2SS_MCS2, + ODM_MGN_VHT2SS_MCS3, + ODM_MGN_VHT2SS_MCS4, + ODM_MGN_VHT2SS_MCS5 = 0xaf, + ODM_MGN_VHT2SS_MCS6 = 0xb0, + ODM_MGN_VHT2SS_MCS7, + ODM_MGN_VHT2SS_MCS8, + ODM_MGN_VHT2SS_MCS9 = 0xb3, + ODM_MGN_VHT3SS_MCS0 = 0xb4, + ODM_MGN_VHT3SS_MCS1, + ODM_MGN_VHT3SS_MCS2, + ODM_MGN_VHT3SS_MCS3, + ODM_MGN_VHT3SS_MCS4, + ODM_MGN_VHT3SS_MCS5, + ODM_MGN_VHT3SS_MCS6, + ODM_MGN_VHT3SS_MCS7 = 0xbb, + ODM_MGN_VHT3SS_MCS8 = 0xbc, + ODM_MGN_VHT3SS_MCS9 = 0xbd, + ODM_MGN_VHT4SS_MCS0 = 0xbe, + ODM_MGN_VHT4SS_MCS1, + ODM_MGN_VHT4SS_MCS2, + ODM_MGN_VHT4SS_MCS3, + ODM_MGN_VHT4SS_MCS4, + ODM_MGN_VHT4SS_MCS5, + ODM_MGN_VHT4SS_MCS6, + ODM_MGN_VHT4SS_MCS7, + ODM_MGN_VHT4SS_MCS8, + ODM_MGN_VHT4SS_MCS9 = 0xc7, + ODM_MGN_UNKNOWN +}; + +#define ODM_MGN_MCS0_SG 0xc0 +#define ODM_MGN_MCS1_SG 0xc1 +#define ODM_MGN_MCS2_SG 0xc2 +#define ODM_MGN_MCS3_SG 0xc3 +#define ODM_MGN_MCS4_SG 0xc4 +#define ODM_MGN_MCS5_SG 0xc5 +#define ODM_MGN_MCS6_SG 0xc6 +#define ODM_MGN_MCS7_SG 0xc7 +#define ODM_MGN_MCS8_SG 0xc8 +#define ODM_MGN_MCS9_SG 0xc9 +#define ODM_MGN_MCS10_SG 0xca +#define ODM_MGN_MCS11_SG 0xcb +#define ODM_MGN_MCS12_SG 0xcc +#define ODM_MGN_MCS13_SG 0xcd +#define ODM_MGN_MCS14_SG 0xce +#define ODM_MGN_MCS15_SG 0xcf + +/* @-----DESC rate--------------------------------- */ + +#define ODM_RATEMCS15_SG 0x1c +#define ODM_RATEMCS32 0x20 + +enum phydm_ctrl_info_rate { + ODM_RATE1M = 0x00, + ODM_RATE2M = 0x01, + ODM_RATE5_5M = 0x02, + ODM_RATE11M = 0x03, +/* OFDM Rates, TxHT = 0 */ + ODM_RATE6M = 0x04, + ODM_RATE9M = 0x05, + ODM_RATE12M = 0x06, + ODM_RATE18M = 0x07, + ODM_RATE24M = 0x08, + ODM_RATE36M = 0x09, + ODM_RATE48M = 0x0A, + ODM_RATE54M = 0x0B, +/* @MCS Rates, TxHT = 1 */ + ODM_RATEMCS0 = 0x0C, + ODM_RATEMCS1 = 0x0D, + ODM_RATEMCS2 = 0x0E, + ODM_RATEMCS3 = 0x0F, + ODM_RATEMCS4 = 0x10, + ODM_RATEMCS5 = 0x11, + ODM_RATEMCS6 = 0x12, + ODM_RATEMCS7 = 0x13, + ODM_RATEMCS8 = 0x14, + ODM_RATEMCS9 = 0x15, + ODM_RATEMCS10 = 0x16, + ODM_RATEMCS11 = 0x17, + ODM_RATEMCS12 = 0x18, + ODM_RATEMCS13 = 0x19, + ODM_RATEMCS14 = 0x1A, + ODM_RATEMCS15 = 0x1B, + ODM_RATEMCS16 = 0x1C, + ODM_RATEMCS17 = 0x1D, + ODM_RATEMCS18 = 0x1E, + ODM_RATEMCS19 = 0x1F, + ODM_RATEMCS20 = 0x20, + ODM_RATEMCS21 = 0x21, + ODM_RATEMCS22 = 0x22, + ODM_RATEMCS23 = 0x23, + ODM_RATEMCS24 = 0x24, + ODM_RATEMCS25 = 0x25, + ODM_RATEMCS26 = 0x26, + ODM_RATEMCS27 = 0x27, + ODM_RATEMCS28 = 0x28, + ODM_RATEMCS29 = 0x29, + ODM_RATEMCS30 = 0x2A, + ODM_RATEMCS31 = 0x2B, + ODM_RATEVHTSS1MCS0 = 0x2C, + ODM_RATEVHTSS1MCS1 = 0x2D, + ODM_RATEVHTSS1MCS2 = 0x2E, + ODM_RATEVHTSS1MCS3 = 0x2F, + ODM_RATEVHTSS1MCS4 = 0x30, + ODM_RATEVHTSS1MCS5 = 0x31, + ODM_RATEVHTSS1MCS6 = 0x32, + ODM_RATEVHTSS1MCS7 = 0x33, + ODM_RATEVHTSS1MCS8 = 0x34, + ODM_RATEVHTSS1MCS9 = 0x35, + ODM_RATEVHTSS2MCS0 = 0x36, + ODM_RATEVHTSS2MCS1 = 0x37, + ODM_RATEVHTSS2MCS2 = 0x38, + ODM_RATEVHTSS2MCS3 = 0x39, + ODM_RATEVHTSS2MCS4 = 0x3A, + ODM_RATEVHTSS2MCS5 = 0x3B, + ODM_RATEVHTSS2MCS6 = 0x3C, + ODM_RATEVHTSS2MCS7 = 0x3D, + ODM_RATEVHTSS2MCS8 = 0x3E, + ODM_RATEVHTSS2MCS9 = 0x3F, + ODM_RATEVHTSS3MCS0 = 0x40, + ODM_RATEVHTSS3MCS1 = 0x41, + ODM_RATEVHTSS3MCS2 = 0x42, + ODM_RATEVHTSS3MCS3 = 0x43, + ODM_RATEVHTSS3MCS4 = 0x44, + ODM_RATEVHTSS3MCS5 = 0x45, + ODM_RATEVHTSS3MCS6 = 0x46, + ODM_RATEVHTSS3MCS7 = 0x47, + ODM_RATEVHTSS3MCS8 = 0x48, + ODM_RATEVHTSS3MCS9 = 0x49, + ODM_RATEVHTSS4MCS0 = 0x4A, + ODM_RATEVHTSS4MCS1 = 0x4B, + ODM_RATEVHTSS4MCS2 = 0x4C, + ODM_RATEVHTSS4MCS3 = 0x4D, + ODM_RATEVHTSS4MCS4 = 0x4E, + ODM_RATEVHTSS4MCS5 = 0x4F, + ODM_RATEVHTSS4MCS6 = 0x50, + ODM_RATEVHTSS4MCS7 = 0x51, + ODM_RATEVHTSS4MCS8 = 0x52, + ODM_RATEVHTSS4MCS9 = 0x53, +}; + +enum phydm_legacy_spec_rate { + PHYDM_SPEC_RATE_6M = 0xb, + PHYDM_SPEC_RATE_9M = 0xf, + PHYDM_SPEC_RATE_12M = 0xa, + PHYDM_SPEC_RATE_18M = 0xe, + PHYDM_SPEC_RATE_24M = 0x9, + PHYDM_SPEC_RATE_36M = 0xd, + PHYDM_SPEC_RATE_48M = 0x8, + PHYDM_SPEC_RATE_54M = 0xc +}; + +#define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1) +#define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1) +#define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1) +#define NUM_RATE_AC_1SS (ODM_RATEVHTSS1MCS9 + 1) +#define NUM_RATE_N_4SS (ODM_RATEMCS31 + 1) +#define NUM_RATE_N_3SS (ODM_RATEMCS23 + 1) +#define NUM_RATE_N_2SS (ODM_RATEMCS15 + 1) +#define NUM_RATE_N_1SS (ODM_RATEMCS7 + 1) + +/*Define from larger rate size to small rate size, DO NOT change the position*/ +/*[AC-4SS]*/ +#if (RTL8814B_SUPPORT) + #define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS +/*[AC-3SS]*/ +#elif (RTL8814A_SUPPORT) + #define PHY_NUM_RATE_IDX NUM_RATE_AC_3SS +/*[AC-2SS]*/ +#elif (RTL8812A_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT) + #define PHY_NUM_RATE_IDX NUM_RATE_AC_2SS +/*[AC-1SS]*/ +#elif (RTL8881A_SUPPORT || RTL8821A_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8195B_SUPPORT) + #define PHY_NUM_RATE_IDX NUM_RATE_AC_1SS +/*[N-4SS]*/ +#elif (RTL8198F_SUPPORT) + #define PHY_NUM_RATE_IDX NUM_RATE_N_4SS +/*[N-2SS]*/ +#elif (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\ + RTL8197G_SUPPORT) + #define PHY_NUM_RATE_IDX NUM_RATE_N_2SS +/*[N-1SS]*/ +#elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \ + RTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\ + RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT) + #define PHY_NUM_RATE_IDX NUM_RATE_N_1SS +#else + #define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define CONFIG_SFW_SUPPORTED +#endif + +/**************************************************************** + * 1 ============================================================ + * 1 enumeration + * 1 ============================================================ + ***************************************************************/ + +/* ODM_CMNINFO_INTERFACE */ +enum odm_interface { + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}; + +enum phydm_api_host { + RUN_IN_FW = 0, + RUN_IN_DRIVER = 1, +}; + +/*@========[Run time IC flag] ===================================*/ + +enum phydm_ic { + ODM_RTL8188E = BIT(0), + ODM_RTL8812 = BIT(1), + ODM_RTL8821 = BIT(2), + ODM_RTL8192E = BIT(3), + ODM_RTL8723B = BIT(4), + ODM_RTL8814A = BIT(5), + ODM_RTL8881A = BIT(6), + ODM_RTL8822B = BIT(7), + ODM_RTL8703B = BIT(8), + ODM_RTL8195A = BIT(9), + ODM_RTL8188F = BIT(10), + ODM_RTL8723D = BIT(11), + ODM_RTL8197F = BIT(12), + ODM_RTL8821C = BIT(13), + ODM_RTL8814B = BIT(14), + ODM_RTL8198F = BIT(15), + ODM_RTL8710B = BIT(16), + ODM_RTL8192F = BIT(17), + ODM_RTL8822C = BIT(18), + ODM_RTL8195B = BIT(19), + ODM_RTL8812F = BIT(20), + ODM_RTL8197G = BIT(21), + ODM_RTL8721D = BIT(22), + ODM_RTL8710C = BIT(23), + ODM_RTL8723F = BIT(24) +}; + +#define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\ + ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\ + ODM_RTL8710B | ODM_RTL8721D | ODM_RTL8710C) +#define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F) +#define ODM_IC_N_3SS 0 +#define ODM_IC_N_4SS 0 + +#define ODM_IC_AC_1SS (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\ + ODM_RTL8195B) +#define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B) +#define ODM_IC_AC_3SS 0 +#define ODM_IC_AC_4SS (ODM_RTL8814A) + +#define ODM_IC_JGR3_1SS (ODM_RTL8723F) +#define ODM_IC_JGR3_2SS (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G) +#define ODM_IC_JGR3_3SS 0 +#define ODM_IC_JGR3_4SS (ODM_RTL8198F | ODM_RTL8814B) + +/*@====the following macro DO NOT need to update when adding a new IC======= */ +#define ODM_IC_1SS (ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS) +#define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS) +#define ODM_IC_3SS (ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS) +#define ODM_IC_4SS (ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS) + +#define PHYDM_IC_ABOVE_1SS (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\ + ODM_IC_4SS) +#define PHYDM_IC_ABOVE_2SS (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) +#define PHYDM_IC_ABOVE_3SS (ODM_IC_3SS | ODM_IC_4SS) +#define PHYDM_IC_ABOVE_4SS ODM_IC_4SS + +#define ODM_IC_11N_SERIES (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\ + ODM_IC_N_4SS) +#define ODM_IC_11AC_SERIES (ODM_IC_AC_1SS | ODM_IC_AC_2SS |\ + ODM_IC_AC_3SS | ODM_IC_AC_4SS) +#define ODM_IC_JGR3_SERIES (ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\ + ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS) +/*@====================================================*/ + +#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) +#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\ + ODM_RTL8195B) + +/*@[Phy status type]*/ +#define PHYSTS_2ND_TYPE_IC (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\ + ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\ + ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C) +#define PHYSTS_3RD_TYPE_IC (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\ + ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F) +/*@[FW Type]*/ +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\ + ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\ + ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D |\ + ODM_RTL8710C) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ + ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ + ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\ + ODM_RTL8197G | ODM_RTL8723F) +/*@[LA mode]*/ +#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ + ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ + ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\ + ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G | ODM_RTL8723F) +/*@[BF]*/ +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\ + ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\ + ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\ + ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\ + ODM_RTL8814B | ODM_RTL8197G) +#define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\ + ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C |\ + ODM_RTL8812F | ODM_RTL8723F) +#define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\ + ODM_RTL8822C | ODM_RTL8812F) + +#define PHYDM_IC_SUPPORT_MU (PHYDM_IC_SUPPORT_MU_BFEE |\ + PHYDM_IC_SUPPORT_MU_BFER) +/*@[PHYDM API]*/ +#define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\ + ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\ + ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\ + ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C | ODM_RTL8723F) + +/* fw offload ability*/ +#define PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD (ODM_RTL8814A | ODM_RTL8822B |\ + ODM_RTL8821C | ODM_RTL8822C) + +/* halmac offload ability*/ +#define PHYDM_IC_SUPPORT_HALMAC_PARAM_OFFLOAD (ODM_RTL8822C | ODM_RTL8812F |\ + ODM_RTL8814B | ODM_RTL8723F) + +/*[CCX]*/ +#define PHYDM_IC_SUPPORT_FAHM (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8198F |\ + ODM_RTL8814B | ODM_RTL8822C | ODM_RTL8812F |\ + ODM_RTL8197G | ODM_RTL8723F) +#define PHYDM_IC_SUPPORT_IFS_CLM (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F) + +/*[ARFR]*/ +/*for MAC HW control rate_id=0~12 and 2.4g vht mode(1ss/2ss) support*/ +#define PHYDM_IC_RATEID_IDX_TYPE2 (ODM_RTL8822B | ODM_RTL8822C | ODM_RTL8195B |\ + ODM_RTL8821C) + +/*@========[Compile time IC flag] ========================*/ +/*@========[AC-3/AC/N Support] ===========================*/ + +#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) + #define PHYDM_IC_JGR3_SERIES_SUPPORT + #if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) + #define PHYDM_IC_JGR3_80M_SUPPORT + #endif +#endif + +#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\ + RTL8723F_SUPPORT) + #define PHYDM_IC_HALMAC_PARAM_SUPPORT +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + #ifdef RTK_AC_SUPPORT + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #else + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #endif + + #define ODM_IC_11N_SERIES_SUPPORT 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #define ODM_IC_11N_SERIES_SUPPORT 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #define ODM_IC_11N_SERIES_SUPPORT 1 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) + + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #define ODM_IC_11N_SERIES_SUPPORT 1 + +#else /*ODM_CE*/ + + #if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\ + RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\ + RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\ + RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) + #define ODM_IC_11N_SERIES_SUPPORT 1 + #define ODM_IC_11AC_SERIES_SUPPORT 0 + #else + #define ODM_IC_11N_SERIES_SUPPORT 0 + #define ODM_IC_11AC_SERIES_SUPPORT 1 + #endif +#endif + +/*@===IC SS Compile Flag, prepare for code size reduction==============*/ +#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\ + RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\ + RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\ + RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT ||\ + RTL8710C_SUPPORT || RTL8723F_SUPPORT) + + #define PHYDM_COMPILE_IC_1SS +#endif + +#if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\ + RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8197G_SUPPORT) + #define PHYDM_COMPILE_IC_2SS +#endif + +/*@#define PHYDM_COMPILE_IC_3SS*/ + +#if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT)) + #define PHYDM_COMPILE_IC_4SS +#endif + +/*@==[ABOVE N-SS COMPILE FLAG]=================================================*/ +#if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\ + defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_1SS +#endif + +#if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\ + defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_2SS +#endif + +#if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_3SS +#endif + +#if (defined(PHYDM_COMPILE_IC_4SS)) + #define PHYDM_COMPILE_ABOVE_4SS +#endif + +/*@==[Max RF path number among all compiled ICs]==============================*/ +/*@ ex: support 8814B & 8821C => size=4 */ +/*@ ex: support 8822C & 8821C => size=2 */ +#if (defined(PHYDM_COMPILE_IC_4SS)) + #define RF_PATH_MEM_SIZE 4 +#elif (defined(PHYDM_COMPILE_IC_3SS)) + #define RF_PATH_MEM_SIZE 3 +#elif (defined(PHYDM_COMPILE_IC_2SS)) + #define RF_PATH_MEM_SIZE 2 +#else + #define RF_PATH_MEM_SIZE 1 +#endif + +/*@========[New Phy-Status Support] ========================*/ +#if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\ + RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\ + RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) + #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 +#else + #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 +#endif + +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) + #define PHYSTS_3RD_TYPE_SUPPORT +#endif + +#ifdef PHYSTS_3RD_TYPE_SUPPORT + #define PHYSTS_AUTO_SWITCH_IC (ODM_RTL8822C) +#endif + +#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) + #define BB_RAM_SUPPORT +#endif + +#if (RTL8821C_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8812F_SUPPORT || RTL8814B_SUPPORT || RTL8195B_SUPPORT ||\ + RTL8198F_SUPPORT) + #define PHYDM_COMPILE_MU +#endif + +#if (RTL8822B_SUPPORT) + #define CONFIG_MU_JAGUAR_2 +#endif + +#if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) + #define CONFIG_MU_JAGUAR_3 +#endif + +#if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3)) + #if (RTL8814B_SUPPORT) + #define MU_EX_MACID 76 + #elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) + #define MU_EX_MACID 30 + #endif +#endif +/*@============================================================================*/ + +#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ + RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\ + RTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\ + RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT) +#define PHYDM_COMMON_API_SUPPORT +#endif + +#define PHYDM_COMMON_API_IC (ODM_IC_JGR3_SERIES | ODM_RTL8822B |\ + ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8195B |\ + ODM_RTL8721D | ODM_RTL8710C) + +#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT || RTL8821A_SUPPORT ||\ + RTL8812A_SUPPORT || RTL8723B_SUPPORT || RTL8703B_SUPPORT ||\ + RTL8195A_SUPPORT || RTL8814A_SUPPORT) +#define PHYDM_COMMON_API_NOT_SUPPORT +#endif + +#if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8197G_SUPPORT) + #define CONFIG_RFE_BY_HW_INFO +#endif + +#define CCK_RATE_NUM 4 +#define OFDM_RATE_NUM 8 + +#define LEGACY_RATE_NUM 12 + +#define HT_RATE_NUM_4SS 32 +#define VHT_RATE_NUM_4SS 40 + +#define HT_RATE_NUM_3SS 24 +#define VHT_RATE_NUM_3SS 30 + +#define HT_RATE_NUM_2SS 16 +#define VHT_RATE_NUM_2SS 20 + +#define HT_RATE_NUM_1SS 8 +#define VHT_RATE_NUM_1SS 10 +#if (defined(PHYDM_COMPILE_ABOVE_4SS)) + #define HT_RATE_NUM HT_RATE_NUM_4SS + #define VHT_RATE_NUM VHT_RATE_NUM_4SS +#elif (defined(PHYDM_COMPILE_ABOVE_3SS)) + #define HT_RATE_NUM HT_RATE_NUM_3SS + #define VHT_RATE_NUM VHT_RATE_NUM_3SS +#elif (defined(PHYDM_COMPILE_ABOVE_2SS)) + #define HT_RATE_NUM HT_RATE_NUM_2SS + #define VHT_RATE_NUM VHT_RATE_NUM_2SS +#else + #define HT_RATE_NUM HT_RATE_NUM_1SS + #define VHT_RATE_NUM VHT_RATE_NUM_1SS +#endif + +#define LOW_BW_RATE_NUM VHT_RATE_NUM + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/ +#define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/ +#define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/ +#else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/ +#define SECOND_CH_AT_LSB 1 /*@primary CH @ MSB, SD8: HT_2NDCH_OFFSET_BELOW*/ +#define SECOND_CH_AT_USB 2 /*@primary CH @ LSB, SD8: HT_2NDCH_OFFSET_ABOVE*/ +#endif + +enum phydm_ic_ip { + PHYDM_IC_N = 0, + PHYDM_IC_AC = 1, + PHYDM_IC_JGR3 = 2 +}; + +enum phydm_phy_sts_type { + PHYDM_PHYSTS_TYPE_1 = 1, + PHYDM_PHYSTS_TYPE_2 = 2, + PHYDM_PHYSTS_TYPE_3 = 3 +}; + +/* ODM_CMNINFO_CUT_VER */ +enum odm_cut_version { + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + ODM_CUT_G = 6, + ODM_CUT_H = 7, + ODM_CUT_I = 8, + ODM_CUT_J = 9, + ODM_CUT_K = 10, + ODM_CUT_L = 11, + ODM_CUT_M = 12, + ODM_CUT_N = 13, + ODM_CUT_O = 14, + ODM_CUT_TEST = 15, +}; + +/* ODM_CMNINFO_FAB_VER */ +enum odm_fab { + ODM_TSMC = 0, + ODM_UMC = 1, +}; + +/* ODM_CMNINFO_OP_MODE */ +enum odm_operation_mode { + ODM_NO_LINK = BIT(0), + ODM_LINK = BIT(1), + ODM_SCAN = BIT(2), + ODM_POWERSAVE = BIT(3), + ODM_AP_MODE = BIT(4), + ODM_CLIENT_MODE = BIT(5), + ODM_AD_HOC = BIT(6), + ODM_WIFI_DIRECT = BIT(7), + ODM_WIFI_DISPLAY = BIT(8), +}; + +/* ODM_CMNINFO_WM_MODE */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +enum odm_wireless_mode { + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT(0), + ODM_WM_G = BIT(1), + ODM_WM_A = BIT(2), + ODM_WM_N24G = BIT(3), + ODM_WM_N5G = BIT(4), + ODM_WM_AUTO = BIT(5), + ODM_WM_AC = BIT(6), +}; +#else +enum odm_wireless_mode { + ODM_WM_UNKNOWN = 0x00,/*@0x0*/ + ODM_WM_A = BIT(0), /* @0x1*/ + ODM_WM_B = BIT(1), /* @0x2*/ + ODM_WM_G = BIT(2),/* @0x4*/ + ODM_WM_AUTO = BIT(3),/* @0x8*/ + ODM_WM_N24G = BIT(4),/* @0x10*/ + ODM_WM_N5G = BIT(5),/* @0x20*/ + ODM_WM_AC_5G = BIT(6),/* @0x40*/ + ODM_WM_AC_24G = BIT(7),/* @0x80*/ + ODM_WM_AC_ONLY = BIT(8),/* @0x100*/ + ODM_WM_MAX = BIT(11)/* @0x800*/ + +}; +#endif + +/* ODM_CMNINFO_BAND */ +enum odm_band_type { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + ODM_BAND_2_4G = BIT(0), + ODM_BAND_5G = BIT(1), +#else + ODM_BAND_2_4G = 0, + ODM_BAND_5G, + ODM_BAND_ON_BOTH, + ODM_BANDMAX +#endif +}; + +enum odm_rf_band { + ODM_RF_BAND_2G = 0, + ODM_RF_BAND_5G_LOW = 1, + ODM_RF_BAND_5G_MID = 2, + ODM_RF_BAND_5G_HIGH = 3, +}; + +/* ODM_CMNINFO_SEC_CHNL_OFFSET */ +enum phydm_sec_chnl_offset { + PHYDM_DONT_CARE = 0, + PHYDM_BELOW = 1, + PHYDM_ABOVE = 2 +}; + +/* ODM_CMNINFO_SEC_MODE */ +enum odm_security { + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ + ODM_SEC_SMS4 = 7, +}; + +/* ODM_CMNINFO_CHNL */ + +/* ODM_CMNINFO_BOARD_TYPE */ +enum odm_board_type { + ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ + ODM_BOARD_MINICARD = BIT(0), /* @0 = non-mini card, 1= mini card. */ + ODM_BOARD_SLIM = BIT(1), /* @0 = non-slim card, 1 = slim card */ + ODM_BOARD_BT = BIT(2), /* @0 = without BT card, 1 = with BT */ + ODM_BOARD_EXT_PA = BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */ + ODM_BOARD_EXT_LNA = BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ + ODM_BOARD_EXT_TRSW = BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */ + ODM_BOARD_EXT_PA_5G = BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */ + ODM_BOARD_EXT_LNA_5G = BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ +}; + +enum odm_package_type { + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), +}; + +enum odm_type_gpa { + TYPE_GPA0 = 0x0000, + TYPE_GPA1 = 0x0055, + TYPE_GPA2 = 0x00AA, + TYPE_GPA3 = 0x00FF, + TYPE_GPA4 = 0x5500, + TYPE_GPA5 = 0x5555, + TYPE_GPA6 = 0x55AA, + TYPE_GPA7 = 0x55FF, + TYPE_GPA8 = 0xAA00, + TYPE_GPA9 = 0xAA55, + TYPE_GPA10 = 0xAAAA, + TYPE_GPA11 = 0xAAFF, + TYPE_GPA12 = 0xFF00, + TYPE_GPA13 = 0xFF55, + TYPE_GPA14 = 0xFFAA, + TYPE_GPA15 = 0xFFFF, +}; + +enum odm_type_apa { + TYPE_APA0 = 0x0000, + TYPE_APA1 = 0x0055, + TYPE_APA2 = 0x00AA, + TYPE_APA3 = 0x00FF, + TYPE_APA4 = 0x5500, + TYPE_APA5 = 0x5555, + TYPE_APA6 = 0x55AA, + TYPE_APA7 = 0x55FF, + TYPE_APA8 = 0xAA00, + TYPE_APA9 = 0xAA55, + TYPE_APA10 = 0xAAAA, + TYPE_APA11 = 0xAAFF, + TYPE_APA12 = 0xFF00, + TYPE_APA13 = 0xFF55, + TYPE_APA14 = 0xFFAA, + TYPE_APA15 = 0xFFFF, +}; + +enum odm_type_glna { + TYPE_GLNA0 = 0x0000, + TYPE_GLNA1 = 0x0055, + TYPE_GLNA2 = 0x00AA, + TYPE_GLNA3 = 0x00FF, + TYPE_GLNA4 = 0x5500, + TYPE_GLNA5 = 0x5555, + TYPE_GLNA6 = 0x55AA, + TYPE_GLNA7 = 0x55FF, + TYPE_GLNA8 = 0xAA00, + TYPE_GLNA9 = 0xAA55, + TYPE_GLNA10 = 0xAAAA, + TYPE_GLNA11 = 0xAAFF, + TYPE_GLNA12 = 0xFF00, + TYPE_GLNA13 = 0xFF55, + TYPE_GLNA14 = 0xFFAA, + TYPE_GLNA15 = 0xFFFF, +}; + +enum odm_type_alna { + TYPE_ALNA0 = 0x0000, + TYPE_ALNA1 = 0x0055, + TYPE_ALNA2 = 0x00AA, + TYPE_ALNA3 = 0x00FF, + TYPE_ALNA4 = 0x5500, + TYPE_ALNA5 = 0x5555, + TYPE_ALNA6 = 0x55AA, + TYPE_ALNA7 = 0x55FF, + TYPE_ALNA8 = 0xAA00, + TYPE_ALNA9 = 0xAA55, + TYPE_ALNA10 = 0xAAAA, + TYPE_ALNA11 = 0xAAFF, + TYPE_ALNA12 = 0xFF00, + TYPE_ALNA13 = 0xFF55, + TYPE_ALNA14 = 0xFFAA, + TYPE_ALNA15 = 0xFFFF, +}; + +#if (RTL8721D_SUPPORT) +/* ODM_CMNINFO_POWER_VOLTAGE */ +enum odm_power_voltage { + ODM_POWER_18V = 0, + ODM_POWER_33V = 1, +}; + +/* ODM_CMNINFO_ANTDIV_GPIO */ +enum odm_antdiv_gpio { + ANTDIV_GPIO_PA2PA4 = 0, + ANTDIV_GPIO_PA5PA6 = 1, + ANTDIV_GPIO_PA12PA13 = 2, + ANTDIV_GPIO_PA14PA15 = 3, + ANTDIV_GPIO_PA16PA17 = 4, + ANTDIV_GPIO_PB1PB2 = 5, + ANTDIV_GPIO_PB26PB29 = 6, + ANTDIV_GPIO_PB1PB2PB26 = 7, // add by Jiao Qi for AmebaD SP3T only +}; + +/* ODM_CMNINFO_PEAK_DETECT_MODE */ +enum odm_peak_detect_mode { + ODM_PD_DIS = 0, + ODM_PD_ENG = 1, + ODM_PD_ENA = 2, + ODM_PD_ENALL = 3, +}; +#endif + +#define PAUSE_FAIL 0 +#define PAUSE_SUCCESS 1 + +enum odm_parameter_init { + ODM_PRE_SETTING = 0, + ODM_POST_SETTING = 1, + ODM_INIT_FW_SETTING = 2, + ODM_PRE_RF_SET = 3, + ODM_POST_RF_SET = 4 +}; + +enum phydm_pause_type { + PHYDM_PAUSE = 1, /*Pause & Set new value*/ + PHYDM_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/ + PHYDM_RESUME = 3 +}; + +enum phydm_backup_type { + PHYDM_BACKUP = 1, + PHYDM_RESTORE = 2 +}; + +enum phydm_pause_level { + PHYDM_PAUSE_RELEASE = -1, + PHYDM_PAUSE_LEVEL_0 = 0, /* @Low Priority function */ + PHYDM_PAUSE_LEVEL_1 = 1, /* @Middle Priority function */ + PHYDM_PAUSE_LEVEL_2 = 2, /* @High priority function (ex: Check hang function) */ + PHYDM_PAUSE_LEVEL_3 = 3, /* @Debug function (the highest priority) */ + PHYDM_PAUSE_MAX_NUM = 4 +}; + +enum phydm_dis_hw_fun { + HW_FUN_DIS = 0, /*@Disable a cetain HW function & backup the original value*/ + HW_FUN_RESUME = 1 /*Revert */ +}; + +#endif diff --git a/hal/phydm/phydm_precomp.h b/hal/phydm/phydm_precomp.h new file mode 100644 index 0000000..4fda5a3 --- /dev/null +++ b/hal/phydm/phydm_precomp.h @@ -0,0 +1,652 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "phydm_types.h" +#include "halrf/halrf_features.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "Precomp.h" /* @We need to include mp_precomp.h due to batch file setting. */ +#else + #define TEST_FALG___ 1 +#endif + +/* @2 Config Flags and Structs - defined by each ODM type */ + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../8192cd_cfg.h" + #include "../odm_inc.h" + + #include "../8192cd.h" + #include "../8192cd_util.h" + #include "../8192cd_hw.h" + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + + #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) + #define INIT_TIMER_EVENT_ENTRY(_entry, _func, _data) \ + do { \ + _rtw_init_listhead(&(_entry)->list); \ + (_entry)->data = (_data); \ + (_entry)->function = (_func); \ + } while (0) + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #include "../wifi.h" + #include "rtl_phydm.h" + #elif defined(DM_ODM_CE_MAC80211_V2) + #include "../main.h" + #include "../hw.h" + #include "../fw.h" + #endif + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "mp_precomp.h" + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #include + #include + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #define __PACK +#endif + +/* @2 OutSrc Header Files */ + +#include "phydm.h" +#include "phydm_hwconfig.h" +#include "phydm_phystatus.h" +#include "phydm_debug.h" +#include "phydm_regdefine11ac.h" +#include "phydm_regdefine11n.h" +#include "phydm_interface.h" +#include "phydm_reg.h" +#include "halrf/halrf_debug.h" + +#ifndef RTL8188E_SUPPORT + #define RTL8188E_SUPPORT 0 +#endif +#ifndef RTL8812A_SUPPORT + #define RTL8812A_SUPPORT 0 +#endif +#ifndef RTL8821A_SUPPORT + #define RTL8821A_SUPPORT 0 +#endif +#ifndef RTL8192E_SUPPORT + #define RTL8192E_SUPPORT 0 +#endif +#ifndef RTL8723B_SUPPORT + #define RTL8723B_SUPPORT 0 +#endif +#ifndef RTL8814A_SUPPORT + #define RTL8814A_SUPPORT 0 +#endif +#ifndef RTL8881A_SUPPORT + #define RTL8881A_SUPPORT 0 +#endif +#ifndef RTL8822B_SUPPORT + #define RTL8822B_SUPPORT 0 +#endif +#ifndef RTL8703B_SUPPORT + #define RTL8703B_SUPPORT 0 +#endif +#ifndef RTL8195A_SUPPORT + #define RTL8195A_SUPPORT 0 +#endif +#ifndef RTL8188F_SUPPORT + #define RTL8188F_SUPPORT 0 +#endif +#ifndef RTL8723D_SUPPORT + #define RTL8723D_SUPPORT 0 +#endif +#ifndef RTL8197F_SUPPORT + #define RTL8197F_SUPPORT 0 +#endif +#ifndef RTL8821C_SUPPORT + #define RTL8821C_SUPPORT 0 +#endif +#ifndef RTL8814B_SUPPORT + #define RTL8814B_SUPPORT 0 +#endif +#ifndef RTL8198F_SUPPORT + #define RTL8198F_SUPPORT 0 +#endif +#ifndef RTL8710B_SUPPORT + #define RTL8710B_SUPPORT 0 +#endif +#ifndef RTL8192F_SUPPORT + #define RTL8192F_SUPPORT 0 +#endif +#ifndef RTL8822C_SUPPORT + #define RTL8822C_SUPPORT 0 +#endif +#ifndef RTL8195B_SUPPORT + #define RTL8195B_SUPPORT 0 +#endif +#ifndef RTL8812F_SUPPORT + #define RTL8812F_SUPPORT 0 +#endif +#ifndef RTL8197G_SUPPORT + #define RTL8197G_SUPPORT 0 +#endif +#ifndef RTL8721D_SUPPORT + #define RTL8721D_SUPPORT 0 +#endif +#ifndef RTL8710C_SUPPORT + #define RTL8710C_SUPPORT 0 +#endif +#ifndef RTL8723F_SUPPORT + #define RTL8723F_SUPPORT 0 +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \ + (!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2)) + +void phy_set_tx_power_limit( + struct dm_struct *dm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit); + +void phy_set_tx_power_limit_ex(struct dm_struct *dm, u8 regulation, u8 band, + u8 bandwidth, u8 rate_section, u8 rf_path, + u8 channel, s8 power_limit); + +enum hal_status +rtw_phydm_fw_iqk( + struct dm_struct *dm, + u8 clear, + u8 segment); + +enum hal_status +rtw_phydm_fw_dpk( + struct dm_struct *dm); + +enum hal_status +rtw_phydm_cfg_phy_para( + struct dm_struct *dm, + enum phydm_halmac_param config_type, + u32 offset, + u32 data, + u32 mask, + enum rf_path e_rf_path, + u32 delay_time); + +#endif + +#if RTL8188E_SUPPORT == 1 + #define RTL8188E_T_SUPPORT 1 + #ifdef CONFIG_SFW_SUPPORTED + #define RTL8188E_S_SUPPORT 1 + #else + #define RTL8188E_S_SUPPORT 0 + #endif + + #include "rtl8188e/hal8188erateadaptive.h" /* @for RA,Power training */ + #include "rtl8188e/halhwimg8188e_mac.h" + #include "rtl8188e/halhwimg8188e_rf.h" + #include "rtl8188e/halhwimg8188e_bb.h" + #include "rtl8188e/phydm_regconfig8188e.h" + #include "rtl8188e/phydm_rtl8188e.h" + #include "rtl8188e/hal8188ereg.h" + #include "rtl8188e/version_rtl8188e.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8188e_hal.h" + #include "halrf/rtl8188e/halrf_8188e_ce.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8188e/halrf_8188e_win.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8188e/halrf_8188e_ap.h" + #endif +#endif /* @88E END */ + +#if (RTL8192E_SUPPORT == 1) + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/ + #endif + + #include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */ + #include "rtl8192e/version_rtl8192e.h" + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8192e/halhwimg8192e_bb.h" + #include "rtl8192e/halhwimg8192e_mac.h" + #include "rtl8192e/halhwimg8192e_rf.h" + #include "rtl8192e/phydm_regconfig8192e.h" + #include "rtl8192e/hal8192ereg.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192e_hal.h" + #endif +#endif /* @92E END */ + +#if (RTL8812A_SUPPORT == 1) + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8812a/halrf_8812a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8812a/halrf_8812a_ap.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8812a/halrf_8812a_ce.h" + #endif + + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8812a/halhwimg8812a_bb.h" + #include "rtl8812a/halhwimg8812a_mac.h" + #include "rtl8812a/halhwimg8812a_rf.h" + #include "rtl8812a/phydm_regconfig8812a.h" + #endif + #include "rtl8812a/phydm_rtl8812a.h" + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8812a_hal.h" + #endif + #include "rtl8812a/version_rtl8812a.h" + +#endif /* @8812 END */ + +#if (RTL8814A_SUPPORT == 1) + + #include "rtl8814a/halhwimg8814a_mac.h" + #include "rtl8814a/halhwimg8814a_bb.h" + #include "rtl8814a/version_rtl8814a.h" + #include "rtl8814a/phydm_rtl8814a.h" + #include "halrf/rtl8814a/halhwimg8814a_rf.h" + #include "halrf/rtl8814a/version_rtl8814a_rf.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8814a/halrf_8814a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8814a/halrf_8814a_ce.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8814a/halrf_8814a_ap.h" + #endif + #include "rtl8814a/phydm_regconfig8814a.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8814a_hal.h" + #include "halrf/rtl8814a/halrf_iqk_8814a.h" + #endif +#endif /* @8814 END */ + +#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8821a/halrf_iqk_8821a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h" + #else + #include "halrf/rtl8821a/halrf_iqk_8821a_ap.h" + #endif +#endif + +#if (RTL8723B_SUPPORT == 1) + #include "rtl8723b/halhwimg8723b_mac.h" + #include "rtl8723b/halhwimg8723b_rf.h" + #include "rtl8723b/halhwimg8723b_bb.h" + #include "rtl8723b/phydm_regconfig8723b.h" + #include "rtl8723b/phydm_rtl8723b.h" + #include "rtl8723b/hal8723breg.h" + #include "rtl8723b/version_rtl8723b.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8723b/halrf_8723b_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8723b/halrf_8723b_ce.h" + #include "rtl8723b/halhwimg8723b_mp.h" + #include "rtl8723b_hal.h" + #else + #include "halrf/rtl8723b/halrf_8723b_ap.h" + #endif +#endif + +#if (RTL8821A_SUPPORT == 1) + #include "rtl8821a/halhwimg8821a_mac.h" + #include "rtl8821a/halhwimg8821a_rf.h" + #include "rtl8821a/halhwimg8821a_bb.h" + #include "rtl8821a/phydm_regconfig8821a.h" + #include "rtl8821a/phydm_rtl8821a.h" + #include "rtl8821a/version_rtl8821a.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "halrf/rtl8821a/halrf_8821a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "halrf/rtl8821a/halrf_8821a_ce.h" + #include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/ + #include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/ + #include "rtl8812a_hal.h" + #else + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) +#include "../halmac/halmac_reg2.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) +#include "../halmac/halmac_reg2.h" +#endif + + +#if (RTL8822B_SUPPORT == 1) + #include "rtl8822b/halhwimg8822b_mac.h" + #include "rtl8822b/halhwimg8822b_bb.h" + #include "rtl8822b/phydm_regconfig8822b.h" + #include "halrf/rtl8822b/halrf_8822b.h" + #include "halrf/rtl8822b/halhwimg8822b_rf.h" + #include "halrf/rtl8822b/version_rtl8822b_rf.h" + #include "rtl8822b/phydm_rtl8822b.h" + #include "rtl8822b/phydm_hal_api8822b.h" + #include "rtl8822b/version_rtl8822b.h" + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #include "../halmac/halmac_reg_8822b.h" + #elif defined(DM_ODM_CE_MAC80211_V2) + #include "../halmac/halmac_reg_8822b.h" + #else + #include /* @struct HAL_DATA_TYPE */ + #include /* @RX_SMOOTH_FACTOR, reg definition and etc.*/ + #endif + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #endif + +#endif + +#if (RTL8703B_SUPPORT == 1) + #include "rtl8703b/phydm_rtl8703b.h" + #include "rtl8703b/phydm_regconfig8703b.h" + #include "rtl8703b/halhwimg8703b_mac.h" + #include "rtl8703b/halhwimg8703b_rf.h" + #include "rtl8703b/halhwimg8703b_bb.h" + #include "halrf/rtl8703b/halrf_8703b.h" + #include "rtl8703b/version_rtl8703b.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8703b_hal.h" + #endif +#endif + +#if (RTL8188F_SUPPORT == 1) + #include "rtl8188f/halhwimg8188f_mac.h" + #include "rtl8188f/halhwimg8188f_rf.h" + #include "rtl8188f/halhwimg8188f_bb.h" + #include "rtl8188f/hal8188freg.h" + #include "rtl8188f/phydm_rtl8188f.h" + #include "rtl8188f/phydm_regconfig8188f.h" + #include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/ + #include "rtl8188f/version_rtl8188f.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8188f_hal.h" + #endif +#endif + +#if (RTL8723D_SUPPORT == 1) + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + + #include "rtl8723d/halhwimg8723d_bb.h" + #include "rtl8723d/halhwimg8723d_mac.h" + #include "rtl8723d/halhwimg8723d_rf.h" + #include "rtl8723d/phydm_regconfig8723d.h" + #include "rtl8723d/hal8723dreg.h" + #include "rtl8723d/phydm_rtl8723d.h" + #include "halrf/rtl8723d/halrf_8723d.h" + #include "rtl8723d/version_rtl8723d.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #else + #include "rtl8723d_hal.h" + #endif + #endif +#endif /* @8723D End */ + +#if (RTL8710B_SUPPORT == 1) + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + + #include "rtl8710b/halhwimg8710b_bb.h" + #include "rtl8710b/halhwimg8710b_mac.h" + #include "rtl8710b/phydm_regconfig8710b.h" + #include "rtl8710b/hal8710breg.h" + #include "rtl8710b/phydm_rtl8710b.h" + #include "halrf/rtl8710b/halrf_8710b.h" + #include "halrf/rtl8710b/halhwimg8710b_rf.h" + #include "halrf/rtl8710b/version_rtl8710b_rf.h" + #include "rtl8710b/version_rtl8710b.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8710b_hal.h" + #endif +#endif /* @8710B End */ + +#if (RTL8197F_SUPPORT == 1) + #include "rtl8197f/halhwimg8197f_mac.h" + #include "rtl8197f/halhwimg8197f_bb.h" + #include "rtl8197f/phydm_hal_api8197f.h" + #include "rtl8197f/version_rtl8197f.h" + #include "rtl8197f/phydm_rtl8197f.h" + #include "rtl8197f/phydm_regconfig8197f.h" + #include "halrf/rtl8197f/halrf_8197f.h" + #include "halrf/rtl8197f/halrf_iqk_8197f.h" + #include "halrf/rtl8197f/halrf_dpk_8197f.h" + #include "halrf/rtl8197f/halhwimg8197f_rf.h" + #include "halrf/rtl8197f/version_rtl8197f_rf.h" +#endif + +#if (RTL8821C_SUPPORT == 1) + #include "rtl8821c/phydm_hal_api8821c.h" + #include "rtl8821c/halhwimg8821c_mac.h" + #include "rtl8821c/halhwimg8821c_bb.h" + #include "rtl8821c/phydm_regconfig8821c.h" + #include "rtl8821c/phydm_rtl8821c.h" + #include "halrf/rtl8821c/halrf_8821c.h" + #include "halrf/rtl8821c/halhwimg8821c_rf.h" + #include "halrf/rtl8821c/version_rtl8821c_rf.h" + #include "rtl8821c/version_rtl8821c.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef DM_ODM_CE_MAC80211 + #include "../halmac/halmac_reg_8821c.h" + #else + #include "rtl8821c_hal.h" + #endif + #endif +#endif + +#if (RTL8192F_SUPPORT == 1) + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192f_hal.h"/*need to before rf.h*/ + #endif + #include "rtl8192f/halhwimg8192f_mac.h" + #include "rtl8192f/halhwimg8192f_bb.h" + #include "rtl8192f/phydm_hal_api8192f.h" + #include "rtl8192f/version_rtl8192f.h" + #include "rtl8192f/phydm_rtl8192f.h" + #include "rtl8192f/phydm_regconfig8192f.h" + #include "halrf/rtl8192f/halrf_8192f.h" + #include "halrf/rtl8192f/halhwimg8192f_rf.h" + #include "halrf/rtl8192f/version_rtl8192f_rf.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8192f/halrf_dpk_8192f.h" + #endif +#endif + +#if (RTL8721D_SUPPORT == 1) + #include "halrf/rtl8721d/halrf_btiqk_8721d.h" + #include "halrf/rtl8721d/halrf_rfk_init_8721d.h" + #include "halrf/rtl8721d/halrf_dpk_8721d.h" + #include "halrf/rtl8721d/halrf_8721d.h" + #include "halrf/rtl8721d/halhwimg8721d_rf.h" + #include "halrf/rtl8721d/version_rtl8721d_rf.h" + #include "rtl8721d/phydm_hal_api8721d.h" + #include "rtl8721d/phydm_regconfig8721d.h" + #include "rtl8721d/halhwimg8721d_mac.h" + #include "rtl8721d/halhwimg8721d_bb.h" + #include "rtl8721d/version_rtl8721d.h" + #include "rtl8721d/phydm_rtl8721d.h" + #include "rtl8721d/hal8721dreg.h" + #include + #if 0 + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8721d_hal.h" + #endif + #endif +#endif + +#if (RTL8710C_SUPPORT == 1) + #include "halrf/rtl8710c/halrf_8710c.h" + #include "halrf/rtl8710c/halhwimg8710c_rf.h" + //#include "halrf/rtl8710c/version_rtl8710c_rf.h" + #include "rtl8710c/phydm_hal_api8710c.h" + #include "rtl8710c/phydm_regconfig8710c.h" + #include "rtl8710c/halhwimg8710c_mac.h" + #include "rtl8710c/halhwimg8710c_bb.h" + #include "rtl8710c/version_rtl8710c.h" + #include "rtl8710c/phydm_rtl8710c.h" + //#include "rtl8710c/hal87100creg.h" + #include /*@HAL_DATA_TYPE*/ + #if 0 + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "halrf/rtl8710c/halrf_dpk_8710c.h" + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8710c_hal.h" + #endif + #endif +#endif + +#if (RTL8195B_SUPPORT == 1) + #include "halrf/rtl8195b/halrf_8195b.h" + #include "halrf/rtl8195b/halhwimg8195b_rf.h" + #include "halrf/rtl8195b/version_rtl8195b_rf.h" + #include "rtl8195b/phydm_hal_api8195b.h" + #include "rtl8195b/phydm_regconfig8195b.h" + #include "rtl8195b/halhwimg8195b_mac.h" + #include "rtl8195b/halhwimg8195b_bb.h" + #include "rtl8195b/version_rtl8195b.h" + #include /*@HAL_DATA_TYPE*/ +#endif + +#if (RTL8198F_SUPPORT == 1) + #include "rtl8198f/phydm_regconfig8198f.h" + #include "rtl8198f/phydm_hal_api8198f.h" + #include "rtl8198f/halhwimg8198f_mac.h" + #include "rtl8198f/halhwimg8198f_bb.h" + #include "rtl8198f/version_rtl8198f.h" + #include "halrf/rtl8198f/halrf_8198f.h" + #include "halrf/rtl8198f/halrf_iqk_8198f.h" + #include "halrf/rtl8198f/halhwimg8198f_rf.h" + #include "halrf/rtl8198f/version_rtl8198f_rf.h" +#endif + +#if (RTL8822C_SUPPORT) + #include "rtl8822c/halhwimg8822c_bb.h" + #include "rtl8822c/phydm_regconfig8822c.h" + #include "rtl8822c/phydm_hal_api8822c.h" + #include "rtl8822c/version_rtl8822c.h" + #include "rtl8822c/phydm_rtl8822c.h" + #include "halrf/rtl8822c/halrf_8822c.h" + #include "halrf/rtl8822c/halhwimg8822c_rf.h" + #include "halrf/rtl8822c/version_rtl8822c_rf.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + /* @struct HAL_DATA_TYPE */ + #include + /* @RX_SMOOTH_FACTOR, reg definition and etc.*/ + #include + #endif +#endif +#if (RTL8814B_SUPPORT == 1) + #include "rtl8814b/halhwimg8814b_bb.h" + #include "rtl8814b/phydm_regconfig8814b.h" + #include "halrf/rtl8814b/halrf_8814b.h" + #include "halrf/rtl8814b/halhwimg8814b_rf.h" + #include "halrf/rtl8814b/version_rtl8814b_rf.h" + #include "rtl8814b/phydm_hal_api8814b.h" + #include "rtl8814b/version_rtl8814b.h" + #include "rtl8814b/phydm_extraagc8814b.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include /* @struct HAL_DATA_TYPE */ + #include /* @RX_SMOOTH_FACTOR, reg definition and etc.*/ + #endif +#endif +#if (RTL8812F_SUPPORT) + #include "rtl8812f/halhwimg8812f_bb.h" + #include "rtl8812f/phydm_regconfig8812f.h" + #include "halrf/rtl8812f/halrf_8812f.h" + #include "halrf/rtl8812f/halhwimg8812f_rf.h" + #include "halrf/rtl8812f/version_rtl8812f_rf.h" + #include "rtl8812f/phydm_hal_api8812f.h" + #include "rtl8812f/version_rtl8812f.h" + #include "rtl8812f/phydm_rtl8812f.h" +#endif +#if (RTL8197G_SUPPORT) + #include "rtl8197g/halhwimg8197g_bb.h" + #include "rtl8197g/halhwimg8197g_mac.h" + #include "rtl8197g/phydm_regconfig8197g.h" + #include "halrf/rtl8197g/halrf_8197g.h" + #include "halrf/rtl8197g/halhwimg8197g_rf.h" + #include "halrf/rtl8197g/version_rtl8197g_rf.h" + #include "rtl8197g/phydm_hal_api8197g.h" + #include "rtl8197g/version_rtl8197g.h" + #include "rtl8197g/phydm_rtl8197g.h" +#endif +#if (RTL8723F_SUPPORT) + #include "rtl8723f/halhwimg8723f_bb.h" + #include "rtl8723f/halhwimg8723f_mac.h" + #include "rtl8723f/phydm_regconfig8723f.h" + #include "halrf/rtl8723f/halrf_8723f.h" + #include "halrf/rtl8723f/halhwimg8723f_rf.h" + #include "halrf/rtl8723f/version_rtl8723f_rf.h" + #include "halrf/rtl8723f/halrf_iqk_8723f.h" + #include "halrf/rtl8723f/halrf_dpk_8723f.h" + #include "halrf/rtl8723f/halrf_txgapk_8723f.h" + #include "halrf/rtl8723f/halrf_tssi_8723f.h" + #include "halrf/rtl8723f/halrf_rfk_init_8723f.h" + #include "rtl8723f/phydm_hal_api8723f.h" + #include "rtl8723f/version_rtl8723f.h" + #include "rtl8723f/phydm_rtl8723f.h" + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + /* @struct HAL_DATA_TYPE */ + #include + /* @RX_SMOOTH_FACTOR, reg definition and etc.*/ + #include + #endif +#endif +#endif /* @__ODM_PRECOMP_H__ */ diff --git a/hal/phydm/phydm_primary_cca.c b/hal/phydm/phydm_primary_cca.c new file mode 100644 index 0000000..dec6c53 --- /dev/null +++ b/hal/phydm/phydm_primary_cca.c @@ -0,0 +1,173 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" +#ifdef PHYDM_PRIMARY_CCA + +void phydm_write_dynamic_cca( + void *dm_void, + u8 curr_mf_state + + ) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + if (pri_cca->mf_state == curr_mf_state) + return; + + if (dm->support_ic_type & ODM_IC_11N_SERIES) { + if (curr_mf_state == MF_USC_LSC) { + odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC); + /*@40M OFDM MF CCA threshold*/ + odm_set_bb_reg(dm, R_0xc84, 0xf0000000, + pri_cca->cca_th_40m_bkp); + } else { + odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state); + /*@40M OFDM MF CCA threshold*/ + odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0); + } + } + + pri_cca->mf_state = curr_mf_state; + PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n", + ((curr_mf_state == MF_USC_LSC) ? "D" : + ((curr_mf_state == MF_LSC) ? "L" : "U")), curr_mf_state); +} + +void phydm_primary_cca_reset( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n"); + pri_cca->mf_state = 0xff; + pri_cca->pre_bw = (enum channel_width)0xff; + phydm_write_dynamic_cca(dm, MF_USC_LSC); +} + +void phydm_primary_cca_11n( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + enum channel_width curr_bw = (enum channel_width)*dm->band_width; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n"); + + if (pri_cca->pri_cca_is_become_linked) { + phydm_primary_cca_reset(dm); + pri_cca->pri_cca_is_become_linked = dm->is_linked; + } + return; + } else { + if (!pri_cca->pri_cca_is_become_linked) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n"); + pri_cca->pri_cca_is_become_linked = dm->is_linked; + } + } + + if (curr_bw != pri_cca->pre_bw) { + PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n"); + pri_cca->pre_bw = curr_bw; + + if (curr_bw == CHANNEL_WIDTH_40) { + if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) { + /* Primary CH @ upper sideband*/ + PHYDM_DBG(dm, DBG_PRI_CCA, + "BW40M, Primary CH at USB\n"); + phydm_write_dynamic_cca(dm, MF_USC); + } else { + /*Primary CH @ lower sideband*/ + PHYDM_DBG(dm, DBG_PRI_CCA, + "BW40M, Primary CH at LSB\n"); + phydm_write_dynamic_cca(dm, MF_LSC); + } + } else { + PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n"); + phydm_primary_cca_reset(dm); + } + } +} + +boolean +odm_dynamic_primary_cca_dup_rts(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + return pri_cca->dup_rts_flag; +} + +void phydm_primary_cca_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; + + PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n"); +#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) + pri_cca->dup_rts_flag = 0; + pri_cca->intf_flag = 0; + pri_cca->intf_type = 0; + pri_cca->monitor_flag = 0; + pri_cca->pri_cca_flag = 0; + pri_cca->ch_offset = 0; +#endif + pri_cca->mf_state = 0xff; + pri_cca->pre_bw = (enum channel_width)0xff; + pri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000); +} + +void phydm_primary_cca(void *dm_void) +{ +#ifdef PHYDM_PRIMARY_CCA + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ic_type & ODM_IC_11N_SERIES)) + return; + + if (!(dm->support_ability & ODM_BB_PRIMARY_CCA)) + return; + + phydm_primary_cca_11n(dm); + +#endif +} +#endif diff --git a/hal/phydm/phydm_primary_cca.h b/hal/phydm/phydm_primary_cca.h new file mode 100644 index 0000000..1978586 --- /dev/null +++ b/hal/phydm/phydm_primary_cca.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_PRIMARYCCA_H__ +#define __PHYDM_PRIMARYCCA_H__ + +#ifdef PHYDM_PRIMARY_CCA +#define PRIMARYCCA_VERSION "2.0" + +/*@============================================================*/ +/*@Definition */ +/*@============================================================*/ + +#define OFDMCCA_TH 500 +#define bw_ind_bias 500 +#define PRI_CCA_MONITOR_TIME 30 + +/*@============================================================*/ +/*structure and define*/ +/*@============================================================*/ +enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/ + MF_USC_LSC = 0, + MF_LSC = 1, + MF_USC = 2 +}; + +struct phydm_pricca_struct { + #if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) + u8 pri_cca_flag; + u8 intf_flag; + u8 intf_type; + u8 monitor_flag; + u8 ch_offset; + #endif + u8 dup_rts_flag; + u8 cca_th_40m_bkp; /*@c84[31:28]*/ + enum channel_width pre_bw; + u8 pri_cca_is_become_linked; + u8 mf_state; +}; + +/*@============================================================*/ +/*@function prototype*/ +/*@============================================================*/ +void phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state); + +boolean odm_dynamic_primary_cca_dup_rts(void *dm_void); + +void phydm_primary_cca_init(void *dm_void); + +void phydm_primary_cca(void *dm_void); +#endif /*@#ifdef PHYDM_PRIMARY_CCA*/ +#endif /*@#ifndef __PHYDM_PRIMARYCCA_H__*/ + diff --git a/hal/phydm/phydm_psd.c b/hal/phydm/phydm_psd.c new file mode 100644 index 0000000..8a19160 --- /dev/null +++ b/hal/phydm/phydm_psd.c @@ -0,0 +1,564 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/****************************************************************************** + * include files + *****************************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CONFIG_PSD_TOOL +u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u32 psd_report = 0; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #if(RTL8723F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8723F)) { + odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff80000, psd_tone_idx & 0x7ff); + /*PSD trigger start*/ + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 1); + ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7)); + /*PSD trigger stop*/ + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 0); + } + #endif + #if 0 + odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff); + odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26), + psd_tone_idx >> 10); + /*PSD trigger start*/ + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1); + ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7)); + /*PSD trigger stop*/ + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0); + #endif + } else if (dm->support_ic_type & (ODM_RTL8721D | + ODM_RTL8710C)) { + odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx); + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1); + /*PSD trigger start*/ + ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7)); + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0); + /*PSD trigger stop*/ + } else { + odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); + /*PSD trigger start*/ + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1); + ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7)); + /*PSD trigger stop*/ + odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0); + } + + /*Get PSD Report*/ + if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D | + ODM_RTL8710C)) { + psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, + 0xffffff); + psd_report = psd_report >> 5; + } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #if(RTL8723F_SUPPORT) + if (dm->support_ic_type & (ODM_RTL8723F)) { + psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, + 0x1ffffff); + } + #endif + #if 0 + psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, + 0xffffff); + #endif + } else { + psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, + 0xffff); + } + psd_report = odm_convert_to_db((u64)psd_report) + igi; + + return psd_report; +} + +u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127}; +u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67}; + +u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u32 i = 0, mod_tone_idx = 0; + u32 t = 0; + u16 fft_max_half_bw = 0; + u16 psd_fc_channel = dm_psd_table->psd_fc_channel; + u8 ag_rf_mode_reg = 0; + u8 is_5G = 0; + u32 psd_result_tmp = 0; + u8 psd_result = 0; + u8 psd_result_cali_tone[7] = {0}; + u8 psd_result_cali_val[7] = {0}; + u8 noise_idx = 0; + u8 set_result = 0; + u32 igi_tmp = 0x6e; + + if (dm->support_ic_type == ODM_RTL8821) { + odm_move_memory(dm, psd_result_cali_tone, + psd_result_cali_tone_8821, 7); + odm_move_memory(dm, psd_result_cali_val, + psd_result_cali_val_8821, 7); + } + + dm_psd_table->psd_in_progress = 1; + + PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n"); + + /* @[Stop DIG]*/ + /* @IGI target at 0dBm & make it can't CCA*/ + if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1, + &igi_tmp) == PAUSE_FAIL) { + return PHYDM_SET_FAIL; + } + + ODM_delay_us(10); + + if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) { + phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, + 1, &igi_tmp); + return PHYDM_SET_FAIL; + } + + /* @[Set IGI]*/ + phydm_write_dig_reg(dm, (u8)igi); + + /* @[Backup RF Reg]*/ + dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, + RFREG_MASK); + dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18, + RFREG_MASK); + + if (psd_fc_channel > 14) { + is_5G = 1; + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G)) { + #if 0 + if (psd_fc_channel < 80) + ag_rf_mode_reg = 0x1; + else if (psd_fc_channel >= 80 && psd_fc_channel <= 140) + ag_rf_mode_reg = 0x3; + else if (psd_fc_channel > 140) + ag_rf_mode_reg = 0x5; + #endif + } else if (dm->support_ic_type & ODM_RTL8723F) { + if (psd_fc_channel < 80) + ag_rf_mode_reg = 0x1; + else if (psd_fc_channel >= 80 && psd_fc_channel <= 144) + ag_rf_mode_reg = 0x5; + else if (psd_fc_channel > 144) + ag_rf_mode_reg = 0x9; + } else if (dm->support_ic_type == ODM_RTL8721D) { + if (psd_fc_channel >= 36 && psd_fc_channel <= 64) + ag_rf_mode_reg = 0x1; + else if (psd_fc_channel >= 100 && psd_fc_channel <= 140) + ag_rf_mode_reg = 0x5; + else if (psd_fc_channel > 140) + ag_rf_mode_reg = 0x9; + } else { + if (psd_fc_channel >= 36 && psd_fc_channel <= 64) + ag_rf_mode_reg = 0x1; + else if (psd_fc_channel >= 100 && psd_fc_channel <= 140) + ag_rf_mode_reg = 0x3; + else if (psd_fc_channel > 140) + ag_rf_mode_reg = 0x5; + } + } + + /* Set RF fc*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel); + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G); + if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F | + ODM_RTL8197G)) { + #if 0 + /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000, + dm_psd_table->psd_bw_rf_reg); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000, + dm_psd_table->psd_bw_rf_reg); + /* Set RF ag fc mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000, + ag_rf_mode_reg); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000, + ag_rf_mode_reg); + #endif + } else if (dm->support_ic_type & ODM_RTL8723F) { + /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00, + dm_psd_table->psd_bw_rf_reg); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x1c00, + dm_psd_table->psd_bw_rf_reg); + /* Set RF ag fc mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x30000, 1); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x30000, 1); + if(ag_rf_mode_reg == 1) { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 0); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 0); + } + else if(ag_rf_mode_reg == 5){ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 1); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 1); + } + else { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 2); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 2); + } + } else { + /* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + if (dm->support_ic_type == ODM_RTL8721D) { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00, + dm_psd_table->psd_bw_rf_reg); +#if (RTL8710C_SUPPORT == 1) + } else if (dm->support_ic_type == ODM_RTL8710C) { + odm_set_rf_reg(dm, RF_PATH_A, + RF_0x18, 0x1c00, + dm_psd_table->psd_bw_rf_reg); +#endif + } else { + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00, + dm_psd_table->psd_bw_rf_reg); + } + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00, + dm_psd_table->psd_bw_rf_reg); + /* Set RF ag fc mode*/ + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000, + ag_rf_mode_reg); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000, + ag_rf_mode_reg); + } + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES){ + if (dm->support_ic_type & ODM_RTL8723F) { + PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n", + odm_get_bb_reg(dm, R_0x1d70, MASKDWORD)); + PHYDM_DBG(dm, ODM_COMP_API, "RF0x19=((0x%x))\n", + odm_get_rf_reg(dm, RF_PATH_A, RF_0x19, RFREG_MASK)); + } + } else + PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n", + odm_get_bb_reg(dm, R_0xc50, MASKDWORD)); + + PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n", + odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK)); + + /* @[Stop 3-wires]*/ + phydm_stop_3_wire(dm, PHYDM_SET); + + ODM_delay_us(10); + + if (stop_point > (dm_psd_table->fft_smp_point - 1)) + stop_point = (dm_psd_table->fft_smp_point - 1); + + if (start_point > (dm_psd_table->fft_smp_point - 1)) + start_point = (dm_psd_table->fft_smp_point - 1); + + if (start_point > stop_point) + stop_point = start_point; + + for (i = start_point; i <= stop_point; i++) { + fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1; + + if (i < fft_max_half_bw) + mod_tone_idx = i + fft_max_half_bw; + else + mod_tone_idx = i - fft_max_half_bw; + + psd_result_tmp = 0; + for (t = 0; t < dm_psd_table->sw_avg_time; t++) + psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx, + igi); + psd_result = + (u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) - + dm_psd_table->psd_pwr_common_offset; + + if (dm_psd_table->fft_smp_point == 128 && + dm_psd_table->noise_k_en) { + if (i > psd_result_cali_tone[noise_idx]) + noise_idx++; + + if (noise_idx > 6) + noise_idx = 6; + + if (psd_result >= psd_result_cali_val[noise_idx]) + psd_result = psd_result - + psd_result_cali_val[noise_idx]; + else + psd_result = 0; + + dm_psd_table->psd_result[i] = psd_result; + } + + PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n", + mod_tone_idx, psd_result_cali_val[noise_idx], + psd_result); + } + + /*@[Start 3-wires]*/ + phydm_stop_3_wire(dm, PHYDM_REVERT); + + ODM_delay_us(10); + + /*@[Revert Reg]*/ + set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT); + + odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK, + dm_psd_table->rf_0x18_bkp); + odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK, + dm_psd_table->rf_0x18_bkp_b); + + PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n"); + + phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1, + &igi_tmp); + dm_psd_table->psd_in_progress = 0; + + return PHYDM_SET_SUCCESS; +} + +void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time, + u8 i_q_setting, u16 fft_smp_point, u8 ant_sel, + u8 psd_input, u8 channel, u8 noise_k_en) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u8 fft_smp_point_idx = 0; + + dm_psd_table->fft_smp_point = fft_smp_point; + + if (sw_avg_time == 0) + sw_avg_time = 1; + + dm_psd_table->sw_avg_time = sw_avg_time; + dm_psd_table->psd_fc_channel = channel; + dm_psd_table->noise_k_en = noise_k_en; + if (dm->support_ic_type & ODM_RTL8723F) { + if (fft_smp_point == 128) + fft_smp_point_idx = 3; + else if (fft_smp_point == 256) + fft_smp_point_idx = 2; + else if (fft_smp_point == 512) + fft_smp_point_idx = 1; + else if (fft_smp_point == 1024) + fft_smp_point_idx = 0; + } + else { + if (fft_smp_point == 128) + fft_smp_point_idx = 0; + else if (fft_smp_point == 256) + fft_smp_point_idx = 1; + else if (fft_smp_point == 512) + fft_smp_point_idx = 2; + else if (fft_smp_point == 1024) + fft_smp_point_idx = 3; + } + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #if (RTL8723F_SUPPORT) + odm_set_bb_reg(dm, R_0x1e8c, BIT(12) | BIT(11), hw_avg_time); + odm_set_bb_reg(dm, R_0x1e8c, BIT(14) | BIT(13), + fft_smp_point_idx); + odm_set_bb_reg(dm, R_0x1e8c, BIT(18) | BIT(17), ant_sel); + odm_set_bb_reg(dm, R_0x1e88, BIT(25) | BIT(24), psd_input); + #else + #if 0 + odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting); + odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time); + + if (fft_smp_point == 4096) { + odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2); + } else if (fft_smp_point == 2048) { + odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1); + } else { + odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0); + odm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14), + fft_smp_point_idx); + } + odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel); + odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input); + #endif + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting); + odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time); + odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14), + fft_smp_point_idx); + odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel); + odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input); + } else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) { + odm_set_bb_reg(dm, R_0x808, BIT(19) | BIT(18), i_q_setting); + odm_set_bb_reg(dm, R_0x808, BIT(21) | BIT(20), hw_avg_time); + odm_set_bb_reg(dm, R_0x808, BIT(23) | BIT(22), + fft_smp_point_idx); + odm_set_bb_reg(dm, R_0x804, BIT(5) | BIT(4), ant_sel); + odm_set_bb_reg(dm, R_0x80c, BIT(23), psd_input); + +#if 0 + } else { /*ODM_IC_11N_SERIES*/ +#endif + } + /*@bw = (*dm->band_width); //ODM_BW20M */ + /*@channel = *(dm->channel);*/ +} + +void phydm_psd_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + + PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n"); + + dm_psd_table->psd_in_progress = false; + + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) { + #if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) { + dm_psd_table->psd_reg = R_0x1e8c; + dm_psd_table->psd_report_reg = R_0x2d90; + + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + dm_psd_table->psd_bw_rf_reg = 2; + } + #else + #if 0 + dm_psd_table->psd_reg = R_0x1e8c; + dm_psd_table->psd_report_reg = R_0x2d90; + + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + dm_psd_table->psd_bw_rf_reg = 1; + #endif + + return; + #endif + } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) { + dm_psd_table->psd_reg = R_0x910; + dm_psd_table->psd_report_reg = R_0xf44; + + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + if (ODM_IC_11AC_2_SERIES) + dm_psd_table->psd_bw_rf_reg = 1; + else + dm_psd_table->psd_bw_rf_reg = 2; + } else { + dm_psd_table->psd_reg = R_0x808; + dm_psd_table->psd_report_reg = R_0x8b4; + /*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + dm_psd_table->psd_bw_rf_reg = 2; + } + + dm_psd_table->psd_pwr_common_offset = 0; + + phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0); +#if 0 + /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */ +#endif +} + +void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i = 0; + + if ((strcmp(input[1], help) == 0)) { + #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT + #if (RTL8723F_SUPPORT) + if (dm->support_ic_type & ODM_RTL8723F) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n"); + #endif + #if 0 + if (dm->support_ic_type & ODM_IC_JGR3_SERIES) + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n"); + else + #endif + #endif + PDM_SNPF(out_len, used, output + used, out_len - used, + "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n"); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {IGI(hex)} {start_point} {stop_point}\n"); + goto out; + } + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 0) { + for (i = 1; i < 10; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, + &var1[i]); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", + var1[1], var1[2], var1[3], var1[4], var1[5], + var1[6], (u8)var1[7], (u8)var1[8]); + phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2], + (u8)var1[3], (u16)var1[4], + (u8)var1[5], (u8)var1[6], + (u8)var1[7], (u8)var1[8]); + + } else if (var1[0] == 1) { + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", + var1[1], var1[2], var1[3]); + dm->debug_components |= ODM_COMP_API; + if (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) == + PHYDM_SET_FAIL) + PDM_SNPF(out_len, used, output + used, out_len - used, + "PSD_SET_FAIL\n"); + dm->debug_components &= ~(ODM_COMP_API); + } + +out: + *_used = used; + *_out_len = out_len; +} + +u8 phydm_get_psd_result_table(void *dm_void, int index) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct psd_info *dm_psd_table = &dm->dm_psd_table; + u8 result = 0; + + if (index < 128) + result = dm_psd_table->psd_result[index]; + + return result; +} + +#endif diff --git a/hal/phydm/phydm_psd.h b/hal/phydm/phydm_psd.h new file mode 100644 index 0000000..dec384a --- /dev/null +++ b/hal/phydm/phydm_psd.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMPSD_H__ +#define __PHYDMPSD_H__ + +/*@#define PSD_VERSION "1.0"*/ /*@2016.09.22 Dino*/ +/*@2016.10.07 Dino, Add Option for PSD Tone index Selection */ +/*@2019.04.26 Early return & "IF0" for JGR3 ICs */ +#define PSD_VERSION "1.2" + +#ifdef CONFIG_PSD_TOOL + + +struct psd_info { + u8 psd_in_progress; + u32 psd_reg; + u32 psd_report_reg; + u8 psd_pwr_common_offset; + u16 sw_avg_time; + u16 fft_smp_point; + u32 rf_0x18_bkp; + u32 rf_0x18_bkp_b; + u16 psd_fc_channel; + u32 psd_bw_rf_reg; + u8 psd_result[128]; + u8 noise_k_en; +}; + +u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi); + +void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point); + +void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time, + u8 i_q_setting, u16 fft_smp_point, u8 ant_sel, + u8 psd_input, u8 channel, u8 noise_k_en); + +void phydm_psd_init(void *dm_void); + +u8 phydm_get_psd_result_table(void *dm_void, int index); + +#endif +#endif diff --git a/hal/phydm/phydm_rainfo.c b/hal/phydm/phydm_rainfo.c new file mode 100644 index 0000000..d4a6215 --- /dev/null +++ b/hal/phydm/phydm_rainfo.c @@ -0,0 +1,2432 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +boolean phydm_is_vht_rate(void *dm_void, u8 rate) +{ + return ((rate & 0x7f) >= ODM_RATEVHTSS1MCS0) ? true : false; +} + +boolean phydm_is_ht_rate(void *dm_void, u8 rate) +{ + return (((rate & 0x7f) >= ODM_RATEMCS0) && + ((rate & 0x7f) <= ODM_RATEMCS31)) ? true : false; +} + +boolean phydm_is_ofdm_rate(void *dm_void, u8 rate) +{ + return (((rate & 0x7f) >= ODM_RATE6M) && + ((rate & 0x7f) <= ODM_RATE54M)) ? true : false; +} + +boolean phydm_is_cck_rate(void *dm_void, u8 rate) +{ + return ((rate & 0x7f) <= ODM_RATE11M) ? true : false; +} + +u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate) +{ + u8 rate_idx = 0x0; + u8 legacy_spec_rate_t[8] = {PHYDM_SPEC_RATE_6M, PHYDM_SPEC_RATE_9M, + PHYDM_SPEC_RATE_12M, PHYDM_SPEC_RATE_18M, + PHYDM_SPEC_RATE_24M, PHYDM_SPEC_RATE_36M, + PHYDM_SPEC_RATE_48M, PHYDM_SPEC_RATE_54M}; + + if ((rate >= ODM_RATE6M) && (rate <= ODM_RATE54M)) + rate_idx = rate - ODM_RATE6M; + return legacy_spec_rate_t[rate_idx]; +} + +u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate) +{ + u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 rate_digit = 0; + + if (rate_idx >= ODM_RATEVHTSS1MCS0) + rate_digit = (rate_idx - ODM_RATEVHTSS1MCS0) % 10; + else if (rate_idx >= ODM_RATEMCS0) + rate_digit = (rate_idx - ODM_RATEMCS0); + else if (rate_idx <= ODM_RATE54M) + rate_digit = legacy_table[rate_idx]; + + return rate_digit; +} + +u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type) +{ + u8 num_ss = 1; + + switch (type) { + case PDM_CCK: + case PDM_OFDM: + case PDM_1SS: + num_ss = 1; + break; + case PDM_2SS: + num_ss = 2; + break; + case PDM_3SS: + num_ss = 3; + break; + case PDM_4SS: + num_ss = 4; + break; + default: + break; + } + + return num_ss; +} + +u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate) +{ + u8 num_ss = 1; + + if (data_rate <= ODM_RATE54M) + num_ss = 1; + else if (data_rate <= ODM_RATEMCS31) + num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1; + else if (data_rate <= ODM_RATEVHTSS1MCS9) + num_ss = 1; + else if (data_rate <= ODM_RATEVHTSS2MCS9) + num_ss = 2; + else if (data_rate <= ODM_RATEVHTSS3MCS9) + num_ss = 3; + else if (data_rate <= ODM_RATEVHTSS4MCS9) + num_ss = 4; + + return num_ss; +} + +void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + u8 i = 0, input_idx = 0; + u8 h2c_parameter[H2C_MAX_LENGTH] = {0}; + u8 phydm_h2c_id = 0; + + for (i = 0; i < 8; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + input_idx++; + } + + if (input_idx == 0) + return; + + phydm_h2c_id = (u8)dm_value[0]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id); + + for (i = 0; i < H2C_MAX_LENGTH; i++) { + h2c_parameter[i] = (u8)dm_value[i + 1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i]); + } + + odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter); + + *_used = used; + *_out_len = out_len; +} + +void phydm_fw_fix_rate(void *dm_void, u8 en, u8 macid, u8 bw, u8 rate) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 reg_u32_tmp; + + if (dm->support_ic_type & PHYDM_IC_8051_SERIES) { + reg_u32_tmp = (bw << 24) | (rate << 16) | (macid << 8) | en; + odm_set_mac_reg(dm, R_0x4a0, MASKDWORD, reg_u32_tmp); + + } else { + if (en == 1) + reg_u32_tmp = BYTE_2_DWORD(0x60, macid, bw, rate); + else + reg_u32_tmp = 0x40000000; + if (dm->support_ic_type & ODM_RTL8814B) + odm_set_mac_reg(dm, R_0x448, MASKDWORD, reg_u32_tmp); + else + odm_set_mac_reg(dm, R_0x450, MASKDWORD, reg_u32_tmp); + } + if (en == 1) { + PHYDM_DBG(dm, ODM_COMP_API, + "FW fix TX rate[id =%d], %dM, Rate(%d)=", macid, + (20 << bw), rate); + phydm_print_rate(dm, rate, ODM_COMP_API); + } else { + PHYDM_DBG(dm, ODM_COMP_API, "Auto Rate\n"); + } +} + +void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u32 used = *_used; + u32 out_len = *_out_len; + char help[] = "-h"; + u32 var[5] = {0}; + u8 macid = 0, bw = 0, rate = 0; + u8 tx_cls_en = 0, tx_cls_th = 0, tmp = 0; + u8 i = 0; + + for (i = 0; i < 5; i++) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var[i]); + } + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {0:-,1:+} {ofst}: set offset\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {100}: show offset\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {en} {macid} {bw} {rate}: fw fix rate\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {en}: Dynamic RRSR\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} {0:pkt RA, 1:TBTT RA, 100:query RA mode}\n"); +#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH + PDM_SNPF(out_len, used, output + used, out_len - used, + "{5} {0:dis, 1:en}{th; 255:auto, xx:dB}: Tx CLS\n"); +#endif + } else if (var[0] == 1) { /*@Adjust PCR offset*/ + + if (var[1] == 100) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Get] RA_ofst=((%s%d))\n", + ((ra_tab->ra_ofst_direc) ? "+" : "-"), + ra_tab->ra_th_ofst); + + } else if (var[1] == 0) { + ra_tab->ra_ofst_direc = 0; + ra_tab->ra_th_ofst = (u8)var[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set] RA_ofst=((-%d))\n", ra_tab->ra_th_ofst); + } else if (var[1] == 1) { + ra_tab->ra_ofst_direc = 1; + ra_tab->ra_th_ofst = (u8)var[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set] RA_ofst=((+%d))\n", ra_tab->ra_th_ofst); + } + + } else if (var[0] == 2) { /*@FW fix rate*/ + macid = (u8)var[2]; + bw = (u8)var[3]; + rate = (u8)var[4]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[FW fix TX Rate] {en, macid,bw,rate}={%d, %d, %d, 0x%x}", + var[1], macid, bw, rate); + + phydm_fw_fix_rate(dm, (u8)var[1], macid, bw, rate); + } else if (var[0] == 3) { /*@Dynamic RRSR*/ + ra_tab->dynamic_rrsr_en = (boolean)var[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Dynamic RRSR] enable=%d", ra_tab->dynamic_rrsr_en); + } else if (var[0] == 4) { /*@RA trigger mode*/ + if (var[1] == 0 || var[1] == 1) + ra_tab->ra_trigger_mode = (u8)var[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[RA trigger] mode=%d\n", ra_tab->ra_trigger_mode); +#ifdef CONFIG_DYNAMIC_TXCOLLISION_TH + } else if (var[0] == 5) { /*@Tx Collision Detection*/ + tx_cls_en = (u8)var[1]; + ra_tab->ra_tx_cls_th = (u8)var[2]; + tmp = (u8)var[2]; + tx_cls_th = (tmp < 50) ? 0 : (tmp > 81) ? 31 : tmp - 50; + if (tx_cls_en) { + odm_set_bb_reg(dm, R_0x8f8, BIT(16), 1); + if (ra_tab->ra_tx_cls_th != 255) { + phydm_tx_collsion_th_set(dm, tx_cls_th, + tx_cls_th); + } + + } else { + odm_set_bb_reg(dm, R_0x8f8, BIT(16), 0); + } + + if (tx_cls_en & ra_tab->ra_tx_cls_th != 255) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Tx Collision Detec] {en, th}={%d, %d}\n", + tx_cls_en, tx_cls_th + 50); + } else if (tx_cls_en & ra_tab->ra_tx_cls_th == 255) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Tx Collision Detec] {en, th}={%d, auto}\n", + tx_cls_en); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Tx Collision Detec] {en, th}={%d, xx}\n", + tx_cls_en); + } +#endif + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[Set] Error\n"); + } + *_used = used; + *_out_len = out_len; +} + +void phydm_ra_mask_report_h2c_trigger(void *dm_void, + struct ra_mask_rpt_trig *trig_rpt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + phydm_fw_trace_en_h2c(dm, true, 1, 2, trig_rpt->macid); + + trig_rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp; +} +void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 i = 0; + + rpt->ra_mask_rpt_stamp = ra_tab->ra_mask_rpt_stamp; + + odm_move_memory(dm, &rpt->ra_mask_buf[0], &ra_tab->ra_mask_buf[0], 8); +} + +void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 mode = cmd_buf[0]; /*Retry Penalty, NH, NL*/ + u8 i; + + PHYDM_DBG(dm, DBG_FW_TRACE, "[%s] [mode: %d]----------------------->\n", + __func__, mode); + + if (mode == RADBG_DEBUG_MONITOR1) { + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "rate =", + cmd_buf[2] & 0x7f); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "SGI =", + (cmd_buf[2] & 0x80) >> 7); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW =", + cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "BW_max =", + cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "multi_rate0 =", cmd_buf[5]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "multi_rate1 =", cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =", + cmd_buf[7]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =", + cmd_buf[8]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", + "SGI_support =", cmd_buf[9]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "try_ness =", + cmd_buf[10]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "pre_rate =", + cmd_buf[11]); + } else { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "RSSI =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %x\n", "BW =", + cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "DISRA =", + cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "VHT_EN =", + cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", + "Hightest rate =", cmd_buf[5]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "Lowest rate =", cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "SGI_support =", cmd_buf[7]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Rate_ID =", + cmd_buf[8]); + } + } else if (mode == RADBG_DEBUG_MONITOR2) { + if (dm->support_ic_type & PHYDM_IC_3081_SERIES) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate_id =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "highest_rate =", cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", + "lowest_rate =", cmd_buf[3]); + + for (i = 4; i <= 11; i++) + PHYDM_DBG(dm, DBG_FW_TRACE, "RAMASK = 0x%x\n", + cmd_buf[i]); + + odm_move_memory(dm, &ra_tab->ra_mask_buf[0], &cmd_buf[4], 8); + ra_tab->ra_mask_rpt_stamp++; + } else { + PHYDM_DBG(dm, DBG_FW_TRACE, + "%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", + cmd_buf[8], cmd_buf[7], cmd_buf[6], + cmd_buf[5], cmd_buf[4], cmd_buf[3], + cmd_buf[2], cmd_buf[1]); + } + } else if (mode == RADBG_DEBUG_MONITOR3) { + for (i = 0; i < (cmd_len - 1); i++) + PHYDM_DBG(dm, DBG_FW_TRACE, "content[%d] = %d\n", i, + cmd_buf[1 + i]); + } else if (mode == RADBG_DEBUG_MONITOR4) + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {%d.%d}\n", "RA version =", + cmd_buf[1], cmd_buf[2]); + else if (mode == RADBG_DEBUG_MONITOR5) { + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "Current rate =", + cmd_buf[1]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "Retry ratio =", + cmd_buf[2]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s %d\n", "rate down ratio =", + cmd_buf[3]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x\n", "highest rate =", + cmd_buf[4]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s {0x%x 0x%x}\n", "Muti-try =", + cmd_buf[5], cmd_buf[6]); + PHYDM_DBG(dm, DBG_FW_TRACE, "%5s 0x%x%x%x%x%x\n", "RA mask =", + cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], + cmd_buf[7]); + } + PHYDM_DBG(dm, DBG_FW_TRACE, "-------------------------------\n"); +} + +void phydm_ra_dynamic_retry_count(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR)) + return; + + /*PHYDM_DBG(dm, DBG_RA, "dm->pre_b_noisy = %d\n", dm->pre_b_noisy );*/ + + if (dm->pre_b_noisy != dm->noisy_decision) { + if (dm->noisy_decision) { + PHYDM_DBG(dm, DBG_DYN_ARFR, "Noisy Env. RA fallback\n"); + odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x0); + odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x04030201); + } else { + PHYDM_DBG(dm, DBG_DYN_ARFR, "Clean Env. RA fallback\n"); + odm_set_mac_reg(dm, R_0x430, MASKDWORD, 0x01000000); + odm_set_mac_reg(dm, R_0x434, MASKDWORD, 0x06050402); + } + dm->pre_b_noisy = dm->noisy_decision; + } +} + +void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + boolean vht_en = phydm_is_vht_rate(dm, rate_idx); + u8 b_sgi = (rate & 0x80) >> 7; + u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx); + u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx); + + PHYDM_DBG_F(dm, dbg_component, "( %s%s%s%s%s%d%s%s)\n", + (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "", + (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "", + (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "", + (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + rate_digit, + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M"); +} + +void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + boolean vht_en = phydm_is_vht_rate(dm, rate_idx); + u8 b_sgi = (rate & 0x80) >> 7; + u8 rate_ss = phydm_rate_to_num_ss(dm, rate_idx); + u8 rate_digit = phydm_rate_2_rate_digit(dm, rate_idx); + + PHYDM_SNPRINTF(buf, buf_size, "( %s%s%s%s%s%d%s%s)", + (vht_en && (rate_ss == 1)) ? "VHT 1ss " : "", + (vht_en && (rate_ss == 2)) ? "VHT 2ss " : "", + (vht_en && (rate_ss == 3)) ? "VHT 3ss " : "", + (vht_en && (rate_ss == 4)) ? "VHT 4ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + rate_digit, + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M"); +} + +void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + u8 macid = cmd_buf[1]; + u8 rate = cmd_buf[0]; + u8 ra_ratio = 0xff; + u8 curr_bw = 0xff; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 rate_order; + u8 gid_index = 0; + u8 txcls_rate = 0; + char dbg_buf[PHYDM_SNPRINT_SIZE] = {0}; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + sta = dm->phydm_sta_info[dm->phydm_macid_table[macid]]; + #else + sta = dm->phydm_sta_info[macid]; + #endif + + if (cmd_len == 7) { + ra_ratio = cmd_buf[5]; + curr_bw = cmd_buf[6]; + PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d\n", macid, ra_ratio); + } else if (cmd_len == 8) { + ra_ratio = cmd_buf[5]; + curr_bw = cmd_buf[6]; + txcls_rate = cmd_buf[7]; + PHYDM_DBG(dm, DBG_RA, "[%d] PER=%d TxCLS=%d\n", macid, ra_ratio, + txcls_rate); + } + + if (cmd_buf[3] != 0) { + if (cmd_buf[3] == 0xff) + PHYDM_DBG(dm, DBG_RA, "FW Fix Rate\n"); + else if (cmd_buf[3] == 1) + PHYDM_DBG(dm, DBG_RA, "Try Success\n"); + else if (cmd_buf[3] == 2) + PHYDM_DBG(dm, DBG_RA, "Try Fail & Again\n"); + else if (cmd_buf[3] == 3) + PHYDM_DBG(dm, DBG_RA, "Rate Back\n"); + else if (cmd_buf[3] == 4) + PHYDM_DBG(dm, DBG_RA, "Start rate by RSSI\n"); + else if (cmd_buf[3] == 5) + PHYDM_DBG(dm, DBG_RA, "Try rate\n"); + } + phydm_print_rate_2_buff(dm, rate, dbg_buf, PHYDM_SNPRINT_SIZE); + PHYDM_DBG(dm, DBG_RA, "Tx Rate=%s (%d)\n", dbg_buf, rate); + +#ifdef MU_EX_MACID + if (macid >= 128 && macid < (128 + MU_EX_MACID)) { + gid_index = macid - 128; + ra_tab->mu1_rate[gid_index] = rate; + } + if (macid >= ODM_ASSOCIATE_ENTRY_NUM) + return; +#endif + if (is_sta_active(sta)) { + sta->ra_info.curr_tx_rate = rate; + sta->ra_info.curr_tx_bw = (enum channel_width)curr_bw; + sta->ra_info.curr_retry_ratio = ra_ratio; + } + + /*trigger power training*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + + rate_order = phydm_rate_order_compute(dm, rate_idx); + + if (dm->is_one_entry_only || + (rate_order > ra_tab->highest_client_tx_order && + ra_tab->power_tracking_flag == 1)) { + halrf_update_pwr_track(dm, rate_idx); + ra_tab->power_tracking_flag = 0; + } + +#endif + +#if 0 + /*trigger dynamic rate ID*/ + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) + phydm_update_rate_id(dm, rate, macid); +#endif +} + +void odm_ra_post_action_on_assoc(void *dm_void) +{ +} + +void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc, + u8 ra_th_ofst) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + ra_tab->ra_ofst_direc = ra_ofst_direc; + ra_tab->ra_th_ofst = ra_th_ofst; + PHYDM_DBG(dm, DBG_RA_MASK, "Set ra_th_offset=(( %s%d ))\n", + ((ra_ofst_direc) ? "+" : "-"), ra_th_ofst); +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +void phydm_gen_ramask_h2c_AP( + void *dm_void, + struct rtl8192cd_priv *priv, + struct sta_info *entry, + u8 rssi_level) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type == ODM_RTL8812) { + #if (RTL8812A_SUPPORT == 1) + UpdateHalRAMask8812(priv, entry, rssi_level); + #endif + } else if (dm->support_ic_type == ODM_RTL8188E) { + #if (RTL8188E_SUPPORT == 1) + #ifdef TXREPORT + add_RATid(priv, entry); + #endif + #endif + } else { + #ifdef CONFIG_WLAN_HAL + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, entry, rssi_level); + #endif + } +} + +void phydm_update_hal_ra_mask( + void *dm_void, + u32 wireless_mode, + u8 rf_type, + u8 bw, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_lsb_in, + u8 tx_rate_level) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ratr_bitmap = *ratr_bitmap_lsb_in; + u32 ratr_bitmap_msb = *ratr_bitmap_msb_in; + +#if 0 + /*PHYDM_DBG(dm, DBG_RA_MASK, "phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type);*/ +#endif + PHYDM_DBG(dm, DBG_RA_MASK, + "Platfoem original RA Mask = (( 0x %x | %x ))\n", + ratr_bitmap_msb, ratr_bitmap); + + switch (wireless_mode) { + case PHYDM_WIRELESS_MODE_B: { + ratr_bitmap &= 0x0000000f; + } break; + + case PHYDM_WIRELESS_MODE_G: { + ratr_bitmap &= 0x00000ff5; + } break; + + case PHYDM_WIRELESS_MODE_A: { + ratr_bitmap &= 0x00000ff0; + } break; + + case PHYDM_WIRELESS_MODE_N_24G: + case PHYDM_WIRELESS_MODE_N_5G: { + if (mimo_ps_enable) + rf_type = RF_1T1R; + + if (rf_type == RF_1T1R) { + if (bw == CHANNEL_WIDTH_40) + ratr_bitmap &= 0x000ff015; + else + ratr_bitmap &= 0x000ff005; + } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) { + if (bw == CHANNEL_WIDTH_40) + ratr_bitmap &= 0x0ffff015; + else + ratr_bitmap &= 0x0ffff005; + } else { /*@3T*/ + + ratr_bitmap &= 0xfffff015; + ratr_bitmap_msb &= 0xf; + } + } break; + + case PHYDM_WIRELESS_MODE_AC_24G: { + if (rf_type == RF_1T1R) { + ratr_bitmap &= 0x003ff015; + } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) { + ratr_bitmap &= 0xfffff015; + } else { /*@3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } + + if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } break; + + case PHYDM_WIRELESS_MODE_AC_5G: { + if (rf_type == RF_1T1R) { + ratr_bitmap &= 0x003ff010; + } else if (rf_type == RF_2T2R || rf_type == RF_2T4R || rf_type == RF_2T3R) { + ratr_bitmap &= 0xfffff010; + } else { /*@3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } + + if (bw == CHANNEL_WIDTH_20) { /*@AC 20MHz not support MCS9*/ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } break; + + default: + break; + } + + if (wireless_mode != PHYDM_WIRELESS_MODE_B) { + if (tx_rate_level == 0) + ratr_bitmap &= 0xffffffff; + else if (tx_rate_level == 1) + ratr_bitmap &= 0xfffffff0; + else if (tx_rate_level == 2) + ratr_bitmap &= 0xffffefe0; + else if (tx_rate_level == 3) + ratr_bitmap &= 0xffffcfc0; + else if (tx_rate_level == 4) + ratr_bitmap &= 0xffff8f80; + else if (tx_rate_level >= 5) + ratr_bitmap &= 0xffff0f00; + } + + if (disable_cck_rate) + ratr_bitmap &= 0xfffffff0; + + PHYDM_DBG(dm, DBG_RA_MASK, + "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n", + wireless_mode, rf_type, bw, mimo_ps_enable, tx_rate_level); + +#if 0 + /*PHYDM_DBG(dm, DBG_RA_MASK, "111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap);*/ +#endif + + *ratr_bitmap_lsb_in = ratr_bitmap; + *ratr_bitmap_msb_in = ratr_bitmap_msb; + PHYDM_DBG(dm, DBG_RA_MASK, + "Phydm modified RA Mask = (( 0x %x | %x ))\n", + *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in); +} + +#endif + +void phydm_rate_adaptive_mask_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER adapter = dm->adapter; + PMGNT_INFO mgnt_info = &(adapter->MgntInfo); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)dm->adapter)); + + if (mgnt_info->DM_Type == dm_type_by_driver) + hal_data->bUseRAMask = true; + else + hal_data->bUseRAMask = false; + +#endif + + ra_t->ldpc_thres = 35; + ra_t->up_ramask_cnt = 0; + ra_t->up_ramask_cnt_tmp = 0; +} + +void phydm_refresh_rate_adaptive_mask(void *dm_void) +{ +/*@Will be removed*/ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_ra_mask_watchdog(dm); +} + +void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; +#ifdef CONFIG_BEAMFORMING + struct bf_cmn_info *bf = NULL; +#endif + char help[] = "-h"; + u32 var[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u32 i, sta_idx_start, sta_idx_end; + u8 tatal_sta_num = 0; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]); + + if ((strcmp(input[1], help) == 0)) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "All STA: {1}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "STA[macid]: {2} {macid}\n"); + return; + } else if (var[0] == 1) { + sta_idx_start = 0; + sta_idx_end = ODM_ASSOCIATE_ENTRY_NUM; + } else if (var[0] == 2) { + sta_idx_start = var[1]; + sta_idx_end = var[1]; + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "Warning input value!\n"); + return; + } + + for (i = sta_idx_start; i < sta_idx_end; i++) { + sta = dm->phydm_sta_info[i]; + + if (!is_sta_active(sta)) + continue; + + ra = &sta->ra_info; + #ifdef CONFIG_BEAMFORMING + bf = &sta->bf_info; + #endif + + tatal_sta_num++; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "==[sta_idx: %d][MACID: %d]============>\n", i, + sta->mac_id); + PDM_SNPF(out_len, used, output + used, out_len - used, + "AID:%d\n", sta->aid); + PDM_SNPF(out_len, used, output + used, out_len - used, + "ADDR:%x-%x-%x-%x-%x-%x\n", sta->mac_addr[5], + sta->mac_addr[4], sta->mac_addr[3], sta->mac_addr[2], + sta->mac_addr[1], sta->mac_addr[0]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "DM_ctrl:0x%x\n", sta->dm_ctrl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "BW:%d, MIMO_Type:0x%x\n", sta->bw_mode, + sta->mimo_type); + PDM_SNPF(out_len, used, output + used, out_len - used, + "STBC_en:%d, LDPC_en=%d\n", sta->stbc_en, + sta->ldpc_en); + + /*@[RSSI Info]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "RSSI{All, OFDM, CCK}={%d, %d, %d}\n", + sta->rssi_stat.rssi, sta->rssi_stat.rssi_ofdm, + sta->rssi_stat.rssi_cck); + + /*@[RA Info]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "Rate_ID:%d, RSSI_LV:%d, ra_bw:%d, SGI_en:%d\n", + ra->rate_id, ra->rssi_level, ra->ra_bw_mode, + ra->is_support_sgi); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "VHT_en:%d, Wireless_set=0x%x, sm_ps=%d\n", + ra->is_vht_enable, sta->support_wireless_set, + sta->sm_ps); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Dis{RA, PT}={%d, %d}, TxRx:%d, Noisy:%d\n", + ra->disable_ra, ra->disable_pt, ra->txrx_state, + ra->is_noisy); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "TX{Rate, BW}={0x%x, %d}, RTY:%d\n", ra->curr_tx_rate, + ra->curr_tx_bw, ra->curr_retry_ratio); + + PDM_SNPF(out_len, used, output + used, out_len - used, + "RA_Mask:0x%llx\n", ra->ramask); + + /*@[TP]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "TP{TX,RX}={%d, %d}\n", sta->tx_moving_average_tp, + sta->rx_moving_average_tp); + +#ifdef CONFIG_BEAMFORMING + /*@[Beamforming]*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "BF CAP{HT,VHT}={0x%x, 0x%x}\n", bf->ht_beamform_cap, + bf->vht_beamform_cap); + PDM_SNPF(out_len, used, output + used, out_len - used, + "BF {p_aid,g_id}={0x%x, 0x%x}\n\n", bf->p_aid, + bf->g_id); +#endif + } + + if (tatal_sta_num == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "No Linked STA\n"); + } + + *_used = used; + *_out_len = out_len; +} + +u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rx_num = 1; + + if (type == RF_1T1R) + rx_num = 1; + else if (type == RF_2T2R || type == RF_1T2R) + rx_num = 2; + else if (type == RF_3T3R || type == RF_2T3R) + rx_num = 3; + else if (type == RF_4T4R || type == RF_3T4R || type == RF_2T4R) + rx_num = 4; + else + pr_debug("[Warrning] %s\n", __func__); + + return rx_num; +} + +u8 phydm_get_tx_stream_num(void *dm_void, enum rf_type type) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 tx_num = 1; + + if (type == RF_1T1R || type == RF_1T2R) + tx_num = 1; + else if (type == RF_2T2R || type == RF_2T3R || type == RF_2T4R) + tx_num = 2; + else if (type == RF_3T3R || type == RF_3T4R) + tx_num = 3; + else if (type == RF_4T4R) + tx_num = 4; + else + PHYDM_DBG(dm, DBG_RA, "[Warrning] no mimo_type is found\n"); + + return tx_num; +} + +u64 phydm_get_bb_mod_ra_mask(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_iot_center *iot_table = &dm->iot_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + enum channel_width bw = 0; + enum wireless_set wrls_mode = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + struct rtl8192cd_priv *priv = dm->priv; +#endif + u8 tx_stream_num = 1; + u8 rssi_lv = 0; + u64 ra_mask_bitmap = 0; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + bw = ra->ra_bw_mode; + wrls_mode = sta->support_wireless_set; + tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type); + rssi_lv = ra->rssi_level; + ra_mask_bitmap = ra->ramask; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__); + return 0; + } + + PHYDM_DBG(dm, DBG_RA, "macid=%d ori_RA_Mask= 0x%llx\n", sta->mac_id, + ra_mask_bitmap); + PHYDM_DBG(dm, DBG_RA, + "wireless_mode=0x%x, tx_ss=%d, BW=%d, MimoPs=%d, rssi_lv=%d\n", + wrls_mode, tx_stream_num, bw, sta->sm_ps, rssi_lv); + + if (sta->sm_ps == SM_PS_STATIC) /*@mimo_ps_enable*/ + tx_stream_num = 1; + + /*@[Modify RA Mask by Wireless Mode]*/ + + if (wrls_mode == WIRELESS_CCK) { /*@B mode*/ + ra_mask_bitmap &= 0x0000000f; + } else if (wrls_mode == WIRELESS_OFDM) { /*@G mode*/ + ra_mask_bitmap &= 0x00000ff0; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { /*@BG mode*/ + ra_mask_bitmap &= 0x00000ff5; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) { + /*N_2G*/ + if (tx_stream_num == 1) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x000ff015; + else + ra_mask_bitmap &= 0x000ff005; + } else if (tx_stream_num == 2) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x0ffff015; + else + ra_mask_bitmap &= 0x0ffff005; + } else if (tx_stream_num == 3) { + ra_mask_bitmap &= 0xffffff015; + } else { + ra_mask_bitmap &= 0xffffffff015; + } + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { /*N_5G*/ + + if (tx_stream_num == 1) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x000ff030; + else + ra_mask_bitmap &= 0x000ff010; + } else if (tx_stream_num == 2) { + if (bw == CHANNEL_WIDTH_40) + ra_mask_bitmap &= 0x0ffff030; + else + ra_mask_bitmap &= 0x0ffff010; + } else if (tx_stream_num == 3) { + ra_mask_bitmap &= 0xffffff010; + } else { + ra_mask_bitmap &= 0xffffffff010; + } + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) { + /*@AC_2G*/ + if (tx_stream_num == 1) + ra_mask_bitmap &= 0x003ff015; + else if (tx_stream_num == 2) + ra_mask_bitmap &= 0xfffff015; + else if (tx_stream_num == 3) + ra_mask_bitmap &= 0x3fffffff015; + else /*@AC_4SS 2G*/ + ra_mask_bitmap &= 0x000ffffffffff015; + if (bw == CHANNEL_WIDTH_20) { + /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/ + ra_mask_bitmap &= 0x0007ffff7fdff015; + } else if (bw == CHANNEL_WIDTH_80) { + /* @AC 80MHz doesn't support 3SS MCS6*/ + ra_mask_bitmap &= 0x000fffbffffff015; + } + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { /*@AC_5G*/ + + if (tx_stream_num == 1) + ra_mask_bitmap &= 0x003ff010; + else if (tx_stream_num == 2) + ra_mask_bitmap &= 0xfffff010; + else if (tx_stream_num == 3) + ra_mask_bitmap &= 0x3fffffff010; + else /*@AC_4SS 5G*/ + ra_mask_bitmap &= 0x000ffffffffff010; + + if (bw == CHANNEL_WIDTH_20) { + /* @AC 20MHz doesn't support MCS9 except 3SS & 6SS*/ + ra_mask_bitmap &= 0x0007ffff7fdff010; + } else if (bw == CHANNEL_WIDTH_80) { + /* @AC 80MHz doesn't support 3SS MCS6*/ + ra_mask_bitmap &= 0x000fffbffffff010; + } else if (bw == CHANNEL_WIDTH_160) { + /* @AC 80M+80M doesn't support 3SS & 4SS*/ + ra_mask_bitmap &= 0xfffff010; + } + } else { + PHYDM_DBG(dm, DBG_RA, "[Warrning] RA mask is Not found\n"); + } + + PHYDM_DBG(dm, DBG_RA, "Mod by mode=0x%llx\n", ra_mask_bitmap); + +#if ((DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(PHYDM_IC_JGR3_SERIES_SUPPORT)) + if (priv->pshare->veriwave_sta_num > 0) { + PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap); + return ra_mask_bitmap; + } +#endif + /*@[Modify RA Mask by RSSI level]*/ + if (wrls_mode != WIRELESS_CCK) { + if (iot_table->patch_id_40010700) { + ra_mask_bitmap &= (rssi_lv == 0 ? + 0xffffffffffffffff : + 0xfffffffffffffff0); + return ra_mask_bitmap; + } + + if (rssi_lv == 0) + ra_mask_bitmap &= 0xffffffffffffffff; + else if (rssi_lv == 1) + ra_mask_bitmap &= 0xfffffffffffffff0; + else if (rssi_lv == 2) + ra_mask_bitmap &= 0xffffffffffffefe0; + else if (rssi_lv == 3) + ra_mask_bitmap &= 0xffffffffffffcfc0; + else if (rssi_lv == 4) + ra_mask_bitmap &= 0xffffffffffff8f80; + else if (rssi_lv >= 5) + ra_mask_bitmap &= 0xffffffffffff0f00; + } + PHYDM_DBG(dm, DBG_RA, "Mod by RSSI=0x%llx\n", ra_mask_bitmap); + + return ra_mask_bitmap; +} + +u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + enum wireless_set wrls_set = 0; + u8 rssi_lv = 0; + u8 rate_idx = 0; + u8 rate_ofst = 0; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + wrls_set = sta->support_wireless_set; + rssi_lv = ra->rssi_level; + } else { + pr_debug("[Warning] %s: invalid STA\n", __func__); + return 0; + } + + PHYDM_DBG(dm, DBG_RA, "[%s]macid=%d, wireless_set=0x%x, rssi_lv=%d\n", + __func__, sta->mac_id, wrls_set, rssi_lv); + + rate_ofst = (rssi_lv <= 1) ? 0 : (rssi_lv - 1); + + if (wrls_set & WIRELESS_VHT) { + rate_idx = ODM_RATEVHTSS1MCS0 + rate_ofst; + } else if (wrls_set & WIRELESS_HT) { + rate_idx = ODM_RATEMCS0 + rate_ofst; + } else if (wrls_set & WIRELESS_OFDM) { + rate_idx = ODM_RATE6M + rate_ofst; + } else { + rate_idx = ODM_RATE1M + rate_ofst; + + if (rate_idx > ODM_RATE11M) + rate_idx = ODM_RATE11M; + } + return rate_idx; +} + +u8 phydm_get_rate_id(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + enum channel_width bw = 0; + enum wireless_set wrls_mode = 0; + u8 tx_stream_num = 1; + u8 rate_id_idx = PHYDM_BGN_20M_1SS; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + bw = ra->ra_bw_mode; + wrls_mode = sta->support_wireless_set; + tx_stream_num = phydm_get_tx_stream_num(dm, sta->mimo_type); + + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid STA\n", __func__); + return 0; + } + + PHYDM_DBG(dm, DBG_RA, "macid=%d,wireless_set=0x%x,tx_SS_num=%d,BW=%d\n", + sta->mac_id, wrls_mode, tx_stream_num, bw); + + if (wrls_mode == WIRELESS_CCK) { + /*@B mode*/ + rate_id_idx = PHYDM_B_20M; + } else if (wrls_mode == WIRELESS_OFDM) { + /*@G mode*/ + rate_id_idx = PHYDM_G; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM)) { + /*@BG mode*/ + rate_id_idx = PHYDM_BG; + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_HT)) { + /*@GN mode*/ + if (tx_stream_num == 1) + rate_id_idx = PHYDM_GN_N1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_GN_N2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) { + /*@BGN mode*/ + if (bw == CHANNEL_WIDTH_40) { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_BGN_40M_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR7_N_4SS; + + } else { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_BGN_20M_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR7_N_4SS; + } + } else if (wrls_mode == (WIRELESS_OFDM | WIRELESS_VHT)) { + /*@AC mode*/ + if (bw == CHANNEL_WIDTH_160) { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + } else { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR6_AC_4SS; + } + } else if (wrls_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT)) { + /*@AC 2.4G mode*/ + if (bw >= CHANNEL_WIDTH_80) { + if (tx_stream_num == 1) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (tx_stream_num == 2) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (tx_stream_num == 3) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + else if (tx_stream_num == 4) + rate_id_idx = PHYDM_ARFR6_AC_4SS; + } else { + if (tx_stream_num == 1) { + if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) + rate_id_idx = PHYDM_TYPE2_ARFR5_AC_2G_1SS; + else + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + } else if (tx_stream_num == 2) { + if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) + rate_id_idx = PHYDM_TYPE2_ARFR3_AC_2G_2SS; + else + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + } else if (tx_stream_num == 3) { + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } else if (tx_stream_num == 4) { + rate_id_idx = PHYDM_ARFR6_AC_4SS; + } + } + } else { + PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n"); + rate_id_idx = 0; + } + + PHYDM_DBG(dm, DBG_RA, "Rate_ID=((0x%x))\n", rate_id_idx); + + return rate_id_idx; +} + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_ra_mode_selection(void *dm_void, u8 mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 pre_mode = ra_tab->ra_trigger_mode; /* 0:pkt RA, 1:TBTT RA */ + + if (mode >= 2) { + PHYDM_DBG(dm, DBG_RA, "RA mode selection Fail\n"); + } else { + ra_tab->ra_trigger_mode = mode; + PHYDM_DBG(dm, DBG_RA, "RA mode, 0:pkt RA, 1:TBTT RA\n"); + PHYDM_DBG(dm, DBG_RA, "PreMode=%d,CurMode=%d\n", pre_mode, + mode); + } +} +#endif + +void phydm_ra_h2c(void *dm_void, u8 sta_idx, u8 dis_ra, u8 dis_pt, + u8 no_update_bw, u8 init_ra_lv, u64 ra_mask) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + u8 h2c_val[H2C_MAX_LENGTH] = {0}; + u8 rate_id_idx = 0; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid sta_info\n", + __func__); + return; + } + + PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id); + + +#ifdef PHYDM_POWER_TRAINING_SUPPORT + if ((dm->support_ability & ODM_BB_PWR_TRAIN) && !dm->is_disable_power_training) + dis_pt = false; + else + dis_pt = true; + +#else + dis_pt= true; +#endif + + rate_id_idx = ra->rate_id; + + /*for compatibility issues with FW RA [PHYDM-405]*/ + if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) { + if (rate_id_idx == PHYDM_TYPE2_ARFR5_AC_2G_1SS) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else if (rate_id_idx == PHYDM_TYPE2_ARFR3_AC_2G_2SS) + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + } + + h2c_val[0] = sta->mac_id; + h2c_val[1] = (rate_id_idx & 0x1f) | ((init_ra_lv & 0x3) << 5) | + (ra->is_support_sgi << 7); + h2c_val[2] = (u8)((ra->ra_bw_mode) | (((sta->ldpc_en) ? 1 : 0) << 2) | + ((no_update_bw & 0x1) << 3) | + (ra->is_vht_enable << 4) | + ((dis_pt & 0x1) << 6) | ((dis_ra & 0x1) << 7)); + + h2c_val[3] = (u8)(ra_mask & 0xff); + h2c_val[4] = (u8)((ra_mask & 0xff00) >> 8); + h2c_val[5] = (u8)((ra_mask & 0xff0000) >> 16); + h2c_val[6] = (u8)((ra_mask & 0xff000000) >> 24); + + PHYDM_DBG(dm, DBG_RA, "PHYDM h2c[0x40]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], h2c_val[2], + h2c_val[1], h2c_val[0]); + + odm_fill_h2c_cmd(dm, PHYDM_H2C_RA_MASK, H2C_MAX_LENGTH, h2c_val); + + #if (defined(PHYDM_COMPILE_ABOVE_3SS)) + if (dm->support_ic_type & (PHYDM_IC_ABOVE_3SS)) { + h2c_val[3] = (u8)((ra_mask >> 32) & 0x000000ff); + h2c_val[4] = (u8)(((ra_mask >> 32) & 0x0000ff00) >> 8); + h2c_val[5] = (u8)(((ra_mask >> 32) & 0x00ff0000) >> 16); + h2c_val[6] = (u8)(((ra_mask >> 32) & 0xff000000) >> 24); + + PHYDM_DBG(dm, DBG_RA, "h2c[0x46]=0x%x %x %x %x %x %x %x\n", + h2c_val[6], h2c_val[5], h2c_val[4], h2c_val[3], + h2c_val[2], h2c_val[1], h2c_val[0]); + + odm_fill_h2c_cmd(dm, PHYDM_RA_MASK_ABOVE_3SS, + H2C_MAX_LENGTH, h2c_val); + } + #endif +} + +void phydm_ra_registed(void *dm_void, u8 sta_idx, + /*@index of sta_info array, not MACID*/ + u8 rssi_from_assoc) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + u8 init_ra_lv = 0; + u64 ra_mask = 0; + /*@SD7 STA_idx != macid*/ + /*@SD4,8 STA_idx == macid, */ + + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx, + sta->mac_id); + } else { + PHYDM_DBG(dm, DBG_RA_MASK, "[Warning] %s invalid STA\n", + __func__); + PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d\n", sta_idx); + return; + } + + #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + ra->rate_id = phydm_get_rate_id_88e(dm, sta_idx); + else + #endif + { + ra->rate_id = phydm_get_rate_id(dm, sta_idx); + } + + ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx); + + PHYDM_DBG(dm, DBG_RA_MASK, "rssi_assoc=%d\n", rssi_from_assoc); + + if (rssi_from_assoc > 40) + init_ra_lv = 1; + else if (rssi_from_assoc > 20) + init_ra_lv = 2; + else if (rssi_from_assoc > 1) + init_ra_lv = 3; + else + init_ra_lv = 0; + + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, sta_idx, sta, ra_mask); + + #if (RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8188E) + /*@Driver RA*/ + phydm_ra_update_8188e(dm, sta_idx, ra->rate_id, + (u32)ra_mask, ra->is_support_sgi); + else + #endif + { + /*@FW RA*/ + phydm_ra_h2c(dm, sta_idx, ra->disable_ra, ra->disable_pt, 0, + init_ra_lv, ra_mask); + } +} + +void phydm_ra_offline(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s invalid STA\n", __func__); + return; + } + + PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RA, "MACID=%d\n", sta->mac_id); + + odm_memory_set(dm, &ra->rate_id, 0, sizeof(struct ra_sta_info)); + ra->disable_ra = 1; + ra->disable_pt = 1; + + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, sta->mac_id, sta, 0); + + if (dm->support_ic_type != ODM_RTL8188E) + phydm_ra_h2c(dm, sta->mac_id, 1, 1, 0, 0, 0); +} + +void phydm_ra_mask_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + boolean force_ra_mask_en = false; + u8 sta_idx; + u64 ra_mask; + u8 rssi_lv_new; + u8 rssi = 0; + + if (!(dm->support_ability & ODM_BB_RA_MASK)) + return; + + if (!dm->is_linked || (dm->phydm_sys_up_time % 2) == 1) + return; + + PHYDM_DBG(dm, DBG_RA_MASK, "%s ======>\n", __func__); + + ra_t->up_ramask_cnt++; + + if (ra_t->up_ramask_cnt >= FORCED_UPDATE_RAMASK_PERIOD) { + ra_t->up_ramask_cnt = 0; + force_ra_mask_en = true; + } + + for (sta_idx = 0; sta_idx < ODM_ASSOCIATE_ENTRY_NUM; sta_idx++) { + sta = dm->phydm_sta_info[sta_idx]; + + if (!is_sta_active(sta)) + continue; + + ra = &sta->ra_info; + + if (ra->disable_ra) + continue; + + PHYDM_DBG(dm, DBG_RA_MASK, "sta_idx=%d, macid=%d\n", sta_idx, + sta->mac_id); + + rssi = (u8)(sta->rssi_stat.rssi); + + /*@to be modified*/ + #if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + if (dm->support_ic_type == ODM_RTL8812 || + (dm->support_ic_type == ODM_RTL8821 && + dm->cut_version == ODM_CUT_A) + ) { + if (rssi < ra_t->ldpc_thres) { + /*@LDPC TX enable*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + set_ra_ldpc_8812(sta, true); + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + MgntSet_TX_LDPC(dm->adapter, sta->mac_id, true); + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + /*to be added*/ + #endif + PHYDM_DBG(dm, DBG_RA_MASK, + "RSSI=%d, ldpc_en =TRUE\n", rssi); + + } else if (rssi > (ra_t->ldpc_thres + 3)) { + /*@LDPC TX disable*/ + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + set_ra_ldpc_8812(sta, false); + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + MgntSet_TX_LDPC(dm->adapter, sta->mac_id, false); + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + /*to be added*/ + #endif + PHYDM_DBG(dm, DBG_RA_MASK, + "RSSI=%d, ldpc_en =FALSE\n", rssi); + } + } + #endif + + rssi_lv_new = phydm_rssi_lv_dec(dm, (u32)rssi, ra->rssi_level); + + if (ra->rssi_level != rssi_lv_new || + (force_ra_mask_en && dm->number_linked_client < 10)) { + PHYDM_DBG(dm, DBG_RA_MASK, "RSSI LV:((%d))->((%d))\n", + ra->rssi_level, rssi_lv_new); + + ra->rssi_level = rssi_lv_new; + + ra_mask = phydm_get_bb_mod_ra_mask(dm, sta_idx); + + if (ra_t->record_ra_info) + ra_t->record_ra_info(dm, sta_idx, sta, ra_mask); + + #if (RTL8188E_SUPPORT) && (RATE_ADAPTIVE_SUPPORT) + if (dm->support_ic_type == ODM_RTL8188E) + /*@Driver RA*/ + phydm_ra_update_8188e(dm, sta_idx, ra->rate_id, + (u32)ra_mask, + ra->is_support_sgi); + else + #endif + { + /*@FW RA*/ + phydm_ra_h2c(dm, sta_idx, ra->disable_ra, + ra->disable_pt, 1, 0, ra_mask); + } + } + } +} + +u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 vht_en_out = 0; + + if (wireless_mode == PHYDM_WIRELESS_MODE_AC_5G || + wireless_mode == PHYDM_WIRELESS_MODE_AC_24G || + wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY) + vht_en_out = 1; + + PHYDM_DBG(dm, DBG_RA, "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", + wireless_mode, vht_en_out); + return vht_en_out; +} + +u8 phydm_rftype2rateid_2g_n20(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; + + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_BGN_20M_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else + rate_id_idx = PHYDM_ARFR7_N_4SS; + return rate_id_idx; +} + +u8 phydm_rftype2rateid_2g_n40(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; + + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_BGN_40M_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else + rate_id_idx = PHYDM_ARFR7_N_4SS; + return rate_id_idx; +} + +u8 phydm_rftype2rateid_5g_n(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; + + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_GN_N1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_GN_N2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR5_N_3SS; + else + rate_id_idx = PHYDM_ARFR7_N_4SS; + return rate_id_idx; +} + +u8 phydm_rftype2rateid_ac80(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; + + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + else + rate_id_idx = PHYDM_ARFR6_AC_4SS; + return rate_id_idx; +} + +u8 phydm_rftype2rateid_ac40(void *dm_void, u8 rf_type) +{ + u8 rate_id_idx = 0; + + if (rf_type == RF_1T1R) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else if (rf_type == RF_2T2R) + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + else if (rf_type == RF_3T3R) + rate_id_idx = PHYDM_ARFR4_AC_3SS; + else + rate_id_idx = PHYDM_ARFR6_AC_4SS; + return rate_id_idx; +} + +u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rate_id_idx = 0; + + PHYDM_DBG(dm, DBG_RA, + "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n", + wireless_mode, rf_type, bw); + + switch (wireless_mode) { + case PHYDM_WIRELESS_MODE_N_24G: + if (bw == CHANNEL_WIDTH_40) + rate_id_idx = phydm_rftype2rateid_2g_n40(dm, rf_type); + else + rate_id_idx = phydm_rftype2rateid_2g_n20(dm, rf_type); + break; + + case PHYDM_WIRELESS_MODE_N_5G: + rate_id_idx = phydm_rftype2rateid_5g_n(dm, rf_type); + break; + + case PHYDM_WIRELESS_MODE_G: + rate_id_idx = PHYDM_BG; + break; + + case PHYDM_WIRELESS_MODE_A: + rate_id_idx = PHYDM_G; + break; + + case PHYDM_WIRELESS_MODE_B: + rate_id_idx = PHYDM_B_20M; + break; + + case PHYDM_WIRELESS_MODE_AC_5G: + case PHYDM_WIRELESS_MODE_AC_ONLY: + rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type); + break; + + case PHYDM_WIRELESS_MODE_AC_24G: +/*@Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/ + if (bw >= CHANNEL_WIDTH_80) + rate_id_idx = phydm_rftype2rateid_ac80(dm, rf_type); + else + rate_id_idx = phydm_rftype2rateid_ac40(dm, rf_type); + break; + + default: + rate_id_idx = 0; + break; + } + + PHYDM_DBG(dm, DBG_RA, "RA rate ID = (( 0x%x ))\n", rate_id_idx); + + return rate_id_idx; +} + +u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + /*@MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ + u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; + u8 new_rssi_lv = 0; + u8 i; + + PHYDM_DBG(dm, DBG_RA_MASK, + "curr RA level=(%d), Table_ori=[%d, %d, %d, %d, %d, %d]\n", + ratr_state, rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], + rssi_lv_t[3], rssi_lv_t[4], rssi_lv_t[5]); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (i >= (ratr_state)) + rssi_lv_t[i] += RA_FLOOR_UP_GAP; + } + + PHYDM_DBG(dm, DBG_RA_MASK, + "RSSI=(%d), Table_mod=[%d, %d, %d, %d, %d, %d]\n", rssi, + rssi_lv_t[0], rssi_lv_t[1], rssi_lv_t[2], rssi_lv_t[3], + rssi_lv_t[4], rssi_lv_t[5]); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + if (rssi < rssi_lv_t[i]) { + new_rssi_lv = i; + break; + } + } + return new_rssi_lv; +} + +enum phydm_qam_order phydm_get_ofdm_qam_order(void *dm_void, u8 rate_idx) +{ + u8 tmp_idx = rate_idx; + enum phydm_qam_order qam_order = PHYDM_QAM_BPSK; + enum phydm_qam_order qam[10] = {PHYDM_QAM_BPSK, PHYDM_QAM_QPSK, + PHYDM_QAM_QPSK, PHYDM_QAM_16QAM, + PHYDM_QAM_16QAM, PHYDM_QAM_64QAM, + PHYDM_QAM_64QAM, PHYDM_QAM_64QAM, + PHYDM_QAM_256QAM, PHYDM_QAM_256QAM}; + + if (rate_idx <= ODM_RATE11M) + return PHYDM_QAM_CCK; + + if (rate_idx >= ODM_RATEVHTSS1MCS0) { + if (rate_idx >= ODM_RATEVHTSS4MCS0) + tmp_idx -= ODM_RATEVHTSS4MCS0; + else if (rate_idx >= ODM_RATEVHTSS3MCS0) + tmp_idx -= ODM_RATEVHTSS3MCS0; + else if (rate_idx >= ODM_RATEVHTSS2MCS0) + tmp_idx -= ODM_RATEVHTSS2MCS0; + else + tmp_idx -= ODM_RATEVHTSS1MCS0; + + qam_order = qam[tmp_idx]; + } else if (rate_idx >= ODM_RATEMCS0) { + if (rate_idx >= ODM_RATEMCS24) + tmp_idx -= ODM_RATEMCS24; + else if (rate_idx >= ODM_RATEMCS16) + tmp_idx -= ODM_RATEMCS16; + else if (rate_idx >= ODM_RATEMCS8) + tmp_idx -= ODM_RATEMCS8; + else + tmp_idx -= ODM_RATEMCS0; + + qam_order = qam[tmp_idx]; + } else { + if (rate_idx > ODM_RATE6M) { + tmp_idx -= ODM_RATE6M; + qam_order = qam[tmp_idx - 1]; + } else { + qam_order = PHYDM_QAM_BPSK; + } + } + + return qam_order; +} + +u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx) +{ + u8 rate_order = rate_idx & 0x7f; + + rate_idx &= 0x7f; + + if (rate_idx >= ODM_RATEVHTSS4MCS0) + rate_order -= ODM_RATEVHTSS4MCS0; + else if (rate_idx >= ODM_RATEVHTSS3MCS0) + rate_order -= ODM_RATEVHTSS3MCS0; + else if (rate_idx >= ODM_RATEVHTSS2MCS0) + rate_order -= ODM_RATEVHTSS2MCS0; + else if (rate_idx >= ODM_RATEVHTSS1MCS0) + rate_order -= ODM_RATEVHTSS1MCS0; + else if (rate_idx >= ODM_RATEMCS24) + rate_order -= ODM_RATEMCS24; + else if (rate_idx >= ODM_RATEMCS16) + rate_order -= ODM_RATEMCS16; + else if (rate_idx >= ODM_RATEMCS8) + rate_order -= ODM_RATEMCS8; + else if (rate_idx >= ODM_RATEMCS0) + rate_order -= ODM_RATEMCS0; + else if (rate_idx >= ODM_RATE6M) + rate_order -= ODM_RATE6M; + else + rate_order -= ODM_RATE1M; + + if (rate_idx >= ODM_RATEMCS0) + rate_order++; + + return rate_order; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +u8 phydm_rate2ss(void *dm_void, u8 rate_idx) +{ + u8 ret = 0xff; + u8 i, j; + u8 search_idx; + u32 ss_mapping_tab[4][3] = {{0x00000000, 0x003ff000, 0x000ff000}, + {0x00000000, 0xffc00000, 0x0ff00000}, + {0x000003ff, 0x0000000f, 0xf0000000}, + {0x000ffc00, 0x00000ff0, 0x00000000} }; + if (rate_idx < 32) { + search_idx = rate_idx; + j = 0; + } else if (rate_idx < 64) { + search_idx = rate_idx - 32; + j = 1; + } else { + search_idx = rate_idx - 64; + j = 2; + } + for (i = 0; i < 4; i++) + if (ss_mapping_tab[i][j] & BIT(search_idx)) + ret = i; + return ret; +} + +u8 phydm_rate2plcp(void *dm_void, u8 rate_idx) +{ + u8 rate2ss = 0; + u8 ltftime = 0; + u8 plcptime = 0xff; + + if (rate_idx < ODM_RATE6M) { + plcptime = 192; + /* @CCK PLCP = 192us (long preamble) */ + } else if (rate_idx < ODM_RATEMCS0) { + plcptime = 20; + /* @LegOFDM PLCP = 20us */ + } else { + if (rate_idx < ODM_RATEVHTSS1MCS0) + plcptime = 32; + /* @HT mode PLCP = 20us + 12us + 4us x Nss */ + else + plcptime = 36; + /* VHT mode PLCP = 20us + 16us + 4us x Nss */ + rate2ss = phydm_rate2ss(dm_void, rate_idx); + if (rate2ss != 0xff) + ltftime = (rate2ss + 1) * 4; + else + return 0xff; + + plcptime += ltftime; + } + return plcptime; +} + +u8 phydm_get_plcp(void *dm_void, u16 macid) +{ + u8 plcp_time = 0; + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct ra_sta_info *ra = NULL; + + sta = dm->phydm_sta_info[macid]; + ra = &sta->ra_info; + plcp_time = phydm_rate2plcp(dm, ra->curr_tx_rate); + return plcp_time; +} +#endif + +void phydm_ra_common_info_update(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + u16 macid; + u8 rate_order_tmp; + u8 rate_idx = 0; + u8 cnt = 0; + + ra_tab->highest_client_tx_order = 0; + ra_tab->power_tracking_flag = 1; + + if (!dm->number_linked_client) + return; + + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + sta = dm->phydm_sta_info[macid]; + + if (!is_sta_active(sta)) + continue; + + rate_idx = sta->ra_info.curr_tx_rate & 0x7f; + rate_order_tmp = phydm_rate_order_compute(dm, rate_idx); + + if (rate_order_tmp >= ra_tab->highest_client_tx_order) { + ra_tab->highest_client_tx_order = rate_order_tmp; + ra_tab->highest_client_tx_rate_order = macid; + } + + cnt++; + + if (cnt == dm->number_linked_client) + break; + } + PHYDM_DBG(dm, DBG_RA, + "MACID[%d], Highest Tx order Update for power traking: %d\n", + ra_tab->highest_client_tx_rate_order, + ra_tab->highest_client_tx_order); +} + +void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val); +} + +void phydm_masked_rrsr_set_register(void *dm_void, u32 rrsr_val) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + if (ra_tab->rrsr_val_curr == rrsr_val) + return; + + ra_tab->rrsr_val_curr = rrsr_val; + odm_set_mac_reg(dm, R_0x440, 0xfffff, rrsr_val); +} + +void phydm_rrsr_mask(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra = &dm->dm_ra_table; + struct cmn_sta_info *sta = NULL; + u8 rate_order = 0; + u8 rate_order_min = 0xff; + u32 rrsr_mask = 0, rrsr_mask_ofdm = 0; + u8 tx_rate_idx = 0; + u8 i = 0, sta_cnt = 0; + + if (!ra->dynamic_rrsr_en) + return; + + if (!dm->is_linked) { + phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init); + return; + } + +#if 1 + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (!is_sta_active(sta)) + continue; + + sta_cnt++; + tx_rate_idx = sta->ra_info.curr_tx_rate & 0x7f; + rate_order = phydm_rate_order_compute(dm, tx_rate_idx); + if (rate_order < rate_order_min) + rate_order_min = rate_order; + + if (sta_cnt == dm->number_linked_client) + break; + } +#else + sta = dm->phydm_sta_info[dm->rssi_min_macid]; + + if (!is_sta_active(sta)) { + PHYDM_DBG(dm, DBG_DYN_ARFR, "[Warning] %s invalid STA\n", + __func__); + return; + } + + rate_order = phydm_rate_order_compute(dm, sta->ra_info.curr_tx_rate); +#endif + if (rate_order_min == 0) { + rrsr_mask = 0x1f; + } else { + rrsr_mask_ofdm = (u32)phydm_gen_bitmask(rate_order_min); + rrsr_mask = (rrsr_mask_ofdm << 4) | 0xf; + } + + /*ra->rrsr_val_init = 0x15d;*/ + + phydm_masked_rrsr_set_register(dm, ra->rrsr_val_init & rrsr_mask); + + PHYDM_DBG(dm, DBG_DYN_ARFR, + "tx{rate, rate_order_min}={0x%x, %d}, rrsr_init=0x%x, ofdm_rrsr_mask=0x%x, rrsr_val=0x%x\n", + tx_rate_idx, rate_order_min, ra->rrsr_val_init, + rrsr_mask, ra->rrsr_val_curr); +} + +void phydm_ra_info_watchdog(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + phydm_ra_common_info_update(dm); + phydm_ra_dynamic_retry_count(dm); + phydm_rrsr_mask(dm); + phydm_ra_mask_watchdog(dm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + odm_refresh_basic_rate_mask(dm); +#endif +} + +void phydm_rrsr_en(void *dm_void, boolean en_rrsr) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + ra_tab->dynamic_rrsr_en = en_rrsr; +} + +void phydm_arfr_table_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & PHYDM_IC_RATEID_IDX_TYPE2) { + /*ARFR table3(2.4g ac 2ss) for rate_id = 16*/ + odm_set_mac_reg(dm, R_0x494, MASKDWORD, 0xfe01f015); + odm_set_mac_reg(dm, R_0x498, MASKDWORD, 0x40000000); + + /*ARFR table5(2.4g ac 1ss) for rate_id = 18*/ + odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0x3ff015); + odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x40000000); + } +} + +void phydm_ra_info_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + ra_tab->highest_client_tx_rate_order = 0; + ra_tab->highest_client_tx_order = 0; + ra_tab->ra_th_ofst = 0; + ra_tab->ra_ofst_direc = 0; + ra_tab->rrsr_val_init = odm_get_mac_reg(dm, R_0x440, MASKDWORD); + ra_tab->dynamic_rrsr_en = false; + ra_tab->ra_trigger_mode = 1; // default TBTT RA + ra_tab->ra_tx_cls_th = 255; +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + u32 ret_value; + + ret_value = odm_get_mac_reg(dm, R_0x4c8, MASKBYTE2); + odm_set_mac_reg(dm, R_0x4cc, MASKBYTE3, (ret_value - 1)); + } +#endif + + #if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + phydm_ra_dynamic_retry_limit_init(dm); + #endif + + #if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/ + phydm_ra_dynamic_rate_id_init(dm); + #endif + + phydm_arfr_table_init(dm); + + phydm_rate_adaptive_mask_init(dm); +} + +u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u8 rts_ini_rate = ODM_RATE6M; + + if (is_erp_protect) { /* use CCK rate as RTS*/ + rts_ini_rate = ODM_RATE1M; + } else { + switch (tx_rate) { + case ODM_RATEVHTSS4MCS9: + case ODM_RATEVHTSS4MCS8: + case ODM_RATEVHTSS4MCS7: + case ODM_RATEVHTSS4MCS6: + case ODM_RATEVHTSS4MCS5: + case ODM_RATEVHTSS4MCS4: + case ODM_RATEVHTSS4MCS3: + case ODM_RATEVHTSS3MCS9: + case ODM_RATEVHTSS3MCS8: + case ODM_RATEVHTSS3MCS7: + case ODM_RATEVHTSS3MCS6: + case ODM_RATEVHTSS3MCS5: + case ODM_RATEVHTSS3MCS4: + case ODM_RATEVHTSS3MCS3: + case ODM_RATEVHTSS2MCS9: + case ODM_RATEVHTSS2MCS8: + case ODM_RATEVHTSS2MCS7: + case ODM_RATEVHTSS2MCS6: + case ODM_RATEVHTSS2MCS5: + case ODM_RATEVHTSS2MCS4: + case ODM_RATEVHTSS2MCS3: + case ODM_RATEVHTSS1MCS9: + case ODM_RATEVHTSS1MCS8: + case ODM_RATEVHTSS1MCS7: + case ODM_RATEVHTSS1MCS6: + case ODM_RATEVHTSS1MCS5: + case ODM_RATEVHTSS1MCS4: + case ODM_RATEVHTSS1MCS3: + case ODM_RATEMCS31: + case ODM_RATEMCS30: + case ODM_RATEMCS29: + case ODM_RATEMCS28: + case ODM_RATEMCS27: + case ODM_RATEMCS23: + case ODM_RATEMCS22: + case ODM_RATEMCS21: + case ODM_RATEMCS20: + case ODM_RATEMCS19: + case ODM_RATEMCS15: + case ODM_RATEMCS14: + case ODM_RATEMCS13: + case ODM_RATEMCS12: + case ODM_RATEMCS11: + case ODM_RATEMCS7: + case ODM_RATEMCS6: + case ODM_RATEMCS5: + case ODM_RATEMCS4: + case ODM_RATEMCS3: + case ODM_RATE54M: + case ODM_RATE48M: + case ODM_RATE36M: + case ODM_RATE24M: + rts_ini_rate = ODM_RATE24M; + break; + case ODM_RATEVHTSS4MCS2: + case ODM_RATEVHTSS4MCS1: + case ODM_RATEVHTSS3MCS2: + case ODM_RATEVHTSS3MCS1: + case ODM_RATEVHTSS2MCS2: + case ODM_RATEVHTSS2MCS1: + case ODM_RATEVHTSS1MCS2: + case ODM_RATEVHTSS1MCS1: + case ODM_RATEMCS26: + case ODM_RATEMCS25: + case ODM_RATEMCS18: + case ODM_RATEMCS17: + case ODM_RATEMCS10: + case ODM_RATEMCS9: + case ODM_RATEMCS2: + case ODM_RATEMCS1: + case ODM_RATE18M: + case ODM_RATE12M: + rts_ini_rate = ODM_RATE12M; + break; + case ODM_RATEVHTSS4MCS0: + case ODM_RATEVHTSS3MCS0: + case ODM_RATEVHTSS2MCS0: + case ODM_RATEVHTSS1MCS0: + case ODM_RATEMCS24: + case ODM_RATEMCS16: + case ODM_RATEMCS8: + case ODM_RATEMCS0: + case ODM_RATE9M: + case ODM_RATE6M: + rts_ini_rate = ODM_RATE6M; + break; + case ODM_RATE11M: + case ODM_RATE5_5M: + case ODM_RATE2M: + case ODM_RATE1M: + rts_ini_rate = ODM_RATE1M; + break; + default: + rts_ini_rate = ODM_RATE6M; + break; + } + } + + if (*dm->band_type == ODM_BAND_5G) { + if (rts_ini_rate < ODM_RATE6M) + rts_ini_rate = ODM_RATE6M; + } + return rts_ini_rate; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void odm_refresh_basic_rate_mask( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *adapter = dm->adapter; + static u8 stage = 0; + u8 cur_stage = 0; + OCTET_STRING os_rate_set; + PMGNT_INFO mgnt_info = GetDefaultMgntInfo(((PADAPTER)adapter)); + u8 rate_set[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; + + if (dm->support_ic_type != ODM_RTL8812 && dm->support_ic_type != ODM_RTL8821) + return; + + if (dm->is_linked == false) /* unlink Default port information */ + cur_stage = 0; + else if (dm->rssi_min < 40) /* @link RSSI < 40% */ + cur_stage = 1; + else if (dm->rssi_min > 45) /* @link RSSI > 45% */ + cur_stage = 3; + else + cur_stage = 2; /* @link 25% <= RSSI <= 30% */ + + if (cur_stage != stage) { + if (cur_stage == 1) { + FillOctetString(os_rate_set, rate_set, 5); + FilterSupportRate(mgnt_info->mBrates, &os_rate_set, false); + phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)&os_rate_set); + } else if (cur_stage == 3 && (stage == 1 || stage == 2)) + phydm_set_hw_reg_handler_interface(dm, HW_VAR_BASIC_RATE, (u8 *)(&mgnt_info->mBrates)); + } + + stage = cur_stage; +} + +#endif + +#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + +void phydm_retry_limit_table_bound( + void *dm_void, + u8 *retry_limit, + u8 offset) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + if (*retry_limit > offset) { + *retry_limit -= offset; + + if (*retry_limit < ra_tab->retrylimit_low) + *retry_limit = ra_tab->retrylimit_low; + else if (*retry_limit > ra_tab->retrylimit_high) + *retry_limit = ra_tab->retrylimit_high; + } else + *retry_limit = ra_tab->retrylimit_low; +} + +void phydm_reset_retry_limit_table( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + u8 i; + + u8 per_rate_retrylimit_table_20M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*@CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 2, 4, 6, 8, 12, 18, 20, 22, /*@20M HT-1SS*/ + 2, 4, 6, 8, 12, 18, 20, 22 /*@20M HT-2SS*/ + }; + u8 per_rate_retrylimit_table_40M[ODM_RATEMCS15 + 1] = { + 1, 1, 2, 4, /*@CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 4, 8, 12, 16, 24, 32, 32, 32, /*@40M HT-1SS*/ + 4, 8, 12, 16, 24, 32, 32, 32 /*@40M HT-2SS*/ + }; + + memcpy(&ra_t->per_rate_retrylimit_20M[0], + &per_rate_retrylimit_table_20M[0], PHY_NUM_RATE_IDX); + memcpy(&ra_t->per_rate_retrylimit_40M[0], + &per_rate_retrylimit_table_40M[0], PHY_NUM_RATE_IDX); + + for (i = 0; i < PHY_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(dm, + &ra_t->per_rate_retrylimit_20M[i], + 0); + phydm_retry_limit_table_bound(dm, + &ra_t->per_rate_retrylimit_40M[i], + 0); + } +} + +void phydm_ra_dynamic_retry_limit_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + ra_tab->retry_descend_num = RA_RETRY_DESCEND_NUM; + ra_tab->retrylimit_low = RA_RETRY_LIMIT_LOW; + ra_tab->retrylimit_high = RA_RETRY_LIMIT_HIGH; + + phydm_reset_retry_limit_table(dm); +} + +void phydm_ra_dynamic_retry_limit( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 i, retry_offset; + u32 ma_rx_tp; + + if (dm->pre_number_active_client == dm->number_active_client) { + PHYDM_DBG(dm, DBG_RA, + "pre_number_active_client == number_active_client\n"); + return; + + } else { + if (dm->number_active_client == 1) { + phydm_reset_retry_limit_table(dm); + PHYDM_DBG(dm, DBG_RA, + "one client only->reset to default value\n"); + } else { + retry_offset = dm->number_active_client * ra_tab->retry_descend_num; + + for (i = 0; i < PHY_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_20M[i], + retry_offset); + phydm_retry_limit_table_bound(dm, + &ra_tab->per_rate_retrylimit_40M[i], + retry_offset); + } + } + } +} +#endif + +#if 0 /*@CONFIG_RA_DYNAMIC_RATE_ID*/ +void phydm_ra_dynamic_rate_id_on_assoc( + void *dm_void, + u8 wireless_mode, + u8 init_rate_id) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_RA, + "[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", + dm->rf_type, wireless_mode, init_rate_id); + + if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) { + if ((dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) && + (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G))) { + PHYDM_DBG(dm, DBG_RA, + "[ON ASSOC] set N-2SS ARFR5 table\n"); + odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + } else if ((dm->support_ic_type & (ODM_RTL8812)) && + (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY))) { + PHYDM_DBG(dm, DBG_RA, + "[ON ASSOC] set AC-2SS ARFR0 table\n"); + odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/ + } + } +} + +void phydm_ra_dynamic_rate_id_init( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E)) { + odm_set_mac_reg(dm, R_0x4a4, MASKDWORD, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + odm_set_mac_reg(dm, R_0x4a8, MASKDWORD, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + + odm_set_mac_reg(dm, R_0x444, MASKDWORD, 0x0fff); /*@AC-2SS, ARFR0, rate_id = 0x9*/ + odm_set_mac_reg(dm, R_0x448, MASKDWORD, 0xff01f000); /*@AC-2SS, ARFR0, rate_id = 0x9*/ + } +} + +void phydm_update_rate_id( + void *dm_void, + u8 rate, + u8 platform_macid) +{ +#if 0 + + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + u8 current_tx_ss; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + enum wireless_set wireless_set; + u8 phydm_macid; + struct cmn_sta_info *sta; + +#if 0 + if (rate_idx >= ODM_RATEVHTSS2MCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT2SS-MCS%d ))\n", + platform_macid, (rate_idx - ODM_RATEVHTSS2MCS0)); + /*@dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( VHT1SS-MCS%d ))\n", + platform_macid, (rate_idx - ODM_RATEVHTSS1MCS0)); + /*@dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEMCS0) { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n", + platform_macid, (rate_idx - ODM_RATEMCS0)); + /*@dummy for SD4 check patch*/ + } else { + PHYDM_DBG(dm, DBG_RA, "rate[%d]: (( HT-MCS%d ))\n", + platform_macid, rate_idx); + /*@dummy for SD4 check patch*/ + } +#endif + + phydm_macid = dm->phydm_macid_table[platform_macid]; + sta = dm->phydm_sta_info[phydm_macid]; + + if (is_sta_active(sta)) { + wireless_set = sta->support_wireless_set; + + if (dm->rf_type == RF_2T2R || dm->rf_type == RF_2T3R || dm->rf_type == RF_2T4R) { + if (wireless_set & WIRELESS_HT) { /*N mode*/ + if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*@2SS mode*/ + + sta->ra_info.rate_id = ARFR_5_RATE_ID; + PHYDM_DBG(dm, DBG_RA, "ARFR_5\n"); + } + } else if (wireless_set & WIRELESS_VHT) {/*@AC mode*/ + if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*@2SS mode*/ + + sta->ra_info.rate_id = ARFR_0_RATE_ID; + PHYDM_DBG(dm, DBG_RA, "ARFR_0\n"); + } + } else + sta->ra_info.rate_id = ARFR_0_RATE_ID; + + PHYDM_DBG(dm, DBG_RA, "UPdate_RateID[%d]: (( 0x%x ))\n", + platform_macid, sta->ra_info.rate_id); + } + } +#endif +} + +#endif diff --git a/hal/phydm/phydm_rainfo.h b/hal/phydm/phydm_rainfo.h new file mode 100644 index 0000000..5cef3ce --- /dev/null +++ b/hal/phydm/phydm_rainfo.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMRAINFO_H__ +#define __PHYDMRAINFO_H__ + +/* 2020.08.05 Fix ARFR bug due to rate_id error for 2.4G VHT mode*/ +#define RAINFO_VERSION "8.8" + +#define FORCED_UPDATE_RAMASK_PERIOD 5 + +#define H2C_MAX_LENGTH 7 + +#define RA_FLOOR_UP_GAP 3 +#define RA_FLOOR_TABLE_SIZE 7 + +#define ACTIVE_TP_THRESHOLD 1 +#define RA_RETRY_DESCEND_NUM 2 +#define RA_RETRY_LIMIT_LOW 4 +#define RA_RETRY_LIMIT_HIGH 32 + +#define PHYDM_IS_LEGACY_RATE(rate) ((rate <= ODM_RATE54M) ? true : false) +#define PHYDM_IS_CCK_RATE(rate) ((rate <= ODM_RATE11M) ? true : false) + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define FIRST_MACID 1 +#else + #define FIRST_MACID 0 +#endif + +/* @1 ============================================================ + * 1 enumrate + * 1 ============================================================ + */ + +enum phydm_ra_dbg_para { + RADBG_PCR_TH_OFFSET = 0, + RADBG_RTY_PENALTY = 1, + RADBG_N_HIGH = 2, + RADBG_N_LOW = 3, + RADBG_TRATE_UP_TABLE = 4, + RADBG_TRATE_DOWN_TABLE = 5, + RADBG_TRYING_NECESSARY = 6, + RADBG_TDROPING_NECESSARY = 7, + RADBG_RATE_UP_RTY_RATIO = 8, + RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ + + RADBG_DEBUG_MONITOR1 = 0xc, + RADBG_DEBUG_MONITOR2 = 0xd, + RADBG_DEBUG_MONITOR3 = 0xe, + RADBG_DEBUG_MONITOR4 = 0xf, + RADBG_DEBUG_MONITOR5 = 0x10, + NUM_RA_PARA +}; + +enum phydm_wireless_mode { + PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, + PHYDM_WIRELESS_MODE_A = 0x01, + PHYDM_WIRELESS_MODE_B = 0x02, + PHYDM_WIRELESS_MODE_G = 0x04, + PHYDM_WIRELESS_MODE_AUTO = 0x08, + PHYDM_WIRELESS_MODE_N_24G = 0x10, + PHYDM_WIRELESS_MODE_N_5G = 0x20, + PHYDM_WIRELESS_MODE_AC_5G = 0x40, + PHYDM_WIRELESS_MODE_AC_24G = 0x80, + PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, + PHYDM_WIRELESS_MODE_MAX = 0x800, + PHYDM_WIRELESS_MODE_ALL = 0xFFFF +}; + +enum phydm_rateid_idx { + PHYDM_BGN_40M_2SS = 0, + PHYDM_BGN_40M_1SS = 1, + PHYDM_BGN_20M_2SS = 2, + PHYDM_BGN_20M_1SS = 3, + PHYDM_GN_N2SS = 4, + PHYDM_GN_N1SS = 5, + PHYDM_BG = 6, + PHYDM_G = 7, + PHYDM_B_20M = 8, + PHYDM_ARFR0_AC_2SS = 9, + PHYDM_ARFR1_AC_1SS = 10, + PHYDM_ARFR2_AC_2G_1SS = 11, + PHYDM_ARFR3_AC_2G_2SS = 12, + PHYDM_ARFR4_AC_3SS = 13, + PHYDM_ARFR5_N_3SS = 14, + PHYDM_ARFR7_N_4SS = 15, + PHYDM_ARFR6_AC_4SS = 16 +}; + +/*ARFR4(0x49c/0x4a0) can not be used because FW BT would use.*/ +enum phydm_rateid_idx_type_2 { + PHYDM_TYPE2_AC_2SS = 9, + PHYDM_TYPE2_AC_1SS = 10, + PHYDM_TYPE2_MIX_1SS = 11, + PHYDM_TYPE2_MIX_2SS = 12, + PHYDM_TYPE2_ARFR3_AC_2G_2SS = 16, /*0x494/0x498*/ + PHYDM_TYPE2_ARFR5_AC_2G_1SS = 18 /*0x4a4/0x4a8*/ +}; + +enum phydm_qam_order { + PHYDM_QAM_CCK = 0, + PHYDM_QAM_BPSK = 1, + PHYDM_QAM_QPSK = 2, + PHYDM_QAM_16QAM = 3, + PHYDM_QAM_64QAM = 4, + PHYDM_QAM_256QAM = 5 +}; + +#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */ + +struct _phydm_txstatistic_ { + u32 hw_total_tx; + u32 hw_tx_success; + u32 hw_tx_rty; + u32 hw_tx_drop; +}; + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ +struct _odm_ra_info_ { + u8 rate_id; + u32 rate_mask; + u32 ra_use_rate; + u8 rate_sgi; + u8 rssi_sta_ra; + u8 pre_rssi_sta_ra; + u8 sgi_enable; + u8 decision_rate; + u8 pre_rate; + u8 highest_rate; + u8 lowest_rate; + u32 nsc_up; + u32 nsc_down; + u16 RTY[5]; + u32 TOTAL; + u16 DROP; + u8 active; + u16 rpt_time; + u8 ra_waiting_counter; + u8 ra_pending_counter; + u8 ra_drop_after_down; +#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */ + u8 pt_active; /* on or off */ + u8 pt_try_state; /* @0 trying state, 1 for decision state */ + u8 pt_stage; /* @0~6 */ + u8 pt_stop_count; /* Stop PT counter */ + u8 pt_pre_rate; /* @if rate change do PT */ + u8 pt_pre_rssi; /* @if RSSI change 5% do PT */ + u8 pt_mode_ss; /* @decide whitch rate should do PT */ + u8 ra_stage; /* @StageRA, decide how many times RA will be done between PT */ + u8 pt_smooth_factor; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + u8 rate_down_counter; + u8 rate_up_counter; + u8 rate_direction; + u8 bounding_type; + u8 bounding_counter; + u8 bounding_learning_time; + u8 rate_down_start_time; +#endif +}; +#endif + + +struct ra_table { + #ifdef MU_EX_MACID + u8 mu1_rate[MU_EX_MACID]; + #endif + u8 highest_client_tx_order; + u16 highest_client_tx_rate_order; + u8 power_tracking_flag; + u8 ra_th_ofst; /*RA_threshold_offset*/ + u8 ra_ofst_direc; /*RA_offset_direction*/ + u8 up_ramask_cnt; /*@force update_ra_mask counter*/ + u8 up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/ + u32 rrsr_val_init; /*0x440*/ + u32 rrsr_val_curr; /*0x440*/ + boolean dynamic_rrsr_en; + u8 ra_trigger_mode; /*0: pkt RA, 1: TBTT RA*/ + u8 ra_tx_cls_th; /*255: auto, xx: in dB*/ +#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + u8 per_rate_retrylimit_20M[PHY_NUM_RATE_IDX]; + u8 per_rate_retrylimit_40M[PHY_NUM_RATE_IDX]; + u8 retry_descend_num; + u8 retrylimit_low; + u8 retrylimit_high; +#endif + u8 ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */ + void (*record_ra_info)(void *dm_void, u8 macid, + struct cmn_sta_info *sta, u64 ra_mask); + u8 ra_mask_rpt_stamp; + u8 ra_mask_buf[8]; +}; + +struct ra_mask_rpt_trig { + u8 ra_mask_rpt_stamp; + u8 macid; +}; + +struct ra_mask_rpt { + u8 ra_mask_rpt_stamp; + u8 ra_mask_buf[8]; +}; + +/* @1 ============================================================ + * 1 Function Prototype + * 1 ============================================================ + */ +boolean phydm_is_cck_rate(void *dm_void, u8 rate); + +boolean phydm_is_ofdm_rate(void *dm_void, u8 rate); + +boolean phydm_is_ht_rate(void *dm_void, u8 rate); + +boolean phydm_is_vht_rate(void *dm_void, u8 rate); + +u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate); + +u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate); + +u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type); + +u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate); + +void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output, + u32 *_out_len); + +void phydm_ra_mask_report_h2c_trigger(void *dm_void, + struct ra_mask_rpt_trig *trig_rpt); + +void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt); + +void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component); + +void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size); + +void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); + +u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx); + +void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val); + +void phydm_ra_info_watchdog(void *dm_void); + +void phydm_rrsr_en(void *dm_void, boolean en_rrsr); + +void phydm_ra_info_init(void *dm_void); + +void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc, + u8 ra_th_ofst); + +u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode); + +u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw); +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void phydm_update_hal_ra_mask( + void *dm_void, + u32 wireless_mode, + u8 rf_type, + u8 BW, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_in, + u8 tx_rate_level); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +u8 phydm_get_plcp(void *dm_void, u16 macid); +#endif + +void phydm_refresh_rate_adaptive_mask(void *dm_void); + +u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type); + +u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state); + +void odm_ra_post_action_on_assoc(void *dm); + +u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect); + +void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx); + +void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc); + +void phydm_ra_offline(void *dm_void, u8 macid); + +void phydm_ra_mask_watchdog(void *dm_void); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void odm_refresh_basic_rate_mask( + void *dm_void); +#endif + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +void phydm_ra_mode_selection(void *dm_void, u8 mode); +#endif + +#endif /*@#ifndef __PHYDMRAINFO_H__*/ diff --git a/hal/phydm/phydm_reg.h b/hal/phydm/phydm_reg.h new file mode 100644 index 0000000..0835f34 --- /dev/null +++ b/hal/phydm/phydm_reg.h @@ -0,0 +1,243 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +/************************************************************* + * File Name: odm_reg.h + * + * Description: + * + * This file is for general register definition. + * + * + ************************************************************/ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +/*@ + * Register Definition + * + */ + +/* @MAC REG */ +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define RF_T_METER_OLD 0x24 +#define RF_T_METER_NEW 0x42 + +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +/* @LTE_COEX */ +#define REG_LTECOEX_CTRL 0x07C0 +#define REG_LTECOEX_WRITE_DATA 0x07C4 +#define REG_LTECOEX_READ_DATA 0x07C8 +#define REG_LTECOEX_PATH_CONTROL 0x70 + +/* @BB REG */ +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +/* RF REG */ +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 +#define ODM_RF_T_METER 0x24 +#define ODM_RF_T_METER_92D 0x42 +#define ODM_RF_T_METER_88E 0x42 +#define ODM_RF_T_METER_92E 0x42 +#define ODM_RF_T_METER_8812 0x42 +#define REG_RF_TX_GAIN_OFFSET 0x55 + +/* @ant Detect Reg */ +#define ODM_DPDT 0x300 + +/* PSD Init */ +#define ODM_PSDREG 0x808 + +/* @92D path Div */ +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +/*@ + * Bitmap Definition + */ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + /* TX AGC */ + #define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20 + #define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24 + #define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28 + #define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c + #define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30 + #define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34 + #define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38 + #define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c + #define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40 + #define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44 + #define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48 + #define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c + #if defined(CONFIG_WLAN_HAL_8814AE) + #define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8 + #define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc + #define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0 + #define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4 + #define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8 + #endif + #define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20 + #define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24 + #define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28 + #define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c + #define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30 + #define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34 + #define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38 + #define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c + #define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40 + #define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44 + #define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48 + #define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c + #if defined(CONFIG_WLAN_HAL_8814AE) + #define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8 + #define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc + #define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0 + #define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4 + #define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8 + #define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820 + #define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824 + #define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828 + #define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c + #define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830 + #define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834 + #define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838 + #define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c + #define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840 + #define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844 + #define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848 + #define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c + #define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8 + #define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc + #define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0 + #define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4 + #define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8 + #define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20 + #define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24 + #define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28 + #define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c + #define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30 + #define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34 + #define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38 + #define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c + #define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40 + #define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44 + #define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48 + #define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c + #define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8 + #define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc + #define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0 + #define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4 + #define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8 + #endif + + #define is_tx_agc_byte0_jaguar 0xff + #define is_tx_agc_byte1_jaguar 0xff00 + #define is_tx_agc_byte2_jaguar 0xff0000 + #define is_tx_agc_byte3_jaguar 0xff000000 +#if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\ +defined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE) ||\ +defined(CONFIG_WLAN_HAL_8197G) + #define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3 0x3a00 + #define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3 0x3a04 + #define REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3 0x3a08 + #define REG_TX_AGC_MCS3_0_JAGUAR3 0x3a0c + #define REG_TX_AGC_MCS7_4_JAGUAR3 0x3a10 + #define REG_TX_AGC_MCS11_8_JAGUAR3 0x3a14 + #define REG_TX_AGC_MCS15_12_JAGUAR3 0x3a18 + #define REG_TX_AGC_MCS19_16_JAGUAR3 0x3a1c + #define REG_TX_AGC_MCS23_20_JAGUAR3 0x3a20 + #define REG_TX_AGC_MCS27_24_JAGUAR3 0x3a24 + #define REG_TX_AGC_MCS31_28_JAGUAR3 0x3a28 + #define REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3 0x3a2c + #define REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3 0x3a30 + #define REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3 0x3a34 + #define REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3 0x3a38 + #define REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3 0x3a3c + #define REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3 0x3a40 + #define REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3 0x3a44 + #define REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3 0x3a48 + #define REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3 0x3a4c + #define REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3 0x3a50 +#endif +#endif + +#define BIT_FA_RESET BIT(0) + +#endif diff --git a/hal/phydm/phydm_regdefine11ac.h b/hal/phydm/phydm_regdefine11ac.h new file mode 100644 index 0000000..7824ac2 --- /dev/null +++ b/hal/phydm/phydm_regdefine11ac.h @@ -0,0 +1,109 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +/* @2 RF REG LIST */ + + + +/* @2 BB REG LIST */ +/* PAGE 8 */ +#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 +#define ODM_REG_BB_RX_PATH_11AC 0x808 +#define ODM_REG_BB_TX_PATH_11AC 0x80c +#define ODM_REG_BB_ATC_11AC 0x860 +#define ODM_REG_EDCCA_POWER_CAL 0x8dc +#define ODM_REG_DBG_RPT_11AC 0x8fc +/* PAGE 9 */ +#define ODM_REG_EDCCA_DOWN_OPT 0x900 +#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 +#define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/ +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +#define ODM_REG_CCX_PERIOD_11AC 0x990 +#define ODM_REG_NHM_TH9_TH10_11AC 0x994 +#define ODM_REG_CLM_11AC 0x994 +#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 +#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c +#define ODM_REG_NHM_TH8_11AC 0x9a0 +#define ODM_REG_NHM_9E8_11AC 0x9e8 +#define ODM_REG_CSI_CONTENT_VALUE 0x9b4 +/* PAGE A */ +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +/* PAGE B */ +#define ODM_REG_RST_RPT_11AC 0xB58 +/* PAGE C */ +#define ODM_REG_TRMUX_11AC 0xC08 +#define ODM_REG_IGI_A_11AC 0xC50 +/* PAGE E */ +#define ODM_REG_IGI_B_11AC 0xE50 +#define ODM_REG_ANT_11AC_B 0xE08 +/* PAGE F */ +#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 +#define ODM_REG_CCK_CCA_CNT_11AC 0xF08 +#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c +#define ODM_REG_HT_CRC32_CNT_11AC 0xF10 +#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 +#define ODM_REG_OFDM_FA_11AC 0xF48 +#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC +#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC +#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0 +#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4 +#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8 +#define ODM_REG_RPT_11AC 0xfa0 +#define ODM_REG_CLM_RESULT_11AC 0xfa4 +#define ODM_REG_NHM_CNT_11AC 0xfa8 +#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 + +#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac +#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 +/* PAGE 18 */ +#define ODM_REG_IGI_C_11AC 0x1850 +/* PAGE 1A */ +#define ODM_REG_IGI_D_11AC 0x1A50 + +/* PAGE 1D */ +#define ODM_REG_IGI_11AC3 0x1D70 + +/* @2 MAC REG LIST */ +#define ODM_REG_RESP_TX_11AC 0x6D8 + + + +/* @DIG Related */ +#define ODM_BIT_IGI_11AC 0x0000007F +#define ODM_BIT_IGI_B_11AC3 0x00007F00 +#define ODM_BIT_IGI_C_11AC3 0x007F0000 +#define ODM_BIT_IGI_D_11AC3 0x7F000000 +#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16) +#define ODM_BIT_BB_RX_PATH_11AC 0xF +#define ODM_BIT_BB_TX_PATH_11AC 0xF +#define ODM_BIT_BB_ATC_11AC BIT(14) + +#endif diff --git a/hal/phydm/phydm_regdefine11n.h b/hal/phydm/phydm_regdefine11n.h new file mode 100644 index 0000000..aa16232 --- /dev/null +++ b/hal/phydm/phydm_regdefine11n.h @@ -0,0 +1,220 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + +/* @2 RF REG LIST */ +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 +#define ODM_REF_RF_DF_11N 0xDF + + + +/* @2 BB REG LIST + * PAGE 8 + */ +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C +#define ODM_REG_RX_DEFAULT_A_11N 0x858 +#define ODM_REG_RX_DEFAULT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_CCX_PERIOD_11N 0x894 +#define ODM_REG_NHM_TH9_TH10_11N 0x890 +#define ODM_REG_CLM_11N 0x890 +#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 +#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c +#define ODM_REG_NHM_TH8_11N 0xe28 +#define ODM_REG_CLM_READY_11N 0x8b4 +#define ODM_REG_CLM_RESULT_11N 0x8d0 +#define ODM_REG_NHM_CNT_11N 0x8d8 + +/* @For struct acs_info, Jeffery, 2014-12-26 */ +#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc +#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 +#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 + +/* PAGE 9 */ +#define ODM_REG_BB_CTRL_PAGE9_11N 0x900 +#define ODM_REG_DBG_RPT_11N 0x908 +#define ODM_REG_BB_TX_PATH_11N 0x90c +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 +#define ODM_REG_RX_DFIR_MOD_97F 0x948 +#define ODM_REG_SOML_97F 0x998 + +/* PAGE A */ +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_ANT_SEL_11N 0xA04 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +/* PAGE B */ +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +#define ODM_REG_RXCK_RFMOD 0xBB0 +#define ODM_REG_EDCCA_DCNF_97F 0xBC0 + +/* PAGE C */ +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_BB_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_L1SBD_PD_CH_11N 0XC6C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_BB_AGC_SET_2_11N 0xc74 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +/* PAGE D */ +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_BB_RX_ANT_11N 0xD04 +#define ODM_REG_BB_ATC_11N 0xD2C +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +#define ODM_REG_RPT_11N 0xDF4 +/* PAGE E */ +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_EDCCA_DCNF_11N 0xE24 +#define ODM_REG_TAP_UPD_97F 0xE24 +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_PAGE_B1_97F 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC +/* PAGE F */ +#define ODM_REG_PAGE_F_RST_11N 0xF14 +#define ODM_REG_IGI_C_11N 0xF84 +#define ODM_REG_IGI_D_11N 0xF88 +#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 +#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 +#define ODM_REG_HT_CRC32_CNT_11N 0xF90 +#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 +#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8 + +/* @2 MAC REG LIST */ +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + + +/* @DIG Related */ +#define ODM_BIT_IGI_11N 0x0000007F +#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9) +#define ODM_BIT_BB_RX_PATH_11N 0xF +#define ODM_BIT_BB_TX_PATH_11N 0xF +#define ODM_BIT_BB_ATC_11N BIT(11) +#endif + diff --git a/hal/phydm/phydm_regtable.h b/hal/phydm/phydm_regtable.h new file mode 100644 index 0000000..155d2e4 --- /dev/null +++ b/hal/phydm/phydm_regtable.h @@ -0,0 +1,1122 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2019 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * + *****************************************************************************/ + +#define R_0x0 0x0 +#define R_0x00 0x00 +#define R_0x08 0x08 +#define R_0x0106 0x0106 +#define R_0x0140 0x0140 +#define R_0x0144 0x0144 +#define R_0x0148 0x0148 +#define R_0x040 0x040 +#define R_0x10 0x10 +#define R_0x100 0x100 +#define R_0x1000 0x1000 +#define R_0x1008 0x1008 +#define R_0x1038 0x1038 +#define R_0x103c 0x103c +#define R_0x1040 0x1040 +#define R_0x1048 0x1048 +#define R_0x1064 0x1064 +#define R_0x1080 0x1080 +#define R_0x10d8 0x10d8 +#define R_0x10dc 0x10dc +#define R_0x1200 0x1200 +#define R_0x1204 0x1204 +#define R_0x1208 0x1208 +#define R_0x1210 0x1210 +#define R_0x1214 0x1214 +#define R_0x1218 0x1218 +#define R_0x121c 0x121c +#define R_0x14 0x14 +#define R_0x14c0 0x14c0 +#define R_0x14c4 0x14c4 +#define R_0x14c8 0x14c8 +#define R_0x14cc 0x14cc +#define R_0x1518 0x1518 +#define R_0x1684 0x1684 +#define R_0x1688 0x1688 +#define R_0x168c 0x168c +#define R_0x1700 0x1700 +#define R_0x1704 0x1704 +#define R_0x1800 0x1800 +#define R_0x1804 0x1804 +#define R_0x1808 0x1808 +#define R_0x180c 0x180c +#define R_0x1810 0x1810 +#define R_0x1814 0x1814 +#define R_0x1818 0x1818 +#define R_0x181c 0x181c +#define R_0x1830 0x1830 +#define R_0x1834 0x1834 +#define R_0x1838 0x1838 +#define R_0x183c 0x183c +#define R_0x1840 0x1840 +#define R_0x1844 0x1844 +#define R_0x1848 0x1848 +#define R_0x1860 0x1860 +#define R_0x1864 0x1864 +#define R_0x1868 0x1868 +#define R_0x186c 0x186c +#define R_0x1870 0x1870 +#define R_0x1880 0x1880 +#define R_0x1884 0x1884 +#define R_0x188c 0x188c +#define R_0x1894 0x1894 +#define R_0x189c 0x189c +#define R_0x18a0 0x18a0 +#define R_0x18a4 0x18a4 +#define R_0x18a8 0x18a8 +#define R_0x18ac 0x18ac +#define R_0x18e0 0x18e0 +#define R_0x18e8 0x18e8 +#define R_0x18ec 0x18ec +#define R_0x18f0 0x18f0 +#define R_0x18f8 0x18f8 +#define R_0x18fc 0x18fc +#define R_0x1900 0x1900 +#define R_0x1904 0x1904 +#define R_0x1908 0x1908 +#define R_0x1910 0x1910 +#define R_0x1918 0x1918 +#define R_0x191c 0x191c +#define R_0x1928 0x1928 +#define R_0x1938 0x1938 +#define R_0x1940 0x1940 +#define R_0x1944 0x1944 +#define R_0x1950 0x1950 +#define R_0x1954 0x1954 +#define R_0x195c 0x195c +#define R_0x1970 0x1970 +#define R_0x1984 0x1984 +#define R_0x1988 0x1988 +#define R_0x198c 0x198c +#define R_0x1990 0x1990 +#define R_0x1991 0x1991 +#define R_0x1998 0x1998 +#define R_0x19a8 0x19a8 +#define R_0x19b8 0x19b8 +#define R_0x19d4 0x19d4 +#define R_0x19d8 0x19d8 +#define R_0x19e0 0x19e0 +#define R_0x19f0 0x19f0 +#define R_0x19f8 0x19f8 +#define R_0x1a00 0x1a00 +#define R_0x1a04 0x1a04 +#define R_0x1a08 0x1a08 +#define R_0x1a0c 0x1a0c +#define R_0x1a10 0x1a10 +#define R_0x1a14 0x1a14 +#define R_0x1a18 0x1a18 +#define R_0x1a1c 0x1a1c +#define R_0x1a20 0x1a20 +#define R_0x1a24 0x1a24 +#define R_0x1a28 0x1a28 +#define R_0x1a2c 0x1a2c +#define R_0x1a30 0x1a30 +#define R_0x1a34 0x1a34 +#define R_0x1a38 0x1a38 +#define R_0x1a48 0x1a48 +#define R_0x1a5c 0x1a5c +#define R_0x1a70 0x1a70 +#define R_0x1a74 0x1a74 +#define R_0x1a80 0x1a80 +#define R_0x1a84 0x1a84 +#define R_0x1a8c 0x1a8c +#define R_0x1a94 0x1a94 +#define R_0x1a98 0x1a98 +#define R_0x1a9c 0x1a9c +#define R_0x1aa0 0x1aa0 +#define R_0x1aa8 0x1aa8 +#define R_0x1aac 0x1aac +#define R_0x1ab0 0x1ab0 +#define R_0x1abc 0x1abc +#define R_0x1ac0 0x1ac0 +#define R_0x1ac8 0x1ac8 +#define R_0x1acc 0x1acc +#define R_0x1ad0 0x1ad0 +#define R_0x1ad4 0x1ad4 +#define R_0x1ae0 0x1ae0 +#define R_0x1ae8 0x1ae8 +#define R_0x1aec 0x1aec +#define R_0x1b00 0x1b00 +#define R_0x1b04 0x1b04 +#define R_0x1b08 0x1b08 +#define R_0x1b0c 0x1b0c +#define R_0x1b10 0x1b10 +#define R_0x1b14 0x1b14 +#define R_0x1b18 0x1b18 +#define R_0x1b1c 0x1b1c +#define R_0x1b20 0x1b20 +#define R_0x1b23 0x1b23 +#define R_0x1b24 0x1b24 +#define R_0x1b28 0x1b28 +#define R_0x1b2c 0x1b2c +#define R_0x1b30 0x1b30 +#define R_0x1b34 0x1b34 +#define R_0x1b38 0x1b38 +#define R_0x1b3c 0x1b3c +#define R_0x1b40 0x1b40 +#define R_0x1b44 0x1b44 +#define R_0x1b48 0x1b48 +#define R_0x1b4c 0x1b4c +#define R_0x1b50 0x1b50 +#define R_0x1b54 0x1b54 +#define R_0x1b58 0x1b58 +#define R_0x1b5c 0x1b5c +#define R_0x1b60 0x1b60 +#define R_0x1b64 0x1b64 +#define R_0x1b67 0x1b67 +#define R_0x1b68 0x1b68 +#define R_0x1b6c 0x1b6c +#define R_0x1b70 0x1b70 +#define R_0x1b74 0x1b74 +#define R_0x1b78 0x1b78 +#define R_0x1b7c 0x1b7c +#define R_0x1b80 0x1b80 +#define R_0x1b83 0x1b83 +#define R_0x1b84 0x1b84 +#define R_0x1b88 0x1b88 +#define R_0x1b8c 0x1b8c +#define R_0x1b90 0x1b90 +#define R_0x1b92 0x1b92 +#define R_0x1b94 0x1b94 +#define R_0x1b97 0x1b97 +#define R_0x1b98 0x1b98 +#define R_0x1b9c 0x1b9c +#define R_0x1ba0 0x1ba0 +#define R_0x1ba4 0x1ba4 +#define R_0x1ba8 0x1ba8 +#define R_0x1bac 0x1bac +#define R_0x1bb0 0x1bb0 +#define R_0x1bb4 0x1bb4 +#define R_0x1bb8 0x1bb8 +#define R_0x1bbc 0x1bbc +#define R_0x1bc0 0x1bc0 +#define R_0x1bc4 0x1bc4 +#define R_0x1bc8 0x1bc8 +#define R_0x1bca 0x1bca +#define R_0x1bcb 0x1bcb +#define R_0x1bcc 0x1bcc +#define R_0x1bce 0x1bce +#define R_0x1bd0 0x1bd0 +#define R_0x1bd4 0x1bd4 +#define R_0x1bd6 0x1bd6 +#define R_0x1bd8 0x1bd8 +#define R_0x1bdc 0x1bdc +#define R_0x1be3 0x1be3 +#define R_0x1be4 0x1be4 +#define R_0x1be8 0x1be8 +#define R_0x1beb 0x1beb +#define R_0x1bec 0x1bec +#define R_0x1bef 0x1bef +#define R_0x1bf0 0x1bf0 +#define R_0x1bf4 0x1bf4 +#define R_0x1bf8 0x1bf8 +#define R_0x1bfc 0x1bfc +#define R_0x1c 0x1c +#define R_0x1c20 0x1c20 +#define R_0x1c24 0x1c24 +#define R_0x1c28 0x1c28 +#define R_0x1c2c 0x1c2c +#define R_0x1c30 0x1c30 +#define R_0x1c34 0x1c34 +#define R_0x1c38 0x1c38 +#define R_0x1c3c 0x1c3c +#define R_0x1c64 0x1c64 +#define R_0x1c68 0x1c68 +#define R_0x1c6c 0x1c6c +#define R_0x1c74 0x1c74 +#define R_0x1c78 0x1c78 +#define R_0x1c7c 0x1c7c +#define R_0x1c80 0x1c80 +#define R_0x1c8c 0x1c8c +#define R_0x1c90 0x1c90 +#define R_0x1c94 0x1c94 +#define R_0x1c98 0x1c98 +#define R_0x1c9c 0x1c9c +#define R_0x1ca0 0x1ca0 +#define R_0x1ca4 0x1ca4 +#define R_0x1cb0 0x1cb0 +#define R_0x1cb8 0x1cb8 +#define R_0x1cbc 0x1cbc +#define R_0x1cc0 0x1cc0 +#define R_0x1cd0 0x1cd0 +#define R_0x1cd8 0x1cd8 +#define R_0x1ce4 0x1ce4 +#define R_0x1ce8 0x1ce8 +#define R_0x1cec 0x1cec +#define R_0x1cf0 0x1cf0 +#define R_0x1cf4 0x1cf4 +#define R_0x1cf8 0x1cf8 +#define R_0x1d04 0x1d04 +#define R_0x1d08 0x1d08 +#define R_0x1d0c 0x1d0c +#define R_0x1d10 0x1d10 +#define R_0x1d2c 0x1d2c +#define R_0x1d30 0x1d30 +#define R_0x1d3c 0x1d3c +#define R_0x1d40 0x1d40 +#define R_0x1d44 0x1d44 +#define R_0x1d48 0x1d48 +#define R_0x1d58 0x1d58 +#define R_0x1d60 0x1d60 +#define R_0x1d6c 0x1d6c +#define R_0x1d70 0x1d70 +#define R_0x1d90 0x1d90 +#define R_0x1d94 0x1d94 +#define R_0x1d9c 0x1d9c +#define R_0x1da4 0x1da4 +#define R_0x1da8 0x1da8 +#define R_0x1de8 0x1de8 +#define R_0x1e14 0x1e14 +#define R_0x1e18 0x1e18 +#define R_0x1e1c 0x1e1c +#define R_0x1e24 0x1e24 +#define R_0x1e28 0x1e28 +#define R_0x1e2c 0x1e2c +#define R_0x1e28 0x1e28 +#define R_0x1e30 0x1e30 +#define R_0x1e40 0x1e40 +#define R_0x1e44 0x1e44 +#define R_0x1e48 0x1e48 +#define R_0x1e4c 0x1e4c +#define R_0x1e50 0x1e50 +#define R_0x1e54 0x1e54 +#define R_0x1e58 0x1e58 +#define R_0x1e5c 0x1e5c +#define R_0x1e60 0x1e60 +#define R_0x1e64 0x1e64 +#define R_0x1e68 0x1e68 +#define R_0x1e6c 0x1e6c +#define R_0x1e70 0x1e70 +#define R_0x1e7c 0x1e7c +#define R_0x1e80 0x1e80 +#define R_0x1e84 0x1e84 +#define R_0x1e88 0x1e88 +#define R_0x1e8c 0x1e8c +#define R_0x1ea4 0x1ea4 +#define R_0x1eb4 0x1eb4 +#define R_0x1eb8 0x1eb8 +#define R_0x1ed4 0x1ed4 +#define R_0x1ed8 0x1ed8 +#define R_0x1edc 0x1edc +#define R_0x1ee0 0x1ee0 +#define R_0x1ee4 0x1ee4 +#define R_0x1ee8 0x1ee8 +#define R_0x1eec 0x1eec +#define R_0x1ef0 0x1ef0 +#define R_0x1ef4 0x1ef4 +#define R_0x1ef8 0x1ef8 +#define R_0x1efc 0x1efc +#define R_0x1f80 0x1f80 +#define R_0x1f98 0x1f98 +#define R_0x24 0x24 +#define R_0x28 0x28 +#define R_0x2a00 0x2a00 +#define R_0x2a04 0x2a04 +#define R_0x2a08 0x2a08 +#define R_0x2a24 0x2a24 +#define R_0x2a38 0x2a38 +#define R_0x2a3c 0x2a3c +#define R_0x2a44 0x2a44 +#define R_0x2aa0 0x2aa0 +#define R_0x2aa8 0x2aa8 +#define R_0x2aac 0x2aac +#define R_0x2ad0 0x2ad0 +#define R_0x2c 0x2c +#define R_0x28a4 0x28a4 +#define R_0x28bc 0x28bc +#define R_0x2c04 0x2c04 +#define R_0x2c08 0x2c08 +#define R_0x2c0c 0x2c0c +#define R_0x2c10 0x2c10 +#define R_0x2c14 0x2c14 +#define R_0x2c18 0x2c18 +#define R_0x2c1c 0x2c1c +#define R_0x2c20 0x2c20 +#define R_0x2c2c 0x2c2c +#define R_0x2c30 0x2c30 +#define R_0x2c34 0x2c34 +#define R_0x2c54 0x2c54 +#define R_0x2d00 0x2d00 +#define R_0x2d04 0x2d04 +#define R_0x2d08 0x2d08 +#define R_0x2d0c 0x2d0c +#define R_0x2d10 0x2d10 +#define R_0x2d20 0x2d20 +#define R_0x2d38 0x2d38 +#define R_0x2d40 0x2d40 +#define R_0x2d44 0x2d44 +#define R_0x2d48 0x2d48 +#define R_0x2d4c 0x2d4c +#define R_0x2d6c 0x2d6c +#define R_0x2d84 0x2d84 +#define R_0x2d88 0x2d88 +#define R_0x2d90 0x2d90 +#define R_0x2d9c 0x2d9c +#define R_0x2db4 0x2db4 +#define R_0x2db8 0x2db8 +#define R_0x2dbc 0x2dbc +#define R_0x2de0 0x2de0 +#define R_0x2de4 0x2de4 +#define R_0x2de8 0x2de8 +#define R_0x2e00 0x2e00 +#define R_0x2e20 0x2e20 +#define R_0x2e60 0x2e60 +#define R_0x2e64 0x2e64 +#define R_0x2e68 0x2e68 +#define R_0x2e6c 0x2e6c +#define R_0x2e70 0x2e70 +#define R_0x2e74 0x2e74 +#define R_0x2e78 0x2e78 +#define R_0x2e7c 0x2e7c +#define R_0x2e80 0x2e80 +#define R_0x300 0x300 +#define R_0x38 0x38 +#define R_0x3a00 0x3a00 +#define R_0x3a04 0x3a04 +#define R_0x3a08 0x3a08 +#define R_0x3a0c 0x3a0c +#define R_0x3a10 0x3a10 +#define R_0x3a14 0x3a14 +#define R_0x3a18 0x3a18 +#define R_0x3a1c 0x3a1c +#define R_0x3a20 0x3a20 +#define R_0x3a24 0x3a24 +#define R_0x3a28 0x3a28 +#define R_0x3a2c 0x3a2c +#define R_0x3a30 0x3a30 +#define R_0x3a34 0x3a34 +#define R_0x3a38 0x3a38 +#define R_0x3a3c 0x3a3c +#define R_0x3a40 0x3a40 +#define R_0x3a44 0x3a44 +#define R_0x3a48 0x3a48 +#define R_0x3a4c 0x3a4c +#define R_0x3a50 0x3a50 +#define R_0x3a54 0x3a54 +#define R_0x3a58 0x3a58 +#define R_0x3a5c 0x3a5c +#define R_0x3a60 0x3a60 +#define R_0x3a64 0x3a64 +#define R_0x3a68 0x3a68 +#define R_0x3a6c 0x3a6c +#define R_0x3a70 0x3a70 +#define R_0x3a74 0x3a74 +#define R_0x3a78 0x3a78 +#define R_0x3a7c 0x3a7c +#define R_0x3a80 0x3a80 +#define R_0x3a84 0x3a84 +#define R_0x3a88 0x3a88 +#define R_0x3a8c 0x3a8c +#define R_0x3a90 0x3a90 +#define R_0x3a94 0x3a94 +#define R_0x3a98 0x3a98 +#define R_0x3a9c 0x3a9c +#define R_0x3aa0 0x3aa0 +#define R_0x3aa4 0x3aa4 +#define R_0x3c00 0x3c00 +#define R_0x40 0x40 +#define R_0x4000 0x4000 +#define R_0x4008 0x4008 +#define R_0x4018 0x4018 +#define R_0x401c 0x401c +#define R_0x4028 0x4028 +#define R_0x4040 0x4040 +#define R_0x4044 0x4044 +#define R_0x4100 0x4100 +#define R_0x4104 0x4104 +#define R_0x4108 0x4108 +#define R_0x410c 0x410c +#define R_0x4110 0x4110 +#define R_0x4114 0x4114 +#define R_0x4118 0x4118 +#define R_0x411c 0x411c +#define R_0x4130 0x4130 +#define R_0x4134 0x4134 +#define R_0x4138 0x4138 +#define R_0x413c 0x413c +#define R_0x4140 0x4140 +#define R_0x4144 0x4144 +#define R_0x4148 0x4148 +#define R_0x4160 0x4160 +#define R_0x4164 0x4164 +#define R_0x4168 0x4168 +#define R_0x416c 0x416c +#define R_0x4180 0x4180 +#define R_0x419c 0x419c +#define R_0x41a0 0x41a0 +#define R_0x41a4 0x41a4 +#define R_0x41a8 0x41a8 +#define R_0x41ac 0x41ac +#define R_0x41e0 0x41e0 +#define R_0x41e8 0x41e8 +#define R_0x41ec 0x41ec +#define R_0x41f0 0x41f0 +#define R_0x41f8 0x41f8 +#define R_0x41fc 0x41fc +#define R_0x42 0x42 +#define R_0x430 0x430 +#define R_0x434 0x434 +#define R_0x42b0 0x42b0 +#define R_0x42b4 0x42b4 +#define R_0x42f0 0x42f0 +#define R_0x4300 0x4300 +#define R_0x4304 0x4304 +#define R_0x4308 0x4308 +#define R_0x430c 0x430c +#define R_0x4310 0x4310 +#define R_0x4314 0x4314 +#define R_0x4318 0x4318 +#define R_0x431c 0x431c +#define R_0x4320 0x4320 +#define R_0x4324 0x4324 +#define R_0x4328 0x4328 +#define R_0x432c 0x432c +#define R_0x4330 0x4330 +#define R_0x4334 0x4334 +#define R_0x4338 0x4338 +#define R_0x433c 0x433c +#define R_0x4340 0x4340 +#define R_0x4344 0x4344 +#define R_0x4348 0x4348 +#define R_0x434c 0x434c +#define R_0x4350 0x4350 +#define R_0x4354 0x4354 +#define R_0x4358 0x4358 +#define R_0x435c 0x435c +#define R_0x4360 0x4360 +#define R_0x4364 0x4364 +#define R_0x4368 0x4368 +#define R_0x436c 0x436c +#define R_0x4370 0x4370 +#define R_0x4374 0x4374 +#define R_0x4378 0x4378 +#define R_0x437c 0x437c +#define R_0x4380 0x4380 +#define R_0x4384 0x4384 +#define R_0x4388 0x4388 +#define R_0x438c 0x438c +#define R_0x4390 0x4390 +#define R_0x4394 0x4394 +#define R_0x4398 0x4398 +#define R_0x439c 0x439c +#define R_0x43a0 0x43a0 +#define R_0x43a4 0x43a4 +#define R_0x43a8 0x43a8 +#define R_0x43ac 0x43ac +#define R_0x43b0 0x43b0 +#define R_0x43b4 0x43b4 +#define R_0x43b8 0x43b8 +#define R_0x44 0x44 +#define R_0x440 0x440 +#define R_0x444 0x444 +#define R_0x448 0x448 +#define R_0x450 0x450 +#define R_0x454 0x454 +#define R_0x494 0x494 +#define R_0x498 0x498 +#define R_0x49c 0x49c +#define R_0x4a0 0x4a0 +#define R_0x4a4 0x4a4 +#define R_0x4a8 0x4a8 +#define R_0x4c 0x4c +#define R_0x4c8 0x4c8 +#define R_0x4cc 0x4cc +#define R_0x45a4 0x45a4 +#define R_0x4c00 0x4c00 +#define R_0x5000 0x5000 +#define R_0x5008 0x5008 +#define R_0x5018 0x5018 +#define R_0x501c 0x501c +#define R_0x5028 0x5028 +#define R_0x5040 0x5040 +#define R_0x5044 0x5044 +#define R_0x5100 0x5100 +#define R_0x5108 0x5108 +#define R_0x5118 0x5118 +#define R_0x511c 0x511c +#define R_0x5128 0x5128 +#define R_0x5140 0x5140 +#define R_0x5144 0x5144 +#define R_0x520 0x520 +#define R_0x5200 0x5200 +#define R_0x520c 0x520c +#define R_0x522 0x522 +#define R_0x524 0x524 +#define R_0x5230 0x5230 +#define R_0x5234 0x5234 +#define R_0x5238 0x5238 +#define R_0x523c 0x523c +#define R_0x5240 0x5240 +#define R_0x5244 0x5244 +#define R_0x5248 0x5248 +#define R_0x526c 0x526c +#define R_0x5280 0x5280 +#define R_0x52a0 0x52a0 +#define R_0x52a4 0x52a4 +#define R_0x52ac 0x52ac +#define R_0x52e8 0x52e8 +#define R_0x5300 0x5300 +#define R_0x530c 0x530c +#define R_0x5330 0x5330 +#define R_0x5334 0x5334 +#define R_0x5338 0x5338 +#define R_0x533c 0x533c +#define R_0x5340 0x5340 +#define R_0x5344 0x5344 +#define R_0x5348 0x5348 +#define R_0x536c 0x536c +#define R_0x5380 0x5380 +#define R_0x53a0 0x53a0 +#define R_0x53a4 0x53a4 +#define R_0x53ac 0x53ac +#define R_0x53e8 0x53e8 +#define R_0x550 0x550 +#define R_0x551 0x551 +#define R_0x568 0x568 +#define R_0x588 0x588 +#define R_0x60 0x60 +#define R_0x604 0x604 +#define R_0x608 0x608 +#define R_0x60c 0x60c +#define R_0x60f 0x60f +#define R_0x64 0x64 +#define R_0x66 0x66 +#define R_0x660 0x660 +#define R_0x668 0x668 +#define R_0x688 0x688 +#define R_0x6a0 0x6a0 +#define R_0x6d8 0x6d8 +#define R_0x6dc 0x6dc +#define R_0x6f8 0x6f8 +#define R_0x70 0x70 +#define R_0x74 0x74 +#define R_0x700 0x700 +#define R_0x71c 0x71c +#define R_0x72c 0x72c +#define R_0x764 0x764 +#define R_0x7b0 0x7b0 +#define R_0x7b4 0x7b4 +#define R_0x7c0 0x7c0 +#define R_0x7c4 0x7c4 +#define R_0x7c8 0x7c8 +#define R_0x7cc 0x7cc +#define R_0x7f0 0x7f0 +#define R_0x7f4 0x7f4 +#define R_0x7f8 0x7f8 +#define R_0x7fc 0x7fc +#define R_0x800 0x800 +#define R_0x8000 0x8000 +#define R_0x804 0x804 +#define R_0x808 0x808 +#define R_0x80c 0x80c +#define R_0x810 0x810 +#define R_0x814 0x814 +#define R_0x818 0x818 +#define R_0x81c 0x81c +#define R_0x820 0x820 +#define R_0x824 0x824 +#define R_0x828 0x828 +#define R_0x82c 0x82c +#define R_0x830 0x830 +#define R_0x834 0x834 +#define R_0x838 0x838 +#define R_0x83c 0x83c +#define R_0x840 0x840 +#define R_0x844 0x840 +#define R_0x848 0x848 +#define R_0x84c 0x84c +#define R_0x850 0x850 +#define R_0x854 0x854 +#define R_0x858 0x858 +#define R_0x85c 0x85c +#define R_0x860 0x860 +#define R_0x864 0x864 +#define R_0x868 0x868 +#define R_0x86c 0x86c +#define R_0x870 0x870 +#define R_0x874 0x874 +#define R_0x878 0x878 +#define R_0x87c 0x87c +#define R_0x880 0x880 +#define R_0x884 0x884 +#define R_0x888 0x888 +#define R_0x88c 0x88c +#define R_0x890 0x890 +#define R_0x894 0x894 +#define R_0x898 0x898 +#define R_0x89c 0x89c +#define R_0x8a0 0x8a0 +#define R_0x8a4 0x8a4 +#define R_0x8ac 0x8ac +#define R_0x8b4 0x8b4 +#define R_0x8b8 0x8b8 +#define R_0x8c0 0x8c0 +#define R_0x8c4 0x8c4 +#define R_0x8c8 0x8c8 +#define R_0x8cc 0x8cc +#define R_0x8d0 0x8d0 +#define R_0x8d4 0x8d4 +#define R_0x8d8 0x8d8 +#define R_0x8dc 0x8dc +#define R_0x8f0 0x8f0 +#define R_0x8f8 0x8f8 +#define R_0x8fc 0x8fc +#define R_0x900 0x900 +#define R_0x908 0x908 +#define R_0x90c 0x90c +#define R_0x910 0x910 +#define R_0x914 0x914 +#define R_0x918 0x918 +#define R_0x91c 0x91c +#define R_0x920 0x920 +#define R_0x924 0x924 +#define R_0x92c 0x92c +#define R_0x930 0x930 +#define R_0x934 0x934 +#define R_0x938 0x938 +#define R_0x93c 0x93c +#define R_0x940 0x940 +#define R_0x944 0x944 +#define R_0x948 0x948 +#define R_0x94c 0x94c +#define R_0x950 0x950 +#define R_0x954 0x954 +#define R_0x958 0x958 +#define R_0x95c 0x95c +#define R_0x960 0x960 +#define R_0x964 0x964 +#define R_0x968 0x968 +#define R_0x970 0x970 +#define R_0x974 0x974 +#define R_0x978 0x978 +#define R_0x97c 0x97c +#define R_0x980 0x980 +#define R_0x988 0x988 +#define R_0x98c 0x98c +#define R_0x990 0x990 +#define R_0x994 0x994 +#define R_0x998 0x998 +#define R_0x99c 0x99c +#define R_0x9a0 0x9a0 +#define R_0x9a4 0x9a4 +#define R_0x9ac 0x9ac +#define R_0x9b0 0x9b0 +#define R_0x9b4 0x9b4 +#define R_0x9b8 0x9b8 +#define R_0x9cc 0x9cc +#define R_0x9d0 0x9d0 +#define R_0x9d8 0x9d8 +#define R_0x9e4 0x9e4 +#define R_0x9e8 0x9e8 +#define R_0x9f0 0x9f0 +#define R_0xa0 0xa0 +#define R_0xa00 0xa00 +#define R_0xa04 0xa04 +#define R_0xa08 0xa08 +#define R_0xa0a 0xa0a +#define R_0xa0c 0xa0c +#define R_0xa10 0xa10 +#define R_0xa14 0xa14 +#define R_0xa20 0xa20 +#define R_0xa24 0xa24 +#define R_0xa28 0xa28 +#define R_0xa2c 0xa2c +#define R_0xa40 0xa40 +#define R_0xa44 0xa44 +#define R_0xa48 0xa48 +#define R_0xa4c 0xa4c +#define R_0xa50 0xa50 +#define R_0xa54 0xa54 +#define R_0xa58 0xa58 +#define R_0xa68 0xa68 +#define R_0xa6c 0xa6c +#define R_0xa70 0xa70 +#define R_0xa74 0xa74 +#define R_0xa78 0xa78 +#define R_0xa8 0xa8 +#define R_0xa80 0xa80 +#define R_0xa84 0xa84 +#define R_0xa98 0xa98 +#define R_0xa9c 0xa9c +#define R_0xaa8 0xaa8 +#define R_0xaac 0xaac +#define R_0xab4 0xab4 +#define R_0xabc 0xabc +#define R_0xac 0xac +#define R_0xac8 0xac8 +#define R_0xacc 0xacc +#define R_0xad0 0xad0 +#define R_0xb0 0xb0 +#define R_0xb00 0xb00 +#define R_0xb04 0xb04 +#define R_0xb07 0xb07 +#define R_0xb08 0xb08 +#define R_0xb0c 0xb0c +#define R_0xb10 0xb10 +#define R_0xb14 0xb14 +#define R_0xb18 0xb18 +#define R_0xb1c 0xb1c +#define R_0xb20 0xb20 +#define R_0xb24 0xb24 +#define R_0xb28 0xb28 +#define R_0xb2a 0xb2a +#define R_0xb2b 0xb2b +#define R_0xb2c 0xb2c +#define R_0xb30 0xb30 +#define R_0xb34 0xb34 +#define R_0xb38 0xb38 +#define R_0xb3b 0xb3b +#define R_0xb3c 0xb3c +#define R_0xb40 0xb40 +#define R_0xb44 0xb44 +#define R_0xb48 0xb48 +#define R_0xb54 0xb54 +#define R_0xb58 0xb58 +#define R_0xb60 0xb60 +#define R_0xb64 0xb64 +#define R_0xb68 0xb68 +#define R_0xb6a 0xb6a +#define R_0xb6b 0xb6b +#define R_0xb6c 0xb6c +#define R_0xb6e 0xb6e +#define R_0xb70 0xb70 +#define R_0xb74 0xb74 +#define R_0xb77 0xb77 +#define R_0xb78 0xb78 +#define R_0xb7c 0xb7c +#define R_0xb80 0xb80 +#define R_0xb84 0xb84 +#define R_0xb88 0xb88 +#define R_0xb8c 0xb8c +#define R_0xb90 0xb90 +#define R_0xb94 0xb94 +#define R_0xb98 0xb98 +#define R_0xb9b 0xb9b +#define R_0xb9c 0xb9c +#define R_0xba0 0xba0 +#define R_0xba4 0xba4 +#define R_0xba8 0xba8 +#define R_0xbac 0xbac +#define R_0xbad 0xbad +#define R_0xbc0 0xbc0 +#define R_0xbc4 0xbc4 +#define R_0xbc8 0xbc8 +#define R_0xbcc 0xbcc +#define R_0xbd8 0xbd8 +#define R_0xbdc 0xbdc +#define R_0xbe0 0xbe0 +#define R_0xbe4 0xbe4 +#define R_0xbe8 0xbe8 +#define R_0xbec 0xbec +#define R_0xbf0 0xbf0 +#define R_0xbf4 0xbf4 +#define R_0xbf8 0xbf8 +#define R_0xc00 0xc00 +#define R_0xc04 0xc04 +#define R_0xc08 0xc08 +#define R_0xc0c 0xc0c +#define R_0xc10 0xc10 +#define R_0xc14 0xc14 +#define R_0xc18 0xc18 +#define R_0xc1c 0xc1c +#define R_0xc20 0xc20 +#define R_0xc24 0xc24 +#define R_0xc2c 0xc2c +#define R_0xc30 0xc30 +#define R_0xc34 0xc34 +#define R_0xc38 0xc38 +#define R_0xc3c 0xc3c +#define R_0xc40 0xc40 +#define R_0xc44 0xc44 +#define R_0xc4c 0xc4c +#define R_0xc50 0xc50 +#define R_0xc54 0xc54 +#define R_0xc58 0xc58 +#define R_0xc5c 0xc5c +#define R_0xc6c 0xc6c +#define R_0xc70 0xc70 +#define R_0xc74 0xc74 +#define R_0xc78 0xc78 +#define R_0xc7c 0xc7c +#define R_0xc80 0xc80 +#define R_0xc84 0xc84 +#define R_0xc88 0xc88 +#define R_0xc8c 0xc8c +#define R_0xc90 0xc90 +#define R_0xc94 0xc94 +#define R_0xc9c 0xc9c +#define R_0xca0 0xca0 +#define R_0xca4 0xca4 +#define R_0xca8 0xca8 +#define R_0xcac 0xcac +#define R_0xcb0 0xcb0 +#define R_0xcb4 0xcb4 +#define R_0xcb8 0xcb8 +#define R_0xcbc 0xcbc +#define R_0xcbd 0xcbd +#define R_0xcbe 0xcbe +#define R_0xcc0 0xcc0 +#define R_0xcc4 0xcc4 +#define R_0xcc8 0xcc8 +#define R_0xccc 0xccc +#define R_0xcd0 0xcd0 +#define R_0xcd4 0xcd4 +#define R_0xcd8 0xcd8 +#define R_0xce0 0xce0 +#define R_0xce4 0xce4 +#define R_0xce8 0xce8 +#define R_0xd00 0xd00 +#define R_0xd04 0xd04 +#define R_0xd08 0xd08 +#define R_0xd0c 0xd0c +#define R_0xd10 0xd10 +#define R_0xd14 0xd14 +#define R_0xd2c 0xd2c +#define R_0xd30 0xd30 +#define R_0xd40 0xd40 +#define R_0xd44 0xd44 +#define R_0xd48 0xd48 +#define R_0xd4c 0xd4c +#define R_0xd50 0xd50 +#define R_0xd54 0xd54 +#define R_0xd5c 0xd5c +#define R_0xd6c 0xd6c +#define R_0xd7c 0xd7c +#define R_0xd80 0xd80 +#define R_0xd84 0xd84 +#define R_0xd8c 0xd8c +#define R_0xd90 0xd90 +#define R_0xd94 0xd94 +#define R_0xdac 0xdac +#define R_0xdb0 0xdb0 +#define R_0xdb4 0xdb4 +#define R_0xdb8 0xdb8 +#define R_0xdbc 0xdbc +#define R_0xdc 0xdc +#define R_0xdcc 0xdcc +#define R_0xdd0 0xdd0 +#define R_0xdd4 0xdd4 +#define R_0xdd8 0xdd8 +#define R_0xde0 0xde0 +#define R_0xdec 0xdec +#define R_0xdf4 0xdf4 +#define R_0xe00 0xe00 +#define R_0xe04 0xe04 +#define R_0xe08 0xe08 +#define R_0xe10 0xe10 +#define R_0xe14 0xe14 +#define R_0xe18 0xe18 +#define R_0xe1c 0xe1c +#define R_0xe20 0xe20 +#define R_0xe24 0xe24 +#define R_0xe28 0xe28 +#define R_0xe30 0xe30 +#define R_0xe34 0xe34 +#define R_0xe38 0xe38 +#define R_0xe3c 0xe3c +#define R_0xe40 0xe40 +#define R_0xe44 0xe44 +#define R_0xe48 0xe48 +#define R_0xe4c 0xe4c +#define R_0xe50 0xe50 +#define R_0xe54 0xe54 +#define R_0xe5c 0xe5c +#define R_0xe64 0xe64 +#define R_0xe6c 0xe6c +#define R_0xe70 0xe70 +#define R_0xe74 0xe74 +#define R_0xe78 0xe78 +#define R_0xe7c 0xe7c +#define R_0xe80 0xe80 +#define R_0xe84 0xe84 +#define R_0xe88 0xe88 +#define R_0xe8c 0xe8c +#define R_0xe90 0xe90 +#define R_0xe94 0xe94 +#define R_0xe98 0xe98 +#define R_0xe9c 0xe9c +#define R_0xea0 0xea0 +#define R_0xea4 0xea4 +#define R_0xea8 0xea8 +#define R_0xeac 0xeac +#define R_0xeb0 0xeb0 +#define R_0xeb4 0xeb4 +#define R_0xeb8 0xeb8 +#define R_0xebc 0xebc +#define R_0xec 0xec +#define R_0xec0 0xec0 +#define R_0xec4 0xec4 +#define R_0xec8 0xec8 +#define R_0xecc 0xecc +#define R_0xed0 0xed0 +#define R_0xed4 0xed4 +#define R_0xed8 0xed8 +#define R_0xedc 0xedc +#define R_0xee0 0xee0 +#define R_0xee8 0xee8 +#define R_0xeec 0xeec +#define R_0xf0 0xf0 +#define R_0xf00 0xf00 +#define R_0xf04 0xf04 +#define R_0xf08 0xf08 +#define R_0xf0c 0xf0c +#define R_0xf10 0xf10 +#define R_0xf14 0xf14 +#define R_0xf18 0xf18 +#define R_0xf1c 0xf1c +#define R_0xf20 0xf20 +#define R_0xf24 0xf24 +#define R_0xf2c 0xf2c +#define R_0xf30 0xf30 +#define R_0xf34 0xf34 +#define R_0xf4 0xf4 +#define R_0xf44 0xf44 +#define R_0xf48 0xf48 +#define R_0xf4c 0xf4c +#define R_0xf50 0xf50 +#define R_0xf54 0xf54 +#define R_0xf58 0xf58 +#define R_0xf5c 0xf5c +#define R_0xf70 0xf70 +#define R_0xf74 0xf74 +#define R_0xf80 0xf80 +#define R_0xf84 0xf84 +#define R_0xf87 0xf87 +#define R_0xf88 0xf88 +#define R_0xf8c 0xf8c +#define R_0xf90 0xf90 +#define R_0xf94 0xf94 +#define R_0xf98 0xf98 +#define R_0xf9c 0xf9c +#define R_0xfa0 0xfa0 +#define R_0xfa4 0xfa4 +#define R_0xfa8 0xfa8 +#define R_0xfac 0xfac +#define R_0xfb0 0xfb0 +#define R_0xfb4 0xfb4 +#define R_0xfb8 0xfb8 +#define R_0xfbc 0xfbc +#define R_0xfc0 0xfc0 +#define R_0xfc4 0xfc4 +#define R_0xfc8 0xfc8 +#define R_0xfcc 0xfcc +#define R_0xfd0 0xfd0 +#define R_0xff0 0xff0 +#define RF_0x0 0x0 +#define RF_0x00 0x00 +#define RF_0x08 0x08 +#define RF_0x09 0x09 +#define RF_0x0c 0x0c +#define RF_0x0d 0x0d +#define RF_0x1 0x1 +#define RF_0x18 0x18 +#define RF_0x19 0x19 +#define RF_0x1a 0x1a +#define RF_0x1bf0 0x1bf0 +#define RF_0x2 0x2 +#define RF_0x3 0x3 +#define RF_0x1e 0x1e +#define RF_0x1f 0x1f +#define RF_0x20 0x20 +#define RF_0x30 0x30 +#define RF_0x31 0x31 +#define RF_0x32 0x32 +#define RF_0x33 0x33 +#define RF_0x35 0x35 +#define RF_0x3e 0x3e +#define RF_0x3f 0x3f +#define RF_0x4 0x4 +#define RF_0x42 0x42 +#define RF_0x43 0x43 +#define RF_0x5 0x5 +#define RF_0x51 0x51 +#define RF_0x52 0x52 +#define RF_0x53 0x53 +#define RF_0x54 0x54 +#define RF_0x55 0x55 +#define RF_0x56 0x56 +#define RF_0x57 0x57 +#define RF_0x58 0x58 +#define RF_0x5c 0x5c +#define RF_0x5d 0x5d +#define RF_0x5e 0x5e +#define RF_0x60 0x60 +#define RF_0x61 0x61 +#define RF_0x63 0x63 +#define RF_0x64 0x64 +#define RF_0x65 0x65 +#define RF_0x66 0x66 +#define RF_0x67 0x67 +#define RF_0x6d 0x6d +#define RF_0x6e 0x6e +#define RF_0x6f 0x6f +#define RF_0x75 0x75 +#define RF_0x76 0x76 +#define RF_0x78 0x78 +#define RF_0x7c 0x7c +#define RF_0x7f 0x7f +#define RF_0x8 0x8 +#define RF_0x80 0x80 +#define RF_0x81 0x81 +#define RF_0x82 0x82 +#define RF_0x83 0x83 +#define RF_0x85 0x85 +#define RF_0x86 0x86 +#define RF_0x87 0x87 +#define RF_0x88 0x88 +#define RF_0x8a 0x8a +#define RF_0x8b 0x8b +#define RF_0x8c 0x8c +#define RF_0x8d 0x8d +#define RF_0x8f 0x8f +#define RF_0x92 0x92 +#define RF_0x93 0x93 +#define RF_0x9e 0x9e +#define RF_0x9f 0x9f +#define RF_0xa3 0xa3 +#define RF_0xa9 0xa9 +#define RF_0xae 0xae +#define RF_0xb0 0xb0 +#define RF_0xb3 0xb3 +#define RF_0xb4 0xb4 +#define RF_0xb8 0xb8 +#define RF_0xbc 0xbc +#define RF_0xbe 0xbe +#define RF_0xc4 0xc4 +#define RF_0xc8 0xc8 +#define RF_0xc9 0xc9 +#define RF_0xca 0xca +#define RF_0xcc 0xcc +#define RF_0xd 0xd +#define RF_0xdd 0xdd +#define RF_0xde 0xde +#define RF_0xdf 0xdf +#define RF_0xed 0xed +#define RF_0xee 0xee +#define RF_0xef 0xef +#define RF_0xf5 0xf5 +#define RF_0xf6 0xf6 diff --git a/hal/phydm/phydm_rssi_monitor.c b/hal/phydm/phydm_rssi_monitor.c new file mode 100644 index 0000000..1fde036 --- /dev/null +++ b/hal/phydm/phydm_rssi_monitor.c @@ -0,0 +1,189 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/*@************************************************************ + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef PHYDM_SUPPORT_RSSI_MONITOR + +void phydm_rssi_monitor_h2c(void *dm_void, u8 macid) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_t = &dm->dm_ra_table; + struct cmn_sta_info *sta = dm->phydm_sta_info[macid]; + struct ra_sta_info *ra = NULL; + #ifdef CONFIG_BEAMFORMING + struct bf_cmn_info *bf = NULL; + #endif + u8 h2c[H2C_MAX_LENGTH] = {0}; + u8 stbc_en, ldpc_en; + u8 bf_en = 0; + u8 is_rx, is_tx; + + if (is_sta_active(sta)) { + ra = &sta->ra_info; + } else { + PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s\n", __func__); + return; + } + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id); + + is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0; + is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0; + stbc_en = (sta->stbc_en) ? 1 : 0; + ldpc_en = (sta->ldpc_en) ? 1 : 0; + + #ifdef CONFIG_BEAMFORMING + bf = &sta->bf_info; + + if ((bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + (bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + bf_en = 1; + #endif + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst=(( %s%d ))\n", + ((ra_t->ra_ofst_direc) ? "+" : "-"), ra_t->ra_th_ofst); + + h2c[0] = sta->mac_id; + h2c[1] = 0; + h2c[2] = sta->rssi_stat.rssi; + h2c[3] = is_rx | (stbc_en << 1) | + ((dm->noisy_decision & 0x1) << 2) | (bf_en << 6); + h2c[4] = (ra_t->ra_th_ofst & 0x7f) | + ((ra_t->ra_ofst_direc & 0x1) << 7); + h2c[5] = 0; + h2c[6] = ((ra_t->ra_trigger_mode) << 2); + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n", + h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]); + + #if (RTL8188E_SUPPORT) + if (dm->support_ic_type == ODM_RTL8188E) + odm_ra_set_rssi_8188e(dm, sta->mac_id, sta->rssi_stat.rssi); + else + #endif + { + odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c); + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = NULL; + struct rssi_info *rssi_t = NULL; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + + sta = dm->phydm_sta_info[macid]; + rssi_t = &sta->rssi_stat; + + rssi_t->rssi_acc = (init_rssi << RSSI_MA); + rssi_t->rssi = init_rssi; +} +#endif +void phydm_calculate_rssi_min_max(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta; + s8 rssi_max_tmp = 0, rssi_min_tmp = 100; + u8 i; + u8 sta_cnt = 0; + + if (!dm->is_linked) + return; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + sta = dm->phydm_sta_info[i]; + if (is_sta_active(sta)) { + sta_cnt++; + + if (sta->rssi_stat.rssi < rssi_min_tmp) { + rssi_min_tmp = sta->rssi_stat.rssi; + dm->rssi_min_macid = i; + } + + if (sta->rssi_stat.rssi > rssi_max_tmp) { + rssi_max_tmp = sta->rssi_stat.rssi; + dm->rssi_max_macid = i; + } + + /*@[Send RSSI to FW]*/ + if (!sta->ra_info.disable_ra) + phydm_rssi_monitor_h2c(dm, i); + + if (sta_cnt == dm->number_linked_client) + break; + } + } + dm->pre_rssi_min = dm->rssi_min; + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (dm->number_linked_client == 0) + return; +#endif + dm->rssi_max = (u8)rssi_max_tmp; + dm->rssi_min = (u8)rssi_min_tmp; +} + +void phydm_rssi_monitor_check(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_RSSI_MONITOR)) + return; + + /*@for AP watchdog period = 1 sec*/ + if ((dm->phydm_sys_up_time % 2) == 1) + return; + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__); + + phydm_calculate_rssi_min_max(dm); + + PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n", + dm->rssi_max, dm->rssi_min); +} + +void phydm_rssi_monitor_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct ra_table *ra_tab = &dm->dm_ra_table; + + dm->pre_rssi_min = 0; + dm->rssi_max = 0; + dm->rssi_min = 0; +} + +#endif diff --git a/hal/phydm/phydm_rssi_monitor.h b/hal/phydm/phydm_rssi_monitor.h new file mode 100644 index 0000000..b0f446e --- /dev/null +++ b/hal/phydm/phydm_rssi_monitor.h @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDM_RSSI_MONITOR_H__ +#define __PHYDM_RSSI_MONITOR_H__ + +#define RSSI_MONITOR_VERSION "2.0" + +/* @1 ============================================================ + * 1 Definition + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 structure + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 enumeration + * 1 ============================================================ + */ + +/* @1 ============================================================ + * 1 function prototype + * 1 ============================================================ + */ + +void phydm_rssi_monitor_check(void *dm_void); + +void phydm_rssi_monitor_init(void *dm_void); +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi); +#endif + +#endif diff --git a/hal/phydm/phydm_smt_ant.c b/hal/phydm/phydm_smt_ant.c new file mode 100644 index 0000000..8e805b3 --- /dev/null +++ b/hal/phydm/phydm_smt_ant.c @@ -0,0 +1,2277 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/******************************************************* + * when antenna test utility is on or some testing need to disable antenna diversity + * call this function to disable all ODM related mechanisms which will switch antenna. + ******************************************************/ +#if (defined(CONFIG_SMART_ANTENNA)) + +#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT +#if (RTL8198F_SUPPORT == 1) +void phydm_smt_ant_init_98f(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 val = 0; + + #if 0 + odm_set_bb_reg(dm, R_0x1da4, 0x3c, 4); /*6.25*4 = 25ms*/ + odm_set_bb_reg(dm, R_0x1da4, BIT(6), 1); + odm_set_bb_reg(dm, R_0x1da4, BIT(7), 1); + #endif +} +#endif +#endif + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +void phydm_cumitek_smt_ant_mapping_table_8822b( + void *dm_void, + u8 *table_path_a, + u8 *table_path_b) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 path_a_0to3_idx = 0; + u32 path_b_0to3_idx = 0; + u32 path_a_4to7_idx = 0; + u32 path_b_4to7_idx = 0; + + path_a_0to3_idx = ((table_path_a[3] & 0xf) << 24) | ((table_path_a[2] & 0xf) << 16) | ((table_path_a[1] & 0xf) << 8) | (table_path_a[0] & 0xf); + + path_b_0to3_idx = ((table_path_b[3] & 0xf) << 28) | ((table_path_b[2] & 0xf) << 20) | ((table_path_b[1] & 0xf) << 12) | ((table_path_b[0] & 0xf) << 4); + + path_a_4to7_idx = ((table_path_a[7] & 0xf) << 24) | ((table_path_a[6] & 0xf) << 16) | ((table_path_a[5] & 0xf) << 8) | (table_path_a[4] & 0xf); + + path_b_4to7_idx = ((table_path_b[7] & 0xf) << 28) | ((table_path_b[6] & 0xf) << 20) | ((table_path_b[5] & 0xf) << 12) | ((table_path_b[4] & 0xf) << 4); + +#if 0 + /*PHYDM_DBG(dm, DBG_SMT_ANT, "mapping table{A, B} = {0x%x, 0x%x}\n", path_a_0to3_idx, path_b_0to3_idx);*/ +#endif + + /*pathA*/ + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, path_a_0to3_idx); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xca8, MASKDWORD, path_a_4to7_idx); /*@ant map 2*/ + + /*pathB*/ + odm_set_bb_reg(dm, R_0xea4, MASKDWORD, path_b_0to3_idx); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xea8, MASKDWORD, path_b_4to7_idx); /*@ant map 2*/ +} + +void phydm_cumitek_smt_ant_init_8822b( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + + PHYDM_DBG(dm, DBG_SMT_ANT, "[8822B Cumitek SmtAnt Int]\n"); + + /*@========= MAC GPIO setting =================================*/ + + /* Pin, pin_name, RFE_CTRL_NUM*/ + + /* @A0, 55, 5G_TRSW, 3*/ + /* @A1, 52, 5G_TRSW, 0*/ + /* @A2, 25, 5G_TRSW, 8*/ + + /* @B0, 16, 5G_TRSW, 4*/ + /* @B1, 13, 5G_TRSW, 11*/ + /* @B2, 24, 5G_TRSW, 9*/ + + /*@for RFE_CTRL 8 & 9*/ + odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2); + odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0); + + /*@for RFE_CTRL 0*/ + odm_set_mac_reg(dm, R_0x4c, BIT(25), 0); + odm_set_mac_reg(dm, R_0x64, BIT(29), 1); + + /*@for RFE_CTRL 2 & 3*/ + odm_set_mac_reg(dm, R_0x4c, BIT(26), 0); + odm_set_mac_reg(dm, R_0x64, BIT(28), 1); + + /*@for RFE_CTRL 11*/ + odm_set_mac_reg(dm, R_0x40, BIT(3), 1); + + /*@0x604[25]=1 : 2bit mode for pathA&B&C&D*/ + /*@0x604[25]=0 : 3bit mode for pathA&B*/ + smtant_table->tx_desc_mode = 0; + odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode); + + /*@========= BB RFE setting =================================*/ +#if 0 + /*path A*/ + odm_set_bb_reg(dm, R_0x1990, BIT(3), 0); /*RFE_CTRL_3*/ /*A_0*/ + odm_set_bb_reg(dm, R_0xcbc, BIT(3), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xcb0, 0xf000, 8); + + odm_set_bb_reg(dm, R_0x1990, BIT(0), 0); /*RFE_CTRL_0*/ /*A_1*/ + odm_set_bb_reg(dm, R_0xcbc, BIT(0), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xcb0, 0xf, 0x9); + + odm_set_bb_reg(dm, R_0x1990, BIT(8), 0); /*RFE_CTRL_8*/ /*A_2*/ + odm_set_bb_reg(dm, R_0xcbc, BIT(8), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xcb4, 0xf, 0xa); + + + /*path B*/ + odm_set_bb_reg(dm, R_0x1990, BIT(4), 1); /*RFE_CTRL_4*/ /*B_0*/ + odm_set_bb_reg(dm, R_0xdbc, BIT(4), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xdb0, 0xf0000, 0xb); + + odm_set_bb_reg(dm, R_0x1990, BIT(11), 1); /*RFE_CTRL_11*/ /*B_1*/ + odm_set_bb_reg(dm, R_0xdbc, BIT(11), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xdb4, 0xf000, 0xc); + + odm_set_bb_reg(dm, R_0x1990, BIT(9), 1); /*RFE_CTRL_9*/ /*B_2*/ + odm_set_bb_reg(dm, R_0xdbc, BIT(9), 0); /*@inv*/ + odm_set_bb_reg(dm, R_0xdb4, 0xf0, 0xd); +#endif + /*@========= BB SmtAnt setting =================================*/ + odm_set_mac_reg(dm, R_0x6d8, BIT(22) | BIT(21), 2); /*resp tx by register*/ + odm_set_mac_reg(dm, R_0x668, BIT(3), 1); + odm_set_bb_reg(dm, R_0x804, BIT(4), 0); /*@lathch antsel*/ + odm_set_bb_reg(dm, R_0x818, 0xf00000, 0); /*@keep tx by rx*/ + odm_set_bb_reg(dm, R_0x900, BIT(19), 0); /*@fast train*/ + odm_set_bb_reg(dm, R_0x900, BIT(18), 1); /*@1: by TXDESC*/ + + /*pathA*/ + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x03020100); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x07060504); /*@ant map 2*/ + odm_set_bb_reg(dm, R_0xcac, BIT(9), 0); /*@keep antsel map by GNT_BT*/ + + /*pathB*/ + odm_set_bb_reg(dm, R_0xea4, MASKDWORD, 0x30201000); /*@ant map 1*/ + odm_set_bb_reg(dm, R_0xea8, MASKDWORD, 0x70605040); /*@ant map 2*/ + odm_set_bb_reg(dm, R_0xeac, BIT(9), 0); /*@keep antsel map by GNT_BT*/ +} + +void phydm_cumitek_smt_ant_init_8197f( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + + PHYDM_DBG(dm, DBG_SMT_ANT, "[8197F Cumitek SmtAnt Int]\n"); + + /*@GPIO setting*/ +} + +void phydm_cumitek_smt_ant_init_8192f( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 value32; + PHYDM_DBG(dm, DBG_SMT_ANT, "[8192F Cumitek SmtAnt Int]\n"); + + /*@GPIO setting*/ +} + +void phydm_cumitek_smt_tx_ant_update( + void *dm_void, + u8 tx_ant_idx_path_a, + u8 tx_ant_idx_path_b, + u32 mac_id) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Cumitek] Set TX-ANT[%d] = (( A:0x%x , B:0x%x ))\n", mac_id, + tx_ant_idx_path_a, tx_ant_idx_path_b); + + /*path-A*/ + cumi_smtant_table->tx_ant_idx[0][mac_id] = tx_ant_idx_path_a; /*@fill this value into TXDESC*/ + + /*path-B*/ + cumi_smtant_table->tx_ant_idx[1][mac_id] = tx_ant_idx_path_b; /*@fill this value into TXDESC*/ +} + +void phydm_cumitek_smt_rx_default_ant_update( + void *dm_void, + u8 rx_ant_idx_path_a, + u8 rx_ant_idx_path_b) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Cumitek] Set RX-ANT = (( A:0x%x, B:0x%x ))\n", + rx_ant_idx_path_a, rx_ant_idx_path_b); + + /*path-A*/ + if (cumi_smtant_table->rx_default_ant_idx[0] != rx_ant_idx_path_a) { + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + odm_set_bb_reg(dm, R_0xc08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_a); /*@default RX antenna*/ + odm_set_mac_reg(dm, R_0x6d8, BIT(2) | BIT(1) | BIT(0), rx_ant_idx_path_a); /*@default response TX antenna*/ + } + #endif + + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + } + #endif + + /*@jj add 20170822*/ + #if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + } + #endif + cumi_smtant_table->rx_default_ant_idx[0] = rx_ant_idx_path_a; + } + + /*path-B*/ + if (cumi_smtant_table->rx_default_ant_idx[1] != rx_ant_idx_path_b) { + #if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) { + odm_set_bb_reg(dm, R_0xe08, BIT(21) | BIT(20) | BIT(19), rx_ant_idx_path_b); /*@default antenna*/ + odm_set_mac_reg(dm, R_0x6d8, BIT(5) | BIT(4) | BIT(3), rx_ant_idx_path_b); /*@default response TX antenna*/ + } + #endif + + #if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) { + } + #endif + + /*@jj add 20170822*/ + #if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) { + } + #endif + cumi_smtant_table->rx_default_ant_idx[1] = rx_ant_idx_path_b; + } +} + +void phydm_cumitek_smt_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + struct smt_ant_cumitek *cumi_smtant_table = &dm->smtant_table.cumi_smtant_table; + u32 used = *_used; + u32 out_len = *_out_len; + char help[] = "-h"; + u32 dm_value[10] = {0}; + u8 i; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "{1} {PathA rx_ant_idx} {pathB rx_ant_idx}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{2} {PathA tx_ant_idx} {pathB tx_ant_idx} {macid}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{3} {PathA mapping table} {PathB mapping table}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + "{4} {txdesc_mode 0:3bit, 1:2bit}\n"); + + } else if (dm_value[0] == 1) { /*@fix rx_idle pattern*/ + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); + + phydm_cumitek_smt_rx_default_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "RX Ant{A, B}={%d, %d}\n", dm_value[1], dm_value[2]); + + } else if (dm_value[0] == 2) { /*@fix tx pattern*/ + + for (i = 1; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "STA[%d] TX Ant{A, B}={%d, %d}\n", dm_value[3], + dm_value[1], dm_value[2]); + phydm_cumitek_smt_tx_ant_update(dm, (u8)dm_value[1], (u8)dm_value[2], (u8)dm_value[3]); + + } else if (dm_value[0] == 3) { + u8 table_path_a[8] = {0}; + u8 table_path_b[8] = {0}; + + for (i = 1; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Set Path-AB mapping table={%d, %d}\n", dm_value[1], + dm_value[2]); + + for (i = 0; i < 8; i++) { + table_path_a[i] = (u8)((dm_value[1] >> (4 * i)) & 0xf); + table_path_b[i] = (u8)((dm_value[2] >> (4 * i)) & 0xf); + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "Ant_Table_A[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n", + table_path_a[7], table_path_a[6], table_path_a[5], + table_path_a[4], table_path_a[3], table_path_a[2], + table_path_a[1], table_path_a[0]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "Ant_Table_B[7:0]={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x}\n", + table_path_b[7], table_path_b[6], table_path_b[5], + table_path_b[4], table_path_b[3], table_path_b[2], + table_path_b[1], table_path_b[0]); + + phydm_cumitek_smt_ant_mapping_table_8822b(dm, &table_path_a[0], &table_path_b[0]); + + } else if (dm_value[0] == 4) { + smtant_table->tx_desc_mode = (u8)dm_value[1]; + odm_set_mac_reg(dm, R_0x604, BIT(25), (u32)smtant_table->tx_desc_mode); + } + *_used = used; + *_out_len = out_len; +} + +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + +#if (RTL8822B_SUPPORT == 1) +void phydm_hl_smart_ant_type2_init_8822b( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u8 j; + u8 rfu_codeword_table_init_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { + {1, 1}, /*@0*/ + {1, 2}, + {2, 1}, + {2, 2}, + {4, 0}, + {5, 0}, + {6, 0}, + {7, 0}, + {8, 0}, /*@8*/ + {9, 0}, + {0xa, 0}, + {0xb, 0}, + {0xc, 0}, + {0xd, 0}, + {0xe, 0}, + {0xf, 0}}; + u8 rfu_codeword_table_init_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B] = { +#if 1 + {9, 1}, /*@0*/ + {9, 9}, + {1, 9}, + {9, 6}, + {2, 1}, + {2, 9}, + {9, 2}, + {2, 2}, /*@8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6}, + {1, 1} +#else + {1, 1}, /*@0*/ + {9, 1}, + {9, 9}, + {1, 9}, + {1, 2}, + {9, 2}, + {9, 6}, + {1, 6}, + {2, 1}, /*@8*/ + {6, 1}, + {6, 9}, + {2, 9}, + {2, 2}, + {6, 2}, + {6, 6}, + {2, 6} +#endif + }; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***RTK 8822B SmartAnt_Init: Hong-Bo SmrtAnt Type2]\n"); + + /* @---------------------------------------- */ + /* @GPIO 0-1 for Beam control */ + /* reg0x66[2:0]=0 */ + /* reg0x44[25:24] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* @------------------------------------------ */ + + odm_move_memory(dm, sat_tab->rfu_codeword_table_2g, rfu_codeword_table_init_2g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + odm_move_memory(dm, sat_tab->rfu_codeword_table_5g, rfu_codeword_table_init_5g, (SUPPORT_BEAM_SET_PATTERN_NUM * MAX_PATH_NUM_8822B)); + + /*@GPIO setting*/ + odm_set_mac_reg(dm, R_0x64, (BIT(18) | BIT(17) | BIT(16)), 0); + odm_set_mac_reg(dm, R_0x44, BIT(25) | BIT(24), 0); /*@config P_GPIO[3:2] to data port*/ + odm_set_mac_reg(dm, R_0x44, BIT(17) | BIT(16), 0x3); /*@enable_output for P_GPIO[3:2]*/ +#if 0 + /*odm_set_mac_reg(dm, R_0x44, BIT(9)|BIT(8), 0);*/ /*P_GPIO[3:2] output value*/ +#endif + odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/ + + /*@Hong_lin smart antenna HW setting*/ + sat_tab->rfu_protocol_type = 2; + sat_tab->rfu_protocol_delay_time = 45; + + sat_tab->rfu_codeword_total_bit_num = 16; /*@max=32bit*/ + sat_tab->rfu_each_ant_bit_num = 4; + + sat_tab->total_beam_set_num = 4; + sat_tab->total_beam_set_num_2g = 4; + sat_tab->total_beam_set_num_5g = 8; + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_SDIO) + sat_tab->latch_time = 100; /*@mu sec*/ +#endif +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (dm->support_interface == ODM_ITRF_USB) + sat_tab->latch_time = 100; /*@mu sec*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; + + sat_tab->ant_num = 2; + sat_tab->ant_num_total = MAX_PATH_NUM_8822B; + sat_tab->first_train_ant = MAIN_ANT; + + sat_tab->fix_beam_pattern_en = 0; + sat_tab->decision_holding_period = 0; + + /*@beam training setting*/ + sat_tab->pkt_counter = 0; + sat_tab->per_beam_training_pkt_num = 10; + + /*set default beam*/ + sat_tab->fast_training_beam_num = 0; + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + + for (j = 0; j < SUPPORT_BEAM_SET_PATTERN_NUM; j++) { + sat_tab->beam_set_avg_rssi_pre[j] = 0; + sat_tab->beam_set_train_val_diff[j] = 0; + sat_tab->beam_set_train_cnt[j] = 0; + } + phydm_set_rfu_beam_pattern_type2(dm); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; +} +#endif + +u32 phydm_construct_hb_rfu_codeword_type2( + void *dm_void, + u32 beam_set_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 sync_codeword = 0x7f; + u32 codeword = 0; + u32 data_tmp = 0; + u32 i; + + for (i = 0; i < sat_tab->ant_num_total; i++) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[beam_set_idx][i]; + else + data_tmp = sat_tab->rfu_codeword_table_2g[beam_set_idx][i]; + + codeword |= (data_tmp << (i * sat_tab->rfu_each_ant_bit_num)); + } + + codeword = (codeword << 8) | sync_codeword; + + return codeword; +} + +void phydm_update_beam_pattern_type2( + void *dm_void, + u32 codeword, + u32 codeword_length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Set codeword = ((0x%x))\n", codeword); + + reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/ +#endif + + /*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + #if 1 + if (dm->debug_components & DBG_ANT_DIV) { + if (i == (codeword_length - 1)) + pr_debug("%d ]\n", beam_ctrl_signal); + else if (i == 0) + pr_debug("Start sending codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + pr_debug("%d | ", beam_ctrl_signal); + else + pr_debug("%d ", beam_ctrl_signal); + } + #endif + + if (dm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + if (sat_tab->rfu_protocol_type == 2) { + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/ + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(sat_tab->rfu_protocol_delay_time); +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/ +#endif + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif + } +} + +void phydm_update_rx_idle_beam_type2( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 i; + + sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->rx_idle_beam_set_idx); + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-Beam ] BeamSet idx = ((%d))\n", + sat_tab->rx_idle_beam_set_idx); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#endif +#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif +#endif + + sat_tab->pre_codeword = sat_tab->update_beam_codeword; +} + +void phydm_hl_smt_ant_dbg_type2( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = sat_tab->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + char help[] = "-h"; + u32 dm_value[10] = {0}; + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &dm_value[0]); + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &dm_value[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &dm_value[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &dm_value[4]); + + if (strcmp(input[1], help) == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + " 1 {fix_en} {codeword(Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 3 {Fix_training_num_en} {Per_beam_training_pkt_num} {Decision_holding_period}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 5 {0:show, 1:2G, 2:5G} {beam_num} {idxA(Hex)} {idxB(Hex)}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 7 {0:show, 1:2G, 2:5G} {total_beam_set_num}\n"); + PDM_SNPF(out_len, used, output + used, out_len - used, + " 8 {0:show, 1:set} {RFU delay time(us)}\n"); + + } else if (dm_value[0] == 1) { /*@fix beam pattern*/ + + sat_tab->fix_beam_pattern_en = dm_value[1]; + + if (sat_tab->fix_beam_pattern_en == 1) { + PHYDM_SSCANF(input[3], DCMD_HEX, &dm_value[2]); + sat_tab->fix_beam_pattern_codeword = dm_value[2]; + + if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", + sat_tab->fix_beam_pattern_codeword, + codeword_length); + + (sat_tab->fix_beam_pattern_codeword) &= 0xffffff; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Auto modify to (0x%x)\n", + sat_tab->fix_beam_pattern_codeword); + } + + sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword; + + /*@---------------------------------------------------------*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "Fix Beam Pattern\n"); + + /*@devide_num = (sat_tab->rfu_protocol_type == 2) ? 8 : 4;*/ + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "%d]\n", + beam_ctrl_signal); + else if (i == 0) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "Send Codeword[1:%d] to RFU -> [%d", + sat_tab->rfu_codeword_total_bit_num, + beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d|", + beam_ctrl_signal); + else + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d", + beam_ctrl_signal); + } +/*@---------------------------------------------------------*/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#endif +#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif +#endif + } else if (sat_tab->fix_beam_pattern_en == 0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Smart Antenna: Enable\n"); + + } else if (dm_value[0] == 2) { /*set latch time*/ + + sat_tab->latch_time = dm_value[1]; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] latch_time =0x%x\n", + sat_tab->latch_time); + } else if (dm_value[0] == 3) { + sat_tab->fix_training_num_en = dm_value[1]; + + if (sat_tab->fix_training_num_en == 1) { + sat_tab->per_beam_training_pkt_num = (u8)dm_value[2]; + sat_tab->decision_holding_period = (u8)dm_value[3]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + } else if (sat_tab->fix_training_num_en == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] AUTO per_beam_training_pkt_num\n"); + } + } else if (dm_value[0] == 4) { + #if 0 + if (dm_value[1] == 1) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + sat_tab->ant_num = 2; + sat_tab->first_train_ant = MAIN_ANT; + } + + PDM_SNPF((output + used, out_len - used, + "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + sat_tab->ant_num, (sat_tab->first_train_ant - 1))); + #endif + } else if (dm_value[0] == 5) { /*set beam set table*/ + + PHYDM_SSCANF(input[4], DCMD_HEX, &dm_value[3]); + PHYDM_SSCANF(input[5], DCMD_HEX, &dm_value[4]); + + if (dm_value[1] == 1) { /*@2G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_2g[dm_value[2]][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_2g[dm_value[2]][1] = (u8)dm_value[4]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Set 2G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], dm_value[4]); + } + + } else if (dm_value[1] == 2) { /*@5G*/ + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_5g[dm_value[2]][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_5g[dm_value[2]][1] = (u8)dm_value[4]; + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], dm_value[4]); + } + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] 2G Beam Table==============>\n"); + for (i = 0; i < sat_tab->total_beam_set_num_2g; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "2G Table[%d] = [A:0x%x, B:0x%x]\n", i, + sat_tab->rfu_codeword_table_2g[i][0], + sat_tab->rfu_codeword_table_2g[i][1]); + } + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] 5G Beam Table==============>\n"); + for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "5G Table[%d] = [A:0x%x, B:0x%x]\n", i, + sat_tab->rfu_codeword_table_5g[i][0], + sat_tab->rfu_codeword_table_5g[i][1]); + } + } + + } else if (dm_value[0] == 6) { +#if 0 + if (dm_value[1] == 0) { + if (dm_value[2] < SUPPORT_BEAM_SET_PATTERN_NUM) { + sat_tab->rfu_codeword_table_5g[dm_value[2] ][0] = (u8)dm_value[3]; + sat_tab->rfu_codeword_table_5g[dm_value[2] ][1] = (u8)dm_value[4]; + PDM_SNPF((output + used, out_len - used, + "[SmtAnt] Set5G Table[%d] = [A:0x%x, B:0x%x]\n", + dm_value[2], dm_value[3], + dm_value[4])); + } + } else { + for (i = 0; i < sat_tab->total_beam_set_num_5g; i++) { + PDM_SNPF((output + used, out_len - used, + "[SmtAnt] Read 5G Table[%d] = [A:0x%x, B:0x%x]\n", + i, + sat_tab->rfu_codeword_table_5g[i][0], + sat_tab->rfu_codeword_table_5g[i][1])); + } + } +#endif + } else if (dm_value[0] == 7) { + if (dm_value[1] == 1) { + sat_tab->total_beam_set_num_2g = (u8)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] total_beam_set_num_2g = ((%d))\n", + sat_tab->total_beam_set_num_2g); + + } else if (dm_value[1] == 2) { + sat_tab->total_beam_set_num_5g = (u8)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] total_beam_set_num_5g = ((%d))\n", + sat_tab->total_beam_set_num_5g); + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Show total_beam_set_num{2g,5g} = {%d,%d}\n", + sat_tab->total_beam_set_num_2g, + sat_tab->total_beam_set_num_5g); + } + + } else if (dm_value[0] == 8) { + if (dm_value[1] == 1) { + sat_tab->rfu_protocol_delay_time = (u16)(dm_value[2]); + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] Set rfu_protocol_delay_time = ((%d))\n", + sat_tab->rfu_protocol_delay_time); + } else if (dm_value[1] == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmtAnt] Read rfu_protocol_delay_time = ((%d))\n", + sat_tab->rfu_protocol_delay_time); + } + } + + *_used = used; + *_out_len = out_len; +} + +void phydm_set_rfu_beam_pattern_type2( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + + if (dm->ant_div_type != HL_SW_SMART_ANT_TYPE2) + return; + + PHYDM_DBG(dm, DBG_ANT_DIV, "Training beam_set index = (( 0x%x ))\n", + sat_tab->fast_training_beam_num); + sat_tab->update_beam_codeword = phydm_construct_hb_rfu_codeword_type2(dm, sat_tab->fast_training_beam_num); + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + #endif + #if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif + #endif +} + +void phydm_fast_ant_training_hl_smart_antenna_type2( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 codeword = 0; + u8 i = 0, j = 0; + u8 avg_rssi_tmp; + u8 avg_rssi_tmp_ma; + u8 max_beam_ant_rssi = 0; + u8 rssi_target_beam = 0, target_beam_max_rssi = 0; + u8 evm1ss_target_beam = 0, evm2ss_target_beam = 0; + u32 target_beam_max_evm1ss = 0, target_beam_max_evm2ss = 0; + u32 beam_tmp; + u8 per_beam_val_diff_tmp = 0, training_pkt_num_offset; + u32 avg_evm2ss[2] = {0}, avg_evm2ss_sum = 0; + u32 avg_evm1ss = 0; + u32 beam_path_evm_2ss_cnt_all = 0; /*sum of all 2SS-pattern cnt*/ + u32 beam_path_evm_1ss_cnt_all = 0; /*sum of all 1SS-pattern cnt*/ + u8 decision_type; + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + sat_tab->decision_holding_period = 0; + PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n"); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + fat_tab->is_become_linked = dm->is_linked; + } + return; + + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + + fat_tab->fat_state = FAT_PREPARE_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + + /*sat_tab->fast_training_beam_num = 0;*/ + /*phydm_set_rfu_beam_pattern_type2(dm);*/ + + fat_tab->is_become_linked = dm->is_linked; + } + } + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/ +#endif + + /* @[DECISION STATE] */ + /*@=======================================================================================*/ + if (fat_tab->fat_state == FAT_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n"); + + /*@compute target beam in each antenna*/ + + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + /*@[Decision1: RSSI]-------------------------------------------------------------------*/ + if (sat_tab->statistic_pkt_cnt[j] == 0) { /*@if new RSSI = 0 -> MA_RSSI-=2*/ + avg_rssi_tmp = sat_tab->beam_set_avg_rssi_pre[j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (u8)((sat_tab->beam_set_rssi_avg_sum[j]) / (sat_tab->statistic_pkt_cnt[j])); + avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->beam_set_avg_rssi_pre[j]) >> 1; + } + + sat_tab->beam_set_avg_rssi_pre[j] = avg_rssi_tmp; + + if (avg_rssi_tmp > target_beam_max_rssi) { + rssi_target_beam = j; + target_beam_max_rssi = avg_rssi_tmp; + } + + /*@[Decision2: EVM 2ss]-------------------------------------------------------------------*/ + if (sat_tab->beam_path_evm_2ss_cnt[j] != 0) { + avg_evm2ss[0] = sat_tab->beam_path_evm_2ss_sum[j][0] / sat_tab->beam_path_evm_2ss_cnt[j]; + avg_evm2ss[1] = sat_tab->beam_path_evm_2ss_sum[j][1] / sat_tab->beam_path_evm_2ss_cnt[j]; + avg_evm2ss_sum = avg_evm2ss[0] + avg_evm2ss[1]; + beam_path_evm_2ss_cnt_all += sat_tab->beam_path_evm_2ss_cnt[j]; + + sat_tab->beam_set_avg_evm_2ss_pre[j] = (u8)avg_evm2ss_sum; + } + + if (avg_evm2ss_sum > target_beam_max_evm2ss) { + evm2ss_target_beam = j; + target_beam_max_evm2ss = avg_evm2ss_sum; + } + + /*@[Decision3: EVM 1ss]-------------------------------------------------------------------*/ + if (sat_tab->beam_path_evm_1ss_cnt[j] != 0) { + avg_evm1ss = sat_tab->beam_path_evm_1ss_sum[j] / sat_tab->beam_path_evm_1ss_cnt[j]; + beam_path_evm_1ss_cnt_all += sat_tab->beam_path_evm_1ss_cnt[j]; + + sat_tab->beam_set_avg_evm_1ss_pre[j] = (u8)avg_evm1ss; + } + + if (avg_evm1ss > target_beam_max_evm1ss) { + evm1ss_target_beam = j; + target_beam_max_evm1ss = avg_evm1ss; + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Beam[%d] Pkt_cnt=(( %d )), avg{MA,rssi}={%d, %d}, EVM1={%d}, EVM2={%d, %d, %d}\n", + j, sat_tab->statistic_pkt_cnt[j], + avg_rssi_tmp_ma, avg_rssi_tmp, avg_evm1ss, + avg_evm2ss[0], avg_evm2ss[1], avg_evm2ss_sum); + + /*reset counter value*/ + sat_tab->beam_set_rssi_avg_sum[j] = 0; + sat_tab->beam_path_rssi_sum[j][0] = 0; + sat_tab->beam_path_rssi_sum[j][1] = 0; + sat_tab->statistic_pkt_cnt[j] = 0; + + sat_tab->beam_path_evm_2ss_sum[j][0] = 0; + sat_tab->beam_path_evm_2ss_sum[j][1] = 0; + sat_tab->beam_path_evm_2ss_cnt[j] = 0; + + sat_tab->beam_path_evm_1ss_sum[j] = 0; + sat_tab->beam_path_evm_1ss_cnt[j] = 0; + } + + /*@[Joint Decision]-------------------------------------------------------------------*/ + PHYDM_DBG(dm, DBG_ANT_DIV, + "--->1.[RSSI] Target Beam(( %d )) RSSI_max=((%d))\n", + rssi_target_beam, target_beam_max_rssi); + PHYDM_DBG(dm, DBG_ANT_DIV, + "--->2.[Evm2SS] Target Beam(( %d )) EVM2SS_max=((%d))\n", + evm2ss_target_beam, target_beam_max_evm2ss); + PHYDM_DBG(dm, DBG_ANT_DIV, + "--->3.[Evm1SS] Target Beam(( %d )) EVM1SS_max=((%d))\n", + evm1ss_target_beam, target_beam_max_evm1ss); + + if (target_beam_max_rssi <= 10) { + sat_tab->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; + } else { + if (beam_path_evm_2ss_cnt_all != 0) { + sat_tab->rx_idle_beam_set_idx = evm2ss_target_beam; + decision_type = 2; + } else if (beam_path_evm_1ss_cnt_all != 0) { + sat_tab->rx_idle_beam_set_idx = evm1ss_target_beam; + decision_type = 3; + } else { + sat_tab->rx_idle_beam_set_idx = rssi_target_beam; + decision_type = 1; + } + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "---> Decision_type=((%d)), Final Target Beam(( %d ))\n", + decision_type, sat_tab->rx_idle_beam_set_idx); + + /*@Calculate packet counter offset*/ + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + if (decision_type == 1) { + per_beam_val_diff_tmp = target_beam_max_rssi - sat_tab->beam_set_avg_rssi_pre[j]; + + } else if (decision_type == 2) { + per_beam_val_diff_tmp = ((u8)target_beam_max_evm2ss - sat_tab->beam_set_avg_evm_2ss_pre[j]) >> 1; + } else if (decision_type == 3) { + per_beam_val_diff_tmp = (u8)target_beam_max_evm1ss - sat_tab->beam_set_avg_evm_1ss_pre[j]; + } + sat_tab->beam_set_train_val_diff[j] = per_beam_val_diff_tmp; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Beam_Set[%d]: diff= ((%d))\n", j, + per_beam_val_diff_tmp); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam_type2(dm); + fat_tab->fat_state = FAT_PREPARE_STATE; + } + /* @[TRAINING STATE] */ + else if (fat_tab->fat_state == FAT_TRAINING_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "curr_beam_idx = (( %d )), pre_beam_idx = (( %d ))\n", + sat_tab->fast_training_beam_num, + sat_tab->pre_fast_training_beam_num); + + if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num) + + sat_tab->force_update_beam_en = 0; + + else { + sat_tab->force_update_beam_en = 1; + + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", + sat_tab->fast_training_beam_num); + fat_tab->fat_state = FAT_DECISION_STATE; + phydm_fast_ant_training_hl_smart_antenna_type2(dm); + + } else { + sat_tab->fast_training_beam_num++; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, + sat_tab->fast_training_beam_num); + phydm_set_rfu_beam_pattern_type2(dm); + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + PHYDM_DBG(dm, DBG_ANT_DIV, "Update Pre_Beam =(( %d ))\n", + sat_tab->pre_fast_training_beam_num); + } + /* @[Prepare state] */ + /*@=======================================================================================*/ + else if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n"); + + if (dm->pre_traffic_load == dm->traffic_load) { + if (sat_tab->decision_holding_period != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Holding_period = (( %d )), return!!!\n", + sat_tab->decision_holding_period); + sat_tab->decision_holding_period--; + return; + } + } + + /* Set training packet number*/ + if (sat_tab->fix_training_num_en == 0) { + switch (dm->traffic_load) { + case TRAFFIC_HIGH: + sat_tab->per_beam_training_pkt_num = 8; + sat_tab->decision_holding_period = 2; + break; + case TRAFFIC_MID: + sat_tab->per_beam_training_pkt_num = 6; + sat_tab->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/ + sat_tab->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + sat_tab->per_beam_training_pkt_num = 1; + sat_tab->decision_holding_period = 6; + break; + default: + break; + } + } + + PHYDM_DBG(dm, DBG_ANT_DIV, + "TrafficLoad = (( %d )), Fix_beam = (( %d )), per_beam_training_pkt_num = (( %d )), decision_holding_period = ((%d))\n", + dm->traffic_load, sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + /*@Beam_set number*/ + if (*dm->band_type == ODM_BAND_5G) { + sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_5g; + PHYDM_DBG(dm, DBG_ANT_DIV, "5G beam_set num = ((%d))\n", + sat_tab->total_beam_set_num); + } else { + sat_tab->total_beam_set_num = sat_tab->total_beam_set_num_2g; + PHYDM_DBG(dm, DBG_ANT_DIV, "2G beam_set num = ((%d))\n", + sat_tab->total_beam_set_num); + } + + for (j = 0; j < (sat_tab->total_beam_set_num); j++) { + training_pkt_num_offset = sat_tab->beam_set_train_val_diff[j]; + + if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset) + sat_tab->beam_set_train_cnt[j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset; + else + sat_tab->beam_set_train_cnt[j] = 1; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Beam_Set[ %d ] training_pkt_offset = ((%d)), training_pkt_num = ((%d))\n", + j, sat_tab->beam_set_train_val_diff[j], + sat_tab->beam_set_train_cnt[j]); + } + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->update_beam_idx = 0; + sat_tab->pkt_counter = 0; + + sat_tab->fast_training_beam_num = 0; + phydm_set_rfu_beam_pattern_type2(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + fat_tab->fat_state = FAT_TRAINING_STATE; + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void phydm_beam_switch_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + sat_tab->pkt_skip_statistic_en = 1; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", + sat_tab->pkt_skip_statistic_en); + + phydm_update_beam_pattern_type2(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE +#if 0 + /*odm_stall_execution(sat_tab->latch_time);*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", + sat_tab->pkt_skip_statistic_en, sat_tab->latch_time); +} + +void phydm_beam_decision_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam decision Workitem Callback\n"); + phydm_fast_ant_training_hl_smart_antenna_type2(dm); +} +#endif + +void phydm_process_rssi_for_hb_smtant_type2( + void *dm_void, + void *phy_info_void, + void *pkt_info_void, + u8 rssi_avg) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void; + struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 train_pkt_number; + u32 beam_tmp; + u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0]; + u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1]; + u8 rx_evm_ant0 = phy_info->rx_mimo_evm_dbm[0]; + u8 rx_evm_ant1 = phy_info->rx_mimo_evm_dbm[1]; + + /*@[Beacon]*/ + if (pktinfo->is_packet_beacon) { + sat_tab->beacon_counter++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "MatchBSSID_beacon_counter = ((%d))\n", + sat_tab->beacon_counter); + + if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) { + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n", + sat_tab->pre_beacon_counter, + sat_tab->pkt_counter, + sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + /*@[data]*/ + else if (pktinfo->is_packet_to_self) { + if (sat_tab->pkt_skip_statistic_en == 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "ID[%d] pkt_cnt=((%d)): Beam_set = ((%d)), RSSI{A,B,avg} = {%d, %d, %d}\n", + pktinfo->station_id, sat_tab->pkt_counter, + sat_tab->fast_training_beam_num, + rx_power_ant0, rx_power_ant1, rssi_avg); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "Rate_ss = ((%d)), EVM{A,B} = {%d, %d}, RX Rate =", + pktinfo->rate_ss, rx_evm_ant0, rx_evm_ant1); + phydm_print_rate(dm, dm->rx_rate, DBG_ANT_DIV); + + if (sat_tab->pkt_counter >= 1) /*packet skip count*/ + { + sat_tab->beam_set_rssi_avg_sum[sat_tab->fast_training_beam_num] += rssi_avg; + sat_tab->statistic_pkt_cnt[sat_tab->fast_training_beam_num]++; + + sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][0] += rx_power_ant0; + sat_tab->beam_path_rssi_sum[sat_tab->fast_training_beam_num][1] += rx_power_ant1; + + if (pktinfo->rate_ss == 2) { + sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][0] += rx_evm_ant0; + sat_tab->beam_path_evm_2ss_sum[sat_tab->fast_training_beam_num][1] += rx_evm_ant1; + sat_tab->beam_path_evm_2ss_cnt[sat_tab->fast_training_beam_num]++; + } else { + sat_tab->beam_path_evm_1ss_sum[sat_tab->fast_training_beam_num] += rx_evm_ant0; + sat_tab->beam_path_evm_1ss_cnt[sat_tab->fast_training_beam_num]++; + } + } + + sat_tab->pkt_counter++; + + train_pkt_number = sat_tab->beam_set_train_cnt[sat_tab->fast_training_beam_num]; + + if (sat_tab->pkt_counter >= train_pkt_number) { + sat_tab->update_beam_idx++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "pre_beacon_counter = ((%d)), Update_new_beam = ((%d))\n", + sat_tab->pre_beacon_counter, + sat_tab->update_beam_idx); + + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->pkt_counter = 0; + } + } + } + + if (sat_tab->update_beam_idx > 0) { + sat_tab->update_beam_idx = 0; + + if (sat_tab->fast_training_beam_num >= ((u32)sat_tab->total_beam_set_num - 1)) { + fat_tab->fat_state = FAT_DECISION_STATE; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_fast_ant_training_hl_smart_antenna_type2(dm); /*@go to make decision*/ + #endif + #if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem); + #endif + + } else { + beam_tmp = sat_tab->fast_training_beam_num; + sat_tab->fast_training_beam_num++; + PHYDM_DBG(dm, DBG_ANT_DIV, + "Update Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, sat_tab->fast_training_beam_num); + phydm_set_rfu_beam_pattern_type2(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } +} +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + +void phydm_hl_smart_ant_type1_init_8821a( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + u32 value32; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "***8821A SmartAnt_Init => ant_div_type=[Hong-Lin Smart ant Type1]\n"); + +#if 0 + /* @---------------------------------------- */ + /* @GPIO 2-3 for Beam control */ + /* reg0x66[2]=0 */ + /* reg0x44[27:26] = 0 */ + /* reg0x44[23:16] enable_output for P_GPIO[7:0] */ + /* reg0x44[15:8] output_value for P_GPIO[7:0] */ + /* reg0x40[1:0] = 0 GPIO function */ + /* @------------------------------------------ */ +#endif + + /*@GPIO setting*/ + odm_set_mac_reg(dm, R_0x64, BIT(18), 0); + odm_set_mac_reg(dm, R_0x44, BIT(27) | BIT(26), 0); + odm_set_mac_reg(dm, R_0x44, BIT(19) | BIT(18), 0x3); /*@enable_output for P_GPIO[3:2]*/ +#if 0 + /*odm_set_mac_reg(dm, R_0x44, BIT(11)|BIT(10), 0);*/ /*output value*/ +#endif + odm_set_mac_reg(dm, R_0x40, BIT(1) | BIT(0), 0); /*@GPIO function*/ + + /*@Hong_lin smart antenna HW setting*/ + sat_tab->rfu_codeword_total_bit_num = 24; /*@max=32*/ + sat_tab->rfu_each_ant_bit_num = 4; + sat_tab->beam_patten_num_each_ant = 4; + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + sat_tab->latch_time = 100; /*@mu sec*/ +#elif DEV_BUS_TYPE == RT_USB_INTERFACE + sat_tab->latch_time = 100; /*@mu sec*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; + + sat_tab->ant_num = 1; /*@max=8*/ + sat_tab->ant_num_total = NUM_ANTENNA_8821A; + sat_tab->first_train_ant = MAIN_ANT; + + sat_tab->rfu_codeword_table[0] = 0x0; + sat_tab->rfu_codeword_table[1] = 0x4; + sat_tab->rfu_codeword_table[2] = 0x8; + sat_tab->rfu_codeword_table[3] = 0xc; + + sat_tab->rfu_codeword_table_5g[0] = 0x1; + sat_tab->rfu_codeword_table_5g[1] = 0x2; + sat_tab->rfu_codeword_table_5g[2] = 0x4; + sat_tab->rfu_codeword_table_5g[3] = 0x8; + + sat_tab->fix_beam_pattern_en = 0; + sat_tab->decision_holding_period = 0; + + /*@beam training setting*/ + sat_tab->pkt_counter = 0; + sat_tab->per_beam_training_pkt_num = 10; + + /*set default beam*/ + sat_tab->fast_training_beam_num = 0; + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + phydm_set_all_ant_same_beam_num(dm); + + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + + odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x01000100); + odm_set_bb_reg(dm, R_0xca8, MASKDWORD, 0x01000100); + + /*@[BB] FAT setting*/ + odm_set_bb_reg(dm, R_0xc08, BIT(18) | BIT(17) | BIT(16), sat_tab->ant_num); + odm_set_bb_reg(dm, R_0xc08, BIT(31), 0); /*@increase ant num every FAT period 0:+1, 1+2*/ + odm_set_bb_reg(dm, R_0x8c4, BIT(2) | BIT(1), 1); /*@change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ + odm_set_bb_reg(dm, R_0x8c4, BIT(0), 1); /*@FAT_watchdog_en*/ + + value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD); + odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /*Reg7B4[16]=1 enable antenna training */ + /*Reg7B4[17]=1 enable match MAC addr*/ + odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0); /*@Match MAC ADDR*/ + odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0); +} + +u32 phydm_construct_hl_beam_codeword( + void *dm_void, + u32 *beam_pattern_idx, + u32 ant_num) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 codeword = 0; + u32 data_tmp; + u32 i; + u32 break_counter = 0; + + if (ant_num < 8) { + for (i = 0; i < (sat_tab->ant_num_total); i++) { +#if 0 + /*PHYDM_DBG(dm,DBG_ANT_DIV, "beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] );*/ +#endif + if ((i < (sat_tab->first_train_ant - 1)) || break_counter >= sat_tab->ant_num) { + data_tmp = 0; + } else { + break_counter++; + + if (beam_pattern_idx[i] == 0) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[0]; + else + data_tmp = sat_tab->rfu_codeword_table[0]; + + } else if (beam_pattern_idx[i] == 1) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[1]; + else + data_tmp = sat_tab->rfu_codeword_table[1]; + + } else if (beam_pattern_idx[i] == 2) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[2]; + else + data_tmp = sat_tab->rfu_codeword_table[2]; + + } else if (beam_pattern_idx[i] == 3) { + if (*dm->band_type == ODM_BAND_5G) + data_tmp = sat_tab->rfu_codeword_table_5g[3]; + else + data_tmp = sat_tab->rfu_codeword_table[3]; + } + } + + codeword |= (data_tmp << (i * 4)); + } + } + + return codeword; +} + +void phydm_update_beam_pattern( + void *dm_void, + u32 codeword, + u32 codeword_length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u8 i; + boolean beam_ctrl_signal; + u32 one = 0x1; + u32 reg44_tmp_p, reg44_tmp_n, reg44_ori; + u8 devide_num = 4; + + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] Set Beam Pattern =0x%x\n", + codeword); + + reg44_ori = odm_get_mac_reg(dm, R_0x44, MASKDWORD); + reg44_tmp_p = reg44_ori; +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_ori =0x%x\n", reg44_ori);*/ +#endif + + devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((codeword & BIT(i)) >> i); + + if (dm->debug_components & DBG_ANT_DIV) { + if (i == (codeword_length - 1)) + pr_debug("%d ]\n", beam_ctrl_signal); + else if (i == 0) + pr_debug("Send codeword[1:%d] ---> [ %d ", codeword_length, beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + pr_debug("%d | ", beam_ctrl_signal); + else + pr_debug("%d ", beam_ctrl_signal); + } + + if (dm->support_ic_type == ODM_RTL8821) { + #if (RTL8821A_SUPPORT == 1) + reg44_tmp_p = reg44_ori & (~(BIT(11) | BIT(10))); /*@clean bit 10 & 11*/ + reg44_tmp_p |= ((1 << 11) | (beam_ctrl_signal << 10)); + reg44_tmp_n = reg44_ori & (~(BIT(11) | BIT(10))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n);*/ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + #endif + } + #if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) { + if (sat_tab->rfu_protocol_type == 2) { + reg44_tmp_p = reg44_tmp_p & ~(BIT(8)); /*@clean bit 8*/ + reg44_tmp_p = reg44_tmp_p ^ BIT(9); /*@get new clk high/low, exclusive-or*/ + + reg44_tmp_p |= (beam_ctrl_signal << 8); + + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44 =(( 0x%x )), reg44[9:8] = ((%x)), beam_ctrl_signal =((%x))\n", reg44_tmp_p, ((reg44_tmp_p & 0x300)>>8), beam_ctrl_signal);*/ +#endif + + } else { + reg44_tmp_p = reg44_ori & (~(BIT(9) | BIT(8))); /*@clean bit 9 & 8*/ + reg44_tmp_p |= ((1 << 9) | (beam_ctrl_signal << 8)); + reg44_tmp_n = reg44_ori & (~(BIT(9) | BIT(8))); + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n); */ +#endif + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_p); + ODM_delay_us(10); + odm_set_mac_reg(dm, R_0x44, MASKDWORD, reg44_tmp_n); + ODM_delay_us(10); + } + } + #endif + } +} + +void phydm_update_rx_idle_beam( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 i; + + sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm, + &sat_tab->rx_idle_beam[0], + sat_tab->ant_num); + PHYDM_DBG(dm, DBG_ANT_DIV, + "Set target beam_pattern codeword = (( 0x%x ))\n", + sat_tab->update_beam_codeword); + + for (i = 0; i < (sat_tab->ant_num); i++) + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, + sat_tab->rx_idle_beam[i]); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#endif +#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif +#endif + + sat_tab->pre_codeword = sat_tab->update_beam_codeword; +} + +void phydm_hl_smart_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 one = 0x1; + u32 codeword_length = sat_tab->rfu_codeword_total_bit_num; + u32 beam_ctrl_signal, i; + u8 devide_num = 4; + + if (dm_value[0] == 1) { /*@fix beam pattern*/ + + sat_tab->fix_beam_pattern_en = dm_value[1]; + + if (sat_tab->fix_beam_pattern_en == 1) { + sat_tab->fix_beam_pattern_codeword = dm_value[2]; + + if (sat_tab->fix_beam_pattern_codeword > (one << codeword_length)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Codeword overflow, Current codeword is ((0x%x)), and should be less than ((%d))bit\n", + sat_tab->fix_beam_pattern_codeword, + codeword_length); + + (sat_tab->fix_beam_pattern_codeword) &= 0xffffff; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Auto modify to (0x%x)\n", + sat_tab->fix_beam_pattern_codeword); + } + + sat_tab->update_beam_codeword = sat_tab->fix_beam_pattern_codeword; + + /*@---------------------------------------------------------*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "Fix Beam Pattern\n"); + + devide_num = (sat_tab->rfu_protocol_type == 2) ? 6 : 4; + + for (i = 0; i <= (codeword_length - 1); i++) { + beam_ctrl_signal = (boolean)((sat_tab->update_beam_codeword & BIT(i)) >> i); + + if (i == (codeword_length - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "%d]\n", + beam_ctrl_signal); + else if (i == 0) + PDM_SNPF(out_len, used, + output + used, + out_len - used, + "Send Codeword[1:24] to RFU -> [%d", + beam_ctrl_signal); + else if ((i % devide_num) == (devide_num - 1)) + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d|", + beam_ctrl_signal); + else + PDM_SNPF(out_len, used, + output + used, + out_len - used, "%d", + beam_ctrl_signal); + } +/*@---------------------------------------------------------*/ + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + #endif + #if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +#if 0 + /*odm_stall_execution(1);*/ +#endif + #endif + } else if (sat_tab->fix_beam_pattern_en == 0) + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Smart Antenna: Enable\n"); + + } else if (dm_value[0] == 2) { /*set latch time*/ + + sat_tab->latch_time = dm_value[1]; + PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] latch_time =0x%x\n", + sat_tab->latch_time); + } else if (dm_value[0] == 3) { + sat_tab->fix_training_num_en = dm_value[1]; + + if (sat_tab->fix_training_num_en == 1) { + sat_tab->per_beam_training_pkt_num = (u8)dm_value[2]; + sat_tab->decision_holding_period = (u8)dm_value[3]; + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[SmartAnt][Dbg] Fix_train_en = (( %d )), train_pkt_num = (( %d )), holding_period = (( %d )),\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + + } else if (sat_tab->fix_training_num_en == 0) { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] AUTO per_beam_training_pkt_num\n"); + } + } else if (dm_value[0] == 4) { + if (dm_value[1] == 1) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = MAIN_ANT; + + } else if (dm_value[1] == 2) { + sat_tab->ant_num = 1; + sat_tab->first_train_ant = AUX_ANT; + + } else if (dm_value[1] == 3) { + sat_tab->ant_num = 2; + sat_tab->first_train_ant = MAIN_ANT; + } + + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set ant Num = (( %d )), first_train_ant = (( %d ))\n", + sat_tab->ant_num, (sat_tab->first_train_ant - 1)); + } else if (dm_value[0] == 5) { + if (dm_value[1] <= 3) { + sat_tab->rfu_codeword_table[dm_value[1]] = dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2]); + } else { + for (i = 0; i < 4; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show Beam_2G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, sat_tab->rfu_codeword_table[i]); + } + } + } else if (dm_value[0] == 6) { + if (dm_value[1] <= 3) { + sat_tab->rfu_codeword_table_5g[dm_value[1]] = dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + dm_value[1], dm_value[2]); + } else { + for (i = 0; i < 4; i++) { + PDM_SNPF(out_len, used, output + used, + out_len - used, + "[ SmartAnt ] Show Beam_5G: (( %d )), RFU codeword table = (( 0x%x ))\n", + i, sat_tab->rfu_codeword_table_5g[i]); + } + } + } else if (dm_value[0] == 7) { + if (dm_value[1] <= 4) { + sat_tab->beam_patten_num_each_ant = dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Set Beam number = (( %d ))\n", + sat_tab->beam_patten_num_each_ant); + } else { + PDM_SNPF(out_len, used, output + used, out_len - used, + "[ SmartAnt ] Show Beam number = (( %d ))\n", + sat_tab->beam_patten_num_each_ant); + } + } + *_used = used; + *_out_len = out_len; +} + +void phydm_set_all_ant_same_beam_num( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + + if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) { /*@2ant for 8821A*/ + + sat_tab->rx_idle_beam[0] = sat_tab->fast_training_beam_num; + sat_tab->rx_idle_beam[1] = sat_tab->fast_training_beam_num; + } + + sat_tab->update_beam_codeword = phydm_construct_hl_beam_codeword(dm, + &sat_tab->rx_idle_beam[0], + sat_tab->ant_num); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", + sat_tab->update_beam_codeword); + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); +#endif +#if DEV_BUS_TYPE == RT_USB_INTERFACE || DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (dm->support_interface == ODM_ITRF_USB || dm->support_interface == ODM_ITRF_SDIO) + odm_schedule_work_item(&sat_tab->hl_smart_antenna_workitem); +/*odm_stall_execution(1);*/ +#endif +} + +void odm_fast_ant_training_hl_smart_antenna_type1( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + struct phydm_fat_struct *fat_tab = &dm->dm_fat_table; + struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table; + u32 codeword = 0, i, j; + u32 target_ant; + u32 avg_rssi_tmp, avg_rssi_tmp_ma; + u32 target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; + u32 max_beam_ant_rssi = 0; + u32 target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; + u32 beam_tmp; + u8 next_ant; + u32 rssi_sorting_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_seq[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u32 rank_idx_out[SUPPORT_BEAM_PATTERN_NUM] = {0}; + u8 per_beam_rssi_diff_tmp = 0, training_pkt_num_offset; + u32 break_counter = 0; + u32 used_ant; + + if (!dm->is_linked) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n"); + + if (fat_tab->is_become_linked == true) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Link->no Link\n"); + fat_tab->fat_state = FAT_BEFORE_LINK_STATE; + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + + fat_tab->is_become_linked = dm->is_linked; + } + return; + + } else { + if (fat_tab->is_become_linked == false) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n"); + + fat_tab->fat_state = FAT_PREPARE_STATE; + PHYDM_DBG(dm, DBG_ANT_DIV, + "change to (( %d )) FAT_state\n", + fat_tab->fat_state); + +#if 0 + /*sat_tab->fast_training_beam_num = 0;*/ + /*phydm_set_all_ant_same_beam_num(dm);*/ +#endif + + fat_tab->is_become_linked = dm->is_linked; + } + } + + if (!(*fat_tab->p_force_tx_by_desc)) { + if (dm->is_one_entry_only == true) + odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG); + else + odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC); + } + +#if 0 + /*PHYDM_DBG(dm, DBG_ANT_DIV, "HL Smart ant Training: state (( %d ))\n", fat_tab->fat_state);*/ +#endif + + /* @[DECISION STATE] */ + /*@=======================================================================================*/ + if (fat_tab->fat_state == FAT_DECISION_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 3. In Decision state]\n"); + phydm_fast_training_enable(dm, FAT_OFF); + + break_counter = 0; + /*@compute target beam in each antenna*/ + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + if (sat_tab->pkt_rssi_cnt[i][j] == 0) { + avg_rssi_tmp = sat_tab->pkt_rssi_pre[i][j]; + avg_rssi_tmp = (avg_rssi_tmp >= 2) ? (avg_rssi_tmp - 2) : avg_rssi_tmp; + avg_rssi_tmp_ma = avg_rssi_tmp; + } else { + avg_rssi_tmp = (sat_tab->pkt_rssi_sum[i][j]) / (sat_tab->pkt_rssi_cnt[i][j]); + avg_rssi_tmp_ma = (avg_rssi_tmp + sat_tab->pkt_rssi_pre[i][j]) >> 1; + } + + rssi_sorting_seq[j] = avg_rssi_tmp; + sat_tab->pkt_rssi_pre[i][j] = avg_rssi_tmp; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "ant[%d], Beam[%d]: pkt_cnt=(( %d )), avg_rssi_MA=(( %d )), avg_rssi=(( %d ))\n", + i, j, sat_tab->pkt_rssi_cnt[i][j], + avg_rssi_tmp_ma, avg_rssi_tmp); + + if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { + target_ant_beam[i] = j; + target_ant_beam_max_rssi[i] = avg_rssi_tmp; + } + + /*reset counter value*/ + sat_tab->pkt_rssi_sum[i][j] = 0; + sat_tab->pkt_rssi_cnt[i][j] = 0; + } + sat_tab->rx_idle_beam[i] = target_ant_beam[i]; + PHYDM_DBG(dm, DBG_ANT_DIV, + "---------> Target of ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", + i, target_ant_beam[i], + target_ant_beam_max_rssi[i]); + +#if 0 + /*sorting*/ + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Pre]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]); + */ + + /*phydm_seq_sorting(dm, &rssi_sorting_seq[0], &rank_idx_seq[0], &rank_idx_out[0], SUPPORT_BEAM_PATTERN_NUM);*/ + + /*@ + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rssi_sorting_seq = [%d, %d, %d, %d]\n", rssi_sorting_seq[0], rssi_sorting_seq[1], rssi_sorting_seq[2], rssi_sorting_seq[3]); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_seq = [%d, %d, %d, %d]\n", rank_idx_seq[0], rank_idx_seq[1], rank_idx_seq[2], rank_idx_seq[3]); + PHYDM_DBG(dm, DBG_ANT_DIV, "[Post]rank_idx_out = [%d, %d, %d, %d]\n", rank_idx_out[0], rank_idx_out[1], rank_idx_out[2], rank_idx_out[3]); + */ +#endif + + if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { + target_ant = i; + max_beam_ant_rssi = target_ant_beam_max_rssi[i]; +#if + /*PHYDM_DBG(dm, DBG_ANT_DIV, "Target of ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", + target_ant, max_beam_ant_rssi);*/ +#endif + } + break_counter++; + if (break_counter >= sat_tab->ant_num) + break; + } + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + per_beam_rssi_diff_tmp = (u8)(max_beam_ant_rssi - sat_tab->pkt_rssi_pre[i][j]); + sat_tab->beam_train_rssi_diff[i][j] = per_beam_rssi_diff_tmp; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "ant[%d], Beam[%d]: RSSI_diff= ((%d))\n", + i, j, per_beam_rssi_diff_tmp); + } + break_counter++; + if (break_counter >= sat_tab->ant_num) + break; + } +#endif + + if (target_ant == 0) + target_ant = MAIN_ANT; + else if (target_ant == 1) + target_ant = AUX_ANT; + + if (sat_tab->ant_num > 1) { + /* @[ update RX ant ]*/ + odm_update_rx_idle_ant(dm, (u8)target_ant); + + /* @[ update TX ant ]*/ + odm_update_tx_ant(dm, (u8)target_ant, (fat_tab->train_idx)); + } + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam(dm); + + odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A); + fat_tab->fat_state = FAT_PREPARE_STATE; + return; + } + /* @[TRAINING STATE] */ + else if (fat_tab->fat_state == FAT_TRAINING_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "[ 2. In Training state]\n"); + + PHYDM_DBG(dm, DBG_ANT_DIV, + "fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", + sat_tab->fast_training_beam_num, + sat_tab->pre_fast_training_beam_num); + + if (sat_tab->fast_training_beam_num > sat_tab->pre_fast_training_beam_num) + + sat_tab->force_update_beam_en = 0; + + else { + sat_tab->force_update_beam_en = 1; + + sat_tab->pkt_counter = 0; + beam_tmp = sat_tab->fast_training_beam_num; + if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", + sat_tab->fast_training_beam_num); + fat_tab->fat_state = FAT_DECISION_STATE; + odm_fast_ant_training_hl_smart_antenna_type1(dm); + + } else { + sat_tab->fast_training_beam_num++; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", + beam_tmp, + sat_tab->fast_training_beam_num); + phydm_set_all_ant_same_beam_num(dm); + fat_tab->fat_state = FAT_TRAINING_STATE; + } + } + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + PHYDM_DBG(dm, DBG_ANT_DIV, + "[prepare state] Update Pre_Beam =(( %d ))\n", + sat_tab->pre_fast_training_beam_num); + } + /* @[Prepare state] */ + /*@=======================================================================================*/ + else if (fat_tab->fat_state == FAT_PREPARE_STATE) { + PHYDM_DBG(dm, DBG_ANT_DIV, "\n\n[ 1. In Prepare state]\n"); + + if (dm->pre_traffic_load == dm->traffic_load) { + if (sat_tab->decision_holding_period != 0) { + PHYDM_DBG(dm, DBG_ANT_DIV, + "Holding_period = (( %d )), return!!!\n", + sat_tab->decision_holding_period); + sat_tab->decision_holding_period--; + return; + } + } + + /* Set training packet number*/ + if (sat_tab->fix_training_num_en == 0) { + switch (dm->traffic_load) { + case TRAFFIC_HIGH: + sat_tab->per_beam_training_pkt_num = 8; + sat_tab->decision_holding_period = 2; + break; + case TRAFFIC_MID: + sat_tab->per_beam_training_pkt_num = 6; + sat_tab->decision_holding_period = 3; + break; + case TRAFFIC_LOW: + sat_tab->per_beam_training_pkt_num = 3; /*ping 60000*/ + sat_tab->decision_holding_period = 4; + break; + case TRAFFIC_ULTRA_LOW: + sat_tab->per_beam_training_pkt_num = 1; + sat_tab->decision_holding_period = 6; + break; + default: + break; + } + } + PHYDM_DBG(dm, DBG_ANT_DIV, + "Fix_training_en = (( %d )), training_pkt_num_base = (( %d )), holding_period = ((%d))\n", + sat_tab->fix_training_num_en, + sat_tab->per_beam_training_pkt_num, + sat_tab->decision_holding_period); + +#ifdef CONFIG_FAT_PATCH + break_counter = 0; + for (i = (sat_tab->first_train_ant - 1); i < sat_tab->ant_num_total; i++) { + for (j = 0; j < (sat_tab->beam_patten_num_each_ant); j++) { + per_beam_rssi_diff_tmp = sat_tab->beam_train_rssi_diff[i][j]; + training_pkt_num_offset = per_beam_rssi_diff_tmp; + + if (sat_tab->per_beam_training_pkt_num > training_pkt_num_offset) + sat_tab->beam_train_cnt[i][j] = sat_tab->per_beam_training_pkt_num - training_pkt_num_offset; + else + sat_tab->beam_train_cnt[i][j] = 1; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "ant[%d]: Beam_num-(( %d )) training_pkt_num = ((%d))\n", + i, j, sat_tab->beam_train_cnt[i][j]); + } + break_counter++; + if (break_counter >= sat_tab->ant_num) + break; + } + + phydm_fast_training_enable(dm, FAT_OFF); + sat_tab->pre_beacon_counter = sat_tab->beacon_counter; + sat_tab->update_beam_idx = 0; + + if (*dm->band_type == ODM_BAND_5G) { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set 5G ant\n"); + /*used_ant = (sat_tab->first_train_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;*/ + used_ant = sat_tab->first_train_ant; + } else { + PHYDM_DBG(dm, DBG_ANT_DIV, "Set 2.4G ant\n"); + used_ant = sat_tab->first_train_ant; + } + + odm_update_rx_idle_ant(dm, (u8)used_ant); + +#else + /* Set training MAC addr. of target */ + odm_set_next_mac_addr_target(dm); + phydm_fast_training_enable(dm, FAT_ON); +#endif + + odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A); + sat_tab->pkt_counter = 0; + sat_tab->fast_training_beam_num = 0; + phydm_set_all_ant_same_beam_num(dm); + sat_tab->pre_fast_training_beam_num = sat_tab->fast_training_beam_num; + fat_tab->fat_state = FAT_TRAINING_STATE; + } +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +void phydm_beam_switch_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct smt_ant_honbo *sat_tab = &dm->dm_sat_table; + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE + sat_tab->pkt_skip_statistic_en = 1; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", + sat_tab->pkt_skip_statistic_en); + + phydm_update_beam_pattern(dm, sat_tab->update_beam_codeword, sat_tab->rfu_codeword_total_bit_num); + +#if DEV_BUS_TYPE != RT_PCI_INTERFACE +#if 0 + /*odm_stall_execution(sat_tab->latch_time);*/ +#endif + sat_tab->pkt_skip_statistic_en = 0; +#endif + PHYDM_DBG(dm, DBG_ANT_DIV, + "pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", + sat_tab->pkt_skip_statistic_en, sat_tab->latch_time); +} + +void phydm_beam_decision_workitem_callback( + void *context) +{ + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + + PHYDM_DBG(dm, DBG_ANT_DIV, + "[ SmartAnt ] Beam decision Workitem Callback\n"); + odm_fast_ant_training_hl_smart_antenna_type1(dm); +} +#endif + +#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +#endif /*@#ifdef CONFIG_HL_SMART_ANTENNA*/ + +void phydm_smt_ant_config( + void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + + dm->support_ability |= ODM_BB_SMT_ANT; + smtant_table->smt_ant_vendor = SMTANT_CUMITEK; + smtant_table->smt_ant_type = 1; +#if (RTL8822B_SUPPORT == 1) + dm->rfe_type = SMTANT_TMP_RFE_TYPE; +#endif +#elif (defined(CONFIG_HL_SMART_ANTENNA)) + + dm->support_ability |= ODM_BB_SMT_ANT; + smtant_table->smt_ant_vendor = SMTANT_HON_BO; + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + smtant_table->smt_ant_type = 1; +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + smtant_table->smt_ant_type = 2; +#endif +#endif + + PHYDM_DBG(dm, DBG_SMT_ANT, + "[SmtAnt Config] Vendor=((%d)), Smt_ant_type =((%d))\n", + smtant_table->smt_ant_vendor, smtant_table->smt_ant_type); +} + +void phydm_smt_ant_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct smt_ant *smtant_table = &dm->smtant_table; + + phydm_smt_ant_config(dm); + + if (smtant_table->smt_ant_vendor == SMTANT_CUMITEK) { +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +#if (RTL8822B_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8822B) + phydm_cumitek_smt_ant_init_8822b(dm); +#endif + +#if (RTL8197F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8197F) + phydm_cumitek_smt_ant_init_8197f(dm); +#endif +/*@jj add 20170822*/ +#if (RTL8192F_SUPPORT == 1) + if (dm->support_ic_type == ODM_RTL8192F) + phydm_cumitek_smt_ant_init_8192f(dm); +#endif +#endif /*@#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))*/ + + } else if (smtant_table->smt_ant_vendor == SMTANT_HON_BO) { +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (dm->support_ic_type == ODM_RTL8821) + phydm_hl_smart_ant_type1_init_8821a(dm); +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + if (dm->support_ic_type == ODM_RTL8822B) + phydm_hl_smart_ant_type2_init_8822b(dm); +#endif +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/ + } +} +#endif diff --git a/hal/phydm/phydm_smt_ant.h b/hal/phydm/phydm_smt_ant.h new file mode 100644 index 0000000..3a408c4 --- /dev/null +++ b/hal/phydm/phydm_smt_ant.h @@ -0,0 +1,210 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +#ifndef __PHYDMSMTANT_H__ +#define __PHYDMSMTANT_H__ + +/*@#define SMT_ANT_VERSION "1.1"*/ /*@2017.03.13*/ +/*@#define SMT_ANT_VERSION "1.2"*/ /*@2017.03.28*/ +#define SMT_ANT_VERSION "2.0" /* @Add Cumitek SmtAnt 2017.05.25*/ + +#define SMTANT_RTK 1 +#define SMTANT_HON_BO 2 +#define SMTANT_CUMITEK 3 + +#if (defined(CONFIG_SMART_ANTENNA)) + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +struct smt_ant_cumitek { + u8 tx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*@[pathA~B] [MACID 0~128]*/ + u8 rx_default_ant_idx[2]; /*@[pathA~B]*/ +}; +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +struct smt_ant_honbo { + u32 latch_time; + boolean pkt_skip_statistic_en; + u32 fix_beam_pattern_en; + u32 fix_training_num_en; + u32 fix_beam_pattern_codeword; + u32 update_beam_codeword; + u32 ant_num; /*number of "used" smart beam antenna*/ + u32 ant_num_total;/*number of "total" smart beam antenna*/ + u32 first_train_ant; /*@decide witch antenna to train first*/ + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*@rssi of each path with a certain beam pattern*/ + u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u32 rfu_codeword_table[4]; /*@2G beam truth table*/ + u32 rfu_codeword_table_5g[4]; /*@5G beam truth table*/ + u32 beam_patten_num_each_ant;/*@number of beam can be switched in each antenna*/ + u32 rx_idle_beam[SUPPORT_RF_PATH_NUM]; + u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; + u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; + #endif + + u32 fast_training_beam_num;/*@current training beam_set index*/ + u32 pre_fast_training_beam_num;/*pre training beam_set index*/ + u32 rfu_codeword_total_bit_num; /* @total bit number of RFU protocol*/ + u32 rfu_each_ant_bit_num; /* @bit number of RFU protocol for each ant*/ + u8 per_beam_training_pkt_num; + u8 decision_holding_period; + + + u32 pre_codeword; + boolean force_update_beam_en; + u32 beacon_counter; + u32 pre_beacon_counter; + u8 pkt_counter; /*@packet number that each beam-set should be colected in training state*/ + u8 update_beam_idx; /*@the index announce that the beam can be updated*/ + u8 rfu_protocol_type; + u16 rfu_protocol_delay_time; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM hl_smart_antenna_workitem; + RT_WORK_ITEM hl_smart_antenna_decision_workitem; + #endif + + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 + u8 beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@avg pre_rssi of each beam set*/ + u8 beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/ + u8 beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@training pkt num of each beam set*/ + u32 beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@RSSI_sum of avg(pathA,pathB) for each beam-set)*/ + u32 beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@RSSI_sum of each path for each beam-set)*/ + + u8 beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@2SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u8 beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; + u32 beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*@1SS evm_sum of each path for each beam-set)*/ + u32 beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; + + u32 statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@statistic_pkt_cnt for SmtAnt make decision*/ + + u8 total_beam_set_num; /*@number of beam set can be switched*/ + u8 total_beam_set_num_2g;/*@number of beam set can be switched in 2G*/ + u8 total_beam_set_num_5g;/*@number of beam set can be switched in 5G*/ + + u8 rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@2G beam truth table*/ + u8 rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@5G beam truth table*/ + u8 rx_idle_beam_set_idx; /*the filanl decsion result*/ + #endif + + +}; +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/ + +struct smt_ant { + u8 smt_ant_vendor; + u8 smt_ant_type; + u8 tx_desc_mode; /*@0:3 bit mode, 1:2 bit mode*/ + #if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) + struct smt_ant_cumitek cumi_smtant_table; + #endif +}; + +#if (defined(CONFIG_CUMITEK_SMART_ANTENNA)) +void phydm_cumitek_smt_tx_ant_update( + void *dm_void, + u8 tx_ant_idx_path_a, + u8 tx_ant_idx_path_b, + u32 mac_id); + +void phydm_cumitek_smt_rx_default_ant_update( + void *dm_void, + u8 rx_ant_idx_path_a, + u8 rx_ant_idx_path_b); + +void phydm_cumitek_smt_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +#endif + +#if (defined(CONFIG_HL_SMART_ANTENNA)) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_beam_switch_workitem_callback( + void *context); + +void phydm_beam_decision_workitem_callback( + void *context); +#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2 +void phydm_hl_smart_ant_type2_init_8822b( + void *dm_void); + +void phydm_update_beam_pattern_type2( + void *dm_void, + u32 codeword, + u32 codeword_length); + +void phydm_set_rfu_beam_pattern_type2( + void *dm_void); + +void phydm_hl_smt_ant_dbg_type2( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +void phydm_process_rssi_for_hb_smtant_type2( + void *dm_void, + void *phy_info_void, + void *pkt_info_void, + u8 rssi_avg); + +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/ + +#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1)) + +void phydm_update_beam_pattern( + void *dm_void, + u32 codeword, + u32 codeword_length); + +void phydm_set_all_ant_same_beam_num( + void *dm_void); + +void phydm_hl_smart_ant_debug( + void *dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len); + +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/ +#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/ +void phydm_smt_ant_init(void *dm_void); +#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/ +#endif \ No newline at end of file diff --git a/hal/phydm/phydm_soml.c b/hal/phydm/phydm_soml.c new file mode 100644 index 0000000..cd4001a --- /dev/null +++ b/hal/phydm/phydm_soml.c @@ -0,0 +1,1451 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ + +/************************************************************* + * include files + ************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#ifdef CONFIG_ADAPTIVE_SOML + +void phydm_dynamicsoftmletting(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 ret_val; + +#if (RTL8822B_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8822B) { + if (!dm->is_linked | dm->iot_table.is_linked_cmw500) + return; + + if (dm->bsomlenabled) { + PHYDM_DBG(dm, ODM_COMP_API, + "PHYDM_DynamicSoftMLSetting(): SoML has been enable, skip dynamic SoML switch\n"); + return; + } + + ret_val = odm_get_bb_reg(dm, R_0xf8c, MASKBYTE0); + PHYDM_DBG(dm, ODM_COMP_API, + "PHYDM_DynamicSoftMLSetting(): Read 0xF8C = 0x%08X\n", + ret_val); + + if (ret_val < 0x16) { + PHYDM_DBG(dm, ODM_COMP_API, + "PHYDM_DynamicSoftMLSetting(): 0xF8C(== 0x%08X) < 0x16, enable SoML\n", + ret_val); + phydm_somlrxhp_setting(dm, true); +#if 0 + /*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xc10a0000);*/ +#endif + dm->bsomlenabled = true; + } + } + } +#endif +} + +void phydm_soml_on_off(void *dm_void, u8 swch) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + if (swch == SOML_ON) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn on )) SOML\n"); + + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0x998, BIT(6), swch); +#if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) + phydm_somlrxhp_setting(dm, true); +#endif + + } else if (swch == SOML_OFF) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "(( Turn off )) SOML\n"); + + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, R_0x998, BIT(6), swch); +#if (RTL8822B_SUPPORT == 1) + else if (dm->support_ic_type == ODM_RTL8822B) + phydm_somlrxhp_setting(dm, false); +#endif + } + soml_tab->soml_on_off = swch; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_adaptive_soml_callback(struct phydm_timer_list *timer) +{ + void *adapter = (void *)timer->Adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + #if USE_WORKITEM + odm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem); + #else + { +#if 0 + /*@dbg_print("%s\n",__func__);*/ +#endif + phydm_adsl(dm); + } + #endif + #else + odm_schedule_work_item(&soml_tab->phydm_adaptive_soml_workitem); + #endif +} + +void phydm_adaptive_soml_workitem_callback(void *context) +{ +#ifdef CONFIG_ADAPTIVE_SOML + void *adapter = (void *)context; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + struct dm_struct *dm = &hal_data->DM_OutSrc; + +#if 0 + /*@dbg_print("%s\n",__func__);*/ +#endif + phydm_adsl(dm); +#endif +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_adaptive_soml_callback(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + void *padapter = dm->adapter; + + if (*dm->is_net_closed == true) + return; + if (dm->support_interface == ODM_ITRF_PCIE) + phydm_adsl(dm); + else { + /* @Can't do I/O in timer callback*/ + phydm_run_in_thread_cmd(dm, + phydm_adaptive_soml_workitem_callback, + dm); + } +} + +void phydm_adaptive_soml_workitem_callback(void *context) +{ + struct dm_struct *dm = (void *)context; + +#if 0 + /*@dbg_print("%s\n",__func__);*/ +#endif + phydm_adsl(dm); +} + +#else +void phydm_adaptive_soml_callback(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "******SOML_Callback******\n"); + phydm_adsl(dm); +} +#endif + +void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + struct phydm_perpkt_info_struct *pktinfo = NULL; + u8 data_rate; + + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + data_rate = (pktinfo->data_rate & 0x7f); + + if (pktinfo->data_rate >= ODM_RATEMCS0 && + pktinfo->data_rate <= ODM_RATEMCS31) + soml_tab->ht_cnt[data_rate - ODM_RATEMCS0]++; + else if ((pktinfo->data_rate >= ODM_RATEVHTSS1MCS0) && + (pktinfo->data_rate <= ODM_RATEVHTSS4MCS9)) + soml_tab->vht_cnt[data_rate - ODM_RATEVHTSS1MCS0]++; +} + +void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + struct phydm_perpkt_info_struct *pktinfo = NULL; + u8 date_rate; + + pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void; + date_rate = (pktinfo->data_rate & 0x7f); + if (soml_tab->soml_state_cnt < (soml_tab->soml_train_num << 1)) { + if (soml_tab->soml_on_off == SOML_ON) { + return; + } else if (soml_tab->soml_on_off == SOML_OFF) { + if (date_rate >= ODM_RATEMCS8 && + date_rate <= ODM_RATEMCS10) + soml_tab->num_ht_qam[BPSK_QPSK]++; + + else if ((date_rate >= ODM_RATEMCS11) && + (date_rate <= ODM_RATEMCS12)) + soml_tab->num_ht_qam[QAM16]++; + + else if ((date_rate >= ODM_RATEMCS13) && + (date_rate <= ODM_RATEMCS15)) + soml_tab->num_ht_qam[QAM64]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS0) && + (date_rate <= ODM_RATEVHTSS2MCS2)) + soml_tab->num_vht_qam[BPSK_QPSK]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS3) && + (date_rate <= ODM_RATEVHTSS2MCS4)) + soml_tab->num_vht_qam[QAM16]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS5) && + (date_rate <= ODM_RATEVHTSS2MCS5)) + soml_tab->num_vht_qam[QAM64]++; + + else if ((date_rate >= ODM_RATEVHTSS2MCS8) && + (date_rate <= ODM_RATEVHTSS2MCS9)) + soml_tab->num_vht_qam[QAM256]++; + } + } +} + +void phydm_soml_reset_rx_rate(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 order; + + for (order = 0; order < HT_RATE_IDX; order++) { + soml_tab->ht_cnt[order] = 0; + soml_tab->pre_ht_cnt[order] = 0; + soml_tab->ht_cnt_on[order] = 0; + soml_tab->ht_cnt_off[order] = 0; + soml_tab->ht_crc_ok_cnt_on[order] = 0; + soml_tab->ht_crc_fail_cnt_on[order] = 0; + soml_tab->ht_crc_ok_cnt_off[order] = 0; + soml_tab->ht_crc_fail_cnt_off[order] = 0; + } + + for (order = 0; order < VHT_RATE_IDX; order++) { + soml_tab->vht_cnt[order] = 0; + soml_tab->pre_vht_cnt[order] = 0; + soml_tab->vht_cnt_on[order] = 0; + soml_tab->vht_cnt_off[order] = 0; + soml_tab->vht_crc_ok_cnt_on[order] = 0; + soml_tab->vht_crc_fail_cnt_on[order] = 0; + soml_tab->vht_crc_ok_cnt_off[order] = 0; + soml_tab->vht_crc_fail_cnt_off[order] = 0; + } +} + +void phydm_soml_reset_qam(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 order; + + for (order = 0; order < HT_ORDER_TYPE; order++) + soml_tab->num_ht_qam[order] = 0; + + for (order = 0; order < VHT_ORDER_TYPE; order++) + soml_tab->num_vht_qam[order] = 0; +} + +void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 value32, value32_1, value32_2, value32_3; + s32 cfo_acq_a, cfo_acq_b, cfo_end_a, cfo_end_b; + + value32 = odm_get_bb_reg(dm, R_0xd10, MASKDWORD); + value32_1 = odm_get_bb_reg(dm, R_0xd14, MASKDWORD); + value32_2 = odm_get_bb_reg(dm, R_0xd50, MASKDWORD); + value32_3 = odm_get_bb_reg(dm, R_0xd54, MASKDWORD); + + cfo_acq_a = (s32)((value32 & 0x1fff0000) >> 16); + cfo_end_a = (s32)((value32_1 & 0x1fff0000) >> 16); + cfo_acq_b = (s32)((value32_2 & 0x1fff0000) >> 16); + cfo_end_b = (s32)((value32_3 & 0x1fff0000) >> 16); + + *diff_a = ((cfo_acq_a >= cfo_end_a) ? (cfo_acq_a - cfo_end_a) : + (cfo_end_a - cfo_acq_a)); + *diff_b = ((cfo_acq_b >= cfo_end_b) ? (cfo_acq_b - cfo_end_b) : + (cfo_end_b - cfo_acq_b)); + + *diff_a = ((*diff_a * 312) + (*diff_a >> 1)) >> 12; /* @312.5/2^12 */ + *diff_b = ((*diff_b * 312) + (*diff_b >> 1)) >> 12; /* @312.5/2^12 */ +} + +void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u32 used = *_used; + u32 out_len = *_out_len; + u32 dm_value[10] = {0}; + u8 i = 0, input_idx = 0; + + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) + return; + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &dm_value[i]); + input_idx++; + } + } + + if (input_idx == 0) + return; + + if (dm_value[0] == 1) { /*Turn on/off SOML*/ + soml_tab->soml_select = (u8)dm_value[1]; + + } else if (dm_value[0] == 2) { /*training number for SOML*/ + + soml_tab->soml_train_num = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_train_num = ((%d))\n", + soml_tab->soml_train_num); + } else if (dm_value[0] == 3) { /*training interval for SOML*/ + + soml_tab->soml_intvl = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_intvl = ((%d))\n", soml_tab->soml_intvl); + } else if (dm_value[0] == 4) { /*@function period for SOML*/ + + soml_tab->soml_period = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_period = ((%d))\n", soml_tab->soml_period); + } else if (dm_value[0] == 5) { /*@delay_time for SOML*/ + + soml_tab->soml_delay_time = (u8)dm_value[1]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_delay_time = ((%d))\n", + soml_tab->soml_delay_time); + } else if (dm_value[0] == 6) { /* @for SOML Rx QAM distribution th*/ + if (dm_value[1] == 256) { + soml_tab->qam256_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam256_dist_th = ((%d))\n", + soml_tab->qam256_dist_th); + } else if (dm_value[1] == 64) { + soml_tab->qam64_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam64_dist_th = ((%d))\n", + soml_tab->qam64_dist_th); + } else if (dm_value[1] == 16) { + soml_tab->qam16_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam16_dist_th = ((%d))\n", + soml_tab->qam16_dist_th); + } else if (dm_value[1] == 4) { + soml_tab->bpsk_qpsk_dist_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "bpsk_qpsk_dist_th = ((%d))\n", + soml_tab->bpsk_qpsk_dist_th); + } + } else if (dm_value[0] == 7) { /* @for SOML cfo th*/ + if (dm_value[1] == 256) { + soml_tab->cfo_qam256_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam256_th = ((%d KHz))\n", + soml_tab->cfo_qam256_th); + } else if (dm_value[1] == 64) { + soml_tab->cfo_qam64_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam64_th = ((%d KHz))\n", + soml_tab->cfo_qam64_th); + } else if (dm_value[1] == 16) { + soml_tab->cfo_qam16_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam16_th = ((%d KHz))\n", + soml_tab->cfo_qam16_th); + } else if (dm_value[1] == 4) { + soml_tab->cfo_qpsk_th = (u8)dm_value[2]; + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qpsk_th = ((%d KHz))\n", + soml_tab->cfo_qpsk_th); + } + } else if (dm_value[0] == 100) { + /*show parameters*/ + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_select = ((%d))\n", soml_tab->soml_select); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_train_num = ((%d))\n", + soml_tab->soml_train_num); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_intvl = ((%d))\n", soml_tab->soml_intvl); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_period = ((%d))\n", soml_tab->soml_period); + PDM_SNPF(out_len, used, output + used, out_len - used, + "soml_delay_time = ((%d))\n\n", + soml_tab->soml_delay_time); + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam256_dist_th = ((%d)), qam64_dist_th = ((%d)), ", + soml_tab->qam256_dist_th, + soml_tab->qam64_dist_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "qam16_dist_th = ((%d)), bpsk_qpsk_dist_th = ((%d))\n", + soml_tab->qam16_dist_th, + soml_tab->bpsk_qpsk_dist_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam256_th = ((%d KHz)), cfo_qam64_th = ((%d KHz)), ", + soml_tab->cfo_qam256_th, + soml_tab->cfo_qam64_th); + PDM_SNPF(out_len, used, output + used, out_len - used, + "cfo_qam16_th = ((%d KHz)), cfo_qpsk_th = ((%d KHz))\n", + soml_tab->cfo_qam16_th, + soml_tab->cfo_qpsk_th); + } + *_used = used; + *_out_len = out_len; +} + +void phydm_soml_stats_ht_on(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 i, mcs0; + u16 num_bytes_diff, num_rate_diff; + + mcs0 = ODM_RATEMCS0; + for (i = mcs0; i <= ODM_RATEMCS15; i++) { + num_rate_diff = soml_tab->ht_cnt[i - mcs0] - + soml_tab->pre_ht_cnt[i - mcs0]; + soml_tab->ht_cnt_on[i - mcs0] += num_rate_diff; + soml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0]; + num_bytes_diff = soml_tab->ht_byte[i - mcs0] - + soml_tab->pre_ht_byte[i - mcs0]; + soml_tab->ht_byte_on[i - mcs0] += num_bytes_diff; + soml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0]; + } +} + +void phydm_soml_stats_ht_off(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 i, mcs0; + u16 num_bytes_diff, num_rate_diff; + + mcs0 = ODM_RATEMCS0; + for (i = mcs0; i <= ODM_RATEMCS15; i++) { + num_rate_diff = soml_tab->ht_cnt[i - mcs0] - + soml_tab->pre_ht_cnt[i - mcs0]; + soml_tab->ht_cnt_off[i - mcs0] += num_rate_diff; + soml_tab->pre_ht_cnt[i - mcs0] = soml_tab->ht_cnt[i - mcs0]; + num_bytes_diff = soml_tab->ht_byte[i - mcs0] - + soml_tab->pre_ht_byte[i - mcs0]; + soml_tab->ht_byte_off[i - mcs0] += num_bytes_diff; + soml_tab->pre_ht_byte[i - mcs0] = soml_tab->ht_byte[i - mcs0]; + } +} + +void phydm_soml_stats_vht_on(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 j, vht0; + u16 num_bytes_diff, num_rate_diff; + + vht0 = ODM_RATEVHTSS1MCS0; + for (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) { + num_rate_diff = soml_tab->vht_cnt[j - vht0] - + soml_tab->pre_vht_cnt[j - vht0]; + soml_tab->vht_cnt_on[j - vht0] += num_rate_diff; + soml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0]; + num_bytes_diff = soml_tab->vht_byte[j - vht0] - + soml_tab->pre_vht_byte[j - vht0]; + soml_tab->vht_byte_on[j - vht0] += num_bytes_diff; + soml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0]; + } +} + +void phydm_soml_stats_vht_off(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 j, vht0; + u16 num_bytes_diff, num_rate_diff; + + vht0 = ODM_RATEVHTSS1MCS0; + for (j = vht0; j <= ODM_RATEVHTSS2MCS9; j++) { + num_rate_diff = soml_tab->vht_cnt[j - vht0] - + soml_tab->pre_vht_cnt[j - vht0]; + soml_tab->vht_cnt_off[j - vht0] += num_rate_diff; + soml_tab->pre_vht_cnt[j - vht0] = soml_tab->vht_cnt[j - vht0]; + num_bytes_diff = soml_tab->vht_byte[j - vht0] - + soml_tab->pre_vht_byte[j - vht0]; + soml_tab->vht_byte_off[j - vht0] += num_bytes_diff; + soml_tab->pre_vht_byte[j - vht0] = soml_tab->vht_byte[j - vht0]; + } +} + +void phydm_soml_statistics(void *dm_void, u8 on_off_state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + if (on_off_state == SOML_ON) { + if (*dm->channel <= 14) + phydm_soml_stats_ht_on(dm); + if (dm->support_ic_type == ODM_RTL8822B) + phydm_soml_stats_vht_on(dm); + } else if (on_off_state == SOML_OFF) { + if (*dm->channel <= 14) + phydm_soml_stats_ht_off(dm); + if (dm->support_ic_type == ODM_RTL8822B) + phydm_soml_stats_vht_off(dm); + } +} + +void phydm_adsl_init_state(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + u8 next_on_off; + u16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0}; + u8 size = sizeof(ht_reset[0]); + + phydm_soml_reset_rx_rate(dm); + odm_move_memory(dm, soml_tab->ht_byte, ht_reset, + HT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->ht_byte_on, ht_reset, + HT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->ht_byte_off, ht_reset, + HT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->vht_byte, vht_reset, + VHT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->vht_byte_on, vht_reset, + VHT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->vht_byte_off, vht_reset, + VHT_RATE_IDX * size); + if (dm->support_ic_type == ODM_RTL8822B) { + soml_tab->cfo_cnt++; + phydm_soml_cfo_process(dm, + &soml_tab->cfo_diff_a, + &soml_tab->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", + soml_tab->cfo_cnt, soml_tab->cfo_diff_a, + soml_tab->cfo_diff_b); + soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a; + soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b; + } + + soml_tab->is_soml_method_enable = 1; + soml_tab->get_stats = false; + soml_tab->soml_state_cnt++; + next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_ON : SOML_OFF; + phydm_soml_on_off(dm, next_on_off); + odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer, + soml_tab->soml_delay_time); /*@ms*/ +} + +void phydm_adsl_odd_state(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u16 ht_reset[HT_RATE_IDX] = {0}, vht_reset[VHT_RATE_IDX] = {0}; + u8 size = sizeof(ht_reset[0]); + + soml_tab->get_stats = true; + soml_tab->soml_state_cnt++; + odm_move_memory(dm, soml_tab->pre_ht_cnt, soml_tab->ht_cnt, + HT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->pre_vht_cnt, soml_tab->vht_cnt, + VHT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->pre_ht_byte, soml_tab->ht_byte, + HT_RATE_IDX * size); + odm_move_memory(dm, soml_tab->pre_vht_byte, soml_tab->vht_byte, + VHT_RATE_IDX * size); + + if (dm->support_ic_type == ODM_RTL8822B) { + soml_tab->cfo_cnt++; + phydm_soml_cfo_process(dm, + &soml_tab->cfo_diff_a, + &soml_tab->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", + soml_tab->cfo_cnt, soml_tab->cfo_diff_a, + soml_tab->cfo_diff_b); + soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a; + soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b; + } + odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer, + soml_tab->soml_intvl); /*@ms*/ +} + +void phydm_adsl_even_state(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 next_on_off; + + soml_tab->get_stats = false; + if (dm->support_ic_type == ODM_RTL8822B) { + soml_tab->cfo_cnt++; + phydm_soml_cfo_process(dm, + &soml_tab->cfo_diff_a, + &soml_tab->cfo_diff_b); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ (%d) cfo_diff_a = %d KHz; cfo_diff_b = %d KHz ]\n", + soml_tab->cfo_cnt, soml_tab->cfo_diff_a, + soml_tab->cfo_diff_b); + soml_tab->cfo_diff_sum_a += soml_tab->cfo_diff_a; + soml_tab->cfo_diff_sum_b += soml_tab->cfo_diff_b; + } + soml_tab->soml_state_cnt++; + phydm_soml_statistics(dm, soml_tab->soml_on_off); + next_on_off = (soml_tab->soml_on_off == SOML_ON) ? SOML_OFF : SOML_ON; + phydm_soml_on_off(dm, next_on_off); + odm_set_timer(dm, &soml_tab->phydm_adaptive_soml_timer, + soml_tab->soml_delay_time); /*@ms*/ +} + +void phydm_adsl_decision_state(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + boolean on_above = false, off_above = false; + u8 i, max_idx_on = 0, max_idx_off = 0; + u8 next_on_off = soml_tab->soml_last_state; + u8 mcs0 = ODM_RATEMCS0, vht0 = ODM_RATEVHTSS1MCS0; + u8 crc_taget = soml_tab->soml_last_state; + u8 rate_num = 1, ss_shift = 0; + u16 ht_ok_max_on = 0, ht_fail_max_on = 0, utility_on = 0; + u16 ht_ok_max_off = 0, ht_fail_max_off = 0, utility_off = 0; + u16 vht_ok_max_on = 0, vht_fail_max_on = 0; + u16 vht_ok_max_off = 0, vht_fail_max_off = 0; + u16 num_total_qam = 0; + u16 cnt_max_on = 0, cnt_max_off = 0; + u32 ht_total_cnt_on = 0, ht_total_cnt_off = 0; + u32 total_ht_rate_on = 0, total_ht_rate_off = 0; + u32 vht_total_cnt_on = 0, vht_total_cnt_off = 0; + u32 total_vht_rate_on = 0, total_vht_rate_off = 0; + u32 rate_per_pkt_on = 0, rate_per_pkt_off = 0; + s32 cfo_diff_avg_a, cfo_diff_avg_b; + u16 vht_phy_rate_table[] = { + /*@20M*/ + 6, 13, 19, 26, 39, 52, 58, 65, 78, 90, /*@1SS MCS0~9*/ + 13, 26, 39, 52, 78, 104, 117, 130, 156, 180 /*@2SSMCS0~9*/ + }; + + if (dm->support_ic_type & ODM_IC_1SS) + rate_num = 1; + #ifdef PHYDM_COMPILE_ABOVE_2SS + else if (dm->support_ic_type & ODM_IC_2SS) + rate_num = 2; + #endif + #ifdef PHYDM_COMPILE_ABOVE_3SS + else if (dm->support_ic_type & ODM_IC_3SS) + rate_num = 3; + #endif + #ifdef PHYDM_COMPILE_ABOVE_4SS + else if (dm->support_ic_type & ODM_IC_4SS) + rate_num = 4; + #endif + else + pr_debug("%s: mismatch IC type %x\n", __func__, + dm->support_ic_type); + soml_tab->get_stats = false; + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[Decisoin state ]\n"); + phydm_soml_statistics(dm, soml_tab->soml_on_off); + if (*dm->channel <= 14) { + /* @[Search 1st and 2nd rate by counter] */ + for (i = 0; i < rate_num; i++) { + ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*ht_cnt_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_shift), (ss_shift + 7), + soml_tab->ht_cnt_on[ss_shift + 0], + soml_tab->ht_cnt_on[ss_shift + 1], + soml_tab->ht_cnt_on[ss_shift + 2], + soml_tab->ht_cnt_on[ss_shift + 3], + soml_tab->ht_cnt_on[ss_shift + 4], + soml_tab->ht_cnt_on[ss_shift + 5], + soml_tab->ht_cnt_on[ss_shift + 6], + soml_tab->ht_cnt_on[ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*ht_cnt_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_shift), (ss_shift + 7), + soml_tab->ht_cnt_off[ss_shift + 0], + soml_tab->ht_cnt_off[ss_shift + 1], + soml_tab->ht_cnt_off[ss_shift + 2], + soml_tab->ht_cnt_off[ss_shift + 3], + soml_tab->ht_cnt_off[ss_shift + 4], + soml_tab->ht_cnt_off[ss_shift + 5], + soml_tab->ht_cnt_off[ss_shift + 6], + soml_tab->ht_cnt_off[ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*ht_crc_ok_cnt_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_shift), (ss_shift + 7), + soml_tab->ht_crc_ok_cnt_on[ss_shift + 0], + soml_tab->ht_crc_ok_cnt_on[ss_shift + 1], + soml_tab->ht_crc_ok_cnt_on[ss_shift + 2], + soml_tab->ht_crc_ok_cnt_on[ss_shift + 3], + soml_tab->ht_crc_ok_cnt_on[ss_shift + 4], + soml_tab->ht_crc_ok_cnt_on[ss_shift + 5], + soml_tab->ht_crc_ok_cnt_on[ss_shift + 6], + soml_tab->ht_crc_ok_cnt_on[ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*ht_crc_fail_cnt_on HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_shift), (ss_shift + 7), + soml_tab->ht_crc_fail_cnt_on[ss_shift + 0], + soml_tab->ht_crc_fail_cnt_on[ss_shift + 1], + soml_tab->ht_crc_fail_cnt_on[ss_shift + 2], + soml_tab->ht_crc_fail_cnt_on[ss_shift + 3], + soml_tab->ht_crc_fail_cnt_on[ss_shift + 4], + soml_tab->ht_crc_fail_cnt_on[ss_shift + 5], + soml_tab->ht_crc_fail_cnt_on[ss_shift + 6], + soml_tab->ht_crc_fail_cnt_on[ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*ht_crc_ok_cnt_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_shift), (ss_shift + 7), + soml_tab->ht_crc_ok_cnt_off[ss_shift + 0], + soml_tab->ht_crc_ok_cnt_off[ss_shift + 1], + soml_tab->ht_crc_ok_cnt_off[ss_shift + 2], + soml_tab->ht_crc_ok_cnt_off[ss_shift + 3], + soml_tab->ht_crc_ok_cnt_off[ss_shift + 4], + soml_tab->ht_crc_ok_cnt_off[ss_shift + 5], + soml_tab->ht_crc_ok_cnt_off[ss_shift + 6], + soml_tab->ht_crc_ok_cnt_off[ss_shift + 7]); + } + + for (i = 0; i < rate_num; i++) { + ss_shift = (i << 3); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*ht_crc_fail_cnt_off HT MCS[%d :%d ] = {%d, %d, %d, %d, %d, %d, %d, %d}\n", + (ss_shift), (ss_shift + 7), + soml_tab->ht_crc_fail_cnt_off[ss_shift + 0], + soml_tab->ht_crc_fail_cnt_off[ss_shift + 1], + soml_tab->ht_crc_fail_cnt_off[ss_shift + 2], + soml_tab->ht_crc_fail_cnt_off[ss_shift + 3], + soml_tab->ht_crc_fail_cnt_off[ss_shift + 4], + soml_tab->ht_crc_fail_cnt_off[ss_shift + 5], + soml_tab->ht_crc_fail_cnt_off[ss_shift + 6], + soml_tab->ht_crc_fail_cnt_off[ss_shift + 7]); + } + for (i = ODM_RATEMCS0; i <= ODM_RATEMCS15; i++) { + ht_total_cnt_on += soml_tab->ht_cnt_on[i - mcs0]; + ht_total_cnt_off += soml_tab->ht_cnt_off[i - mcs0]; + total_ht_rate_on += (soml_tab->ht_cnt_on[i - mcs0] * + phy_rate_table[i]); + total_ht_rate_off += (soml_tab->ht_cnt_off[i - mcs0] * + phy_rate_table[i]); + if (soml_tab->ht_cnt_on[i - mcs0] > cnt_max_on) { + cnt_max_on = soml_tab->ht_cnt_on[i - mcs0]; + max_idx_on = i - mcs0; + } + + if (soml_tab->ht_cnt_off[i - mcs0] > cnt_max_off) { + cnt_max_off = soml_tab->ht_cnt_off[i - mcs0]; + max_idx_off = i - mcs0; + } + } + total_ht_rate_on = total_ht_rate_on << 3; + total_ht_rate_off = total_ht_rate_off << 3; + rate_per_pkt_on = (ht_total_cnt_on != 0) ? + (total_ht_rate_on / ht_total_cnt_on) : 0; + rate_per_pkt_off = (ht_total_cnt_off != 0) ? + (total_ht_rate_off / ht_total_cnt_off) : 0; + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + ht_ok_max_on = soml_tab->ht_crc_ok_cnt_on[max_idx_on]; + ht_fail_max_on = soml_tab->ht_crc_fail_cnt_on[max_idx_on]; + ht_ok_max_off = soml_tab->ht_crc_ok_cnt_off[max_idx_off]; + ht_fail_max_off = soml_tab->ht_crc_fail_cnt_off[max_idx_off]; + + if (ht_fail_max_on == 0) + ht_fail_max_on = 1; + + if (ht_fail_max_off == 0) + ht_fail_max_off = 1; + + if (ht_ok_max_on > ht_fail_max_on) + on_above = true; + + if (ht_ok_max_off > ht_fail_max_off) + off_above = true; + + if (on_above && !off_above) { + crc_taget = SOML_ON; + } else if (!on_above && off_above) { + crc_taget = SOML_OFF; + } else if (on_above && off_above) { + utility_on = (ht_ok_max_on << 7) / ht_fail_max_on; + utility_off = (ht_ok_max_off << 7) / ht_fail_max_off; + crc_taget = (utility_on == utility_off) ? + (soml_tab->soml_last_state) : + ((utility_on > utility_off) ? SOML_ON : + SOML_OFF); + + } else if (!on_above && !off_above) { + if (ht_ok_max_on == 0) + ht_ok_max_on = 1; + if (ht_ok_max_off == 0) + ht_ok_max_off = 1; + utility_on = (ht_fail_max_on << 7) / ht_ok_max_on; + utility_off = (ht_fail_max_off << 7) / ht_ok_max_off; + crc_taget = (utility_on == utility_off) ? + (soml_tab->soml_last_state) : + ((utility_on < utility_off) ? SOML_ON : + SOML_OFF); + } + #endif + } else if (dm->support_ic_type == ODM_RTL8822B) { + cfo_diff_avg_a = soml_tab->cfo_diff_sum_a / soml_tab->cfo_cnt; + cfo_diff_avg_b = soml_tab->cfo_diff_sum_b / soml_tab->cfo_cnt; + soml_tab->cfo_diff_avg_a = (soml_tab->cfo_cnt != 0) ? + cfo_diff_avg_a : 0; + soml_tab->cfo_diff_avg_b = (soml_tab->cfo_cnt != 0) ? + cfo_diff_avg_b : 0; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ cfo_diff_avg_a = %d KHz; cfo_diff_avg_b = %d KHz]\n", + soml_tab->cfo_diff_avg_a, + soml_tab->cfo_diff_avg_b); + for (i = 0; i < VHT_ORDER_TYPE; i++) + num_total_qam += soml_tab->num_vht_qam[i]; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ ((2SS)) BPSK_QPSK_count = %d ; 16QAM_count = %d ; 64QAM_count = %d ; 256QAM_count = %d ; num_total_qam = %d]\n", + soml_tab->num_vht_qam[BPSK_QPSK], + soml_tab->num_vht_qam[QAM16], + soml_tab->num_vht_qam[QAM64], + soml_tab->num_vht_qam[QAM256], + num_total_qam); + if (((soml_tab->num_vht_qam[QAM256] * 100) > + (num_total_qam * soml_tab->qam256_dist_th)) && + cfo_diff_avg_a > soml_tab->cfo_qam256_th && + cfo_diff_avg_b > soml_tab->cfo_qam256_th) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ QAM256_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", + soml_tab->qam256_dist_th, + soml_tab->cfo_qam256_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((soml_tab->num_vht_qam[QAM64] * 100) > + (num_total_qam * soml_tab->qam64_dist_th)) && + (cfo_diff_avg_a > soml_tab->cfo_qam64_th) && + (cfo_diff_avg_b > soml_tab->cfo_qam64_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ QAM64_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", + soml_tab->qam64_dist_th, + soml_tab->cfo_qam64_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((soml_tab->num_vht_qam[QAM16] * 100) > + (num_total_qam * soml_tab->qam16_dist_th)) && + (cfo_diff_avg_a > soml_tab->cfo_qam16_th) && + (cfo_diff_avg_b > soml_tab->cfo_qam16_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ QAM16_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", + soml_tab->qam16_dist_th, + soml_tab->cfo_qam16_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } else if (((soml_tab->num_vht_qam[BPSK_QPSK] * 100) > + (num_total_qam * soml_tab->bpsk_qpsk_dist_th)) && + (cfo_diff_avg_a > soml_tab->cfo_qpsk_th) && + (cfo_diff_avg_b > soml_tab->cfo_qpsk_th)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ BPSK_QPSK_ratio > %d ; cfo_diff_avg_a > %d KHz ==> SOML_OFF]\n", + soml_tab->bpsk_qpsk_dist_th, + soml_tab->cfo_qpsk_th); + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, SOML_OFF); + return; + } + + for (i = 0; i < rate_num; i++) { + ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ vht_cnt_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + soml_tab->vht_cnt_on[ss_shift + 0], + soml_tab->vht_cnt_on[ss_shift + 1], + soml_tab->vht_cnt_on[ss_shift + 2], + soml_tab->vht_cnt_on[ss_shift + 3], + soml_tab->vht_cnt_on[ss_shift + 4], + soml_tab->vht_cnt_on[ss_shift + 5], + soml_tab->vht_cnt_on[ss_shift + 6], + soml_tab->vht_cnt_on[ss_shift + 7], + soml_tab->vht_cnt_on[ss_shift + 8], + soml_tab->vht_cnt_on[ss_shift + 9]); + } + + for (i = 0; i < rate_num; i++) { + ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ vht_cnt_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d} ]\n", + (i + 1), + soml_tab->vht_cnt_off[ss_shift + 0], + soml_tab->vht_cnt_off[ss_shift + 1], + soml_tab->vht_cnt_off[ss_shift + 2], + soml_tab->vht_cnt_off[ss_shift + 3], + soml_tab->vht_cnt_off[ss_shift + 4], + soml_tab->vht_cnt_off[ss_shift + 5], + soml_tab->vht_cnt_off[ss_shift + 6], + soml_tab->vht_cnt_off[ss_shift + 7], + soml_tab->vht_cnt_off[ss_shift + 8], + soml_tab->vht_cnt_off[ss_shift + 9]); + } + + for (i = 0; i < rate_num; i++) { + ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*vht_crc_ok_cnt_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + soml_tab->vht_crc_ok_cnt_on[ss_shift + 0], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 1], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 2], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 3], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 4], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 5], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 6], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 7], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 8], + soml_tab->vht_crc_ok_cnt_on[ss_shift + 9]); + } + for (i = 0; i < rate_num; i++) { + ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*vht_crc_fail_cnt_on VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + soml_tab->vht_crc_fail_cnt_on[ss_shift + 0], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 1], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 2], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 3], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 4], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 5], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 6], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 7], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 8], + soml_tab->vht_crc_fail_cnt_on[ss_shift + 9]); + } + for (i = 0; i < rate_num; i++) { + ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*vht_crc_ok_cnt_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + soml_tab->vht_crc_ok_cnt_off[ss_shift + 0], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 1], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 2], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 3], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 4], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 5], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 6], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 7], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 8], + soml_tab->vht_crc_ok_cnt_off[ss_shift + 9]); + } + for (i = 0; i < rate_num; i++) { + ss_shift = 10 * i; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "*vht_crc_fail_cnt_off VHT-%d ss MCS[0:9] = {%d, %d, %d, %d, %d, %d, %d, %d, %d, %d}\n", + (i + 1), + soml_tab->vht_crc_fail_cnt_off[ss_shift + 0], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 1], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 2], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 3], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 4], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 5], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 6], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 7], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 8], + soml_tab->vht_crc_fail_cnt_off[ss_shift + 9]); + } + + for (i = ODM_RATEVHTSS2MCS0; i <= ODM_RATEVHTSS2MCS9; i++) { + vht_total_cnt_on += soml_tab->vht_cnt_on[i - vht0]; + vht_total_cnt_off += soml_tab->vht_cnt_off[i - vht0]; + total_vht_rate_on += (soml_tab->vht_cnt_on[i - vht0] * + vht_phy_rate_table[i - vht0]); + total_vht_rate_off += (soml_tab->vht_cnt_off[i - vht0] * + vht_phy_rate_table[i - vht0]); + + if (soml_tab->vht_cnt_on[i - vht0] > cnt_max_on) { + cnt_max_on = soml_tab->vht_cnt_on[i - vht0]; + max_idx_on = i - vht0; + } + + if (soml_tab->vht_cnt_off[i - vht0] > cnt_max_off) { + cnt_max_off = soml_tab->vht_cnt_off[i - vht0]; + max_idx_off = i - vht0; + } + } + total_vht_rate_on = total_vht_rate_on << 3; + total_vht_rate_off = total_vht_rate_off << 3; + rate_per_pkt_on = (vht_total_cnt_on != 0) ? + (total_vht_rate_on / vht_total_cnt_on) : 0; + rate_per_pkt_off = (vht_total_cnt_off != 0) ? + (total_vht_rate_off / vht_total_cnt_off) : 0; + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + vht_ok_max_on = soml_tab->vht_crc_ok_cnt_on[max_idx_on]; + vht_fail_max_on = soml_tab->vht_crc_fail_cnt_on[max_idx_on]; + vht_ok_max_off = soml_tab->vht_crc_ok_cnt_off[max_idx_off]; + vht_fail_max_off = soml_tab->vht_crc_fail_cnt_off[max_idx_off]; + + if (vht_fail_max_on == 0) + vht_fail_max_on = 1; + + if (vht_fail_max_off == 0) + vht_fail_max_off = 1; + + if (vht_ok_max_on > vht_fail_max_on) + on_above = true; + + if (vht_ok_max_off > vht_fail_max_off) + off_above = true; + + if (on_above && !off_above) { + crc_taget = SOML_ON; + } else if (!on_above && off_above) { + crc_taget = SOML_OFF; + } else if (on_above && off_above) { + utility_on = (vht_ok_max_on << 7) / vht_fail_max_on; + utility_off = (vht_ok_max_off << 7) / vht_fail_max_off; + crc_taget = (utility_on == utility_off) ? + (soml_tab->soml_last_state) : + ((utility_on > utility_off) ? SOML_ON : + SOML_OFF); + + } else if (!on_above && !off_above) { + if (vht_ok_max_on == 0) + vht_ok_max_on = 1; + if (vht_ok_max_off == 0) + vht_ok_max_off = 1; + utility_on = (vht_fail_max_on << 7) / vht_ok_max_on; + utility_off = (vht_fail_max_off << 7) / vht_ok_max_off; + crc_taget = (utility_on == utility_off) ? + (soml_tab->soml_last_state) : + ((utility_on < utility_off) ? SOML_ON : + SOML_OFF); + } + #endif + + } + + /* @[Decision] */ + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ rate_per_pkt_on = %d ; rate_per_pkt_off = %d ]\n", + rate_per_pkt_on, rate_per_pkt_off); + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (max_idx_on == max_idx_off && max_idx_on != 0) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ max_idx_on == max_idx_off ]\n"); + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ max_idx = %d, crc_utility_on = %d, crc_utility_off = %d, crc_target = %d]\n", + max_idx_on, utility_on, utility_off, + crc_taget); + next_on_off = crc_taget; + } else + #endif + if (rate_per_pkt_on > rate_per_pkt_off) { + next_on_off = SOML_ON; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ rate_per_pkt_on > rate_per_pkt_off ==> SOML_ON ]\n"); + } else if (rate_per_pkt_on < rate_per_pkt_off) { + next_on_off = SOML_OFF; + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ rate_per_pkt_on < rate_per_pkt_off ==> SOML_OFF ]\n"); + } else { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ stay at soml_last_state ]\n"); + next_on_off = soml_tab->soml_last_state; + } + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Final decisoin ] : "); + phydm_soml_on_off(dm, next_on_off); + soml_tab->soml_last_state = next_on_off; +} + +void phydm_adsl(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + if (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "soml_state_cnt =((%d))\n", + soml_tab->soml_state_cnt); + /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)===============*/ + if (soml_tab->soml_state_cnt < + (soml_tab->soml_train_num << 1)) { + if (soml_tab->soml_state_cnt == 0) + phydm_adsl_init_state(dm); + else if ((soml_tab->soml_state_cnt % 2) != 0) + phydm_adsl_odd_state(dm); + else if ((soml_tab->soml_state_cnt % 2) == 0) + phydm_adsl_even_state(dm); + } else { + phydm_adsl_decision_state(dm); + } + } +} + +void phydm_adaptive_soml_reset(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + soml_tab->soml_state_cnt = 0; + soml_tab->is_soml_method_enable = 0; + soml_tab->soml_counter = 0; +} + +void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) + return; + + if (val_len != 1) { + PHYDM_DBG(dm, ODM_COMP_API, "[Error][ADSL]Need val_len=1\n"); + return; + } + + phydm_soml_on_off(dm, (u8)val_buf[1]); +} + +void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 offset = 0; + + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) + return; + + if (!soml_tab->get_stats) + return; + if (length < 1400) + return; + + if (soml_tab->soml_on_off == SOML_ON) { + if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) { + offset = rate_id - ODM_RATEMCS0; + if (crc32 == CRC_OK) + soml_tab->ht_crc_ok_cnt_on[offset]++; + else if (crc32 == CRC_FAIL) + soml_tab->ht_crc_fail_cnt_on[offset]++; + } else if (rate_id >= ODM_RATEVHTSS1MCS0 && + rate_id <= ODM_RATEVHTSS2MCS9) { + offset = rate_id - ODM_RATEVHTSS1MCS0; + if (crc32 == CRC_OK) + soml_tab->vht_crc_ok_cnt_on[offset]++; + else if (crc32 == CRC_FAIL) + soml_tab->vht_crc_fail_cnt_on[offset]++; + } + } else if (soml_tab->soml_on_off == SOML_OFF) { + if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS15) { + offset = rate_id - ODM_RATEMCS0; + if (crc32 == CRC_OK) + soml_tab->ht_crc_ok_cnt_off[offset]++; + else if (crc32 == CRC_FAIL) + soml_tab->ht_crc_fail_cnt_off[offset]++; + } else if (rate_id >= ODM_RATEVHTSS1MCS0 && + rate_id <= ODM_RATEVHTSS2MCS9) { + offset = rate_id - ODM_RATEVHTSS1MCS0; + if (crc32 == CRC_OK) + soml_tab->vht_crc_ok_cnt_off[offset]++; + else if (crc32 == CRC_FAIL) + soml_tab->vht_crc_fail_cnt_off[offset]++; + } + } +} + +void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + u8 offset = 0; + + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) + return; + + if (rate_id >= ODM_RATEMCS0 && rate_id <= ODM_RATEMCS31) { + offset = rate_id - ODM_RATEMCS0; + if (offset > (HT_RATE_IDX - 1)) + offset = HT_RATE_IDX - 1; + + soml_tab->ht_byte[offset] += (u16)length; + } else if (rate_id >= ODM_RATEVHTSS1MCS0 && + rate_id <= ODM_RATEVHTSS4MCS9) { + offset = rate_id - ODM_RATEVHTSS1MCS0; + if (offset > (VHT_RATE_IDX - 1)) + offset = VHT_RATE_IDX - 1; + + soml_tab->vht_byte[offset] += (u16)length; + } +} + +#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) +static void pre_phydm_adaptive_soml_callback(unsigned long task_dm) +{ + struct dm_struct *dm = (struct dm_struct *)task_dm; + struct rtl8192cd_priv *priv = dm->priv; + struct priv_shared_info *pshare = priv->pshare; + + if (!(priv->drv_state & DRV_STATE_OPEN)) + return; + if (pshare->bDriverStopped || pshare->bSurpriseRemoved) { + printk("[%s] bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", + __FUNCTION__, pshare->bDriverStopped, + pshare->bSurpriseRemoved); + return; + } + + rtw_enqueue_timer_event(priv, &pshare->adaptive_soml_event, + ENQUEUE_TO_TAIL); +} + +void phydm_adaptive_soml_timers_usb(void *dm_void, u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + struct rtl8192cd_priv *priv = dm->priv; + + if (state == INIT_SOML_TIMMER) { + init_timer(&soml_tab->phydm_adaptive_soml_timer); + soml_tab->phydm_adaptive_soml_timer.data = (unsigned long)dm; + soml_tab->phydm_adaptive_soml_timer.function = pre_phydm_adaptive_soml_callback; + INIT_TIMER_EVENT_ENTRY(&priv->pshare->adaptive_soml_event, + phydm_adaptive_soml_callback, + (unsigned long)dm); + } else if (state == CANCEL_SOML_TIMMER) { + odm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer); + } else if (state == RELEASE_SOML_TIMMER) { + odm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer); + } +} +#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */ + +void phydm_adaptive_soml_timers(void *dm_void, u8 state) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + if (!(dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC)) + return; + +#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) + struct rtl8192cd_priv *priv = dm->priv; + + if (priv->hci_type == RTL_HCI_USB) { + phydm_adaptive_soml_timers_usb(dm_void, state); + } else +#endif /* defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) */ + { + if (state == INIT_SOML_TIMMER) { + odm_initialize_timer(dm, &soml_tab->phydm_adaptive_soml_timer, + (void *)phydm_adaptive_soml_callback, NULL, + "phydm_adaptive_soml_timer"); + } else if (state == CANCEL_SOML_TIMMER) { + odm_cancel_timer(dm, &soml_tab->phydm_adaptive_soml_timer); + } else if (state == RELEASE_SOML_TIMMER) { + odm_release_timer(dm, &soml_tab->phydm_adaptive_soml_timer); + } + } +} + +void phydm_adaptive_soml_init(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; +#if 0 + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[Return] Not Support Adaptive SOML\n"); + return; + } +#endif + + if (!(dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC)) + return; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "%s\n", __func__); + + soml_tab->soml_state_cnt = 0; + soml_tab->soml_delay_time = 40; + soml_tab->soml_intvl = 150; + soml_tab->soml_train_num = 4; + soml_tab->is_soml_method_enable = 0; + soml_tab->soml_counter = 0; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + soml_tab->soml_period = 1; +#else + soml_tab->soml_period = 4; +#endif + soml_tab->soml_select = 0; + soml_tab->cfo_cnt = 0; + soml_tab->cfo_diff_sum_a = 0; + soml_tab->cfo_diff_sum_b = 0; + + soml_tab->cfo_qpsk_th = 94; + soml_tab->cfo_qam16_th = 38; + soml_tab->cfo_qam64_th = 17; + soml_tab->cfo_qam256_th = 7; + + soml_tab->bpsk_qpsk_dist_th = 20; + soml_tab->qam16_dist_th = 20; + soml_tab->qam64_dist_th = 20; + soml_tab->qam256_dist_th = 20; + + if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) + odm_set_bb_reg(dm, 0x988, BIT(25), 1); +} + +void phydm_adaptive_soml(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + if (!(dm->support_ability & ODM_BB_ADAPTIVE_SOML)) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[Return!!!] Not Support Adaptive SOML Function\n"); + return; + } + + if (dm->pause_ability & ODM_BB_ADAPTIVE_SOML) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "Return: Pause ADSL in LV=%d\n", + dm->pause_lv_table.lv_adsl); + return; + } + + if (soml_tab->soml_counter < soml_tab->soml_period) { + soml_tab->soml_counter++; + return; + } + soml_tab->soml_counter = 0; + soml_tab->soml_state_cnt = 0; + soml_tab->cfo_cnt = 0; + soml_tab->cfo_diff_sum_a = 0; + soml_tab->cfo_diff_sum_b = 0; + + phydm_soml_reset_qam(dm); + + if (soml_tab->soml_select == 0) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, + "[ Adaptive SOML Training !!!]\n"); + } else if (soml_tab->soml_select == 1) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n"); + phydm_soml_on_off(dm, SOML_ON); + return; + } else if (soml_tab->soml_select == 2) { + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[ Stop Adaptive SOML !!!]\n"); + phydm_soml_on_off(dm, SOML_OFF); + return; + } + + if (dm->support_ic_type & PHYDM_ADAPTIVE_SOML_IC) + phydm_adsl(dm); +} + +void phydm_enable_adaptive_soml(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__); + dm->support_ability |= ODM_BB_ADAPTIVE_SOML; + phydm_soml_on_off(dm, SOML_ON); +} + +void phydm_stop_adaptive_soml(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + + PHYDM_DBG(dm, DBG_ADPTV_SOML, "[%s]\n", __func__); + dm->support_ability &= ~ODM_BB_ADAPTIVE_SOML; + phydm_soml_on_off(dm, SOML_ON); +} + +void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl, + u8 period, u8 delay_time) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct adaptive_soml *soml_tab = &dm->dm_soml_table; + + soml_tab->soml_train_num = train_num; + soml_tab->soml_intvl = intvl; + soml_tab->soml_period = period; + soml_tab->soml_delay_time = delay_time; +} +#endif /* @end of CONFIG_ADAPTIVE_SOML*/ + +void phydm_init_soft_ml_setting(void *dm_void) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + u32 soml_mask = BIT(31) | BIT(30) | BIT(29) | BIT(28); + +#if (RTL8822B_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8822B) { +#if 0 + /*odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd10a0000);*/ +#endif + phydm_somlrxhp_setting(dm, true); + dm->bsomlenabled = true; + } + } +#endif +#if (RTL8821C_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd); + } +#endif +#if (RTL8195B_SUPPORT == 1) + if (!*dm->mp_mode) { + if (dm->support_ic_type & ODM_RTL8195B) + odm_set_bb_reg(dm, R_0x19a8, soml_mask, 0xd); + } +#endif +} diff --git a/hal/phydm/phydm_soml.h b/hal/phydm/phydm_soml.h new file mode 100644 index 0000000..e2c6e17 --- /dev/null +++ b/hal/phydm/phydm_soml.h @@ -0,0 +1,199 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __PHYDMSOML_H__ +#define __PHYDMSOML_H__ + +/*@#define ADAPTIVE_SOML_VERSION "1.0" Byte counter version*/ +#define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/ + +#define PHYDM_ADAPTIVE_SOML_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F) +/*@jj add 20170822*/ + +#define INIT_SOML_TIMMER 0 +#define CANCEL_SOML_TIMMER 1 +#define RELEASE_SOML_TIMMER 2 + +#define SOML_RSSI_TH_HIGH 25 +#define SOML_RSSI_TH_LOW 20 + +#define HT_RATE_IDX 16 +#define VHT_RATE_IDX 20 + +#define HT_ORDER_TYPE 3 +#define VHT_ORDER_TYPE 4 + +#define CRC_FAIL 1 +#define CRC_OK 0 + +#if 0 +#define CFO_QPSK_TH 20 +#define CFO_QAM16_TH 20 +#define CFO_QAM64_TH 20 +#define CFO_QAM256_TH 20 + +#define BPSK_QPSK_DIST 20 +#define QAM16_DIST 30 +#define QAM64_DIST 30 +#define QAM256_DIST 20 +#endif +#define HT_TYPE 1 +#define VHT_TYPE 2 + +#define SOML_ON 1 +#define SOML_OFF 0 + +#ifdef CONFIG_ADAPTIVE_SOML + +struct adaptive_soml { + u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/ + boolean is_soml_method_enable; + boolean get_stats; + u8 soml_on_off; + u8 soml_state_cnt; + u8 soml_delay_time; + u8 soml_intvl; + u8 soml_train_num; + u8 soml_counter; + u8 soml_period; + u8 soml_select; + u8 soml_last_state; + u8 cfo_qpsk_th; + u8 cfo_qam16_th; + u8 cfo_qam64_th; + u8 cfo_qam256_th; + u8 bpsk_qpsk_dist_th; + u8 qam16_dist_th; + u8 qam64_dist_th; + u8 qam256_dist_th; + u8 cfo_cnt; + s32 cfo_diff_a; + s32 cfo_diff_b; + s32 cfo_diff_sum_a; + s32 cfo_diff_sum_b; + s32 cfo_diff_avg_a; + s32 cfo_diff_avg_b; + u16 ht_cnt[HT_RATE_IDX]; + u16 pre_ht_cnt[HT_RATE_IDX]; + u16 ht_cnt_on[HT_RATE_IDX]; + u16 ht_cnt_off[HT_RATE_IDX]; + u16 ht_crc_ok_cnt_on[HT_RATE_IDX]; + u16 ht_crc_fail_cnt_on[HT_RATE_IDX]; + u16 ht_crc_ok_cnt_off[HT_RATE_IDX]; + u16 ht_crc_fail_cnt_off[HT_RATE_IDX]; + u16 vht_crc_ok_cnt_on[VHT_RATE_IDX]; + u16 vht_crc_fail_cnt_on[VHT_RATE_IDX]; + u16 vht_crc_ok_cnt_off[VHT_RATE_IDX]; + u16 vht_crc_fail_cnt_off[VHT_RATE_IDX]; + + u16 vht_cnt[VHT_RATE_IDX]; + u16 pre_vht_cnt[VHT_RATE_IDX]; + u16 vht_cnt_on[VHT_RATE_IDX]; + u16 vht_cnt_off[VHT_RATE_IDX]; + + u16 num_ht_qam[HT_ORDER_TYPE]; + u16 ht_byte[HT_RATE_IDX]; + u16 pre_ht_byte[HT_RATE_IDX]; + u16 ht_byte_on[HT_RATE_IDX]; + u16 ht_byte_off[HT_RATE_IDX]; + u16 num_vht_qam[VHT_ORDER_TYPE]; + u16 vht_byte[VHT_RATE_IDX]; + u16 pre_vht_byte[VHT_RATE_IDX]; + u16 vht_byte_on[VHT_RATE_IDX]; + u16 vht_byte_off[VHT_RATE_IDX]; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM phydm_adaptive_soml_workitem; +#endif +#endif + struct phydm_timer_list phydm_adaptive_soml_timer; + +}; + +enum qam_order { + BPSK_QPSK = 0, + QAM16 = 1, + QAM64 = 2, + QAM256 = 3 +}; + +void phydm_dynamicsoftmletting(void *dm_void); + +void phydm_soml_on_off(void *dm_void, u8 swch); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_adaptive_soml_callback(struct phydm_timer_list *timer); + +void phydm_adaptive_soml_workitem_callback(void *context); + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +void phydm_adaptive_soml_callback(void *dm_void); + +void phydm_adaptive_soml_workitem_callback(void *context); + +#else +void phydm_adaptive_soml_callback(void *dm_void); +#endif + +void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void); + +void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void); + +void phydm_soml_reset_rx_rate(void *dm_void); + +void phydm_soml_reset_qam(void *dm_void); + +void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b); + +void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used, + char *output, u32 *_out_len); + +void phydm_soml_statistics(void *dm_void, u8 on_off_state); + +void phydm_adsl(void *dm_void); + +void phydm_adaptive_soml_reset(void *dm_void); + +void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len); + +void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length); + +void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length); + +void phydm_adaptive_soml_timers(void *dm_void, u8 state); + +void phydm_adaptive_soml_init(void *dm_void); + +void phydm_adaptive_soml(void *dm_void); + +void phydm_enable_adaptive_soml(void *dm_void); + +void phydm_stop_adaptive_soml(void *dm_void); + +void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl, + u8 period, u8 delay_time); +#endif +void phydm_init_soft_ml_setting(void *dm_void); +#endif /*@#ifndef __PHYDMSOML_H__*/ diff --git a/hal/phydm/phydm_types.h b/hal/phydm/phydm_types.h new file mode 100644 index 0000000..4db8da5 --- /dev/null +++ b/hal/phydm/phydm_types.h @@ -0,0 +1,413 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + +/*Define Different SW team support*/ +#define ODM_AP 0x01 /*BIT(0)*/ +#define ODM_CE 0x04 /*BIT(2)*/ +#define ODM_WIN 0x08 /*BIT(3)*/ +#define ODM_ADSL 0x10 +/*BIT(4)*/ /*already combine with ODM_AP, and is nouse now*/ +#define ODM_IOT 0x20 /*BIT(5)*/ + +/*For FW API*/ +#define __iram_odm_func__ +#define __odm_func__ +#define __odm_func_aon__ + +/*Deifne HW endian support*/ +#define ODM_ENDIAN_BIG 0 +#define ODM_ENDIAN_LITTLE 1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc)) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #define GET_PDM_ODM(__padapter) ((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv)) +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&__padapter->pshare->_dmODM)) +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) + #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) + /* enable PCI & USB HCI at the same time */ + #define RT_PCI_USB_INTERFACE 1 + #define RT_PCI_INTERFACE RT_PCI_USB_INTERFACE + #define RT_USB_INTERFACE RT_PCI_USB_INTERFACE + #define RT_SDIO_INTERFACE 3 + #else + #define RT_PCI_INTERFACE 1 + #define RT_USB_INTERFACE 2 + #define RT_SDIO_INTERFACE 3 + #endif +#endif + +enum hal_status { + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, +#if 0 + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +#endif +}; + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) + +#define VISTA_USB_RX_REVISE 0 + +/* + * Declare for ODM spin lock definition temporarily fro compile pass. + */ +enum rt_spinlock_type { + RT_TX_SPINLOCK = 1, + RT_RX_SPINLOCK = 2, + RT_RM_SPINLOCK = 3, + RT_CAM_SPINLOCK = 4, + RT_SCAN_SPINLOCK = 5, + RT_LOG_SPINLOCK = 7, + RT_BW_SPINLOCK = 8, + RT_CHNLOP_SPINLOCK = 9, + RT_RF_OPERATE_SPINLOCK = 10, + RT_INITIAL_SPINLOCK = 11, + RT_RF_STATE_SPINLOCK = 12, + /* For RF state. Added by Bruce, 2007-10-30. */ +#if VISTA_USB_RX_REVISE + RT_USBRX_CONTEXT_SPINLOCK = 13, + RT_USBRX_POSTPROC_SPINLOCK = 14, + /* protect data of adapter->IndicateW/ IndicateR */ +#endif + /* Shall we define Ndis 6.2 SpinLock Here ? */ + RT_PORT_SPINLOCK = 16, + RT_VNIC_SPINLOCK = 17, + RT_HVL_SPINLOCK = 18, + RT_H2C_SPINLOCK = 20, + /* For H2C cmd. Added by tynli. 2009.11.09. */ + + rt_bt_data_spinlock = 25, + + RT_WAPI_OPTION_SPINLOCK = 26, + RT_WAPI_RX_SPINLOCK = 27, + + /* add for 92D CCK control issue */ + RT_CCK_PAGEA_SPINLOCK = 28, + RT_BUFFER_SPINLOCK = 29, + RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, + RT_GEN_TEMP_BUF_SPINLOCK = 31, + RT_AWB_SPINLOCK = 32, + RT_FW_PS_SPINLOCK = 33, + RT_HW_TIMER_SPIN_LOCK = 34, + RT_MPT_WI_SPINLOCK = 35, + RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */ + RT_DBG_SPIN_LOCK = 37, + RT_IQK_SPINLOCK = 38, + RT_PENDED_OID_SPINLOCK = 39, + RT_CHNLLIST_SPINLOCK = 40, + RT_INDIC_SPINLOCK = 41, /* protect indication */ + RT_RFD_SPINLOCK = 42, + RT_SYNC_IO_CNT_SPINLOCK = 43, + RT_LAST_SPINLOCK, +}; + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define sta_info _RT_WLAN_STA + #define __func__ __FUNCTION__ + #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT + #define MASKH3BYTES 0xffffff00 + #define SUCCESS 0 + #define FAIL (-1) + + #define u8 u1Byte + #define s8 s1Byte + + #define u16 u2Byte + #define s16 s2Byte + + #define u32 u4Byte + #define s32 s4Byte + + #define u64 u8Byte + #define s64 s8Byte + + #define phydm_timer_list _RT_TIMER + + // for power limit table + enum odm_pw_lmt_regulation_type { + PW_LMT_REGU_FCC = 0, + PW_LMT_REGU_ETSI = 1, + PW_LMT_REGU_MKK = 2, + PW_LMT_REGU_WW13 = 3, + PW_LMT_REGU_IC = 4, + PW_LMT_REGU_KCC = 5, + PW_LMT_REGU_ACMA = 6, + PW_LMT_REGU_CHILE = 7, + PW_LMT_REGU_UKRAINE = 8, + PW_LMT_REGU_MEXICO = 9, + PW_LMT_REGU_CN = 10 + }; + + enum odm_pw_lmt_band_type { + PW_LMT_BAND_2_4G = 0, + PW_LMT_BAND_5G = 1 + }; + + enum odm_pw_lmt_bandwidth_type { + PW_LMT_BW_20M = 0, + PW_LMT_BW_40M = 1, + PW_LMT_BW_80M = 2, + PW_LMT_BW_160M = 3 + }; + + enum odm_pw_lmt_ratesection_type { + PW_LMT_RS_CCK = 0, + PW_LMT_RS_OFDM = 1, + PW_LMT_RS_HT = 2, + PW_LMT_RS_VHT = 3 + }; + + enum odm_pw_lmt_rfpath_type { + PW_LMT_PH_1T = 0, + PW_LMT_PH_2T = 1, + PW_LMT_PH_3T = 2, + PW_LMT_PH_4T = 3 + }; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../typedef.h" + + #ifdef CONFIG_PCI_HCI + #if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI) + #define DEV_BUS_TYPE RT_PCI_USB_INTERFACE + #else + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #endif + #endif + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif + + #define sta_info stat_info + #define boolean bool + + #define phydm_timer_list timer_list + #if defined(__ECOS) + #define s64 s8Byte + #endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) + + #include + + #define DEV_BUS_TYPE RT_PCI_INTERFACE + + #if defined(__LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined(__BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #error + #endif + + /* define useless flag to avoid compile warning */ + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + #define PHYDM_TESTCHIP_SUPPORT 0 + + + #define RATE_ADAPTIVE_SUPPORT 0 + #define POWER_TRAINING_ACTIVE 0 + + #define sta_info rtl_sta_info + #define boolean bool + + #define phydm_timer_list timer_list + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include + + #ifdef CONFIG_USB_HCI + #define DEV_BUS_TYPE RT_USB_INTERFACE + #elif defined(CONFIG_PCI_HCI) + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #elif defined(CONFIG_SDIO_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_GSPI_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #endif + + + #if defined(CONFIG_LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined(CONFIG_BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #endif + + #define boolean bool + + #define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value) + #define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value) + #define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value) + + /* define useless flag to avoid compile warning */ + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif + + #define phydm_timer_list rtw_timer_list + + // for power limit table + enum odm_pw_lmt_regulation_type { + PW_LMT_REGU_FCC = 0, + PW_LMT_REGU_ETSI = 1, + PW_LMT_REGU_MKK = 2, + PW_LMT_REGU_WW13 = 3, + PW_LMT_REGU_IC = 4, + PW_LMT_REGU_KCC = 5, + PW_LMT_REGU_ACMA = 6, + PW_LMT_REGU_CHILE = 7, + PW_LMT_REGU_UKRAINE = 8, + PW_LMT_REGU_MEXICO = 9, + PW_LMT_REGU_CN = 10 + }; + + enum odm_pw_lmt_band_type { + PW_LMT_BAND_2_4G = 0, + PW_LMT_BAND_5G = 1 + }; + + enum odm_pw_lmt_bandwidth_type { + PW_LMT_BW_20M = 0, + PW_LMT_BW_40M = 1, + PW_LMT_BW_80M = 2, + PW_LMT_BW_160M = 3 + }; + + enum odm_pw_lmt_ratesection_type { + PW_LMT_RS_CCK = 0, + PW_LMT_RS_OFDM = 1, + PW_LMT_RS_HT = 2, + PW_LMT_RS_VHT = 3 + }; + + enum odm_pw_lmt_rfpath_type { + PW_LMT_PH_1T = 0, + PW_LMT_PH_2T = 1, + PW_LMT_PH_3T = 2, + PW_LMT_PH_4T = 3 + }; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT) + #define boolean bool + #define true _TRUE + #define false _FALSE + + // for power limit table + enum odm_pw_lmt_regulation_type { + PW_LMT_REGU_NULL = 0, + PW_LMT_REGU_FCC = 1, + PW_LMT_REGU_ETSI = 2, + PW_LMT_REGU_MKK = 3, + PW_LMT_REGU_WW13 = 4 + }; + + enum odm_pw_lmt_band_type { + PW_LMT_BAND_NULL = 0, + PW_LMT_BAND_2_4G = 1, + PW_LMT_BAND_5G = 2 + }; + + enum odm_pw_lmt_bandwidth_type { + PW_LMT_BW_NULL = 0, + PW_LMT_BW_20M = 1, + PW_LMT_BW_40M = 2, + PW_LMT_BW_80M = 3 + }; + + enum odm_pw_lmt_ratesection_type { + PW_LMT_RS_NULL = 0, + PW_LMT_RS_CCK = 1, + PW_LMT_RS_OFDM = 2, + PW_LMT_RS_HT = 3, + PW_LMT_RS_VHT = 4 + }; + + enum odm_pw_lmt_rfpath_type { + PW_LMT_PH_NULL = 0, + PW_LMT_PH_1T = 1, + PW_LMT_PH_2T = 2, + PW_LMT_PH_3T = 3, + PW_LMT_PH_4T = 4 + }; + + #define phydm_timer_list timer_list + +#endif + +#define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0) +#define COND_ELSE 2 +#define COND_ENDIF 3 + +#define MASKBYTE0 0xff +#define MASKBYTE1 0xff00 +#define MASKBYTE2 0xff0000 +#define MASKBYTE3 0xff000000 +#define MASKHWORD 0xffff0000 +#define MASKLWORD 0x0000ffff +#define MASKDWORD 0xffffffff + +#define MASK7BITS 0x7f +#define MASK12BITS 0xfff +#define MASKH4BITS 0xf0000000 +#define MASK20BITS 0xfffff +#define MASK24BITS 0xffffff +#define MASKOFDM_D 0xffc00000 +#define MASKCCK 0x3f3f3f3f + +#define RFREGOFFSETMASK 0xfffff +#define RFREG_MASK 0xfffff + +#define MASKH3BYTES 0xffffff00 +#define MASKL3BYTES 0x00ffffff +#define MASKBYTE2HIGHNIBBLE 0x00f00000 +#define MASKBYTE3LOWNIBBLE 0x0f000000 +#define MASKL3BYTES 0x00ffffff + +#endif /* __ODM_TYPES_H__ */ diff --git a/hal/phydm/rtl8188e/hal8188erateadaptive.c b/hal/phydm/rtl8188e/hal8188erateadaptive.c new file mode 100644 index 0000000..0f9bc89 --- /dev/null +++ b/hal/phydm/rtl8188e/hal8188erateadaptive.c @@ -0,0 +1,1325 @@ +/****************************************************************************** + * + * Copyright(c) Semiconductor - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + +#if (RATE_ADAPTIVE_SUPPORT == 1) +/* rate adaptive parameters */ + +static u8 RETRY_PENALTY[PERENTRY][RETRYSIZE + 1] = {{5, 4, 3, 2, 0, 3}, /* 92 , idx=0 */ + {6, 5, 4, 3, 0, 4}, /* 86 , idx=1 */ + {6, 5, 4, 2, 0, 4}, /* 81 , idx=2 */ + {8, 7, 6, 4, 0, 6}, /* 75 , idx=3 */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + {10, 9, 7, 6, 0, 8}, /*71 , idx=4*/ + {10, 9, 7, 4, 0, 8}, /*66 , idx=5*/ +#else + {10, 9, 8, 6, 0, 8}, /* 71 , idx=4 */ + {10, 9, 8, 4, 0, 8}, /* 66 , idx=5 */ +#endif + {10, 9, 8, 2, 0, 8}, /* 62 , idx=6 */ + {10, 9, 8, 0, 0, 8}, /* 59 , idx=7 */ + {18, 17, 16, 8, 0, 16}, /* 53 , idx=8 */ + {26, 25, 24, 16, 0, 24}, /* 50 , idx=9 */ + {34, 33, 32, 24, 0, 32}, /* 47 , idx=0x0a */ + /* {34,33,32,16,0,32}, */ /* 43 , idx=0x0b */ + /* {34,33,32,8,0,32}, */ /* 40 , idx=0x0c */ + /* {34,33,28,8,0,32}, */ /* 37 , idx=0x0d */ + /* {34,33,20,8,0,32}, */ /* 32 , idx=0x0e */ + /* {34,32,24,8,0,32}, */ /* 26 , idx=0x0f */ + /* {49,48,32,16,0,48}, */ /* 20 , idx=0x10 */ + /* {49,48,24,0,0,48}, */ /* 17 , idx=0x11 */ + /* {49,47,16,16,0,48}, */ /* 15 , idx=0x12 */ + /* {49,44,16,16,0,48}, */ /* 12 , idx=0x13 */ + /* {49,40,16,0,0,48}, */ /* 9 , idx=0x14 */ + {34, 31, 28, 20, 0, 32}, /* 43 , idx=0x0b */ + {34, 31, 27, 18, 0, 32}, /* 40 , idx=0x0c */ + {34, 31, 26, 16, 0, 32}, /* 37 , idx=0x0d */ + {34, 30, 22, 16, 0, 32}, /* 32 , idx=0x0e */ + {34, 30, 24, 16, 0, 32}, /* 26 , idx=0x0f */ + {49, 46, 40, 16, 0, 48}, /* 20 , idx=0x10 */ + {49, 45, 32, 0, 0, 48}, /* 17 , idx=0x11 */ + {49, 45, 22, 18, 0, 48}, /* 15 , idx=0x12 */ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + {49, 40, 28, 18, 0, 48}, /* 12 , idx=0x13 */ + {49, 34, 20, 16, 0, 48}, /* 9 , idx=0x14 */ +#else + {49, 40, 24, 16, 0, 48}, /* 12 , idx=0x13 */ + {49, 32, 18, 12, 0, 48}, /* 9 , idx=0x14 */ +#endif + {49, 22, 18, 14, 0, 48}, /* 6 , idx=0x15 */ + {49, 16, 16, 0, 0, 48}}; + /* 3 */ /* 3, idx=0x16 */ + +static u8 RETRY_PENALTY_UP[RETRYSIZE + 1] = {49, 44, 16, 16, 0, 48}; /* 12% for rate up */ + +static u8 PT_PENALTY[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32}; + +#if 0 +static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{ + 4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */ + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f + }, /* 0329 R01 */ + { + 4, 4, 4, 5, 7, 7, 9, 9, 0x0c, 0x0e, 0x10, 0x12, /* SSTH */ +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + 4, 4, 4, 4, 0x0d, 0x0d, 0x0f, 0x0f, +#else + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, +#endif + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f}, /* 0329 R01 */ + { + 0x0a, 0x0a, 0x0a, 0x0a, 0x0c, 0x0c, 0x0e, 0x10, 0x11, 0x12, 0x12, 0x13, /* SSTH */ + 0x13, 0x13, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, + 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15}; + +static u8 RSSI_THRESHOLD[RATESIZE] = {0, 0, 0, 0, + 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a, + 0x17, 0x1a, 0x1c, 0x1f, 0x23, 0x28, 0x2a, 0x2c, + 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c}; +#else + +/* wilson modify */ +#if 0 +static u8 RETRY_PENALTY_IDX[2][RATESIZE] = {{ + 4, 4, 4, 5, 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */ + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f + }, /* 0329 R01 */ + { + 0x0a, 0x0a, 0x0b, 0x0c, 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x14, /* SSTH */ + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f}, /* 0329 R01 */ + { + 0x0a, 0x0a, 0x0b, 0x0c, 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13, /* SSTH */ + 0x0f, 0x10, 0x10, 0x12, 0x12, 0x13, 0x14, 0x15, + 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15}; + +static u8 RSSI_THRESHOLD[RATESIZE] = {0, 0, 0, 0, + 0, 0, 0, 0, 0, 0x24, 0x26, 0x2a, + 0x18, 0x1a, 0x1d, 0x1f, 0x21, 0x27, 0x29, 0x2a, + 0, 0, 0, 0x1f, 0x23, 0x28, 0x2a, 0x2c}; + +#endif + +/*static u8 RSSI_THRESHOLD[RATESIZE] = {0,0,0,0, + 0,0,0,0,0,0x24,0x26,0x2a, + 0x1a,0x1c,0x1e,0x21,0x24,0x2a,0x2b,0x2d, + 0,0,0,0x1f,0x23,0x28,0x2a,0x2c};*/ +/*static u16 N_THRESHOLD_HIGH[RATESIZE] = {4,4,8,16, + 24,36,48,72,96,144,192,216, + 60,80,100,160,240,400,560,640, + 300,320,480,720,1000,1200,1600,2000}; +static u16 N_THRESHOLD_LOW[RATESIZE] = {2,2,4,8, + 12,18,24,36,48,72,96,108, + 30,40,50,80,120,200,280,320, + 150,160,240,360,500,600,800,1000};*/ +static u16 N_THRESHOLD_HIGH[RATESIZE] = {4, 4, 8, 16, + 24, 36, 48, 72, 96, 144, 192, 216, + 60, 80, 100, 160, 240, 400, 600, 800, + 300, 320, 480, 720, 1000, 1200, 1600, 2000}; +static u16 N_THRESHOLD_LOW[RATESIZE] = {2, 2, 4, 8, + 12, 18, 24, 36, 48, 72, 96, 108, + 30, 40, 50, 80, 120, 200, 300, 400, + 150, 160, 240, 360, 500, 600, 800, 1000}; +static u8 TRYING_NECESSARY[RATESIZE] = {2, 2, 2, 2, + 2, 2, 3, 3, 4, 4, 5, 7, + 4, 4, 7, 10, 10, 12, 12, 18, + 5, 7, 7, 8, 11, 18, 36, 60}; + /* 0329 */ /* 1207 */ +#if 0 +static u8 POOL_RETRY_TH[RATESIZE] = {30, 30, 30, 30, + 30, 30, 25, 25, 20, 15, 15, 10, + 30, 25, 25, 20, 15, 10, 10, 10, + 30, 25, 25, 20, 15, 10, 10, 10 + }; +#endif + +static u8 DROPING_NECESSARY[RATESIZE] = {1, 1, 1, 1, + 1, 2, 3, 4, 5, 6, 7, 8, + 1, 2, 3, 4, 5, 6, 7, 8, + 5, 6, 7, 8, 9, 10, 11, 12}; + +static u32 INIT_RATE_FALLBACK_TABLE[16] = { + 0x0f8ff015, /* 0: 40M BGN mode */ + 0x0f8ff010, /* 1: 40M GN mode */ + 0x0f8ff005, /* 2: BN mode/ 40M BGN mode */ + 0x0f8ff000, /* 3: N mode */ + 0x00000ff5, /* 4: BG mode */ + 0x00000ff0, /* 5: G mode */ + 0x0000000d, /* 6: B mode */ + 0, /* 7: */ + 0, /* 8: */ + 0, /* 9: */ + 0, /* 10: */ + 0, /* 11: */ + 0, /* 12: */ + 0, /* 13: */ + 0, /* 14: */ + 0, /* 15: */ + +}; +static u8 pending_for_rate_up_fail[5] = {2, 10, 24, 40, 60}; +static u16 dynamic_tx_rpt_timing[6] = {0x186a, 0x30d4, 0x493e, 0x61a8, 0x7a12, 0x927c}; /*200ms-1200ms*/ + +/* End rate adaptive parameters */ + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) +static int +odm_ra_learn_bounding( + struct dm_struct *dm, + struct _odm_ra_info_ *p_ra_info) +{ + PHYDM_DBG(dm, DBG_RA, " %s\n", __func__); + if (DM_RA_RATE_UP != p_ra_info->rate_direction) { + /* Check if previous RA adjustment trend as +++--- or ++++----*/ + if (((3 == p_ra_info->rate_up_counter && p_ra_info->bounding_learning_time <= 10) || (4 == p_ra_info->rate_up_counter && p_ra_info->bounding_learning_time <= 16)) && p_ra_info->rate_up_counter == p_ra_info->rate_down_counter) { + if (1 != p_ra_info->bounding_type) { + p_ra_info->bounding_type = 1; + p_ra_info->bounding_counter = 0; + } + p_ra_info->bounding_counter++; + /* Check if previous RA adjustment trend as ++--*/ + } else if ((2 == p_ra_info->rate_up_counter) && (p_ra_info->bounding_learning_time <= 7) && (p_ra_info->rate_up_counter == p_ra_info->rate_down_counter)) { + if (2 != p_ra_info->bounding_type) { + p_ra_info->bounding_type = 2; + p_ra_info->bounding_counter = 0; + } + p_ra_info->bounding_counter++; + /* Check if previous RA adjustment trend as +++++-----*/ + } else if ((5 == p_ra_info->rate_up_counter) && (p_ra_info->bounding_learning_time <= 17) && (p_ra_info->rate_up_counter == p_ra_info->rate_down_counter)) { + if (3 != p_ra_info->bounding_type) { + p_ra_info->bounding_type = 3; + p_ra_info->bounding_counter = 0; + } + p_ra_info->bounding_counter++; + } else + p_ra_info->bounding_type = 0; + + p_ra_info->rate_down_counter = 0; + p_ra_info->rate_up_counter = 0; + p_ra_info->bounding_learning_time = 1; + } else if (p_ra_info->bounding_type) { + /* Check if RA adjustment trend as +++---++(+) or ++++----++(+)*/ + if ((1 == p_ra_info->bounding_type) && (1 == p_ra_info->bounding_counter) && (2 == p_ra_info->rate_up_counter)) { + p_ra_info->bounding_type = 0; + if (p_ra_info->bounding_learning_time <= 5) + return 1; + /* Check if RA adjustment trend as ++--++--+(+)*/ + } else if ((2 == p_ra_info->bounding_type) && (2 == p_ra_info->bounding_counter) && (1 == p_ra_info->rate_up_counter)) { + p_ra_info->bounding_type = 0; + if (p_ra_info->bounding_learning_time <= 2) + return 1; + /* Check if RA adjustment trend as +++++-----++(+)*/ + } else if ((3 == p_ra_info->bounding_type) && (1 == p_ra_info->bounding_counter) && (2 == p_ra_info->rate_up_counter)) { + p_ra_info->bounding_type = 0; + if (p_ra_info->bounding_learning_time <= 4) + return 1; + } + } + + return 0; +} +#endif + +static void +odm_set_tx_rpt_timing_8188e( + struct dm_struct *dm, + struct _odm_ra_info_ *p_ra_info, + u8 extend) +{ + u8 idx = 0; + + for (idx = 0; idx < 5; idx++) + if (dynamic_tx_rpt_timing[idx] == p_ra_info->rpt_time) + break; + + if (extend == 0) /* back to default timing */ + idx = 0; /* 200ms */ + else if (extend == 1) { /* increase the timing */ + idx += 1; + if (idx > 5) + idx = 5; + } else if (extend == 2) { /* decrease the timing */ + if (idx != 0) + idx -= 1; + } + p_ra_info->rpt_time = dynamic_tx_rpt_timing[idx]; + + PHYDM_DBG(dm, DBG_RA, "p_ra_info->rpt_time=0x%x\n", + p_ra_info->rpt_time); +} + +static int +odm_rate_down_8188e( + struct dm_struct *dm, + struct _odm_ra_info_ *p_ra_info) +{ + u8 rate_id, lowest_rate, highest_rate; + s8 i; + PHYDM_DBG(dm, DBG_RA, "=====>%s\n", __func__); + if (NULL == p_ra_info) { + PHYDM_DBG(dm, DBG_RA, "%s: p_ra_info is NULL\n", __func__); + return -1; + } + rate_id = p_ra_info->pre_rate; + lowest_rate = p_ra_info->lowest_rate; + highest_rate = p_ra_info->highest_rate; + PHYDM_DBG(dm, DBG_RA, + " rate_id=%d lowest_rate=%d highest_rate=%d rate_sgi=%d\n", + rate_id, lowest_rate, highest_rate, p_ra_info->rate_sgi); + if (rate_id > highest_rate) + rate_id = highest_rate; + else if (p_ra_info->rate_sgi) + p_ra_info->rate_sgi = 0; + else if (rate_id > lowest_rate) { + for (i = rate_id - 1; i >= lowest_rate; i--) { + if (p_ra_info->ra_use_rate & BIT(i)) { +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + u8 raup_cnt, learning_t, radn_t; + + raup_cnt = p_ra_info->rate_up_counter; + learning_t = p_ra_info->bounding_learning_time; + p_ra_info->rate_down_counter++; + p_ra_info->rate_direction = DM_RA_RATE_DOWN; + radn_t = p_ra_info->rate_down_start_time; + if (radn_t == 0xFF) { + if (raup_cnt == 0) + radn_t = 0; + else if (raup_cnt + 2 < learning_t) + radn_t = 0; + else + radn_t = learning_t; + } + p_ra_info->rate_down_start_time = radn_t; +#endif + rate_id = i; + goto rate_down_finish; + } + } + } else if (rate_id <= lowest_rate) + rate_id = lowest_rate; +rate_down_finish: +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + /*if (p_ra_info->RTY[2] >= 100) { + p_ra_info->ra_waiting_counter = 2; + p_ra_info->ra_pending_counter += 1; + } else */ if ((0 != p_ra_info->rate_down_start_time) && (0xFF != p_ra_info->rate_down_start_time)) { + /* Learning +(0)-(-)(-)+ and ++(0)--(-)(-)(0)+ after the persistence of learned TX rate expire*/ + if (p_ra_info->rate_down_counter < raup_cnt) { + } else if (p_ra_info->rate_down_counter == p_ra_info->rate_up_counter) { + p_ra_info->ra_waiting_counter = 2; + p_ra_info->ra_pending_counter += 1; + } else if (p_ra_info->rate_down_counter <= p_ra_info->rate_up_counter + 2) + rate_id = p_ra_info->pre_rate; + else { + p_ra_info->ra_waiting_counter = 0; + p_ra_info->ra_pending_counter = 0; + p_ra_info->rate_down_start_time = 0; + } + } else +#endif + if (p_ra_info->ra_waiting_counter == 1) { + p_ra_info->ra_waiting_counter += 1; + p_ra_info->ra_pending_counter += 1; + } else if (p_ra_info->ra_waiting_counter == 0) { + } else { + p_ra_info->ra_waiting_counter = 0; + p_ra_info->ra_pending_counter = 0; + } + + if (p_ra_info->ra_pending_counter >= 4) + p_ra_info->ra_pending_counter = 4; + p_ra_info->ra_drop_after_down = 1; + p_ra_info->decision_rate = rate_id; + odm_set_tx_rpt_timing_8188e(dm, p_ra_info, 2); + PHYDM_DBG(dm, DBG_RA, "rate down, Decrease RPT Timing\n"); + PHYDM_DBG(dm, DBG_RA, + "ra_waiting_counter %d, ra_pending_counter %d RADrop %d", + p_ra_info->ra_waiting_counter, p_ra_info->ra_pending_counter, + p_ra_info->ra_drop_after_down); + PHYDM_DBG(dm, DBG_RA, "rate down to rate_id %d rate_sgi %d\n", rate_id, + p_ra_info->rate_sgi); + PHYDM_DBG(dm, DBG_RA, "<=====%s\n", __func__); + return 0; +} + +static int +odm_rate_up_8188e( + struct dm_struct *dm, + struct _odm_ra_info_ *p_ra_info) +{ + u8 rate_id, highest_rate; + u8 i; + + PHYDM_DBG(dm, DBG_RA, "=====>%s\n", __func__); + if (NULL == p_ra_info) { + PHYDM_DBG(dm, DBG_RA, "%s: p_ra_info is NULL\n", __func__); + return -1; + } + rate_id = p_ra_info->pre_rate; + highest_rate = p_ra_info->highest_rate; + PHYDM_DBG(dm, DBG_RA, " rate_id=%d highest_rate=%d\n", rate_id, + highest_rate); + if (p_ra_info->ra_waiting_counter == 1) { + p_ra_info->ra_waiting_counter = 0; + p_ra_info->ra_pending_counter = 0; + } else if (p_ra_info->ra_waiting_counter > 1) { + p_ra_info->pre_rssi_sta_ra = p_ra_info->rssi_sta_ra; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + p_ra_info->rate_down_start_time = 0; +#endif + goto rate_up_finish; + } + odm_set_tx_rpt_timing_8188e(dm, p_ra_info, 0); + PHYDM_DBG(dm, DBG_RA, "%s: default RPT Timing\n", __func__); + + if (rate_id < highest_rate) { + for (i = rate_id + 1; i <= highest_rate; i++) { + if (p_ra_info->ra_use_rate & BIT(i)) { +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if (odm_ra_learn_bounding(dm, p_ra_info)) { + p_ra_info->ra_waiting_counter = 2; + p_ra_info->ra_pending_counter = 1; + goto rate_up_finish; + } + p_ra_info->rate_up_counter++; + p_ra_info->rate_direction = DM_RA_RATE_UP; +#endif + rate_id = i; + goto rate_up_finish; + } + } + } else if (rate_id == highest_rate) { + if (p_ra_info->sgi_enable && p_ra_info->rate_sgi != 1) + p_ra_info->rate_sgi = 1; + else if ((p_ra_info->sgi_enable) != 1) + p_ra_info->rate_sgi = 0; + } else /* if((sta_info_ra->Decision_rate) > (sta_info_ra->Highest_rate)) */ + rate_id = highest_rate; + +rate_up_finish: + /* if(p_ra_info->ra_waiting_counter==10) */ + if (p_ra_info->ra_waiting_counter == (4 + pending_for_rate_up_fail[p_ra_info->ra_pending_counter])) { + p_ra_info->ra_waiting_counter = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + /* Mark persistence expiration state*/ + p_ra_info->rate_down_start_time = 0xFF; + /* Clear state to avoid wrong bounding check*/ + p_ra_info->rate_down_counter = 0; + p_ra_info->rate_up_counter = 0; + p_ra_info->rate_direction = 0; +#endif + } else + p_ra_info->ra_waiting_counter++; + + p_ra_info->decision_rate = rate_id; + PHYDM_DBG(dm, DBG_RA, "rate up to rate_id %d\n", rate_id); + PHYDM_DBG(dm, DBG_RA, "ra_waiting_counter %d, ra_pending_counter %d", + p_ra_info->ra_waiting_counter, p_ra_info->ra_pending_counter); + PHYDM_DBG(dm, DBG_RA, "<=====%s\n", __func__); + return 0; +} + +static void odm_reset_ra_counter_8188e(struct _odm_ra_info_ *p_ra_info) +{ + u8 rate_id; + rate_id = p_ra_info->decision_rate; + p_ra_info->nsc_up = (N_THRESHOLD_HIGH[rate_id] + N_THRESHOLD_LOW[rate_id]) >> 1; + p_ra_info->nsc_down = (N_THRESHOLD_HIGH[rate_id] + N_THRESHOLD_LOW[rate_id]) >> 1; +} + +static void +odm_rate_decision_8188e( + struct dm_struct *dm, + struct _odm_ra_info_ *p_ra_info, + u8 mac_id) +{ + u8 rate_id = 0, rty_pt_id = 0, penalty_id1 = 0, penalty_id2 = 0; + static u8 dynamic_tx_rpt_timing_counter = 0; + u8 cmd_buf[3]; + + PHYDM_DBG(dm, DBG_RA, "%s ======>\n", __func__); + + if (p_ra_info->active && p_ra_info->TOTAL > 0) { /* STA used and data packet exits */ + +#if AP_USB_SDIO + if ((p_ra_info->rssi_sta_ra <= 17 && p_ra_info->rssi_sta_ra > p_ra_info->pre_rssi_sta_ra) || (p_ra_info->pre_rssi_sta_ra <= 17 && p_ra_info->pre_rssi_sta_ra > p_ra_info->rssi_sta_ra)) { + /* don't reset state in low signal due to the power different between CCK and MCS is large.*/ + } else +#endif + if (p_ra_info->ra_drop_after_down) { + p_ra_info->ra_drop_after_down--; + odm_reset_ra_counter_8188e(p_ra_info); + return; + } + if ((p_ra_info->rssi_sta_ra < (p_ra_info->pre_rssi_sta_ra - 3)) || (p_ra_info->rssi_sta_ra > (p_ra_info->pre_rssi_sta_ra + 3))) { + p_ra_info->pre_rssi_sta_ra = p_ra_info->rssi_sta_ra; + p_ra_info->ra_waiting_counter = 0; + p_ra_info->ra_pending_counter = 0; +#if AP_USB_SDIO + p_ra_info->bounding_type = 0; +#endif + } + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + if (dm->priv->pshare->rf_ft_var.txforce != 0xff) { + p_ra_info->pre_rate = dm->priv->pshare->rf_ft_var.txforce; + odm_reset_ra_counter_8188e(p_ra_info); + } +#endif + + /* Start RA decision */ + if (p_ra_info->pre_rate > p_ra_info->highest_rate) + rate_id = p_ra_info->highest_rate; + else + rate_id = p_ra_info->pre_rate; + + if (p_ra_info->rssi_sta_ra > RSSI_THRESHOLD[rate_id]) + rty_pt_id = 0; + else + rty_pt_id = 1; + + penalty_id1 = RETRY_PENALTY_IDX[rty_pt_id][rate_id]; /* TODO by page */ + + PHYDM_DBG(dm, DBG_RA, "nsc_down=%d\n", p_ra_info->nsc_down); + + p_ra_info->nsc_down += p_ra_info->RTY[0] * RETRY_PENALTY[penalty_id1][0]; + p_ra_info->nsc_down += p_ra_info->RTY[1] * RETRY_PENALTY[penalty_id1][1]; + p_ra_info->nsc_down += p_ra_info->RTY[2] * RETRY_PENALTY[penalty_id1][2]; + p_ra_info->nsc_down += p_ra_info->RTY[3] * RETRY_PENALTY[penalty_id1][3]; + p_ra_info->nsc_down += p_ra_info->RTY[4] * RETRY_PENALTY[penalty_id1][4]; + + PHYDM_DBG(dm, DBG_RA, " nsc_down=%d, total*penalty[5]=%d\n", + p_ra_info->nsc_down, + (p_ra_info->TOTAL * RETRY_PENALTY[penalty_id1][5])); + + if (p_ra_info->nsc_down > (p_ra_info->TOTAL * RETRY_PENALTY[penalty_id1][5])) + p_ra_info->nsc_down -= p_ra_info->TOTAL * RETRY_PENALTY[penalty_id1][5]; + else + p_ra_info->nsc_down = 0; + + /* rate up */ + penalty_id2 = RETRY_PENALTY_UP_IDX[rate_id]; + + PHYDM_DBG(dm, DBG_RA, " nsc_up=%d\n", p_ra_info->nsc_up); + + p_ra_info->nsc_up += p_ra_info->RTY[0] * RETRY_PENALTY[penalty_id2][0]; + p_ra_info->nsc_up += p_ra_info->RTY[1] * RETRY_PENALTY[penalty_id2][1]; + p_ra_info->nsc_up += p_ra_info->RTY[2] * RETRY_PENALTY[penalty_id2][2]; + p_ra_info->nsc_up += p_ra_info->RTY[3] * RETRY_PENALTY[penalty_id2][3]; + p_ra_info->nsc_up += p_ra_info->RTY[4] * RETRY_PENALTY[penalty_id2][4]; + + PHYDM_DBG(dm, DBG_RA, "nsc_up=%d, total*up[5]=%d\n", + p_ra_info->nsc_up, + (p_ra_info->TOTAL * RETRY_PENALTY[penalty_id2][5])); + + if (p_ra_info->nsc_up > (p_ra_info->TOTAL * RETRY_PENALTY[penalty_id2][5])) + p_ra_info->nsc_up -= p_ra_info->TOTAL * RETRY_PENALTY[penalty_id2][5]; + else + p_ra_info->nsc_up = 0; + + PHYDM_DBG(dm, DBG_RA | ODM_COMP_INIT, + " RssiStaRa= %d rty_pt_id=%d penalty_id1=0x%x penalty_id2=0x%x rate_id=%d nsc_down=%d nsc_up=%d SGI=%d\n", + p_ra_info->rssi_sta_ra, rty_pt_id, penalty_id1, + penalty_id2, rate_id, p_ra_info->nsc_down, + p_ra_info->nsc_up, p_ra_info->rate_sgi); + +#if AP_USB_SDIO + if (0xFF != p_ra_info->bounding_learning_time) + p_ra_info->bounding_learning_time++; +#endif + + if ((p_ra_info->nsc_down < N_THRESHOLD_LOW[rate_id]) || (p_ra_info->DROP > DROPING_NECESSARY[rate_id])) + odm_rate_down_8188e(dm, p_ra_info); + /* else if ((p_ra_info->nsc_up > N_THRESHOLD_HIGH[rate_id])&&(pool_retrynsc_up > N_THRESHOLD_HIGH[rate_id]) + odm_rate_up_8188e(dm, p_ra_info); + +#if AP_USB_SDIO + else if ((p_ra_info->RTY[2] >= 100) && (*dm->band_width == CHANNEL_WIDTH_20)) + odm_rate_down_8188e(dm, p_ra_info); +#endif + + if (p_ra_info->decision_rate == p_ra_info->pre_rate) { + PHYDM_DBG(dm, DBG_RA, + "[Rate stay] macid=%d, dec_rate=0x%x, pre_rate=0x%x\n", + mac_id, p_ra_info->decision_rate, + p_ra_info->pre_rate); + dynamic_tx_rpt_timing_counter += 1; + } else { /*rate update*/ + + PHYDM_DBG(dm, DBG_RA, + "[Rate update] macid=%d, dec_rate=0x%x, pre_rate=0x%x\n", + mac_id, p_ra_info->decision_rate, + p_ra_info->pre_rate); + dynamic_tx_rpt_timing_counter = 0; + /*update rate information*/ + cmd_buf[0] = (p_ra_info->rate_sgi << 7) | (p_ra_info->decision_rate & 0x7f); + cmd_buf[1] = mac_id; + phydm_c2h_ra_report_handler(dm, &(cmd_buf[0]), 3); + } + + if (dynamic_tx_rpt_timing_counter >= 4) { + odm_set_tx_rpt_timing_8188e(dm, p_ra_info, 1); + PHYDM_DBG(dm, DBG_RA, + "<=====rate don't change 4 times, Extend RPT Timing\n"); + dynamic_tx_rpt_timing_counter = 0; + } + + p_ra_info->pre_rate = p_ra_info->decision_rate; + + odm_reset_ra_counter_8188e(p_ra_info); + } + PHYDM_DBG(dm, DBG_RA, "RA end\n"); +} + +static int +odm_arfb_refresh_8188e( + struct dm_struct *dm, + struct _odm_ra_info_ *p_ra_info) +{ + /* Wilson 2011/10/26 */ + u32 mask_from_reg; + u8 i; + + switch (p_ra_info->rate_id) { + case RATR_INX_WIRELESS_NGB: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & 0x0f8fe00f; + break; + case RATR_INX_WIRELESS_NG: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & 0x0f8ff010; + break; + case RATR_INX_WIRELESS_NB: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & 0x0f8fe00f; + break; + case RATR_INX_WIRELESS_N: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & 0x0f8ff000; + break; + case RATR_INX_WIRELESS_GB: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & 0x00000fef; + break; + case RATR_INX_WIRELESS_G: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & 0x00000ff0; + break; + case RATR_INX_WIRELESS_B: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & 0x0000000d; + break; + case 12: + mask_from_reg = odm_read_4byte(dm, REG_ARFR0); + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & mask_from_reg; + break; + case 13: + mask_from_reg = odm_read_4byte(dm, REG_ARFR1); + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & mask_from_reg; + break; + case 14: + mask_from_reg = odm_read_4byte(dm, REG_ARFR2); + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & mask_from_reg; + break; + case 15: + mask_from_reg = odm_read_4byte(dm, REG_ARFR3); + p_ra_info->ra_use_rate = (p_ra_info->rate_mask) & mask_from_reg; + break; + + default: + p_ra_info->ra_use_rate = (p_ra_info->rate_mask); + break; + } + /* Highest rate */ + p_ra_info->highest_rate = 0; + for (i = RATESIZE; i > 0; i--) { + if (p_ra_info->ra_use_rate & BIT(i)) { + p_ra_info->highest_rate = i; + break; + } + } + + /* Lowest rate */ + p_ra_info->lowest_rate = 0; + for (i = 0; i < RATESIZE; i++) { + if (p_ra_info->ra_use_rate & BIT(i)) { + p_ra_info->lowest_rate = i; + break; + } + } + +#if POWER_TRAINING_ACTIVE == 1 + if (p_ra_info->highest_rate > 0x13) + p_ra_info->pt_mode_ss = 3; + else if (p_ra_info->highest_rate > 0x0b) + p_ra_info->pt_mode_ss = 2; + else if (p_ra_info->highest_rate > 0x0b) + p_ra_info->pt_mode_ss = 1; + else + p_ra_info->pt_mode_ss = 0; + PHYDM_DBG(dm, DBG_RA, "ODM_ARFBRefresh_8188E(): pt_mode_ss=%d\n", + p_ra_info->pt_mode_ss); + +#endif + PHYDM_DBG(dm, DBG_RA, + "ODM_ARFBRefresh_8188E(): rate_id=%d rate_mask=%8.8x ra_use_rate=%8.8x highest_rate=%d\n", + p_ra_info->rate_id, p_ra_info->rate_mask, + p_ra_info->ra_use_rate, p_ra_info->highest_rate); + return 0; +} + +#if POWER_TRAINING_ACTIVE == 1 +static void +odm_pt_try_state_8188e( + struct dm_struct *dm, + struct _odm_ra_info_ *p_ra_info) +{ + p_ra_info->pt_try_state = 0; + switch (p_ra_info->pt_mode_ss) { + case 3: + if (p_ra_info->decision_rate >= 0x19) + p_ra_info->pt_try_state = 1; + break; + case 2: + if (p_ra_info->decision_rate >= 0x11) + p_ra_info->pt_try_state = 1; + break; + case 1: + if (p_ra_info->decision_rate >= 0x0a) + p_ra_info->pt_try_state = 1; + break; + case 0: + if (p_ra_info->decision_rate >= 0x03) + p_ra_info->pt_try_state = 1; + break; + default: + p_ra_info->pt_try_state = 0; + } + + if (p_ra_info->rssi_sta_ra < 48) + p_ra_info->pt_stage = 0; + else if (p_ra_info->pt_try_state == 1) { + if (p_ra_info->pt_stop_count >= 10 || (p_ra_info->pt_pre_rssi > p_ra_info->rssi_sta_ra + 5) || (p_ra_info->pt_pre_rssi < p_ra_info->rssi_sta_ra - 5) || p_ra_info->decision_rate != p_ra_info->pt_pre_rate) { + if (p_ra_info->pt_stage == 0) + p_ra_info->pt_stage = 1; + else if (p_ra_info->pt_stage == 1) + p_ra_info->pt_stage = 3; + else + p_ra_info->pt_stage = 5; + + p_ra_info->pt_pre_rssi = p_ra_info->rssi_sta_ra; + p_ra_info->pt_stop_count = 0; + + } else { + p_ra_info->ra_stage = 0; + p_ra_info->pt_stop_count++; + } + } else { + p_ra_info->pt_stage = 0; + p_ra_info->ra_stage = 0; + } + p_ra_info->pt_pre_rate = p_ra_info->decision_rate; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + /* Disable power training when noisy environment */ + if (dm->is_disable_power_training) { + PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable pow train when noisy\n"); + p_ra_info->pt_stage = 0; + p_ra_info->ra_stage = 0; + p_ra_info->pt_stop_count = 0; + } +#endif +} + +static void +odm_pt_decision_8188e( + struct _odm_ra_info_ *p_ra_info) +{ + u8 stage_BUF; + u8 j; + u8 temp_stage; + u32 numsc; + u32 num_total; + u8 stage_id; + + stage_BUF = p_ra_info->pt_stage; + numsc = 0; + num_total = p_ra_info->TOTAL * PT_PENALTY[5]; + for (j = 0; j <= 4; j++) { + numsc += p_ra_info->RTY[j] * PT_PENALTY[j]; + if (numsc > num_total) + break; + } + + j = j >> 1; + temp_stage = (p_ra_info->pt_stage + 1) >> 1; + if (temp_stage > j) + stage_id = temp_stage - j; + else + stage_id = 0; + + p_ra_info->pt_smooth_factor = (p_ra_info->pt_smooth_factor >> 1) + (p_ra_info->pt_smooth_factor >> 2) + stage_id * 16 + 2; + if (p_ra_info->pt_smooth_factor > 192) + p_ra_info->pt_smooth_factor = 192; + stage_id = p_ra_info->pt_smooth_factor >> 6; + temp_stage = stage_id * 2; + if (temp_stage != 0) + temp_stage -= 1; + if (p_ra_info->DROP > 3) + temp_stage = 0; + p_ra_info->pt_stage = temp_stage; +} +#endif + +static void +odm_ra_tx_rpt_timer_setting( + struct dm_struct *dm, + u16 min_rpt_time) +{ + PHYDM_DBG(dm, DBG_RA, " =====>%s\n", __func__); + + if (dm->currmin_rpt_time != min_rpt_time) { + PHYDM_DBG(dm, DBG_RA, + " currmin_rpt_time =0x%04x min_rpt_time=0x%04x\n", + dm->currmin_rpt_time, min_rpt_time); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) + odm_ra_set_tx_rpt_time(dm, min_rpt_time); +#else + rtw_rpt_timer_cfg_cmd(dm->adapter, min_rpt_time); +#endif + dm->currmin_rpt_time = min_rpt_time; + } + PHYDM_DBG(dm, DBG_RA, " <=====%s\n", __func__); +} + +void odm_ra_support_init(struct dm_struct *dm) +{ + PHYDM_DBG(dm, DBG_RA, "=====>%s\n", __func__); + + /* 2012/02/14 MH Be noticed, the init must be after IC type is recognized!!!!! */ + if (dm->support_ic_type == ODM_RTL8188E) + dm->ra_support88e = true; +} + +void phydm_tx_stats_rst(struct dm_struct *dm) +{ + struct _phydm_txstatistic_ *tx_stats = NULL; + tx_stats = &(dm->hw_stats); + tx_stats->hw_total_tx = 0; + tx_stats->hw_tx_drop = 0; + tx_stats->hw_tx_rty = 0; + tx_stats->hw_tx_success = 0; +} + +int odm_ra_info_init(struct dm_struct *dm, u32 mac_id) +{ + struct _odm_ra_info_ *p_ra_info = &dm->ra_info[mac_id]; + + p_ra_info->decision_rate = ODM_RATEMCS7; + p_ra_info->pre_rate = ODM_RATEMCS7; + p_ra_info->highest_rate = ODM_RATEMCS7; + p_ra_info->lowest_rate = 0; + p_ra_info->rate_id = 0; + p_ra_info->rate_mask = 0xffffffff; + p_ra_info->rssi_sta_ra = 0; + p_ra_info->pre_rssi_sta_ra = 0; + p_ra_info->sgi_enable = 0; + p_ra_info->ra_use_rate = 0xffffffff; + p_ra_info->nsc_down = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2; + p_ra_info->nsc_up = (N_THRESHOLD_HIGH[0x13] + N_THRESHOLD_LOW[0x13]) / 2; + p_ra_info->rate_sgi = 0; + p_ra_info->active = 1; /* active is not used at present. by page, 110819 */ + p_ra_info->rpt_time = 0x927c; + p_ra_info->DROP = 0; + p_ra_info->RTY[0] = 0; + p_ra_info->RTY[1] = 0; + p_ra_info->RTY[2] = 0; + p_ra_info->RTY[3] = 0; + p_ra_info->RTY[4] = 0; + p_ra_info->TOTAL = 0; + p_ra_info->ra_waiting_counter = 0; + p_ra_info->ra_pending_counter = 0; + p_ra_info->ra_drop_after_down = 0; +#if POWER_TRAINING_ACTIVE == 1 + p_ra_info->pt_active = 1; /* active when this STA is use */ + p_ra_info->pt_try_state = 0; + p_ra_info->pt_stage = 5; /* Need to fill into HW_PWR_STATUS */ + p_ra_info->pt_smooth_factor = 192; + p_ra_info->pt_stop_count = 0; + p_ra_info->pt_pre_rate = 0; + p_ra_info->pt_pre_rssi = 0; + p_ra_info->pt_mode_ss = 0; + p_ra_info->ra_stage = 0; +#endif +#if AP_USB_SDIO + p_ra_info->rate_down_counter = 0; + p_ra_info->rate_up_counter = 0; + p_ra_info->rate_direction = 0; + p_ra_info->bounding_type = 0; + p_ra_info->bounding_counter = 0; + p_ra_info->bounding_learning_time = 0; + p_ra_info->rate_down_start_time = 0; +#endif + return 0; +} + +void odm_ra_info_init_all(struct dm_struct *dm) +{ + u32 mac_id = 0; + + if (dm->support_ic_type != ODM_RTL8188E) + return; + + PHYDM_DBG(dm, DBG_RA, "=====>\n"); + dm->currmin_rpt_time = 0; + + for (mac_id = 0; mac_id < ODM_ASSOCIATE_ENTRY_NUM; mac_id++) + odm_ra_info_init(dm, mac_id); + + /* Init Tx stats*/ + phydm_tx_stats_rst(dm); + + /* Redifine arrays for I-cut NIC */ + if (dm->cut_version == ODM_CUT_I) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + u8 i; + u8 RETRY_PENALTY_IDX_S[2][RATESIZE] = {{4, 4, 4, 5, + 4, 4, 5, 7, 7, 7, 8, 0x0a, /* SS>TH */ + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f}, /* 0329 R01 */ + { + 0x0a, 0x0a, 0x0b, 0x0c, + 0x0a, 0x0a, 0x0b, 0x0c, 0x0d, 0x10, 0x13, 0x13, /* SSTH */ + 0x0b, 0x0b, 0x11, 0x11, 0x12, 0x12, 0x12, 0x12, + 0x11, 0x11, 0x12, 0x13, 0x13, 0x13, 0x14, 0x15}; + + for (i = 0; i < RATESIZE; i++) { + RETRY_PENALTY_IDX[0][i] = RETRY_PENALTY_IDX_S[0][i]; + RETRY_PENALTY_IDX[1][i] = RETRY_PENALTY_IDX_S[1][i]; + + RETRY_PENALTY_UP_IDX[i] = RETRY_PENALTY_UP_IDX_S[i]; + } + return; +#endif + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /* This is for non-I-cut */ + { + void *adapter = dm->adapter; + + /* dbg_print("adapter->mgnt_info.reg_ra_lvl = %d\n", adapter->mgnt_info.reg_ra_lvl); */ + + /* 2012/09/14 MH Add for different Ra pattern init. For TPLINK case, we */ + /* need to to adjust different RA pattern for middle range RA. 20-30dB degarde */ + /* 88E rate adptve will raise too slow. */ + if (((PADAPTER)adapter)->MgntInfo.RegRALvl == 0) { + RETRY_PENALTY_UP_IDX[11] = 0x14; + + RETRY_PENALTY_UP_IDX[17] = 0x13; + RETRY_PENALTY_UP_IDX[18] = 0x14; + RETRY_PENALTY_UP_IDX[19] = 0x15; + + RETRY_PENALTY_UP_IDX[23] = 0x13; + RETRY_PENALTY_UP_IDX[24] = 0x13; + RETRY_PENALTY_UP_IDX[25] = 0x13; + RETRY_PENALTY_UP_IDX[26] = 0x14; + RETRY_PENALTY_UP_IDX[27] = 0x15; + } else if (((PADAPTER)adapter)->MgntInfo.RegRALvl == 1) { + RETRY_PENALTY_UP_IDX[17] = 0x13; + RETRY_PENALTY_UP_IDX[18] = 0x13; + RETRY_PENALTY_UP_IDX[19] = 0x14; + + RETRY_PENALTY_UP_IDX[23] = 0x12; + RETRY_PENALTY_UP_IDX[24] = 0x13; + RETRY_PENALTY_UP_IDX[25] = 0x13; + RETRY_PENALTY_UP_IDX[26] = 0x13; + RETRY_PENALTY_UP_IDX[27] = 0x14; + } else if (((PADAPTER)adapter)->MgntInfo.RegRALvl == 2) { + /* Compile flag default is lvl2, we need not to update. */ + } else if (((PADAPTER)adapter)->MgntInfo.RegRALvl >= 0x80) { + u8 index = 0, offset = ((PADAPTER)adapter)->MgntInfo.RegRALvl - 0x80; + + /* Reset to default rate adaptive value. */ + RETRY_PENALTY_UP_IDX[11] = 0x14; + + RETRY_PENALTY_UP_IDX[17] = 0x13; + RETRY_PENALTY_UP_IDX[18] = 0x14; + RETRY_PENALTY_UP_IDX[19] = 0x15; + + RETRY_PENALTY_UP_IDX[23] = 0x13; + RETRY_PENALTY_UP_IDX[24] = 0x13; + RETRY_PENALTY_UP_IDX[25] = 0x13; + RETRY_PENALTY_UP_IDX[26] = 0x14; + RETRY_PENALTY_UP_IDX[27] = 0x15; + + if (((PADAPTER)adapter)->MgntInfo.RegRALvl >= 0x90) { + offset = ((PADAPTER)adapter)->MgntInfo.RegRALvl - 0x90; + /* Lazy mode. */ + for (index = 0; index < 28; index++) + RETRY_PENALTY_UP_IDX[index] += (offset); + } else { + /* Aggrasive side. */ + for (index = 0; index < 28; index++) + RETRY_PENALTY_UP_IDX[index] -= (offset); + } + } + } +#endif + return; +} + +u8 odm_ra_get_sgi_8188e(struct dm_struct *dm, u8 mac_id) +{ + if (dm == NULL || mac_id >= ASSOCIATE_ENTRY_NUM) + return 0; + PHYDM_DBG(dm, DBG_RA, "mac_id=%d SGI=%d\n", mac_id, + dm->ra_info[mac_id].rate_sgi); + return dm->ra_info[mac_id].rate_sgi; +} + +u8 odm_ra_get_decision_rate_8188e(struct dm_struct *dm, u8 mac_id) +{ + u8 rate = 0; + + if (dm == NULL || mac_id >= ASSOCIATE_ENTRY_NUM) + return 0; + + rate = (dm->ra_info[mac_id].decision_rate); + + /*PHYDM_DBG(dm, DBG_RA, "Rate[%d]=0x%x\n", mac_id, rate);*/ + return rate; +} + +u8 odm_ra_get_hw_pwr_status_8188e(struct dm_struct *dm, u8 mac_id) +{ + u8 pt_stage = 5; + if (dm == NULL || mac_id >= ASSOCIATE_ENTRY_NUM) + return 0; + pt_stage = (dm->ra_info[mac_id].pt_stage); + PHYDM_DBG(dm, DBG_RA, "mac_id=%d pt_stage=0x%x\n", mac_id, pt_stage); + return pt_stage; +} + +u8 phydm_get_rate_id_88e(void *dm_void, u8 sta_idx) +{ + struct dm_struct *dm = (struct dm_struct *)dm_void; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + struct ra_sta_info *ra = NULL; + enum channel_width bw = (enum channel_width)0; + enum wireless_set wireless_mode = WIRELESS_HT; + u8 rate_id_idx = PHYDM_BGN_20M_1SS; + + if (is_sta_active(sta)) { + ra = &(sta->ra_info); + bw = sta->bw_mode; + wireless_mode = sta->support_wireless_set; + + } else { + PHYDM_DBG(dm, DBG_RA, "[Warning] %s: invalid sta_info\n", + __func__); + return 0; + } + + PHYDM_DBG(dm, DBG_RA, "[88E] macid=%d, wireless_set=0x%x, BW=0x%x\n", + sta->mac_id, wireless_mode, bw); + + if (wireless_mode == WIRELESS_CCK) /*B mode*/ + rate_id_idx = PHYDM_RAID_88E_B; + else if (wireless_mode == WIRELESS_OFDM) /*G mode*/ + rate_id_idx = PHYDM_RAID_88E_G; + else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM)) /*BG mode*/ + rate_id_idx = PHYDM_RAID_88E_GB; + else if (wireless_mode == WIRELESS_HT) /*N mode*/ + rate_id_idx = PHYDM_RAID_88E_N; + else if (wireless_mode == (WIRELESS_OFDM | WIRELESS_HT)) /*GN mode*/ + rate_id_idx = PHYDM_RAID_88E_NG; + else if (wireless_mode == (WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT)) /*BGN mode*/ + rate_id_idx = PHYDM_RAID_88E_NGB; + else { + PHYDM_DBG(dm, DBG_RA, "[Warrning] No rate_id is found\n"); + rate_id_idx = RATR_INX_WIRELESS_GB; + } + + PHYDM_DBG(dm, DBG_RA, "88E Rate_ID=((0x%x))\n", rate_id_idx); + return rate_id_idx; +} + +void phydm_ra_update_8188e(struct dm_struct *dm, u8 sta_idx, u8 rate_id, + u32 rate_mask, u8 sgi_enable) +{ + struct _odm_ra_info_ *p_ra_info = NULL; + struct cmn_sta_info *sta = dm->phydm_sta_info[sta_idx]; + + PHYDM_DBG(dm, DBG_RA, + "mac_id=%d rate_id=0x%x rate_mask=0x%x sgi_enable=%d\n", + sta->mac_id, rate_id, rate_mask, sgi_enable); + if (dm == NULL || sta->mac_id >= ASSOCIATE_ENTRY_NUM) + return; + + p_ra_info = &(dm->ra_info[sta->mac_id]); + p_ra_info->rate_id = rate_id; + p_ra_info->rate_mask = rate_mask; + p_ra_info->sgi_enable = sgi_enable; + odm_arfb_refresh_8188e(dm, p_ra_info); +} + +void odm_ra_set_rssi_8188e(struct dm_struct *dm, u8 mac_id, u8 rssi) +{ + struct _odm_ra_info_ *p_ra_info = NULL; + + PHYDM_DBG(dm, DBG_RA, " mac_id=%d rssi=%d\n", mac_id, rssi); + if (dm == NULL || mac_id >= ASSOCIATE_ENTRY_NUM) + return; + + p_ra_info = &(dm->ra_info[mac_id]); + p_ra_info->rssi_sta_ra = rssi; +} + +void odm_ra_set_tx_rpt_time(struct dm_struct *dm, u16 min_rpt_time) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if (min_rpt_time != 0xffff) { +#if defined(CONFIG_PCI_HCI) + odm_write_2byte(dm, REG_TX_RPT_TIME, min_rpt_time); +#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) + notify_tx_report_interval_change(dm->priv, min_rpt_time); +#endif + } +#else + odm_write_2byte(dm, REG_TX_RPT_TIME, min_rpt_time); +#endif +} + +void odm_ra_tx_rpt2_handle_8188e(struct dm_struct *dm, u8 *tx_rpt_buf, + u16 tx_rpt_len, u32 mac_id_valid_entry0, + u32 mac_id_valid_entry1) +{ + struct _odm_ra_info_ *p_ra_info = NULL; + struct _phydm_txstatistic_ *tx_stats = NULL; + u8 mac_id = 0; + u8 *p_buffer = NULL; + u32 valid = 0, item_num = 0; + u16 min_rpt_time = 0x927c; + + PHYDM_DBG(dm, DBG_RA, "=====>%s: valid0=%d valid1=%d BufferLength=%d\n", + __func__, mac_id_valid_entry0, mac_id_valid_entry1, + tx_rpt_len); + + item_num = tx_rpt_len >> 3; + p_buffer = tx_rpt_buf; + + do { + valid = 0; + if (mac_id < 32) + valid = (1 << mac_id) & mac_id_valid_entry0; + /*else if (mac_id < 64)*/ + /* valid = (1 << (mac_id - 32)) & mac_id_valid_entry1;*/ + + p_ra_info = &(dm->ra_info[mac_id]); + tx_stats = &(dm->hw_stats); + + if (valid) { + p_ra_info->RTY[0] = (u16)GET_TX_REPORT_TYPE1_RERTY_0(p_buffer); + p_ra_info->RTY[1] = (u16)GET_TX_REPORT_TYPE1_RERTY_1(p_buffer); + p_ra_info->RTY[2] = (u16)GET_TX_REPORT_TYPE1_RERTY_2(p_buffer); + p_ra_info->RTY[3] = (u16)GET_TX_REPORT_TYPE1_RERTY_3(p_buffer); + p_ra_info->RTY[4] = (u16)GET_TX_REPORT_TYPE1_RERTY_4(p_buffer); + p_ra_info->DROP = (u16)GET_TX_REPORT_TYPE1_DROP_0(p_buffer); + + p_ra_info->TOTAL = p_ra_info->RTY[0] + + p_ra_info->RTY[1] + + p_ra_info->RTY[2] + + p_ra_info->RTY[3] + + p_ra_info->RTY[4] + + p_ra_info->DROP; + tx_stats->hw_total_tx += p_ra_info->TOTAL; + tx_stats->hw_tx_success += p_ra_info->TOTAL - p_ra_info->DROP; + tx_stats->hw_tx_drop += p_ra_info->DROP; + tx_stats->hw_tx_rty += p_ra_info->RTY[1] + p_ra_info->RTY[2] * 2 + p_ra_info->RTY[3] * 3 + p_ra_info->RTY[4] * 4; +#if defined(TXRETRY_CNT) + extern struct stat_info *get_macidinfo(struct rtl8192cd_priv * priv, unsigned int aid); + + { + struct stat_info *pstat = get_macidinfo(dm->priv, mac_id); + if (pstat) { + pstat->cur_tx_ok += p_ra_info->RTY[0]; + pstat->cur_tx_retry_pkts += p_ra_info->RTY[1] + p_ra_info->RTY[2] + p_ra_info->RTY[3] + p_ra_info->RTY[4]; + pstat->cur_tx_retry_cnt += p_ra_info->RTY[1] + p_ra_info->RTY[2] * 2 + p_ra_info->RTY[3] * 3 + p_ra_info->RTY[4] * 4; + pstat->total_tx_retry_cnt += pstat->cur_tx_retry_cnt; + pstat->total_tx_retry_pkts += pstat->cur_tx_retry_pkts; + pstat->cur_tx_fail += p_ra_info->DROP; + } + } +#endif + if (p_ra_info->TOTAL != 0) { + PHYDM_DBG(dm, DBG_RA, + "macid=%d Total=%d R0=%d R1=%d R2=%d R3=%d R4=%d D0=%d valid0=%x valid1=%x\n", + mac_id, p_ra_info->TOTAL, + p_ra_info->RTY[0], p_ra_info->RTY[1], + p_ra_info->RTY[2], p_ra_info->RTY[3], + p_ra_info->RTY[4], p_ra_info->DROP, + mac_id_valid_entry0, + mac_id_valid_entry1); +#if POWER_TRAINING_ACTIVE == 1 + if (p_ra_info->pt_active) { + if (p_ra_info->ra_stage < 5) + odm_rate_decision_8188e(dm, p_ra_info, mac_id); + else if (p_ra_info->ra_stage == 5) /* Power training try state */ + odm_pt_try_state_8188e(dm, p_ra_info); + else /* ra_stage==6 */ + odm_pt_decision_8188e(p_ra_info); + + /* Stage_RA counter */ + if (p_ra_info->ra_stage <= 5) + p_ra_info->ra_stage++; + else + p_ra_info->ra_stage = 0; + } else + odm_rate_decision_8188e(dm, p_ra_info, mac_id); +#else + odm_rate_decision_8188e(dm, p_ra_info, mac_id); +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + extern void rtl8188e_set_station_tx_rate_info(struct dm_struct *, struct _odm_ra_info_ *, int); + rtl8188e_set_station_tx_rate_info(dm, p_ra_info, mac_id); +#if 0 + void rtl8188e_detect_sta_existance(struct dm_struct *dm, struct _odm_ra_info_ *p_ra_info, int mac_id); + rtl8188e_detect_sta_existance(dm, p_ra_info, mac_id); +#endif +#endif + + PHYDM_DBG(dm, DBG_RA, + "macid=%d R0=%d R1=%d R2=%d R3=%d R4=%d drop=%d valid0=%x rate_id=%d SGI=%d\n", + mac_id, p_ra_info->RTY[0], + p_ra_info->RTY[1], p_ra_info->RTY[2], + p_ra_info->RTY[3], p_ra_info->RTY[4], + p_ra_info->DROP, mac_id_valid_entry0, + p_ra_info->decision_rate, + p_ra_info->rate_sgi); + } else + PHYDM_DBG(dm, DBG_RA, " TOTAL=0!!!!\n"); + + if (min_rpt_time > p_ra_info->rpt_time) + min_rpt_time = p_ra_info->rpt_time; + } + + p_buffer += TX_RPT2_ITEM_SIZE; + + mac_id++; + } while (mac_id < item_num); + + odm_ra_tx_rpt_timer_setting(dm, min_rpt_time); + + PHYDM_DBG(dm, DBG_RA, "<===== %s\n", __func__); +} + +#else + +static void +odm_ra_tx_rpt_timer_setting( + struct dm_struct *dm, + u16 min_rpt_time) +{ + return; +} + +void odm_ra_support_init(struct dm_struct *dm) +{ + return; +} + +int odm_ra_info_init(struct dm_struct *dm, u32 mac_id) +{ + return 0; +} + +void odm_ra_info_init_all(struct dm_struct *dm) +{ + return; +} + +u8 odm_ra_get_sgi_8188e(struct dm_struct *dm, u8 mac_id) +{ + return 0; +} + +u8 odm_ra_get_decision_rate_8188e(struct dm_struct *dm, u8 mac_id) +{ + return 0; +} +u8 odm_ra_get_hw_pwr_status_8188e(struct dm_struct *dm, u8 mac_id) +{ + return 0; +} + +void phydm_ra_update_8188e(struct dm_struct *dm, u8 mac_id, u8 rate_id, + u32 rate_mask, u8 sgi_enable) +{ + return; +} + +void odm_ra_set_rssi_8188e(struct dm_struct *dm, u8 mac_id, u8 rssi) +{ + return; +} + +void odm_ra_set_tx_rpt_time(struct dm_struct *dm, u16 min_rpt_time) +{ + return; +} + +void odm_ra_tx_rpt2_handle_8188e(struct dm_struct *dm, u8 *tx_rpt_buf, + u16 tx_rpt_len, u32 mac_id_valid_entry0, + u32 mac_id_valid_entry1) +{ + return; +} + +#endif diff --git a/hal/phydm/rtl8188e/hal8188erateadaptive.h b/hal/phydm/rtl8188e/hal8188erateadaptive.h new file mode 100644 index 0000000..979e464 --- /dev/null +++ b/hal/phydm/rtl8188e/hal8188erateadaptive.h @@ -0,0 +1,86 @@ +/****************************************************************************** + * + * Copyright(c) Semiconductor - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_RA_H +#define __INC_RA_H + +/* rate adaptive define */ +#define PERENTRY 23 +#define RETRYSIZE 5 +#define RATESIZE 28 +#define TX_RPT2_ITEM_SIZE 8 + +#define DM_RA_RATE_UP 1 +#define DM_RA_RATE_DOWN 2 + +#define AP_USB_SDIO ((DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))) + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +/* + * TX report 2 format in Rx desc + * */ +#define GET_TX_RPT2_DESC_PKT_LEN_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc, 0, 9) +#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc + 16, 0, 32) +#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc + 20, 0, 32) + +#define GET_TX_REPORT_TYPE1_RERTY_0(__paddr) LE_BITS_TO_4BYTE(__paddr, 0, 16) +#define GET_TX_REPORT_TYPE1_RERTY_1(__paddr) LE_BITS_TO_1BYTE(__paddr + 2, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_2(__paddr) LE_BITS_TO_1BYTE(__paddr + 3, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_3(__paddr) LE_BITS_TO_1BYTE(__paddr + 4, 0, 8) +#define GET_TX_REPORT_TYPE1_RERTY_4(__paddr) LE_BITS_TO_1BYTE(__paddr + 4 + 1, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_0(__paddr) LE_BITS_TO_1BYTE(__paddr + 4 + 2, 0, 8) +#define GET_TX_REPORT_TYPE1_DROP_1(__paddr) LE_BITS_TO_1BYTE(__paddr + 4 + 3, 0, 8) +#endif + +enum phydm_rateid_idx_88e_e { /*Copy From SD4 _RATR_TABLE_MODE*/ + PHYDM_RAID_88E_NGB = 0, /* BGN 40 Mhz 2SS 1SS */ + PHYDM_RAID_88E_NG = 1, /* GN or N */ + PHYDM_RAID_88E_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */ + PHYDM_RAID_88E_N = 3, + PHYDM_RAID_88E_GB = 4, + PHYDM_RAID_88E_G = 5, + PHYDM_RAID_88E_B = 6, + PHYDM_RAID_88E_MC = 7, + PHYDM_RAID_88E_AC_N = 8 +}; + +/* End rate adaptive define */ + +extern void phydm_tx_stats_rst(struct dm_struct *dm); + +void odm_ra_support_init(struct dm_struct *dm); + +void odm_ra_info_init_all(struct dm_struct *dm); + +int odm_ra_info_init(struct dm_struct *dm, u32 mac_id); + +u8 odm_ra_get_sgi_8188e(struct dm_struct *dm, u8 mac_id); + +u8 odm_ra_get_decision_rate_8188e(struct dm_struct *dm, u8 mac_id); + +u8 odm_ra_get_hw_pwr_status_8188e(struct dm_struct *dm, u8 mac_id); + +u8 phydm_get_rate_id_88e(void *dm_void, u8 macid); + +void phydm_ra_update_8188e(struct dm_struct *dm, u8 mac_id, u8 rate_id, + u32 rate_mask, u8 sgi_enable); + +void odm_ra_set_rssi_8188e(struct dm_struct *dm, u8 mac_id, u8 rssi); + +void odm_ra_tx_rpt2_handle_8188e(struct dm_struct *dm, u8 *tx_rpt_buf, + u16 tx_rpt_len, u32 mac_id_valid_entry0, + u32 mac_id_valid_entry1); + +void odm_ra_set_tx_rpt_time(struct dm_struct *dm, u16 min_rpt_time); +#endif diff --git a/hal/phydm/rtl8188e/hal8188ereg.h b/hal/phydm/rtl8188e/hal8188ereg.h new file mode 100644 index 0000000..1479fd6 --- /dev/null +++ b/hal/phydm/rtl8188e/hal8188ereg.h @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +/* ************************************************************ + * File Name: hal8188ereg.h + * + * Description: + * + * This file is for RTL8188E register definition. + * + * + * ************************************************************ */ +#ifndef __HAL_8188E_REG_H__ +#define __HAL_8188E_REG_H__ + +/* + * Register Definition + * */ +#define TRX_ANTDIV_PATH 0x860 +#define RX_ANTDIV_PATH 0xb2c +#define ODM_R_A_AGC_CORE1_8188E 0xc50 + +#define REG_GPIO_EXT_CTRL 0x0060 + +#define REG_MCUFWDL_8188E 0x0080 +#define REG_FW_DBG_STATUS_8188E 0x0088 +#define REG_FW_DBG_CTRL_8188E 0x008F + +#define REG_CR_8188E 0x0100 + +/* + * Bitmap Definition + * */ +#define BIT_FA_RESET_8188E BIT(0) +#define REG_ADAPTIVE_DATA_RATE_0 0x2B0 +#define REG_DBI_WDATA_8188 0x0348 /* DBI Write data */ +#define REG_DBI_RDATA_8188 0x034C /* DBI Read data */ +#define REG_DBI_ADDR_8188 0x0350 /* DBI Address */ +#define REG_DBI_FLAG_8188 0x0352 /* DBI Read/Write Flag */ +#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */ +#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */ +#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */ + +/* [0-63] */ +#define REG_MACID_NO_LINK 0x484 /* No Link register (bit[x] enabled means dropping packets for MACID in HW queue) */ + +#endif diff --git a/hal/phydm/rtl8188e/halhwimg8188e_bb.c b/hal/phydm/rtl8188e/halhwimg8188e_bb.c new file mode 100644 index 0000000..be47b39 --- /dev/null +++ b/hal/phydm/rtl8188e/halhwimg8188e_bb.c @@ -0,0 +1,1779 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*Image2HeaderVersion: 3.5.2*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) +static boolean +check_positive( + struct dm_struct *dm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 +) +{ + u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ + ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ + ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ + ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ + ((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ + ((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/ + ((dm->board_type & BIT(5)) >> 5) << 6; /* _TRSWT*/ + + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; + + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; + + u32 driver1 = cut_version_for_para << 24 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | + pkg_type_for_para << 12 | + (dm->support_interface & 0x0F) << 8 | + _board_type; + + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; + + u32 driver3 = 0; + + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; + + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, driver1, driver2, driver3, driver4); + + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", + dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Board, Package) = (0x%X, 0x%X)\n", dm->board_type, + dm->package_type); + + + /*============== value Defined Check ===============*/ + /*QFN type [15:12] and cut version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u32 bit_mask = 0; + + if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ + return true; + + if ((cond1 & BIT(0)) != 0) /*GLNA*/ + bit_mask |= 0x000000FF; + if ((cond1 & BIT(1)) != 0) /*GPA*/ + bit_mask |= 0x0000FF00; + if ((cond1 & BIT(2)) != 0) /*ALNA*/ + bit_mask |= 0x00FF0000; + if ((cond1 & BIT(3)) != 0) /*APA*/ + bit_mask |= 0xFF000000; + + if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ + return true; + else + return false; + } else + return false; +} + +/****************************************************************************** +* agc_tab.TXT +******************************************************************************/ + +u32 array_mp_8188e_agc_tab[] = { + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF6000001, + 0xC78, 0xF5010001, + 0xC78, 0xF4020001, + 0xC78, 0xF3030001, + 0xC78, 0xF2040001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF7000001, + 0xC78, 0xF6010001, + 0xC78, 0xF5020001, + 0xC78, 0xF4030001, + 0xC78, 0xF3040001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0xF9000001, + 0xC78, 0xF8010001, + 0xC78, 0xF7020001, + 0xC78, 0xF6030001, + 0xC78, 0xF5040001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFA020001, + 0xC78, 0xF9030001, + 0xC78, 0xF8040001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0xFF000001, + 0xC78, 0xFF010001, + 0xC78, 0xFE020001, + 0xC78, 0xFD030001, + 0xC78, 0xFC040001, + 0xA0000000, 0x00000000, + 0xC78, 0xFB000001, + 0xC78, 0xFB010001, + 0xC78, 0xFB020001, + 0xC78, 0xFB030001, + 0xC78, 0xFB040001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF1050001, + 0xC78, 0xF0060001, + 0xC78, 0xEF070001, + 0xC78, 0xEE080001, + 0xC78, 0xED090001, + 0xC78, 0xEC0A0001, + 0xC78, 0xEB0B0001, + 0xC78, 0xEA0C0001, + 0xC78, 0xE90D0001, + 0xC78, 0xE80E0001, + 0xC78, 0xE70F0001, + 0xC78, 0xE6100001, + 0xC78, 0xE5110001, + 0xC78, 0xE4120001, + 0xC78, 0xE3130001, + 0xC78, 0xE2140001, + 0xC78, 0xC5150001, + 0xC78, 0xC4160001, + 0xC78, 0xC3170001, + 0xC78, 0xC2180001, + 0xC78, 0x88190001, + 0xC78, 0x871A0001, + 0xC78, 0x861B0001, + 0xC78, 0x851C0001, + 0xC78, 0x841D0001, + 0xC78, 0x831E0001, + 0xC78, 0x821F0001, + 0xC78, 0x81200001, + 0xC78, 0x80210001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xF2050001, + 0xC78, 0xF1060001, + 0xC78, 0xF0070001, + 0xC78, 0xEF080001, + 0xC78, 0xEE090001, + 0xC78, 0xED0A0001, + 0xC78, 0xEC0B0001, + 0xC78, 0xEB0C0001, + 0xC78, 0xEA0D0001, + 0xC78, 0xE90E0001, + 0xC78, 0xE80F0001, + 0xC78, 0xE7100001, + 0xC78, 0xE6110001, + 0xC78, 0xE5120001, + 0xC78, 0xE4130001, + 0xC78, 0xE3140001, + 0xC78, 0xE2150001, + 0xC78, 0xE1160001, + 0xC78, 0x89170001, + 0xC78, 0x88180001, + 0xC78, 0x87190001, + 0xC78, 0x861A0001, + 0xC78, 0x851B0001, + 0xC78, 0x841C0001, + 0xC78, 0x831D0001, + 0xC78, 0x821E0001, + 0xC78, 0x811F0001, + 0xC78, 0x6B200001, + 0xC78, 0x6A210001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0xF4050001, + 0xC78, 0xF3060001, + 0xC78, 0xF2070001, + 0xC78, 0xF1080001, + 0xC78, 0xF0090001, + 0xC78, 0xEF0A0001, + 0xC78, 0xEE0B0001, + 0xC78, 0xED0C0001, + 0xC78, 0xEC0D0001, + 0xC78, 0xEB0E0001, + 0xC78, 0xEA0F0001, + 0xC78, 0xE9100001, + 0xC78, 0xE8110001, + 0xC78, 0xE7120001, + 0xC78, 0xE6130001, + 0xC78, 0xE5140001, + 0xC78, 0xE4150001, + 0xC78, 0xE3160001, + 0xC78, 0xE2170001, + 0xC78, 0xE1180001, + 0xC78, 0x8A190001, + 0xC78, 0x891A0001, + 0xC78, 0x881B0001, + 0xC78, 0x871C0001, + 0xC78, 0x861D0001, + 0xC78, 0x851E0001, + 0xC78, 0x841F0001, + 0xC78, 0x83200001, + 0xC78, 0x82210001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0xF7050001, + 0xC78, 0xF6060001, + 0xC78, 0xF5070001, + 0xC78, 0xF4080001, + 0xC78, 0xF3090001, + 0xC78, 0xF20A0001, + 0xC78, 0xF10B0001, + 0xC78, 0xF00C0001, + 0xC78, 0xEF0D0001, + 0xC78, 0xEE0E0001, + 0xC78, 0xED0F0001, + 0xC78, 0xEC100001, + 0xC78, 0xEB110001, + 0xC78, 0xEA120001, + 0xC78, 0xE9130001, + 0xC78, 0xE8140001, + 0xC78, 0xE7150001, + 0xC78, 0xE6160001, + 0xC78, 0xE5170001, + 0xC78, 0xE4180001, + 0xC78, 0xC7190001, + 0xC78, 0xC61A0001, + 0xC78, 0xC51B0001, + 0xC78, 0xC41C0001, + 0xC78, 0xC31D0001, + 0xC78, 0xC21E0001, + 0xC78, 0x871F0001, + 0xC78, 0x86200001, + 0xC78, 0x85210001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0xFB050001, + 0xC78, 0xFA060001, + 0xC78, 0xF9070001, + 0xC78, 0xF8080001, + 0xC78, 0xF7090001, + 0xC78, 0xF60A0001, + 0xC78, 0xF50B0001, + 0xC78, 0xF40C0001, + 0xC78, 0xF30D0001, + 0xC78, 0xF20E0001, + 0xC78, 0xF10F0001, + 0xC78, 0xF0100001, + 0xC78, 0xEF110001, + 0xC78, 0xEE120001, + 0xC78, 0xED130001, + 0xC78, 0xEC140001, + 0xC78, 0xEB150001, + 0xC78, 0xEA160001, + 0xC78, 0xE9170001, + 0xC78, 0xE8180001, + 0xC78, 0xE7190001, + 0xC78, 0xE61A0001, + 0xC78, 0xC51B0001, + 0xC78, 0xC41C0001, + 0xC78, 0xC31D0001, + 0xC78, 0xC21E0001, + 0xC78, 0x881F0001, + 0xC78, 0x87200001, + 0xC78, 0x86210001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFA050001, + 0xC78, 0xF9060001, + 0xC78, 0xF8070001, + 0xC78, 0xF7080001, + 0xC78, 0xF6090001, + 0xC78, 0xF50A0001, + 0xC78, 0xF40B0001, + 0xC78, 0xF30C0001, + 0xC78, 0xF20D0001, + 0xC78, 0xF10E0001, + 0xC78, 0xF00F0001, + 0xC78, 0xEF100001, + 0xC78, 0xEE110001, + 0xC78, 0xED120001, + 0xC78, 0xEC130001, + 0xC78, 0xEB140001, + 0xC78, 0xEA150001, + 0xC78, 0xE9160001, + 0xC78, 0xE8170001, + 0xC78, 0xE7180001, + 0xC78, 0xE6190001, + 0xC78, 0xE51A0001, + 0xC78, 0xE41B0001, + 0xC78, 0xC71C0001, + 0xC78, 0xC61D0001, + 0xC78, 0xC51E0001, + 0xC78, 0xC41F0001, + 0xC78, 0xC3200001, + 0xC78, 0xC2210001, + 0xA0000000, 0x00000000, + 0xC78, 0xFB050001, + 0xC78, 0xFA060001, + 0xC78, 0xF9070001, + 0xC78, 0xF8080001, + 0xC78, 0xF7090001, + 0xC78, 0xF60A0001, + 0xC78, 0xF50B0001, + 0xC78, 0xF40C0001, + 0xC78, 0xF30D0001, + 0xC78, 0xF20E0001, + 0xC78, 0xF10F0001, + 0xC78, 0xF0100001, + 0xC78, 0xEF110001, + 0xC78, 0xEE120001, + 0xC78, 0xED130001, + 0xC78, 0xEC140001, + 0xC78, 0xEB150001, + 0xC78, 0xEA160001, + 0xC78, 0xE9170001, + 0xC78, 0xE8180001, + 0xC78, 0xE7190001, + 0xC78, 0xE61A0001, + 0xC78, 0xE51B0001, + 0xC78, 0xE41C0001, + 0xC78, 0xE31D0001, + 0xC78, 0xE21E0001, + 0xC78, 0xE11F0001, + 0xC78, 0x8A200001, + 0xC78, 0x89210001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x66220001, + 0xC78, 0x65230001, + 0xC78, 0x64240001, + 0xC78, 0x63250001, + 0xC78, 0x62260001, + 0xC78, 0x61270001, + 0xC78, 0x60280001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x69220001, + 0xC78, 0x68230001, + 0xC78, 0x67240001, + 0xC78, 0x66250001, + 0xC78, 0x65260001, + 0xC78, 0x64270001, + 0xC78, 0x63280001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x6B220001, + 0xC78, 0x6A230001, + 0xC78, 0x69240001, + 0xC78, 0x68250001, + 0xC78, 0x67260001, + 0xC78, 0x66270001, + 0xC78, 0x65280001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x84220001, + 0xC78, 0x83230001, + 0xC78, 0x82240001, + 0xC78, 0x81250001, + 0xC78, 0x67260001, + 0xC78, 0x66270001, + 0xC78, 0x65280001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x85220001, + 0xC78, 0x84230001, + 0xC78, 0x83240001, + 0xC78, 0x82250001, + 0xC78, 0x6A260001, + 0xC78, 0x69270001, + 0xC78, 0x68280001, + 0xA0000000, 0x00000000, + 0xC78, 0x88220001, + 0xC78, 0x87230001, + 0xC78, 0x86240001, + 0xC78, 0x85250001, + 0xC78, 0x84260001, + 0xC78, 0x83270001, + 0xC78, 0x82280001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x4A290001, + 0xC78, 0x492A0001, + 0xC78, 0x482B0001, + 0xC78, 0x472C0001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x62290001, + 0xC78, 0x612A0001, + 0xC78, 0x462B0001, + 0xC78, 0x452C0001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x64290001, + 0xC78, 0x632A0001, + 0xC78, 0x622B0001, + 0xC78, 0x612C0001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x64290001, + 0xC78, 0x632A0001, + 0xC78, 0x622B0001, + 0xC78, 0x612C0001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x67290001, + 0xC78, 0x662A0001, + 0xC78, 0x652B0001, + 0xC78, 0x642C0001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x81290001, + 0xC78, 0x242A0001, + 0xC78, 0x232B0001, + 0xC78, 0x222C0001, + 0xA0000000, 0x00000000, + 0xC78, 0x6B290001, + 0xC78, 0x6A2A0001, + 0xC78, 0x692B0001, + 0xC78, 0x682C0001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x462D0001, + 0xC78, 0x452E0001, + 0xC78, 0x442F0001, + 0xC78, 0x43300001, + 0xC78, 0x42310001, + 0xC78, 0x41320001, + 0xC78, 0x40330001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x442D0001, + 0xC78, 0x432E0001, + 0xC78, 0x422F0001, + 0xC78, 0x41300001, + 0xC78, 0x40310001, + 0xC78, 0x40320001, + 0xC78, 0x40330001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x462D0001, + 0xC78, 0x452E0001, + 0xC78, 0x442F0001, + 0xC78, 0x43300001, + 0xC78, 0x42310001, + 0xC78, 0x41320001, + 0xC78, 0x40330001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x4B2D0001, + 0xC78, 0x4A2E0001, + 0xC78, 0x492F0001, + 0xC78, 0x48300001, + 0xC78, 0x47310001, + 0xC78, 0x46320001, + 0xC78, 0x45330001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x4A2D0001, + 0xC78, 0x492E0001, + 0xC78, 0x482F0001, + 0xC78, 0x47300001, + 0xC78, 0x46310001, + 0xC78, 0x45320001, + 0xC78, 0x44330001, + 0xA0000000, 0x00000000, + 0xC78, 0x672D0001, + 0xC78, 0x662E0001, + 0xC78, 0x652F0001, + 0xC78, 0x64300001, + 0xC78, 0x63310001, + 0xC78, 0x62320001, + 0xC78, 0x61330001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x40340001, + 0xC78, 0x40350001, + 0xC78, 0x40360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x40340001, + 0xC78, 0x40350001, + 0xC78, 0x40360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x40340001, + 0xC78, 0x40350001, + 0xC78, 0x40360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x44340001, + 0xC78, 0x43350001, + 0xC78, 0x42360001, + 0xC78, 0x41370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x43340001, + 0xC78, 0x42350001, + 0xC78, 0x41360001, + 0xC78, 0x40370001, + 0xC78, 0x40380001, + 0xC78, 0x40390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0x60340001, + 0xC78, 0x4A350001, + 0xC78, 0x49360001, + 0xC78, 0x48370001, + 0xC78, 0x47380001, + 0xC78, 0x46390001, + 0xC78, 0x453A0001, + 0xC78, 0x443B0001, + 0xC78, 0x433C0001, + 0xC78, 0x423D0001, + 0xC78, 0x413E0001, + 0xA0000000, 0x00000000, + 0xC78, 0x46340001, + 0xC78, 0x45350001, + 0xC78, 0x44360001, + 0xC78, 0x43370001, + 0xC78, 0x42380001, + 0xC78, 0x41390001, + 0xC78, 0x403A0001, + 0xC78, 0x403B0001, + 0xC78, 0x403C0001, + 0xC78, 0x403D0001, + 0xC78, 0x403E0001, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x403F0001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x403F0001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x403F0001, + 0xA0000000, 0x00000000, + 0xC78, 0x403F0001, + 0xB0000000, 0x00000000, + 0x88000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFA410001, + 0xC78, 0xF9420001, + 0xC78, 0xF8430001, + 0xC78, 0xF7440001, + 0xC78, 0xF6450001, + 0xC78, 0xF5460001, + 0xC78, 0xF4470001, + 0xC78, 0xF3480001, + 0xC78, 0xF2490001, + 0xC78, 0xF14A0001, + 0xC78, 0xF04B0001, + 0xC78, 0xEF4C0001, + 0xC78, 0xEE4D0001, + 0xC78, 0xED4E0001, + 0xC78, 0xEC4F0001, + 0xC78, 0xEB500001, + 0xC78, 0xEA510001, + 0xC78, 0xE9520001, + 0xC78, 0xE8530001, + 0xC78, 0xE7540001, + 0xC78, 0xE6550001, + 0xC78, 0xE5560001, + 0xC78, 0xC6570001, + 0xC78, 0xC5580001, + 0xC78, 0xC4590001, + 0xC78, 0xC35A0001, + 0xC78, 0xC25B0001, + 0xC78, 0xC15C0001, + 0xC78, 0xC05D0001, + 0xC78, 0xA35E0001, + 0xC78, 0xA25F0001, + 0xC78, 0xA1600001, + 0xC78, 0x88610001, + 0xC78, 0x87620001, + 0xC78, 0x86630001, + 0xC78, 0x85640001, + 0xC78, 0x84650001, + 0xC78, 0x83660001, + 0xC78, 0x82670001, + 0xC78, 0x66680001, + 0xC78, 0x65690001, + 0xC78, 0x646A0001, + 0xC78, 0x636B0001, + 0xC78, 0x626C0001, + 0xC78, 0x616D0001, + 0xC78, 0x486E0001, + 0xC78, 0x476F0001, + 0xC78, 0x46700001, + 0xC78, 0x45710001, + 0xC78, 0x44720001, + 0xC78, 0x43730001, + 0xC78, 0x42740001, + 0xC78, 0x41750001, + 0xC78, 0x40760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFA410001, + 0xC78, 0xF9420001, + 0xC78, 0xF8430001, + 0xC78, 0xF7440001, + 0xC78, 0xF6450001, + 0xC78, 0xF5460001, + 0xC78, 0xF4470001, + 0xC78, 0xF3480001, + 0xC78, 0xF2490001, + 0xC78, 0xF14A0001, + 0xC78, 0xF04B0001, + 0xC78, 0xEF4C0001, + 0xC78, 0xEE4D0001, + 0xC78, 0xED4E0001, + 0xC78, 0xEC4F0001, + 0xC78, 0xEB500001, + 0xC78, 0xEA510001, + 0xC78, 0xE9520001, + 0xC78, 0xE8530001, + 0xC78, 0xE7540001, + 0xC78, 0xE6550001, + 0xC78, 0xE5560001, + 0xC78, 0xE4570001, + 0xC78, 0xE3580001, + 0xC78, 0xE2590001, + 0xC78, 0xC35A0001, + 0xC78, 0xC25B0001, + 0xC78, 0xC15C0001, + 0xC78, 0x8B5D0001, + 0xC78, 0x8A5E0001, + 0xC78, 0x895F0001, + 0xC78, 0x88600001, + 0xC78, 0x87610001, + 0xC78, 0x86620001, + 0xC78, 0x85630001, + 0xC78, 0x84640001, + 0xC78, 0x67650001, + 0xC78, 0x66660001, + 0xC78, 0x65670001, + 0xC78, 0x64680001, + 0xC78, 0x63690001, + 0xC78, 0x626A0001, + 0xC78, 0x616B0001, + 0xC78, 0x606C0001, + 0xC78, 0x466D0001, + 0xC78, 0x456E0001, + 0xC78, 0x446F0001, + 0xC78, 0x43700001, + 0xC78, 0x42710001, + 0xC78, 0x41720001, + 0xC78, 0x40730001, + 0xC78, 0x40740001, + 0xC78, 0x40750001, + 0xC78, 0x40760001, + 0xC78, 0x40770001, + 0xC78, 0x40780001, + 0xC78, 0x40790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFA460001, + 0xC78, 0xF9470001, + 0xC78, 0xF8480001, + 0xC78, 0xF7490001, + 0xC78, 0xF64A0001, + 0xC78, 0xF54B0001, + 0xC78, 0xF44C0001, + 0xC78, 0xF34D0001, + 0xC78, 0xF24E0001, + 0xC78, 0xF14F0001, + 0xC78, 0xF0500001, + 0xC78, 0xEF510001, + 0xC78, 0xEE520001, + 0xC78, 0xED530001, + 0xC78, 0xEC540001, + 0xC78, 0xEB550001, + 0xC78, 0xEA560001, + 0xC78, 0xE9570001, + 0xC78, 0xE8580001, + 0xC78, 0xE7590001, + 0xC78, 0xE65A0001, + 0xC78, 0xE55B0001, + 0xC78, 0xC65C0001, + 0xC78, 0xC55D0001, + 0xC78, 0xC45E0001, + 0xC78, 0xC35F0001, + 0xC78, 0xC2600001, + 0xC78, 0xC1610001, + 0xC78, 0xC0620001, + 0xC78, 0xA3630001, + 0xC78, 0xA2640001, + 0xC78, 0xA1650001, + 0xC78, 0x88660001, + 0xC78, 0x87670001, + 0xC78, 0x86680001, + 0xC78, 0x85690001, + 0xC78, 0x846A0001, + 0xC78, 0x836B0001, + 0xC78, 0x826C0001, + 0xC78, 0x666D0001, + 0xC78, 0x656E0001, + 0xC78, 0x646F0001, + 0xC78, 0x63700001, + 0xC78, 0x62710001, + 0xC78, 0x61720001, + 0xC78, 0x48730001, + 0xC78, 0x47740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFB460001, + 0xC78, 0xFB470001, + 0xC78, 0xFB480001, + 0xC78, 0xFA490001, + 0xC78, 0xF94A0001, + 0xC78, 0xF84B0001, + 0xC78, 0xF74C0001, + 0xC78, 0xF64D0001, + 0xC78, 0xF54E0001, + 0xC78, 0xF44F0001, + 0xC78, 0xF3500001, + 0xC78, 0xF2510001, + 0xC78, 0xF1520001, + 0xC78, 0xF0530001, + 0xC78, 0xEF540001, + 0xC78, 0xEE550001, + 0xC78, 0xED560001, + 0xC78, 0xEC570001, + 0xC78, 0xEB580001, + 0xC78, 0xEA590001, + 0xC78, 0xE95A0001, + 0xC78, 0xE85B0001, + 0xC78, 0xE75C0001, + 0xC78, 0xE65D0001, + 0xC78, 0xE55E0001, + 0xC78, 0xE45F0001, + 0xC78, 0xE3600001, + 0xC78, 0xE2610001, + 0xC78, 0xC3620001, + 0xC78, 0xC2630001, + 0xC78, 0xC1640001, + 0xC78, 0x8B650001, + 0xC78, 0x8A660001, + 0xC78, 0x89670001, + 0xC78, 0x88680001, + 0xC78, 0x87690001, + 0xC78, 0x866A0001, + 0xC78, 0x856B0001, + 0xC78, 0x846C0001, + 0xC78, 0x676D0001, + 0xC78, 0x666E0001, + 0xC78, 0x656F0001, + 0xC78, 0x64700001, + 0xC78, 0x63710001, + 0xC78, 0x62720001, + 0xC78, 0x61730001, + 0xC78, 0x60740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFB460001, + 0xC78, 0xFB470001, + 0xC78, 0xFB480001, + 0xC78, 0xFA490001, + 0xC78, 0xF94A0001, + 0xC78, 0xF84B0001, + 0xC78, 0xF74C0001, + 0xC78, 0xF64D0001, + 0xC78, 0xF54E0001, + 0xC78, 0xF44F0001, + 0xC78, 0xF3500001, + 0xC78, 0xF2510001, + 0xC78, 0xF1520001, + 0xC78, 0xF0530001, + 0xC78, 0xEF540001, + 0xC78, 0xEE550001, + 0xC78, 0xED560001, + 0xC78, 0xEC570001, + 0xC78, 0xEB580001, + 0xC78, 0xEA590001, + 0xC78, 0xE95A0001, + 0xC78, 0xE85B0001, + 0xC78, 0xE75C0001, + 0xC78, 0xE65D0001, + 0xC78, 0xE55E0001, + 0xC78, 0xE45F0001, + 0xC78, 0xE3600001, + 0xC78, 0xE2610001, + 0xC78, 0xC3620001, + 0xC78, 0xC2630001, + 0xC78, 0xC1640001, + 0xC78, 0x8B650001, + 0xC78, 0x8A660001, + 0xC78, 0x89670001, + 0xC78, 0x88680001, + 0xC78, 0x87690001, + 0xC78, 0x866A0001, + 0xC78, 0x856B0001, + 0xC78, 0x846C0001, + 0xC78, 0x676D0001, + 0xC78, 0x666E0001, + 0xC78, 0x656F0001, + 0xC78, 0x64700001, + 0xC78, 0x63710001, + 0xC78, 0x62720001, + 0xC78, 0x61730001, + 0xC78, 0x60740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC78, 0xFF400001, + 0xC78, 0xFF410001, + 0xC78, 0xFE420001, + 0xC78, 0xFD430001, + 0xC78, 0xFC440001, + 0xC78, 0xFB450001, + 0xC78, 0xFA460001, + 0xC78, 0xF9470001, + 0xC78, 0xF8480001, + 0xC78, 0xF7490001, + 0xC78, 0xF64A0001, + 0xC78, 0xF54B0001, + 0xC78, 0xF44C0001, + 0xC78, 0xF34D0001, + 0xC78, 0xF24E0001, + 0xC78, 0xF14F0001, + 0xC78, 0xF0500001, + 0xC78, 0xEF510001, + 0xC78, 0xEE520001, + 0xC78, 0xED530001, + 0xC78, 0xEC540001, + 0xC78, 0xEB550001, + 0xC78, 0xEA560001, + 0xC78, 0xE9570001, + 0xC78, 0xE8580001, + 0xC78, 0xE7590001, + 0xC78, 0xE65A0001, + 0xC78, 0xE55B0001, + 0xC78, 0xE45C0001, + 0xC78, 0xA85D0001, + 0xC78, 0xA75E0001, + 0xC78, 0xA65F0001, + 0xC78, 0xA5600001, + 0xC78, 0xA4610001, + 0xC78, 0xA3620001, + 0xC78, 0xA2630001, + 0xC78, 0xA1640001, + 0xC78, 0x28650001, + 0xC78, 0x27660001, + 0xC78, 0x26670001, + 0xC78, 0x07680001, + 0xC78, 0x06690001, + 0xC78, 0x056A0001, + 0xC78, 0x046B0001, + 0xC78, 0x036C0001, + 0xC78, 0x026D0001, + 0xC78, 0x016E0001, + 0xC78, 0x646F0001, + 0xC78, 0x63700001, + 0xC78, 0x62710001, + 0xC78, 0x61720001, + 0xC78, 0x47730001, + 0xC78, 0x46740001, + 0xC78, 0x45750001, + 0xC78, 0x44760001, + 0xC78, 0x43770001, + 0xC78, 0x42780001, + 0xC78, 0x41790001, + 0xC78, 0x407A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xA0000000, 0x00000000, + 0xC78, 0xFB400001, + 0xC78, 0xFB410001, + 0xC78, 0xFB420001, + 0xC78, 0xFB430001, + 0xC78, 0xFB440001, + 0xC78, 0xFB450001, + 0xC78, 0xFB460001, + 0xC78, 0xFB470001, + 0xC78, 0xFB480001, + 0xC78, 0xFA490001, + 0xC78, 0xF94A0001, + 0xC78, 0xF84B0001, + 0xC78, 0xF74C0001, + 0xC78, 0xF64D0001, + 0xC78, 0xF54E0001, + 0xC78, 0xF44F0001, + 0xC78, 0xF3500001, + 0xC78, 0xF2510001, + 0xC78, 0xF1520001, + 0xC78, 0xF0530001, + 0xC78, 0xEF540001, + 0xC78, 0xEE550001, + 0xC78, 0xED560001, + 0xC78, 0xEC570001, + 0xC78, 0xEB580001, + 0xC78, 0xEA590001, + 0xC78, 0xE95A0001, + 0xC78, 0xE85B0001, + 0xC78, 0xE75C0001, + 0xC78, 0xE65D0001, + 0xC78, 0xE55E0001, + 0xC78, 0xE45F0001, + 0xC78, 0xE3600001, + 0xC78, 0xE2610001, + 0xC78, 0xC3620001, + 0xC78, 0xC2630001, + 0xC78, 0xC1640001, + 0xC78, 0x8B650001, + 0xC78, 0x8A660001, + 0xC78, 0x89670001, + 0xC78, 0x88680001, + 0xC78, 0x87690001, + 0xC78, 0x866A0001, + 0xC78, 0x856B0001, + 0xC78, 0x846C0001, + 0xC78, 0x676D0001, + 0xC78, 0x666E0001, + 0xC78, 0x656F0001, + 0xC78, 0x64700001, + 0xC78, 0x63710001, + 0xC78, 0x62720001, + 0xC78, 0x61730001, + 0xC78, 0x60740001, + 0xC78, 0x46750001, + 0xC78, 0x45760001, + 0xC78, 0x44770001, + 0xC78, 0x43780001, + 0xC78, 0x42790001, + 0xC78, 0x417A0001, + 0xC78, 0x407B0001, + 0xC78, 0x407C0001, + 0xB0000000, 0x00000000, + 0x80000001, 0x00000001, 0x40000000, 0x00000000, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xA0000000, 0x00000000, + 0xC78, 0x407D0001, + 0xC78, 0x407E0001, + 0xC78, 0x407F0001, + 0xB0000000, 0x00000000, + 0xC50, 0x69553422, + 0xC50, 0x69553420, + +}; + +void +odm_read_and_config_mp_8188e_agc_tab(struct dm_struct *dm) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8188e_agc_tab) / sizeof(u32); + u32 *array = array_mp_8188e_agc_tab; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_bb_agc_8188e(dm, v1, MASKDWORD, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8188e_agc_tab(void) +{ + return 71; +} + +/****************************************************************************** +* phy_reg.TXT +******************************************************************************/ + +u32 array_mp_8188e_phy_reg[] = { + 0x800, 0x80040000, + 0x804, 0x00000003, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x02200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390204, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x824, 0x00390004, + 0xA0000000, 0x00000000, + 0x824, 0x00390204, + 0xB0000000, 0x00000000, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00000000, + 0x854, 0x00000000, + 0x858, 0x569A11A9, + 0x85C, 0x01000014, + 0x860, 0x66F60110, + 0x864, 0x061F0649, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x870, 0x07000300, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000760, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x870, 0x07000760, + 0xA0000000, 0x00000000, + 0x870, 0x07000760, + 0xB0000000, 0x00000000, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x00000000, + 0x880, 0xB0000C1C, + 0x884, 0x00000001, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0xA08, 0x8C838300, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xA0C, 0x2D38120F, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xA0C, 0x2D38120F, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xA0C, 0x2E34120F, + 0xA0000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0xB0000000, 0x00000000, + 0xA10, 0x9500BB7E, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x13130000, + 0xA24, 0x060A0D10, + 0xA28, 0x00000103, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xA0000000, 0x00000000, + 0xA20, 0x1A1B0000, + 0xA24, 0x090E1317, + 0xA28, 0x00000204, + 0xB0000000, 0x00000000, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0xA78, 0x00000900, + 0xA7C, 0x225B0606, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xA80, 0x21807530, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xA80, 0x21807530, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x218075B1, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xA80, 0x21807531, + 0xA0000000, 0x00000000, + 0xA80, 0x218075B1, + 0xB0000000, 0x00000000, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xB2C, 0x00000000, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x80000000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xB2C, 0x80000000, + 0xA0000000, 0x00000000, + 0xB2C, 0x80000000, + 0xB0000000, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x08800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9AC47, + 0xC34, 0x469652AF, + 0xC38, 0x49795994, + 0xC3C, 0x0A97971C, + 0xC40, 0x1F7C403F, + 0xC44, 0x000100B7, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xC58, 0x00013959, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC58, 0x00013959, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xC58, 0x00013169, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013169, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013169, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC58, 0x00013169, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC58, 0x00013169, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC58, 0x00013159, + 0xA0000000, 0x00000000, + 0xC58, 0x00013169, + 0xB0000000, 0x00000000, + 0xC5C, 0x00250492, + 0xC60, 0x00000000, + 0xC64, 0x7112848B, + 0xC68, 0x47C00BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xC74, 0x020610DB, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x020610DB, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x020610DB, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC74, 0x020610DB, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC74, 0x020610DB, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC74, 0x028610DB, + 0xA0000000, 0x00000000, + 0xC74, 0x020610DB, + 0xB0000000, 0x00000000, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x2D4000B5, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xC80, 0x390000E4, + 0xA0000000, 0x00000000, + 0xC80, 0x390000E4, + 0xB0000000, 0x00000000, + 0xC84, 0x21F60000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xCA8, 0x00000000, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xCA8, 0x00000000, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xCA8, 0x00000000, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xCA8, 0xFFFF0000, + 0xA0000000, 0x00000000, + 0xCA8, 0x00000000, + 0xB0000000, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x00000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x00000740, + 0xD04, 0x00020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC43, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCC979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x00000000, + 0xD3C, 0x00127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000048, + 0xE68, 0x001B25A4, + 0xE6C, 0x00C00014, + 0xE70, 0x00C00014, + 0xE74, 0x01000014, + 0xE78, 0x01000014, + 0xE7C, 0x01000014, + 0xE80, 0x01000014, + 0xE84, 0x00C00014, + 0xE88, 0x01000014, + 0xE8C, 0x00C00014, + 0xED0, 0x00C00014, + 0xED4, 0x00C00014, + 0xED8, 0x00C00014, + 0xEDC, 0x00000014, + 0xEE0, 0x00000014, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0xEE8, 0x32555448, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x21555448, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0xEE8, 0x21555448, + 0xA0000000, 0x00000000, + 0xEE8, 0x21555448, + 0xB0000000, 0x00000000, + 0xEEC, 0x01C00014, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, + +}; + +void +odm_read_and_config_mp_8188e_phy_reg(struct dm_struct *dm) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8188e_phy_reg) / sizeof(u32); + u32 *array = array_mp_8188e_phy_reg; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_bb_phy_8188e(dm, v1, MASKDWORD, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8188e_phy_reg(void) +{ + return 71; +} + +/****************************************************************************** +* phy_reg_pg.TXT +******************************************************************************/ + +u32 array_mp_8188e_phy_reg_pg[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003800, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32343600, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x40424446, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28323638, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x38404244, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26303436 +}; + +void +odm_read_and_config_mp_8188e_phy_reg_pg(struct dm_struct *dm) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8188e_phy_reg_pg) / sizeof(u32); + u32 *array = array_mp_8188e_phy_reg_pg; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrByRate = array_len / 6; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + dm->phy_reg_pg_version = 1; + dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i + 1]; + u32 v3 = array[i + 2]; + u32 v4 = array[i + 3]; + u32 v5 = array[i + 4]; + u32 v6 = array[i + 5]; + + odm_config_bb_phy_reg_pg_8188e(dm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/hal/phydm/rtl8188e/halhwimg8188e_bb.h b/hal/phydm/rtl8188e/halhwimg8188e_bb.h new file mode 100644 index 0000000..335c290 --- /dev/null +++ b/hal/phydm/rtl8188e/halhwimg8188e_bb.h @@ -0,0 +1,51 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*Image2HeaderVersion: 3.5.2*/ +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8188E_H +#define __INC_MP_BB_HW_IMG_8188E_H + + +/****************************************************************************** +* agc_tab.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_agc_tab( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_agc_tab(void); + +/****************************************************************************** +* phy_reg.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_phy_reg( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_phy_reg(void); + +/****************************************************************************** +* phy_reg_pg.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_phy_reg_pg( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_phy_reg_pg(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/hal/phydm/rtl8188e/halhwimg8188e_mac.c b/hal/phydm/rtl8188e/halhwimg8188e_mac.c new file mode 100644 index 0000000..8fd2eb0 --- /dev/null +++ b/hal/phydm/rtl8188e/halhwimg8188e_mac.c @@ -0,0 +1,283 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*Image2HeaderVersion: 3.5.2*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) +static boolean +check_positive( + struct dm_struct *dm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 +) +{ + u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ + ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ + ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ + ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ + ((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ + ((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/ + ((dm->board_type & BIT(5)) >> 5) << 6; /* _TRSWT*/ + + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; + + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; + + u32 driver1 = cut_version_for_para << 24 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | + pkg_type_for_para << 12 | + (dm->support_interface & 0x0F) << 8 | + _board_type; + + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; + + u32 driver3 = 0; + + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; + + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, driver1, driver2, driver3, driver4); + + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", + dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Board, Package) = (0x%X, 0x%X)\n", dm->board_type, + dm->package_type); + + + /*============== value Defined Check ===============*/ + /*QFN type [15:12] and cut version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u32 bit_mask = 0; + + if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ + return true; + + if ((cond1 & BIT(0)) != 0) /*GLNA*/ + bit_mask |= 0x000000FF; + if ((cond1 & BIT(1)) != 0) /*GPA*/ + bit_mask |= 0x0000FF00; + if ((cond1 & BIT(2)) != 0) /*ALNA*/ + bit_mask |= 0x00FF0000; + if ((cond1 & BIT(3)) != 0) /*APA*/ + bit_mask |= 0xFF000000; + + if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ + return true; + else + return false; + } else + return false; +} + +/****************************************************************************** +* mac_reg.TXT +******************************************************************************/ + +u32 array_mp_8188e_mac_reg[] = { + 0x026, 0x00000041, + 0x027, 0x00000035, + 0x80000002, 0x00000000, 0x40000000, 0x00000000, + 0x040, 0x0000000C, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x040, 0x0000000C, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x040, 0x0000000C, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x040, 0x0000000C, + 0xA0000000, 0x00000000, + 0x040, 0x00000000, + 0xB0000000, 0x00000000, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000001, + 0x432, 0x00000002, + 0x433, 0x00000004, + 0x434, 0x00000005, + 0x435, 0x00000006, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x438, 0x00000000, + 0x439, 0x00000000, + 0x43A, 0x00000001, + 0x43B, 0x00000002, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000006, + 0x43F, 0x00000007, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000015, + 0x445, 0x000000F0, + 0x446, 0x0000000F, + 0x447, 0x00000000, + 0x458, 0x00000041, + 0x459, 0x000000A8, + 0x45A, 0x00000072, + 0x45B, 0x000000B9, + 0x460, 0x00000066, + 0x461, 0x00000066, + 0x480, 0x00000008, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4D3, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x63C, 0x00000008, + 0x63D, 0x00000008, + 0x63E, 0x0000000C, + 0x63F, 0x0000000C, + 0x640, 0x00000040, + 0x652, 0x00000020, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + +}; + +void +odm_read_and_config_mp_8188e_mac_reg(struct dm_struct *dm) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8188e_mac_reg) / sizeof(u32); + u32 *array = array_mp_8188e_mac_reg; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_mac_8188e(dm, v1, (u8)v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8188e_mac_reg(void) +{ + return 71; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/hal/phydm/rtl8188e/halhwimg8188e_mac.h b/hal/phydm/rtl8188e/halhwimg8188e_mac.h new file mode 100644 index 0000000..fdf71f4 --- /dev/null +++ b/hal/phydm/rtl8188e/halhwimg8188e_mac.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*Image2HeaderVersion: 3.5.2*/ +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8188E_H +#define __INC_MP_MAC_HW_IMG_8188E_H + + +/****************************************************************************** +* mac_reg.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_mac_reg( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_mac_reg(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/hal/phydm/rtl8188e/halhwimg8188e_rf.c b/hal/phydm/rtl8188e/halhwimg8188e_rf.c new file mode 100644 index 0000000..632c80c --- /dev/null +++ b/hal/phydm/rtl8188e/halhwimg8188e_rf.c @@ -0,0 +1,2414 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*Image2HeaderVersion: 3.5.2*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) +static boolean +check_positive( + struct dm_struct *dm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 +) +{ + u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ + ((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ + ((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ + ((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ + ((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ + ((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/ + ((dm->board_type & BIT(5)) >> 5) << 6; /* _TRSWT*/ + + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; + + u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version; + u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; + + u32 driver1 = cut_version_for_para << 24 | + (dm->support_interface & 0xF0) << 16 | + dm->support_platform << 16 | + pkg_type_for_para << 12 | + (dm->support_interface & 0x0F) << 8 | + _board_type; + + u32 driver2 = (dm->type_glna & 0xFF) << 0 | + (dm->type_gpa & 0xFF) << 8 | + (dm->type_alna & 0xFF) << 16 | + (dm->type_apa & 0xFF) << 24; + + u32 driver3 = 0; + + u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | + (dm->type_gpa & 0xFF00) | + (dm->type_alna & 0xFF00) << 8 | + (dm->type_apa & 0xFF00) << 16; + + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, cond1, cond2, cond3, cond4); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", + __func__, driver1, driver2, driver3, driver4); + + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Platform, Interface) = (0x%X, 0x%X)\n", + dm->support_platform, dm->support_interface); + PHYDM_DBG(dm, ODM_COMP_INIT, + " (Board, Package) = (0x%X, 0x%X)\n", dm->board_type, + dm->package_type); + + + /*============== value Defined Check ===============*/ + /*QFN type [15:12] and cut version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u32 bit_mask = 0; + + if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ + return true; + + if ((cond1 & BIT(0)) != 0) /*GLNA*/ + bit_mask |= 0x000000FF; + if ((cond1 & BIT(1)) != 0) /*GPA*/ + bit_mask |= 0x0000FF00; + if ((cond1 & BIT(2)) != 0) /*ALNA*/ + bit_mask |= 0x00FF0000; + if ((cond1 & BIT(3)) != 0) /*APA*/ + bit_mask |= 0xFF000000; + + if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ + return true; + else + return false; + } else + return false; +} + +/****************************************************************************** +* radioa.TXT +******************************************************************************/ + +u32 array_mp_8188e_radioa[] = { + 0x000, 0x00030000, + 0x008, 0x00084000, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000084, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0xA0000000, 0x00000000, + 0xB0000000, 0x00000000, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000C0000, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000000, + 0xB0000000, 0x00000000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000BE180, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF8FC, + 0x0B1, 0x00054400, + 0x0B2, 0x000CCC19, + 0x0B4, 0x00043003, + 0x0B6, 0x0004953E, + 0x0B7, 0x0001C718, + 0x0B8, 0x000060FF, + 0x0B9, 0x00080001, + 0x0BA, 0x00040000, + 0x0BB, 0x00000400, + 0x0BF, 0x000C0000, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x00088820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x051, 0x0006B27D, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E4DD, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E49D, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x0007E4DD, + 0xA0000000, 0x00000000, + 0x052, 0x0007E49D, + 0xB0000000, 0x00000000, + 0x053, 0x00000073, + 0x056, 0x00051FF3, + 0x035, 0x00000086, + 0x035, 0x00000186, + 0x035, 0x00000286, + 0x036, 0x00001C25, + 0x036, 0x00009C25, + 0x036, 0x00011C25, + 0x036, 0x00019C25, + 0x0B6, 0x00048538, + 0x018, 0x00000C07, + 0x05A, 0x0004BD00, + 0x019, 0x000739D0, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000A095, + 0x034, 0x00009092, + 0x034, 0x0000808E, + 0x034, 0x0000704F, + 0x034, 0x0000604C, + 0x034, 0x00005049, + 0x034, 0x0000400C, + 0x034, 0x00003009, + 0x034, 0x00002006, + 0x034, 0x00001003, + 0x034, 0x00000000, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADF3, + 0x034, 0x00009DF0, + 0x034, 0x00008DED, + 0x034, 0x00007DEA, + 0x034, 0x00006DE7, + 0x034, 0x000054EE, + 0x034, 0x000044EB, + 0x034, 0x000034E8, + 0x034, 0x0000246B, + 0x034, 0x00001468, + 0x034, 0x0000006D, + 0xB0000000, 0x00000000, + 0x000, 0x00030159, + 0x084, 0x00068200, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00079F80, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00079F80, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x0008014E, + 0x087, 0x0004DF80, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0xA0000000, 0x00000000, + 0x086, 0x000000CE, + 0x087, 0x00048A00, + 0xB0000000, 0x00000000, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x88000003, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000003, 0x00000001, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000003, 0x00000002, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x90000003, 0x00000002, 0x40000000, 0x00000000, + 0x03B, 0x000F07B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D0020, + 0x03B, 0x000CF060, + 0x03B, 0x000B07E0, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x0008F780, + 0x03B, 0x000727B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000001, 0x00000001, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000001, 0x00000002, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x90000002, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x90000001, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x90000001, 0x00000001, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x90000001, 0x00000002, 0x40000000, 0x00000000, + 0x03B, 0x000F07B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D0020, + 0x03B, 0x000CF060, + 0x03B, 0x000B07E0, + 0x03B, 0x000A0010, + 0x03B, 0x00090000, + 0x03B, 0x0008F780, + 0x03B, 0x000727B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0x98000000, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F6030, + 0x03B, 0x000E6030, + 0x03B, 0x000D6030, + 0x03B, 0x000C6030, + 0x03B, 0x000BF030, + 0x03B, 0x000A0020, + 0x03B, 0x00090090, + 0x03B, 0x0008F080, + 0x03B, 0x0007A730, + 0x03B, 0x000607B0, + 0x03B, 0x0005F770, + 0x03B, 0x00040060, + 0x03B, 0x00030090, + 0x03B, 0x00020780, + 0x03B, 0x000107A0, + 0x03B, 0x0000F760, + 0x0EF, 0x000000A0, + 0x90000400, 0x00000000, 0x40000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0xA0000000, 0x00000000, + 0x03B, 0x000F02B0, + 0x03B, 0x000EF7B0, + 0x03B, 0x000D4FB0, + 0x03B, 0x000CF060, + 0x03B, 0x000B0090, + 0x03B, 0x000A0080, + 0x03B, 0x00090080, + 0x03B, 0x0008F780, + 0x03B, 0x000722B0, + 0x03B, 0x0006F7B0, + 0x03B, 0x00054FB0, + 0x03B, 0x0004F060, + 0x03B, 0x00030090, + 0x03B, 0x00020080, + 0x03B, 0x00010080, + 0x03B, 0x0000F780, + 0x0EF, 0x000000A0, + 0xB0000000, 0x00000000, + 0x000, 0x00010159, + 0x018, 0x0000F407, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01F, 0x00080003, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033E60, + +}; + +void +odm_read_and_config_mp_8188e_radioa(struct dm_struct *dm) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8188e_radioa) / sizeof(u32); + u32 *array = array_mp_8188e_radioa; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n"); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped ? false : true; + PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n"); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n"); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(dm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_rf_radio_a_8188e(dm, v1, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8188e_radioa(void) +{ + return 71; +} + +/****************************************************************************** +* txpowertrack_ap.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_ap_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_ap_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_ap_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_ap_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_ap_8188e[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_ap_8188e[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_ap_8188e[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_ap_8188e[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_ap_8188e[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_ap_8188e[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_ap_8188e[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_ap_8188e[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +#endif + +void +odm_read_and_config_mp_8188e_txpowertrack_ap(struct dm_struct *dm) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8188e\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_ap_8188e, DELTA_SWINGIDX_SIZE * 3); +#endif +} + +/****************************************************************************** +* txpowertrack_pcie.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_pcie_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_pcie_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_pcie_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_pcie_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_pcie_8188e[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_pcie_8188e[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_pcie_8188e[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_pcie_8188e[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_pcie_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_pcie_8188e[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_pcie_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_pcie_8188e[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +#endif + +void +odm_read_and_config_mp_8188e_txpowertrack_pcie(struct dm_struct *dm) +{ +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8188e\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_pcie_8188e, DELTA_SWINGIDX_SIZE * 3); +#endif +} + +/****************************************************************************** +* txpowertrack_pcie_icut.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_pcie_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_pcie_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_pcie_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_pcie_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_pcie_icut_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_pcie_icut_8188e[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_pcie_icut_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_pcie_icut_8188e[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_pcie_icut_8188e[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_pcie_icut_8188e[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_pcie_icut_8188e[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_pcie_icut_8188e[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; + +void +odm_read_and_config_mp_8188e_txpowertrack_pcie_icut(struct dm_struct *dm) +{ + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8188e\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_pcie_icut_8188e, DELTA_SWINGIDX_SIZE * 3); +} + +/****************************************************************************** +* txpowertrack_sdio.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_8188e[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_8188e[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_8188e[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_8188e[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_8188e[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_8188e[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +#endif + +void +odm_read_and_config_mp_8188e_txpowertrack_sdio(struct dm_struct *dm) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8188e\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_8188e, DELTA_SWINGIDX_SIZE * 3); +#endif +} + +/****************************************************************************** +* txpowertrack_sdio_icut.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_icut_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_icut_8188e[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_icut_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_icut_8188e[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_icut_8188e[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_icut_8188e[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_icut_8188e[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_icut_8188e[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; + +void +odm_read_and_config_mp_8188e_txpowertrack_sdio_icut(struct dm_struct *dm) +{ + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8188e\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_sdio_icut_8188e, DELTA_SWINGIDX_SIZE * 3); +} + +/****************************************************************************** +* txpowertrack_usb.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_8188e[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_8188e[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_8188e[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_8188e[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_8188e[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_8188e[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +#endif + +void +odm_read_and_config_mp_8188e_txpowertrack_usb(struct dm_struct *dm) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8188e\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_8188e, DELTA_SWINGIDX_SIZE * 3); +#endif +} + +/****************************************************************************** +* txpowertrack_usb_icut.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_icut_8188e[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_icut_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_icut_8188e[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_icut_8188e[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_icut_8188e[] = {0, 0, 0, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 9, 9, 9, 9, 10, 11, 11, 11, 11, 11}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_icut_8188e[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_icut_8188e[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_icut_8188e[] = {0, 1, 2, 2, 2, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_icut_8188e[] = {0, 0, 0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 10, 10, 11, 12, 12, 12, 12}; + +void +odm_read_and_config_mp_8188e_txpowertrack_usb_icut(struct dm_struct *dm) +{ + struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info); + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_mp_8188e\n"); + + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + odm_move_memory(dm, cali_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE); + + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE * 3); + odm_move_memory(dm, cali_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_usb_icut_8188e, DELTA_SWINGIDX_SIZE * 3); +} + +/****************************************************************************** +* txpwr_lmt.TXT +******************************************************************************/ + +const char *array_mp_8188e_txpwr_lmt[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "30", + "FCC", "2.4G", "20M", "HT", "1T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "30", + "FCC", "2.4G", "20M", "HT", "1T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "30", + "FCC", "2.4G", "20M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "30", + "FCC", "2.4G", "20M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "30", + "FCC", "2.4G", "20M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "30", + "FCC", "2.4G", "20M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "30", + "FCC", "2.4G", "20M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "30", + "FCC", "2.4G", "20M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "30", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "30", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "30", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8188e_txpwr_lmt(struct dm_struct *dm) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8188e_txpwr_lmt) / sizeof(u8); + u8 *array = (u8 *)array_mp_8188e_txpwr_lmt; +#else + u32 array_len = sizeof(array_mp_8188e_txpwr_lmt) / sizeof(u8 *); + u8 **array = (u8 **)array_mp_8188e_txpwr_lmt; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len / 7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i + 1]; + u8 bandwidth = array[i + 2]; + u8 rate = array[i + 3]; + u8 rf_path = array[i + 4]; + u8 chnl = array[i + 5]; + u8 val = array[i + 6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i + 1]; + u8 *bandwidth = array[i + 2]; + u8 *rate = array[i + 3]; + u8 *rf_path = array[i + 4]; + u8 *chnl = array[i + 5]; + u8 *val = array[i + 6]; +#endif + + odm_config_bb_txpwr_lmt_8188e(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } +} + +/****************************************************************************** +* txpwr_lmt_88ee_m2_for_msi.TXT +******************************************************************************/ + +const char *array_mp_8188e_txpwr_lmt_88ee_m2_for_msi[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "28", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "28", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "30", + "FCC", "2.4G", "20M", "HT", "1T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "30", + "FCC", "2.4G", "20M", "HT", "1T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "30", + "FCC", "2.4G", "20M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "30", + "FCC", "2.4G", "20M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "30", + "FCC", "2.4G", "20M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "30", + "FCC", "2.4G", "20M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "30", + "FCC", "2.4G", "20M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "30", + "FCC", "2.4G", "20M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "30", + "FCC", "2.4G", "20M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "30", + "FCC", "2.4G", "20M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "30", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +odm_read_and_config_mp_8188e_txpwr_lmt_88ee_m2_for_msi(struct dm_struct *dm) +{ + u32 i = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u32 array_len = sizeof(array_mp_8188e_txpwr_lmt_88ee_m2_for_msi) / sizeof(u8); + u8 *array = (u8 *)array_mp_8188e_txpwr_lmt_88ee_m2_for_msi; +#else + u32 array_len = sizeof(array_mp_8188e_txpwr_lmt_88ee_m2_for_msi) / sizeof(u8 *); + u8 **array = (u8 **)array_mp_8188e_txpwr_lmt_88ee_m2_for_msi; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + void *adapter = dm->adapter; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter)); + + PlatformZeroMemory(hal_data->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT); + hal_data->nLinesReadPwrLmt = array_len / 7; +#endif + + PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__); + + for (i = 0; i < array_len; i += 7) { +#if (DM_ODM_SUPPORT_TYPE == ODM_IOT) + u8 regulation = array[i]; + u8 band = array[i + 1]; + u8 bandwidth = array[i + 2]; + u8 rate = array[i + 3]; + u8 rf_path = array[i + 4]; + u8 chnl = array[i + 5]; + u8 val = array[i + 6]; +#else + u8 *regulation = array[i]; + u8 *band = array[i + 1]; + u8 *bandwidth = array[i + 2]; + u8 *rate = array[i + 3]; + u8 *rf_path = array[i + 4]; + u8 *chnl = array[i + 5]; + u8 *val = array[i + 6]; +#endif + + odm_config_bb_txpwr_lmt_8188e(dm, regulation, band, bandwidth, rate, rf_path, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)hal_data->BufOfLinesPwrLmt[i / 7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rf_path, chnl, val); +#endif + } +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/hal/phydm/rtl8188e/halhwimg8188e_rf.h b/hal/phydm/rtl8188e/halhwimg8188e_rf.h new file mode 100644 index 0000000..752d0a9 --- /dev/null +++ b/hal/phydm/rtl8188e/halhwimg8188e_rf.h @@ -0,0 +1,118 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/*Image2HeaderVersion: 3.5.2*/ +#if (RTL8188E_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8188E_H +#define __INC_MP_RF_HW_IMG_8188E_H + + +/****************************************************************************** +* radioa.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_radioa( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_radioa(void); + +/****************************************************************************** +* txpowertrack_ap.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpowertrack_ap( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpowertrack_ap(void); + +/****************************************************************************** +* txpowertrack_pcie.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpowertrack_pcie( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpowertrack_pcie(void); + +/****************************************************************************** +* txpowertrack_pcie_icut.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpowertrack_pcie_icut( + /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpowertrack_pcie_icut(void); + +/****************************************************************************** +* txpowertrack_sdio.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpowertrack_sdio( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpowertrack_sdio(void); + +/****************************************************************************** +* txpowertrack_sdio_icut.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpowertrack_sdio_icut( + /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpowertrack_sdio_icut(void); + +/****************************************************************************** +* txpowertrack_usb.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpowertrack_usb( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpowertrack_usb(void); + +/****************************************************************************** +* txpowertrack_usb_icut.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpowertrack_usb_icut( + /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpowertrack_usb_icut(void); + +/****************************************************************************** +* txpwr_lmt.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpwr_lmt( /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpwr_lmt(void); + +/****************************************************************************** +* txpwr_lmt_88ee_m2_for_msi.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8188e_txpwr_lmt_88ee_m2_for_msi( + /* tc: Test Chip, mp: mp Chip*/ + struct dm_struct *dm); +u32 odm_get_version_mp_8188e_txpwr_lmt_88ee_m2_for_msi(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/hal/phydm/rtl8188e/phydm_regconfig8188e.c b/hal/phydm/rtl8188e/phydm_regconfig8188e.c new file mode 100644 index 0000000..530556e --- /dev/null +++ b/hal/phydm/rtl8188e/phydm_regconfig8188e.c @@ -0,0 +1,181 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) + +void odm_config_rf_reg_8188e(struct dm_struct *dm, u32 addr, u32 data, + enum rf_path RF_PATH, u32 reg_addr) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifndef SMP_SYNC + unsigned long x; +#endif + struct rtl8192cd_priv *priv = dm->priv; +#endif + + if (addr == 0xffe) { +#ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); +#else + ODM_delay_ms(50); +#endif + } else if (addr == 0xfd) + ODM_delay_ms(5); + else if (addr == 0xfc) + ODM_delay_ms(1); + else if (addr == 0xfb) + ODM_delay_us(50); + else if (addr == 0xfa) + ODM_delay_us(5); + else if (addr == 0xf9) + ODM_delay_us(1); + else { +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + SAVE_INT_AND_CLI(x); + odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data); + RESTORE_INT(x); +#else + odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data); +#endif + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } +} + +void odm_config_rf_radio_a_8188e(struct dm_struct *dm, u32 addr, u32 data) +{ + u32 content = 0x1000; /* RF_Content: radioa_txt */ + u32 maskfor_phy_set = (u32)(content & 0xE000); + + odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set); + + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", + addr, data); +} + +void odm_config_rf_radio_b_8188e(struct dm_struct *dm, u32 addr, u32 data) +{ + u32 content = 0x1001; /* RF_Content: radiob_txt */ + u32 maskfor_phy_set = (u32)(content & 0xE000); + + odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set); + + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", + addr, data); +} + +void odm_config_mac_8188e(struct dm_struct *dm, u32 addr, u8 data) +{ + odm_write_1byte(dm, addr, data); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", + addr, data); +} + +void odm_config_bb_agc_8188e(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data) +{ + odm_set_bb_reg(dm, addr, bitmask, data); + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", + addr, data); +} + +void odm_config_bb_phy_reg_pg_8188e(struct dm_struct *dm, u32 band, u32 rf_path, + u32 tx_num, u32 addr, u32 bitmask, u32 data) +{ + if (addr == 0xfe) { +#ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); +#else + ODM_delay_ms(50); +#endif + } else if (addr == 0xfd) + ODM_delay_ms(5); + else if (addr == 0xfc) + ODM_delay_ms(1); + else if (addr == 0xfb) + ODM_delay_us(50); + else if (addr == 0xfa) + ODM_delay_us(5); + else if (addr == 0xf9) + ODM_delay_us(1); + else { + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", + addr, bitmask, data); + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data); +#endif + } +} + +void odm_config_bb_txpwr_lmt_8188e(struct dm_struct *dm, u8 *regulation, + u8 *band, u8 *bandwidth, u8 *rate_section, + u8 *rf_path, u8 *channel, u8 *power_limit) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + phy_set_tx_power_limit(dm, regulation, band, + bandwidth, rate_section, rf_path, channel, power_limit); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHY_SetTxPowerLimit(dm, regulation, band, + bandwidth, rate_section, rf_path, channel, power_limit); +#endif +} + +void odm_config_bb_phy_8188e(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data) +{ + if (addr == 0xfe) { +#ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); +#else + ODM_delay_ms(50); +#endif + } else if (addr == 0xfd) + ODM_delay_ms(5); + else if (addr == 0xfc) + ODM_delay_ms(1); + else if (addr == 0xfb) + ODM_delay_us(50); + else if (addr == 0xfa) + ODM_delay_us(5); + else if (addr == 0xf9) + ODM_delay_us(1); + else { + if (addr == 0xa24) + dm->rf_calibrate_info.rega24 = data; + odm_set_bb_reg(dm, addr, bitmask, data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + PHYDM_DBG(dm, ODM_COMP_INIT, + "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", + addr, data); + } +} +#endif diff --git a/hal/phydm/rtl8188e/phydm_regconfig8188e.h b/hal/phydm/rtl8188e/phydm_regconfig8188e.h new file mode 100644 index 0000000..83afba8 --- /dev/null +++ b/hal/phydm/rtl8188e/phydm_regconfig8188e.h @@ -0,0 +1,44 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8188E +#define __INC_ODM_REGCONFIG_H_8188E + +#if (RTL8188E_SUPPORT == 1) + +void odm_config_rf_reg_8188e(struct dm_struct *dm, u32 addr, u32 data, + enum rf_path RF_PATH, u32 reg_addr); + +void odm_config_rf_radio_a_8188e(struct dm_struct *dm, u32 addr, u32 data); + +void odm_config_rf_radio_b_8188e(struct dm_struct *dm, u32 addr, u32 data); + +void odm_config_mac_8188e(struct dm_struct *dm, u32 addr, u8 data); + +void odm_config_bb_agc_8188e(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data); + +void odm_config_bb_phy_reg_pg_8188e(struct dm_struct *dm, u32 band, u32 rf_path, + u32 tx_num, u32 addr, u32 bitmask, + u32 data); + +void odm_config_bb_phy_8188e(struct dm_struct *dm, u32 addr, u32 bitmask, + u32 data); + +void odm_config_bb_txpwr_lmt_8188e(struct dm_struct *dm, u8 *regulation, + u8 *band, u8 *bandwidth, u8 *rate_section, + u8 *rf_path, u8 *channel, u8 *power_limit); + +#endif +#endif /* end of SUPPORT */ diff --git a/hal/phydm/rtl8188e/phydm_rtl8188e.c b/hal/phydm/rtl8188e/phydm_rtl8188e.c new file mode 100644 index 0000000..0e9c890 --- /dev/null +++ b/hal/phydm/rtl8188e/phydm_rtl8188e.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" + +#include "../phydm_precomp.h" + +#if (RTL8188E_SUPPORT == 1) + +s8 phydm_cck_rssi_8188e(struct dm_struct *dm, u16 lna_idx, u8 vga_idx) +{ + s8 rx_pwr_all = 0; + s8 lna_gain = 0; + /*only use lna0/1/2/3/7*/ + s8 lna_gain_table_0[8] = {17, -1, -13, 0, -32, -35, -38, -36}; + /*only use lna3 /7*/ + s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; + /*only use lna1/3/5/7*/ + s8 lna_gain_table_2[8] = {17, -1, -13, -17, -32, -43, -38, -47}; + + if (dm->cut_version >= ODM_CUT_I) { /*SMIC*/ + if (dm->ext_lna == 0x1) { + switch (dm->type_glna) { + case 0x2: /*eLNA 14dB*/ + lna_gain = lna_gain_table_2[lna_idx]; + break; + default: + lna_gain = lna_gain_table_0[lna_idx]; + break; + } + } else { + lna_gain = lna_gain_table_0[lna_idx]; + } + } else { /*TSMC*/ + lna_gain = lna_gain_table_1[lna_idx]; + } + + rx_pwr_all = lna_gain - (2 * vga_idx); + + return rx_pwr_all; +} +#endif diff --git a/hal/phydm/rtl8188e/phydm_rtl8188e.h b/hal/phydm/rtl8188e/phydm_rtl8188e.h new file mode 100644 index 0000000..99ebb27 --- /dev/null +++ b/hal/phydm/rtl8188e/phydm_rtl8188e.h @@ -0,0 +1,21 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + *****************************************************************************/ +#ifndef __ODM_RTL8188E_H__ +#define __ODM_RTL8188E_H__ + +#if (RTL8188E_SUPPORT == 1) +s8 phydm_cck_rssi_8188e(struct dm_struct *dm, u16 lna_idx, u8 vga_idx); +#endif +#endif \ No newline at end of file diff --git a/hal/phydm/rtl8188e/version_rtl8188e.h b/hal/phydm/rtl8188e/version_rtl8188e.h new file mode 100644 index 0000000..84df3d9 --- /dev/null +++ b/hal/phydm/rtl8188e/version_rtl8188e.h @@ -0,0 +1,34 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2017 Realtek Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * The full GNU General Public License is included in this distribution in the + * file called LICENSE. + * + * Contact Information: + * wlanfae + * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, + * Hsinchu 300, Taiwan. + * + * Larry Finger + * + *****************************************************************************/ +/*RTL8188E PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8188E 20171218 +#define COMMIT_BY_8188E "RF_Eason" +#define RELEASE_VERSION_8188E 71 diff --git a/hal/phydm/sd4_phydm_2_kernel.mk b/hal/phydm/sd4_phydm_2_kernel.mk new file mode 100644 index 0000000..f11c6ac --- /dev/null +++ b/hal/phydm/sd4_phydm_2_kernel.mk @@ -0,0 +1,188 @@ +EXTRA_CFLAGS += -I$(src)/hal/phydm + +_PHYDM_FILES := hal/phydm/phydm_debug.o \ + hal/phydm/phydm_interface.o\ + hal/phydm/phydm_phystatus.o\ + hal/phydm/phydm_hwconfig.o\ + hal/phydm/phydm.o\ + hal/phydm/phydm_dig.o\ + hal/phydm/phydm_rainfo.o\ + hal/phydm/phydm_adaptivity.o\ + hal/phydm/phydm_cfotracking.o\ + hal/phydm/phydm_noisemonitor.o\ + hal/phydm/phydm_beamforming.o\ + hal/phydm/phydm_dfs.o\ + hal/phydm/txbf/halcomtxbf.o\ + hal/phydm/txbf/haltxbfinterface.o\ + hal/phydm/txbf/phydm_hal_txbf_api.o\ + hal/phydm/phydm_ccx.o\ + hal/phydm/phydm_cck_pd.o\ + hal/phydm/phydm_rssi_monitor.o\ + hal/phydm/phydm_math_lib.o\ + hal/phydm/phydm_api.o\ + hal/phydm/halrf/halrf.o\ + hal/phydm/halrf/halrf_debug.o\ + hal/phydm/halrf/halphyrf_ce.o\ + hal/phydm/halrf/halrf_powertracking_ce.o\ + hal/phydm/halrf/halrf_powertracking.o\ + hal/phydm/halrf/halrf_kfree.o + +ifeq ($(CONFIG_RTL8188E), y) +RTL871X = rtl8188e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\ + hal/phydm/$(RTL871X)/hal8188erateadaptive.o\ + hal/phydm/$(RTL871X)/phydm_rtl8188e.o +endif + +ifeq ($(CONFIG_RTL8192E), y) +RTL871X = rtl8192e +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192e.o +endif + + +ifeq ($(CONFIG_RTL8812A), y) +RTL871X = rtl8812a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\ + hal/phydm/$(RTL871X)/phydm_rtl8812a.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + +ifeq ($(CONFIG_RTL8821A), y) +RTL871X = rtl8821a +_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\ + hal/phydm/rtl8821a/halhwimg8821a_bb.o\ + hal/phydm/rtl8821a/halhwimg8821a_rf.o\ + hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\ + hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\ + hal/phydm/rtl8821a/phydm_regconfig8821a.o\ + hal/phydm/rtl8821a/phydm_rtl8821a.o\ + hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\ + hal/phydm/txbf/haltxbfjaguar.o +endif + + +ifeq ($(CONFIG_RTL8723B), y) +RTL871X = rtl8723b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\ + hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723b.o +endif + + +ifeq ($(CONFIG_RTL8814A), y) +RTL871X = rtl8814a +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\ + hal/phydm/$(RTL871X)/phydm_rtl8814a.o\ + hal/phydm/txbf/haltxbf8814a.o +endif + + +ifeq ($(CONFIG_RTL8723C), y) +RTL871X = rtl8703b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8703b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8703b.o +endif + +ifeq ($(CONFIG_RTL8723D), y) +RTL871X = rtl8723d +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\ + hal/phydm/$(RTL871X)/phydm_rtl8723d.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8723d.o +endif + + +ifeq ($(CONFIG_RTL8710B), y) +RTL871X = rtl8710b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\ + hal/phydm/$(RTL871X)/phydm_rtl8710b.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8710b.o +endif + + +ifeq ($(CONFIG_RTL8188F), y) +RTL871X = rtl8188f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \ + hal/phydm/$(RTL871X)/phydm_rtl8188f.o +endif + +ifeq ($(CONFIG_RTL8822B), y) +RTL871X = rtl8822b +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \ + hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \ + hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \ + hal/phydm/$(RTL871X)/phydm_rtl8822b.o + +_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o +endif + + +ifeq ($(CONFIG_RTL8821C), y) +RTL871X = rtl8821c +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \ + hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \ + hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \ + hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\ + hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o +endif +ifeq ($(CONFIG_RTL8192F), y) +RTL871X = rtl8192f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\ + hal/phydm/$(RTL871X)/phydm_rtl8192f.o\ + hal/phydm/halrf/$(RTL871X)/halrf_8192f.o +endif + +ifeq ($(CONFIG_RTL8198F), y) +RTL871X = rtl8198f +_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\ + hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\ + hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\ + hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\ + hal/phydm/$(RTL871X)/phydm_regconfig8198f.o +endif