Enabled regd source selection
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@ -20,6 +20,9 @@
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#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0
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#define RTL8188E_FPGA_TRUE_PHY_VERIFICATION 0
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/* ***** temporarily flag ******* */
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/* ***** temporarily flag ******* */
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#define CONFIG_REGD_SRC_FROM_OS /* default regd source selection */
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/*
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/*
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* Public General Config
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* Public General Config
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*/
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*/
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