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ivanovborislav
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTL8188E_CMD_H__
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#define __RTL8188E_CMD_H__
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#if 0
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enum cmd_msg_element_id {
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NONE_CMDMSG_EID,
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AP_OFFLOAD_EID = 0,
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SET_PWRMODE_EID = 1,
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JOINBSS_RPT_EID = 2,
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RSVD_PAGE_EID = 3,
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RSSI_4_EID = 4,
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RSSI_SETTING_EID = 5,
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MACID_CONFIG_EID = 6,
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MACID_PS_MODE_EID = 7,
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P2P_PS_OFFLOAD_EID = 8,
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SELECTIVE_SUSPEND_ROF_CMD = 9,
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P2P_PS_CTW_CMD_EID = 32,
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MAX_CMDMSG_EID
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};
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#else
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typedef enum _RTL8188E_H2C_CMD_ID {
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/* Class Common */
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H2C_COM_RSVD_PAGE = 0x00,
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H2C_COM_MEDIA_STATUS_RPT = 0x01,
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H2C_COM_SCAN = 0x02,
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H2C_COM_KEEP_ALIVE = 0x03,
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H2C_COM_DISCNT_DECISION = 0x04,
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#ifndef CONFIG_WOWLAN
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H2C_COM_WWLAN = 0x05,
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#endif
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H2C_COM_INIT_OFFLOAD = 0x06,
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H2C_COM_REMOTE_WAKE_CTL = 0x07,
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H2C_COM_AP_OFFLOAD = 0x08,
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H2C_COM_BCN_RSVD_PAGE = 0x09,
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H2C_COM_PROB_RSP_RSVD_PAGE = 0x0A,
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/* Class PS */
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H2C_PS_PWR_MODE = 0x20,
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H2C_PS_TUNE_PARA = 0x21,
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H2C_PS_TUNE_PARA_2 = 0x22,
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H2C_PS_LPS_PARA = 0x23,
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H2C_PS_P2P_OFFLOAD = 0x24,
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/* Class DM */
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H2C_DM_MACID_CFG = 0x40,
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H2C_DM_TXBF = 0x41,
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H2C_RSSI_REPORT = 0x42,
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/* Class BT */
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H2C_BT_COEX_MASK = 0x60,
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H2C_BT_COEX_GPIO_MODE = 0x61,
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H2C_BT_DAC_SWING_VAL = 0x62,
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H2C_BT_PSD_RST = 0x63,
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/* Class Remote WakeUp */
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#ifdef CONFIG_WOWLAN
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H2C_COM_WWLAN = 0x80,
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H2C_COM_REMOTE_WAKE_CTRL = 0x81,
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H2C_COM_AOAC_GLOBAL_INFO = 0x82,
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H2C_COM_AOAC_RSVD_PAGE = 0x83,
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#endif
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/* Class */
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/* H2C_RESET_TSF =0xc0, */
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} RTL8188E_H2C_CMD_ID;
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#endif
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struct cmd_msg_parm {
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u8 eid; /* element id */
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u8 sz; /* sz */
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u8 buf[6];
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};
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enum {
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PWRS
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};
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typedef struct _SETPWRMODE_PARM {
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u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
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/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
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u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
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u8 AwakeInterval; /* unit: beacon interval */
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u8 bAllQueueUAPSD;
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u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
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} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
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struct H2C_SS_RFOFF_PARAM {
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u8 ROFOn; /* 1: on, 0:off */
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u16 gpio_period; /* unit: 1024 us */
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} __attribute__((packed));
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typedef struct JOINBSSRPT_PARM_88E {
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u8 OpMode; /* RT_MEDIA_STATUS */
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#ifdef CONFIG_WOWLAN
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u8 MacID; /* MACID */
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#endif /* CONFIG_WOWLAN */
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} JOINBSSRPT_PARM_88E, *PJOINBSSRPT_PARM_88E;
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#if 0
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/* move to hal_com_h2c.h */
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typedef struct _RSVDPAGE_LOC_88E {
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u8 LocProbeRsp;
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u8 LocPsPoll;
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u8 LocNullData;
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u8 LocQosNull;
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u8 LocBTQosNull;
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#ifdef CONFIG_WOWLAN
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u8 LocRemoteCtrlInfo;
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u8 LocArpRsp;
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u8 LocNbrAdv;
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u8 LocGTKRsp;
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u8 LocGTKInfo;
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u8 LocProbeReq;
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u8 LocNetList;
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#endif /* CONFIG_WOWLAN */
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} RSVDPAGE_LOC_88E, *PRSVDPAGE_LOC_88E;
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#endif
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/* host message to firmware cmd */
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void rtl8188e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
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void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
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s32 FillH2CCmd_88E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
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/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
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u8 GetTxBufferRsvdPageNum8188E(_adapter *padapter, bool wowlan);
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#ifdef CONFIG_P2P
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void rtl8188e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
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#endif /* CONFIG_P2P */
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/* #define H2C_8188E_RSVDPAGE_LOC_LEN 5 */
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/* #define H2C_8188E_AOAC_RSVDPAGE_LOC_LEN 7 */
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/* ---------------------------------------------------------------------------------------------------------
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* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
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* ---------------------------------------------------------------------------------------------------------
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* */
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#if 0
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/* move to hal_com_h2c.h
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* _RSVDPAGE_LOC_CMD_0x00 */
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#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
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#define SET_8188E_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
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#define SET_8188E_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
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#define SET_8188E_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
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/* AOAC_RSVDPAGE_LOC_0x83 */
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#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
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#define SET_8188E_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
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#endif
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#endif/* __RTL8188E_CMD_H__ */
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@ -0,0 +1,27 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTL8188E_DM_H__
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#define __RTL8188E_DM_H__
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void rtl8188e_init_dm_priv(PADAPTER Adapter);
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void rtl8188e_deinit_dm_priv(PADAPTER Adapter);
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void rtl8188e_InitHalDm(PADAPTER Adapter);
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void rtl8188e_HalDmWatchDog(PADAPTER Adapter);
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/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
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/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
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#endif
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@ -0,0 +1,321 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTL8188E_HAL_H__
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#define __RTL8188E_HAL_H__
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/* #include "hal_com.h" */
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#include "hal_data.h"
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/* include HAL Related header after HAL Related compiling flags */
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#include "rtl8188e_spec.h"
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#include "Hal8188EPhyReg.h"
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#include "Hal8188EPhyCfg.h"
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#include "rtl8188e_rf.h"
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#include "rtl8188e_dm.h"
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#include "rtl8188e_recv.h"
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#include "rtl8188e_xmit.h"
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#include "rtl8188e_cmd.h"
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#include "rtl8188e_led.h"
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#include "Hal8188EPwrSeq.h"
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#ifdef DBG_CONFIG_ERROR_DETECT
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#include "rtl8188e_sreset.h"
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#endif
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/* --------------------------------------------------------------------- */
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/* RTL8188E Power Configuration CMDs for USB/SDIO/PCIE interfaces */
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/* --------------------------------------------------------------------- */
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#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
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#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
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#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
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#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
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#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
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#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
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#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
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#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
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#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
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#if 1 /* download firmware related data structure */
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#define MAX_FW_8188E_SIZE 0x8000 /* 32768, 32k / 16384, 16k */
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#define FW_8188E_SIZE 0x4000 /* 16384, 16k */
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#define FW_8188E_SIZE_2 0x8000 /* 32768, 32k */
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#define FW_8188E_START_ADDRESS 0x1000
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#define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */
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#define IS_FW_HEADER_EXIST_88E(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88E0)
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typedef struct _RT_FIRMWARE_8188E {
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FIRMWARE_SOURCE eFWSource;
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#ifdef CONFIG_EMBEDDED_FWIMG
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u8 *szFwBuffer;
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#else
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u8 szFwBuffer[MAX_FW_8188E_SIZE];
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#endif
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u32 ulFwLength;
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} RT_FIRMWARE_8188E, *PRT_FIRMWARE_8188E;
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/*
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* This structure must be cared byte-ordering
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* */
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typedef struct _RT_8188E_FIRMWARE_HDR {
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/* 8-byte alinment required */
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/* --- LONG WORD 0 ---- */
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u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
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u8 Category; /* AP/NIC and USB/PCI */
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u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
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u16 Version; /* FW Version */
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u8 Subversion; /* FW Subversion, default 0x00 */
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u16 Rsvd1;
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/* --- LONG WORD 1 ---- */
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u8 Month; /* Release time Month field */
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u8 Date; /* Release time Date field */
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u8 Hour; /* Release time Hour field */
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u8 Minute; /* Release time Minute field */
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u16 RamCodeSize; /* The size of RAM code */
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u8 Foundry;
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u8 Rsvd2;
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/* --- LONG WORD 2 ---- */
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u32 SvnIdx; /* The SVN entry index */
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u32 Rsvd3;
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/* --- LONG WORD 3 ---- */
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u32 Rsvd4;
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u32 Rsvd5;
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} RT_8188E_FIRMWARE_HDR, *PRT_8188E_FIRMWARE_HDR;
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#endif /* download firmware related data structure */
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#define DRIVER_EARLY_INT_TIME_8188E 0x05
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#define BCN_DMA_ATIME_INT_TIME_8188E 0x02
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/* #define MAX_RX_DMA_BUFFER_SIZE_88E 0x2400 */ /* 9k for 88E nornal chip , */ /* MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
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#ifdef CONFIG_USB_HCI
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#define RX_DMA_SIZE_88E(__Adapter) 0x2800
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#else
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#define RX_DMA_SIZE_88E(__Adapter) ((!IS_VENDOR_8188E_I_CUT_SERIES(__Adapter))?0x2800:0x4000)
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#endif
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#ifdef CONFIG_WOWLAN
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#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
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#else
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#define RESV_FMWF 0
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#endif
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#define RX_DMA_RESERVD_FW_FEATURE 0x200 /* for tx report (64*8) */
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#define MAX_RX_DMA_BUFFER_SIZE_88E(__Adapter) (RX_DMA_SIZE_88E(__Adapter)-RX_DMA_RESERVD_FW_FEATURE)
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#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */
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#define PAGE_SIZE_TX_88E PAGE_SIZE_128
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/* Note: We will divide number of page equally for each queue other than public queue!
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* 22k = 22528 bytes = 176 pages (@page = 128 bytes)
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* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_88E
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* 1 ps-poll / 1 null-data /1 prob_rsp /1 QOS null-data = 4 pages */
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#define BCNQ_PAGE_NUM_88E (MAX_BEACON_LEN / PAGE_SIZE_TX_88E + 4) /*0x09*/
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/* For WoWLan , more reserved page */
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#ifdef CONFIG_WOWLAN
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#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
|
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#define WOWLAN_KEEP_ALIVE_PAGE 0x02 /*for keep alive packet*/
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#else
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#define WOWLAN_KEEP_ALIVE_PAGE 0x00
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#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
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/* 1 ArpRsp + 2 NbrAdv + 2 NDPInfo + 1 RCI + 1 AOAC = 7 pages */
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#define WOWLAN_PAGE_NUM_88E (0x07+ WOWLAN_KEEP_ALIVE_PAGE)
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#else
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#define WOWLAN_PAGE_NUM_88E 0x00
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#endif
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||||
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/* Note:
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Tx FIFO Size : previous CUT:22K /I_CUT after:32KB
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Tx page Size : 128B
|
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Total page numbers : 176(0xB0) / 256(0x100)
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*/
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||||
#ifdef CONFIG_USB_HCI
|
||||
#define TOTAL_PAGE_NUMBER_88E(_Adapter) (0xB0 - 1)
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#else
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||||
#define TOTAL_PAGE_NUMBER_88E(_Adapter) ((IS_VENDOR_8188E_I_CUT_SERIES(_Adapter)?0x100:0xB0) - 1)/* must reserved 1 page for dma issue */
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#endif
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#define TX_TOTAL_PAGE_NUMBER_88E(_Adapter) (TOTAL_PAGE_NUMBER_88E(_Adapter) - BCNQ_PAGE_NUM_88E - WOWLAN_PAGE_NUM_88E)
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#define TX_PAGE_BOUNDARY_88E(_Adapter) (TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1) /* beacon header start address */
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#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) TX_TOTAL_PAGE_NUMBER_88E(_Adapter)
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#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E(_Adapter) (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_88E(_Adapter) + 1)
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/* For Normal Chip Setting
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||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
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||||
#define NORMAL_PAGE_NUM_HPQ_88E 0x0
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#define NORMAL_PAGE_NUM_LPQ_88E 0x09
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||||
#define NORMAL_PAGE_NUM_NPQ_88E 0x0
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||||
/* Note: For Normal Chip Setting, modify later */
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#define WMM_NORMAL_PAGE_NUM_HPQ_88E 0x29
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||||
#define WMM_NORMAL_PAGE_NUM_LPQ_88E 0x1C
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#define WMM_NORMAL_PAGE_NUM_NPQ_88E 0x1C
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||||
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||||
/* -------------------------------------------------------------------------
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||||
* Chip specific
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||||
* ------------------------------------------------------------------------- */
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||||
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22) & 0x3)
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||||
#define CHIP_BONDING_92C_1T2R 0x1
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||||
#define CHIP_BONDING_88C_USB_MCARD 0x2
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||||
#define CHIP_BONDING_88C_USB_HP 0x1
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
* Channel Plan
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
#define EFUSE_REAL_CONTENT_LEN 512
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||||
#define EFUSE_MAP_LEN 128
|
||||
#define EFUSE_MAX_SECTION 16
|
||||
#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
|
||||
/*
|
||||
* <Roger_Notes>
|
||||
* To prevent out of boundary programming case,
|
||||
* leave 1byte and program full section
|
||||
* 9bytes + 1byt + 5bytes and pre 1byte.
|
||||
* For worst case:
|
||||
* | 1byte|----8bytes----|1byte|--5bytes--|
|
||||
* | | Reserved(14bytes) |
|
||||
* */
|
||||
#define EFUSE_OOB_PROTECT_BYTES 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
|
||||
|
||||
#define EFUSE_REAL_CONTENT_LEN_88E 256
|
||||
#define EFUSE_MAP_LEN_88E 512
|
||||
#define EFUSE_MAX_SECTION_88E 64
|
||||
#define EFUSE_MAX_WORD_UNIT_88E 4
|
||||
#define EFUSE_IC_ID_OFFSET_88E 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
|
||||
#define AVAILABLE_EFUSE_ADDR_88E(addr) (addr < EFUSE_REAL_CONTENT_LEN_88E)
|
||||
/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
|
||||
* 9bytes + 1byt + 5bytes and pre 1byte.
|
||||
* For worst case:
|
||||
* | 2byte|----8bytes----|1byte|--7bytes--| */ /* 92D */
|
||||
#define EFUSE_OOB_PROTECT_BYTES_88E 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
|
||||
#define EFUSE_PROTECT_BYTES_BANK_88E 16
|
||||
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */
|
||||
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
|
||||
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
/* #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
|
||||
|
||||
/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* according to the define in the rtw_xmit.h, rtw_recv.h */
|
||||
#define TX_DESC_NUM_8188EE TXDESC_NUM /* 128 */
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
/*#define BE_QUEUE_TX_DESC_NUM_8188EE (TXDESC_NUM<<1)*/ /* 256 */
|
||||
#define BE_QUEUE_TX_DESC_NUM_8188EE ((TXDESC_NUM<<1)+(TXDESC_NUM>>1)) /* 320 */
|
||||
/*#define BE_QUEUE_TX_DESC_NUM_8188EE ((TXDESC_NUM<<1)+TXDESC_NUM)*/ /* 384 */
|
||||
#else
|
||||
#define BE_QUEUE_TX_DESC_NUM_8188EE TXDESC_NUM /* 128 */
|
||||
/*#define BE_QUEUE_TX_DESC_NUM_8188EE (TXDESC_NUM+(TXDESC_NUM>>1)) */ /* 192 */
|
||||
#endif
|
||||
|
||||
void InterruptRecognized8188EE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
|
||||
void UpdateInterruptMask8188EE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
/* rtl8188e_hal_init.c */
|
||||
|
||||
s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
|
||||
void _8051Reset88E(PADAPTER padapter);
|
||||
void rtl8188e_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
|
||||
s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8188E(PADAPTER padapter);
|
||||
void Hal_InitPGData88E(PADAPTER padapter);
|
||||
void Hal_EfuseParseIDCode88E(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_ReadTxPowerInfo88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
|
||||
void Hal_EfuseParseEEPROMVer88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void rtl8188e_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID88E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadAntennaDiversity88E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadThermalMeter_88E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_EfuseParseXtal_8188E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBoardType88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadPowerSavingMode88E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadPAType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadAmplifierType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadRFEType_8188E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
|
||||
BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter);
|
||||
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
|
||||
void InitBeaconParameters_8188e(_adapter *adapter);
|
||||
void SetBeaconRelatedRegisters8188E(PADAPTER padapter);
|
||||
|
||||
void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8188e(_adapter *adapter);
|
||||
|
||||
void rtl8188e_start_thread(_adapter *padapter);
|
||||
void rtl8188e_stop_thread(_adapter *padapter);
|
||||
|
||||
void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter, int data_len);
|
||||
#ifdef CONFIG_IOL_EFUSE_PATCH
|
||||
s32 rtl8188e_iol_efuse_patch(PADAPTER padapter);
|
||||
#endif/* CONFIG_IOL_EFUSE_PATCH */
|
||||
void _InitTransferPageSize(PADAPTER padapter);
|
||||
|
||||
u8 SetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8188E(PADAPTER padapter, u8 variable, u8 *val);
|
||||
|
||||
u8
|
||||
GetHalDefVar8188E(
|
||||
PADAPTER Adapter,
|
||||
HAL_DEF_VARIABLE eVariable,
|
||||
void *pValue
|
||||
);
|
||||
#ifdef CONFIG_GPIO_API
|
||||
int rtl8188e_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
|
||||
#endif
|
||||
#endif /* __RTL8188E_HAL_H__ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188E_LED_H__
|
||||
#define __RTL8188E_LED_H__
|
||||
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8188eu_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8188eu_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8188ee_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8188ee_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
void rtl8188es_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8188es_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif /*CONFIG_RTW_SW_LED*/
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188E_RECV_H__
|
||||
#define __RTL8188E_RECV_H__
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
|
||||
/* #define MAX_RECVBUF_SZ (9100) */
|
||||
/* #else */
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K
|
||||
* #endif */
|
||||
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (10240)
|
||||
|
||||
#endif
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
#define TX_RPT1_PKT_LEN 8
|
||||
|
||||
typedef struct rxreport_8188e {
|
||||
/* Offset 0 */
|
||||
u32 pktlen:14;
|
||||
u32 crc32:1;
|
||||
u32 icverr:1;
|
||||
u32 drvinfosize:4;
|
||||
u32 security:3;
|
||||
u32 qos:1;
|
||||
u32 shift:2;
|
||||
u32 physt:1;
|
||||
u32 swdec:1;
|
||||
u32 ls:1;
|
||||
u32 fs:1;
|
||||
u32 eor:1;
|
||||
u32 own:1;
|
||||
|
||||
/* Offset 4 */
|
||||
u32 macid:5;
|
||||
u32 tid:4;
|
||||
u32 hwrsvd:4;
|
||||
u32 amsdu:1;
|
||||
u32 paggr:1;
|
||||
u32 faggr:1;
|
||||
u32 a1fit:4;
|
||||
u32 a2fit:4;
|
||||
u32 pam:1;
|
||||
u32 pwr:1;
|
||||
u32 md:1;
|
||||
u32 mf:1;
|
||||
u32 type:2;
|
||||
u32 mc:1;
|
||||
u32 bc:1;
|
||||
|
||||
/* Offset 8 */
|
||||
u32 seq:12;
|
||||
u32 frag:4;
|
||||
u32 nextpktlen:14;
|
||||
u32 nextind:1;
|
||||
u32 rsvd0831:1;
|
||||
|
||||
/* Offset 12 */
|
||||
u32 rxmcs:6;
|
||||
u32 rxht:1;
|
||||
u32 gf:1;
|
||||
u32 splcp:1;
|
||||
u32 bw:1;
|
||||
u32 htc:1;
|
||||
u32 eosp:1;
|
||||
u32 bssidfit:2;
|
||||
u32 rpt_sel:2;
|
||||
u32 rsvd1216:13;
|
||||
u32 pattern_match:1;
|
||||
u32 unicastwake:1;
|
||||
u32 magicwake:1;
|
||||
|
||||
/* Offset 16 */
|
||||
/*
|
||||
u32 pattern0match:1;
|
||||
u32 pattern1match:1;
|
||||
u32 pattern2match:1;
|
||||
u32 pattern3match:1;
|
||||
u32 pattern4match:1;
|
||||
u32 pattern5match:1;
|
||||
u32 pattern6match:1;
|
||||
u32 pattern7match:1;
|
||||
u32 pattern8match:1;
|
||||
u32 pattern9match:1;
|
||||
u32 patternamatch:1;
|
||||
u32 patternbmatch:1;
|
||||
u32 patterncmatch:1;
|
||||
u32 rsvd1613:19;
|
||||
*/
|
||||
u32 rsvd16;
|
||||
|
||||
/* Offset 20 */
|
||||
u32 tsfl;
|
||||
|
||||
/* Offset 24 */
|
||||
u32 bassn:12;
|
||||
u32 bavld:1;
|
||||
u32 rsvd2413:19;
|
||||
} RXREPORT, *PRXREPORT;
|
||||
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8188es_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8188es_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8188eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
s32 rtl8188eu_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8188eu_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8188ee_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8188ee_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8188e_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *prxstat);
|
||||
|
||||
#endif /* __RTL8188E_RECV_H__ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188E_RF_H__
|
||||
#define __RTL8188E_RF_H__
|
||||
|
||||
|
||||
|
||||
int PHY_RF6052_Config8188E(PADAPTER Adapter);
|
||||
void rtl8188e_RF_ChangeTxPath(PADAPTER Adapter,
|
||||
u16 DataRate);
|
||||
void rtl8188e_PHY_RF6052SetBandwidth(
|
||||
PADAPTER Adapter,
|
||||
enum channel_width Bandwidth);
|
||||
|
||||
#endif/* __RTL8188E_RF_H__ */
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188E_SPEC_H__
|
||||
#define __RTL8188E_SPEC_H__
|
||||
|
||||
|
||||
/* ************************************************************
|
||||
* 8188E Regsiter offset definition
|
||||
* ************************************************************ */
|
||||
|
||||
|
||||
/* ************************************************************
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_BB_PAD_CTRL 0x0064
|
||||
#define REG_HMEBOX_E0 0x0088
|
||||
#define REG_HMEBOX_E1 0x008A
|
||||
#define REG_HMEBOX_E2 0x008C
|
||||
#define REG_HMEBOX_E3 0x008E
|
||||
#define REG_HMEBOX_EXT_0 0x01F0
|
||||
#define REG_HMEBOX_EXT_1 0x01F4
|
||||
#define REG_HMEBOX_EXT_2 0x01F8
|
||||
#define REG_HMEBOX_EXT_3 0x01FC
|
||||
#define REG_HIMR_88E 0x00B0 /* RTL8188E */
|
||||
#define REG_HISR_88E 0x00B4 /* RTL8188E */
|
||||
#define REG_HIMRE_88E 0x00B8 /* RTL8188E */
|
||||
#define REG_HISRE_88E 0x00BC /* RTL8188E */
|
||||
|
||||
#define REG_DBI_WDATA_8188E 0x0348 /* DBI Write data */
|
||||
#define REG_DBI_RDATA_8188E 0x034C /* DBI Read data */
|
||||
#define REG_DBI_ADDR_8188E 0x0350 /* DBI Address */
|
||||
#define REG_DBI_FLAG_8188E 0x0352 /* DBI Read/Write Flag */
|
||||
#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */
|
||||
#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */
|
||||
#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */
|
||||
|
||||
#define REG_MACID_NO_LINK_0 0x0484
|
||||
#define REG_MACID_NO_LINK_1 0x0488
|
||||
#define REG_MACID_PAUSE_0 0x048c
|
||||
#define REG_MACID_PAUSE_1 0x0490
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
|
||||
#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
|
||||
#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
|
||||
#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_HRPWM_8188E 0x0361 /* PCIe RPWM */
|
||||
#define REG_PCIE_HCPWM_8188E 0x0363 /* PCIe CPWM */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x01a4
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x01a8
|
||||
#endif
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
#define EEPROM_RF_GAIN_OFFSET 0xC1
|
||||
#define EEPROM_RF_GAIN_VAL 0xF6
|
||||
#define EEPROM_THERMAL_OFFSET 0xF5
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)
|
||||
* ----------------------------------------------------------------------------
|
||||
* IOL config for REG_FDHM0(Reg0x88) */
|
||||
#define CMD_INIT_LLT BIT0
|
||||
#define CMD_READ_EFUSE_MAP BIT1
|
||||
#define CMD_EFUSE_PATCH BIT2
|
||||
#define CMD_IOCONFIG BIT3
|
||||
#define CMD_INIT_LLT_ERR BIT4
|
||||
#define CMD_READ_EFUSE_MAP_ERR BIT5
|
||||
#define CMD_EFUSE_PATCH_ERR BIT6
|
||||
#define CMD_IOCONFIG_ERR BIT7
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* Redifine register definition for compatibility
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* TODO: use these definition when using REG_xxx naming rule.
|
||||
* NOTE: DO NOT Remove these definition. Use later. */
|
||||
#define ISR_88E REG_HISR_88E
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* #define IMR_RX_MASK (IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E)
|
||||
|
||||
#ifdef CONFIG_CONCURRENT_MODE
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E)
|
||||
#else
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E)
|
||||
#endif
|
||||
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E)
|
||||
#endif
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8192C EEPROM/EFUSE share register definition.
|
||||
* ---------------------------------------------------------------------------- */
|
||||
|
||||
#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */
|
||||
#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */
|
||||
|
||||
#endif /* __RTL8188E_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8188E_SRESET_H_
|
||||
#define _RTL8188E_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8188e_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8188e_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188E_XMIT_H__
|
||||
#define __RTL8188E_XMIT_H__
|
||||
|
||||
|
||||
|
||||
|
||||
/* For 88e early mode */
|
||||
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
|
||||
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
|
||||
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
|
||||
|
||||
/*
|
||||
* defined for TX DESC Operation
|
||||
* */
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
/* OFFSET 0 */
|
||||
#define OFFSET_SZ 0
|
||||
#define OFFSET_SHT 16
|
||||
#define BMC BIT(24)
|
||||
#define LSG BIT(26)
|
||||
#define FSG BIT(27)
|
||||
#define OWN BIT(31)
|
||||
|
||||
|
||||
/* OFFSET 4 */
|
||||
#define PKT_OFFSET_SZ 0
|
||||
#define QSEL_SHT 8
|
||||
#define RATE_ID_SHT 16
|
||||
#define NAVUSEHDR BIT(20)
|
||||
#define SEC_TYPE_SHT 22
|
||||
#define PKT_OFFSET_SHT 26
|
||||
|
||||
/* OFFSET 8 */
|
||||
#define AGG_EN BIT(12)
|
||||
#define AGG_BK BIT(16)
|
||||
#define AMPDU_DENSITY_SHT 20
|
||||
#define ANTSEL_A BIT(24)
|
||||
#define ANTSEL_B BIT(25)
|
||||
#define TX_ANT_CCK_SHT 26
|
||||
#define TX_ANTL_SHT 28
|
||||
#define TX_ANT_HT_SHT 30
|
||||
|
||||
/* OFFSET 12 */
|
||||
#define SEQ_SHT 16
|
||||
#define EN_HWSEQ BIT(31)
|
||||
|
||||
/* OFFSET 16 */
|
||||
#define QOS BIT(6)
|
||||
#define HW_SSN BIT(7)
|
||||
#define USERATE BIT(8)
|
||||
#define DISDATAFB BIT(10)
|
||||
#define CTS_2_SELF BIT(11)
|
||||
#define RTS_EN BIT(12)
|
||||
#define HW_RTS_EN BIT(13)
|
||||
#define DATA_SHORT BIT(24)
|
||||
#define PWR_STATUS_SHT 15
|
||||
#define DATA_SC_SHT 20
|
||||
#define DATA_BW BIT(25)
|
||||
|
||||
/* OFFSET 20 */
|
||||
#define RTY_LMT_EN BIT(17)
|
||||
|
||||
|
||||
/* OFFSET 20 */
|
||||
#define SGI BIT(6)
|
||||
#define USB_TXAGG_NUM_SHT 24
|
||||
|
||||
typedef struct txdesc_88e {
|
||||
/* Offset 0 */
|
||||
u32 pktlen:16;
|
||||
u32 offset:8;
|
||||
u32 bmc:1;
|
||||
u32 htc:1;
|
||||
u32 ls:1;
|
||||
u32 fs:1;
|
||||
u32 linip:1;
|
||||
u32 noacm:1;
|
||||
u32 gf:1;
|
||||
u32 own:1;
|
||||
|
||||
/* Offset 4 */
|
||||
u32 macid:6;
|
||||
u32 rsvd0406:2;
|
||||
u32 qsel:5;
|
||||
u32 rd_nav_ext:1;
|
||||
u32 lsig_txop_en:1;
|
||||
u32 pifs:1;
|
||||
u32 rate_id:4;
|
||||
u32 navusehdr:1;
|
||||
u32 en_desc_id:1;
|
||||
u32 sectype:2;
|
||||
u32 rsvd0424:2;
|
||||
u32 pkt_offset:5; /* unit: 8 bytes */
|
||||
u32 rsvd0431:1;
|
||||
|
||||
/* Offset 8 */
|
||||
u32 rts_rc:6;
|
||||
u32 data_rc:6;
|
||||
u32 agg_en:1;
|
||||
u32 rd_en:1;
|
||||
u32 bar_rty_th:2;
|
||||
u32 bk:1;
|
||||
u32 morefrag:1;
|
||||
u32 raw:1;
|
||||
u32 ccx:1;
|
||||
u32 ampdu_density:3;
|
||||
u32 bt_null:1;
|
||||
u32 ant_sel_a:1;
|
||||
u32 ant_sel_b:1;
|
||||
u32 tx_ant_cck:2;
|
||||
u32 tx_antl:2;
|
||||
u32 tx_ant_ht:2;
|
||||
|
||||
/* Offset 12 */
|
||||
u32 nextheadpage:8;
|
||||
u32 tailpage:8;
|
||||
u32 seq:12;
|
||||
u32 cpu_handle:1;
|
||||
u32 tag1:1;
|
||||
u32 trigger_int:1;
|
||||
u32 hwseq_en:1;
|
||||
|
||||
/* Offset 16 */
|
||||
u32 rtsrate:5;
|
||||
u32 ap_dcfe:1;
|
||||
u32 hwseq_sel:2;
|
||||
u32 userate:1;
|
||||
u32 disrtsfb:1;
|
||||
u32 disdatafb:1;
|
||||
u32 cts2self:1;
|
||||
u32 rtsen:1;
|
||||
u32 hw_rts_en:1;
|
||||
u32 port_id:1;
|
||||
u32 pwr_status:3;
|
||||
u32 wait_dcts:1;
|
||||
u32 cts2ap_en:1;
|
||||
u32 data_sc:2;
|
||||
u32 data_stbc:2;
|
||||
u32 data_short:1;
|
||||
u32 data_bw:1;
|
||||
u32 rts_short:1;
|
||||
u32 rts_bw:1;
|
||||
u32 rts_sc:2;
|
||||
u32 vcs_stbc:2;
|
||||
|
||||
/* Offset 20 */
|
||||
u32 datarate:6;
|
||||
u32 sgi:1;
|
||||
u32 try_rate:1;
|
||||
u32 data_ratefb_lmt:5;
|
||||
u32 rts_ratefb_lmt:4;
|
||||
u32 rty_lmt_en:1;
|
||||
u32 data_rt_lmt:6;
|
||||
u32 usb_txagg_num:8;
|
||||
|
||||
/* Offset 24 */
|
||||
u32 txagg_a:5;
|
||||
u32 txagg_b:5;
|
||||
u32 use_max_len:1;
|
||||
u32 max_agg_num:5;
|
||||
u32 mcsg1_max_len:4;
|
||||
u32 mcsg2_max_len:4;
|
||||
u32 mcsg3_max_len:4;
|
||||
u32 mcs7_sgi_max_len:4;
|
||||
|
||||
/* Offset 28 */
|
||||
u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */
|
||||
u32 sw0:8; /* offset 30 */
|
||||
u32 sw1:4;
|
||||
u32 mcs15_sgi_max_len:4;
|
||||
} TXDESC_8188E, *PTXDESC_8188E;
|
||||
|
||||
#define txdesc_set_ccx_sw_88e(txdesc, value) \
|
||||
do { \
|
||||
((struct txdesc_88e *)(txdesc))->sw1 = (((value)>>8) & 0x0f); \
|
||||
((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
|
||||
} while (0)
|
||||
|
||||
struct txrpt_ccx_88e {
|
||||
/* offset 0 */
|
||||
u8 tag1:1;
|
||||
u8 pkt_num:3;
|
||||
u8 txdma_underflow:1;
|
||||
u8 int_bt:1;
|
||||
u8 int_tri:1;
|
||||
u8 int_ccx:1;
|
||||
|
||||
/* offset 1 */
|
||||
u8 mac_id:6;
|
||||
u8 pkt_ok:1;
|
||||
u8 bmc:1;
|
||||
|
||||
/* offset 2 */
|
||||
u8 retry_cnt:6;
|
||||
u8 lifetime_over:1;
|
||||
u8 retry_over:1;
|
||||
|
||||
/* offset 3 */
|
||||
u8 ccx_qtime0;
|
||||
u8 ccx_qtime1;
|
||||
|
||||
/* offset 5 */
|
||||
u8 final_data_rate;
|
||||
|
||||
/* offset 6 */
|
||||
u8 sw1:4;
|
||||
u8 qsel:4;
|
||||
|
||||
/* offset 7 */
|
||||
u8 sw0;
|
||||
};
|
||||
|
||||
#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1<<8))
|
||||
#define txrpt_ccx_qtime_88e(txrpt_ccx) ((txrpt_ccx)->ccx_qtime0+((txrpt_ccx)->ccx_qtime1<<8))
|
||||
|
||||
#define SET_TX_DESC_SEC_TYPE_8188E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
|
||||
void rtl8188e_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen,
|
||||
u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8188es_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8188es_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8188es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8188es_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8188es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
thread_return rtl8188es_xmit_thread(thread_context context);
|
||||
s32 rtl8188es_xmit_buf_handler(PADAPTER padapter);
|
||||
|
||||
#ifdef CONFIG_SDIO_TX_TASKLET
|
||||
void rtl8188es_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8188eu_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8188eu_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8188eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8188eu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8188eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188eu_xmit_buf_handler(PADAPTER padapter);
|
||||
void rtl8188eu_xmit_tasklet(void *priv);
|
||||
s32 rtl8188eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8188ee_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8188ee_free_xmit_priv(PADAPTER padapter);
|
||||
void rtl8188ee_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8188ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8188ee_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8188ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8188ee_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef CONFIG_TX_EARLY_MODE
|
||||
void UpdateEarlyModeInfo8188E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_XMIT_ACK
|
||||
void dump_txrpt_ccx_88e(void *buf);
|
||||
void handle_txrpt_ccx_88e(_adapter *adapter, u8 *buf);
|
||||
#else
|
||||
#define dump_txrpt_ccx_88e(buf) do {} while (0)
|
||||
#define handle_txrpt_ccx_88e(adapter, buf) do {} while (0)
|
||||
#endif /* CONFIG_XMIT_ACK */
|
||||
|
||||
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc);
|
||||
#endif /* __RTL8188E_XMIT_H__ */
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_CMD_H__
|
||||
#define __RTL8188F_CMD_H__
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
enum h2c_cmd_8188F {
|
||||
/* Common Class: 000 */
|
||||
H2C_8188F_RSVD_PAGE = 0x00,
|
||||
H2C_8188F_MEDIA_STATUS_RPT = 0x01,
|
||||
H2C_8188F_SCAN_ENABLE = 0x02,
|
||||
H2C_8188F_KEEP_ALIVE = 0x03,
|
||||
H2C_8188F_DISCON_DECISION = 0x04,
|
||||
H2C_8188F_PSD_OFFLOAD = 0x05,
|
||||
H2C_8188F_AP_OFFLOAD = 0x08,
|
||||
H2C_8188F_BCN_RSVDPAGE = 0x09,
|
||||
H2C_8188F_PROBERSP_RSVDPAGE = 0x0A,
|
||||
H2C_8188F_FCS_RSVDPAGE = 0x10,
|
||||
H2C_8188F_FCS_INFO = 0x11,
|
||||
H2C_8188F_AP_WOW_GPIO_CTRL = 0x13,
|
||||
|
||||
/* PoweSave Class: 001 */
|
||||
H2C_8188F_SET_PWR_MODE = 0x20,
|
||||
H2C_8188F_PS_TUNING_PARA = 0x21,
|
||||
H2C_8188F_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8188F_P2P_LPS_PARAM = 0x23,
|
||||
H2C_8188F_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8188F_PS_SCAN_ENABLE = 0x25,
|
||||
H2C_8188F_SAP_PS_ = 0x26,
|
||||
H2C_8188F_INACTIVE_PS_ = 0x27, /* Inactive_PS */
|
||||
H2C_8188F_FWLPS_IN_IPS_ = 0x28,
|
||||
|
||||
/* Dynamic Mechanism Class: 010 */
|
||||
H2C_8188F_MACID_CFG = 0x40,
|
||||
H2C_8188F_TXBF = 0x41,
|
||||
H2C_8188F_RSSI_SETTING = 0x42,
|
||||
H2C_8188F_AP_REQ_TXRPT = 0x43,
|
||||
H2C_8188F_INIT_RATE_COLLECT = 0x44,
|
||||
H2C_8188F_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
/* BT Class: 011 */
|
||||
H2C_8188F_B_TYPE_TDMA = 0x60,
|
||||
H2C_8188F_BT_INFO = 0x61,
|
||||
H2C_8188F_FORCE_BT_TXPWR = 0x62,
|
||||
H2C_8188F_BT_IGNORE_WLANACT = 0x63,
|
||||
H2C_8188F_DAC_SWING_VALUE = 0x64,
|
||||
H2C_8188F_ANT_SEL_RSV = 0x65,
|
||||
H2C_8188F_WL_OPMODE = 0x66,
|
||||
H2C_8188F_BT_MP_OPER = 0x67,
|
||||
H2C_8188F_BT_CONTROL = 0x68,
|
||||
H2C_8188F_BT_WIFI_CTRL = 0x69,
|
||||
H2C_8188F_BT_FW_PATCH = 0x6A,
|
||||
H2C_8188F_BT_WLAN_CALIBRATION = 0x6D,
|
||||
|
||||
/* WOWLAN Class: 100 */
|
||||
H2C_8188F_WOWLAN = 0x80,
|
||||
H2C_8188F_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8188F_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8188F_AOAC_RSVD_PAGE = 0x83,
|
||||
H2C_8188F_AOAC_RSVD_PAGE2 = 0x84,
|
||||
H2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85,
|
||||
H2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86,
|
||||
H2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87,
|
||||
H2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
|
||||
H2C_8188F_P2P_OFFLOAD = 0x8B,
|
||||
|
||||
H2C_8188F_RESET_TSF = 0xC0,
|
||||
H2C_8188F_MAXID,
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
|
||||
* ---------------------------------------------------------------------------------------------------------
|
||||
* _RSVDPAGE_LOC_CMD_0x00 */
|
||||
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/* _KEEP_ALIVE_CMD_0x03 */
|
||||
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _DISCONNECT_DECISION_CMD_0x04 */
|
||||
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
|
||||
/* _PWR_MOD_CMD_0x20 */
|
||||
#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _PS_TUNE_PARAM_CMD_0x21 */
|
||||
#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
|
||||
#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _MACID_CFG_CMD_0x40 */
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
|
||||
|
||||
/* _RSSI_SETTING_CMD_0x42 */
|
||||
#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
|
||||
#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _AP_REQ_TXRPT_CMD_0x43 */
|
||||
#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_TXPWR_CMD_0x62 */
|
||||
#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_MP_OPER_CMD_0x67 */
|
||||
#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
|
||||
/* _BT_FW_PATCH_0x6A */
|
||||
#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ------------------------------------------- Structure --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- Function Statement --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/* host message to firmware cmd */
|
||||
void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
|
||||
void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
|
||||
/* s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
|
||||
void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter);
|
||||
void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
|
||||
void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
|
||||
|
||||
s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_DM_H__
|
||||
#define __RTL8188F_DM_H__
|
||||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for 8188F dynamic mechanism only
|
||||
*
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* structure and define
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* function prototype
|
||||
* ************************************************************ */
|
||||
|
||||
void rtl8188f_init_dm_priv(PADAPTER padapter);
|
||||
void rtl8188f_deinit_dm_priv(PADAPTER padapter);
|
||||
|
||||
void rtl8188f_InitHalDm(PADAPTER padapter);
|
||||
void rtl8188f_HalDmWatchDog(PADAPTER padapter);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,260 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_HAL_H__
|
||||
#define __RTL8188F_HAL_H__
|
||||
|
||||
#include "hal_data.h"
|
||||
|
||||
#include "rtl8188f_spec.h"
|
||||
#include "rtl8188f_rf.h"
|
||||
#include "rtl8188f_dm.h"
|
||||
#include "rtl8188f_recv.h"
|
||||
#include "rtl8188f_xmit.h"
|
||||
#include "rtl8188f_cmd.h"
|
||||
#include "rtl8188f_led.h"
|
||||
#include "Hal8188FPwrSeq.h"
|
||||
#include "Hal8188FPhyReg.h"
|
||||
#include "Hal8188FPhyCfg.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8188f_sreset.h"
|
||||
#endif
|
||||
|
||||
#define FW_8188F_SIZE 0x8000
|
||||
#define FW_8188F_START_ADDRESS 0x1000
|
||||
#define FW_8188F_END_ADDRESS 0x1FFF /* 0x5FFF */
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8188F(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x88F0)
|
||||
|
||||
typedef struct _RT_FIRMWARE {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_8188F_SIZE];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8188F, *PRT_FIRMWARE_8188F;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
typedef struct _RT_8188F_FIRMWARE_HDR {
|
||||
/* 8-byte alinment required */
|
||||
|
||||
/* --- LONG WORD 0 ---- */
|
||||
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
u8 Category; /* AP/NIC and USB/PCI */
|
||||
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
u16 Version; /* FW Version */
|
||||
u16 Subversion; /* FW Subversion, default 0x00 */
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
u8 Month; /* Release time Month field */
|
||||
u8 Date; /* Release time Date field */
|
||||
u8 Hour; /* Release time Hour field */
|
||||
u8 Minute; /* Release time Minute field */
|
||||
u16 RamCodeSize; /* The size of RAM code */
|
||||
u16 Rsvd2;
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
u32 SvnIdx; /* The SVN entry index */
|
||||
u32 Rsvd3;
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
} RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8188F 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8188F 0x02
|
||||
|
||||
/* for 8188F
|
||||
* TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
|
||||
#define PAGE_SIZE_TX_8188F 128
|
||||
#define PAGE_SIZE_RX_8188F 8
|
||||
|
||||
#define RX_DMA_SIZE_8188F 0x4000 /* 16K */
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8188F 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8188F 0x80 /* 128B, reserved for tx report */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#define RX_DMA_BOUNDARY_8188F (RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1)
|
||||
|
||||
/* Note: We will divide number of page equally for each queue other than public queue! */
|
||||
|
||||
/* For General Reserved Page Number(Beacon Queue is reserved page)
|
||||
* BCN rsvd_page_num = MAX_BEACON_LEN / PAGE_SIZE_TX_8188F,
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1, CTS-2-SELF / LTE QoS Null */
|
||||
|
||||
#define BCNQ_PAGE_NUM_8188F (MAX_BEACON_LEN / PAGE_SIZE_TX_8188F + 6) /*0x08*/
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt:1 ,PNO: 6
|
||||
* NS offload:2 NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8188F 0x0b
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8188F 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#undef WOWLAN_PAGE_NUM_8188F
|
||||
#define WOWLAN_PAGE_NUM_8188F 0x15
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_WOWLAN
|
||||
#define AP_WOWLAN_PAGE_NUM_8188F 0x02
|
||||
#endif
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F)
|
||||
#define TX_PAGE_BOUNDARY_8188F (TX_TOTAL_PAGE_NUMBER_8188F + 1)
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F TX_TOTAL_PAGE_NUMBER_8188F
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1)
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F */
|
||||
#define NORMAL_PAGE_NUM_HPQ_8188F 0x0C
|
||||
#define NORMAL_PAGE_NUM_LPQ_8188F 0x02
|
||||
#define NORMAL_PAGE_NUM_NPQ_8188F 0x02
|
||||
|
||||
/* Note: For Normal Chip Setting, modify later */
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8188F 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8188F 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8188F 0x20
|
||||
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
#define EFUSE_OOB_PROTECT_BYTES (34 + 1)
|
||||
|
||||
#define HAL_EFUSE_MEMORY
|
||||
|
||||
#define HWSET_MAX_SIZE_8188F 512
|
||||
#define EFUSE_REAL_CONTENT_LEN_8188F 256
|
||||
#define EFUSE_MAP_LEN_8188F 512
|
||||
#define EFUSE_MAX_SECTION_8188F (EFUSE_MAP_LEN_8188F / 8)
|
||||
|
||||
#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8188F)
|
||||
|
||||
#define EFUSE_ACCESS_ON 0x69 /* For RTL8188 only. */
|
||||
#define EFUSE_ACCESS_OFF 0x00 /* For RTL8188 only. */
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */
|
||||
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
|
||||
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
/* rtl8188a_hal_init.c */
|
||||
s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
|
||||
void rtl8188f_FirmwareSelfReset(PADAPTER padapter);
|
||||
void rtl8188f_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
void rtl8188f_InitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8188f_CheckAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8188f_init_default_value(PADAPTER padapter);
|
||||
|
||||
s32 rtl8188f_InitLLTTable(PADAPTER padapter);
|
||||
|
||||
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
|
||||
s32 CardDisableWithoutHWSM(PADAPTER padapter);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8188F(PADAPTER padapter);
|
||||
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */
|
||||
void Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
|
||||
#if 0 /* Do not need for rtl8188f */
|
||||
void Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
#endif
|
||||
|
||||
void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel);
|
||||
|
||||
void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8188f(_adapter *adapter);
|
||||
u8 SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val);
|
||||
u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
|
||||
/* register */
|
||||
void rtl8188f_InitBeaconParameters(PADAPTER padapter);
|
||||
void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
|
||||
void _InitBurstPktLen_8188FS(PADAPTER Adapter);
|
||||
void _8051Reset8188(PADAPTER padapter);
|
||||
#ifdef CONFIG_WOWLAN
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
void rtl8188f_start_thread(_adapter *padapter);
|
||||
void rtl8188f_stop_thread(_adapter *padapter);
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void rtl8188fs_init_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8188fs_free_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8188fs_hal_check_bt_hang(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
|
||||
#endif
|
||||
|
||||
void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len);
|
||||
|
||||
u8 MRateToHwRate8188F(u8 rate);
|
||||
u8 HwRateToMRate8188F(u8 rate);
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
BOOLEAN InterruptRecognized8188FE(PADAPTER Adapter);
|
||||
void UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_LED_H__
|
||||
#define __RTL8188F_LED_H__
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8188fu_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8188fu_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8188fs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_GSPI_HCI
|
||||
void rtl8188fs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8188fs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8188fe_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8188fe_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif/*CONFIG_RTW_SW_LED*/
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_RECV_H__
|
||||
#define __RTL8188F_RECV_H__
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
|
||||
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#else
|
||||
#ifdef CONFIG_PLATFORM_HISILICON
|
||||
#define MAX_RECVBUF_SZ (16384) /* 16k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (32768) /* 32k */
|
||||
#endif
|
||||
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
/* minmum 4K, multiple of 8-byte is required, multiple of sdio block size is prefered */
|
||||
#define MAX_RECVBUF_SZ _RND(RX_DMA_BOUNDARY_8188F + 1, 8)
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8188fs_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8188fs_free_recv_priv(PADAPTER padapter);
|
||||
s32 rtl8188fs_recv_hdl(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
int rtl8188fu_init_recv_priv(_adapter *padapter);
|
||||
void rtl8188fu_free_recv_priv(_adapter *padapter);
|
||||
void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8188fe_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8188fe_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8188F_RECV_H__ */
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_RF_H__
|
||||
#define __RTL8188F_RF_H__
|
||||
|
||||
int PHY_RF6052_Config8188F(PADAPTER Adapter);
|
||||
|
||||
void
|
||||
PHY_RF6052SetBandwidth8188F(
|
||||
PADAPTER Adapter,
|
||||
enum channel_width Bandwidth);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_SPEC_H__
|
||||
#define __RTL8188F_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
|
||||
#define HAL_NAV_UPPER_UNIT_8188F 128 /* micro-second */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RSV_CTRL_8188F 0x001C /* 3 Byte */
|
||||
#define REG_BT_WIFI_ANTENNA_SWITCH_8188F 0x0038
|
||||
#define REG_HSISR_8188F 0x005c
|
||||
#define REG_PAD_CTRL1_8188F 0x0064
|
||||
#define REG_AFE_CTRL_4_8188F 0x0078
|
||||
#define REG_HMEBOX_DBG_0_8188F 0x0088
|
||||
#define REG_HMEBOX_DBG_1_8188F 0x008A
|
||||
#define REG_HMEBOX_DBG_2_8188F 0x008C
|
||||
#define REG_HMEBOX_DBG_3_8188F 0x008E
|
||||
#define REG_HIMR0_8188F 0x00B0
|
||||
#define REG_HISR0_8188F 0x00B4
|
||||
#define REG_HIMR1_8188F 0x00B8
|
||||
#define REG_HISR1_8188F 0x00BC
|
||||
#define REG_PMC_DBG_CTRL2_8188F 0x00CC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_C2HEVT_CMD_ID_8188F 0x01A0
|
||||
#define REG_C2HEVT_CMD_LEN_8188F 0x01AE
|
||||
#define REG_WOWLAN_WAKE_REASON 0x01C7
|
||||
#define REG_WOWLAN_GTK_DBG1 0x630
|
||||
#define REG_WOWLAN_GTK_DBG2 0x634
|
||||
|
||||
#define REG_HMEBOX_EXT0_8188F 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8188F 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8188F 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8188F 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RXDMA_CONTROL_8188F 0x0286 /* Control the RX DMA. */
|
||||
#define REG_RXDMA_MODE_CTRL_8188F 0x0290
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8188F 0x0300
|
||||
#define REG_INT_MIG_8188F 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_DESA_8188F 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_HQ_DESA_8188F 0x0310 /* TX High Queue Descriptor Address */
|
||||
#define REG_MGQ_DESA_8188F 0x0318 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_DESA_8188F 0x0320 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_DESA_8188F 0x0328 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_DESA_8188F 0x0330 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_DESA_8188F 0x0338 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RX_DESA_8188F 0x0340 /* RX Queue Descriptor Address */
|
||||
#define REG_DBI_WDATA_8188F 0x0348 /* DBI Write Data */
|
||||
#define REG_DBI_RDATA_8188F 0x034C /* DBI Read Data */
|
||||
#define REG_DBI_ADDR_8188F 0x0350 /* DBI Address */
|
||||
#define REG_DBI_FLAG_8188F 0x0352 /* DBI Read/Write Flag */
|
||||
#define REG_MDIO_WDATA_8188F 0x0354 /* MDIO for Write PCIE PHY */
|
||||
#define REG_MDIO_RDATA_8188F 0x0356 /* MDIO for Reads PCIE PHY */
|
||||
#define REG_MDIO_CTL_8188F 0x0358 /* MDIO for Control */
|
||||
#define REG_DBG_SEL_8188F 0x0360 /* Debug Selection Register */
|
||||
#define REG_PCIE_HRPWM_8188F 0x0361 /* PCIe RPWM */
|
||||
#define REG_PCIE_HCPWM_8188F 0x0363 /* PCIe CPWM */
|
||||
#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A /* PCIE Multi-Fethc Control */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424
|
||||
#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x0484
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x0488
|
||||
#endif
|
||||
#define REG_AMPDU_BURST_MODE_8188F 0x04BC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SECONDARY_CCA_CTRL_8188F 0x0577
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
|
||||
/* ************************************************************
|
||||
* SDIO Bus Specification
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO CMD Address Mapping
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* I/O bus domain (Host)
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO register
|
||||
* ----------------------------------------------------- */
|
||||
#define SDIO_REG_HIQ_FREEPG_8188F 0x0020
|
||||
#define SDIO_REG_MID_FREEPG_8188F 0x0022
|
||||
#define SDIO_REG_LOW_FREEPG_8188F 0x0024
|
||||
#define SDIO_REG_PUB_FREEPG_8188F 0x0026
|
||||
#define SDIO_REG_EXQ_FREEPG_8188F 0x0028
|
||||
#define SDIO_REG_AC_OQT_FREEPG_8188F 0x002A
|
||||
#define SDIO_REG_NOAC_OQT_FREEPG_8188F 0x002B
|
||||
|
||||
#define SDIO_REG_HCPWM1_8188F 0x0038
|
||||
|
||||
/* ****************************************************************************
|
||||
* 8188 Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
/* 2 HSISR
|
||||
* interrupt mask which needs to clear */
|
||||
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
|
||||
HSISR_SPS_OCP_INT |\
|
||||
HSISR_RON_INT |\
|
||||
HSISR_PDNINT |\
|
||||
HSISR_GPIO9_INT)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define BIT_USB_RXDMA_AGG_EN BIT(31)
|
||||
#define RXDMA_AGG_MODE_EN BIT(1)
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RXPKT_RELEASE_POLL BIT(16)
|
||||
#define RXDMA_IDLE BIT(17)
|
||||
#define RW_RELEASE_EN BIT(18)
|
||||
#endif
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8188F REG_CCK_CHECK (offset 0x454)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define BIT_BCN_PORT_SEL BIT(5)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8195 IMR/ISR bits (offset 0xB0, 8bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define IMR_DISABLED_8188F 0
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8188F BIT(31) /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8188F BIT(30) /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8188F BIT(29) /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8188F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
|
||||
#define IMR_GTINT3_8188F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8188F BIT(26) /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8188F BIT(25) /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8188F BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8188F BIT(20) /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8188F BIT(16) /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8188F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8188F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8188F BIT(12) /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8188F BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
|
||||
#define IMR_CPWM2_8188F BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_CPWM_8188F BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8188F BIT(7) /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8188F BIT(6) /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8188F BIT(5) /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8188F BIT(4) /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8188F BIT(3) /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8188F BIT(2) /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8188F BIT(1) /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8188F BIT(0) /* Receive DMA OK */
|
||||
|
||||
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
||||
#define IMR_BCNDMAINT7_8188F BIT(27) /* Beacon DMA Interrupt 7 */
|
||||
#define IMR_BCNDMAINT6_8188F BIT(26) /* Beacon DMA Interrupt 6 */
|
||||
#define IMR_BCNDMAINT5_8188F BIT(25) /* Beacon DMA Interrupt 5 */
|
||||
#define IMR_BCNDMAINT4_8188F BIT(24) /* Beacon DMA Interrupt 4 */
|
||||
#define IMR_BCNDMAINT3_8188F BIT(23) /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2_8188F BIT(22) /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1_8188F BIT(21) /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8188F BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
|
||||
#define IMR_BCNDOK6_8188F BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
|
||||
#define IMR_BCNDOK5_8188F BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
|
||||
#define IMR_BCNDOK4_8188F BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
|
||||
#define IMR_BCNDOK3_8188F BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
|
||||
#define IMR_BCNDOK2_8188F BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
|
||||
#define IMR_BCNDOK1_8188F BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
|
||||
#define IMR_ATIMEND_E_8188F BIT(13) /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8188F BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR_8188F BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8188F BIT(9) /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8188F BIT(8) /* Receive FIFO Overflow */
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* #define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F)
|
||||
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)
|
||||
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F)
|
||||
#endif
|
||||
|
||||
#endif /* __RTL8188F_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8188F_SRESET_H_
|
||||
#define _RTL8188F_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8188f_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,340 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8188F_XMIT_H__
|
||||
#define __RTL8188F_XMIT_H__
|
||||
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
|
||||
#ifndef __INC_HAL8188FDESC_H
|
||||
#define __INC_HAL8188FDESC_H
|
||||
|
||||
#define RX_STATUS_DESC_SIZE_8188F 24
|
||||
#define RX_DRV_INFO_SIZE_UNIT_8188F 8
|
||||
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
|
||||
#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
#endif
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
|
||||
#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
|
||||
#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
|
||||
#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
|
||||
|
||||
|
||||
/* Dword 0 */
|
||||
#define GET_TX_DESC_OWN_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
|
||||
#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
|
||||
#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
|
||||
#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
|
||||
#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
|
||||
#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
|
||||
#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
|
||||
#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
|
||||
#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
|
||||
#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
|
||||
#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
|
||||
#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
|
||||
#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
|
||||
#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
|
||||
|
||||
|
||||
/* Dword 2 */
|
||||
#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
|
||||
#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
|
||||
#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
|
||||
#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
|
||||
#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
|
||||
#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
|
||||
#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
|
||||
#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
|
||||
|
||||
|
||||
/* Dword 3 */
|
||||
#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
|
||||
#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
|
||||
#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
|
||||
#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
|
||||
#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
|
||||
#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
|
||||
#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
|
||||
#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
|
||||
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
|
||||
#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
|
||||
#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
|
||||
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
|
||||
#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
|
||||
|
||||
/* Dword 7 */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
|
||||
#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
|
||||
#endif
|
||||
|
||||
/* Dword 8 */
|
||||
#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
|
||||
|
||||
/* Dword 10 */
|
||||
#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
|
||||
#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
|
||||
|
||||
/* Dword 11 */
|
||||
#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
|
||||
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
|
||||
#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
|
||||
#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
|
||||
|
||||
#endif
|
||||
/* -----------------------------------------------------------
|
||||
*
|
||||
* Rate
|
||||
*
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC8188F_RATE1M 0x00
|
||||
#define DESC8188F_RATE2M 0x01
|
||||
#define DESC8188F_RATE5_5M 0x02
|
||||
#define DESC8188F_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC8188F_RATE6M 0x04
|
||||
#define DESC8188F_RATE9M 0x05
|
||||
#define DESC8188F_RATE12M 0x06
|
||||
#define DESC8188F_RATE18M 0x07
|
||||
#define DESC8188F_RATE24M 0x08
|
||||
#define DESC8188F_RATE36M 0x09
|
||||
#define DESC8188F_RATE48M 0x0a
|
||||
#define DESC8188F_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC8188F_RATEMCS0 0x0c
|
||||
#define DESC8188F_RATEMCS1 0x0d
|
||||
#define DESC8188F_RATEMCS2 0x0e
|
||||
#define DESC8188F_RATEMCS3 0x0f
|
||||
#define DESC8188F_RATEMCS4 0x10
|
||||
#define DESC8188F_RATEMCS5 0x11
|
||||
#define DESC8188F_RATEMCS6 0x12
|
||||
#define DESC8188F_RATEMCS7 0x13
|
||||
#define DESC8188F_RATEMCS8 0x14
|
||||
#define DESC8188F_RATEMCS9 0x15
|
||||
#define DESC8188F_RATEMCS10 0x16
|
||||
#define DESC8188F_RATEMCS11 0x17
|
||||
#define DESC8188F_RATEMCS12 0x18
|
||||
#define DESC8188F_RATEMCS13 0x19
|
||||
#define DESC8188F_RATEMCS14 0x1a
|
||||
#define DESC8188F_RATEMCS15 0x1b
|
||||
#define DESC8188F_RATEVHTSS1MCS0 0x2c
|
||||
#define DESC8188F_RATEVHTSS1MCS1 0x2d
|
||||
#define DESC8188F_RATEVHTSS1MCS2 0x2e
|
||||
#define DESC8188F_RATEVHTSS1MCS3 0x2f
|
||||
#define DESC8188F_RATEVHTSS1MCS4 0x30
|
||||
#define DESC8188F_RATEVHTSS1MCS5 0x31
|
||||
#define DESC8188F_RATEVHTSS1MCS6 0x32
|
||||
#define DESC8188F_RATEVHTSS1MCS7 0x33
|
||||
#define DESC8188F_RATEVHTSS1MCS8 0x34
|
||||
#define DESC8188F_RATEVHTSS1MCS9 0x35
|
||||
#define DESC8188F_RATEVHTSS2MCS0 0x36
|
||||
#define DESC8188F_RATEVHTSS2MCS1 0x37
|
||||
#define DESC8188F_RATEVHTSS2MCS2 0x38
|
||||
#define DESC8188F_RATEVHTSS2MCS3 0x39
|
||||
#define DESC8188F_RATEVHTSS2MCS4 0x3a
|
||||
#define DESC8188F_RATEVHTSS2MCS5 0x3b
|
||||
#define DESC8188F_RATEVHTSS2MCS6 0x3c
|
||||
#define DESC8188F_RATEVHTSS2MCS7 0x3d
|
||||
#define DESC8188F_RATEVHTSS2MCS8 0x3e
|
||||
#define DESC8188F_RATEVHTSS2MCS9 0x3f
|
||||
|
||||
|
||||
#define RX_HAL_IS_CCK_RATE_8188F(pDesc)\
|
||||
(GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M)
|
||||
|
||||
|
||||
void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
|
||||
void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8188fs_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8188fs_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8188fs_hal_mgmt_xmitframe_enqueue(PADAPTER, struct xmit_frame *);
|
||||
#endif
|
||||
s32 rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter);
|
||||
thread_return rtl8188fs_xmit_thread(thread_context context);
|
||||
#define hal_xmit_handler rtl8188fs_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#ifdef CONFIG_XMIT_THREAD_MODE
|
||||
s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8188fu_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
s32 rtl8188fu_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8188fu_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8188fu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
|
||||
void rtl8188fu_xmit_tasklet(void *priv);
|
||||
s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8188fe_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8188fe_free_xmit_priv(PADAPTER padapter);
|
||||
struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
void rtl8188fe_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
s32 rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8188fe_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
u8 BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
u8 SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_CMD_H__
|
||||
#define __RTL8192E_CMD_H__
|
||||
|
||||
typedef enum _RTL8192E_H2C_CMD {
|
||||
H2C_8192E_RSVDPAGE = 0x00,
|
||||
H2C_8192E_MSRRPT = 0x01,
|
||||
H2C_8192E_SCAN = 0x02,
|
||||
H2C_8192E_KEEP_ALIVE_CTRL = 0x03,
|
||||
H2C_8192E_DISCONNECT_DECISION = 0x04,
|
||||
H2C_8192E_INIT_OFFLOAD = 0x06,
|
||||
H2C_8192E_AP_OFFLOAD = 0x08,
|
||||
H2C_8192E_BCN_RSVDPAGE = 0x09,
|
||||
H2C_8192E_PROBERSP_RSVDPAGE = 0x0a,
|
||||
|
||||
H2C_8192E_AP_WOW_GPIO_CTRL = 0x13,
|
||||
|
||||
H2C_8192E_SETPWRMODE = 0x20,
|
||||
H2C_8192E_PS_TUNING_PARA = 0x21,
|
||||
H2C_8192E_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8192E_PS_LPS_PARA = 0x23,
|
||||
H2C_8192E_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8192E_SAP_PS = 0x26,
|
||||
H2C_8192E_RA_MASK = 0x40,
|
||||
H2C_8192E_RSSI_REPORT = 0x42,
|
||||
H2C_8192E_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
H2C_8192E_WO_WLAN = 0x80,
|
||||
H2C_8192E_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8192E_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8192E_AOAC_RSVDPAGE = 0x83,
|
||||
|
||||
/* Not defined in new 88E H2C CMD Format */
|
||||
H2C_8192E_SELECTIVE_SUSPEND_ROF_CMD,
|
||||
H2C_8192E_P2P_PS_MODE,
|
||||
H2C_8192E_PSD_RESULT,
|
||||
MAX_8192E_H2CCMD
|
||||
} RTL8192E_H2C_CMD;
|
||||
|
||||
struct cmd_msg_parm {
|
||||
u8 eid; /* element id */
|
||||
u8 sz; /* sz */
|
||||
u8 buf[6];
|
||||
};
|
||||
|
||||
enum {
|
||||
PWRS
|
||||
};
|
||||
|
||||
typedef struct _SETPWRMODE_PARM {
|
||||
u8 Mode;/* 0:Active,1:LPS,2:WMMPS */
|
||||
/* u8 RLBM:4; */ /* 0:Min,1:Max,2: User define */
|
||||
u8 SmartPS_RLBM;/* LPS=0:PS_Poll,1:PS_Poll,2:NullData,WMM=0:PS_Poll,1:NullData */
|
||||
u8 AwakeInterval; /* unit: beacon interval */
|
||||
u8 bAllQueueUAPSD;
|
||||
u8 PwrState;/* AllON(0x0c),RFON(0x04),RFOFF(0x00) */
|
||||
} SETPWRMODE_PARM, *PSETPWRMODE_PARM;
|
||||
|
||||
struct H2C_SS_RFOFF_PARAM {
|
||||
u8 ROFOn; /* 1: on, 0:off */
|
||||
u16 gpio_period; /* unit: 1024 us */
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
typedef struct JOINBSSRPT_PARM_92E {
|
||||
u8 OpMode; /* RT_MEDIA_STATUS */
|
||||
#ifdef CONFIG_WOWLAN
|
||||
u8 MacID; /* MACID */
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
} JOINBSSRPT_PARM_92E, *PJOINBSSRPT_PARM_92E;
|
||||
|
||||
/* move to hal_com_h2c.h
|
||||
typedef struct _RSVDPAGE_LOC_92E {
|
||||
u8 LocProbeRsp;
|
||||
u8 LocPsPoll;
|
||||
u8 LocNullData;
|
||||
u8 LocQosNull;
|
||||
u8 LocBTQosNull;
|
||||
} RSVDPAGE_LOC_92E, *PRSVDPAGE_LOC_92E;
|
||||
*/
|
||||
|
||||
|
||||
/* _SETPWRMODE_PARM */
|
||||
#define SET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192E_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8192E_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8192E_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8192E_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8192E_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define GET_8192E_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _P2P_PS_OFFLOAD */
|
||||
#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
|
||||
#define SET_8192E_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
|
||||
|
||||
|
||||
/* host message to firmware cmd */
|
||||
void rtl8192e_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8192e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
|
||||
s32 FillH2CCmd_8192E(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
u8 GetTxBufferRsvdPageNum8192E(_adapter *padapter, bool wowlan);
|
||||
/* u8 rtl8192c_set_FwSelectSuspend_cmd(PADAPTER padapter, u8 bfwpoll, u16 period); */
|
||||
s32 c2h_handler_8192e(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8192e_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P_PS
|
||||
void rtl8192e_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
/* / TX Feedback Content */
|
||||
#define USEC_UNIT_FOR_8192E_C2H_TX_RPT_QUEUE_TIME 256
|
||||
|
||||
#define GET_8192E_C2H_TX_RPT_QUEUE_SELECT(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
|
||||
#define GET_8192E_C2H_TX_RPT_PKT_BROCAST(_Header) LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
|
||||
#define GET_8192E_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
|
||||
#define GET_8192E_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
|
||||
#define GET_8192E_C2H_TX_RPT_MAC_ID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
|
||||
#define GET_8192E_C2H_TX_RPT_DATA_RETRY_CNT(_Header) LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
|
||||
#define GET_8192E_C2H_TX_RPT_QUEUE_TIME(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) /* In unit of 256 microseconds. */
|
||||
#define GET_8192E_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
|
||||
|
||||
#endif /* __RTL8192E_CMD_H__ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_DM_H__
|
||||
#define __RTL8192E_DM_H__
|
||||
|
||||
|
||||
void rtl8192e_init_dm_priv(PADAPTER Adapter);
|
||||
void rtl8192e_deinit_dm_priv(PADAPTER Adapter);
|
||||
void rtl8192e_InitHalDm(PADAPTER Adapter);
|
||||
void rtl8192e_HalDmWatchDog(PADAPTER Adapter);
|
||||
|
||||
/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
|
||||
|
||||
/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_HAL_H__
|
||||
#define __RTL8192E_HAL_H__
|
||||
|
||||
/* #include "hal_com.h" */
|
||||
|
||||
#include "hal_data.h"
|
||||
|
||||
/* include HAL Related header after HAL Related compiling flags */
|
||||
#include "rtl8192e_spec.h"
|
||||
#include "rtl8192e_rf.h"
|
||||
#include "rtl8192e_dm.h"
|
||||
#include "rtl8192e_recv.h"
|
||||
#include "rtl8192e_xmit.h"
|
||||
#include "rtl8192e_cmd.h"
|
||||
#include "rtl8192e_led.h"
|
||||
#include "Hal8192EPwrSeq.h"
|
||||
#include "Hal8192EPhyReg.h"
|
||||
#include "Hal8192EPhyCfg.h"
|
||||
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8192e_sreset.h"
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* RTL8192E Power Configuration CMDs for PCIe interface
|
||||
* --------------------------------------------------------------------- */
|
||||
#define Rtl8192E_NIC_PWR_ON_FLOW rtl8192E_power_on_flow
|
||||
#define Rtl8192E_NIC_RF_OFF_FLOW rtl8192E_radio_off_flow
|
||||
#define Rtl8192E_NIC_DISABLE_FLOW rtl8192E_card_disable_flow
|
||||
#define Rtl8192E_NIC_ENABLE_FLOW rtl8192E_card_enable_flow
|
||||
#define Rtl8192E_NIC_SUSPEND_FLOW rtl8192E_suspend_flow
|
||||
#define Rtl8192E_NIC_RESUME_FLOW rtl8192E_resume_flow
|
||||
#define Rtl8192E_NIC_PDN_FLOW rtl8192E_hwpdn_flow
|
||||
#define Rtl8192E_NIC_LPS_ENTER_FLOW rtl8192E_enter_lps_flow
|
||||
#define Rtl8192E_NIC_LPS_LEAVE_FLOW rtl8192E_leave_lps_flow
|
||||
|
||||
|
||||
#if 1 /* download firmware related data structure */
|
||||
#define FW_SIZE_8192E 0x8000 /* Compatible with RTL8192e Maximal RAM code size 32k */
|
||||
#define FW_START_ADDRESS 0x1000
|
||||
#define FW_END_ADDRESS 0x5FFF
|
||||
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8192E(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE_8192E(_pFwHdr) & 0xFFF0) == 0x92E0)
|
||||
|
||||
|
||||
|
||||
typedef struct _RT_FIRMWARE_8192E {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_SIZE_8192E];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8192E, *PRT_FIRMWARE_8192E;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
|
||||
/* *****************************************************
|
||||
* Firmware Header(8-byte alinment required)
|
||||
* *****************************************************
|
||||
* --- LONG WORD 0 ---- */
|
||||
#define GET_FIRMWARE_HDR_SIGNATURE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
#define GET_FIRMWARE_HDR_CATEGORY_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
|
||||
#define GET_FIRMWARE_HDR_FUNCTION_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
#define GET_FIRMWARE_HDR_VERSION_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
|
||||
#define GET_FIRMWARE_HDR_SUB_VER_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
|
||||
#define GET_FIRMWARE_HDR_RSVD1_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
#define GET_FIRMWARE_HDR_MONTH_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
|
||||
#define GET_FIRMWARE_HDR_DATE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
|
||||
#define GET_FIRMWARE_HDR_HOUR_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
|
||||
#define GET_FIRMWARE_HDR_MINUTE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
|
||||
#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
|
||||
#define GET_FIRMWARE_HDR_RSVD2_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
#define GET_FIRMWARE_HDR_SVN_IDX_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
|
||||
#define GET_FIRMWARE_HDR_RSVD3_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
#define GET_FIRMWARE_HDR_RSVD4_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
|
||||
#define GET_FIRMWARE_HDR_RSVD5_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
|
||||
|
||||
#endif /* download firmware related data structure */
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8192E 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8192E 0x02
|
||||
#define RX_DMA_SIZE_8192E 0x4000 /* 16K*/
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8192E 0x100 /* 256B, reserved for c2h debug message*/
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8192E 0x40 /* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes)*/
|
||||
#endif
|
||||
#define MAX_RX_DMA_BUFFER_SIZE_8192E (RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E) /*RX 16K*/
|
||||
|
||||
|
||||
#define PAGE_SIZE_TX_92E PAGE_SIZE_256
|
||||
|
||||
/* For General Reserved Page Number(Beacon Queue is reserved page)
|
||||
* if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1
|
||||
* Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E
|
||||
* PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/
|
||||
|
||||
#define RSVD_PAGE_NUM_8192E (MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
|
||||
* NS offload: 2 NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8192E 0x0b
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8192E 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#undef WOWLAN_PAGE_NUM_8192E
|
||||
#define WOWLAN_PAGE_NUM_8192E 0x0d
|
||||
#endif
|
||||
|
||||
/* Note:
|
||||
Tx FIFO Size : 64KB
|
||||
Tx page Size : 256B
|
||||
Total page numbers : 256(0x100)
|
||||
*/
|
||||
|
||||
#define TOTAL_RSVD_PAGE_NUMBER_8192E (RSVD_PAGE_NUM_8192E + WOWLAN_PAGE_NUM_8192E)
|
||||
|
||||
#define TOTAL_PAGE_NUMBER_8192E (0x100)
|
||||
#define TX_TOTAL_PAGE_NUMBER_8192E (TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E)
|
||||
|
||||
#define TX_PAGE_BOUNDARY_8192E (TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */
|
||||
|
||||
|
||||
#define RSVD_PKT_LEN_92E (TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E)
|
||||
|
||||
#define TX_PAGE_LOAD_FW_BOUNDARY_8192E 0x47 /* 0xA5 */
|
||||
#define TX_PAGE_BOUNDARY_WOWLAN_8192E 0xE0
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_92C */
|
||||
|
||||
#define NORMAL_PAGE_NUM_HPQ_8192E 0x10
|
||||
#define NORMAL_PAGE_NUM_LPQ_8192E 0x10
|
||||
#define NORMAL_PAGE_NUM_NPQ_8192E 0x10
|
||||
#define NORMAL_PAGE_NUM_EPQ_8192E 0x00
|
||||
|
||||
|
||||
/* Note: For WMM Normal Chip Setting ,modify later */
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8192E NORMAL_PAGE_NUM_HPQ_8192E
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8192E NORMAL_PAGE_NUM_LPQ_8192E
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8192E NORMAL_PAGE_NUM_NPQ_8192E
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
* Chip specific
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
/* pic buffer descriptor */
|
||||
#define RTL8192EE_SEG_NUM TX_BUFFER_SEG_NUM
|
||||
#define TX_DESC_NUM_92E 128
|
||||
#define RX_DESC_NUM_92E 128
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
* Channel Plan
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
#define HWSET_MAX_SIZE_8192E 512
|
||||
|
||||
#define EFUSE_REAL_CONTENT_LEN_8192E 512
|
||||
|
||||
#define EFUSE_MAP_LEN_8192E 512
|
||||
#define EFUSE_MAX_SECTION_8192E 64
|
||||
#define EFUSE_MAX_WORD_UNIT_8192E 4
|
||||
#define EFUSE_IC_ID_OFFSET_8192E 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
|
||||
#define AVAILABLE_EFUSE_ADDR_8192E(addr) (addr < EFUSE_REAL_CONTENT_LEN_8192E)
|
||||
/*
|
||||
* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
|
||||
* 9bytes + 1byt + 5bytes and pre 1byte.
|
||||
* For worst case:
|
||||
* | 1byte|----8bytes----|1byte|--5bytes--|
|
||||
* | | Reserved(14bytes) |
|
||||
* */
|
||||
#define EFUSE_OOB_PROTECT_BYTES_8192E 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
|
||||
|
||||
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN_8192E 512
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN_8192E 1024 /* 512*2 */
|
||||
#define EFUSE_BT_MAP_LEN_8192E 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION_8192E 128 /* 1024/8 */
|
||||
|
||||
#define EFUSE_PROTECT_BYTES_BANK_8192E 16
|
||||
#define EFUSE_MAX_BANK_8192E 3
|
||||
/* *********************************************************** */
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
/* #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
|
||||
|
||||
/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
|
||||
|
||||
/* rtl8812_hal_init.c */
|
||||
void _8051Reset8192E(PADAPTER padapter);
|
||||
s32 FirmwareDownload8192E(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
|
||||
void InitializeFirmwareVars8192E(PADAPTER padapter);
|
||||
|
||||
s32 InitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8192E(PADAPTER padapter);
|
||||
void hal_InitPGData_8192E(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode8192E(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_ReadPROMVersion8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadPowerSavingMode8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadTxPowerInfo8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadBoardType8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadThermalMeter_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadAntennaDiversity8192E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadPAType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
|
||||
u8 Hal_CrystalAFEAdjust(_adapter *Adapter);
|
||||
|
||||
BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter);
|
||||
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
/***********************************************************/
|
||||
/* RTL8192E-MAC Setting */
|
||||
void _InitQueueReservedPage_8192E(PADAPTER Adapter);
|
||||
void _InitQueuePriority_8192E(PADAPTER Adapter);
|
||||
void _InitTxBufferBoundary_8192E(PADAPTER Adapter, u8 txpktbuf_bndy);
|
||||
void _InitPageBoundary_8192E(PADAPTER Adapter);
|
||||
/* void _InitTransferPageSize_8192E(PADAPTER Adapter); */
|
||||
void _InitDriverInfoSize_8192E(PADAPTER Adapter, u8 drvInfoSize);
|
||||
void _InitRDGSetting_8192E(PADAPTER Adapter);
|
||||
void _InitID_8192E(PADAPTER Adapter);
|
||||
void _InitNetworkType_8192E(PADAPTER Adapter);
|
||||
void _InitWMACSetting_8192E(PADAPTER Adapter);
|
||||
void _InitAdaptiveCtrl_8192E(PADAPTER Adapter);
|
||||
void _InitEDCA_8192E(PADAPTER Adapter);
|
||||
void _InitRetryFunction_8192E(PADAPTER Adapter);
|
||||
void _BBTurnOnBlock_8192E(PADAPTER Adapter);
|
||||
void _InitBeaconParameters_8192E(PADAPTER Adapter);
|
||||
void _InitBeaconMaxError_8192E(
|
||||
PADAPTER Adapter,
|
||||
BOOLEAN InfraMode
|
||||
);
|
||||
void SetBeaconRelatedRegisters8192E(PADAPTER padapter);
|
||||
void hal_ReadRFType_8192E(PADAPTER Adapter);
|
||||
/* RTL8192E-MAC Setting
|
||||
***********************************************************/
|
||||
|
||||
u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
|
||||
void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val);
|
||||
u8
|
||||
SetHalDefVar8192E(
|
||||
PADAPTER Adapter,
|
||||
HAL_DEF_VARIABLE eVariable,
|
||||
void *pValue
|
||||
);
|
||||
u8
|
||||
GetHalDefVar8192E(
|
||||
PADAPTER Adapter,
|
||||
HAL_DEF_VARIABLE eVariable,
|
||||
void *pValue
|
||||
);
|
||||
|
||||
void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8192e(_adapter *adapter);
|
||||
void rtl8192e_init_default_value(_adapter *padapter);
|
||||
|
||||
void rtl8192e_start_thread(_adapter *padapter);
|
||||
void rtl8192e_stop_thread(_adapter *padapter);
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
BOOLEAN InterruptRecognized8192EE(PADAPTER Adapter);
|
||||
u16 get_txbd_rw_reg(u16 ff_hwaddr);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
|
||||
void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8192e_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
|
||||
#endif
|
||||
|
||||
#endif /* __RTL8192E_HAL_H__ */
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_LED_H__
|
||||
#define __RTL8192E_LED_H__
|
||||
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8192eu_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8192eu_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8192ee_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8192ee_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8192es_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8192es_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif/*CONFIG_RTW_SW_LED*/
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_RECV_H__
|
||||
#define __RTL8192E_RECV_H__
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#else
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
|
||||
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
|
||||
#elif defined(CONFIG_PLATFORM_HISILICON)
|
||||
#define MAX_RECVBUF_SZ (16384) /* 16k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (32768) /* 32k */
|
||||
#endif
|
||||
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
|
||||
#undef MAX_RECVBUF_SZ
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
|
||||
#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
|
||||
/* #define MAX_RECVBUF_SZ (9100) */
|
||||
/* #else */
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K
|
||||
* #endif */
|
||||
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (16384)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
/* *************
|
||||
* [1] Rx Buffer Descriptor (for PCIE) buffer descriptor architecture
|
||||
* DWORD 0 */
|
||||
#define SET_RX_BUFFER_DESC_DATA_LENGTH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
|
||||
|
||||
#define GET_RX_BUFFER_DESC_OWN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
#define GET_RX_BUFFER_DESC_LS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_BUFFER_DESC_FS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
|
||||
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
|
||||
|
||||
|
||||
/* DWORD 1 */
|
||||
#define SET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
|
||||
#define GET_RX_BUFFER_PHYSICAL_LOW_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 0, 32)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
|
||||
|
||||
/* *************
|
||||
* [2] Rx Descriptor
|
||||
* DWORD 0 */
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICVERR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_92E(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_MACID_VLD_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 12, 1)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FITS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHKERR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_TCPOFFLOAD_IPVER_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_TCPOFFLOAD_IS_TCPUDP_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_TCPOFFLOAD_CHK_VLD_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_HWRSVD_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 24, 4)
|
||||
#define GET_RX_STATUS_DESC_FCS_OK_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#define GET_RX_STATUS_DESC_DMA_AGG_NUM_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_WAKE_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_SPLCP_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
|
||||
#define GET_RX_STATUS_DESC_LDPC_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
|
||||
#define GET_RX_STATUS_DESC_STBC_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
|
||||
#define GET_RX_STATUS_DESC_BW_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
|
||||
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_92E(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_92E(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
s32 rtl8192es_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8192es_free_recv_priv(PADAPTER padapter);
|
||||
s32 rtl8192es_recv_hdl(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8192eu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
s32 rtl8192eu_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8192eu_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8192ee_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8192ee_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8192e_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8192E_RECV_H__ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_RF_H__
|
||||
#define __RTL8192E_RF_H__
|
||||
|
||||
void
|
||||
PHY_RF6052SetBandwidth8192E(
|
||||
PADAPTER Adapter,
|
||||
enum channel_width Bandwidth);
|
||||
|
||||
|
||||
int
|
||||
PHY_RF6052_Config_8192E(
|
||||
PADAPTER Adapter);
|
||||
|
||||
#endif/* __RTL8192E_RF_H__ */
|
||||
|
|
@ -0,0 +1,313 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_SPEC_H__
|
||||
#define __RTL8192E_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
#define HAL_NAV_UPPER_UNIT_8192E 128 /* micro-second */
|
||||
|
||||
/* ************************************************************
|
||||
* 8192E Regsiter offset definition
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SYS_SWR_CTRL1_8192E 0x0010 /* 1 Byte */
|
||||
#define REG_SYS_SWR_CTRL2_8192E 0x0014 /* 1 Byte */
|
||||
#define REG_AFE_CTRL1_8192E 0x0024
|
||||
#define REG_AFE_CTRL2_8192E 0x0028
|
||||
#define REG_AFE_CTRL3_8192E 0x002c
|
||||
|
||||
#define REG_PAD_CTRL1_8192E 0x0064
|
||||
#define REG_SDIO_CTRL_8192E 0x0070
|
||||
#define REG_OPT_CTRL_8192E 0x0074
|
||||
#define REG_RF_B_CTRL_8192E 0x0076
|
||||
#define REG_AFE_CTRL4_8192E 0x0078
|
||||
#define REG_LDO_SWR_CTRL 0x007C
|
||||
#define REG_FW_DRV_MSG_8192E 0x0088
|
||||
#define REG_HMEBOX_E2_E3_8192E 0x008C
|
||||
#define REG_HIMR0_8192E 0x00B0
|
||||
#define REG_HISR0_8192E 0x00B4
|
||||
#define REG_HIMR1_8192E 0x00B8
|
||||
#define REG_HISR1_8192E 0x00BC
|
||||
|
||||
#define REG_SYS_CFG1_8192E 0x00F0
|
||||
#define REG_SYS_CFG2_8192E 0x00FC
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
|
||||
#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
|
||||
#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
|
||||
#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
|
||||
|
||||
#define REG_RSVD3_8192E 0x0168
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
|
||||
#define REG_C2HEVT_CMD_LEN_88XX 0x01AE
|
||||
|
||||
#define REG_HMEBOX_EXT0_8192E 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8192E 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8192E 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8192E 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_DWBCN0_CTRL 0x0208
|
||||
#define REG_DWBCN1_CTRL 0x0228
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RXDMA_8192E 0x0290
|
||||
#define REG_EARLY_MODE_CONTROL_8192E 0x02BC
|
||||
|
||||
#define REG_RSVD5_8192E 0x02F0
|
||||
#define REG_RSVD6_8192E 0x02F4
|
||||
#define REG_RSVD7_8192E 0x02F8
|
||||
#define REG_RSVD8_8192E 0x02FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8192E 0x0300
|
||||
#define REG_INT_MIG_8192E 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_TXBD_DESA_8192E 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_MGQ_TXBD_DESA_8192E 0x0310 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_TXBD_DESA_8192E 0x0318 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_TXBD_DESA_8192E 0x0320 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_TXBD_DESA_8192E 0x0328 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_TXBD_DESA_8192E 0x0330 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RXQ_RXBD_DESA_8192E 0x0338 /* RX Queue Descriptor Address */
|
||||
#define REG_HI0Q_TXBD_DESA_8192E 0x0340
|
||||
#define REG_HI1Q_TXBD_DESA_8192E 0x0348
|
||||
#define REG_HI2Q_TXBD_DESA_8192E 0x0350
|
||||
#define REG_HI3Q_TXBD_DESA_8192E 0x0358
|
||||
#define REG_HI4Q_TXBD_DESA_8192E 0x0360
|
||||
#define REG_HI5Q_TXBD_DESA_8192E 0x0368
|
||||
#define REG_HI6Q_TXBD_DESA_8192E 0x0370
|
||||
#define REG_HI7Q_TXBD_DESA_8192E 0x0378
|
||||
#define REG_MGQ_TXBD_NUM_8192E 0x0380
|
||||
#define REG_RX_RXBD_NUM_8192E 0x0382
|
||||
#define REG_VOQ_TXBD_NUM_8192E 0x0384
|
||||
#define REG_VIQ_TXBD_NUM_8192E 0x0386
|
||||
#define REG_BEQ_TXBD_NUM_8192E 0x0388
|
||||
#define REG_BKQ_TXBD_NUM_8192E 0x038A
|
||||
#define REG_HI0Q_TXBD_NUM_8192E 0x038C
|
||||
#define REG_HI1Q_TXBD_NUM_8192E 0x038E
|
||||
#define REG_HI2Q_TXBD_NUM_8192E 0x0390
|
||||
#define REG_HI3Q_TXBD_NUM_8192E 0x0392
|
||||
#define REG_HI4Q_TXBD_NUM_8192E 0x0394
|
||||
#define REG_HI5Q_TXBD_NUM_8192E 0x0396
|
||||
#define REG_HI6Q_TXBD_NUM_8192E 0x0398
|
||||
#define REG_HI7Q_TXBD_NUM_8192E 0x039A
|
||||
#define REG_TSFTIMER_HCI_8192E 0x039C
|
||||
|
||||
/* Read Write Point */
|
||||
#define REG_VOQ_TXBD_IDX_8192E 0x03A0
|
||||
#define REG_VIQ_TXBD_IDX_8192E 0x03A4
|
||||
#define REG_BEQ_TXBD_IDX_8192E 0x03A8
|
||||
#define REG_BKQ_TXBD_IDX_8192E 0x03AC
|
||||
#define REG_MGQ_TXBD_IDX_8192E 0x03B0
|
||||
#define REG_RXQ_TXBD_IDX_8192E 0x03B4
|
||||
#define REG_HI0Q_TXBD_IDX_8192E 0x03B8
|
||||
#define REG_HI1Q_TXBD_IDX_8192E 0x03BC
|
||||
#define REG_HI2Q_TXBD_IDX_8192E 0x03C0
|
||||
#define REG_HI3Q_TXBD_IDX_8192E 0x03C4
|
||||
#define REG_HI4Q_TXBD_IDX_8192E 0x03C8
|
||||
#define REG_HI5Q_TXBD_IDX_8192E 0x03CC
|
||||
#define REG_HI6Q_TXBD_IDX_8192E 0x03D0
|
||||
#define REG_HI7Q_TXBD_IDX_8192E 0x03D4
|
||||
|
||||
#define REG_PCIE_HCPWM_8192EE 0x03D8 /* ?????? */
|
||||
#define REG_PCIE_HRPWM_8192EE 0x03DC /* PCIe RPWM */ /* ?????? */
|
||||
#define REG_DBI_WDATA_V1_8192E 0x03E8
|
||||
#define REG_DBI_RDATA_V1_8192E 0x03EC
|
||||
#define REG_DBI_FLAG_V1_8192E 0x03F0
|
||||
#define REG_MDIO_V1_8192E 0x3F4
|
||||
#define REG_PCIE_MIX_CFG_8192E 0x3F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_TXBF_CTRL_8192E 0x042C
|
||||
#define REG_ARFR0_8192E 0x0444
|
||||
#define REG_ARFR1_8192E 0x044C
|
||||
#define REG_CCK_CHECK_8192E 0x0454
|
||||
#define REG_AMPDU_MAX_TIME_8192E 0x0456
|
||||
#define REG_BCNQ1_BDNY_8192E 0x0457
|
||||
|
||||
#define REG_AMPDU_MAX_LENGTH_8192E 0x0458
|
||||
#define REG_WMAC_LBK_BUF_HD_8192E 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8192E 0x045F
|
||||
#define REG_DATA_SC_8192E 0x0483
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x0484
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x0488
|
||||
#endif
|
||||
#define REG_ARFR2_8192E 0x048C
|
||||
#define REG_ARFR3_8192E 0x0494
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_AMPDU_BURST_MODE_8192E 0x04BC
|
||||
#define REG_HT_SINGLE_AMPDU_8192E 0x04C7
|
||||
#define REG_MACID_PKT_DROP0_8192E 0x04D0
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_CTWND_8192E 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8192E 0x0577
|
||||
#define REG_SCH_TXCMD_8192E 0x05F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_MAC_CR_8192E 0x0600
|
||||
|
||||
#define REG_MAC_TX_SM_STATE_8192E 0x06B4
|
||||
|
||||
/* Power */
|
||||
#define REG_BFMER0_INFO_8192E 0x06E4
|
||||
#define REG_BFMER1_INFO_8192E 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC
|
||||
|
||||
/* Hardware Port 2 */
|
||||
#define REG_BFMEE_SEL_8192E 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8192E 0x0718
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* Redifine register definition for compatibility
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* TODO: use these definition when using REG_xxx naming rule.
|
||||
* NOTE: DO NOT Remove these definition. Use later. */
|
||||
#define ISR_8192E REG_HISR0_8192E
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8192E IMR/ISR bits (offset 0xB0, 8bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define IMR_DISABLED_8192E 0
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8192E BIT(31) /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8192E BIT(30) /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8192E BIT(29) /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8192E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
|
||||
#define IMR_GTINT3_8192E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8192E BIT(26) /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8192E BIT(25) /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8192E BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8192E BIT(20) /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8192E BIT(16) /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8192E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8192E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8192E BIT(12) /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8192E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
|
||||
#define IMR_CPWM2_8192E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_CPWM_8192E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8192E BIT(7) /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8192E BIT(6) /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8192E BIT(5) /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8192E BIT(4) /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8192E BIT(3) /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8192E BIT(2) /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8192E BIT(1) /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8192E BIT(0) /* Receive DMA OK */
|
||||
|
||||
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
||||
#define IMR_BCNDMAINT7_8192E BIT(27) /* Beacon DMA Interrupt 7 */
|
||||
#define IMR_BCNDMAINT6_8192E BIT(26) /* Beacon DMA Interrupt 6 */
|
||||
#define IMR_BCNDMAINT5_8192E BIT(25) /* Beacon DMA Interrupt 5 */
|
||||
#define IMR_BCNDMAINT4_8192E BIT(24) /* Beacon DMA Interrupt 4 */
|
||||
#define IMR_BCNDMAINT3_8192E BIT(23) /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2_8192E BIT(22) /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1_8192E BIT(21) /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8192E BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
|
||||
#define IMR_BCNDOK6_8192E BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
|
||||
#define IMR_BCNDOK5_8192E BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
|
||||
#define IMR_BCNDOK4_8192E BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
|
||||
#define IMR_BCNDOK3_8192E BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
|
||||
#define IMR_BCNDOK2_8192E BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
|
||||
#define IMR_BCNDOK1_8192E BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
|
||||
#define IMR_ATIMEND_E_8192E BIT(13) /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8192E BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR_8192E BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8192E BIT(9) /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8192E BIT(8) /* Receive FIFO Overflow */
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8192E Auto LLT bits (offset 0x224, 8bits)
|
||||
* ----------------------------------------------------------------------------
|
||||
* 224 REG_AUTO_LLT
|
||||
* move to hal_com_reg.h */
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8192E Auto LLT bits (offset 0x290, 32bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define BIT_DMA_MODE BIT(1)
|
||||
#define BIT_USB_RXDMA_AGG_EN BIT(31)
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8192E REG_SYS_CFG1 (offset 0xF0, 32bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define BIT_SPSLDO_SEL BIT(24)
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8192E REG_CCK_CHECK (offset 0x454, 8bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define BIT_BCN_PORT_SEL BIT(5)
|
||||
|
||||
/* ****************************************************************************
|
||||
* Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
/* 2 ACMHWCTRL 0x05C0 */
|
||||
#define AcmHw_HwEn_8192E BIT(0)
|
||||
#define AcmHw_VoqEn_8192E BIT(1)
|
||||
#define AcmHw_ViqEn_8192E BIT(2)
|
||||
#define AcmHw_BeqEn_8192E BIT(3)
|
||||
#define AcmHw_VoqStatus_8192E BIT(5)
|
||||
#define AcmHw_ViqStatus_8192E BIT(6)
|
||||
#define AcmHw_BeqStatus_8192E BIT(7)
|
||||
|
||||
#endif /* __RTL8192E_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL88812A_SRESET_H_
|
||||
#define _RTL8812A_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8192e_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8192e_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,457 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192E_XMIT_H__
|
||||
#define __RTL8192E_XMIT_H__
|
||||
|
||||
typedef struct txdescriptor_8192e {
|
||||
/* Offset 0 */
|
||||
u32 pktlen:16;
|
||||
u32 offset:8;
|
||||
u32 bmc:1;
|
||||
u32 htc:1;
|
||||
u32 ls:1;
|
||||
u32 fs:1;
|
||||
u32 linip:1;
|
||||
u32 noacm:1;
|
||||
u32 gf:1;
|
||||
u32 own:1;
|
||||
|
||||
/* Offset 4 */
|
||||
u32 macid:6;
|
||||
u32 rsvd0406:2;
|
||||
u32 qsel:5;
|
||||
u32 rd_nav_ext:1;
|
||||
u32 lsig_txop_en:1;
|
||||
u32 pifs:1;
|
||||
u32 rate_id:4;
|
||||
u32 navusehdr:1;
|
||||
u32 en_desc_id:1;
|
||||
u32 sectype:2;
|
||||
u32 rsvd0424:2;
|
||||
u32 pkt_offset:5; /* unit: 8 bytes */
|
||||
u32 rsvd0431:1;
|
||||
|
||||
/* Offset 8 */
|
||||
u32 rts_rc:6;
|
||||
u32 data_rc:6;
|
||||
u32 agg_en:1;
|
||||
u32 rd_en:1;
|
||||
u32 bar_rty_th:2;
|
||||
u32 bk:1;
|
||||
u32 morefrag:1;
|
||||
u32 raw:1;
|
||||
u32 ccx:1;
|
||||
u32 ampdu_density:3;
|
||||
u32 bt_null:1;
|
||||
u32 ant_sel_a:1;
|
||||
u32 ant_sel_b:1;
|
||||
u32 tx_ant_cck:2;
|
||||
u32 tx_antl:2;
|
||||
u32 tx_ant_ht:2;
|
||||
|
||||
/* Offset 12 */
|
||||
u32 nextheadpage:8;
|
||||
u32 tailpage:8;
|
||||
u32 seq:12;
|
||||
u32 cpu_handle:1;
|
||||
u32 tag1:1;
|
||||
u32 trigger_int:1;
|
||||
u32 hwseq_en:1;
|
||||
|
||||
/* Offset 16 */
|
||||
u32 rtsrate:5;
|
||||
u32 ap_dcfe:1;
|
||||
u32 hwseq_sel:2;
|
||||
u32 userate:1;
|
||||
u32 disrtsfb:1;
|
||||
u32 disdatafb:1;
|
||||
u32 cts2self:1;
|
||||
u32 rtsen:1;
|
||||
u32 hw_rts_en:1;
|
||||
u32 port_id:1;
|
||||
u32 pwr_status:3;
|
||||
u32 wait_dcts:1;
|
||||
u32 cts2ap_en:1;
|
||||
u32 data_sc:2;
|
||||
u32 data_stbc:2;
|
||||
u32 data_short:1;
|
||||
u32 data_bw:1;
|
||||
u32 rts_short:1;
|
||||
u32 rts_bw:1;
|
||||
u32 rts_sc:2;
|
||||
u32 vcs_stbc:2;
|
||||
|
||||
/* Offset 20 */
|
||||
u32 datarate:6;
|
||||
u32 sgi:1;
|
||||
u32 try_rate:1;
|
||||
u32 data_ratefb_lmt:5;
|
||||
u32 rts_ratefb_lmt:4;
|
||||
u32 rty_lmt_en:1;
|
||||
u32 data_rt_lmt:6;
|
||||
u32 usb_txagg_num:8;
|
||||
|
||||
/* Offset 24 */
|
||||
u32 txagg_a:5;
|
||||
u32 txagg_b:5;
|
||||
u32 use_max_len:1;
|
||||
u32 max_agg_num:5;
|
||||
u32 mcsg1_max_len:4;
|
||||
u32 mcsg2_max_len:4;
|
||||
u32 mcsg3_max_len:4;
|
||||
u32 mcs7_sgi_max_len:4;
|
||||
|
||||
/* Offset 28 */
|
||||
u32 checksum:16; /* TxBuffSize(PCIe)/CheckSum(USB) */
|
||||
u32 mcsg4_max_len:4;
|
||||
u32 mcsg5_max_len:4;
|
||||
u32 mcsg6_max_len:4;
|
||||
u32 mcs15_sgi_max_len:4;
|
||||
} TXDESC_8192E, *PTXDESC_8192E;
|
||||
|
||||
|
||||
|
||||
/* For 88e early mode */
|
||||
#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
|
||||
#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
|
||||
#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
|
||||
#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
|
||||
|
||||
/*
|
||||
* defined for TX DESC Operation
|
||||
* */
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
/* OFFSET 0 */
|
||||
#define OFFSET_SZ 0
|
||||
#define OFFSET_SHT 16
|
||||
#define BMC BIT(24)
|
||||
#define LSG BIT(26)
|
||||
#define FSG BIT(27)
|
||||
#define OWN BIT(31)
|
||||
|
||||
|
||||
/* OFFSET 4 */
|
||||
#define PKT_OFFSET_SZ 0
|
||||
#define QSEL_SHT 8
|
||||
#define RATE_ID_SHT 16
|
||||
#define NAVUSEHDR BIT(20)
|
||||
#define SEC_TYPE_SHT 22
|
||||
#define PKT_OFFSET_SHT 26
|
||||
|
||||
/* OFFSET 8 */
|
||||
#define AGG_EN BIT(12)
|
||||
#define AGG_BK BIT(16)
|
||||
#define AMPDU_DENSITY_SHT 20
|
||||
#define ANTSEL_A BIT(24)
|
||||
#define ANTSEL_B BIT(25)
|
||||
#define TX_ANT_CCK_SHT 26
|
||||
#define TX_ANTL_SHT 28
|
||||
#define TX_ANT_HT_SHT 30
|
||||
|
||||
/* OFFSET 12 */
|
||||
#define SEQ_SHT 16
|
||||
#define EN_HWSEQ BIT(31)
|
||||
|
||||
/* OFFSET 16 */
|
||||
#define QOS BIT(6)
|
||||
#define HW_SSN BIT(7)
|
||||
#define USERATE BIT(8)
|
||||
#define DISDATAFB BIT(10)
|
||||
#define CTS_2_SELF BIT(11)
|
||||
#define RTS_EN BIT(12)
|
||||
#define HW_RTS_EN BIT(13)
|
||||
#define DATA_SHORT BIT(24)
|
||||
#define PWR_STATUS_SHT 15
|
||||
#define DATA_SC_SHT 20
|
||||
#define DATA_BW BIT(25)
|
||||
|
||||
/* OFFSET 20 */
|
||||
#define RTY_LMT_EN BIT(17)
|
||||
|
||||
|
||||
/* OFFSET 20 */
|
||||
#define SGI BIT(6)
|
||||
#define USB_TXAGG_NUM_SHT 24
|
||||
|
||||
|
||||
/* *****Tx Desc Buffer content */
|
||||
|
||||
/* config element for each tx buffer
|
||||
*
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
|
||||
*/
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*16)+8, 0, 32, __Valeu)
|
||||
|
||||
|
||||
/* Dword 0 */
|
||||
#define SET_TX_BUFF_DESC_LEN_0_92E(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
|
||||
#define SET_TX_BUFF_DESC_PSB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
|
||||
#define SET_TX_BUFF_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
/* Dword 1 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
|
||||
#define GET_TX_DESC_TX_BUFFER_ADDRESS_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
|
||||
|
||||
|
||||
/* Dword 2 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 32, __Value)
|
||||
/* Dword 3, RESERVED */
|
||||
|
||||
|
||||
/* *****Tx Desc content
|
||||
* Dword 0 */
|
||||
#define SET_TX_DESC_PKT_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
|
||||
#define SET_TX_DESC_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
|
||||
#define SET_TX_DESC_BMC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
|
||||
#define SET_TX_DESC_HTC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
|
||||
#define SET_TX_DESC_LAST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
|
||||
#define SET_TX_DESC_FIRST_SEG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
|
||||
#define SET_TX_DESC_LINIP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
|
||||
#define SET_TX_DESC_NO_ACM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
|
||||
#define SET_TX_DESC_GF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
|
||||
#define SET_TX_DESC_OWN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
#define GET_TX_DESC_OWN_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_DESC_MACID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
|
||||
#define SET_TX_DESC_QUEUE_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
|
||||
#define SET_TX_DESC_PIFS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
|
||||
#define SET_TX_DESC_RATE_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
|
||||
#define SET_TX_DESC_EN_DESC_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
|
||||
#define SET_TX_DESC_SEC_TYPE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PKT_OFFSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
|
||||
#define SET_TX_DESC_MORE_DATA_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
|
||||
#define SET_TX_DESC_TXOP_PS_CAP_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 30, 1, __Value)
|
||||
#define SET_TX_DESC_TXOP_PS_MODE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 31, 1, __Value)
|
||||
|
||||
|
||||
/* Dword 2 */
|
||||
#define SET_TX_DESC_PAID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
|
||||
#define SET_TX_DESC_CCA_RTS_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
|
||||
#define SET_TX_DESC_AGG_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RDG_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
|
||||
#define SET_TX_DESC_NULL_0_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
|
||||
#define SET_TX_DESC_NULL_1_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
|
||||
#define SET_TX_DESC_BK_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MORE_FRAG_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
|
||||
#define SET_TX_DESC_RAW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
|
||||
#define GET_TX_DESC_MORE_FRAG_92E(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
|
||||
#define SET_TX_DESC_SPE_RPT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
|
||||
#define SET_TX_DESC_BT_NULL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
|
||||
#define SET_TX_DESC_GID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
|
||||
|
||||
|
||||
/* Dword 3 */
|
||||
#define SET_TX_DESC_WHEADER_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
|
||||
#define SET_TX_DESC_CHK_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
|
||||
#define SET_TX_DESC_EARLY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_SEL_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
|
||||
#define SET_TX_DESC_USE_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_FB_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
|
||||
#define SET_TX_DESC_CTS2SELF_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
|
||||
#define SET_TX_DESC_HW_PORT_ID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
|
||||
#define SET_TX_DESC_NAV_USE_HDR_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
|
||||
#define SET_TX_DESC_USE_MAX_LEN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
|
||||
#define SET_TX_DESC_NDPA_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
|
||||
#define SET_TX_DESC_TRY_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
|
||||
#define SET_TX_DESC_PCTS_ENABLE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
|
||||
#define SET_TX_DESC_PCTS_MASK_IDX_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
|
||||
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_DATA_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
|
||||
#define SET_TX_DESC_DATA_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_BW_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_LDPC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
|
||||
#define SET_TX_DESC_VCS_STBC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_SHORT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_SC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
|
||||
#define SET_TX_DESC_TX_ANT_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
|
||||
#define SET_TX_DESC_TX_POWER_0_PSET_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
|
||||
#define SET_TX_DESC_MBSSID_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_A_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_B_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_C_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_D_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
|
||||
|
||||
/* Dword 7 */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
|
||||
#define SET_TX_DESC_TX_DESC_CHECKSUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
|
||||
|
||||
|
||||
/* #define SET_TX_DESC_HWSEQ_EN_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) */
|
||||
/* Dword 8 */
|
||||
|
||||
#define SET_TX_DESC_RTS_RC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
|
||||
#define SET_TX_DESC_BAR_RTY_TH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_RC_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
|
||||
#define SET_TX_DESC_EN_HWSEQ_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
|
||||
#define SET_TX_DESC_NEXT_HEAD_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
|
||||
#define SET_TX_DESC_TAIL_PAGE_92E(__pTxDesc, __Value)(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_PADDING_LENGTH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
|
||||
#define SET_TX_DESC_TXBF_PATH_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 11, 1, __Value)
|
||||
#define SET_TX_DESC_SEQ_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_92E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
|
||||
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN0_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN1_1_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
|
||||
#define SET_EARLYMODE_LEN1_2_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
|
||||
#define SET_EARLYMODE_LEN2_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN3_92E(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
|
||||
|
||||
void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8192eu_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8192eu_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8192eu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192eu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8192eu_hal_mgmt_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8192eu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192eu_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8192eu_xmit_buf_handler
|
||||
void rtl8192eu_xmit_tasklet(void *priv);
|
||||
s32 rtl8192eu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8192ee_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8192ee_free_xmit_priv(PADAPTER padapter);
|
||||
struct xmit_buf *rtl8192ee_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8192ee_hal_mgmt_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8192ee_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8192ee_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8192ee_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192ee_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
void rtl8192ee_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8192es_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8192es_free_xmit_priv(PADAPTER padapter);
|
||||
|
||||
s32 rtl8192es_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192es_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8192es_hal_mgmt_xmitframe_enqueue(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8192es_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
thread_return rtl8192es_xmit_thread(thread_context context);
|
||||
s32 rtl8192es_xmit_buf_handler(PADAPTER padapter);
|
||||
|
||||
#ifdef CONFIG_SDIO_TX_TASKLET
|
||||
void rtl8192es_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
struct txrpt_ccx_92e {
|
||||
/* offset 0 */
|
||||
u8 tag1:1;
|
||||
u8 pkt_num:3;
|
||||
u8 txdma_underflow:1;
|
||||
u8 int_bt:1;
|
||||
u8 int_tri:1;
|
||||
u8 int_ccx:1;
|
||||
|
||||
/* offset 1 */
|
||||
u8 mac_id:6;
|
||||
u8 pkt_ok:1;
|
||||
u8 bmc:1;
|
||||
|
||||
/* offset 2 */
|
||||
u8 retry_cnt:6;
|
||||
u8 lifetime_over:1;
|
||||
u8 retry_over:1;
|
||||
|
||||
/* offset 3 */
|
||||
u8 ccx_qtime0;
|
||||
u8 ccx_qtime1;
|
||||
|
||||
/* offset 5 */
|
||||
u8 final_data_rate;
|
||||
|
||||
/* offset 6 */
|
||||
u8 sw1:4;
|
||||
u8 qsel:4;
|
||||
|
||||
/* offset 7 */
|
||||
u8 sw0;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_TX_EARLY_MODE
|
||||
void UpdateEarlyModeInfo8192E(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
#endif
|
||||
s32 rtl8192e_init_xmit_priv(_adapter *padapter);
|
||||
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, u8 *ptxdesc);
|
||||
|
||||
void rtl8192e_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen,
|
||||
u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
void rtl8192e_cal_txdesc_chksum(u8 *ptxdesc);
|
||||
|
||||
u8 BWMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
u8 SCMapping_92E(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
void fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_vcs(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
|
||||
void fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void rtl8192e_fixed_rate(_adapter *padapter, u8 *ptxdesc);
|
||||
|
||||
#endif /* __RTL8192E_XMIT_H__ */
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_CMD_H__
|
||||
#define __RTL8192F_CMD_H__
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
enum h2c_cmd_8192F {
|
||||
/* Common Class: 000 */
|
||||
H2C_8192F_RSVD_PAGE = 0x00,
|
||||
H2C_8192F_MEDIA_STATUS_RPT = 0x01,
|
||||
H2C_8192F_SCAN_ENABLE = 0x02,
|
||||
H2C_8192F_KEEP_ALIVE = 0x03,
|
||||
H2C_8192F_DISCON_DECISION = 0x04,
|
||||
H2C_8192F_PSD_OFFLOAD = 0x05,
|
||||
H2C_8192F_AP_OFFLOAD = 0x08,
|
||||
H2C_8192F_BCN_RSVDPAGE = 0x09,
|
||||
H2C_8192F_PROBERSP_RSVDPAGE = 0x0A,
|
||||
H2C_8192F_FCS_RSVDPAGE = 0x10,
|
||||
H2C_8192F_FCS_INFO = 0x11,
|
||||
H2C_8192F_AP_WOW_GPIO_CTRL = 0x13,
|
||||
|
||||
/* PoweSave Class: 001 */
|
||||
H2C_8192F_SET_PWR_MODE = 0x20,
|
||||
H2C_8192F_PS_TUNING_PARA = 0x21,
|
||||
H2C_8192F_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8192F_P2P_LPS_PARAM = 0x23,
|
||||
H2C_8192F_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8192F_PS_SCAN_ENABLE = 0x25,
|
||||
H2C_8192F_SAP_PS_ = 0x26,
|
||||
H2C_8192F_INACTIVE_PS_ = 0x27,/* Inactive_PS */
|
||||
H2C_8192F_FWLPS_IN_IPS_ = 0x28,
|
||||
|
||||
/* Dynamic Mechanism Class: 010 */
|
||||
H2C_8192F_MACID_CFG = 0x40,
|
||||
H2C_8192F_TXBF = 0x41,
|
||||
H2C_8192F_RSSI_SETTING = 0x42,
|
||||
H2C_8192F_AP_REQ_TXRPT = 0x43,
|
||||
H2C_8192F_INIT_RATE_COLLECT = 0x44,
|
||||
H2C_8192F_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
/* BT Class: 011 */
|
||||
H2C_8192F_B_TYPE_TDMA = 0x60,
|
||||
H2C_8192F_BT_INFO = 0x61,
|
||||
H2C_8192F_FORCE_BT_TXPWR = 0x62,
|
||||
H2C_8192F_BT_IGNORE_WLANACT = 0x63,
|
||||
H2C_8192F_DAC_SWING_VALUE = 0x64,
|
||||
H2C_8192F_ANT_SEL_RSV = 0x65,
|
||||
H2C_8192F_WL_OPMODE = 0x66,
|
||||
H2C_8192F_BT_MP_OPER = 0x67,
|
||||
H2C_8192F_BT_CONTROL = 0x68,
|
||||
H2C_8192F_BT_WIFI_CTRL = 0x69,
|
||||
H2C_8192F_BT_FW_PATCH = 0x6A,
|
||||
H2C_8192F_BT_WLAN_CALIBRATION = 0x6D,
|
||||
|
||||
/* WOWLAN Class: 100 */
|
||||
H2C_8192F_WOWLAN = 0x80,
|
||||
H2C_8192F_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8192F_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8192F_AOAC_RSVD_PAGE = 0x83,
|
||||
H2C_8192F_AOAC_RSVD_PAGE2 = 0x84,
|
||||
H2C_8192F_D0_SCAN_OFFLOAD_CTRL = 0x85,
|
||||
H2C_8192F_D0_SCAN_OFFLOAD_INFO = 0x86,
|
||||
H2C_8192F_CHNL_SWITCH_OFFLOAD = 0x87,
|
||||
H2C_8192F_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
|
||||
H2C_8192F_P2P_OFFLOAD = 0x8B,
|
||||
|
||||
H2C_8192F_RESET_TSF = 0xC0,
|
||||
H2C_8192F_MAXID,
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
|
||||
* ---------------------------------------------------------------------------------------------------------
|
||||
* _RSVDPAGE_LOC_CMD_0x00 */
|
||||
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/*_MEDIA_STATUS_RPT_PARM_CMD_0x01*/
|
||||
#define SET_8192F_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
/* _PWR_MOD_CMD_0x20 */
|
||||
#define SET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8192F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_8192F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _PS_TUNE_PARAM_CMD_0x21 */
|
||||
#define SET_8192F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
|
||||
#define SET_8192F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _MACID_CFG_CMD_0x40 */
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
|
||||
|
||||
/* _RSSI_SETTING_CMD_0x42 */
|
||||
#define SET_8192F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
|
||||
#define SET_8192F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _AP_REQ_TXRPT_CMD_0x43 */
|
||||
#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_TXPWR_CMD_0x62 */
|
||||
#define SET_8192F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_MP_OPER_CMD_0x67 */
|
||||
#define SET_8192F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
|
||||
/* _BT_FW_PATCH_0x6A */
|
||||
#define SET_8192F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ------------------------------------------- Structure --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- Function Statement --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/* host message to firmware cmd */
|
||||
void rtl8192f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8192f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
|
||||
/* s32 rtl8192f__set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
|
||||
void rtl8192f_set_FwPsTuneParam_cmd(PADAPTER padapter);
|
||||
void rtl8192f_download_rsvd_page(PADAPTER padapter, u8 mstatus);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8192f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8192f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
void rtl8192f_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
/* AP_REQ_TXREP_CMD 0x43 */
|
||||
#define SET_8192F_H2CCMD_TXREP_PARM_STA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_TXREP_PARM_STA2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8192F_H2CCMD_TXREP_PARM_RTY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 2, __Value)
|
||||
|
||||
/* C2H_AP_REQ_TXRPT */
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_MACID1(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXOK1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXFAIL1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_INIRATE1(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_MACID2(_Header) LE_BITS_TO_1BYTE((_Header + 6), 0, 8)
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXOK2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_TXFAIL2(_Header) LE_BITS_TO_2BYTE((_Header + 9), 0, 16)
|
||||
#define GET_8192F_C2H_TC2H_APREQ_TXRPT_INIRATE2(_Header) LE_BITS_TO_1BYTE((_Header + 11), 0, 8)
|
||||
|
||||
/* C2H_SPC_STAT */
|
||||
#define GET_8192F_C2H_SPC_STAT_IDX(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 8)
|
||||
/* Tip :TYPE_A data3 is msb and data0 is lsb */
|
||||
#define GET_8192F_C2H_SPC_STAT_TYPEA_RETRY(_Header) LE_BITS_TO_4BYTE((_Header + 1), 0, 32)
|
||||
#define GET_8192F_C2H_SPC_STAT_TYPEB_PKT1(_Header) LE_BITS_TO_2BYTE((_Header + 1), 0, 16)
|
||||
#define GET_8192F_C2H_SPC_STAT_TYPEB_RETRY1(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16)
|
||||
#define GET_8192F_C2H_SPC_STAT_TYPEB_PKT2(_Header) LE_BITS_TO_2BYTE((_Header + 5), 0, 16)
|
||||
#define GET_8192F_C2H_SPC_STAT_TYPEB_RETRY2(_Header) LE_BITS_TO_2BYTE((_Header + 7), 0, 16)
|
||||
|
||||
void rtl8192f_req_txrpt_cmd(PADAPTER, u8 macid);
|
||||
s32 FillH2CCmd8192F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
u8 GetTxBufferRsvdPageNum8192F(_adapter *padapter, bool wowlan);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_DM_H__
|
||||
#define __RTL8192F_DM_H__
|
||||
|
||||
void rtl8192f_init_dm_priv(PADAPTER Adapter);
|
||||
void rtl8192f_deinit_dm_priv(PADAPTER Adapter);
|
||||
void rtl8192f_InitHalDm(PADAPTER Adapter);
|
||||
void rtl8192f_HalDmWatchDog(PADAPTER Adapter);
|
||||
|
||||
/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
|
||||
|
||||
/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
|
||||
#if defined (CONFIG_CONCURRENT_MODE) && defined (CONFIG_TSF_SYNC)
|
||||
void rtl8192f_sync_tsfr(_adapter *Adapter);
|
||||
#endif/*(CONFIG_CONCURRENT_MODE) && defined (CONFIG_TSF_SYNC)*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_HAL_H__
|
||||
#define __RTL8192F_HAL_H__
|
||||
|
||||
#include "hal_data.h"
|
||||
|
||||
#include "rtl8192f_spec.h"
|
||||
#include "rtl8192f_rf.h"
|
||||
#include "rtl8192f_dm.h"
|
||||
#include "rtl8192f_recv.h"
|
||||
#include "rtl8192f_xmit.h"
|
||||
#include "rtl8192f_cmd.h"
|
||||
#include "rtl8192f_led.h"
|
||||
#include "Hal8192FPwrSeq.h"
|
||||
#include "Hal8192FPhyReg.h"
|
||||
#include "Hal8192FPhyCfg.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8192f_sreset.h"
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_POFF
|
||||
#include "rtl8192f_lps_poff.h"
|
||||
#endif
|
||||
|
||||
#define FW_8192F_SIZE 0x8000
|
||||
#define FW_8192F_START_ADDRESS 0x4000
|
||||
#define FW_8192F_END_ADDRESS 0x5000 /* brian_zhang@realsil.com.cn */
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8192F(_pFwHdr)\
|
||||
((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x92F0)
|
||||
|
||||
typedef struct _RT_FIRMWARE {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_8192F_SIZE];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8192F, *PRT_FIRMWARE_8192F;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
typedef struct _RT_8192F_FIRMWARE_HDR {
|
||||
/* 8-byte alinment required */
|
||||
|
||||
/* --- LONG WORD 0 ---- */
|
||||
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
u8 Category; /* AP/NIC and USB/PCI */
|
||||
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
u16 Version; /* FW Version */
|
||||
u16 Subversion; /* FW Subversion, default 0x00 */
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
u8 Month; /* Release time Month field */
|
||||
u8 Date; /* Release time Date field */
|
||||
u8 Hour; /* Release time Hour field */
|
||||
u8 Minute; /* Release time Minute field */
|
||||
u16 RamCodeSize; /* The size of RAM code */
|
||||
u16 Rsvd2;
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
u32 SvnIdx; /* The SVN entry index */
|
||||
u32 Rsvd3;
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
} RT_8192F_FIRMWARE_HDR, *PRT_8192F_FIRMWARE_HDR;
|
||||
#define DRIVER_EARLY_INT_TIME_8192F 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8192F 0x02
|
||||
/* for 8192F
|
||||
* TX 64K, RX 16K, Page size 256B for TX*/
|
||||
#define PAGE_SIZE_TX_8192F 256
|
||||
#define PAGE_SIZE_RX_8192F 8
|
||||
#define TX_DMA_SIZE_8192F 0x10000/* 64K(TX) */
|
||||
#define RX_DMA_SIZE_8192F 0x4000/* 16K(RX) */
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8192F 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8192F 0xc0 /* 192B, reserved for tx report 24*8=192*/
|
||||
#endif
|
||||
#define RX_DMA_BOUNDARY_8192F\
|
||||
(RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F - 1)
|
||||
|
||||
|
||||
/* Note: We will divide number of page equally for each queue other than public queue! */
|
||||
|
||||
/* For General Reserved Page Number(Beacon Queue is reserved page)
|
||||
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8192F
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
|
||||
#define BCNQ_PAGE_NUM_8192F (MAX_BEACON_LEN/PAGE_SIZE_TX_8192F + 6) /*0x08*/
|
||||
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
|
||||
* NS offload: 2 NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
|
||||
#define WOWLAN_KEEP_ALIVE_PAGE 0x02 /*for keep alive packet*/
|
||||
#else
|
||||
#define WOWLAN_KEEP_ALIVE_PAGE 0x00
|
||||
#endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
|
||||
/* 7 pages for wow rsvd page + 2 pages for pattern */
|
||||
#define WOWLAN_PAGE_NUM_8192F (0x09 + WOWLAN_KEEP_ALIVE_PAGE)
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8192F 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_WOW_PATTERN_IN_TXFIFO
|
||||
/* REG_TXBUF_WKCAM_OFFSET 0x1B1[15:0] */
|
||||
#define WKCAM_OFFSET_BIT_MASK 0xFFFF
|
||||
#define WKCAM_OFFSET_BIT_MASK_OFFSET 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#undef WOWLAN_PAGE_NUM_8192F
|
||||
#define WOWLAN_PAGE_NUM_8192F 0x15
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_WOWLAN
|
||||
#define AP_WOWLAN_PAGE_NUM_8192F 0x02
|
||||
#endif
|
||||
|
||||
#ifdef DBG_LA_MODE
|
||||
#define LA_MODE_PAGE_NUM 0xE0
|
||||
#endif
|
||||
|
||||
#define MAX_RX_DMA_BUFFER_SIZE_8192F (RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
|
||||
|
||||
#ifdef DBG_LA_MODE
|
||||
#define TX_TOTAL_PAGE_NUMBER_8192F (0xFF - LA_MODE_PAGE_NUM)
|
||||
#else
|
||||
#define TX_TOTAL_PAGE_NUMBER_8192F (0xFF - BCNQ_PAGE_NUM_8192F - WOWLAN_PAGE_NUM_8192F)
|
||||
#endif
|
||||
|
||||
#define TX_PAGE_BOUNDARY_8192F (TX_TOTAL_PAGE_NUMBER_8192F + 1)
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F \
|
||||
TX_TOTAL_PAGE_NUMBER_8192F
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8192F \
|
||||
(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8192F + 1)
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192F */
|
||||
#define NORMAL_PAGE_NUM_HPQ_8192F 0x8
|
||||
#define NORMAL_PAGE_NUM_LPQ_8192F 0x8
|
||||
#define NORMAL_PAGE_NUM_NPQ_8192F 0x8
|
||||
#define NORMAL_PAGE_NUM_EPQ_8192F 0x00
|
||||
|
||||
/* Note: For Normal Chip Setting, modify later */
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8192F 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8192F 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8192F 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_EPQ_8192F 0x00
|
||||
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
#define EFUSE_OOB_PROTECT_BYTES 56 /*0x1C8~0x1FF*/
|
||||
|
||||
#define HAL_EFUSE_MEMORY
|
||||
#define HWSET_MAX_SIZE_8192F 512
|
||||
#define EFUSE_REAL_CONTENT_LEN_8192F 512
|
||||
#define EFUSE_MAP_LEN_8192F 512
|
||||
#define EFUSE_MAX_SECTION_8192F 64
|
||||
|
||||
/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
|
||||
#define EFUSE_IC_ID_OFFSET 506
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8192F)
|
||||
|
||||
#define EFUSE_ACCESS_ON 0x69
|
||||
#define EFUSE_ACCESS_OFF 0x00
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define BANK_NUM 1
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN 1536/*512 * 3 */
|
||||
/* (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)*/
|
||||
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
typedef enum tag_Package_Definition {
|
||||
PACKAGE_DEFAULT,
|
||||
PACKAGE_QFN32,
|
||||
PACKAGE_QFN40,
|
||||
PACKAGE_QFN46
|
||||
} PACKAGE_TYPE_E;
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
|
||||
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
|
||||
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
#ifdef CONFIG_FILE_FWIMG
|
||||
extern char *rtw_fw_file_path;
|
||||
extern char *rtw_fw_wow_file_path;
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
extern char *rtw_fw_mp_bt_file_path;
|
||||
#endif /* CONFIG_MP_INCLUDED */
|
||||
#endif /* CONFIG_FILE_FWIMG */
|
||||
|
||||
/* rtl8192f_hal_init.c */
|
||||
s32 rtl8192f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
|
||||
void rtl8192f_FirmwareSelfReset(PADAPTER padapter);
|
||||
void rtl8192f_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
void rtl8192f_InitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8192f_DeinitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8192f_CheckAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8192f_init_default_value(PADAPTER padapter);
|
||||
|
||||
s32 rtl8192f_InitLLTTable(PADAPTER padapter);
|
||||
|
||||
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
|
||||
s32 CardDisableWithoutHWSM(PADAPTER padapter);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8192F(PADAPTER padapter);
|
||||
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_EfuseParseTxPowerInfo_8192F(PADAPTER padapter,
|
||||
u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void Hal_EfuseParseBTCoexistInfo_8192F(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
void Hal_EfuseParseEEPROMVer_8192F(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseChnlPlan_8192F(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID_8192F(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseAntennaDiversity_8192F(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8192F(PADAPTER pAdapter,
|
||||
u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseThermalMeter_8192F(PADAPTER padapter,
|
||||
u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseVoltage_8192F(PADAPTER pAdapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBoardType_8192F(PADAPTER Adapter,
|
||||
u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
u8 Hal_ReadRFEType_8192F(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void rtl8192f_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8192f(_adapter *adapter);
|
||||
u8 SetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8192F(PADAPTER padapter, u8 variable, u8 *val);
|
||||
u8 SetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
u8 GetHalDefVar8192F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
|
||||
/* register */
|
||||
void rtl8192f_InitBeaconParameters(PADAPTER padapter);
|
||||
void rtl8192f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
|
||||
|
||||
void _InitMacAPLLSetting_8192F(PADAPTER Adapter);
|
||||
void _8051Reset8192F(PADAPTER padapter);
|
||||
#ifdef CONFIG_WOWLAN
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
void rtl8192f_start_thread(_adapter *padapter);
|
||||
void rtl8192f_stop_thread(_adapter *padapter);
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void rtl8192fs_init_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8192fs_free_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8192fs_cancle_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8192fs_hal_check_bt_hang(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
|
||||
#endif
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
|
||||
#endif
|
||||
void CCX_FwC2HTxRpt_8192f(PADAPTER padapter, u8 *pdata, u8 len);
|
||||
|
||||
u8 MRateToHwRate8192F(u8 rate);
|
||||
u8 HwRateToMRate8192F(u8 rate);
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void check_bt_status_work(void *data);
|
||||
#endif
|
||||
|
||||
|
||||
void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
|
||||
#ifdef CONFIG_AMPDU_PRETX_CD
|
||||
void rtl8192f_pretx_cd_config(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
BOOLEAN InterruptRecognized8192FE(PADAPTER Adapter);
|
||||
void UpdateInterruptMask8192FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
void InitMAC_TRXBD_8192FE(PADAPTER Adapter);
|
||||
|
||||
u16 get_txbd_rw_reg(u16 ff_hwaddr);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_LED_H__
|
||||
#define __RTL8192F_LED_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
/** REG_LED_CFG (0x4C) **/
|
||||
/* LED0 GPIO Enable, 0: disable, 1: enable*/
|
||||
#define LED0_GPIO_ENABLE_8192FU (BIT21)
|
||||
/* LED0 Disabled for analog signal usage, 0:Enable (output mode), 1: disable (input mode) */
|
||||
#define LED0_DISABLE_ANALOGSIGNAL_8192FU (BIT7)
|
||||
/* LED0 software value, 0: turn off, 1:turn on */
|
||||
#define LED0_SW_VALUE_8192FU (BIT3)
|
||||
|
||||
/** REG_GPIO_MUXCFG (0x40) **/
|
||||
/* Enable LED[1:0] for RFE CTRL[7:6], 0: BT, 1: Wi-Fi */
|
||||
#define ENABLE_LED0_AND_LED1_CTRL_BY_WIFI_8192FU (BIT3)
|
||||
|
||||
/** REG_SW_GPIO_SHARE_CTRL_0 (0x1038) **/
|
||||
/* LED Output PIN Location, 0: GPIOA_0, 1:GPIOB_4*/
|
||||
#define LED_OUTPUT_PIN_LOCATION_8192FU (BIT16)
|
||||
|
||||
u8 rtl8192fu_CfgLed0Hw(PADAPTER padapter);
|
||||
void rtl8192fu_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8192fu_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8192fs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8192fs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8192fe_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8192fe_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#endif /*#ifdef CONFIG_RTW_SW_LED*/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_RECV_H__
|
||||
#define __RTL8192F_RECV_H__
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
#ifdef CONFIG_PLATFORM_MSTAR
|
||||
#define MAX_RECVBUF_SZ (8192) /* 8K */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (32768) /* 32k */
|
||||
#endif
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8192F + 1)
|
||||
|
||||
#endif
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#ifndef CONFIG_SDIO_RX_COPY
|
||||
#undef MAX_RECVBUF_SZ
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8192F - RX_DMA_RESERVED_SIZE_8192F)
|
||||
#endif /* !CONFIG_SDIO_RX_COPY */
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RTL8192F RX BUFFER DESC */
|
||||
/*-----------------------------------------------------------------*/
|
||||
/*DWORD 0*/
|
||||
#define SET_RX_BUFFER_DESC_DATA_LENGTH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
|
||||
|
||||
#define GET_RX_BUFFER_DESC_OWN_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
#define GET_RX_BUFFER_DESC_LS_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_BUFFER_DESC_FS_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
|
||||
#ifdef USING_RX_TAG
|
||||
#define GET_RX_BUFFER_DESC_RX_TAG_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
|
||||
#else
|
||||
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8192F(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
|
||||
#endif
|
||||
|
||||
/*DWORD 1*/
|
||||
#define SET_RX_BUFFER_PHYSICAL_LOW_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
|
||||
|
||||
/*DWORD 2*/
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
|
||||
#else
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH_8192F(__pRxStatusDesc, __Value)
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8192fs_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8192fs_free_recv_priv(PADAPTER padapter);
|
||||
s32 rtl8192fs_recv_hdl(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
int rtl8192fu_init_recv_priv(_adapter *padapter);
|
||||
void rtl8192fu_free_recv_priv(_adapter *padapter);
|
||||
void rtl8192fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8192fe_init_recv_priv(_adapter *padapter);
|
||||
void rtl8192fe_free_recv_priv(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
void rtl8192f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8192F_RECV_H__ */
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2012 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_RF_H__
|
||||
#define __RTL8192F_RF_H__
|
||||
|
||||
/*default*/
|
||||
/*#define CONFIG_8192F_DRV_DIS*/
|
||||
/*AP*/
|
||||
#define CONFIG_8192F_TYPE3_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE4_DRV_DIS
|
||||
/*unused*/
|
||||
#define CONFIG_8192F_TYPE20_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE21_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE22_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE23_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE24_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE25_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE26_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE27_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE28_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE29_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE30_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE31_DRV_DIS
|
||||
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI /**/
|
||||
/*usb*/
|
||||
#define CONFIG_8192F_TYPE1_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE5_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE10_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE13_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE14_DRV_DIS
|
||||
/*pcie*/
|
||||
#define CONFIG_8192F_TYPE0_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE6_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE7_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE8_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE9_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE12_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE15_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE16_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE17_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE18_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE19_DRV_DIS
|
||||
#endif/*CONFIG_SDIO_HCI*/
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
/*sdio*/
|
||||
#define CONFIG_8192F_TYPE2_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE11_DRV_DIS
|
||||
/*pcie*/
|
||||
#define CONFIG_8192F_TYPE0_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE6_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE7_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE8_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE9_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE12_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE15_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE16_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE17_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE18_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE19_DRV_DIS
|
||||
#endif/*CONFIG_USB_HCI*/
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/*sdio*/
|
||||
#define CONFIG_8192F_TYPE2_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE11_DRV_DIS
|
||||
/*usb*/
|
||||
#define CONFIG_8192F_TYPE1_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE5_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE10_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE13_DRV_DIS
|
||||
#define CONFIG_8192F_TYPE14_DRV_DIS
|
||||
#endif/*CONFIG_PCI_HCI*/
|
||||
|
||||
int PHY_RF6052_Config8192F(PADAPTER pdapter);
|
||||
|
||||
void PHY_RF6052SetBandwidth8192F(PADAPTER Adapter, enum channel_width Bandwidth);
|
||||
|
||||
#endif/* __RTL8192F_RF_H__ */
|
||||
|
|
@ -0,0 +1,541 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_SPEC_H__
|
||||
#define __RTL8192F_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
|
||||
#define HAL_NAV_UPPER_UNIT_8192F 128 /* micro-second */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SYS_ISO_CTRL_8192F 0x0000 /* 2 Byte */
|
||||
#define REG_SYS_FUNC_EN_8192F 0x0002 /* 2 Byte */
|
||||
#define REG_APS_FSMCO_8192F 0x0004 /* 4 Byte */
|
||||
#define REG_SYS_CLKR_8192F 0x0008 /* 2 Byte */
|
||||
#define REG_9346CR_8192F 0x000A /* 2 Byte */
|
||||
#define REG_EE_VPD_8192F 0x000C /* 2 Byte */
|
||||
#define REG_AFE_MISC_8192F 0x0010 /* 1 Byte */
|
||||
#define REG_SPS0_CTRL_8192F 0x0011 /* 7 Byte */
|
||||
#define REG_SPS_OCP_CFG_8192F 0x0018 /* 4 Byte */
|
||||
#define REG_RSV_CTRL_8192F 0x001C /* 3 Byte */
|
||||
#define REG_RF_CTRL_8192F 0x001F /* 1 Byte */
|
||||
#define REG_LPLDO_CTRL_8192F 0x0023 /* 1 Byte */
|
||||
#define REG_AFE_XTAL_CTRL_8192F 0x0024 /* 4 Byte */
|
||||
#define REG_AFE_PLL_CTRL_8192F 0x0028 /* 4 Byte */
|
||||
#define REG_MAC_PLL_CTRL_EXT_8192F 0x002c /* 4 Byte */
|
||||
#define REG_EFUSE_CTRL_8192F 0x0030
|
||||
#define REG_EFUSE_TEST_8192F 0x0034
|
||||
#define REG_PWR_DATA_8192F 0x0038
|
||||
#define REG_CAL_TIMER_8192F 0x003C
|
||||
#define REG_ACLK_MON_8192F 0x003E
|
||||
#define REG_GPIO_MUXCFG_8192F 0x0040
|
||||
#define REG_GPIO_IO_SEL_8192F 0x0042
|
||||
#define REG_MAC_PINMUX_CFG_8192F 0x0043
|
||||
#define REG_GPIO_PIN_CTRL_8192F 0x0044
|
||||
#define REG_GPIO_INTM_8192F 0x0048
|
||||
#define REG_LEDCFG0_8192F 0x004C
|
||||
#define REG_LEDCFG1_8192F 0x004D
|
||||
#define REG_LEDCFG2_8192F 0x004E
|
||||
#define REG_LEDCFG3_8192F 0x004F
|
||||
#define REG_FSIMR_8192F 0x0050
|
||||
#define REG_FSISR_8192F 0x0054
|
||||
#define REG_HSIMR_8192F 0x0058
|
||||
#define REG_HSISR_8192F 0x005c
|
||||
#define REG_GPIO_EXT_CTRL 0x0060
|
||||
#define REG_PAD_CTRL1_8192F 0x0064
|
||||
#define REG_MULTI_FUNC_CTRL_8192F 0x0068
|
||||
#define REG_GPIO_STATUS_8192F 0x006C
|
||||
#define REG_SDIO_CTRL_8192F 0x0070
|
||||
#define REG_OPT_CTRL_8192F 0x0074
|
||||
#define REG_AFE_CTRL_4_8192F 0x0078
|
||||
#define REG_MCUFWDL_8192F 0x0080
|
||||
#define REG_8051FW_CTRL_8192F 0x0080
|
||||
#define REG_HMEBOX_DBG_0_8192F 0x0088
|
||||
#define REG_HMEBOX_DBG_1_8192F 0x008A
|
||||
#define REG_HMEBOX_DBG_2_8192F 0x008C
|
||||
#define REG_HMEBOX_DBG_3_8192F 0x008E
|
||||
#define REG_WLLPS_CTRL 0x0090
|
||||
#define REG_HIMR0_8192F 0x00B0
|
||||
#define REG_HISR0_8192F 0x00B4
|
||||
#define REG_HIMR1_8192F 0x00B8
|
||||
#define REG_HISR1_8192F 0x00BC
|
||||
#define REG_PMC_DBG_CTRL2_8192F 0x00CC
|
||||
#define REG_EFUSE_BURN_GNT_8192F 0x00CF
|
||||
#define REG_HPON_FSM_8192F 0x00EC
|
||||
#define REG_SYS_CFG1_8192F 0x00F0
|
||||
#define REG_SYS_CFG2_8192F 0x00FC
|
||||
#define REG_ROM_VERSION 0x00FD
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_CR_8192F 0x0100
|
||||
#define REG_PBP_8192F 0x0104
|
||||
#define REG_PKT_BUFF_ACCESS_CTRL_8192F 0x0106
|
||||
#define REG_TRXDMA_CTRL_8192F 0x010C
|
||||
#define REG_TRXFF_BNDY_8192F 0x0114
|
||||
#define REG_TRXFF_STATUS_8192F 0x0118
|
||||
#define REG_RXFF_PTR_8192F 0x011C
|
||||
#define REG_CPWM_8192F 0x012C
|
||||
#define REG_FWIMR_8192F 0x0130
|
||||
#define REG_FWISR_8192F 0x0134
|
||||
#define REG_FTIMR_8192F 0x0138
|
||||
#define REG_PKTBUF_DBG_CTRL_8192F 0x0140
|
||||
#define REG_RXPKTBUF_CTRL_8192F 0x0142
|
||||
#define REG_PKTBUF_DBG_DATA_L_8192F 0x0144
|
||||
#define REG_PKTBUF_DBG_DATA_H_8192F 0x0148
|
||||
|
||||
#define REG_TC0_CTRL_8192F 0x0150
|
||||
#define REG_TC1_CTRL_8192F 0x0154
|
||||
#define REG_TC2_CTRL_8192F 0x0158
|
||||
#define REG_TC3_CTRL_8192F 0x015C
|
||||
#define REG_TC4_CTRL_8192F 0x0160
|
||||
#define REG_TCUNIT_BASE_8192F 0x0164
|
||||
#define REG_RSVD3_8192F 0x0168
|
||||
#define REG_C2HEVT_CMD_ID_8192F 0x01A0
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
|
||||
#define REG_C2HEVT_CMD_LEN_8192F 0x01AE
|
||||
#define REG_C2HEVT_CLEAR_8192F 0x01AF
|
||||
#define REG_TXBUF_WKCAM_OFFSET 0x01B1 /* RTL8192F */
|
||||
#define REG_MCUTST_1_8192F 0x01C0
|
||||
#define REG_WOWLAN_WAKE_REASON 0x01C7
|
||||
#define REG_FMETHR_8192F 0x01C8
|
||||
#define REG_HMETFR_8192F 0x01CC
|
||||
#define REG_HMEBOX_0_8192F 0x01D0
|
||||
#define REG_HMEBOX_1_8192F 0x01D4
|
||||
#define REG_HMEBOX_2_8192F 0x01D8
|
||||
#define REG_HMEBOX_3_8192F 0x01DC
|
||||
#define REG_LLT_INIT_8192F 0x01E0
|
||||
#define REG_HMEBOX_EXT0_8192F 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8192F 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8192F 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8192F 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RQPN_8192F 0x0200
|
||||
#define REG_FIFOPAGE_8192F 0x0204
|
||||
#define REG_DWBCN0_CTRL_8192F REG_TDECTRL
|
||||
#define REG_TXDMA_OFFSET_CHK_8192F 0x020C
|
||||
#define REG_TXDMA_STATUS_8192F 0x0210
|
||||
#define REG_RQPN_NPQ_8192F 0x0214
|
||||
#define REG_DWBCN1_CTRL_8192F 0x0228
|
||||
#define REG_RQPN_EXQ1_EXQ2 0x0230
|
||||
#define REG_TQPNT3_V1_8192F 0x0234
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RXDMA_AGG_PG_TH_8192F 0x0280
|
||||
#define REG_FW_UPD_RDPTR_8192F 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
|
||||
#define REG_RXDMA_CONTROL_8192F 0x0286 /* Control the RX DMA. */
|
||||
#define REG_RXDMA_STATUS_8192F 0x0288
|
||||
#define REG_RXDMA_MODE_CTRL_8192F 0x0290
|
||||
#define REG_EARLY_MODE_CONTROL_8192F 0x02BC
|
||||
#define REG_RSVD5_8192F 0x02F0
|
||||
#define REG_RSVD6_8192F 0x02F4
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8192F 0x0300
|
||||
#define REG_INT_MIG_8192F 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_TXBD_DESA_8192F 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_MGQ_TXBD_DESA_8192F 0x0310 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_TXBD_DESA_8192F 0x0318 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_TXBD_DESA_8192F 0x0320 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_TXBD_DESA_8192F 0x0328 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_TXBD_DESA_8192F 0x0330 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RXQ_RXBD_DESA_8192F 0x0338 /* RX Queue Descriptor Address */
|
||||
#define REG_HI0Q_TXBD_DESA_8192F 0x0340
|
||||
#define REG_HI1Q_TXBD_DESA_8192F 0x0348
|
||||
#define REG_HI2Q_TXBD_DESA_8192F 0x0350
|
||||
#define REG_HI3Q_TXBD_DESA_8192F 0x0358
|
||||
#define REG_HI4Q_TXBD_DESA_8192F 0x0360
|
||||
#define REG_HI5Q_TXBD_DESA_8192F 0x0368
|
||||
#define REG_HI6Q_TXBD_DESA_8192F 0x0370
|
||||
#define REG_HI7Q_TXBD_DESA_8192F 0x0378
|
||||
#define REG_MGQ_TXBD_NUM_8192F 0x0380
|
||||
#define REG_RX_RXBD_NUM_8192F 0x0382
|
||||
#define REG_VOQ_TXBD_NUM_8192F 0x0384
|
||||
#define REG_VIQ_TXBD_NUM_8192F 0x0386
|
||||
#define REG_BEQ_TXBD_NUM_8192F 0x0388
|
||||
#define REG_BKQ_TXBD_NUM_8192F 0x038A
|
||||
#define REG_HI0Q_TXBD_NUM_8192F 0x038C
|
||||
#define REG_HI1Q_TXBD_NUM_8192F 0x038E
|
||||
#define REG_HI2Q_TXBD_NUM_8192F 0x0390
|
||||
#define REG_HI3Q_TXBD_NUM_8192F 0x0392
|
||||
#define REG_HI4Q_TXBD_NUM_8192F 0x0394
|
||||
#define REG_HI5Q_TXBD_NUM_8192F 0x0396
|
||||
#define REG_HI6Q_TXBD_NUM_8192F 0x0398
|
||||
#define REG_HI7Q_TXBD_NUM_8192F 0x039A
|
||||
#define REG_TSFTIMER_HCI_8192F 0x039C
|
||||
#define REG_BD_RW_PTR_CLR_8192F 0x039C
|
||||
|
||||
/* Read Write Point */
|
||||
#define REG_VOQ_TXBD_IDX_8192F 0x03A0
|
||||
#define REG_VIQ_TXBD_IDX_8192F 0x03A4
|
||||
#define REG_BEQ_TXBD_IDX_8192F 0x03A8
|
||||
#define REG_BKQ_TXBD_IDX_8192F 0x03AC
|
||||
#define REG_MGQ_TXBD_IDX_8192F 0x03B0
|
||||
#define REG_RXQ_TXBD_IDX_8192F 0x03B4
|
||||
#define REG_HI0Q_TXBD_IDX_8192F 0x03B8
|
||||
#define REG_HI1Q_TXBD_IDX_8192F 0x03BC
|
||||
#define REG_HI2Q_TXBD_IDX_8192F 0x03C0
|
||||
#define REG_HI3Q_TXBD_IDX_8192F 0x03C4
|
||||
#define REG_HI4Q_TXBD_IDX_8192F 0x03C8
|
||||
#define REG_HI5Q_TXBD_IDX_8192F 0x03CC
|
||||
#define REG_HI6Q_TXBD_IDX_8192F 0x03D0
|
||||
#define REG_HI7Q_TXBD_IDX_8192F 0x03D4
|
||||
#define REG_DBI_WDATA_V1_8192F 0x03E8
|
||||
#define REG_DBI_RDATA_V1_8192F 0x03EC
|
||||
#define REG_DBI_FLAG_V1_8192F 0x03F0
|
||||
#define REG_MDIO_V1_8192F 0x03F4
|
||||
#define REG_HCI_MIX_CFG_8192F 0x03FC
|
||||
#define REG_PCIE_HCPWM_8192FE 0x03D8
|
||||
#define REG_PCIE_HRPWM_8192FE 0x03DC
|
||||
#define REG_PCIE_MIX_CFG_8192F 0x03F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_QUEUELIST_INFO0_8192F 0x0400
|
||||
#define REG_QUEUELIST_INFO1_8192F 0x0404
|
||||
#define REG_QUEUELIST_INFO2_8192F 0x0414
|
||||
#define REG_TXPKT_EMPTY_8192F 0x0418
|
||||
|
||||
#define REG_FWHW_TXQ_CTRL_8192F 0x0420
|
||||
#define REG_HWSEQ_CTRL_8192F 0x0423
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY_8192F 0x0424
|
||||
#define REG_TXPKTBUF_MGQ_BDNY_8192F 0x0425
|
||||
#define REG_LIFECTRL_CTRL_8192F 0x0426
|
||||
#define REG_MULTI_BCNQ_OFFSET_8192F 0x0427
|
||||
#define REG_SPEC_SIFS_8192F 0x0428
|
||||
#define REG_RL_8192F 0x042A
|
||||
#define REG_TXBF_CTRL_8192F 0x042C
|
||||
#define REG_DARFRC_8192F 0x0430
|
||||
#define REG_RARFRC_8192F 0x0438
|
||||
#define REG_RRSR_8192F 0x0440
|
||||
#define REG_ARFR0_8192F 0x0444
|
||||
#define REG_ARFR1_8192F 0x044C
|
||||
#define REG_CCK_CHECK_8192F 0x0454
|
||||
#define REG_AMPDU_MAX_TIME_8192F 0x0456
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY1_8192F 0x0457
|
||||
|
||||
#define REG_AMPDU_MAX_LENGTH_8192F 0x0458
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8192F 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8192F 0x045F
|
||||
#define REG_FAST_EDCA_CTRL_8192F 0x0460
|
||||
#define REG_RD_RESP_PKT_TH_8192F 0x0463
|
||||
#define REG_DATA_SC_8192F 0x0483
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_POWER_STAGE1_8192F 0x04B4
|
||||
#define REG_POWER_STAGE2_8192F 0x04B8
|
||||
#define REG_AMPDU_BURST_MODE_8192F 0x04BC
|
||||
#define REG_PKT_VO_VI_LIFE_TIME_8192F 0x04C0
|
||||
#define REG_PKT_BE_BK_LIFE_TIME_8192F 0x04C2
|
||||
#define REG_STBC_SETTING_8192F 0x04C4
|
||||
#define REG_HT_SINGLE_AMPDU_8192F 0x04C7
|
||||
#define REG_PROT_MODE_CTRL_8192F 0x04C8
|
||||
#define REG_MAX_AGGR_NUM_8192F 0x04CA
|
||||
#define REG_RTS_MAX_AGGR_NUM_8192F 0x04CB
|
||||
#define REG_BAR_MODE_CTRL_8192F 0x04CC
|
||||
#define REG_RA_TRY_RATE_AGG_LMT_8192F 0x04CF
|
||||
#define REG_MACID_PKT_DROP0_8192F 0x04D0
|
||||
#define REG_MACID_PKT_SLEEP_8192F 0x04D4
|
||||
#define REG_PRECNT_CTRL_8192F 0x04E5
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_EDCA_VO_PARAM_8192F 0x0500
|
||||
#define REG_EDCA_VI_PARAM_8192F 0x0504
|
||||
#define REG_EDCA_BE_PARAM_8192F 0x0508
|
||||
#define REG_EDCA_BK_PARAM_8192F 0x050C
|
||||
#define REG_BCNTCFG_8192F 0x0510
|
||||
#define REG_PIFS_8192F 0x0512
|
||||
#define REG_RDG_PIFS_8192F 0x0513
|
||||
#define REG_SIFS_CTX_8192F 0x0514
|
||||
#define REG_SIFS_TRX_8192F 0x0516
|
||||
#define REG_AGGR_BREAK_TIME_8192F 0x051A
|
||||
#define REG_SLOT_8192F 0x051B
|
||||
#define REG_TX_PTCL_CTRL_8192F 0x0520
|
||||
#define REG_TXPAUSE_8192F 0x0522
|
||||
#define REG_DIS_TXREQ_CLR_8192F 0x0523
|
||||
#define REG_RD_CTRL_8192F 0x0524
|
||||
/*
|
||||
* Format for offset 540h-542h:
|
||||
* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
|
||||
* [7:4]: Reserved.
|
||||
* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
|
||||
* [23:20]: Reserved
|
||||
* Description:
|
||||
* |
|
||||
* |<--Setup--|--Hold------------>|
|
||||
* --------------|----------------------
|
||||
* |
|
||||
* TBTT
|
||||
* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
|
||||
* Described by Designer Tim and Bruce, 2011-01-14.
|
||||
* */
|
||||
#define REG_TBTT_PROHIBIT_8192F 0x0540
|
||||
#define REG_RD_NAV_NXT_8192F 0x0544
|
||||
#define REG_NAV_PROT_LEN_8192F 0x0546
|
||||
#define REG_BCN_CTRL_8192F 0x0550
|
||||
#define REG_BCN_CTRL_1_8192F 0x0551
|
||||
#define REG_MBID_NUM_8192F 0x0552
|
||||
#define REG_DUAL_TSF_RST_8192F 0x0553
|
||||
#define REG_BCN_INTERVAL_8192F 0x0554
|
||||
#define REG_DRVERLYINT_8192F 0x0558
|
||||
#define REG_BCNDMATIM_8192F 0x0559
|
||||
#define REG_ATIMWND_8192F 0x055A
|
||||
#define REG_USTIME_TSF_8192F 0x055C
|
||||
#define REG_BCN_MAX_ERR_8192F 0x055D
|
||||
#define REG_RXTSF_OFFSET_CCK_8192F 0x055E
|
||||
#define REG_RXTSF_OFFSET_OFDM_8192F 0x055F
|
||||
#define REG_TSFTR_8192F 0x0560
|
||||
#define REG_CTWND_8192F 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8192F 0x0577
|
||||
#define REG_PSTIMER_8192F 0x0580
|
||||
#define REG_TIMER0_8192F 0x0584
|
||||
#define REG_TIMER1_8192F 0x0588
|
||||
#define REG_ACMHWCTRL_8192F 0x05C0
|
||||
#define REG_SCH_TXCMD_8192F 0x05F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_MAC_CR_8192F 0x0600
|
||||
#define REG_TCR_8192F 0x0604
|
||||
#define REG_RCR_8192F 0x0608
|
||||
#define REG_RX_PKT_LIMIT_8192F 0x060C
|
||||
#define REG_RX_DLK_TIME_8192F 0x060D
|
||||
#define REG_RX_DRVINFO_SZ_8192F 0x060F
|
||||
|
||||
#define REG_MACID_8192F 0x0610
|
||||
#define REG_BSSID_8192F 0x0618
|
||||
#define REG_MAR_8192F 0x0620
|
||||
#define REG_MBIDCAMCFG_8192F 0x0628
|
||||
|
||||
|
||||
#define REG_USTIME_EDCA_8192F 0x0638
|
||||
#define REG_MAC_SPEC_SIFS_8192F 0x063A
|
||||
#define REG_RESP_SIFP_CCK_8192F 0x063C
|
||||
#define REG_RESP_SIFS_OFDM_8192F 0x063E
|
||||
#define REG_ACKTO_8192F 0x0640
|
||||
#define REG_CTS2TO_8192F 0x0641
|
||||
#define REG_EIFS_8192F 0x0642
|
||||
|
||||
#define REG_NAV_UPPER_8192F 0x0652 /* unit of 128*/
|
||||
#define REG_TRXPTCL_CTL_8192F 0x0668
|
||||
|
||||
/* Security*/
|
||||
#define REG_CAMCMD_8192F 0x0670
|
||||
#define REG_CAMWRITE_8192F 0x0674
|
||||
#define REG_CAMREAD_8192F 0x0678
|
||||
#define REG_CAMDBG_8192F 0x067C
|
||||
#define REG_SECCFG_8192F 0x0680
|
||||
|
||||
/* Power */
|
||||
#define REG_WOW_CTRL_8192F 0x0690
|
||||
#define REG_PS_RX_INFO_8192F 0x0692
|
||||
#define REG_UAPSD_TID_8192F 0x0693
|
||||
#define REG_WKFMCAM_CMD_8192F 0x0698
|
||||
#define REG_WKFMCAM_NUM_8192F 0x0698
|
||||
#define REG_WKFMCAM_RWD_8192F 0x069C
|
||||
#define REG_RXFLTMAP0_8192F 0x06A0
|
||||
#define REG_RXFLTMAP1_8192F 0x06A2
|
||||
#define REG_RXFLTMAP2_8192F 0x06A4
|
||||
#define REG_BCN_PSR_RPT_8192F 0x06A8
|
||||
#define REG_BT_COEX_TABLE_8192F 0x06C0
|
||||
#define REG_BFMER0_INFO_8192F 0x06E4
|
||||
#define REG_BFMER1_INFO_8192F 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8192F 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8192F 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8192F 0x06FC
|
||||
|
||||
/* Hardware Port 2 */
|
||||
#define REG_MACID1_8192F 0x0700
|
||||
#define REG_BSSID1_8192F 0x0708
|
||||
#define REG_BFMEE_SEL_8192F 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8192F 0x0718
|
||||
|
||||
/* LTR */
|
||||
#define REG_LTR_CTRL_BASIC_8192F 0x07A4
|
||||
#define REG_LTR_IDLE_LATENCY_V1_8192F 0x0798
|
||||
#define REG_LTR_ACTIVE_LATENCY_V1_8192F 0x079C
|
||||
|
||||
/* GPIO Control */
|
||||
#define REG_SW_GPIO_SHARE_CTRL_8192F_0 0x1038
|
||||
#define REG_SW_GPIO_SHARE_CTRL_8192F_1 0x103c
|
||||
#define REG_SW_GPIO_A_OUT_8192F 0x1040
|
||||
#define REG_SW_GPIO_A_OEN_8192F 0x1044
|
||||
|
||||
/* ************************************************************
|
||||
* SDIO Bus Specification
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO CMD Address Mapping
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* I/O bus domain (Host)
|
||||
* ----------------------------------------------------- */
|
||||
/*SDIO Host Interrupt Mask Register */
|
||||
#define SDIO_HIMR_CRCERR_MSK BIT(31)
|
||||
/* SDIO Host Interrupt Service Routine */
|
||||
#define SDIO_HISR_HEISR_IND_INT BIT(28)
|
||||
#define SDIO_HISR_HSISR2_IND_INT BIT(29)
|
||||
#define SDIO_HISR_HSISR3_IND_INT BIT(30)
|
||||
#define SDIO_HISR_SDIO_CRCERR BIT(31)
|
||||
/* -----------------------------------------------------
|
||||
* SDIO register
|
||||
* ----------------------------------------------------- */
|
||||
#define SDIO_REG_HCPWM1_8192F 0x038/* HCI Current Power Mode 1 */
|
||||
#define SDIO_REG_FREE_TXPG1_8192F 0x0020 /* Free Tx Buffer Page1*/
|
||||
#define SDIO_REG_FREE_TXPG2_8192F 0x0024 /* Free Tx Buffer Page1*/
|
||||
#define SDIO_REG_FREE_TXPG3_8192F 0x0028
|
||||
#define SDIO_REG_AC_OQT_FREEPG_8192F 0x002A
|
||||
#define SDIO_REG_NOAC_OQT_FREEPG_8192F 0x002B
|
||||
/* ****************************************************************************
|
||||
* 8192F Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
#define BIT_USB_RXDMA_AGG_EN BIT(31)
|
||||
#define RXDMA_AGG_MODE_EN BIT(1)
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RXPKT_RELEASE_POLL BIT(16)
|
||||
#define RXDMA_IDLE BIT(17)
|
||||
#define RW_RELEASE_EN BIT(18)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AMPDU_PRETX_CD
|
||||
/*#define BIT_ERRORHDL_INT BIT(2)*/
|
||||
/*#define BIT_MACTX_ERR_3 BIT(4)*/
|
||||
#define BIT_PRE_TX_CMD_8192F BIT(6)
|
||||
#define BIT_EN_PRECNT_8192F BIT(11)
|
||||
#endif
|
||||
/* SDIO Host Interrupt Service Routine */
|
||||
#define SDIO_HISR_HEISR_IND_INT BIT(28)
|
||||
#define SDIO_HISR_HSISR2_IND_INT BIT(29)
|
||||
#define SDIO_HISR_HSISR3_IND_INT BIT(30)
|
||||
#define SDIO_HISR_SDIO_CRCERR BIT(31)
|
||||
|
||||
/* PCIE Host Interrupt Mask Register (HIMR) */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* ----------------------------------------------------------------------------
|
||||
* * 8192F IMR/ISR bits (offset 0xB0, 8bits)
|
||||
* * ---------------------------------------------------------------------------- */
|
||||
|
||||
#define IMR_DISABLED_8192F 0
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8192F BIT(31) /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8192F BIT(30) /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8192F BIT(29) /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8192F BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
|
||||
#define IMR_GTINT3_8192F BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8192F BIT(26) /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8192F BIT(25) /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8192F BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8192F BIT(20) /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8192F BIT(16) /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8192F BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8192F BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8192F BIT(12) /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8192F BIT(10) /* CPU to Host Command INT status, Write 1 clear */
|
||||
#define IMR_CPWM2_8192F BIT(9) /* CPU power mode exchange INT status, Write 1 clear */
|
||||
#define IMR_CPWM_8192F BIT(8) /* CPU power mode exchange INT status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8192F BIT(7) /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8192F BIT(6) /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8192F BIT(5) /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8192F BIT(4) /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8192F BIT(3) /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8192F BIT(2) /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8192F BIT(1) /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8192F BIT(0) /* Receive DMA OK */
|
||||
|
||||
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
||||
#define IMR_MCUERR_8192F BIT(28)
|
||||
#define IMR_BCNDMAINT7_8192F BIT(27) /* Beacon DMA Interrupt 7 */
|
||||
#define IMR_BCNDMAINT6_8192F BIT(26) /* Beacon DMA Interrupt 6 */
|
||||
#define IMR_BCNDMAINT5_8192F BIT(25) /* Beacon DMA Interrupt 5 */
|
||||
#define IMR_BCNDMAINT4_8192F BIT(24) /* Beacon DMA Interrupt 4 */
|
||||
#define IMR_BCNDMAINT3_8192F BIT(23) /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2_8192F BIT(22) /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1_8192F BIT(21) /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8192F BIT(20) /* Beacon Queue DMA OK Interrup 7 */
|
||||
#define IMR_BCNDOK6_8192F BIT(19) /* Beacon Queue DMA OK Interrup 6 */
|
||||
#define IMR_BCNDOK5_8192F BIT(18) /* Beacon Queue DMA OK Interrup 5 */
|
||||
#define IMR_BCNDOK4_8192F BIT(17) /* Beacon Queue DMA OK Interrup 4 */
|
||||
#define IMR_BCNDOK3_8192F BIT(16) /* Beacon Queue DMA OK Interrup 3 */
|
||||
#define IMR_BCNDOK2_8192F BIT(15) /* Beacon Queue DMA OK Interrup 2 */
|
||||
#define IMR_BCNDOK1_8192F BIT(14) /* Beacon Queue DMA OK Interrup 1 */
|
||||
#define IMR_ATIMEND_E_8192F BIT(13) /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8192F BIT(11) /* Tx Error Flag Interrupt status, write 1 clear. */
|
||||
#define IMR_RXERR_8192F BIT(10) /* Rx Error Flag INT status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8192F BIT(9) /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8192F BIT(8) /* Receive FIFO Overflow */
|
||||
|
||||
/* #define IMR_RX_MASK (IMR_ROK_8192F|IMR_RDU_8192F|IMR_RXFOVW_8192F) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_8192F | IMR_VIDOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F | IMR_MGNTDOK_8192F | IMR_HIGHDOK_8192F)
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8192F | IMR_TXBCN0OK_8192F | IMR_TXBCN0ERR_8192F | IMR_BCNDERR0_8192F)
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8192F | IMR_VODOK_8192F | IMR_BEDOK_8192F | IMR_BKDOK_8192F)
|
||||
#endif /* CONFIG_PCI_HCI */
|
||||
|
||||
/* 2 HSISR
|
||||
* interrupt mask which needs to clear */
|
||||
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
|
||||
HSISR_SPS_OCP_INT |\
|
||||
HSISR_RON_INT |\
|
||||
HSISR_PDNINT |\
|
||||
HSISR_GPIO9_INT)
|
||||
|
||||
#define _TXDMA_HIQ_MAP_8192F(x) (((x) & 0x7) << 19)
|
||||
#define _TXDMA_MGQ_MAP_8192F(x) (((x) & 0x7) << 16)
|
||||
#define _TXDMA_BKQ_MAP_8192F(x) (((x) & 0x7) << 13)
|
||||
#define _TXDMA_BEQ_MAP_8192F(x) (((x) & 0x7) << 10)
|
||||
#define _TXDMA_VIQ_MAP_8192F(x) (((x) & 0x7) << 7)
|
||||
#define _TXDMA_VOQ_MAP_8192F(x) (((x) & 0x7) << 4)
|
||||
|
||||
/*mac queue info*/
|
||||
#define QUEUE_TOTAL_NUM 20/*reg414h : 0~f ac queue 0x10~0x13MGQ HIQ BCNQ CMDQ*/
|
||||
#define QUEUE_ACQ_NUM 16
|
||||
#define QUEUE_INDEX_MGQ 0x10
|
||||
#define QUEUE_INDEX_HIQ 0x11
|
||||
#define QUEUE_INDEX_BCNQ 0x12
|
||||
#define QUEUE_INDEX_CMDQ 0x13
|
||||
#endif /* __RTL8192F_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8192F_SRESET_H_
|
||||
#define _RTL8192F_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8192f_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8192f_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif /* DBG_CONFIG_ERROR_DETECT */
|
||||
#endif /* _RTL8192F_SRESET_H_ */
|
||||
|
|
@ -0,0 +1,538 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8192F_XMIT_H__
|
||||
#define __RTL8192F_XMIT_H__
|
||||
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
|
||||
#ifndef __INC_HAL8192FDESC_H
|
||||
#define __INC_HAL8192FDESC_H
|
||||
|
||||
#define RX_STATUS_DESC_SIZE_8192F 24
|
||||
#define RX_DRV_INFO_SIZE_UNIT_8192F 8
|
||||
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICV_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FIT_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_CHKERR_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_IPVER_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP__8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
#define GET_RX_STATUS_DESC_FCS_OK_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
#endif
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_MATCH_ID_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_8192F(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8192F(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
|
||||
|
||||
/* Dword 0, rsvd: bit26, bit28 */
|
||||
#define GET_TX_DESC_OWN_8192F(__pTxDesc)\
|
||||
LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
|
||||
#define SET_TX_DESC_OFFSET_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
|
||||
#define SET_TX_DESC_BMC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
|
||||
#define SET_TX_DESC_HTC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
|
||||
#define SET_TX_DESC_AMSDU_PAD_EN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
|
||||
#define SET_TX_DESC_NO_ACM_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
|
||||
#define SET_TX_DESC_GF_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_DESC_MACID_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
|
||||
#define SET_TX_DESC_QUEUE_SEL_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
|
||||
#define SET_TX_DESC_PIFS_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
|
||||
#define SET_TX_DESC_RATE_ID_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
|
||||
#define SET_TX_DESC_SEC_TYPE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
|
||||
#define SET_TX_DESC_MORE_DATA_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
|
||||
|
||||
/* Dword 2 ADD HW_DIG*/
|
||||
#define SET_TX_DESC_PAID_92F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
|
||||
#define SET_TX_DESC_CCA_RTS_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
|
||||
#define SET_TX_DESC_AGG_ENABLE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RDG_ENABLE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
|
||||
#define SET_TX_DESC_NULL0_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
|
||||
#define SET_TX_DESC_NULL1_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
|
||||
#define SET_TX_DESC_BK_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MORE_FRAG_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
|
||||
#define SET_TX_DESC_RAW_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
|
||||
#define SET_TX_DESC_CCX_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
|
||||
#define SET_TX_DESC_BT_INT_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
|
||||
#define SET_TX_DESC_HW_DIG_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 7, __Value)
|
||||
|
||||
/* Dword 3 */
|
||||
#define SET_TX_DESC_HWSEQ_SEL_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
|
||||
#define SET_TX_DESC_USE_RATE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_FB_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
|
||||
#define SET_TX_DESC_CTS2SELF_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_ENABLE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
|
||||
#define SET_TX_DESC_CHK_EN_92F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 1, __Value)
|
||||
#define SET_TX_DESC_NAV_USE_HDR_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
|
||||
#define SET_TX_DESC_USE_MAX_LEN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
|
||||
#define SET_TX_DESC_NDPA_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
|
||||
#define SET_TX_DESC_TX_TRY_RATE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
|
||||
#define SET_TX_DESC_PCTS_EN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
|
||||
#define SET_TX_DESC_PCTS_MASK_IDX_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_DATA_SC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
|
||||
#define SET_TX_DESC_DATA_SHORT_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_BW_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_LDPC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_STBC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_STBC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_SHORT_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_SC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
|
||||
#define SET_TX_DESC_PORT_ID_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 21, 1, __Value)
|
||||
#define SET_TX_DESC_DROP_ID_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PATH_A_EN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
|
||||
#define SET_TX_DESC_PATH_B_EN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 25, 1, __Value)
|
||||
#define SET_TX_DESC_TXPWR_OF_SET_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
|
||||
#define SET_TX_DESC_MBSSID_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
|
||||
#define SET_TX_DESC_RF_SEL_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
|
||||
|
||||
/* Dword 7 */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define SET_TX_DESC_TX_DESC_CHECKSUM_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define SET_TX_DESC_TX_TIMESTAMP_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
|
||||
#endif
|
||||
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
|
||||
|
||||
/* Dword 8 */
|
||||
#define SET_TX_DESC_RTS_RC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
|
||||
#define SET_TX_DESC_BAR_RC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_RC_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_EN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
|
||||
#define SET_TX_DESC_NEXTHEADPAGE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
|
||||
#define SET_TX_DESC_TAILPAGE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_PADDING_LEN_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
|
||||
#define SET_TX_DESC_SEQ_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_8192F(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
|
||||
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN0_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN1_1_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
|
||||
#define SET_EARLYMODE_LEN1_2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
|
||||
#define SET_EARLYMODE_LEN2_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN3_8192F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RTL8192F TX BUFFER DESC */
|
||||
/*-----------------------------------------------------------------*/
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
|
||||
#else
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */
|
||||
#endif
|
||||
/* ********************************************************* */
|
||||
|
||||
/* 64 bits -- 32 bits */
|
||||
/* ======= ======= */
|
||||
/* Dword 0 0 */
|
||||
#define SET_TX_BUFF_DESC_LEN_0_8192F(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
|
||||
#define SET_TX_BUFF_DESC_PSB_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
|
||||
#define SET_TX_BUFF_DESC_OWN_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
|
||||
/* Dword 1 1 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
|
||||
#define GET_TX_BUFF_DESC_ADDR_LOW_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
|
||||
/* Dword 2 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
|
||||
#else
|
||||
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8192F(__pTxDesc) 0
|
||||
#endif
|
||||
/* Dword 3 NA */
|
||||
/* RESERVED 0 */
|
||||
/* Dword 4 2 */
|
||||
#define SET_TX_BUFF_DESC_LEN_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 5 3 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 6 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 7 NA */
|
||||
/*RESERVED 0 */
|
||||
/* Dword 8 4 */
|
||||
#define SET_TX_BUFF_DESC_LEN_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 9 5 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 10 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 11 NA */
|
||||
/*RESERVED 0 */
|
||||
/* Dword 12 6 */
|
||||
#define SET_TX_BUFF_DESC_LEN_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 13 7 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 14 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8192F(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 15 NA */
|
||||
/*RESERVED 0 */
|
||||
|
||||
|
||||
#endif
|
||||
/* -----------------------------------------------------------
|
||||
*
|
||||
* Rate
|
||||
*
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC8192F_RATE1M 0x00
|
||||
#define DESC8192F_RATE2M 0x01
|
||||
#define DESC8192F_RATE5_5M 0x02
|
||||
#define DESC8192F_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC8192F_RATE6M 0x04
|
||||
#define DESC8192F_RATE9M 0x05
|
||||
#define DESC8192F_RATE12M 0x06
|
||||
#define DESC8192F_RATE18M 0x07
|
||||
#define DESC8192F_RATE24M 0x08
|
||||
#define DESC8192F_RATE36M 0x09
|
||||
#define DESC8192F_RATE48M 0x0a
|
||||
#define DESC8192F_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC8192F_RATEMCS0 0x0c
|
||||
#define DESC8192F_RATEMCS1 0x0d
|
||||
#define DESC8192F_RATEMCS2 0x0e
|
||||
#define DESC8192F_RATEMCS3 0x0f
|
||||
#define DESC8192F_RATEMCS4 0x10
|
||||
#define DESC8192F_RATEMCS5 0x11
|
||||
#define DESC8192F_RATEMCS6 0x12
|
||||
#define DESC8192F_RATEMCS7 0x13
|
||||
#define DESC8192F_RATEMCS8 0x14
|
||||
#define DESC8192F_RATEMCS9 0x15
|
||||
#define DESC8192F_RATEMCS10 0x16
|
||||
#define DESC8192F_RATEMCS11 0x17
|
||||
#define DESC8192F_RATEMCS12 0x18
|
||||
#define DESC8192F_RATEMCS13 0x19
|
||||
#define DESC8192F_RATEMCS14 0x1a
|
||||
#define DESC8192F_RATEMCS15 0x1b
|
||||
#define DESC8192F_RATEVHTSS1MCS0 0x2c
|
||||
#define DESC8192F_RATEVHTSS1MCS1 0x2d
|
||||
#define DESC8192F_RATEVHTSS1MCS2 0x2e
|
||||
#define DESC8192F_RATEVHTSS1MCS3 0x2f
|
||||
#define DESC8192F_RATEVHTSS1MCS4 0x30
|
||||
#define DESC8192F_RATEVHTSS1MCS5 0x31
|
||||
#define DESC8192F_RATEVHTSS1MCS6 0x32
|
||||
#define DESC8192F_RATEVHTSS1MCS7 0x33
|
||||
#define DESC8192F_RATEVHTSS1MCS8 0x34
|
||||
#define DESC8192F_RATEVHTSS1MCS9 0x35
|
||||
#define DESC8192F_RATEVHTSS2MCS0 0x36
|
||||
#define DESC8192F_RATEVHTSS2MCS1 0x37
|
||||
#define DESC8192F_RATEVHTSS2MCS2 0x38
|
||||
#define DESC8192F_RATEVHTSS2MCS3 0x39
|
||||
#define DESC8192F_RATEVHTSS2MCS4 0x3a
|
||||
#define DESC8192F_RATEVHTSS2MCS5 0x3b
|
||||
#define DESC8192F_RATEVHTSS2MCS6 0x3c
|
||||
#define DESC8192F_RATEVHTSS2MCS7 0x3d
|
||||
#define DESC8192F_RATEVHTSS2MCS8 0x3e
|
||||
#define DESC8192F_RATEVHTSS2MCS9 0x3f
|
||||
|
||||
|
||||
#define RX_HAL_IS_CCK_RATE_8192F(pDesc)\
|
||||
(GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE1M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE2M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE5_5M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8192F(pDesc) == DESC8192F_RATE11M)
|
||||
|
||||
#ifdef CONFIG_TRX_BD_ARCH
|
||||
struct tx_desc;
|
||||
#endif
|
||||
|
||||
void rtl8192f_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
void rtl8192f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
|
||||
void rtl8192f_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8192f_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8192f_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8192f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8192fs_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8192fs_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8192fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8192fs_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8192fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192fs_xmit_buf_handler(PADAPTER padapter);
|
||||
thread_return rtl8192fs_xmit_thread(thread_context context);
|
||||
#define hal_xmit_handler rtl8192fs_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8192fu_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8192fu_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8192fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8192fu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8192fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192fu_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8192fu_xmit_buf_handler
|
||||
void rtl8192fu_xmit_tasklet(void *priv);
|
||||
s32 rtl8192fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8192fe_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8192fe_free_xmit_priv(PADAPTER padapter);
|
||||
struct xmit_buf *rtl8192fe_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
void rtl8192fe_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8192fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8192fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8192fe_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8192fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8192fe_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
u8 BWMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
u8 SCMapping_8192F(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_CMD_H__
|
||||
#define __RTL8703B_CMD_H__
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
enum h2c_cmd_8703B {
|
||||
/* Common Class: 000 */
|
||||
H2C_8703B_RSVD_PAGE = 0x00,
|
||||
H2C_8703B_MEDIA_STATUS_RPT = 0x01,
|
||||
H2C_8703B_SCAN_ENABLE = 0x02,
|
||||
H2C_8703B_KEEP_ALIVE = 0x03,
|
||||
H2C_8703B_DISCON_DECISION = 0x04,
|
||||
H2C_8703B_PSD_OFFLOAD = 0x05,
|
||||
H2C_8703B_AP_OFFLOAD = 0x08,
|
||||
H2C_8703B_BCN_RSVDPAGE = 0x09,
|
||||
H2C_8703B_PROBERSP_RSVDPAGE = 0x0A,
|
||||
H2C_8703B_FCS_RSVDPAGE = 0x10,
|
||||
H2C_8703B_FCS_INFO = 0x11,
|
||||
H2C_8703B_AP_WOW_GPIO_CTRL = 0x13,
|
||||
|
||||
/* PoweSave Class: 001 */
|
||||
H2C_8703B_SET_PWR_MODE = 0x20,
|
||||
H2C_8703B_PS_TUNING_PARA = 0x21,
|
||||
H2C_8703B_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8703B_P2P_LPS_PARAM = 0x23,
|
||||
H2C_8703B_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8703B_PS_SCAN_ENABLE = 0x25,
|
||||
H2C_8703B_SAP_PS_ = 0x26,
|
||||
H2C_8703B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
|
||||
H2C_8703B_FWLPS_IN_IPS_ = 0x28,
|
||||
|
||||
/* Dynamic Mechanism Class: 010 */
|
||||
H2C_8703B_MACID_CFG = 0x40,
|
||||
H2C_8703B_TXBF = 0x41,
|
||||
H2C_8703B_RSSI_SETTING = 0x42,
|
||||
H2C_8703B_AP_REQ_TXRPT = 0x43,
|
||||
H2C_8703B_INIT_RATE_COLLECT = 0x44,
|
||||
H2C_8703B_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
/* BT Class: 011 */
|
||||
H2C_8703B_B_TYPE_TDMA = 0x60,
|
||||
H2C_8703B_BT_INFO = 0x61,
|
||||
H2C_8703B_FORCE_BT_TXPWR = 0x62,
|
||||
H2C_8703B_BT_IGNORE_WLANACT = 0x63,
|
||||
H2C_8703B_DAC_SWING_VALUE = 0x64,
|
||||
H2C_8703B_ANT_SEL_RSV = 0x65,
|
||||
H2C_8703B_WL_OPMODE = 0x66,
|
||||
H2C_8703B_BT_MP_OPER = 0x67,
|
||||
H2C_8703B_BT_CONTROL = 0x68,
|
||||
H2C_8703B_BT_WIFI_CTRL = 0x69,
|
||||
H2C_8703B_BT_FW_PATCH = 0x6A,
|
||||
H2C_8703B_BT_WLAN_CALIBRATION = 0x6D,
|
||||
|
||||
/* WOWLAN Class: 100 */
|
||||
H2C_8703B_WOWLAN = 0x80,
|
||||
H2C_8703B_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8703B_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8703B_AOAC_RSVD_PAGE = 0x83,
|
||||
H2C_8703B_AOAC_RSVD_PAGE2 = 0x84,
|
||||
H2C_8703B_D0_SCAN_OFFLOAD_CTRL = 0x85,
|
||||
H2C_8703B_D0_SCAN_OFFLOAD_INFO = 0x86,
|
||||
H2C_8703B_CHNL_SWITCH_OFFLOAD = 0x87,
|
||||
H2C_8703B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
|
||||
H2C_8703B_P2P_OFFLOAD = 0x8B,
|
||||
|
||||
H2C_8703B_RESET_TSF = 0xC0,
|
||||
H2C_8703B_MAXID,
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
|
||||
* ---------------------------------------------------------------------------------------------------------
|
||||
* _RSVDPAGE_LOC_CMD_0x00 */
|
||||
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/* _KEEP_ALIVE_CMD_0x03 */
|
||||
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _DISCONNECT_DECISION_CMD_0x04 */
|
||||
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
|
||||
/* _PWR_MOD_CMD_0x20 */
|
||||
#define SET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8703B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_8703B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _PS_TUNE_PARAM_CMD_0x21 */
|
||||
#define SET_8703B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
|
||||
#define SET_8703B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _MACID_CFG_CMD_0x40 */
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
|
||||
|
||||
/* _RSSI_SETTING_CMD_0x42 */
|
||||
#define SET_8703B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
|
||||
#define SET_8703B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _AP_REQ_TXRPT_CMD_0x43 */
|
||||
#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_TXPWR_CMD_0x62 */
|
||||
#define SET_8703B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_MP_OPER_CMD_0x67 */
|
||||
#define SET_8703B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
|
||||
/* _BT_FW_PATCH_0x6A */
|
||||
#define SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ------------------------------------------- Structure --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- Function Statement --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/* host message to firmware cmd */
|
||||
void rtl8703b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8703b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
|
||||
void rtl8703b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
|
||||
/* s32 rtl8703b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
|
||||
void rtl8703b_set_FwPsTuneParam_cmd(PADAPTER padapter);
|
||||
void rtl8703b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
|
||||
void rtl8703b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8703b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8703b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
void rtl8703b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8703b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
|
||||
|
||||
s32 FillH2CCmd8703B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
u8 GetTxBufferRsvdPageNum8703B(_adapter *padapter, bool wowlan);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_DM_H__
|
||||
#define __RTL8703B_DM_H__
|
||||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for 8703B dynamic mechanism only
|
||||
*
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* structure and define
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* function prototype
|
||||
* ************************************************************ */
|
||||
|
||||
void rtl8703b_init_dm_priv(PADAPTER padapter);
|
||||
void rtl8703b_deinit_dm_priv(PADAPTER padapter);
|
||||
|
||||
void rtl8703b_InitHalDm(PADAPTER padapter);
|
||||
void rtl8703b_HalDmWatchDog(PADAPTER padapter);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,266 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_HAL_H__
|
||||
#define __RTL8703B_HAL_H__
|
||||
|
||||
#include "hal_data.h"
|
||||
|
||||
#include "rtl8703b_spec.h"
|
||||
#include "rtl8703b_rf.h"
|
||||
#include "rtl8703b_dm.h"
|
||||
#include "rtl8703b_recv.h"
|
||||
#include "rtl8703b_xmit.h"
|
||||
#include "rtl8703b_cmd.h"
|
||||
#include "rtl8703b_led.h"
|
||||
#include "Hal8703BPwrSeq.h"
|
||||
#include "Hal8703BPhyReg.h"
|
||||
#include "Hal8703BPhyCfg.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8703b_sreset.h"
|
||||
#endif
|
||||
|
||||
#define FW_8703B_SIZE 0x8000
|
||||
#define FW_8703B_START_ADDRESS 0x1000
|
||||
#define FW_8703B_END_ADDRESS 0x1FFF /* 0x5FFF */
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8703B(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x03B0)
|
||||
|
||||
typedef struct _RT_FIRMWARE {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_8703B_SIZE];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8703B, *PRT_FIRMWARE_8703B;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
typedef struct _RT_8703B_FIRMWARE_HDR {
|
||||
/* 8-byte alinment required */
|
||||
|
||||
/* --- LONG WORD 0 ---- */
|
||||
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
u8 Category; /* AP/NIC and USB/PCI */
|
||||
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
u16 Version; /* FW Version */
|
||||
u16 Subversion; /* FW Subversion, default 0x00 */
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
u8 Month; /* Release time Month field */
|
||||
u8 Date; /* Release time Date field */
|
||||
u8 Hour; /* Release time Hour field */
|
||||
u8 Minute; /* Release time Minute field */
|
||||
u16 RamCodeSize; /* The size of RAM code */
|
||||
u16 Rsvd2;
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
u32 SvnIdx; /* The SVN entry index */
|
||||
u32 Rsvd3;
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
} RT_8703B_FIRMWARE_HDR, *PRT_8703B_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8703B 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8703B 0x02
|
||||
|
||||
/* for 8703B
|
||||
* TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
|
||||
#define PAGE_SIZE_TX_8703B 128
|
||||
#define PAGE_SIZE_RX_8703B 8
|
||||
|
||||
#define TX_DMA_SIZE_8703B 0x8000 /* 32K(TX) */
|
||||
#define RX_DMA_SIZE_8703B 0x4000 /* 16K(RX) */
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8703B 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8703B 0x80 /* 128B, reserved for tx report */
|
||||
#endif
|
||||
#define RX_DMA_BOUNDARY_8703B (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B - 1)
|
||||
|
||||
|
||||
/* Note: We will divide number of page equally for each queue other than public queue! */
|
||||
|
||||
/* For General Reserved Page Number(Beacon Queue is reserved page)
|
||||
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8703B
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
|
||||
|
||||
#define BCNQ_PAGE_NUM_8703B (MAX_BEACON_LEN/PAGE_SIZE_TX_8703B + 6) /*0x08*/
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1 PNO: 6
|
||||
* NS offload: 2NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8703B 0x0b
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8703B 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#undef WOWLAN_PAGE_NUM_8703B
|
||||
#define WOWLAN_PAGE_NUM_8703B 0x15
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_WOWLAN
|
||||
#define AP_WOWLAN_PAGE_NUM_8703B 0x02
|
||||
#endif
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER_8703B (0xFF - BCNQ_PAGE_NUM_8703B - WOWLAN_PAGE_NUM_8703B)
|
||||
#define TX_PAGE_BOUNDARY_8703B (TX_TOTAL_PAGE_NUMBER_8703B + 1)
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B TX_TOTAL_PAGE_NUMBER_8703B
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8703B (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8703B + 1)
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8703B */
|
||||
#define NORMAL_PAGE_NUM_HPQ_8703B 0x0C
|
||||
#define NORMAL_PAGE_NUM_LPQ_8703B 0x02
|
||||
#define NORMAL_PAGE_NUM_NPQ_8703B 0x02
|
||||
|
||||
/* Note: For Normal Chip Setting, modify later */
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8703B 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8703B 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8703B 0x20
|
||||
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
#define EFUSE_OOB_PROTECT_BYTES 15
|
||||
|
||||
#define HAL_EFUSE_MEMORY
|
||||
|
||||
#define HWSET_MAX_SIZE_8703B 256
|
||||
#define EFUSE_REAL_CONTENT_LEN_8703B 256
|
||||
#define EFUSE_MAP_LEN_8703B 512
|
||||
#define EFUSE_MAX_SECTION_8703B 64
|
||||
|
||||
#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8703B)
|
||||
|
||||
#define EFUSE_ACCESS_ON 0x69
|
||||
#define EFUSE_ACCESS_OFF 0x00
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define BANK_NUM 1
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
|
||||
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8)
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
typedef enum tag_Package_Definition {
|
||||
PACKAGE_DEFAULT,
|
||||
PACKAGE_QFN68,
|
||||
PACKAGE_TFBGA90,
|
||||
PACKAGE_TFBGA80,
|
||||
PACKAGE_TFBGA79
|
||||
} PACKAGE_TYPE_E;
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
/* rtl8703b_hal_init.c */
|
||||
s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
|
||||
void rtl8703b_FirmwareSelfReset(PADAPTER padapter);
|
||||
void rtl8703b_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
void rtl8703b_InitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8703b_CheckAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8703b_init_default_value(PADAPTER padapter);
|
||||
|
||||
s32 rtl8703b_InitLLTTable(PADAPTER padapter);
|
||||
|
||||
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
|
||||
s32 CardDisableWithoutHWSM(PADAPTER padapter);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8703B(PADAPTER padapter);
|
||||
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseAntennaDiversity_8703B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8703B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBoardType_8703B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
|
||||
void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8703b(_adapter *adapter);
|
||||
u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val);
|
||||
u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
|
||||
/* register */
|
||||
void rtl8703b_InitBeaconParameters(PADAPTER padapter);
|
||||
void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
|
||||
void _InitBurstPktLen_8703BS(PADAPTER Adapter);
|
||||
void _InitLTECoex_8703BS(PADAPTER Adapter);
|
||||
void _InitMacAPLLSetting_8703B(PADAPTER Adapter);
|
||||
void _8051Reset8703(PADAPTER padapter);
|
||||
#ifdef CONFIG_WOWLAN
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
void rtl8703b_start_thread(_adapter *padapter);
|
||||
void rtl8703b_stop_thread(_adapter *padapter);
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void rtl8703bs_init_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8703bs_free_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8703bs_hal_check_bt_hang(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
|
||||
#endif
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
|
||||
#endif
|
||||
void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len);
|
||||
|
||||
u8 MRateToHwRate8703B(u8 rate);
|
||||
u8 HwRateToMRate8703B(u8 rate);
|
||||
|
||||
void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
BOOLEAN InterruptRecognized8703BE(PADAPTER Adapter);
|
||||
void UpdateInterruptMask8703BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_LED_H__
|
||||
#define __RTL8703B_LED_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8703bu_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8703bu_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8703bs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_GSPI_HCI
|
||||
void rtl8703bs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8703bs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8703be_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8703be_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif/*CONFIG_RTW_SW_LED*/
|
||||
#endif /*__RTL8703B_LED_H__*/
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_RECV_H__
|
||||
#define __RTL8703B_RECV_H__
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
#ifdef CONFIG_PLATFORM_MSTAR
|
||||
#define MAX_RECVBUF_SZ (8192) /* 8K */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
|
||||
#endif
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
|
||||
/* #define MAX_RECVBUF_SZ (9100) */
|
||||
/* #else */
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K
|
||||
* #endif */
|
||||
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
|
||||
|
||||
#endif
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#ifndef CONFIG_SDIO_RX_COPY
|
||||
#undef MAX_RECVBUF_SZ
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8703B - RX_DMA_RESERVED_SIZE_8703B)
|
||||
#endif /* !CONFIG_SDIO_RX_COPY */
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8703bs_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8703bs_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
int rtl8703bu_init_recv_priv(_adapter *padapter);
|
||||
void rtl8703bu_free_recv_priv(_adapter *padapter);
|
||||
void rtl8703bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8703be_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8703be_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8703b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8703B_RECV_H__ */
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_RF_H__
|
||||
#define __RTL8703B_RF_H__
|
||||
|
||||
int PHY_RF6052_Config8703B(PADAPTER Adapter);
|
||||
|
||||
void
|
||||
PHY_RF6052SetBandwidth8703B(
|
||||
PADAPTER Adapter,
|
||||
enum channel_width Bandwidth);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,464 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_SPEC_H__
|
||||
#define __RTL8703B_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
|
||||
#define HAL_NAV_UPPER_UNIT_8703B 128 /* micro-second */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SYS_ISO_CTRL_8703B 0x0000 /* 2 Byte */
|
||||
#define REG_SYS_FUNC_EN_8703B 0x0002 /* 2 Byte */
|
||||
#define REG_APS_FSMCO_8703B 0x0004 /* 4 Byte */
|
||||
#define REG_SYS_CLKR_8703B 0x0008 /* 2 Byte */
|
||||
#define REG_9346CR_8703B 0x000A /* 2 Byte */
|
||||
#define REG_EE_VPD_8703B 0x000C /* 2 Byte */
|
||||
#define REG_AFE_MISC_8703B 0x0010 /* 1 Byte */
|
||||
#define REG_SPS0_CTRL_8703B 0x0011 /* 7 Byte */
|
||||
#define REG_SPS_OCP_CFG_8703B 0x0018 /* 4 Byte */
|
||||
#define REG_RSV_CTRL_8703B 0x001C /* 3 Byte */
|
||||
#define REG_RF_CTRL_8703B 0x001F /* 1 Byte */
|
||||
#define REG_LPLDO_CTRL_8703B 0x0023 /* 1 Byte */
|
||||
#define REG_AFE_XTAL_CTRL_8703B 0x0024 /* 4 Byte */
|
||||
#define REG_AFE_PLL_CTRL_8703B 0x0028 /* 4 Byte */
|
||||
#define REG_MAC_PLL_CTRL_EXT_8703B 0x002c /* 4 Byte */
|
||||
#define REG_EFUSE_CTRL_8703B 0x0030
|
||||
#define REG_EFUSE_TEST_8703B 0x0034
|
||||
#define REG_PWR_DATA_8703B 0x0038
|
||||
#define REG_CAL_TIMER_8703B 0x003C
|
||||
#define REG_ACLK_MON_8703B 0x003E
|
||||
#define REG_GPIO_MUXCFG_8703B 0x0040
|
||||
#define REG_GPIO_IO_SEL_8703B 0x0042
|
||||
#define REG_MAC_PINMUX_CFG_8703B 0x0043
|
||||
#define REG_GPIO_PIN_CTRL_8703B 0x0044
|
||||
#define REG_GPIO_INTM_8703B 0x0048
|
||||
#define REG_LEDCFG0_8703B 0x004C
|
||||
#define REG_LEDCFG1_8703B 0x004D
|
||||
#define REG_LEDCFG2_8703B 0x004E
|
||||
#define REG_LEDCFG3_8703B 0x004F
|
||||
#define REG_FSIMR_8703B 0x0050
|
||||
#define REG_FSISR_8703B 0x0054
|
||||
#define REG_HSIMR_8703B 0x0058
|
||||
#define REG_HSISR_8703B 0x005c
|
||||
#define REG_GPIO_EXT_CTRL 0x0060
|
||||
#define REG_PAD_CTRL1_8703B 0x0064
|
||||
#define REG_MULTI_FUNC_CTRL_8703B 0x0068
|
||||
#define REG_GPIO_STATUS_8703B 0x006C
|
||||
#define REG_SDIO_CTRL_8703B 0x0070
|
||||
#define REG_OPT_CTRL_8703B 0x0074
|
||||
#define REG_AFE_CTRL_4_8703B 0x0078
|
||||
#define REG_MCUFWDL_8703B 0x0080
|
||||
#define REG_HMEBOX_DBG_0_8703B 0x0088
|
||||
#define REG_HMEBOX_DBG_1_8703B 0x008A
|
||||
#define REG_HMEBOX_DBG_2_8703B 0x008C
|
||||
#define REG_HMEBOX_DBG_3_8703B 0x008E
|
||||
#define REG_HIMR0_8703B 0x00B0
|
||||
#define REG_HISR0_8703B 0x00B4
|
||||
#define REG_HIMR1_8703B 0x00B8
|
||||
#define REG_HISR1_8703B 0x00BC
|
||||
#define REG_PMC_DBG_CTRL2_8703B 0x00CC
|
||||
#define REG_EFUSE_BURN_GNT_8703B 0x00CF
|
||||
#define REG_HPON_FSM_8703B 0x00EC
|
||||
#define REG_SYS_CFG_8703B 0x00F0
|
||||
#define REG_SYS_CFG1_8703B 0x00FC
|
||||
#define REG_ROM_VERSION 0x00FD
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_C2HEVT_CMD_ID_8703B 0x01A0
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
|
||||
#define REG_C2HEVT_CMD_LEN_8703B 0x01AE
|
||||
#define REG_C2HEVT_CMD_LEN_88XX REG_C2HEVT_CMD_LEN_8703B
|
||||
#define REG_C2HEVT_CLEAR_8703B 0x01AF
|
||||
#define REG_MCUTST_1_8703B 0x01C0
|
||||
#define REG_WOWLAN_WAKE_REASON 0x01C7
|
||||
#define REG_FMETHR_8703B 0x01C8
|
||||
#define REG_HMETFR_8703B 0x01CC
|
||||
#define REG_HMEBOX_0_8703B 0x01D0
|
||||
#define REG_HMEBOX_1_8703B 0x01D4
|
||||
#define REG_HMEBOX_2_8703B 0x01D8
|
||||
#define REG_HMEBOX_3_8703B 0x01DC
|
||||
#define REG_LLT_INIT_8703B 0x01E0
|
||||
#define REG_HMEBOX_EXT0_8703B 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8703B 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8703B 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8703B 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RQPN_8703B 0x0200
|
||||
#define REG_FIFOPAGE_8703B 0x0204
|
||||
#define REG_DWBCN0_CTRL_8703B REG_TDECTRL
|
||||
#define REG_TXDMA_OFFSET_CHK_8703B 0x020C
|
||||
#define REG_TXDMA_STATUS_8703B 0x0210
|
||||
#define REG_RQPN_NPQ_8703B 0x0214
|
||||
#define REG_DWBCN1_CTRL_8703B 0x0228
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RXDMA_AGG_PG_TH_8703B 0x0280
|
||||
#define REG_FW_UPD_RDPTR_8703B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
|
||||
#define REG_RXDMA_CONTROL_8703B 0x0286 /* Control the RX DMA. */
|
||||
#define REG_RXPKT_NUM_8703B 0x0287 /* The number of packets in RXPKTBUF. */
|
||||
#define REG_RXDMA_STATUS_8703B 0x0288
|
||||
#define REG_RXDMA_MODE_CTRL_8703B 0x0290
|
||||
#define REG_EARLY_MODE_CONTROL_8703B 0x02BC
|
||||
#define REG_RSVD5_8703B 0x02F0
|
||||
#define REG_RSVD6_8703B 0x02F4
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8703B 0x0300
|
||||
#define REG_INT_MIG_8703B 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_DESA_8703B 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_HQ_DESA_8703B 0x0310 /* TX High Queue Descriptor Address */
|
||||
#define REG_MGQ_DESA_8703B 0x0318 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_DESA_8703B 0x0320 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_DESA_8703B 0x0328 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_DESA_8703B 0x0330 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_DESA_8703B 0x0338 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RX_DESA_8703B 0x0340 /* RX Queue Descriptor Address */
|
||||
#define REG_DBI_WDATA_8703B 0x0348 /* DBI Write Data */
|
||||
#define REG_DBI_RDATA_8703B 0x034C /* DBI Read Data */
|
||||
#define REG_DBI_ADDR_8703B 0x0350 /* DBI Address */
|
||||
#define REG_DBI_FLAG_8703B 0x0352 /* DBI Read/Write Flag */
|
||||
#define REG_MDIO_WDATA_8703B 0x0354 /* MDIO for Write PCIE PHY */
|
||||
#define REG_MDIO_RDATA_8703B 0x0356 /* MDIO for Reads PCIE PHY */
|
||||
#define REG_MDIO_CTL_8703B 0x0358 /* MDIO for Control */
|
||||
#define REG_DBG_SEL_8703B 0x0360 /* Debug Selection Register */
|
||||
#define REG_PCIE_HRPWM_8703B 0x0361 /* PCIe RPWM */
|
||||
#define REG_PCIE_HCPWM_8703B 0x0363 /* PCIe CPWM */
|
||||
#define REG_PCIE_MULTIFET_CTRL_8703B 0x036A /* PCIE Multi-Fethc Control */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_VOQ_INFORMATION_8703B 0x0400
|
||||
#define REG_VIQ_INFORMATION_8703B 0x0404
|
||||
#define REG_BEQ_INFORMATION_8703B 0x0408
|
||||
#define REG_BKQ_INFORMATION_8703B 0x040C
|
||||
#define REG_MGQ_INFORMATION_8703B 0x0410
|
||||
#define REG_HGQ_INFORMATION_8703B 0x0414
|
||||
#define REG_BCNQ_INFORMATION_8703B 0x0418
|
||||
#define REG_TXPKT_EMPTY_8703B 0x041A
|
||||
|
||||
#define REG_FWHW_TXQ_CTRL_8703B 0x0420
|
||||
#define REG_HWSEQ_CTRL_8703B 0x0423
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY_8703B 0x0424
|
||||
#define REG_TXPKTBUF_MGQ_BDNY_8703B 0x0425
|
||||
#define REG_LIFECTRL_CTRL_8703B 0x0426
|
||||
#define REG_MULTI_BCNQ_OFFSET_8703B 0x0427
|
||||
#define REG_SPEC_SIFS_8703B 0x0428
|
||||
#define REG_RL_8703B 0x042A
|
||||
#define REG_TXBF_CTRL_8703B 0x042C
|
||||
#define REG_DARFRC_8703B 0x0430
|
||||
#define REG_RARFRC_8703B 0x0438
|
||||
#define REG_RRSR_8703B 0x0440
|
||||
#define REG_ARFR0_8703B 0x0444
|
||||
#define REG_ARFR1_8703B 0x044C
|
||||
#define REG_CCK_CHECK_8703B 0x0454
|
||||
#define REG_AMPDU_MAX_TIME_8703B 0x0456
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY1_8703B 0x0457
|
||||
|
||||
#define REG_AMPDU_MAX_LENGTH_8703B 0x0458
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8703B 0x045F
|
||||
#define REG_FAST_EDCA_CTRL_8703B 0x0460
|
||||
#define REG_RD_RESP_PKT_TH_8703B 0x0463
|
||||
#define REG_DATA_SC_8703B 0x0483
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x0484
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x0488
|
||||
#endif
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_POWER_STAGE1_8703B 0x04B4
|
||||
#define REG_POWER_STAGE2_8703B 0x04B8
|
||||
#define REG_AMPDU_BURST_MODE_8703B 0x04BC
|
||||
#define REG_PKT_VO_VI_LIFE_TIME_8703B 0x04C0
|
||||
#define REG_PKT_BE_BK_LIFE_TIME_8703B 0x04C2
|
||||
#define REG_STBC_SETTING_8703B 0x04C4
|
||||
#define REG_HT_SINGLE_AMPDU_8703B 0x04C7
|
||||
#define REG_PROT_MODE_CTRL_8703B 0x04C8
|
||||
#define REG_MAX_AGGR_NUM_8703B 0x04CA
|
||||
#define REG_RTS_MAX_AGGR_NUM_8703B 0x04CB
|
||||
#define REG_BAR_MODE_CTRL_8703B 0x04CC
|
||||
#define REG_RA_TRY_RATE_AGG_LMT_8703B 0x04CF
|
||||
#define REG_MACID_PKT_DROP0_8703B 0x04D0
|
||||
#define REG_MACID_PKT_SLEEP_8703B 0x04D4
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_EDCA_VO_PARAM_8703B 0x0500
|
||||
#define REG_EDCA_VI_PARAM_8703B 0x0504
|
||||
#define REG_EDCA_BE_PARAM_8703B 0x0508
|
||||
#define REG_EDCA_BK_PARAM_8703B 0x050C
|
||||
#define REG_BCNTCFG_8703B 0x0510
|
||||
#define REG_PIFS_8703B 0x0512
|
||||
#define REG_RDG_PIFS_8703B 0x0513
|
||||
#define REG_SIFS_CTX_8703B 0x0514
|
||||
#define REG_SIFS_TRX_8703B 0x0516
|
||||
#define REG_AGGR_BREAK_TIME_8703B 0x051A
|
||||
#define REG_SLOT_8703B 0x051B
|
||||
#define REG_TX_PTCL_CTRL_8703B 0x0520
|
||||
#define REG_TXPAUSE_8703B 0x0522
|
||||
#define REG_DIS_TXREQ_CLR_8703B 0x0523
|
||||
#define REG_RD_CTRL_8703B 0x0524
|
||||
/*
|
||||
* Format for offset 540h-542h:
|
||||
* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
|
||||
* [7:4]: Reserved.
|
||||
* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
|
||||
* [23:20]: Reserved
|
||||
* Description:
|
||||
* |
|
||||
* |<--Setup--|--Hold------------>|
|
||||
* --------------|----------------------
|
||||
* |
|
||||
* TBTT
|
||||
* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
|
||||
* Described by Designer Tim and Bruce, 2011-01-14.
|
||||
* */
|
||||
#define REG_TBTT_PROHIBIT_8703B 0x0540
|
||||
#define REG_RD_NAV_NXT_8703B 0x0544
|
||||
#define REG_NAV_PROT_LEN_8703B 0x0546
|
||||
#define REG_BCN_CTRL_8703B 0x0550
|
||||
#define REG_BCN_CTRL_1_8703B 0x0551
|
||||
#define REG_MBID_NUM_8703B 0x0552
|
||||
#define REG_DUAL_TSF_RST_8703B 0x0553
|
||||
#define REG_BCN_INTERVAL_8703B 0x0554
|
||||
#define REG_DRVERLYINT_8703B 0x0558
|
||||
#define REG_BCNDMATIM_8703B 0x0559
|
||||
#define REG_ATIMWND_8703B 0x055A
|
||||
#define REG_USTIME_TSF_8703B 0x055C
|
||||
#define REG_BCN_MAX_ERR_8703B 0x055D
|
||||
#define REG_RXTSF_OFFSET_CCK_8703B 0x055E
|
||||
#define REG_RXTSF_OFFSET_OFDM_8703B 0x055F
|
||||
#define REG_TSFTR_8703B 0x0560
|
||||
#define REG_CTWND_8703B 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8703B 0x0577
|
||||
#define REG_PSTIMER_8703B 0x0580
|
||||
#define REG_TIMER0_8703B 0x0584
|
||||
#define REG_TIMER1_8703B 0x0588
|
||||
#define REG_ACMHWCTRL_8703B 0x05C0
|
||||
#define REG_SCH_TXCMD_8703B 0x05F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_MAC_CR_8703B 0x0600
|
||||
#define REG_TCR_8703B 0x0604
|
||||
#define REG_RCR_8703B 0x0608
|
||||
#define REG_RX_PKT_LIMIT_8703B 0x060C
|
||||
#define REG_RX_DLK_TIME_8703B 0x060D
|
||||
#define REG_RX_DRVINFO_SZ_8703B 0x060F
|
||||
|
||||
#define REG_MACID_8703B 0x0610
|
||||
#define REG_BSSID_8703B 0x0618
|
||||
#define REG_MAR_8703B 0x0620
|
||||
#define REG_MBIDCAMCFG_8703B 0x0628
|
||||
#define REG_WOWLAN_GTK_DBG1 0x630
|
||||
#define REG_WOWLAN_GTK_DBG2 0x634
|
||||
|
||||
#define REG_USTIME_EDCA_8703B 0x0638
|
||||
#define REG_MAC_SPEC_SIFS_8703B 0x063A
|
||||
#define REG_RESP_SIFP_CCK_8703B 0x063C
|
||||
#define REG_RESP_SIFS_OFDM_8703B 0x063E
|
||||
#define REG_ACKTO_8703B 0x0640
|
||||
#define REG_CTS2TO_8703B 0x0641
|
||||
#define REG_EIFS_8703B 0x0642
|
||||
|
||||
#define REG_NAV_UPPER_8703B 0x0652 /* unit of 128 */
|
||||
#define REG_TRXPTCL_CTL_8703B 0x0668
|
||||
|
||||
/* Security */
|
||||
#define REG_CAMCMD_8703B 0x0670
|
||||
#define REG_CAMWRITE_8703B 0x0674
|
||||
#define REG_CAMREAD_8703B 0x0678
|
||||
#define REG_CAMDBG_8703B 0x067C
|
||||
#define REG_SECCFG_8703B 0x0680
|
||||
|
||||
/* Power */
|
||||
#define REG_WOW_CTRL_8703B 0x0690
|
||||
#define REG_PS_RX_INFO_8703B 0x0692
|
||||
#define REG_UAPSD_TID_8703B 0x0693
|
||||
#define REG_WKFMCAM_CMD_8703B 0x0698
|
||||
#define REG_WKFMCAM_NUM_8703B 0x0698
|
||||
#define REG_WKFMCAM_RWD_8703B 0x069C
|
||||
#define REG_RXFLTMAP0_8703B 0x06A0
|
||||
#define REG_RXFLTMAP1_8703B 0x06A2
|
||||
#define REG_RXFLTMAP2_8703B 0x06A4
|
||||
#define REG_BCN_PSR_RPT_8703B 0x06A8
|
||||
#define REG_BT_COEX_TABLE_8703B 0x06C0
|
||||
#define REG_BFMER0_INFO_8703B 0x06E4
|
||||
#define REG_BFMER1_INFO_8703B 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8703B 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8703B 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8703B 0x06FC
|
||||
|
||||
/* Hardware Port 2 */
|
||||
#define REG_MACID1_8703B 0x0700
|
||||
#define REG_BSSID1_8703B 0x0708
|
||||
#define REG_BFMEE_SEL_8703B 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8703B 0x0718
|
||||
|
||||
/* LTE_COEX */
|
||||
#define REG_LTECOEX_CTRL 0x07C0
|
||||
#define REG_LTECOEX_WRITE_DATA 0x07C4
|
||||
#define REG_LTECOEX_READ_DATA 0x07C8
|
||||
#define REG_LTECOEX_PATH_CONTROL 0x70
|
||||
|
||||
/* ************************************************************
|
||||
* SDIO Bus Specification
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO CMD Address Mapping
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* I/O bus domain (Host)
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO register
|
||||
* ----------------------------------------------------- */
|
||||
#define SDIO_REG_HCPWM1_8703B 0x025 /* HCI Current Power Mode 1 */
|
||||
|
||||
|
||||
/* ****************************************************************************
|
||||
* 8703 Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
#define BIT_USB_RXDMA_AGG_EN BIT(31)
|
||||
#define RXDMA_AGG_MODE_EN BIT(1)
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RXPKT_RELEASE_POLL BIT(16)
|
||||
#define RXDMA_IDLE BIT(17)
|
||||
#define RW_RELEASE_EN BIT(18)
|
||||
#endif
|
||||
|
||||
/* 2 HSISR
|
||||
* interrupt mask which needs to clear */
|
||||
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
|
||||
HSISR_SPS_OCP_INT |\
|
||||
HSISR_RON_INT |\
|
||||
HSISR_PDNINT |\
|
||||
HSISR_GPIO9_INT)
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8703B REG_CCK_CHECK (offset 0x454)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define BIT_BCN_PORT_SEL BIT(5)
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
|
||||
#ifdef CONFIG_RTL8703B
|
||||
#define EEPROM_RF_GAIN_OFFSET 0xC1
|
||||
#endif
|
||||
|
||||
#define EEPROM_RF_GAIN_VAL 0x1F6
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8195 IMR/ISR bits (offset 0xB0, 8bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define IMR_DISABLED_8703B 0
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8703B BIT(31) /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8703B BIT(30) /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8703B BIT(29) /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8703B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
|
||||
#define IMR_GTINT3_8703B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8703B BIT(26) /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8703B BIT(25) /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8703B BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8703B BIT(20) /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8703B BIT(16) /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8703B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8703B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8703B BIT(12) /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8703B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
|
||||
#define IMR_CPWM2_8703B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_CPWM_8703B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8703B BIT(7) /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8703B BIT(6) /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8703B BIT(5) /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8703B BIT(4) /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8703B BIT(3) /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8703B BIT(2) /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8703B BIT(1) /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8703B BIT(0) /* Receive DMA OK */
|
||||
|
||||
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
||||
#define IMR_BCNDMAINT7_8703B BIT(27) /* Beacon DMA Interrupt 7 */
|
||||
#define IMR_BCNDMAINT6_8703B BIT(26) /* Beacon DMA Interrupt 6 */
|
||||
#define IMR_BCNDMAINT5_8703B BIT(25) /* Beacon DMA Interrupt 5 */
|
||||
#define IMR_BCNDMAINT4_8703B BIT(24) /* Beacon DMA Interrupt 4 */
|
||||
#define IMR_BCNDMAINT3_8703B BIT(23) /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2_8703B BIT(22) /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1_8703B BIT(21) /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8703B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
|
||||
#define IMR_BCNDOK6_8703B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
|
||||
#define IMR_BCNDOK5_8703B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
|
||||
#define IMR_BCNDOK4_8703B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
|
||||
#define IMR_BCNDOK3_8703B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
|
||||
#define IMR_BCNDOK2_8703B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
|
||||
#define IMR_BCNDOK1_8703B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
|
||||
#define IMR_ATIMEND_E_8703B BIT(13) /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8703B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR_8703B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8703B BIT(9) /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8703B BIT(8) /* Receive FIFO Overflow */
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* #define IMR_RX_MASK (IMR_ROK_8703B|IMR_RDU_8703B|IMR_RXFOVW_8703B) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_8703B | IMR_VIDOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B | IMR_MGNTDOK_8703B | IMR_HIGHDOK_8703B)
|
||||
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8703B | IMR_TXBCN0OK_8703B | IMR_TXBCN0ERR_8703B | IMR_BCNDERR0_8703B)
|
||||
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8703B | IMR_VODOK_8703B | IMR_BEDOK_8703B | IMR_BKDOK_8703B)
|
||||
#endif
|
||||
|
||||
#endif /* __RTL8703B_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8703B_SRESET_H_
|
||||
#define _RTL8703B_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8703b_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8703b_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8703B_XMIT_H__
|
||||
#define __RTL8703B_XMIT_H__
|
||||
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
|
||||
#ifndef __INC_HAL8703BDESC_H
|
||||
#define __INC_HAL8703BDESC_H
|
||||
|
||||
#define RX_STATUS_DESC_SIZE_8703B 24
|
||||
#define RX_DRV_INFO_SIZE_UNIT_8703B 8
|
||||
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICV_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_LAST_SEG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
|
||||
#define GET_RX_STATUS_DESC_FIRST_SEG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FIT_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_CHKERR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_IPVER_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP__8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
#endif
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_SPLCP_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
|
||||
#define GET_RX_STATUS_DESC_LDPC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
|
||||
#define GET_RX_STATUS_DESC_STBC_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
|
||||
#define GET_RX_STATUS_DESC_BW_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_8703B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8703B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_STATUS_DESC_BUFF_ADDR_8703B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
|
||||
|
||||
|
||||
/* Dword 0 */
|
||||
#define GET_TX_DESC_OWN_8703B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
|
||||
#define SET_TX_DESC_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
|
||||
#define SET_TX_DESC_BMC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
|
||||
#define SET_TX_DESC_HTC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
|
||||
#define SET_TX_DESC_LAST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
|
||||
#define SET_TX_DESC_FIRST_SEG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
|
||||
#define SET_TX_DESC_LINIP_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
|
||||
#define SET_TX_DESC_NO_ACM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
|
||||
#define SET_TX_DESC_GF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
|
||||
#define SET_TX_DESC_OWN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_DESC_MACID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
|
||||
#define SET_TX_DESC_QUEUE_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
|
||||
#define SET_TX_DESC_PIFS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
|
||||
#define SET_TX_DESC_RATE_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
|
||||
#define SET_TX_DESC_SEC_TYPE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
|
||||
|
||||
|
||||
/* Dword 2 */
|
||||
#define SET_TX_DESC_PAID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
|
||||
#define SET_TX_DESC_CCA_RTS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
|
||||
#define SET_TX_DESC_AGG_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RDG_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
|
||||
#define SET_TX_DESC_AGG_BREAK_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MORE_FRAG_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
|
||||
#define SET_TX_DESC_RAW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
|
||||
#define SET_TX_DESC_SPE_RPT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
|
||||
#define SET_TX_DESC_BT_INT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
|
||||
#define SET_TX_DESC_GID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
|
||||
|
||||
|
||||
/* Dword 3 */
|
||||
#define SET_TX_DESC_WHEADER_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
|
||||
#define SET_TX_DESC_CHK_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
|
||||
#define SET_TX_DESC_EARLY_MODE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_SEL_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
|
||||
#define SET_TX_DESC_USE_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_FB_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
|
||||
#define SET_TX_DESC_CTS2SELF_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
|
||||
#define SET_TX_DESC_NAV_USE_HDR_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
|
||||
#define SET_TX_DESC_USE_MAX_LEN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
|
||||
#define SET_TX_DESC_NDPA_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
|
||||
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_DATA_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
|
||||
#define SET_TX_DESC_DATA_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_BW_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_LDPC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
|
||||
#define SET_TX_DESC_CTROL_STBC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_SHORT_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_SC_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
|
||||
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
|
||||
#define SET_TX_DESC_MBSSID_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_A_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_B_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_C_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_D_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
|
||||
|
||||
/* Dword 7 */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif /*CONFIG_PCI_HCI*/
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
|
||||
#define SET_TX_DESC_TX_DESC_CHECKSUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define SET_TX_DESC_SDIO_TXSEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
|
||||
#endif
|
||||
|
||||
/* Dword 8 */
|
||||
#define SET_TX_DESC_HWSEQ_EN_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_SEQ_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
|
||||
|
||||
/* Dword 10 */
|
||||
#define SET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
|
||||
#define GET_TX_DESC_TX_BUFFER_ADDRESS_8703B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
|
||||
|
||||
/* Dword 11 */
|
||||
#define SET_TX_DESC_NEXT_DESC_ADDRESS_8703B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
|
||||
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN0_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN1_1_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
|
||||
#define SET_EARLYMODE_LEN1_2_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
|
||||
#define SET_EARLYMODE_LEN2_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN3_8703B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
|
||||
|
||||
#endif
|
||||
/* -----------------------------------------------------------
|
||||
*
|
||||
* Rate
|
||||
*
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC8703B_RATE1M 0x00
|
||||
#define DESC8703B_RATE2M 0x01
|
||||
#define DESC8703B_RATE5_5M 0x02
|
||||
#define DESC8703B_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC8703B_RATE6M 0x04
|
||||
#define DESC8703B_RATE9M 0x05
|
||||
#define DESC8703B_RATE12M 0x06
|
||||
#define DESC8703B_RATE18M 0x07
|
||||
#define DESC8703B_RATE24M 0x08
|
||||
#define DESC8703B_RATE36M 0x09
|
||||
#define DESC8703B_RATE48M 0x0a
|
||||
#define DESC8703B_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC8703B_RATEMCS0 0x0c
|
||||
#define DESC8703B_RATEMCS1 0x0d
|
||||
#define DESC8703B_RATEMCS2 0x0e
|
||||
#define DESC8703B_RATEMCS3 0x0f
|
||||
#define DESC8703B_RATEMCS4 0x10
|
||||
#define DESC8703B_RATEMCS5 0x11
|
||||
#define DESC8703B_RATEMCS6 0x12
|
||||
#define DESC8703B_RATEMCS7 0x13
|
||||
#define DESC8703B_RATEMCS8 0x14
|
||||
#define DESC8703B_RATEMCS9 0x15
|
||||
#define DESC8703B_RATEMCS10 0x16
|
||||
#define DESC8703B_RATEMCS11 0x17
|
||||
#define DESC8703B_RATEMCS12 0x18
|
||||
#define DESC8703B_RATEMCS13 0x19
|
||||
#define DESC8703B_RATEMCS14 0x1a
|
||||
#define DESC8703B_RATEMCS15 0x1b
|
||||
#define DESC8703B_RATEVHTSS1MCS0 0x2c
|
||||
#define DESC8703B_RATEVHTSS1MCS1 0x2d
|
||||
#define DESC8703B_RATEVHTSS1MCS2 0x2e
|
||||
#define DESC8703B_RATEVHTSS1MCS3 0x2f
|
||||
#define DESC8703B_RATEVHTSS1MCS4 0x30
|
||||
#define DESC8703B_RATEVHTSS1MCS5 0x31
|
||||
#define DESC8703B_RATEVHTSS1MCS6 0x32
|
||||
#define DESC8703B_RATEVHTSS1MCS7 0x33
|
||||
#define DESC8703B_RATEVHTSS1MCS8 0x34
|
||||
#define DESC8703B_RATEVHTSS1MCS9 0x35
|
||||
#define DESC8703B_RATEVHTSS2MCS0 0x36
|
||||
#define DESC8703B_RATEVHTSS2MCS1 0x37
|
||||
#define DESC8703B_RATEVHTSS2MCS2 0x38
|
||||
#define DESC8703B_RATEVHTSS2MCS3 0x39
|
||||
#define DESC8703B_RATEVHTSS2MCS4 0x3a
|
||||
#define DESC8703B_RATEVHTSS2MCS5 0x3b
|
||||
#define DESC8703B_RATEVHTSS2MCS6 0x3c
|
||||
#define DESC8703B_RATEVHTSS2MCS7 0x3d
|
||||
#define DESC8703B_RATEVHTSS2MCS8 0x3e
|
||||
#define DESC8703B_RATEVHTSS2MCS9 0x3f
|
||||
|
||||
|
||||
#define RX_HAL_IS_CCK_RATE_8703B(pDesc)\
|
||||
(GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE1M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE2M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE5_5M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8703B(pDesc) == DESC8703B_RATE11M)
|
||||
|
||||
|
||||
void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
|
||||
void rtl8703b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8703bs_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8703bs_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8703bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8703bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8703bs_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8703bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8703bs_xmit_buf_handler(PADAPTER padapter);
|
||||
thread_return rtl8703bs_xmit_thread(thread_context context);
|
||||
#define hal_xmit_handler rtl8703bs_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8703bu_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8703bu_xmit_buf_handler
|
||||
|
||||
|
||||
s32 rtl8703bu_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8703bu_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8703bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8703bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8703bu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8703bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
|
||||
void rtl8703bu_xmit_tasklet(void *priv);
|
||||
s32 rtl8703bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8703be_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8703be_free_xmit_priv(PADAPTER padapter);
|
||||
struct xmit_buf *rtl8703be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
void rtl8703be_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8703be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8703be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8703be_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8703be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8703be_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
u8 BWMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
u8 SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_CMD_H__
|
||||
#define __RTL8710B_CMD_H__
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
enum h2c_cmd_8710B {
|
||||
/* Common Class: 000 */
|
||||
H2C_8710B_RSVD_PAGE = 0x00,
|
||||
H2C_8710B_MEDIA_STATUS_RPT = 0x01,
|
||||
H2C_8710B_SCAN_ENABLE = 0x02,
|
||||
H2C_8710B_KEEP_ALIVE = 0x03,
|
||||
H2C_8710B_DISCON_DECISION = 0x04,
|
||||
H2C_8710B_PSD_OFFLOAD = 0x05,
|
||||
H2C_8710B_AP_OFFLOAD = 0x08,
|
||||
H2C_8710B_BCN_RSVDPAGE = 0x09,
|
||||
H2C_8710B_PROBERSP_RSVDPAGE = 0x0A,
|
||||
H2C_8710B_FCS_RSVDPAGE = 0x10,
|
||||
H2C_8710B_FCS_INFO = 0x11,
|
||||
H2C_8710B_AP_WOW_GPIO_CTRL = 0x13,
|
||||
|
||||
/* PoweSave Class: 001 */
|
||||
H2C_8710B_SET_PWR_MODE = 0x20,
|
||||
H2C_8710B_PS_TUNING_PARA = 0x21,
|
||||
H2C_8710B_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8710B_P2P_LPS_PARAM = 0x23,
|
||||
H2C_8710B_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8710B_PS_SCAN_ENABLE = 0x25,
|
||||
H2C_8710B_SAP_PS_ = 0x26,
|
||||
H2C_8710B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
|
||||
H2C_8710B_FWLPS_IN_IPS_ = 0x28,
|
||||
|
||||
/* Dynamic Mechanism Class: 010 */
|
||||
H2C_8710B_MACID_CFG = 0x40,
|
||||
H2C_8710B_TXBF = 0x41,
|
||||
H2C_8710B_RSSI_SETTING = 0x42,
|
||||
H2C_8710B_AP_REQ_TXRPT = 0x43,
|
||||
H2C_8710B_INIT_RATE_COLLECT = 0x44,
|
||||
H2C_8710B_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
/* WOWLAN Class: 100 */
|
||||
H2C_8710B_WOWLAN = 0x80,
|
||||
H2C_8710B_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8710B_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8710B_AOAC_RSVD_PAGE = 0x83,
|
||||
H2C_8710B_AOAC_RSVD_PAGE2 = 0x84,
|
||||
H2C_8710B_D0_SCAN_OFFLOAD_CTRL = 0x85,
|
||||
H2C_8710B_D0_SCAN_OFFLOAD_INFO = 0x86,
|
||||
H2C_8710B_CHNL_SWITCH_OFFLOAD = 0x87,
|
||||
H2C_8710B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
|
||||
H2C_8710B_P2P_OFFLOAD = 0x8B,
|
||||
|
||||
H2C_8710B_RESET_TSF = 0xC0,
|
||||
H2C_8710B_MAXID,
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
|
||||
* ---------------------------------------------------------------------------------------------------------
|
||||
* _RSVDPAGE_LOC_CMD_0x00 */
|
||||
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/* _PWR_MOD_CMD_0x20 */
|
||||
#define SET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8710B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8710B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_8710B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _PS_TUNE_PARAM_CMD_0x21 */
|
||||
#define SET_8710B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
|
||||
#define SET_8710B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
|
||||
#define SET_8710B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _MACID_CFG_CMD_0x40 */
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
|
||||
|
||||
/* _RSSI_SETTING_CMD_0x42 */
|
||||
#define SET_8710B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
|
||||
#define SET_8710B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _AP_REQ_TXRPT_CMD_0x43 */
|
||||
#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_TXPWR_CMD_0x62 */
|
||||
#define SET_8710B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_MP_OPER_CMD_0x67 */
|
||||
#define SET_8710B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
|
||||
/* _BT_FW_PATCH_0x6A */
|
||||
#define SET_8710B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_8710B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ------------------------------------------- Structure --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- Function Statement --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/* host message to firmware cmd */
|
||||
void rtl8710b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8710b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
|
||||
/* s32 rtl8710b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
|
||||
void rtl8710b_set_FwPsTuneParam_cmd(PADAPTER padapter);
|
||||
void rtl8710b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8710b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8710b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
void rtl8710b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
s32 FillH2CCmd8710B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
u8 GetTxBufferRsvdPageNum8710B(_adapter *padapter, bool wowlan);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_DM_H__
|
||||
#define __RTL8710B_DM_H__
|
||||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for 8710B dynamic mechanism only
|
||||
*
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* structure and define
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* function prototype
|
||||
* ************************************************************ */
|
||||
|
||||
void rtl8710b_init_dm_priv(PADAPTER padapter);
|
||||
void rtl8710b_deinit_dm_priv(PADAPTER padapter);
|
||||
|
||||
void rtl8710b_InitHalDm(PADAPTER padapter);
|
||||
void rtl8710b_HalDmWatchDog(PADAPTER padapter);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_HAL_H__
|
||||
#define __RTL8710B_HAL_H__
|
||||
|
||||
#include "hal_data.h"
|
||||
|
||||
#include "rtl8710b_spec.h"
|
||||
#include "rtl8710b_rf.h"
|
||||
#include "rtl8710b_dm.h"
|
||||
#include "rtl8710b_recv.h"
|
||||
#include "rtl8710b_xmit.h"
|
||||
#include "rtl8710b_cmd.h"
|
||||
#include "rtl8710b_led.h"
|
||||
#include "Hal8710BPwrSeq.h"
|
||||
#include "Hal8710BPhyReg.h"
|
||||
#include "Hal8710BPhyCfg.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8710b_sreset.h"
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_POFF
|
||||
#include "rtl8710b_lps_poff.h"
|
||||
#endif
|
||||
|
||||
#define FW_8710B_SIZE 0x8000
|
||||
#define FW_8710B_START_ADDRESS 0x1000
|
||||
#define FW_8710B_END_ADDRESS 0x1FFF /* 0x5FFF */
|
||||
|
||||
typedef struct _RT_FIRMWARE {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_8710B_SIZE];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8710B, *PRT_FIRMWARE_8710B;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
typedef struct _RT_8710B_FIRMWARE_HDR {
|
||||
/* 8-byte alinment required */
|
||||
|
||||
/* --- LONG WORD 0 ---- */
|
||||
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
u8 Category; /* AP/NIC and USB/PCI */
|
||||
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
u16 Version; /* FW Version */
|
||||
u16 Subversion; /* FW Subversion, default 0x00 */
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
u8 Month; /* Release time Month field */
|
||||
u8 Date; /* Release time Date field */
|
||||
u8 Hour; /* Release time Hour field */
|
||||
u8 Minute; /* Release time Minute field */
|
||||
u16 RamCodeSize; /* The size of RAM code */
|
||||
u16 Rsvd2;
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
u32 SvnIdx; /* The SVN entry index */
|
||||
u32 Rsvd3;
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
} RT_8710B_FIRMWARE_HDR, *PRT_8710B_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8710B 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8710B 0x02
|
||||
|
||||
/* for 8710B
|
||||
* TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
|
||||
#define PAGE_SIZE_TX_8710B 128
|
||||
#define PAGE_SIZE_RX_8710B 8
|
||||
|
||||
#define TX_DMA_SIZE_8710B 0x8000 /* 32K(TX) */
|
||||
#define RX_DMA_SIZE_8710B 0x4000 /* 16K(RX) */
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8710B 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8710B 0x80 /* 128B, reserved for tx report */
|
||||
#endif
|
||||
#define RX_DMA_BOUNDARY_8710B\
|
||||
(RX_DMA_SIZE_8710B - RX_DMA_RESERVED_SIZE_8710B - 1)
|
||||
|
||||
|
||||
/* Note: We will divide number of page equally for each queue other than public queue! */
|
||||
|
||||
/* For General Reserved Page Number(Beacon Queue is reserved page)
|
||||
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8710B
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
|
||||
#define BCNQ_PAGE_NUM_8710B (MAX_BEACON_LEN/PAGE_SIZE_TX_8710B + 6) /*0x08*/
|
||||
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
|
||||
* NS offload: 2 NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8710B 0x0b
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8710B 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#undef WOWLAN_PAGE_NUM_8710B
|
||||
#define WOWLAN_PAGE_NUM_8710B 0x15
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_WOWLAN
|
||||
#define AP_WOWLAN_PAGE_NUM_8710B 0x02
|
||||
#endif
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER_8710B\
|
||||
(0xFF - BCNQ_PAGE_NUM_8710B -WOWLAN_PAGE_NUM_8710B)
|
||||
#define TX_PAGE_BOUNDARY_8710B (TX_TOTAL_PAGE_NUMBER_8710B + 1)
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B TX_TOTAL_PAGE_NUMBER_8710B
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8710B\
|
||||
(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8710B + 1)
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8710B */
|
||||
#define NORMAL_PAGE_NUM_HPQ_8710B 0x0C
|
||||
#define NORMAL_PAGE_NUM_LPQ_8710B 0x02
|
||||
#define NORMAL_PAGE_NUM_NPQ_8710B 0x02
|
||||
#define NORMAL_PAGE_NUM_EPQ_8710B 0x04
|
||||
|
||||
/* Note: For Normal Chip Setting, modify later */
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8710B 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8710B 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8710B 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_EPQ_8710B 0x00
|
||||
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
|
||||
|
||||
#define HAL_EFUSE_MEMORY
|
||||
#define HWSET_MAX_SIZE_8710B 512
|
||||
#define EFUSE_REAL_CONTENT_LEN_8710B 512
|
||||
#define EFUSE_MAP_LEN_8710B 512
|
||||
#define EFUSE_MAX_SECTION_8710B 64
|
||||
|
||||
/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
|
||||
#define EFUSE_IC_ID_OFFSET 506
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8710B)
|
||||
|
||||
#define EFUSE_ACCESS_ON 0x69
|
||||
#define EFUSE_ACCESS_OFF 0x00
|
||||
|
||||
#define PACKAGE_QFN32_S 0
|
||||
#define PACKAGE_QFN48M_S 1 //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xFE
|
||||
#define PACKAGE_QFN48_S 2
|
||||
#define PACKAGE_QFN64_S 3
|
||||
#define PACKAGE_QFN32_U 4
|
||||
#define PACKAGE_QFN48M_U 5 //definiton 8188GU Dongle Package, Efuse Physical Address 0xF8 = 0xEE
|
||||
#define PACKAGE_QFN48_U 6
|
||||
#define PACKAGE_QFN68_U 7
|
||||
|
||||
typedef enum _PACKAGE_TYPE_E
|
||||
{
|
||||
PACKAGE_DEFAULT,
|
||||
PACKAGE_QFN68,
|
||||
PACKAGE_TFBGA90,
|
||||
PACKAGE_TFBGA80,
|
||||
PACKAGE_TFBGA79
|
||||
}PACKAGE_TYPE_E;
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
|
||||
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
#ifdef CONFIG_FILE_FWIMG
|
||||
extern char *rtw_fw_file_path;
|
||||
extern char *rtw_fw_wow_file_path;
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
extern char *rtw_fw_mp_bt_file_path;
|
||||
#endif /* CONFIG_MP_INCLUDED */
|
||||
#endif /* CONFIG_FILE_FWIMG */
|
||||
|
||||
/* rtl8710b_hal_init.c */
|
||||
s32 rtl8710b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
|
||||
void rtl8710b_FirmwareSelfReset(PADAPTER padapter);
|
||||
void rtl8710b_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
void rtl8710b_InitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8710b_DeinitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8710b_CheckAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8710b_init_default_value(PADAPTER padapter);
|
||||
|
||||
|
||||
u32 indirect_read32_8710b(PADAPTER padapter, u32 regaddr);
|
||||
void indirect_write32_8710b(PADAPTER padapter, u32 regaddr, u32 data);
|
||||
u32 hal_query_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask);
|
||||
void hal_set_syson_reg_8710b(PADAPTER padapter, u32 regaddr, u32 bitmask, u32 data);
|
||||
#define HAL_SetSYSOnReg hal_set_syson_reg_8710b
|
||||
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8710B(PADAPTER padapter);
|
||||
|
||||
#if 0
|
||||
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_EfuseParseTxPowerInfo_8710B(PADAPTER padapter,
|
||||
u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseEEPROMVer_8710B(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParsePackageType_8710B(PADAPTER pAdapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseChnlPlan_8710B(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID_8710B(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseAntennaDiversity_8710B(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8710B(PADAPTER pAdapter,
|
||||
u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseThermalMeter_8710B(PADAPTER padapter,
|
||||
u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseBoardType_8710B(PADAPTER Adapter,
|
||||
u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
#endif
|
||||
|
||||
void rtl8710b_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8710b(_adapter *adapter);
|
||||
u8 SetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8710B(PADAPTER padapter, u8 variable, u8 *val);
|
||||
u8 SetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
u8 GetHalDefVar8710B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
|
||||
/* register */
|
||||
void rtl8710b_InitBeaconParameters(PADAPTER padapter);
|
||||
void rtl8710b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
|
||||
void _8051Reset8710(PADAPTER padapter);
|
||||
|
||||
void rtl8710b_start_thread(_adapter *padapter);
|
||||
void rtl8710b_stop_thread(_adapter *padapter);
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
|
||||
#endif
|
||||
|
||||
void CCX_FwC2HTxRpt_8710b(PADAPTER padapter, u8 *pdata, u8 len);
|
||||
|
||||
u8 MRateToHwRate8710B(u8 rate);
|
||||
u8 HwRateToMRate8710B(u8 rate);
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_LED_H__
|
||||
#define __RTL8710B_LED_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8710bu_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8710bu_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8710bs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_GSPI_HCI
|
||||
void rtl8710bs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8710bs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8710be_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8710be_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif /*#ifdef CONFIG_RTW_SW_LED*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************** CONST ************************/
|
||||
#define NUM_OF_REGISTER_BANK 13
|
||||
#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
|
||||
#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
|
||||
#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
|
||||
#define LPS_POFF_DYNAMIC_FILE_LEN (512 + TXDESC_SIZE)
|
||||
/******************************************** CONST ************************/
|
||||
|
||||
/******************************************** MACRO ************************/
|
||||
/* HOIE Entry Definition */
|
||||
#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE), 0, 16, __Value)
|
||||
#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
|
||||
#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
|
||||
#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
|
||||
#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
|
||||
|
||||
/*********************Function Definition*******************************************/
|
||||
void rtl8710b_lps_poff_init(PADAPTER padapter);
|
||||
void rtl8710b_lps_poff_deinit(PADAPTER padapter);
|
||||
bool rtl8710b_lps_poff_get_txbndy_status(PADAPTER padapter);
|
||||
void rtl8710b_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
|
||||
void rtl8710b_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
|
||||
bool rtl8710b_lps_poff_get_status(PADAPTER padapter);
|
||||
void rtl8710b_lps_poff_wow(PADAPTER padapter);
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_RECV_H__
|
||||
#define __RTL8710B_RECV_H__
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifdef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#else
|
||||
#ifdef CONFIG_PLATFORM_MSTAR
|
||||
#define MAX_RECVBUF_SZ (8192) /* 8K */
|
||||
#elif defined(CONFIG_PLATFORM_HISILICON)
|
||||
#define MAX_RECVBUF_SZ (16384) /* 16k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
|
||||
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
|
||||
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16k - 92E RX BUF :16K */
|
||||
#endif
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
#endif
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RTL8710B RX BUFFER DESC */
|
||||
/*-----------------------------------------------------------------*/
|
||||
/*DWORD 0*/
|
||||
#define SET_RX_BUFFER_DESC_DATA_LENGTH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
|
||||
|
||||
#define GET_RX_BUFFER_DESC_OWN_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
#define GET_RX_BUFFER_DESC_LS_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_BUFFER_DESC_FS_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
|
||||
#ifdef USING_RX_TAG
|
||||
#define GET_RX_BUFFER_DESC_RX_TAG_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
|
||||
#else
|
||||
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8710B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
|
||||
#endif
|
||||
|
||||
/*DWORD 1*/
|
||||
#define SET_RX_BUFFER_PHYSICAL_LOW_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
|
||||
|
||||
/*DWORD 2*/
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
|
||||
#else
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH_8710B(__pRxStatusDesc, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
int rtl8710bu_init_recv_priv(_adapter *padapter);
|
||||
void rtl8710bu_free_recv_priv(_adapter *padapter);
|
||||
void rtl8710bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
#endif
|
||||
|
||||
void rtl8710b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8710B_RECV_H__ */
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_RF_H__
|
||||
#define __RTL8710B_RF_H__
|
||||
|
||||
int PHY_RF6052_Config8710B(PADAPTER pdapter);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,481 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_SPEC_H__
|
||||
#define __RTL8710B_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
|
||||
#define HAL_NAV_UPPER_UNIT_8710B 128 /* micro-second */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SYS_ISO_CTRL_8710B 0x0000 /* 2 Byte */
|
||||
#define REG_APS_FSMCO_8710B 0x0004 /* 4 Byte */
|
||||
#define REG_SYS_CLKR_8710B 0x0008 /* 2 Byte */
|
||||
#define REG_9346CR_8710B 0x000A /* 2 Byte */
|
||||
#define REG_EE_VPD_8710B 0x000C /* 2 Byte */
|
||||
#define REG_AFE_MISC_8710B 0x0010 /* 1 Byte */
|
||||
#define REG_SPS0_CTRL_8710B 0x0011 /* 7 Byte */
|
||||
#define REG_SPS_OCP_CFG_8710B 0x0018 /* 4 Byte */
|
||||
#define REG_RSV_CTRL_8710B 0x001C /* 3 Byte */
|
||||
#define REG_RF_CTRL_8710B 0x001F /* 1 Byte */
|
||||
#define REG_LPLDO_CTRL_8710B 0x0023 /* 1 Byte */
|
||||
#define REG_AFE_XTAL_CTRL_8710B 0x0024 /* 4 Byte */
|
||||
#define REG_AFE_PLL_CTRL_8710B 0x0028 /* 4 Byte */
|
||||
#define REG_MAC_PLL_CTRL_EXT_8710B 0x002c /* 4 Byte */
|
||||
#define REG_EFUSE_CTRL_8710B 0x0030
|
||||
#define REG_EFUSE_TEST_8710B 0x0034
|
||||
#define REG_PWR_DATA_8710B 0x0038
|
||||
#define REG_CAL_TIMER_8710B 0x003C
|
||||
#define REG_ACLK_MON_8710B 0x003E
|
||||
#define REG_GPIO_MUXCFG_8710B 0x0040
|
||||
#define REG_GPIO_IO_SEL_8710B 0x0042
|
||||
#define REG_MAC_PINMUX_CFG_8710B 0x0043
|
||||
#define REG_GPIO_PIN_CTRL_8710B 0x0044
|
||||
#define REG_GPIO_INTM_8710B 0x0048
|
||||
#define REG_LEDCFG0_8710B 0x004C
|
||||
#define REG_LEDCFG1_8710B 0x004D
|
||||
#define REG_LEDCFG2_8710B 0x004E
|
||||
#define REG_LEDCFG3_8710B 0x004F
|
||||
#define REG_FSIMR_8710B 0x0050
|
||||
#define REG_FSISR_8710B 0x0054
|
||||
#define REG_HSIMR_8710B 0x0058
|
||||
#define REG_HSISR_8710B 0x005c
|
||||
#define REG_GPIO_EXT_CTRL 0x0060
|
||||
#define REG_PAD_CTRL1_8710B 0x0064
|
||||
#define REG_MULTI_FUNC_CTRL_8710B 0x0068
|
||||
#define REG_GPIO_STATUS_8710B 0x006C
|
||||
#define REG_SDIO_CTRL_8710B 0x0070
|
||||
#define REG_OPT_CTRL_8710B 0x0074
|
||||
#define REG_AFE_CTRL_4_8710B 0x0078
|
||||
#define REG_MCUFWDL_8710B 0x0080
|
||||
#define REG_8051FW_CTRL_8710B 0x0080
|
||||
#define REG_HMEBOX_DBG_0_8710B 0x0088
|
||||
#define REG_HMEBOX_DBG_1_8710B 0x008A
|
||||
#define REG_HMEBOX_DBG_2_8710B 0x008C
|
||||
#define REG_HMEBOX_DBG_3_8710B 0x008E
|
||||
#define REG_WLLPS_CTRL 0x0090
|
||||
|
||||
#define REG_PMC_DBG_CTRL2_8710B 0x00CC
|
||||
#define REG_EFUSE_BURN_GNT_8710B 0x00CF
|
||||
#define REG_HPON_FSM_8710B 0x00EC
|
||||
#define REG_SYS_CFG1_8710B 0x00F0
|
||||
#define REG_SYS_CFG_8710B 0x00FC
|
||||
#define REG_ROM_VERSION 0x00FD
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_C2HEVT_CMD_ID_8710B 0x01A0
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
|
||||
#define REG_C2HEVT_CMD_LEN_8710B 0x01AE
|
||||
#define REG_C2HEVT_CLEAR_8710B 0x01AF
|
||||
#define REG_MCUTST_1_8710B 0x01C0
|
||||
#define REG_WOWLAN_WAKE_REASON 0x01C7
|
||||
#define REG_FMETHR_8710B 0x01C8
|
||||
#define REG_HMETFR_8710B 0x01CC
|
||||
#define REG_HMEBOX_0_8710B 0x01D0
|
||||
#define REG_HMEBOX_1_8710B 0x01D4
|
||||
#define REG_HMEBOX_2_8710B 0x01D8
|
||||
#define REG_HMEBOX_3_8710B 0x01DC
|
||||
#define REG_LLT_INIT_8710B 0x01E0
|
||||
#define REG_HMEBOX_EXT0_8710B 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8710B 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8710B 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8710B 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RQPN_8710B 0x0200
|
||||
#define REG_FIFOPAGE_8710B 0x0204
|
||||
#define REG_DWBCN0_CTRL_8710B REG_TDECTRL
|
||||
#define REG_TXDMA_OFFSET_CHK_8710B 0x020C
|
||||
#define REG_TXDMA_STATUS_8710B 0x0210
|
||||
#define REG_RQPN_NPQ_8710B 0x0214
|
||||
#define REG_DWBCN1_CTRL_8710B 0x0228
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RXDMA_AGG_PG_TH_8710B 0x0280
|
||||
#define REG_FW_UPD_RDPTR_8710B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
|
||||
#define REG_RXDMA_CONTROL_8710B 0x0286 /* Control the RX DMA. */
|
||||
#define REG_RXDMA_STATUS_8710B 0x0288
|
||||
#define REG_RXDMA_MODE_CTRL_8710B 0x0290
|
||||
#define REG_EARLY_MODE_CONTROL_8710B 0x02BC
|
||||
#define REG_RSVD5_8710B 0x02F0
|
||||
#define REG_RSVD6_8710B 0x02F4
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8710B 0x0300
|
||||
#define REG_INT_MIG_8710B 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_TXBD_DESA_8710B 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_MGQ_TXBD_DESA_8710B 0x0310 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_TXBD_DESA_8710B 0x0318 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_TXBD_DESA_8710B 0x0320 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_TXBD_DESA_8710B 0x0328 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_TXBD_DESA_8710B 0x0330 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RXQ_RXBD_DESA_8710B 0x0338 /* RX Queue Descriptor Address */
|
||||
#define REG_HI0Q_TXBD_DESA_8710B 0x0340
|
||||
#define REG_HI1Q_TXBD_DESA_8710B 0x0348
|
||||
#define REG_HI2Q_TXBD_DESA_8710B 0x0350
|
||||
#define REG_HI3Q_TXBD_DESA_8710B 0x0358
|
||||
#define REG_HI4Q_TXBD_DESA_8710B 0x0360
|
||||
#define REG_HI5Q_TXBD_DESA_8710B 0x0368
|
||||
#define REG_HI6Q_TXBD_DESA_8710B 0x0370
|
||||
#define REG_HI7Q_TXBD_DESA_8710B 0x0378
|
||||
#define REG_MGQ_TXBD_NUM_8710B 0x0380
|
||||
#define REG_RX_RXBD_NUM_8710B 0x0382
|
||||
#define REG_VOQ_TXBD_NUM_8710B 0x0384
|
||||
#define REG_VIQ_TXBD_NUM_8710B 0x0386
|
||||
#define REG_BEQ_TXBD_NUM_8710B 0x0388
|
||||
#define REG_BKQ_TXBD_NUM_8710B 0x038A
|
||||
#define REG_HI0Q_TXBD_NUM_8710B 0x038C
|
||||
#define REG_HI1Q_TXBD_NUM_8710B 0x038E
|
||||
#define REG_HI2Q_TXBD_NUM_8710B 0x0390
|
||||
#define REG_HI3Q_TXBD_NUM_8710B 0x0392
|
||||
#define REG_HI4Q_TXBD_NUM_8710B 0x0394
|
||||
#define REG_HI5Q_TXBD_NUM_8710B 0x0396
|
||||
#define REG_HI6Q_TXBD_NUM_8710B 0x0398
|
||||
#define REG_HI7Q_TXBD_NUM_8710B 0x039A
|
||||
#define REG_TSFTIMER_HCI_8710B 0x039C
|
||||
#define REG_BD_RW_PTR_CLR_8710B 0x039C
|
||||
|
||||
/* Read Write Point */
|
||||
#define REG_VOQ_TXBD_IDX_8710B 0x03A0
|
||||
#define REG_VIQ_TXBD_IDX_8710B 0x03A4
|
||||
#define REG_BEQ_TXBD_IDX_8710B 0x03A8
|
||||
#define REG_BKQ_TXBD_IDX_8710B 0x03AC
|
||||
#define REG_MGQ_TXBD_IDX_8710B 0x03B0
|
||||
#define REG_RXQ_TXBD_IDX_8710B 0x03B4
|
||||
#define REG_HI0Q_TXBD_IDX_8710B 0x03B8
|
||||
#define REG_HI1Q_TXBD_IDX_8710B 0x03BC
|
||||
#define REG_HI2Q_TXBD_IDX_8710B 0x03C0
|
||||
#define REG_HI3Q_TXBD_IDX_8710B 0x03C4
|
||||
#define REG_HI4Q_TXBD_IDX_8710B 0x03C8
|
||||
#define REG_HI5Q_TXBD_IDX_8710B 0x03CC
|
||||
#define REG_HI6Q_TXBD_IDX_8710B 0x03D0
|
||||
#define REG_HI7Q_TXBD_IDX_8710B 0x03D4
|
||||
|
||||
#define REG_PCIE_HCPWM_8710BE 0x03D8 /* ?????? */
|
||||
#define REG_PCIE_HRPWM_8710BE 0x03DC /* PCIe RPWM ?????? */
|
||||
#define REG_DBI_WDATA_V1_8710B 0x03E8
|
||||
#define REG_DBI_RDATA_V1_8710B 0x03EC
|
||||
#define REG_DBI_FLAG_V1_8710B 0x03F0
|
||||
#define REG_MDIO_V1_8710B 0x03F4
|
||||
#define REG_PCIE_MIX_CFG_8710B 0x03F8
|
||||
#define REG_HCI_MIX_CFG_8710B 0x03FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_VOQ_INFORMATION_8710B 0x0400
|
||||
#define REG_VIQ_INFORMATION_8710B 0x0404
|
||||
#define REG_BEQ_INFORMATION_8710B 0x0408
|
||||
#define REG_BKQ_INFORMATION_8710B 0x040C
|
||||
#define REG_MGQ_INFORMATION_8710B 0x0410
|
||||
#define REG_HGQ_INFORMATION_8710B 0x0414
|
||||
#define REG_BCNQ_INFORMATION_8710B 0x0418
|
||||
#define REG_TXPKT_EMPTY_8710B 0x041A
|
||||
|
||||
#define REG_FWHW_TXQ_CTRL_8710B 0x0420
|
||||
#define REG_HWSEQ_CTRL_8710B 0x0423
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY_8710B 0x0424
|
||||
#define REG_TXPKTBUF_MGQ_BDNY_8710B 0x0425
|
||||
#define REG_LIFECTRL_CTRL_8710B 0x0426
|
||||
#define REG_MULTI_BCNQ_OFFSET_8710B 0x0427
|
||||
#define REG_SPEC_SIFS_8710B 0x0428
|
||||
#define REG_RL_8710B 0x042A
|
||||
#define REG_TXBF_CTRL_8710B 0x042C
|
||||
#define REG_DARFRC_8710B 0x0430
|
||||
#define REG_RARFRC_8710B 0x0438
|
||||
#define REG_RRSR_8710B 0x0440
|
||||
#define REG_ARFR0_8710B 0x0444
|
||||
#define REG_ARFR1_8710B 0x044C
|
||||
#define REG_CCK_CHECK_8710B 0x0454
|
||||
#define REG_AMPDU_MAX_TIME_8710B 0x0456
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY1_8710B 0x0457
|
||||
|
||||
#define REG_AMPDU_MAX_LENGTH_8710B 0x0458
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8710B 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8710B 0x045F
|
||||
#define REG_FAST_EDCA_CTRL_8710B 0x0460
|
||||
#define REG_RD_RESP_PKT_TH_8710B 0x0463
|
||||
#define REG_DATA_SC_8710B 0x0483
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x0484
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x0488
|
||||
#endif
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_POWER_STAGE1_8710B 0x04B4
|
||||
#define REG_POWER_STAGE2_8710B 0x04B8
|
||||
#define REG_AMPDU_BURST_MODE_8710B 0x04BC
|
||||
#define REG_PKT_VO_VI_LIFE_TIME_8710B 0x04C0
|
||||
#define REG_PKT_BE_BK_LIFE_TIME_8710B 0x04C2
|
||||
#define REG_STBC_SETTING_8710B 0x04C4
|
||||
#define REG_HT_SINGLE_AMPDU_8710B 0x04C7
|
||||
#define REG_PROT_MODE_CTRL_8710B 0x04C8
|
||||
#define REG_MAX_AGGR_NUM_8710B 0x04CA
|
||||
#define REG_RTS_MAX_AGGR_NUM_8710B 0x04CB
|
||||
#define REG_BAR_MODE_CTRL_8710B 0x04CC
|
||||
#define REG_RA_TRY_RATE_AGG_LMT_8710B 0x04CF
|
||||
#define REG_MACID_PKT_DROP0_8710B 0x04D0
|
||||
#define REG_MACID_PKT_SLEEP_8710B 0x04D4
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_EDCA_VO_PARAM_8710B 0x0500
|
||||
#define REG_EDCA_VI_PARAM_8710B 0x0504
|
||||
#define REG_EDCA_BE_PARAM_8710B 0x0508
|
||||
#define REG_EDCA_BK_PARAM_8710B 0x050C
|
||||
#define REG_BCNTCFG_8710B 0x0510
|
||||
#define REG_PIFS_8710B 0x0512
|
||||
#define REG_RDG_PIFS_8710B 0x0513
|
||||
#define REG_SIFS_CTX_8710B 0x0514
|
||||
#define REG_SIFS_TRX_8710B 0x0516
|
||||
#define REG_AGGR_BREAK_TIME_8710B 0x051A
|
||||
#define REG_SLOT_8710B 0x051B
|
||||
#define REG_TX_PTCL_CTRL_8710B 0x0520
|
||||
#define REG_TXPAUSE_8710B 0x0522
|
||||
#define REG_DIS_TXREQ_CLR_8710B 0x0523
|
||||
#define REG_RD_CTRL_8710B 0x0524
|
||||
/*
|
||||
* Format for offset 540h-542h:
|
||||
* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
|
||||
* [7:4]: Reserved.
|
||||
* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
|
||||
* [23:20]: Reserved
|
||||
* Description:
|
||||
* |
|
||||
* |<--Setup--|--Hold------------>|
|
||||
* --------------|----------------------
|
||||
* |
|
||||
* TBTT
|
||||
* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
|
||||
* Described by Designer Tim and Bruce, 2011-01-14.
|
||||
* */
|
||||
#define REG_TBTT_PROHIBIT_8710B 0x0540
|
||||
#define REG_RD_NAV_NXT_8710B 0x0544
|
||||
#define REG_NAV_PROT_LEN_8710B 0x0546
|
||||
#define REG_BCN_CTRL_8710B 0x0550
|
||||
#define REG_BCN_CTRL_1_8710B 0x0551
|
||||
#define REG_MBID_NUM_8710B 0x0552
|
||||
#define REG_DUAL_TSF_RST_8710B 0x0553
|
||||
#define REG_BCN_INTERVAL_8710B 0x0554
|
||||
#define REG_DRVERLYINT_8710B 0x0558
|
||||
#define REG_BCNDMATIM_8710B 0x0559
|
||||
#define REG_ATIMWND_8710B 0x055A
|
||||
#define REG_USTIME_TSF_8710B 0x055C
|
||||
#define REG_BCN_MAX_ERR_8710B 0x055D
|
||||
#define REG_RXTSF_OFFSET_CCK_8710B 0x055E
|
||||
#define REG_RXTSF_OFFSET_OFDM_8710B 0x055F
|
||||
#define REG_TSFTR_8710B 0x0560
|
||||
#define REG_CTWND_8710B 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8710B 0x0577
|
||||
#define REG_PSTIMER_8710B 0x0580
|
||||
#define REG_TIMER0_8710B 0x0584
|
||||
#define REG_TIMER1_8710B 0x0588
|
||||
#define REG_ACMHWCTRL_8710B 0x05C0
|
||||
#define REG_SCH_TXCMD_8710B 0x05F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_MAC_CR_8710B 0x0600
|
||||
#define REG_TCR_8710B 0x0604
|
||||
#define REG_RCR_8710B 0x0608
|
||||
#define REG_RX_PKT_LIMIT_8710B 0x060C
|
||||
#define REG_RX_DLK_TIME_8710B 0x060D
|
||||
#define REG_RX_DRVINFO_SZ_8710B 0x060F
|
||||
|
||||
#define REG_MACID_8710B 0x0610
|
||||
#define REG_BSSID_8710B 0x0618
|
||||
#define REG_MAR_8710B 0x0620
|
||||
#define REG_MBIDCAMCFG_8710B 0x0628
|
||||
#define REG_WOWLAN_GTK_DBG1 0x630
|
||||
#define REG_WOWLAN_GTK_DBG2 0x634
|
||||
|
||||
#define REG_USTIME_EDCA_8710B 0x0638
|
||||
#define REG_MAC_SPEC_SIFS_8710B 0x063A
|
||||
#define REG_RESP_SIFP_CCK_8710B 0x063C
|
||||
#define REG_RESP_SIFS_OFDM_8710B 0x063E
|
||||
#define REG_ACKTO_8710B 0x0640
|
||||
#define REG_CTS2TO_8710B 0x0641
|
||||
#define REG_EIFS_8710B 0x0642
|
||||
|
||||
#define REG_NAV_UPPER_8710B 0x0652 /* unit of 128 */
|
||||
#define REG_TRXPTCL_CTL_8710B 0x0668
|
||||
|
||||
/* Security */
|
||||
#define REG_CAMCMD_8710B 0x0670
|
||||
#define REG_CAMWRITE_8710B 0x0674
|
||||
#define REG_CAMREAD_8710B 0x0678
|
||||
#define REG_CAMDBG_8710B 0x067C
|
||||
#define REG_SECCFG_8710B 0x0680
|
||||
|
||||
/* Power */
|
||||
#define REG_WOW_CTRL_8710B 0x0690
|
||||
#define REG_PS_RX_INFO_8710B 0x0692
|
||||
#define REG_UAPSD_TID_8710B 0x0693
|
||||
#define REG_WKFMCAM_CMD_8710B 0x0698
|
||||
#define REG_WKFMCAM_NUM_8710B 0x0698
|
||||
#define REG_WKFMCAM_RWD_8710B 0x069C
|
||||
#define REG_RXFLTMAP0_8710B 0x06A0
|
||||
#define REG_RXFLTMAP1_8710B 0x06A2
|
||||
#define REG_RXFLTMAP2_8710B 0x06A4
|
||||
#define REG_BCN_PSR_RPT_8710B 0x06A8
|
||||
#define REG_BT_COEX_TABLE_8710B 0x06C0
|
||||
#define REG_BFMER0_INFO_8710B 0x06E4
|
||||
#define REG_BFMER1_INFO_8710B 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8710B 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8710B 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8710B 0x06FC
|
||||
|
||||
/* Hardware Port 2 */
|
||||
#define REG_MACID1_8710B 0x0700
|
||||
#define REG_BSSID1_8710B 0x0708
|
||||
#define REG_BFMEE_SEL_8710B 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8710B 0x0718
|
||||
|
||||
/* LTR */
|
||||
#define REG_LTR_CTRL_BASIC_8710B 0x07A4
|
||||
#define REG_LTR_IDLE_LATENCY_V1_8710B 0x0798
|
||||
#define REG_LTR_ACTIVE_LATENCY_V1_8710B 0x079C
|
||||
|
||||
/* LTE_COEX */
|
||||
#define REG_LTECOEX_CTRL 0x07C0
|
||||
#define REG_LTECOEX_WRITE_DATA 0x07C4
|
||||
#define REG_LTECOEX_READ_DATA 0x07C8
|
||||
#define REG_LTECOEX_PATH_CONTROL 0x70
|
||||
|
||||
/* Other */
|
||||
#define REG_USB_ACCESS_TIMEOUT 0xFE4C
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SYSON_REG_SPEC
|
||||
* ----------------------------------------------------- */
|
||||
#define SYSON_REG_BASE_ADDR_8710B 0x40000000
|
||||
#define REG_SYS_XTAL_CTRL0 0x0060
|
||||
#define REG_SYS_SYSTEM_CFG0 0x1F0
|
||||
#define REG_SYS_SYSTEM_CFG1 0x1F4
|
||||
#define REG_SYS_SYSTEM_CFG2 0x1F8
|
||||
#define REG_SYS_EEPROM_CTRL0 0x0E0
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Indirect_R/W_SPEC
|
||||
* ----------------------------------------------------- */
|
||||
#define NORMAL_REG_READ_OFFSET 0x83000000
|
||||
#define NORMAL_REG_WRITE_OFFSET 0x84000000
|
||||
#define EFUSE_READ_OFFSET 0x85000000
|
||||
#define EFUSE_WRITE_OFFSET 0x86000000
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* PAGE0_WLANON_REG_SPEC
|
||||
* ----------------------------------------------------- */
|
||||
#define PAGE0_OFFSET 0x0 // WLANON_PAGE0_REG needs to add an offset.
|
||||
|
||||
|
||||
|
||||
/* ****************************************************************************
|
||||
* 8723 Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* REG_SYS_SYSTEM_CFG0
|
||||
* ----------------------------------------------------- */
|
||||
#define BIT_RTL_ID_8710B BIT(16)
|
||||
|
||||
#define BIT_MASK_CHIP_VER_8710B 0xf
|
||||
#define BIT_GET_CHIP_VER_8710B(x) ((x) & BIT_MASK_CHIP_VER_8710B)
|
||||
|
||||
#define BIT_SHIFT_VENDOR_ID_8710B 4
|
||||
#define BIT_MASK_VENDOR_ID_8710B 0xf
|
||||
#define BIT_GET_VENDOR_ID_8710B(x) (((x) >> BIT_SHIFT_VENDOR_ID_8710B) & BIT_MASK_VENDOR_ID_8710B)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* REG_SYS_SYSTEM_CFG1
|
||||
* ----------------------------------------------------- */
|
||||
#define BIT_SPSLDO_SEL_8710B BIT(25)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* REG_SYS_SYSTEM_CFG2
|
||||
* ----------------------------------------------------- */
|
||||
#define BIT_MASK_RF_RL_ID_8710B 0xf
|
||||
#define BIT_GET_RF_RL_ID_8710B(x) ((x) & BIT_MASK_RF_RL_ID_8710B)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* REG_SYS_SYSTEM_CFG2
|
||||
* ----------------------------------------------------- */
|
||||
#define BIT_EERPOMSEL_8710B BIT(4)
|
||||
#define BIT_AUTOLOAD_SUS_8710B BIT(5)
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* Other
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
|
||||
#define BIT_USB_RXDMA_AGG_EN BIT(31)
|
||||
#define RXDMA_AGG_MODE_EN BIT(1)
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RXPKT_RELEASE_POLL BIT(16)
|
||||
#define RXDMA_IDLE BIT(17)
|
||||
#define RW_RELEASE_EN BIT(18)
|
||||
#endif
|
||||
|
||||
/* 2 HSISR
|
||||
* interrupt mask which needs to clear */
|
||||
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
|
||||
HSISR_SPS_OCP_INT |\
|
||||
HSISR_RON_INT |\
|
||||
HSISR_PDNINT |\
|
||||
HSISR_GPIO9_INT)
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
#ifdef CONFIG_RTL8710B
|
||||
#define EEPROM_RF_GAIN_OFFSET 0xC1
|
||||
#endif
|
||||
|
||||
#define EEPROM_RF_GAIN_VAL 0x1F6
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
#endif /* __RTL8710B_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8710B_SRESET_H_
|
||||
#define _RTL8710B_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8710b_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8710b_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,523 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8710B_XMIT_H__
|
||||
#define __RTL8710B_XMIT_H__
|
||||
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
|
||||
#ifndef __INC_HAL8710BDESC_H
|
||||
#define __INC_HAL8710BDESC_H
|
||||
|
||||
#define RX_STATUS_DESC_SIZE_8710B 24
|
||||
#define RX_DRV_INFO_SIZE_UNIT_8710B 8
|
||||
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICV_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FIT_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_CHKERR_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_IPVER_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP__8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
#define GET_RX_STATUS_DESC_FCS_OK_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
#endif
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_MATCH_ID_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_8710B(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8710B(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_STATUS_DESC_BUFF_ADDR_8710B(__pRxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
|
||||
|
||||
|
||||
/* Dword 0, rsvd: bit26, bit28 */
|
||||
#define GET_TX_DESC_OWN_8710B(__pTxDesc)\
|
||||
LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
|
||||
#define SET_TX_DESC_OFFSET_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
|
||||
#define SET_TX_DESC_BMC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
|
||||
#define SET_TX_DESC_HTC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
|
||||
#define SET_TX_DESC_AMSDU_PAD_EN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
|
||||
#define SET_TX_DESC_NO_ACM_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
|
||||
#define SET_TX_DESC_GF_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_DESC_MACID_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
|
||||
#define SET_TX_DESC_QUEUE_SEL_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
|
||||
#define SET_TX_DESC_PIFS_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
|
||||
#define SET_TX_DESC_RATE_ID_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
|
||||
#define SET_TX_DESC_SEC_TYPE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
|
||||
#define SET_TX_DESC_MORE_DATA_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
|
||||
|
||||
/* Dword 2 remove P_AID, G_ID field*/
|
||||
#define SET_TX_DESC_CCA_RTS_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
|
||||
#define SET_TX_DESC_AGG_ENABLE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RDG_ENABLE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
|
||||
#define SET_TX_DESC_NULL0_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
|
||||
#define SET_TX_DESC_NULL1_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
|
||||
#define SET_TX_DESC_BK_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MORE_FRAG_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
|
||||
#define SET_TX_DESC_RAW_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
|
||||
#define SET_TX_DESC_CCX_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
|
||||
#define SET_TX_DESC_BT_INT_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
|
||||
#define SET_TX_DESC_FTM_EN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
|
||||
|
||||
/* Dword 3 */
|
||||
#define SET_TX_DESC_NAV_USE_HDR_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_SEL_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
|
||||
#define SET_TX_DESC_USE_RATE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_FB_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
|
||||
#define SET_TX_DESC_CTS2SELF_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_ENABLE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
|
||||
#define SET_TX_DESC_PORT_ID_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
|
||||
#define SET_TX_DESC_USE_MAX_LEN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
|
||||
#define SET_TX_DESC_TX_TRY_RATE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
|
||||
#define SET_TX_DESC_PCTS_EN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
|
||||
#define SET_TX_DESC_PCTS_MASK_IDX_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_DATA_SC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
|
||||
#define SET_TX_DESC_DATA_SHORT_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_BW_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_STBC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_STBC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_SHORT_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_SC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
|
||||
#define SET_TX_DESC_PATH_A_EN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
|
||||
#define SET_TX_DESC_TXPWR_OF_SET_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
|
||||
#define SET_TX_DESC_MBSSID_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
|
||||
#define SET_TX_DESC_RF_SEL_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
|
||||
|
||||
/* Dword 7 */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define SET_TX_DESC_TX_DESC_CHECKSUM_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define SET_TX_DESC_TX_TIMESTAMP_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
|
||||
#endif
|
||||
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
|
||||
|
||||
/* Dword 8 */
|
||||
#define SET_TX_DESC_RTS_RC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
|
||||
#define SET_TX_DESC_BAR_RC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_RC_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_EN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
|
||||
#define SET_TX_DESC_NEXTHEADPAGE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
|
||||
#define SET_TX_DESC_TAILPAGE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_PADDING_LEN_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
|
||||
#define SET_TX_DESC_SEQ_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_8710B(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
|
||||
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN0_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN1_1_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
|
||||
#define SET_EARLYMODE_LEN1_2_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
|
||||
#define SET_EARLYMODE_LEN2_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN3_8710B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RTL8710B TX BUFFER DESC */
|
||||
/*-----------------------------------------------------------------*/
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
|
||||
#else
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */
|
||||
#endif
|
||||
/* ********************************************************* */
|
||||
|
||||
/* 64 bits -- 32 bits */
|
||||
/* ======= ======= */
|
||||
/* Dword 0 0 */
|
||||
#define SET_TX_BUFF_DESC_LEN_0_8710B(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
|
||||
#define SET_TX_BUFF_DESC_PSB_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
|
||||
#define SET_TX_BUFF_DESC_OWN_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
|
||||
/* Dword 1 1 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
|
||||
#define GET_TX_BUFF_DESC_ADDR_LOW_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
|
||||
/* Dword 2 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
|
||||
#else
|
||||
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8710B(__pTxDesc) 0
|
||||
#endif
|
||||
/* Dword 3 NA */
|
||||
/* RESERVED 0 */
|
||||
/* Dword 4 2 */
|
||||
#define SET_TX_BUFF_DESC_LEN_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 5 3 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 6 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 7 NA */
|
||||
/*RESERVED 0 */
|
||||
/* Dword 8 4 */
|
||||
#define SET_TX_BUFF_DESC_LEN_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 9 5 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 10 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 11 NA */
|
||||
/*RESERVED 0 */
|
||||
/* Dword 12 6 */
|
||||
#define SET_TX_BUFF_DESC_LEN_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 13 7 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 14 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8710B(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 15 NA */
|
||||
/*RESERVED 0 */
|
||||
|
||||
|
||||
#endif
|
||||
/* -----------------------------------------------------------
|
||||
*
|
||||
* Rate
|
||||
*
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC8710B_RATE1M 0x00
|
||||
#define DESC8710B_RATE2M 0x01
|
||||
#define DESC8710B_RATE5_5M 0x02
|
||||
#define DESC8710B_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC8710B_RATE6M 0x04
|
||||
#define DESC8710B_RATE9M 0x05
|
||||
#define DESC8710B_RATE12M 0x06
|
||||
#define DESC8710B_RATE18M 0x07
|
||||
#define DESC8710B_RATE24M 0x08
|
||||
#define DESC8710B_RATE36M 0x09
|
||||
#define DESC8710B_RATE48M 0x0a
|
||||
#define DESC8710B_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC8710B_RATEMCS0 0x0c
|
||||
#define DESC8710B_RATEMCS1 0x0d
|
||||
#define DESC8710B_RATEMCS2 0x0e
|
||||
#define DESC8710B_RATEMCS3 0x0f
|
||||
#define DESC8710B_RATEMCS4 0x10
|
||||
#define DESC8710B_RATEMCS5 0x11
|
||||
#define DESC8710B_RATEMCS6 0x12
|
||||
#define DESC8710B_RATEMCS7 0x13
|
||||
#define DESC8710B_RATEMCS8 0x14
|
||||
#define DESC8710B_RATEMCS9 0x15
|
||||
#define DESC8710B_RATEMCS10 0x16
|
||||
#define DESC8710B_RATEMCS11 0x17
|
||||
#define DESC8710B_RATEMCS12 0x18
|
||||
#define DESC8710B_RATEMCS13 0x19
|
||||
#define DESC8710B_RATEMCS14 0x1a
|
||||
#define DESC8710B_RATEMCS15 0x1b
|
||||
#define DESC8710B_RATEVHTSS1MCS0 0x2c
|
||||
#define DESC8710B_RATEVHTSS1MCS1 0x2d
|
||||
#define DESC8710B_RATEVHTSS1MCS2 0x2e
|
||||
#define DESC8710B_RATEVHTSS1MCS3 0x2f
|
||||
#define DESC8710B_RATEVHTSS1MCS4 0x30
|
||||
#define DESC8710B_RATEVHTSS1MCS5 0x31
|
||||
#define DESC8710B_RATEVHTSS1MCS6 0x32
|
||||
#define DESC8710B_RATEVHTSS1MCS7 0x33
|
||||
#define DESC8710B_RATEVHTSS1MCS8 0x34
|
||||
#define DESC8710B_RATEVHTSS1MCS9 0x35
|
||||
#define DESC8710B_RATEVHTSS2MCS0 0x36
|
||||
#define DESC8710B_RATEVHTSS2MCS1 0x37
|
||||
#define DESC8710B_RATEVHTSS2MCS2 0x38
|
||||
#define DESC8710B_RATEVHTSS2MCS3 0x39
|
||||
#define DESC8710B_RATEVHTSS2MCS4 0x3a
|
||||
#define DESC8710B_RATEVHTSS2MCS5 0x3b
|
||||
#define DESC8710B_RATEVHTSS2MCS6 0x3c
|
||||
#define DESC8710B_RATEVHTSS2MCS7 0x3d
|
||||
#define DESC8710B_RATEVHTSS2MCS8 0x3e
|
||||
#define DESC8710B_RATEVHTSS2MCS9 0x3f
|
||||
|
||||
|
||||
#define RX_HAL_IS_CCK_RATE_8710B(pDesc)\
|
||||
(GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE1M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE2M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE5_5M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8710B(pDesc) == DESC8710B_RATE11M)
|
||||
|
||||
#ifdef CONFIG_TRX_BD_ARCH
|
||||
struct tx_desc;
|
||||
#endif
|
||||
|
||||
void rtl8710b_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
void rtl8710b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
|
||||
void rtl8710b_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8710b_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8710b_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8710b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8710bs_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8710bs_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8710bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8710bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
s32 rtl8710bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8710bs_xmit_buf_handler(PADAPTER padapter);
|
||||
thread_return rtl8710bs_xmit_thread(thread_context context);
|
||||
#define hal_xmit_handler rtl8710bs_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8710bu_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8710bu_xmit_buf_handler
|
||||
s32 rtl8710bu_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8710bu_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8710bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8710bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8710bu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8710bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8710bu_xmit_tasklet(void *priv);
|
||||
s32 rtl8710bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8710be_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8710be_free_xmit_priv(PADAPTER padapter);
|
||||
struct xmit_buf *rtl8710be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
void rtl8710be_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8710be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8710be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
s32 rtl8710be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8710be_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
u8 BWMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
u8 SCMapping_8710B(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_CMD_H__
|
||||
#define __RTL8723B_CMD_H__
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
enum h2c_cmd_8723B {
|
||||
/* Common Class: 000 */
|
||||
H2C_8723B_RSVD_PAGE = 0x00,
|
||||
H2C_8723B_MEDIA_STATUS_RPT = 0x01,
|
||||
H2C_8723B_SCAN_ENABLE = 0x02,
|
||||
H2C_8723B_KEEP_ALIVE = 0x03,
|
||||
H2C_8723B_DISCON_DECISION = 0x04,
|
||||
H2C_8723B_PSD_OFFLOAD = 0x05,
|
||||
H2C_8723B_AP_OFFLOAD = 0x08,
|
||||
H2C_8723B_BCN_RSVDPAGE = 0x09,
|
||||
H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
|
||||
H2C_8723B_FCS_RSVDPAGE = 0x10,
|
||||
H2C_8723B_FCS_INFO = 0x11,
|
||||
H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
|
||||
|
||||
/* PoweSave Class: 001 */
|
||||
H2C_8723B_SET_PWR_MODE = 0x20,
|
||||
H2C_8723B_PS_TUNING_PARA = 0x21,
|
||||
H2C_8723B_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8723B_P2P_LPS_PARAM = 0x23,
|
||||
H2C_8723B_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8723B_PS_SCAN_ENABLE = 0x25,
|
||||
H2C_8723B_SAP_PS_ = 0x26,
|
||||
H2C_8723B_INACTIVE_PS_ = 0x27, /* Inactive_PS */
|
||||
H2C_8723B_FWLPS_IN_IPS_ = 0x28,
|
||||
|
||||
/* Dynamic Mechanism Class: 010 */
|
||||
H2C_8723B_MACID_CFG = 0x40,
|
||||
H2C_8723B_TXBF = 0x41,
|
||||
H2C_8723B_RSSI_SETTING = 0x42,
|
||||
H2C_8723B_AP_REQ_TXRPT = 0x43,
|
||||
H2C_8723B_INIT_RATE_COLLECT = 0x44,
|
||||
H2C_8723B_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
/* BT Class: 011 */
|
||||
H2C_8723B_B_TYPE_TDMA = 0x60,
|
||||
H2C_8723B_BT_INFO = 0x61,
|
||||
H2C_8723B_FORCE_BT_TXPWR = 0x62,
|
||||
H2C_8723B_BT_IGNORE_WLANACT = 0x63,
|
||||
H2C_8723B_DAC_SWING_VALUE = 0x64,
|
||||
H2C_8723B_ANT_SEL_RSV = 0x65,
|
||||
H2C_8723B_WL_OPMODE = 0x66,
|
||||
H2C_8723B_BT_MP_OPER = 0x67,
|
||||
H2C_8723B_BT_CONTROL = 0x68,
|
||||
H2C_8723B_BT_WIFI_CTRL = 0x69,
|
||||
H2C_8723B_BT_FW_PATCH = 0x6A,
|
||||
H2C_8723B_BT_WLAN_CALIBRATION = 0x6D,
|
||||
|
||||
/* WOWLAN Class: 100 */
|
||||
H2C_8723B_WOWLAN = 0x80,
|
||||
H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8723B_AOAC_RSVD_PAGE = 0x83,
|
||||
H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
|
||||
H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
|
||||
H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
|
||||
H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
|
||||
H2C_8723B_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
|
||||
H2C_8723B_P2P_OFFLOAD = 0x8B,
|
||||
|
||||
H2C_8723B_RESET_TSF = 0xC0,
|
||||
H2C_8723B_MAXID,
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
|
||||
* ---------------------------------------------------------------------------------------------------------
|
||||
* _RSVDPAGE_LOC_CMD_0x00 */
|
||||
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/* _KEEP_ALIVE_CMD_0x03 */
|
||||
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _DISCONNECT_DECISION_CMD_0x04 */
|
||||
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
|
||||
/* _PWR_MOD_CMD_0x20 */
|
||||
#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _PS_TUNE_PARAM_CMD_0x21 */
|
||||
#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
|
||||
#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _MACID_CFG_CMD_0x40 */
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
|
||||
|
||||
/* _RSSI_SETTING_CMD_0x42 */
|
||||
#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
|
||||
#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _AP_REQ_TXRPT_CMD_0x43 */
|
||||
#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_TXPWR_CMD_0x62 */
|
||||
#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_MP_OPER_CMD_0x67 */
|
||||
#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
|
||||
/* _BT_FW_PATCH_0x6A */
|
||||
#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ------------------------------------------- Structure --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- Function Statement --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/* host message to firmware cmd */
|
||||
void rtl8723b_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8723b_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
|
||||
void rtl8723b_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
|
||||
/* s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
|
||||
void rtl8723b_set_FwPsTuneParam_cmd(PADAPTER padapter);
|
||||
void rtl8723b_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
|
||||
void rtl8723b_download_rsvd_page(PADAPTER padapter, u8 mstatus);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8723b_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8723b_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
void rtl8723b_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8723b_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
|
||||
|
||||
s32 FillH2CCmd8723B(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
u8 GetTxBufferRsvdPageNum8723B(_adapter *padapter, bool wowlan);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_DM_H__
|
||||
#define __RTL8723B_DM_H__
|
||||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for 8723B dynamic mechanism only
|
||||
*
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* structure and define
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* function prototype
|
||||
* ************************************************************ */
|
||||
|
||||
void rtl8723b_init_dm_priv(PADAPTER padapter);
|
||||
void rtl8723b_deinit_dm_priv(PADAPTER padapter);
|
||||
|
||||
void rtl8723b_InitHalDm(PADAPTER padapter);
|
||||
void rtl8723b_HalDmWatchDog(PADAPTER padapter);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,274 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_HAL_H__
|
||||
#define __RTL8723B_HAL_H__
|
||||
|
||||
#include "hal_data.h"
|
||||
|
||||
#include "rtl8723b_spec.h"
|
||||
#include "rtl8723b_rf.h"
|
||||
#include "rtl8723b_dm.h"
|
||||
#include "rtl8723b_recv.h"
|
||||
#include "rtl8723b_xmit.h"
|
||||
#include "rtl8723b_cmd.h"
|
||||
#include "rtl8723b_led.h"
|
||||
#include "Hal8723BPwrSeq.h"
|
||||
#include "Hal8723BPhyReg.h"
|
||||
#include "Hal8723BPhyCfg.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8723b_sreset.h"
|
||||
#endif
|
||||
|
||||
#define FW_8723B_SIZE 0x8000
|
||||
#define FW_8723B_START_ADDRESS 0x1000
|
||||
#define FW_8723B_END_ADDRESS 0x1FFF /* 0x5FFF */
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8723B(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x5300)
|
||||
|
||||
typedef struct _RT_FIRMWARE {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_8723B_SIZE];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8723B, *PRT_FIRMWARE_8723B;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
typedef struct _RT_8723B_FIRMWARE_HDR {
|
||||
/* 8-byte alinment required */
|
||||
|
||||
/* --- LONG WORD 0 ---- */
|
||||
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
u8 Category; /* AP/NIC and USB/PCI */
|
||||
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
u16 Version; /* FW Version */
|
||||
u16 Subversion; /* FW Subversion, default 0x00 */
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
u8 Month; /* Release time Month field */
|
||||
u8 Date; /* Release time Date field */
|
||||
u8 Hour; /* Release time Hour field */
|
||||
u8 Minute; /* Release time Minute field */
|
||||
u16 RamCodeSize; /* The size of RAM code */
|
||||
u16 Rsvd2;
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
u32 SvnIdx; /* The SVN entry index */
|
||||
u32 Rsvd3;
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
} RT_8723B_FIRMWARE_HDR, *PRT_8723B_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8723B 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8723B 0x02
|
||||
|
||||
/* for 8723B
|
||||
* TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
|
||||
#define PAGE_SIZE_TX_8723B 128
|
||||
#define PAGE_SIZE_RX_8723B 8
|
||||
|
||||
#define TX_DMA_SIZE_8723B 0x8000 /* 32K(TX) */
|
||||
#define RX_DMA_SIZE_8723B 0x4000 /* 16K(RX) */
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8723B 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8723B 0x80 /* 128B, reserved for tx report */
|
||||
#endif
|
||||
#define RX_DMA_BOUNDARY_8723B (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B - 1)
|
||||
|
||||
|
||||
/* Note: We will divide number of page equally for each queue other than public queue! */
|
||||
|
||||
/* For General Reserved Page Number(Beacon Queue is reserved page)
|
||||
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723B
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
|
||||
#define BCNQ_PAGE_NUM_8723B (MAX_BEACON_LEN / PAGE_SIZE_TX_8723B + 6) /*0x08*/
|
||||
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6
|
||||
* NS offload: 2 NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8723B 0x0b
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8723B 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#undef WOWLAN_PAGE_NUM_8723B
|
||||
#define WOWLAN_PAGE_NUM_8723B 0x15
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_WOWLAN
|
||||
#define AP_WOWLAN_PAGE_NUM_8723B 0x02
|
||||
#endif
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER_8723B (0xFF - BCNQ_PAGE_NUM_8723B - WOWLAN_PAGE_NUM_8723B)
|
||||
#define TX_PAGE_BOUNDARY_8723B (TX_TOTAL_PAGE_NUMBER_8723B + 1)
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B TX_TOTAL_PAGE_NUMBER_8723B
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723B (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723B + 1)
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723B */
|
||||
#define NORMAL_PAGE_NUM_HPQ_8723B 0x0C
|
||||
#define NORMAL_PAGE_NUM_LPQ_8723B 0x02
|
||||
#define NORMAL_PAGE_NUM_NPQ_8723B 0x02
|
||||
#define NORMAL_PAGE_NUM_EPQ_8723B 0x04
|
||||
|
||||
/* Note: For Normal Chip Setting, modify later */
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8723B 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8723B 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8723B 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_EPQ_8723B 0x00
|
||||
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
#define EFUSE_OOB_PROTECT_BYTES 15
|
||||
|
||||
#define HAL_EFUSE_MEMORY
|
||||
|
||||
#define HWSET_MAX_SIZE_8723B 512
|
||||
#define EFUSE_REAL_CONTENT_LEN_8723B 512
|
||||
#define EFUSE_MAP_LEN_8723B 512
|
||||
#define EFUSE_MAX_SECTION_8723B 64
|
||||
|
||||
#define EFUSE_IC_ID_OFFSET 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8723B)
|
||||
|
||||
#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */
|
||||
#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */
|
||||
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
|
||||
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
typedef enum tag_Package_Definition {
|
||||
PACKAGE_DEFAULT,
|
||||
PACKAGE_QFN68,
|
||||
PACKAGE_TFBGA90,
|
||||
PACKAGE_TFBGA80,
|
||||
PACKAGE_TFBGA79
|
||||
} PACKAGE_TYPE_E;
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
/* rtl8723a_hal_init.c */
|
||||
s32 rtl8723b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
|
||||
void rtl8723b_FirmwareSelfReset(PADAPTER padapter);
|
||||
void rtl8723b_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
void rtl8723b_InitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723b_DeinitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723b_CheckAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723b_init_default_value(PADAPTER padapter);
|
||||
|
||||
s32 rtl8723b_InitLLTTable(PADAPTER padapter);
|
||||
|
||||
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
|
||||
s32 CardDisableWithoutHWSM(PADAPTER padapter);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8723B(PADAPTER padapter);
|
||||
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_EfuseParseTxPowerInfo_8723B(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBTCoexistInfo_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseEEPROMVer_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseChnlPlan_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseAntennaDiversity_8723B(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8723B(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseThermalMeter_8723B(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParsePackageType_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseVoltage_8723B(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBoardType_8723B(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
|
||||
void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8723b(_adapter *adapter);
|
||||
u8 SetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8723B(PADAPTER padapter, u8 variable, u8 *val);
|
||||
u8 SetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
u8 GetHalDefVar8723B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
|
||||
/* register */
|
||||
void rtl8723b_InitBeaconParameters(PADAPTER padapter);
|
||||
void rtl8723b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
|
||||
void _InitBurstPktLen_8723BS(PADAPTER Adapter);
|
||||
void _8051Reset8723(PADAPTER padapter);
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
void rtl8723b_start_thread(_adapter *padapter);
|
||||
void rtl8723b_stop_thread(_adapter *padapter);
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void rtl8723bs_init_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8723bs_free_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8723bs_cancle_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8723bs_hal_check_bt_hang(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
|
||||
#endif
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
|
||||
#endif
|
||||
void CCX_FwC2HTxRpt_8723b(PADAPTER padapter, u8 *pdata, u8 len);
|
||||
|
||||
u8 MRateToHwRate8723B(u8 rate);
|
||||
u8 HwRateToMRate8723B(u8 rate);
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
BOOLEAN InterruptRecognized8723BE(PADAPTER Adapter);
|
||||
void UpdateInterruptMask8723BE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_API
|
||||
int rtl8723b_GpioFuncCheck(PADAPTER adapter, u8 gpio_num);
|
||||
void rtl8723b_GpioMultiFuncReset(PADAPTER adapter, u8 gpio_num);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_LED_H__
|
||||
#define __RTL8723B_LED_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8723bu_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723bu_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8723bs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_GSPI_HCI
|
||||
void rtl8723bs_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723bs_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8723be_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723be_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif/*CONFIG_RTW_SW_LED*/
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_RECV_H__
|
||||
#define __RTL8723B_RECV_H__
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
#ifdef CONFIG_PLATFORM_MSTAR
|
||||
#define MAX_RECVBUF_SZ (8192) /* 8K */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
|
||||
#endif
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
|
||||
/* #define MAX_RECVBUF_SZ (9100) */
|
||||
/* #else */
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K
|
||||
* #endif */
|
||||
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
|
||||
|
||||
#endif
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#ifndef CONFIG_SDIO_RX_COPY
|
||||
#undef MAX_RECVBUF_SZ
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8723B - RX_DMA_RESERVED_SIZE_8723B)
|
||||
#endif /* !CONFIG_SDIO_RX_COPY */
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8723bs_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8723bs_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
int rtl8723bu_init_recv_priv(_adapter *padapter);
|
||||
void rtl8723bu_free_recv_priv(_adapter *padapter);
|
||||
void rtl8723bu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8723be_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8723be_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8723b_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8723B_RECV_H__ */
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_RF_H__
|
||||
#define __RTL8723B_RF_H__
|
||||
|
||||
int PHY_RF6052_Config8723B(PADAPTER Adapter);
|
||||
|
||||
void
|
||||
PHY_RF6052SetBandwidth8723B(
|
||||
PADAPTER Adapter,
|
||||
enum channel_width Bandwidth);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,280 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_SPEC_H__
|
||||
#define __RTL8723B_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
|
||||
#define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */
|
||||
#define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038
|
||||
#define REG_HSISR_8723B 0x005c
|
||||
#define REG_PAD_CTRL1_8723B 0x0064
|
||||
#define REG_AFE_CTRL_4_8723B 0x0078
|
||||
#define REG_HMEBOX_DBG_0_8723B 0x0088
|
||||
#define REG_HMEBOX_DBG_1_8723B 0x008A
|
||||
#define REG_HMEBOX_DBG_2_8723B 0x008C
|
||||
#define REG_HMEBOX_DBG_3_8723B 0x008E
|
||||
#define REG_HIMR0_8723B 0x00B0
|
||||
#define REG_HISR0_8723B 0x00B4
|
||||
#define REG_HIMR1_8723B 0x00B8
|
||||
#define REG_HISR1_8723B 0x00BC
|
||||
#define REG_PMC_DBG_CTRL2_8723B 0x00CC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_C2HEVT_CMD_ID_8723B 0x01A0
|
||||
#define REG_C2HEVT_CMD_LEN_8723B 0x01AE
|
||||
#define REG_WOWLAN_WAKE_REASON 0x01C7
|
||||
#define REG_WOWLAN_GTK_DBG1 0x630
|
||||
#define REG_WOWLAN_GTK_DBG2 0x634
|
||||
|
||||
#define REG_HMEBOX_EXT0_8723B 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8723B 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8723B 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8723B 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
|
||||
#define REG_RXDMA_MODE_CTRL_8723B 0x0290
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8723B 0x0300
|
||||
#define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */
|
||||
#define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */
|
||||
#define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
|
||||
#define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */
|
||||
#define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */
|
||||
#define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
|
||||
#define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
|
||||
#define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */
|
||||
#define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */
|
||||
#define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */
|
||||
#define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */
|
||||
#define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */
|
||||
#define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424
|
||||
#define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x0484
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x0488
|
||||
#endif
|
||||
#define REG_AMPDU_BURST_MODE_8723B 0x04BC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SECONDARY_CCA_CTRL_8723B 0x0577
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
|
||||
/* ************************************************************
|
||||
* SDIO Bus Specification
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO CMD Address Mapping
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* I/O bus domain (Host)
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO register
|
||||
* ----------------------------------------------------- */
|
||||
#define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */
|
||||
|
||||
|
||||
/* ****************************************************************************
|
||||
* 8723 Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
/* 2 HSISR
|
||||
* interrupt mask which needs to clear */
|
||||
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
|
||||
HSISR_SPS_OCP_INT |\
|
||||
HSISR_RON_INT |\
|
||||
HSISR_PDNINT |\
|
||||
HSISR_GPIO9_INT)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#undef IS_E_CUT
|
||||
#define IS_E_CUT(version) FALSE
|
||||
#undef IS_F_CUT
|
||||
#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define BIT_USB_RXDMA_AGG_EN BIT(31)
|
||||
#define RXDMA_AGG_MODE_EN BIT(1)
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RXPKT_RELEASE_POLL BIT(16)
|
||||
#define RXDMA_IDLE BIT(17)
|
||||
#define RW_RELEASE_EN BIT(18)
|
||||
#endif
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8723B REG_CCK_CHECK (offset 0x454)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define BIT_BCN_PORT_SEL BIT(5)
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
|
||||
#ifdef CONFIG_RTL8723B
|
||||
#define EEPROM_RF_GAIN_OFFSET 0xC1
|
||||
#endif
|
||||
|
||||
#define EEPROM_RF_GAIN_VAL 0x1F6
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8195 IMR/ISR bits (offset 0xB0, 8bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define IMR_DISABLED_8723B 0
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8723B BIT(31) /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8723B BIT(30) /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8723B BIT(29) /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8723B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
|
||||
#define IMR_GTINT3_8723B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8723B BIT(26) /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8723B BIT(25) /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8723B BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8723B BIT(20) /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8723B BIT(16) /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8723B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8723B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8723B BIT(12) /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8723B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
|
||||
#define IMR_CPWM2_8723B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_CPWM_8723B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8723B BIT(7) /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8723B BIT(6) /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8723B BIT(5) /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8723B BIT(4) /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8723B BIT(3) /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8723B BIT(2) /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8723B BIT(1) /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8723B BIT(0) /* Receive DMA OK */
|
||||
|
||||
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
||||
#define IMR_BCNDMAINT7_8723B BIT(27) /* Beacon DMA Interrupt 7 */
|
||||
#define IMR_BCNDMAINT6_8723B BIT(26) /* Beacon DMA Interrupt 6 */
|
||||
#define IMR_BCNDMAINT5_8723B BIT(25) /* Beacon DMA Interrupt 5 */
|
||||
#define IMR_BCNDMAINT4_8723B BIT(24) /* Beacon DMA Interrupt 4 */
|
||||
#define IMR_BCNDMAINT3_8723B BIT(23) /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2_8723B BIT(22) /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1_8723B BIT(21) /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8723B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */
|
||||
#define IMR_BCNDOK6_8723B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */
|
||||
#define IMR_BCNDOK5_8723B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */
|
||||
#define IMR_BCNDOK4_8723B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */
|
||||
#define IMR_BCNDOK3_8723B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */
|
||||
#define IMR_BCNDOK2_8723B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */
|
||||
#define IMR_BCNDOK1_8723B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */
|
||||
#define IMR_ATIMEND_E_8723B BIT(13) /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8723B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR_8723B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8723B BIT(9) /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8723B BIT(8) /* Receive FIFO Overflow */
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* #define IMR_RX_MASK (IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B)
|
||||
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B)
|
||||
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B)
|
||||
#endif
|
||||
|
||||
#endif /* __RTL8723B_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8723B_SRESET_H_
|
||||
#define _RTL8723B_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8723b_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8723b_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723B_XMIT_H__
|
||||
#define __RTL8723B_XMIT_H__
|
||||
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
|
||||
#ifndef __INC_HAL8723BDESC_H
|
||||
#define __INC_HAL8723BDESC_H
|
||||
|
||||
#define RX_STATUS_DESC_SIZE_8723B 24
|
||||
#define RX_DRV_INFO_SIZE_UNIT_8723B 8
|
||||
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
|
||||
#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
#endif
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
|
||||
#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
|
||||
#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
|
||||
#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
|
||||
|
||||
|
||||
/* Dword 0 */
|
||||
#define GET_TX_DESC_OWN_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
|
||||
#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
|
||||
#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
|
||||
#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
|
||||
#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
|
||||
#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
|
||||
#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
|
||||
#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
|
||||
#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
|
||||
#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
|
||||
#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
|
||||
#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
|
||||
#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
|
||||
#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
|
||||
|
||||
|
||||
/* Dword 2 */
|
||||
#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
|
||||
#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
|
||||
#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
|
||||
#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
|
||||
#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
|
||||
#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
|
||||
#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
|
||||
#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
|
||||
|
||||
|
||||
/* Dword 3 */
|
||||
#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
|
||||
#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
|
||||
#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
|
||||
#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
|
||||
#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
|
||||
#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
|
||||
#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
|
||||
#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
|
||||
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
|
||||
#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
|
||||
#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
|
||||
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
|
||||
#define SET_TX_DESC_MBSSID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
|
||||
#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
|
||||
|
||||
/* Dword 7 */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_USB_HCI)
|
||||
#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
|
||||
#endif
|
||||
|
||||
/* Dword 8 */
|
||||
#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
|
||||
|
||||
/* Dword 10 */
|
||||
#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
|
||||
#define GET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
|
||||
|
||||
/* Dword 11 */
|
||||
#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
|
||||
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
|
||||
#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
|
||||
#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
|
||||
|
||||
#endif
|
||||
/* -----------------------------------------------------------
|
||||
*
|
||||
* Rate
|
||||
*
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC8723B_RATE1M 0x00
|
||||
#define DESC8723B_RATE2M 0x01
|
||||
#define DESC8723B_RATE5_5M 0x02
|
||||
#define DESC8723B_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC8723B_RATE6M 0x04
|
||||
#define DESC8723B_RATE9M 0x05
|
||||
#define DESC8723B_RATE12M 0x06
|
||||
#define DESC8723B_RATE18M 0x07
|
||||
#define DESC8723B_RATE24M 0x08
|
||||
#define DESC8723B_RATE36M 0x09
|
||||
#define DESC8723B_RATE48M 0x0a
|
||||
#define DESC8723B_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC8723B_RATEMCS0 0x0c
|
||||
#define DESC8723B_RATEMCS1 0x0d
|
||||
#define DESC8723B_RATEMCS2 0x0e
|
||||
#define DESC8723B_RATEMCS3 0x0f
|
||||
#define DESC8723B_RATEMCS4 0x10
|
||||
#define DESC8723B_RATEMCS5 0x11
|
||||
#define DESC8723B_RATEMCS6 0x12
|
||||
#define DESC8723B_RATEMCS7 0x13
|
||||
#define DESC8723B_RATEMCS8 0x14
|
||||
#define DESC8723B_RATEMCS9 0x15
|
||||
#define DESC8723B_RATEMCS10 0x16
|
||||
#define DESC8723B_RATEMCS11 0x17
|
||||
#define DESC8723B_RATEMCS12 0x18
|
||||
#define DESC8723B_RATEMCS13 0x19
|
||||
#define DESC8723B_RATEMCS14 0x1a
|
||||
#define DESC8723B_RATEMCS15 0x1b
|
||||
#define DESC8723B_RATEVHTSS1MCS0 0x2c
|
||||
#define DESC8723B_RATEVHTSS1MCS1 0x2d
|
||||
#define DESC8723B_RATEVHTSS1MCS2 0x2e
|
||||
#define DESC8723B_RATEVHTSS1MCS3 0x2f
|
||||
#define DESC8723B_RATEVHTSS1MCS4 0x30
|
||||
#define DESC8723B_RATEVHTSS1MCS5 0x31
|
||||
#define DESC8723B_RATEVHTSS1MCS6 0x32
|
||||
#define DESC8723B_RATEVHTSS1MCS7 0x33
|
||||
#define DESC8723B_RATEVHTSS1MCS8 0x34
|
||||
#define DESC8723B_RATEVHTSS1MCS9 0x35
|
||||
#define DESC8723B_RATEVHTSS2MCS0 0x36
|
||||
#define DESC8723B_RATEVHTSS2MCS1 0x37
|
||||
#define DESC8723B_RATEVHTSS2MCS2 0x38
|
||||
#define DESC8723B_RATEVHTSS2MCS3 0x39
|
||||
#define DESC8723B_RATEVHTSS2MCS4 0x3a
|
||||
#define DESC8723B_RATEVHTSS2MCS5 0x3b
|
||||
#define DESC8723B_RATEVHTSS2MCS6 0x3c
|
||||
#define DESC8723B_RATEVHTSS2MCS7 0x3d
|
||||
#define DESC8723B_RATEVHTSS2MCS8 0x3e
|
||||
#define DESC8723B_RATEVHTSS2MCS9 0x3f
|
||||
|
||||
|
||||
#define RX_HAL_IS_CCK_RATE_8723B(pDesc)\
|
||||
(GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M)
|
||||
|
||||
|
||||
void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
|
||||
void rtl8723b_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8723bs_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8723bs_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8723bs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723bs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8723bs_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8723bs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723bs_xmit_buf_handler(PADAPTER padapter);
|
||||
thread_return rtl8723bs_xmit_thread(thread_context context);
|
||||
#define hal_xmit_handler rtl8723bs_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8723bu_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8723bu_xmit_buf_handler
|
||||
|
||||
|
||||
s32 rtl8723bu_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8723bu_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8723bu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723bu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8723bu_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8723bu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
/* s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); */
|
||||
void rtl8723bu_xmit_tasklet(void *priv);
|
||||
s32 rtl8723bu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8723be_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8723be_free_xmit_priv(PADAPTER padapter);
|
||||
struct xmit_buf *rtl8723be_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
void rtl8723be_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8723be_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723be_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8723be_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8723be_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8723be_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
u8 BWMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
u8 SCMapping_8723B(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_CMD_H__
|
||||
#define __RTL8723D_CMD_H__
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD DEFINITION ------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
enum h2c_cmd_8723D {
|
||||
/* Common Class: 000 */
|
||||
H2C_8723D_RSVD_PAGE = 0x00,
|
||||
H2C_8723D_MEDIA_STATUS_RPT = 0x01,
|
||||
H2C_8723D_SCAN_ENABLE = 0x02,
|
||||
H2C_8723D_KEEP_ALIVE = 0x03,
|
||||
H2C_8723D_DISCON_DECISION = 0x04,
|
||||
H2C_8723D_PSD_OFFLOAD = 0x05,
|
||||
H2C_8723D_AP_OFFLOAD = 0x08,
|
||||
H2C_8723D_BCN_RSVDPAGE = 0x09,
|
||||
H2C_8723D_PROBERSP_RSVDPAGE = 0x0A,
|
||||
H2C_8723D_FCS_RSVDPAGE = 0x10,
|
||||
H2C_8723D_FCS_INFO = 0x11,
|
||||
H2C_8723D_AP_WOW_GPIO_CTRL = 0x13,
|
||||
|
||||
/* PoweSave Class: 001 */
|
||||
H2C_8723D_SET_PWR_MODE = 0x20,
|
||||
H2C_8723D_PS_TUNING_PARA = 0x21,
|
||||
H2C_8723D_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8723D_P2P_LPS_PARAM = 0x23,
|
||||
H2C_8723D_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8723D_PS_SCAN_ENABLE = 0x25,
|
||||
H2C_8723D_SAP_PS_ = 0x26,
|
||||
H2C_8723D_INACTIVE_PS_ = 0x27, /* Inactive_PS */
|
||||
H2C_8723D_FWLPS_IN_IPS_ = 0x28,
|
||||
|
||||
/* Dynamic Mechanism Class: 010 */
|
||||
H2C_8723D_MACID_CFG = 0x40,
|
||||
H2C_8723D_TXBF = 0x41,
|
||||
H2C_8723D_RSSI_SETTING = 0x42,
|
||||
H2C_8723D_AP_REQ_TXRPT = 0x43,
|
||||
H2C_8723D_INIT_RATE_COLLECT = 0x44,
|
||||
H2C_8723D_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
/* BT Class: 011 */
|
||||
H2C_8723D_B_TYPE_TDMA = 0x60,
|
||||
H2C_8723D_BT_INFO = 0x61,
|
||||
H2C_8723D_FORCE_BT_TXPWR = 0x62,
|
||||
H2C_8723D_BT_IGNORE_WLANACT = 0x63,
|
||||
H2C_8723D_DAC_SWING_VALUE = 0x64,
|
||||
H2C_8723D_ANT_SEL_RSV = 0x65,
|
||||
H2C_8723D_WL_OPMODE = 0x66,
|
||||
H2C_8723D_BT_MP_OPER = 0x67,
|
||||
H2C_8723D_BT_CONTROL = 0x68,
|
||||
H2C_8723D_BT_WIFI_CTRL = 0x69,
|
||||
H2C_8723D_BT_FW_PATCH = 0x6A,
|
||||
H2C_8723D_BT_WLAN_CALIBRATION = 0x6D,
|
||||
|
||||
/* WOWLAN Class: 100 */
|
||||
H2C_8723D_WOWLAN = 0x80,
|
||||
H2C_8723D_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8723D_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8723D_AOAC_RSVD_PAGE = 0x83,
|
||||
H2C_8723D_AOAC_RSVD_PAGE2 = 0x84,
|
||||
H2C_8723D_D0_SCAN_OFFLOAD_CTRL = 0x85,
|
||||
H2C_8723D_D0_SCAN_OFFLOAD_INFO = 0x86,
|
||||
H2C_8723D_CHNL_SWITCH_OFFLOAD = 0x87,
|
||||
H2C_8723D_P2P_OFFLOAD_RSVD_PAGE = 0x8A,
|
||||
H2C_8723D_P2P_OFFLOAD = 0x8B,
|
||||
|
||||
H2C_8723D_RESET_TSF = 0xC0,
|
||||
H2C_8723D_MAXID,
|
||||
};
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- H2C CMD CONTENT --------------------------------------------------
|
||||
* ---------------------------------------------------------------------------------------------------------
|
||||
* _RSVDPAGE_LOC_CMD_0x00 */
|
||||
#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/* _PWR_MOD_CMD_0x20 */
|
||||
#define SET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8723D_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8723D_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_8723D_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _PS_TUNE_PARAM_CMD_0x21 */
|
||||
#define SET_8723D_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
|
||||
#define SET_8723D_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
|
||||
#define SET_8723D_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _MACID_CFG_CMD_0x40 */
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
|
||||
|
||||
/* _RSSI_SETTING_CMD_0x42 */
|
||||
#define SET_8723D_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
|
||||
#define SET_8723D_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
|
||||
/* _AP_REQ_TXRPT_CMD_0x43 */
|
||||
#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_TXPWR_CMD_0x62 */
|
||||
#define SET_8723D_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
|
||||
/* _FORCE_BT_MP_OPER_CMD_0x67 */
|
||||
#define SET_8723D_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
|
||||
|
||||
/* _BT_FW_PATCH_0x6A */
|
||||
#define SET_8723D_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_8723D_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ------------------------------------------- Structure --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------------------------------------------------
|
||||
* ---------------------------------- Function Statement --------------------------------------------------
|
||||
* --------------------------------------------------------------------------------------------------------- */
|
||||
|
||||
/* host message to firmware cmd */
|
||||
void rtl8723d_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
|
||||
void rtl8723d_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
|
||||
/* s32 rtl8723d_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); */
|
||||
void rtl8723d_set_FwPsTuneParam_cmd(PADAPTER padapter);
|
||||
void rtl8723d_download_rsvd_page(PADAPTER padapter, u8 mstatus);
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8723d_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P
|
||||
void rtl8723d_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
#ifdef CONFIG_P2P_WOWLAN
|
||||
void rtl8723d_set_p2p_wowlan_offload_cmd(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
s32 FillH2CCmd8723D(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
u8 GetTxBufferRsvdPageNum8723D(_adapter *padapter, bool wowlan);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_DM_H__
|
||||
#define __RTL8723D_DM_H__
|
||||
/* ************************************************************
|
||||
* Description:
|
||||
*
|
||||
* This file is for 8723D dynamic mechanism only
|
||||
*
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* structure and define
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
* function prototype
|
||||
* ************************************************************ */
|
||||
|
||||
void rtl8723d_init_dm_priv(PADAPTER padapter);
|
||||
void rtl8723d_deinit_dm_priv(PADAPTER padapter);
|
||||
|
||||
void rtl8723d_InitHalDm(PADAPTER padapter);
|
||||
void rtl8723d_HalDmWatchDog(PADAPTER padapter);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,303 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_HAL_H__
|
||||
#define __RTL8723D_HAL_H__
|
||||
|
||||
#include "hal_data.h"
|
||||
|
||||
#include "rtl8723d_spec.h"
|
||||
#include "rtl8723d_rf.h"
|
||||
#include "rtl8723d_dm.h"
|
||||
#include "rtl8723d_recv.h"
|
||||
#include "rtl8723d_xmit.h"
|
||||
#include "rtl8723d_cmd.h"
|
||||
#include "rtl8723d_led.h"
|
||||
#include "Hal8723DPwrSeq.h"
|
||||
#include "Hal8723DPhyReg.h"
|
||||
#include "Hal8723DPhyCfg.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8723d_sreset.h"
|
||||
#endif
|
||||
#ifdef CONFIG_LPS_POFF
|
||||
#include "rtl8723d_lps_poff.h"
|
||||
#endif
|
||||
|
||||
#define FW_8723D_SIZE 0x8000
|
||||
#define FW_8723D_START_ADDRESS 0x1000
|
||||
#define FW_8723D_END_ADDRESS 0x1FFF /* 0x5FFF */
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8723D(_pFwHdr)\
|
||||
((le16_to_cpu(_pFwHdr->Signature) & 0xFFF0) == 0x23D0)
|
||||
|
||||
typedef struct _RT_FIRMWARE {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_8723D_SIZE];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8723D, *PRT_FIRMWARE_8723D;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
typedef struct _RT_8723D_FIRMWARE_HDR {
|
||||
/* 8-byte alinment required */
|
||||
|
||||
/* --- LONG WORD 0 ---- */
|
||||
u16 Signature; /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
u8 Category; /* AP/NIC and USB/PCI */
|
||||
u8 Function; /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
u16 Version; /* FW Version */
|
||||
u16 Subversion; /* FW Subversion, default 0x00 */
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
u8 Month; /* Release time Month field */
|
||||
u8 Date; /* Release time Date field */
|
||||
u8 Hour; /* Release time Hour field */
|
||||
u8 Minute; /* Release time Minute field */
|
||||
u16 RamCodeSize; /* The size of RAM code */
|
||||
u16 Rsvd2;
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
u32 SvnIdx; /* The SVN entry index */
|
||||
u32 Rsvd3;
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
} RT_8723D_FIRMWARE_HDR, *PRT_8723D_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8723D 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8723D 0x02
|
||||
|
||||
/* for 8723D
|
||||
* TX 32K, RX 16K, Page size 128B for TX, 8B for RX */
|
||||
#define PAGE_SIZE_TX_8723D 128
|
||||
#define PAGE_SIZE_RX_8723D 8
|
||||
|
||||
#define TX_DMA_SIZE_8723D 0x8000 /* 32K(TX) */
|
||||
#define RX_DMA_SIZE_8723D 0x4000 /* 16K(RX) */
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8723D 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8723D 0x80 /* 128B, reserved for tx report */
|
||||
#endif
|
||||
#define RX_DMA_BOUNDARY_8723D\
|
||||
(RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D - 1)
|
||||
|
||||
|
||||
/* Note: We will divide number of page equally for each queue other than public queue! */
|
||||
|
||||
/* For General Reserved Page Number(Beacon Queue is reserved page)
|
||||
* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8723D
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
|
||||
|
||||
#define BCNQ_PAGE_NUM_8723D (MAX_BEACON_LEN/PAGE_SIZE_TX_8723D + 6) /*0x08*/
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt 1, PNO: 6
|
||||
* NS offload: 2 NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8723D 0x0b
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8723D 0x00
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PNO_SUPPORT
|
||||
#undef WOWLAN_PAGE_NUM_8723D
|
||||
#define WOWLAN_PAGE_NUM_8723D 0x15
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AP_WOWLAN
|
||||
#define AP_WOWLAN_PAGE_NUM_8723D 0x02
|
||||
#endif
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER_8723D\
|
||||
(0xFF - BCNQ_PAGE_NUM_8723D - WOWLAN_PAGE_NUM_8723D)
|
||||
#define TX_PAGE_BOUNDARY_8723D (TX_TOTAL_PAGE_NUMBER_8723D + 1)
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D TX_TOTAL_PAGE_NUMBER_8723D
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8723D\
|
||||
(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8723D + 1)
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8723D */
|
||||
#define NORMAL_PAGE_NUM_HPQ_8723D 0x0C
|
||||
#define NORMAL_PAGE_NUM_LPQ_8723D 0x02
|
||||
#define NORMAL_PAGE_NUM_NPQ_8723D 0x02
|
||||
#define NORMAL_PAGE_NUM_EPQ_8723D 0x04
|
||||
|
||||
/* Note: For Normal Chip Setting, modify later */
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8723D 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8723D 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8723D 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_EPQ_8723D 0x00
|
||||
|
||||
|
||||
#include "HalVerDef.h"
|
||||
#include "hal_com.h"
|
||||
|
||||
#define EFUSE_OOB_PROTECT_BYTES (96 + 1)
|
||||
|
||||
#define HAL_EFUSE_MEMORY
|
||||
#define HWSET_MAX_SIZE_8723D 512
|
||||
#define EFUSE_REAL_CONTENT_LEN_8723D 512
|
||||
#define EFUSE_MAP_LEN_8723D 512
|
||||
#define EFUSE_MAX_SECTION_8723D 64
|
||||
|
||||
/* For some inferiority IC purpose. added by Roger, 2009.09.02.*/
|
||||
#define EFUSE_IC_ID_OFFSET 506
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8723D)
|
||||
|
||||
#define EFUSE_ACCESS_ON 0x69
|
||||
#define EFUSE_ACCESS_OFF 0x00
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define BANK_NUM 1
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN \
|
||||
(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
|
||||
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8)
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
typedef enum tag_Package_Definition {
|
||||
PACKAGE_DEFAULT,
|
||||
PACKAGE_QFN68,
|
||||
PACKAGE_TFBGA90,
|
||||
PACKAGE_TFBGA80,
|
||||
PACKAGE_TFBGA79
|
||||
} PACKAGE_TYPE_E;
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) \
|
||||
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) \
|
||||
(GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
#ifdef CONFIG_FILE_FWIMG
|
||||
extern char *rtw_fw_file_path;
|
||||
extern char *rtw_fw_wow_file_path;
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
extern char *rtw_fw_mp_bt_file_path;
|
||||
#endif /* CONFIG_MP_INCLUDED */
|
||||
#endif /* CONFIG_FILE_FWIMG */
|
||||
|
||||
/* rtl8723d_hal_init.c */
|
||||
s32 rtl8723d_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw);
|
||||
void rtl8723d_FirmwareSelfReset(PADAPTER padapter);
|
||||
void rtl8723d_InitializeFirmwareVars(PADAPTER padapter);
|
||||
|
||||
void rtl8723d_InitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723d_DeinitAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723d_CheckAntenna_Selection(PADAPTER padapter);
|
||||
void rtl8723d_init_default_value(PADAPTER padapter);
|
||||
|
||||
s32 rtl8723d_InitLLTTable(PADAPTER padapter);
|
||||
|
||||
s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
|
||||
s32 CardDisableWithoutHWSM(PADAPTER padapter);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8723D(PADAPTER padapter);
|
||||
void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
|
||||
void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_EfuseParseTxPowerInfo_8723D(PADAPTER padapter,
|
||||
u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBTCoexistInfo_8723D(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseEEPROMVer_8723D(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseChnlPlan_8723D(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseCustomerID_8723D(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseAntennaDiversity_8723D(PADAPTER padapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8723D(PADAPTER pAdapter,
|
||||
u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseThermalMeter_8723D(PADAPTER padapter,
|
||||
u8 *hwinfo, u8 AutoLoadFail);
|
||||
void Hal_EfuseParseVoltage_8723D(PADAPTER pAdapter,
|
||||
u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseBoardType_8723D(PADAPTER Adapter,
|
||||
u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
|
||||
void rtl8723d_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8723d(_adapter *adapter);
|
||||
u8 SetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
|
||||
void GetHwReg8723D(PADAPTER padapter, u8 variable, u8 *val);
|
||||
u8 SetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
u8 GetHalDefVar8723D(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
|
||||
/* register */
|
||||
void rtl8723d_InitBeaconParameters(PADAPTER padapter);
|
||||
void rtl8723d_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
|
||||
void _InitMacAPLLSetting_8723D(PADAPTER Adapter);
|
||||
void _8051Reset8723(PADAPTER padapter);
|
||||
#ifdef CONFIG_WOWLAN
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
void rtl8723d_start_thread(_adapter *padapter);
|
||||
void rtl8723d_stop_thread(_adapter *padapter);
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void rtl8723ds_init_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8723ds_free_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8723ds_cancle_checkbthang_workqueue(_adapter *adapter);
|
||||
void rtl8723ds_hal_check_bt_hang(_adapter *adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GPIO_WAKEUP
|
||||
void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue);
|
||||
#endif
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
|
||||
#endif
|
||||
void CCX_FwC2HTxRpt_8723d(PADAPTER padapter, u8 *pdata, u8 len);
|
||||
|
||||
u8 MRateToHwRate8723D(u8 rate);
|
||||
u8 HwRateToMRate8723D(u8 rate);
|
||||
|
||||
void Hal_ReadRFGainOffset(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
|
||||
#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
|
||||
void check_bt_status_work(void *data);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
BOOLEAN InterruptRecognized8723DE(PADAPTER Adapter);
|
||||
void UpdateInterruptMask8723DE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
u16 get_txbd_rw_reg(u16 ff_hwaddr);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_LED_H__
|
||||
#define __RTL8723D_LED_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
#include <osdep_service.h>
|
||||
#include <drv_types.h>
|
||||
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8723du_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723du_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8723ds_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_GSPI_HCI
|
||||
void rtl8723ds_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723ds_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8723de_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8723de_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#endif /*#ifdef CONFIG_RTW_SW_LED*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/******************************************** CONST ************************/
|
||||
#define NUM_OF_REGISTER_BANK 13
|
||||
#define NUM_OF_TOTAL_DWORD (NUM_OF_REGISTER_BANK * 64)
|
||||
#define TOTAL_LEN_FOR_HIOE ((NUM_OF_TOTAL_DWORD + 1) * 8)
|
||||
#define LPS_POFF_STATIC_FILE_LEN (TOTAL_LEN_FOR_HIOE + TXDESC_SIZE)
|
||||
#define LPS_POFF_DYNAMIC_FILE_LEN (512 + TXDESC_SIZE)
|
||||
/******************************************** CONST ************************/
|
||||
|
||||
/******************************************** MACRO ************************/
|
||||
/* HOIE Entry Definition */
|
||||
#define SET_HOIE_ENTRY_LOW_DATA(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE), 0, 16, __Value)
|
||||
#define SET_HOIE_ENTRY_HIGH_DATA(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE), 16, 16, __Value)
|
||||
#define SET_HOIE_ENTRY_MODE_SELECT(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 0, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_ADDRESS(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 1, 14, __Value)
|
||||
#define SET_HOIE_ENTRY_BYTE_MASK(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 15, 4, __Value)
|
||||
#define SET_HOIE_ENTRY_IO_LOCK(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 19, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_RD_EN(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 20, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_WR_EN(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 21, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_RAW_RW(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 22, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_RAW(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 23, 1, __Value)
|
||||
#define SET_HOIE_ENTRY_IO_DELAY(__pHOIE, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE((__pHOIE)+4, 24, 8, __Value)
|
||||
|
||||
/*********************Function Definition*******************************************/
|
||||
void rtl8723d_lps_poff_init(PADAPTER padapter);
|
||||
void rtl8723d_lps_poff_deinit(PADAPTER padapter);
|
||||
bool rtl8723d_lps_poff_get_txbndy_status(PADAPTER padapter);
|
||||
void rtl8723d_lps_poff_h2c_ctrl(PADAPTER padapter, u8 enable);
|
||||
void rtl8723d_lps_poff_set_ps_mode(PADAPTER padapter, bool bEnterLPS);
|
||||
bool rtl8723d_lps_poff_get_status(PADAPTER padapter);
|
||||
void rtl8723d_lps_poff_wow(PADAPTER padapter);
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_RECV_H__
|
||||
#define __RTL8723D_RECV_H__
|
||||
|
||||
#define RECV_BLK_SZ 512
|
||||
#define RECV_BLK_CNT 16
|
||||
#define RECV_BLK_TH RECV_BLK_CNT
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
/* #define MAX_RECVBUF_SZ (32768) */ /* 32k */
|
||||
/* #define MAX_RECVBUF_SZ (16384) */ /* 16K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
#ifdef CONFIG_PLATFORM_MSTAR
|
||||
#define MAX_RECVBUF_SZ (8192) /* 8K */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
|
||||
#endif
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
|
||||
/* #define MAX_RECVBUF_SZ (9100) */
|
||||
/* #else */
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K
|
||||
* #endif */
|
||||
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8723D + 1)
|
||||
|
||||
#endif
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#ifndef CONFIG_SDIO_RX_COPY
|
||||
#undef MAX_RECVBUF_SZ
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_SIZE_8723D - RX_DMA_RESERVED_SIZE_8723D)
|
||||
#endif /* !CONFIG_SDIO_RX_COPY */
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RTL8723D RX BUFFER DESC */
|
||||
/*-----------------------------------------------------------------*/
|
||||
/*DWORD 0*/
|
||||
#define SET_RX_BUFFER_DESC_DATA_LENGTH_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 15, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 1, __Value)
|
||||
#define SET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 16, 15, __Value)
|
||||
|
||||
#define GET_RX_BUFFER_DESC_OWN_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
#define GET_RX_BUFFER_DESC_LS_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_BUFFER_DESC_FS_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 1)
|
||||
#ifdef USING_RX_TAG
|
||||
#define GET_RX_BUFFER_DESC_RX_TAG_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 13)
|
||||
#else
|
||||
#define GET_RX_BUFFER_DESC_TOTAL_LENGTH_8723D(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 15)
|
||||
#endif
|
||||
|
||||
/*DWORD 1*/
|
||||
#define SET_RX_BUFFER_PHYSICAL_LOW_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+4, 0, 32, __Value)
|
||||
|
||||
/*DWORD 2*/
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc+8, 0, 32, __Value)
|
||||
#else
|
||||
#define SET_RX_BUFFER_PHYSICAL_HIGH_8723D(__pRxStatusDesc, __Value)
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8723ds_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8723ds_free_recv_priv(PADAPTER padapter);
|
||||
s32 rtl8723ds_recv_hdl(_adapter *padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
int rtl8723du_init_recv_priv(_adapter *padapter);
|
||||
void rtl8723du_free_recv_priv(_adapter *padapter);
|
||||
void rtl8723du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8723de_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8723de_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8723d_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8723D_RECV_H__ */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_RF_H__
|
||||
#define __RTL8723D_RF_H__
|
||||
|
||||
int PHY_RF6052_Config8723D(PADAPTER pdapter);
|
||||
|
||||
void PHY_RF6052SetBandwidth8723D(PADAPTER Adapter, enum channel_width Bandwidth);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,447 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_SPEC_H__
|
||||
#define __RTL8723D_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
|
||||
#define HAL_NAV_UPPER_UNIT_8723D 128 /* micro-second */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SYS_ISO_CTRL_8723D 0x0000 /* 2 Byte */
|
||||
#define REG_SYS_FUNC_EN_8723D 0x0002 /* 2 Byte */
|
||||
#define REG_APS_FSMCO_8723D 0x0004 /* 4 Byte */
|
||||
#define REG_SYS_CLKR_8723D 0x0008 /* 2 Byte */
|
||||
#define REG_9346CR_8723D 0x000A /* 2 Byte */
|
||||
#define REG_EE_VPD_8723D 0x000C /* 2 Byte */
|
||||
#define REG_AFE_MISC_8723D 0x0010 /* 1 Byte */
|
||||
#define REG_SPS0_CTRL_8723D 0x0011 /* 7 Byte */
|
||||
#define REG_SPS_OCP_CFG_8723D 0x0018 /* 4 Byte */
|
||||
#define REG_RSV_CTRL_8723D 0x001C /* 3 Byte */
|
||||
#define REG_RF_CTRL_8723D 0x001F /* 1 Byte */
|
||||
#define REG_LPLDO_CTRL_8723D 0x0023 /* 1 Byte */
|
||||
#define REG_AFE_XTAL_CTRL_8723D 0x0024 /* 4 Byte */
|
||||
#define REG_AFE_PLL_CTRL_8723D 0x0028 /* 4 Byte */
|
||||
#define REG_MAC_PLL_CTRL_EXT_8723D 0x002c /* 4 Byte */
|
||||
#define REG_EFUSE_CTRL_8723D 0x0030
|
||||
#define REG_EFUSE_TEST_8723D 0x0034
|
||||
#define REG_PWR_DATA_8723D 0x0038
|
||||
#define REG_CAL_TIMER_8723D 0x003C
|
||||
#define REG_ACLK_MON_8723D 0x003E
|
||||
#define REG_GPIO_MUXCFG_8723D 0x0040
|
||||
#define REG_GPIO_IO_SEL_8723D 0x0042
|
||||
#define REG_MAC_PINMUX_CFG_8723D 0x0043
|
||||
#define REG_GPIO_PIN_CTRL_8723D 0x0044
|
||||
#define REG_GPIO_INTM_8723D 0x0048
|
||||
#define REG_LEDCFG0_8723D 0x004C
|
||||
#define REG_LEDCFG1_8723D 0x004D
|
||||
#define REG_LEDCFG2_8723D 0x004E
|
||||
#define REG_LEDCFG3_8723D 0x004F
|
||||
#define REG_FSIMR_8723D 0x0050
|
||||
#define REG_FSISR_8723D 0x0054
|
||||
#define REG_HSIMR_8723D 0x0058
|
||||
#define REG_HSISR_8723D 0x005c
|
||||
#define REG_GPIO_EXT_CTRL 0x0060
|
||||
#define REG_PAD_CTRL1_8723D 0x0064
|
||||
#define REG_MULTI_FUNC_CTRL_8723D 0x0068
|
||||
#define REG_GPIO_STATUS_8723D 0x006C
|
||||
#define REG_SDIO_CTRL_8723D 0x0070
|
||||
#define REG_OPT_CTRL_8723D 0x0074
|
||||
#define REG_AFE_CTRL_4_8723D 0x0078
|
||||
#define REG_MCUFWDL_8723D 0x0080
|
||||
#define REG_8051FW_CTRL_8723D 0x0080
|
||||
#define REG_HMEBOX_DBG_0_8723D 0x0088
|
||||
#define REG_HMEBOX_DBG_1_8723D 0x008A
|
||||
#define REG_HMEBOX_DBG_2_8723D 0x008C
|
||||
#define REG_HMEBOX_DBG_3_8723D 0x008E
|
||||
#define REG_WLLPS_CTRL 0x0090
|
||||
#define REG_HIMR0_8723D 0x00B0
|
||||
#define REG_HISR0_8723D 0x00B4
|
||||
#define REG_HIMR1_8723D 0x00B8
|
||||
#define REG_HISR1_8723D 0x00BC
|
||||
#define REG_PMC_DBG_CTRL2_8723D 0x00CC
|
||||
#define REG_EFUSE_BURN_GNT_8723D 0x00CF
|
||||
#define REG_HPON_FSM_8723D 0x00EC
|
||||
#define REG_SYS_CFG1_8723D 0x00F0
|
||||
#define REG_SYS_CFG_8723D 0x00FC
|
||||
#define REG_ROM_VERSION 0x00FD
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_C2HEVT_CMD_ID_8723D 0x01A0
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
|
||||
#define REG_C2HEVT_CMD_LEN_8723D 0x01AE
|
||||
#define REG_C2HEVT_CLEAR_8723D 0x01AF
|
||||
#define REG_MCUTST_1_8723D 0x01C0
|
||||
#define REG_WOWLAN_WAKE_REASON 0x01C7
|
||||
#define REG_FMETHR_8723D 0x01C8
|
||||
#define REG_HMETFR_8723D 0x01CC
|
||||
#define REG_HMEBOX_0_8723D 0x01D0
|
||||
#define REG_HMEBOX_1_8723D 0x01D4
|
||||
#define REG_HMEBOX_2_8723D 0x01D8
|
||||
#define REG_HMEBOX_3_8723D 0x01DC
|
||||
#define REG_LLT_INIT_8723D 0x01E0
|
||||
#define REG_HMEBOX_EXT0_8723D 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8723D 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8723D 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8723D 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RQPN_8723D 0x0200
|
||||
#define REG_FIFOPAGE_8723D 0x0204
|
||||
#define REG_DWBCN0_CTRL_8723D REG_TDECTRL
|
||||
#define REG_TXDMA_OFFSET_CHK_8723D 0x020C
|
||||
#define REG_TXDMA_STATUS_8723D 0x0210
|
||||
#define REG_RQPN_NPQ_8723D 0x0214
|
||||
#define REG_DWBCN1_CTRL_8723D 0x0228
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_RXDMA_AGG_PG_TH_8723D 0x0280
|
||||
#define REG_FW_UPD_RDPTR_8723D 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */
|
||||
#define REG_RXDMA_CONTROL_8723D 0x0286 /* Control the RX DMA. */
|
||||
#define REG_RXDMA_STATUS_8723D 0x0288
|
||||
#define REG_RXDMA_MODE_CTRL_8723D 0x0290
|
||||
#define REG_EARLY_MODE_CONTROL_8723D 0x02BC
|
||||
#define REG_RSVD5_8723D 0x02F0
|
||||
#define REG_RSVD6_8723D 0x02F4
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8723D 0x0300
|
||||
#define REG_INT_MIG_8723D 0x0304 /* Interrupt Migration */
|
||||
#define REG_BCNQ_TXBD_DESA_8723D 0x0308 /* TX Beacon Descriptor Address */
|
||||
#define REG_MGQ_TXBD_DESA_8723D 0x0310 /* TX Manage Queue Descriptor Address */
|
||||
#define REG_VOQ_TXBD_DESA_8723D 0x0318 /* TX VO Queue Descriptor Address */
|
||||
#define REG_VIQ_TXBD_DESA_8723D 0x0320 /* TX VI Queue Descriptor Address */
|
||||
#define REG_BEQ_TXBD_DESA_8723D 0x0328 /* TX BE Queue Descriptor Address */
|
||||
#define REG_BKQ_TXBD_DESA_8723D 0x0330 /* TX BK Queue Descriptor Address */
|
||||
#define REG_RXQ_RXBD_DESA_8723D 0x0338 /* RX Queue Descriptor Address */
|
||||
#define REG_HI0Q_TXBD_DESA_8723D 0x0340
|
||||
#define REG_HI1Q_TXBD_DESA_8723D 0x0348
|
||||
#define REG_HI2Q_TXBD_DESA_8723D 0x0350
|
||||
#define REG_HI3Q_TXBD_DESA_8723D 0x0358
|
||||
#define REG_HI4Q_TXBD_DESA_8723D 0x0360
|
||||
#define REG_HI5Q_TXBD_DESA_8723D 0x0368
|
||||
#define REG_HI6Q_TXBD_DESA_8723D 0x0370
|
||||
#define REG_HI7Q_TXBD_DESA_8723D 0x0378
|
||||
#define REG_MGQ_TXBD_NUM_8723D 0x0380
|
||||
#define REG_RX_RXBD_NUM_8723D 0x0382
|
||||
#define REG_VOQ_TXBD_NUM_8723D 0x0384
|
||||
#define REG_VIQ_TXBD_NUM_8723D 0x0386
|
||||
#define REG_BEQ_TXBD_NUM_8723D 0x0388
|
||||
#define REG_BKQ_TXBD_NUM_8723D 0x038A
|
||||
#define REG_HI0Q_TXBD_NUM_8723D 0x038C
|
||||
#define REG_HI1Q_TXBD_NUM_8723D 0x038E
|
||||
#define REG_HI2Q_TXBD_NUM_8723D 0x0390
|
||||
#define REG_HI3Q_TXBD_NUM_8723D 0x0392
|
||||
#define REG_HI4Q_TXBD_NUM_8723D 0x0394
|
||||
#define REG_HI5Q_TXBD_NUM_8723D 0x0396
|
||||
#define REG_HI6Q_TXBD_NUM_8723D 0x0398
|
||||
#define REG_HI7Q_TXBD_NUM_8723D 0x039A
|
||||
#define REG_TSFTIMER_HCI_8723D 0x039C
|
||||
#define REG_BD_RW_PTR_CLR_8723D 0x039C
|
||||
|
||||
/* Read Write Point */
|
||||
#define REG_VOQ_TXBD_IDX_8723D 0x03A0
|
||||
#define REG_VIQ_TXBD_IDX_8723D 0x03A4
|
||||
#define REG_BEQ_TXBD_IDX_8723D 0x03A8
|
||||
#define REG_BKQ_TXBD_IDX_8723D 0x03AC
|
||||
#define REG_MGQ_TXBD_IDX_8723D 0x03B0
|
||||
#define REG_RXQ_TXBD_IDX_8723D 0x03B4
|
||||
#define REG_HI0Q_TXBD_IDX_8723D 0x03B8
|
||||
#define REG_HI1Q_TXBD_IDX_8723D 0x03BC
|
||||
#define REG_HI2Q_TXBD_IDX_8723D 0x03C0
|
||||
#define REG_HI3Q_TXBD_IDX_8723D 0x03C4
|
||||
#define REG_HI4Q_TXBD_IDX_8723D 0x03C8
|
||||
#define REG_HI5Q_TXBD_IDX_8723D 0x03CC
|
||||
#define REG_HI6Q_TXBD_IDX_8723D 0x03D0
|
||||
#define REG_HI7Q_TXBD_IDX_8723D 0x03D4
|
||||
|
||||
#define REG_PCIE_HCPWM_8723DE 0x03D8 /* ?????? */
|
||||
#define REG_PCIE_HRPWM_8723DE 0x03DC /* PCIe RPWM ?????? */
|
||||
#define REG_DBI_WDATA_V1_8723D 0x03E8
|
||||
#define REG_DBI_RDATA_V1_8723D 0x03EC
|
||||
#define REG_DBI_FLAG_V1_8723D 0x03F0
|
||||
#define REG_MDIO_V1_8723D 0x03F4
|
||||
#define REG_PCIE_MIX_CFG_8723D 0x03F8
|
||||
#define REG_HCI_MIX_CFG_8723D 0x03FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_VOQ_INFORMATION_8723D 0x0400
|
||||
#define REG_VIQ_INFORMATION_8723D 0x0404
|
||||
#define REG_BEQ_INFORMATION_8723D 0x0408
|
||||
#define REG_BKQ_INFORMATION_8723D 0x040C
|
||||
#define REG_MGQ_INFORMATION_8723D 0x0410
|
||||
#define REG_HGQ_INFORMATION_8723D 0x0414
|
||||
#define REG_BCNQ_INFORMATION_8723D 0x0418
|
||||
#define REG_TXPKT_EMPTY_8723D 0x041A
|
||||
|
||||
#define REG_FWHW_TXQ_CTRL_8723D 0x0420
|
||||
#define REG_HWSEQ_CTRL_8723D 0x0423
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY_8723D 0x0424
|
||||
#define REG_TXPKTBUF_MGQ_BDNY_8723D 0x0425
|
||||
#define REG_LIFECTRL_CTRL_8723D 0x0426
|
||||
#define REG_MULTI_BCNQ_OFFSET_8723D 0x0427
|
||||
#define REG_SPEC_SIFS_8723D 0x0428
|
||||
#define REG_RL_8723D 0x042A
|
||||
#define REG_TXBF_CTRL_8723D 0x042C
|
||||
#define REG_DARFRC_8723D 0x0430
|
||||
#define REG_RARFRC_8723D 0x0438
|
||||
#define REG_RRSR_8723D 0x0440
|
||||
#define REG_ARFR0_8723D 0x0444
|
||||
#define REG_ARFR1_8723D 0x044C
|
||||
#define REG_CCK_CHECK_8723D 0x0454
|
||||
#define REG_AMPDU_MAX_TIME_8723D 0x0456
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY1_8723D 0x0457
|
||||
|
||||
#define REG_AMPDU_MAX_LENGTH_8723D 0x0458
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723D 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8723D 0x045F
|
||||
#define REG_FAST_EDCA_CTRL_8723D 0x0460
|
||||
#define REG_RD_RESP_PKT_TH_8723D 0x0463
|
||||
#define REG_DATA_SC_8723D 0x0483
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x0484
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x0488
|
||||
#endif
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_POWER_STAGE1_8723D 0x04B4
|
||||
#define REG_POWER_STAGE2_8723D 0x04B8
|
||||
#define REG_AMPDU_BURST_MODE_8723D 0x04BC
|
||||
#define REG_PKT_VO_VI_LIFE_TIME_8723D 0x04C0
|
||||
#define REG_PKT_BE_BK_LIFE_TIME_8723D 0x04C2
|
||||
#define REG_STBC_SETTING_8723D 0x04C4
|
||||
#define REG_HT_SINGLE_AMPDU_8723D 0x04C7
|
||||
#define REG_PROT_MODE_CTRL_8723D 0x04C8
|
||||
#define REG_MAX_AGGR_NUM_8723D 0x04CA
|
||||
#define REG_RTS_MAX_AGGR_NUM_8723D 0x04CB
|
||||
#define REG_BAR_MODE_CTRL_8723D 0x04CC
|
||||
#define REG_RA_TRY_RATE_AGG_LMT_8723D 0x04CF
|
||||
#define REG_MACID_PKT_DROP0_8723D 0x04D0
|
||||
#define REG_MACID_PKT_SLEEP_8723D 0x04D4
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_EDCA_VO_PARAM_8723D 0x0500
|
||||
#define REG_EDCA_VI_PARAM_8723D 0x0504
|
||||
#define REG_EDCA_BE_PARAM_8723D 0x0508
|
||||
#define REG_EDCA_BK_PARAM_8723D 0x050C
|
||||
#define REG_BCNTCFG_8723D 0x0510
|
||||
#define REG_PIFS_8723D 0x0512
|
||||
#define REG_RDG_PIFS_8723D 0x0513
|
||||
#define REG_SIFS_CTX_8723D 0x0514
|
||||
#define REG_SIFS_TRX_8723D 0x0516
|
||||
#define REG_AGGR_BREAK_TIME_8723D 0x051A
|
||||
#define REG_SLOT_8723D 0x051B
|
||||
#define REG_TX_PTCL_CTRL_8723D 0x0520
|
||||
#define REG_TXPAUSE_8723D 0x0522
|
||||
#define REG_DIS_TXREQ_CLR_8723D 0x0523
|
||||
#define REG_RD_CTRL_8723D 0x0524
|
||||
/*
|
||||
* Format for offset 540h-542h:
|
||||
* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT.
|
||||
* [7:4]: Reserved.
|
||||
* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet.
|
||||
* [23:20]: Reserved
|
||||
* Description:
|
||||
* |
|
||||
* |<--Setup--|--Hold------------>|
|
||||
* --------------|----------------------
|
||||
* |
|
||||
* TBTT
|
||||
* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold.
|
||||
* Described by Designer Tim and Bruce, 2011-01-14.
|
||||
* */
|
||||
#define REG_TBTT_PROHIBIT_8723D 0x0540
|
||||
#define REG_RD_NAV_NXT_8723D 0x0544
|
||||
#define REG_NAV_PROT_LEN_8723D 0x0546
|
||||
#define REG_BCN_CTRL_8723D 0x0550
|
||||
#define REG_BCN_CTRL_1_8723D 0x0551
|
||||
#define REG_MBID_NUM_8723D 0x0552
|
||||
#define REG_DUAL_TSF_RST_8723D 0x0553
|
||||
#define REG_BCN_INTERVAL_8723D 0x0554
|
||||
#define REG_DRVERLYINT_8723D 0x0558
|
||||
#define REG_BCNDMATIM_8723D 0x0559
|
||||
#define REG_ATIMWND_8723D 0x055A
|
||||
#define REG_USTIME_TSF_8723D 0x055C
|
||||
#define REG_BCN_MAX_ERR_8723D 0x055D
|
||||
#define REG_RXTSF_OFFSET_CCK_8723D 0x055E
|
||||
#define REG_RXTSF_OFFSET_OFDM_8723D 0x055F
|
||||
#define REG_TSFTR_8723D 0x0560
|
||||
#define REG_CTWND_8723D 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8723D 0x0577
|
||||
#define REG_PSTIMER_8723D 0x0580
|
||||
#define REG_TIMER0_8723D 0x0584
|
||||
#define REG_TIMER1_8723D 0x0588
|
||||
#define REG_ACMHWCTRL_8723D 0x05C0
|
||||
#define REG_SCH_TXCMD_8723D 0x05F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_MAC_CR_8723D 0x0600
|
||||
#define REG_TCR_8723D 0x0604
|
||||
#define REG_RCR_8723D 0x0608
|
||||
#define REG_RX_PKT_LIMIT_8723D 0x060C
|
||||
#define REG_RX_DLK_TIME_8723D 0x060D
|
||||
#define REG_RX_DRVINFO_SZ_8723D 0x060F
|
||||
|
||||
#define REG_MACID_8723D 0x0610
|
||||
#define REG_BSSID_8723D 0x0618
|
||||
#define REG_MAR_8723D 0x0620
|
||||
#define REG_MBIDCAMCFG_8723D 0x0628
|
||||
#define REG_WOWLAN_GTK_DBG1 0x630
|
||||
#define REG_WOWLAN_GTK_DBG2 0x634
|
||||
|
||||
#define REG_USTIME_EDCA_8723D 0x0638
|
||||
#define REG_MAC_SPEC_SIFS_8723D 0x063A
|
||||
#define REG_RESP_SIFP_CCK_8723D 0x063C
|
||||
#define REG_RESP_SIFS_OFDM_8723D 0x063E
|
||||
#define REG_ACKTO_8723D 0x0640
|
||||
#define REG_CTS2TO_8723D 0x0641
|
||||
#define REG_EIFS_8723D 0x0642
|
||||
|
||||
#define REG_NAV_UPPER_8723D 0x0652 /* unit of 128 */
|
||||
#define REG_TRXPTCL_CTL_8723D 0x0668
|
||||
|
||||
/* Security */
|
||||
#define REG_CAMCMD_8723D 0x0670
|
||||
#define REG_CAMWRITE_8723D 0x0674
|
||||
#define REG_CAMREAD_8723D 0x0678
|
||||
#define REG_CAMDBG_8723D 0x067C
|
||||
#define REG_SECCFG_8723D 0x0680
|
||||
|
||||
/* Power */
|
||||
#define REG_WOW_CTRL_8723D 0x0690
|
||||
#define REG_PS_RX_INFO_8723D 0x0692
|
||||
#define REG_UAPSD_TID_8723D 0x0693
|
||||
#define REG_WKFMCAM_CMD_8723D 0x0698
|
||||
#define REG_WKFMCAM_NUM_8723D 0x0698
|
||||
#define REG_WKFMCAM_RWD_8723D 0x069C
|
||||
#define REG_RXFLTMAP0_8723D 0x06A0
|
||||
#define REG_RXFLTMAP1_8723D 0x06A2
|
||||
#define REG_RXFLTMAP2_8723D 0x06A4
|
||||
#define REG_BCN_PSR_RPT_8723D 0x06A8
|
||||
#define REG_BT_COEX_TABLE_8723D 0x06C0
|
||||
#define REG_BFMER0_INFO_8723D 0x06E4
|
||||
#define REG_BFMER1_INFO_8723D 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8723D 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8723D 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8723D 0x06FC
|
||||
|
||||
/* Hardware Port 2 */
|
||||
#define REG_MACID1_8723D 0x0700
|
||||
#define REG_BSSID1_8723D 0x0708
|
||||
#define REG_BFMEE_SEL_8723D 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8723D 0x0718
|
||||
|
||||
/* LTR */
|
||||
#define REG_LTR_CTRL_BASIC_8723D 0x07A4
|
||||
#define REG_LTR_IDLE_LATENCY_V1_8723D 0x0798
|
||||
#define REG_LTR_ACTIVE_LATENCY_V1_8723D 0x079C
|
||||
|
||||
/* LTE_COEX */
|
||||
#define REG_LTECOEX_CTRL 0x07C0
|
||||
#define REG_LTECOEX_WRITE_DATA 0x07C4
|
||||
#define REG_LTECOEX_READ_DATA 0x07C8
|
||||
#define REG_LTECOEX_PATH_CONTROL 0x70
|
||||
|
||||
/* ************************************************************
|
||||
* SDIO Bus Specification
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO CMD Address Mapping
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* I/O bus domain (Host)
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
* SDIO register
|
||||
* ----------------------------------------------------- */
|
||||
#define SDIO_REG_HCPWM1_8723D 0x025 /* HCI Current Power Mode 1 */
|
||||
|
||||
|
||||
/* ****************************************************************************
|
||||
* 8723 Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
#define BIT_USB_RXDMA_AGG_EN BIT(31)
|
||||
#define RXDMA_AGG_MODE_EN BIT(1)
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RXPKT_RELEASE_POLL BIT(16)
|
||||
#define RXDMA_IDLE BIT(17)
|
||||
#define RW_RELEASE_EN BIT(18)
|
||||
#endif
|
||||
|
||||
/* 2 HSISR
|
||||
* interrupt mask which needs to clear */
|
||||
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
|
||||
HSISR_SPS_OCP_INT |\
|
||||
HSISR_RON_INT |\
|
||||
HSISR_PDNINT |\
|
||||
HSISR_GPIO9_INT)
|
||||
|
||||
#ifdef CONFIG_RF_POWER_TRIM
|
||||
#ifdef CONFIG_RTL8723D
|
||||
#define EEPROM_RF_GAIN_OFFSET 0xC1
|
||||
#endif
|
||||
|
||||
#define EEPROM_RF_GAIN_VAL 0x1F6
|
||||
#endif /*CONFIG_RF_POWER_TRIM*/
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* #define IMR_RX_MASK (IMR_ROK_8723D|IMR_RDU_8723D|IMR_RXFOVW_8723D) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_8723D | IMR_VIDOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D | IMR_MGNTDOK_8723D | IMR_HIGHDOK_8723D)
|
||||
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723D | IMR_TXBCN0OK_8723D | IMR_TXBCN0ERR_8723D | IMR_BCNDERR0_8723D)
|
||||
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8723D | IMR_VODOK_8723D | IMR_BEDOK_8723D | IMR_BKDOK_8723D)
|
||||
#endif
|
||||
|
||||
#endif /* __RTL8723D_SPEC_H__ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8723D_SRESET_H_
|
||||
#define _RTL8723D_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8723d_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8723d_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,530 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8723D_XMIT_H__
|
||||
#define __RTL8723D_XMIT_H__
|
||||
|
||||
|
||||
#define MAX_TID (15)
|
||||
|
||||
|
||||
#ifndef __INC_HAL8723DDESC_H
|
||||
#define __INC_HAL8723DDESC_H
|
||||
|
||||
#define RX_STATUS_DESC_SIZE_8723D 24
|
||||
#define RX_DRV_INFO_SIZE_UNIT_8723D 8
|
||||
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICV_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FIT_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_CHKERR_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_IPVER_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP__8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
#define GET_RX_STATUS_DESC_FCS_OK_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 31, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
#endif
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_MATCH_ID_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 7)
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_8723D(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723D(__pRxDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_STATUS_DESC_BUFF_ADDR_8723D(__pRxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
|
||||
|
||||
|
||||
/* Dword 0, rsvd: bit26, bit28 */
|
||||
#define GET_TX_DESC_OWN_8723D(__pTxDesc)\
|
||||
LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
|
||||
|
||||
#define SET_TX_DESC_PKT_SIZE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
|
||||
#define SET_TX_DESC_OFFSET_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
|
||||
#define SET_TX_DESC_BMC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
|
||||
#define SET_TX_DESC_HTC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
|
||||
#define SET_TX_DESC_AMSDU_PAD_EN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
|
||||
#define SET_TX_DESC_NO_ACM_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
|
||||
#define SET_TX_DESC_GF_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
|
||||
|
||||
/* Dword 1 */
|
||||
#define SET_TX_DESC_MACID_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
|
||||
#define SET_TX_DESC_QUEUE_SEL_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RDG_NAV_EXT_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
|
||||
#define SET_TX_DESC_LSIG_TXOP_EN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
|
||||
#define SET_TX_DESC_PIFS_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
|
||||
#define SET_TX_DESC_RATE_ID_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
|
||||
#define SET_TX_DESC_EN_DESC_ID_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
|
||||
#define SET_TX_DESC_SEC_TYPE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
|
||||
#define SET_TX_DESC_PKT_OFFSET_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
|
||||
#define SET_TX_DESC_MORE_DATA_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 29, 1, __Value)
|
||||
|
||||
/* Dword 2 remove P_AID, G_ID field*/
|
||||
#define SET_TX_DESC_CCA_RTS_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
|
||||
#define SET_TX_DESC_AGG_ENABLE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RDG_ENABLE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
|
||||
#define SET_TX_DESC_NULL0_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
|
||||
#define SET_TX_DESC_NULL1_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
|
||||
#define SET_TX_DESC_BK_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MORE_FRAG_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
|
||||
#define SET_TX_DESC_RAW_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
|
||||
#define SET_TX_DESC_CCX_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
|
||||
#define SET_TX_DESC_AMPDU_DENSITY_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
|
||||
#define SET_TX_DESC_BT_INT_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
|
||||
#define SET_TX_DESC_FTM_EN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 30, 1, __Value)
|
||||
|
||||
/* Dword 3 */
|
||||
#define SET_TX_DESC_HWSEQ_SEL_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
|
||||
#define SET_TX_DESC_USE_RATE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_RTS_FB_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
|
||||
#define SET_TX_DESC_DISABLE_FB_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
|
||||
#define SET_TX_DESC_CTS2SELF_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_ENABLE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
|
||||
#define SET_TX_DESC_HW_RTS_ENABLE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
|
||||
#define SET_TX_DESC_PORT_ID_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 14, 2, __Value)
|
||||
#define SET_TX_DESC_NAV_USE_HDR_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
|
||||
#define SET_TX_DESC_USE_MAX_LEN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
|
||||
#define SET_TX_DESC_MAX_AGG_NUM_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
|
||||
#define SET_TX_DESC_AMPDU_MAX_TIME_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
|
||||
|
||||
/* Dword 4 */
|
||||
#define SET_TX_DESC_TX_RATE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
|
||||
#define SET_TX_DESC_TX_TRY_RATE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 7, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
|
||||
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_RETRY_LIMIT_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
|
||||
#define SET_TX_DESC_RTS_RATE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
|
||||
#define SET_TX_DESC_PCTS_EN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 29, 1, __Value)
|
||||
#define SET_TX_DESC_PCTS_MASK_IDX_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 30, 2, __Value)
|
||||
|
||||
/* Dword 5 */
|
||||
#define SET_TX_DESC_DATA_SC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
|
||||
#define SET_TX_DESC_DATA_SHORT_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
|
||||
#define SET_TX_DESC_DATA_BW_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_STBC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_STBC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
|
||||
#define SET_TX_DESC_RTS_SHORT_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
|
||||
#define SET_TX_DESC_RTS_SC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
|
||||
#define SET_TX_DESC_PATH_A_EN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 1, __Value)
|
||||
#define SET_TX_DESC_TXPWR_OF_SET_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 28, 3, __Value)
|
||||
|
||||
/* Dword 6 */
|
||||
#define SET_TX_DESC_SW_DEFINE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
|
||||
#define SET_TX_DESC_MBSSID_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
|
||||
#define SET_TX_DESC_RF_SEL_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
|
||||
|
||||
/* Dword 7 */
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
#define SET_TX_DESC_TX_BUFFER_SIZE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#define SET_TX_DESC_TX_DESC_CHECKSUM_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
#define SET_TX_DESC_TX_TIMESTAMP_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 6, 18, __Value)
|
||||
#endif
|
||||
|
||||
#define SET_TX_DESC_USB_TXAGG_NUM_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
|
||||
|
||||
/* Dword 8 */
|
||||
#define SET_TX_DESC_RTS_RC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 0, 6, __Value)
|
||||
#define SET_TX_DESC_BAR_RC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 6, 2, __Value)
|
||||
#define SET_TX_DESC_DATA_RC_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 8, 6, __Value)
|
||||
#define SET_TX_DESC_HWSEQ_EN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
|
||||
#define SET_TX_DESC_NEXTHEADPAGE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 16, 8, __Value)
|
||||
#define SET_TX_DESC_TAILPAGE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 24, 8, __Value)
|
||||
|
||||
/* Dword 9 */
|
||||
#define SET_TX_DESC_PADDING_LEN_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 0, 11, __Value)
|
||||
#define SET_TX_DESC_SEQ_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
|
||||
#define SET_TX_DESC_FINAL_DATA_RATE_8723D(__pTxDesc, __Value) \
|
||||
SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 24, 8, __Value)
|
||||
|
||||
|
||||
#define SET_EARLYMODE_PKTNUM_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
|
||||
#define SET_EARLYMODE_LEN0_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN1_1_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
|
||||
#define SET_EARLYMODE_LEN1_2_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
|
||||
#define SET_EARLYMODE_LEN2_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
|
||||
#define SET_EARLYMODE_LEN3_8723D(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------*/
|
||||
/* RTL8723D TX BUFFER DESC */
|
||||
/*-----------------------------------------------------------------*/
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+((__Offset)*16)+8, 0, 32, __Valeu)
|
||||
#else
|
||||
#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu)
|
||||
#define SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) /* 64 BIT mode only */
|
||||
#endif
|
||||
/* ********************************************************* */
|
||||
|
||||
/* 64 bits -- 32 bits */
|
||||
/* ======= ======= */
|
||||
/* Dword 0 0 */
|
||||
#define SET_TX_BUFF_DESC_LEN_0_8723D(__pTxDesc, __Valeu) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 14, __Valeu)
|
||||
#define SET_TX_BUFF_DESC_PSB_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 15, __Value)
|
||||
#define SET_TX_BUFF_DESC_OWN_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
|
||||
|
||||
/* Dword 1 1 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 32, __Value)
|
||||
#define GET_TX_BUFF_DESC_ADDR_LOW_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+4, 0, 32)
|
||||
/* Dword 2 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 0, __Value)
|
||||
#ifdef CONFIG_64BIT_DMA
|
||||
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 0, 32)
|
||||
#else
|
||||
#define GET_TX_BUFF_DESC_ADDR_HIGH_0_8723D(__pTxDesc) 0
|
||||
#endif
|
||||
/* Dword 3 NA */
|
||||
/* RESERVED 0 */
|
||||
/* Dword 4 2 */
|
||||
#define SET_TX_BUFF_DESC_LEN_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 5 3 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 6 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_1_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 1, __Value)
|
||||
/* Dword 7 NA */
|
||||
/*RESERVED 0 */
|
||||
/* Dword 8 4 */
|
||||
#define SET_TX_BUFF_DESC_LEN_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 9 5 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 10 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_2_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 2, __Value)
|
||||
/* Dword 11 NA */
|
||||
/*RESERVED 0 */
|
||||
/* Dword 12 6 */
|
||||
#define SET_TX_BUFF_DESC_LEN_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
#define SET_TX_BUFF_DESC_AMSDU_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 13 7 */
|
||||
#define SET_TX_BUFF_DESC_ADDR_LOW_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 14 NA */
|
||||
#define SET_TX_BUFF_DESC_ADDR_HIGH_3_8723D(__pTxDesc, __Value) SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(__pTxDesc, 3, __Value)
|
||||
/* Dword 15 NA */
|
||||
/*RESERVED 0 */
|
||||
|
||||
|
||||
#endif
|
||||
/* -----------------------------------------------------------
|
||||
*
|
||||
* Rate
|
||||
*
|
||||
* -----------------------------------------------------------
|
||||
* CCK Rates, TxHT = 0 */
|
||||
#define DESC8723D_RATE1M 0x00
|
||||
#define DESC8723D_RATE2M 0x01
|
||||
#define DESC8723D_RATE5_5M 0x02
|
||||
#define DESC8723D_RATE11M 0x03
|
||||
|
||||
/* OFDM Rates, TxHT = 0 */
|
||||
#define DESC8723D_RATE6M 0x04
|
||||
#define DESC8723D_RATE9M 0x05
|
||||
#define DESC8723D_RATE12M 0x06
|
||||
#define DESC8723D_RATE18M 0x07
|
||||
#define DESC8723D_RATE24M 0x08
|
||||
#define DESC8723D_RATE36M 0x09
|
||||
#define DESC8723D_RATE48M 0x0a
|
||||
#define DESC8723D_RATE54M 0x0b
|
||||
|
||||
/* MCS Rates, TxHT = 1 */
|
||||
#define DESC8723D_RATEMCS0 0x0c
|
||||
#define DESC8723D_RATEMCS1 0x0d
|
||||
#define DESC8723D_RATEMCS2 0x0e
|
||||
#define DESC8723D_RATEMCS3 0x0f
|
||||
#define DESC8723D_RATEMCS4 0x10
|
||||
#define DESC8723D_RATEMCS5 0x11
|
||||
#define DESC8723D_RATEMCS6 0x12
|
||||
#define DESC8723D_RATEMCS7 0x13
|
||||
#define DESC8723D_RATEMCS8 0x14
|
||||
#define DESC8723D_RATEMCS9 0x15
|
||||
#define DESC8723D_RATEMCS10 0x16
|
||||
#define DESC8723D_RATEMCS11 0x17
|
||||
#define DESC8723D_RATEMCS12 0x18
|
||||
#define DESC8723D_RATEMCS13 0x19
|
||||
#define DESC8723D_RATEMCS14 0x1a
|
||||
#define DESC8723D_RATEMCS15 0x1b
|
||||
#define DESC8723D_RATEVHTSS1MCS0 0x2c
|
||||
#define DESC8723D_RATEVHTSS1MCS1 0x2d
|
||||
#define DESC8723D_RATEVHTSS1MCS2 0x2e
|
||||
#define DESC8723D_RATEVHTSS1MCS3 0x2f
|
||||
#define DESC8723D_RATEVHTSS1MCS4 0x30
|
||||
#define DESC8723D_RATEVHTSS1MCS5 0x31
|
||||
#define DESC8723D_RATEVHTSS1MCS6 0x32
|
||||
#define DESC8723D_RATEVHTSS1MCS7 0x33
|
||||
#define DESC8723D_RATEVHTSS1MCS8 0x34
|
||||
#define DESC8723D_RATEVHTSS1MCS9 0x35
|
||||
#define DESC8723D_RATEVHTSS2MCS0 0x36
|
||||
#define DESC8723D_RATEVHTSS2MCS1 0x37
|
||||
#define DESC8723D_RATEVHTSS2MCS2 0x38
|
||||
#define DESC8723D_RATEVHTSS2MCS3 0x39
|
||||
#define DESC8723D_RATEVHTSS2MCS4 0x3a
|
||||
#define DESC8723D_RATEVHTSS2MCS5 0x3b
|
||||
#define DESC8723D_RATEVHTSS2MCS6 0x3c
|
||||
#define DESC8723D_RATEVHTSS2MCS7 0x3d
|
||||
#define DESC8723D_RATEVHTSS2MCS8 0x3e
|
||||
#define DESC8723D_RATEVHTSS2MCS9 0x3f
|
||||
|
||||
|
||||
#define RX_HAL_IS_CCK_RATE_8723D(pDesc)\
|
||||
(GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE1M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE2M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE5_5M || \
|
||||
GET_RX_STATUS_DESC_RX_RATE_8723D(pDesc) == DESC8723D_RATE11M)
|
||||
|
||||
#ifdef CONFIG_TRX_BD_ARCH
|
||||
struct tx_desc;
|
||||
#endif
|
||||
|
||||
void rtl8723d_cal_txdesc_chksum(struct tx_desc *ptxdesc);
|
||||
void rtl8723d_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
|
||||
void rtl8723d_fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8723d_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8723d_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, struct tx_desc *ptxdesc);
|
||||
void rtl8723d_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
|
||||
|
||||
void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
|
||||
|
||||
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
|
||||
s32 rtl8723ds_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8723ds_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8723ds_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723ds_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8723ds_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8723ds_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723ds_xmit_buf_handler(PADAPTER padapter);
|
||||
thread_return rtl8723ds_xmit_thread(thread_context context);
|
||||
#define hal_xmit_handler rtl8723ds_xmit_buf_handler
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
s32 rtl8723du_xmit_buf_handler(PADAPTER padapter);
|
||||
#define hal_xmit_handler rtl8723du_xmit_buf_handler
|
||||
s32 rtl8723du_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8723du_free_xmit_priv(PADAPTER padapter);
|
||||
s32 rtl8723du_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723du_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8723du_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8723du_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8723du_xmit_tasklet(void *priv);
|
||||
s32 rtl8723du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
|
||||
void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8723de_init_xmit_priv(PADAPTER padapter);
|
||||
void rtl8723de_free_xmit_priv(PADAPTER padapter);
|
||||
struct xmit_buf *rtl8723de_dequeue_xmitbuf(struct rtw_tx_ring *ring);
|
||||
void rtl8723de_xmitframe_resume(_adapter *padapter);
|
||||
s32 rtl8723de_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
|
||||
s32 rtl8723de_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
|
||||
#ifdef CONFIG_RTW_MGMT_QUEUE
|
||||
s32 rtl8723de_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
#endif
|
||||
s32 rtl8723de_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
|
||||
void rtl8723de_xmit_tasklet(void *priv);
|
||||
#endif
|
||||
|
||||
u8 BWMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
u8 SCMapping_8723D(PADAPTER Adapter, struct pkt_attrib *pattrib);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8723F_HAL_H_
|
||||
#define _RTL8723F_HAL_H_
|
||||
|
||||
#include <osdep_service.h> /* BIT(x) */
|
||||
#include <drv_types.h> /* PADAPTER */
|
||||
#include "../hal/halmac/halmac_api.h" /* MAC REG definition */
|
||||
|
||||
#define MAX_RECVBUF_SZ 16384 /* 16KB (RX_FIFO_SIZE_8723F), TX: 32KB */
|
||||
|
||||
/*
|
||||
* MAC Register definition
|
||||
*/
|
||||
#define REG_LEDCFG0 REG_LED_CFG_8723F /* rtw_mp.c */
|
||||
#define MSR (REG_CR_8723F + 2) /* rtw_mp.c & hal_com.c */
|
||||
#define MSR1 REG_CR_EXT_8723F /* rtw_mp.c & hal_com.c */
|
||||
#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */
|
||||
#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */
|
||||
#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8723F /* hal_com.c */
|
||||
|
||||
#define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */
|
||||
#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8723F /* hal_com.c */
|
||||
#define REG_FIFOPAGE REG_FIFOPAGE_INFO_8723F /* hal_com.c */
|
||||
#define REG_RXPKTBUF_CTRL REG_PKTBUF_DBG_CTRL_8723F /* hal_com.c */
|
||||
#define REG_WKFMCAM_NUM REG_WKFMCAM_CMD_8723F /* hal_com.c */
|
||||
#define REG_RSV_CTRL REG_REG_ACCESS_CTRL_8723F /* hal_com.c */
|
||||
#define REG_CAMCMD REG_KEYCAMCMD_8723F /* hal_com.c */
|
||||
#define REG_CAMWRITE REG_KEYCAM_WD_8723F /* hal_com.c */
|
||||
|
||||
#define BIT_AUTO_SYNC_BY_TBTT BIT_EN_TSFAUTO_SYNC_8723F /* hal_com.c */
|
||||
#define BIT_DIS_ATIM_ROOT_8723F 23 /* REG_HIQ_NO_LMT_EN_V2[23], disable ATIM ROOT */
|
||||
#define BIT_SECCAM_POLLING_8723F BIT_KEYCAM_POLLING_8723F /* rtl8723f_ops.c */
|
||||
#define BIT_GET_NETYPE2 BIT_GET_P2_NETSTATE_8723F /* hal_halmac.c */
|
||||
#define BIT_GET_NETYPE3 BIT_GET_P3_NETSTATE_8723F /* hal_halmac.c */
|
||||
#define BIT_GET_NETYPE4 BIT_GET_P4_NETSTATE_8723F /* hal_halmac.c */
|
||||
|
||||
#ifdef CONFIG_WOW_PATTERN_IN_TXFIFO
|
||||
#define WKCAM_OFFSET_BIT_MASK 0xFFF
|
||||
#define WKCAM_OFFSET_BIT_MASK_OFFSET 12
|
||||
#define REG_TXBUF_WKCAM_OFFSET 0x1B4 //BIT_TXBUF_WKCAM_OFFSET [24:12]
|
||||
#define REG_PKT_BUFF_ACCESS_CTRL 0x106 /* hal_com.c */
|
||||
#endif
|
||||
|
||||
/* RXERR_RPT, for rtw_mp.c */
|
||||
#define RXERR_TYPE_OFDM_PPDU 0
|
||||
#define RXERR_TYPE_OFDM_FALSE_ALARM 2
|
||||
#define RXERR_TYPE_OFDM_MPDU_OK 0
|
||||
#define RXERR_TYPE_OFDM_MPDU_FAIL 1
|
||||
#define RXERR_TYPE_CCK_PPDU 3
|
||||
#define RXERR_TYPE_CCK_FALSE_ALARM 5
|
||||
#define RXERR_TYPE_CCK_MPDU_OK 3
|
||||
#define RXERR_TYPE_CCK_MPDU_FAIL 4
|
||||
#define RXERR_TYPE_HT_PPDU 8
|
||||
#define RXERR_TYPE_HT_FALSE_ALARM 9
|
||||
#define RXERR_TYPE_HT_MPDU_TOTAL 6
|
||||
#define RXERR_TYPE_HT_MPDU_OK 6
|
||||
#define RXERR_TYPE_HT_MPDU_FAIL 7
|
||||
#define RXERR_TYPE_RX_FULL_DROP 10
|
||||
|
||||
#define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8723F
|
||||
#define RXERR_RPT_RST BIT_RXERR_RPT_RST_8723F
|
||||
#define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8723F(type) \
|
||||
| ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8723F : 0))
|
||||
|
||||
/*
|
||||
* BB Register definition
|
||||
*/
|
||||
#define rPMAC_Reset 0x100 /* hal_mp.c */
|
||||
|
||||
#define rFPGA0_RFMOD 0x800
|
||||
#define rFPGA0_TxInfo 0x804
|
||||
#define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */
|
||||
#define rFPGA0_TxGainStage 0x80C /* phydm only */
|
||||
#define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */
|
||||
#define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */
|
||||
#define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */
|
||||
#define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */
|
||||
#define rTxAGC_B_Rate18_06 0x830
|
||||
#define rTxAGC_B_Rate54_24 0x834
|
||||
#define rTxAGC_B_CCK1_55_Mcs32 0x838
|
||||
#define rCCAonSec_Jaguar 0x838 /* hal_mp.c */
|
||||
#define rTxAGC_B_Mcs03_Mcs00 0x83C
|
||||
#define rTxAGC_B_Mcs07_Mcs04 0x848
|
||||
#define rTxAGC_B_Mcs11_Mcs08 0x84C
|
||||
#define rFPGA0_XA_RFInterfaceOE 0x860
|
||||
#define rFPGA0_XB_RFInterfaceOE 0x864
|
||||
#define rTxAGC_B_Mcs15_Mcs12 0x868
|
||||
#define rTxAGC_B_CCK11_A_CCK2_11 0x86C
|
||||
#define rFPGA0_XAB_RFInterfaceSW 0x870
|
||||
#define rFPGA0_XAB_RFParameter 0x878
|
||||
#define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */
|
||||
#define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */
|
||||
#define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8723f_phy.c) */
|
||||
|
||||
#define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */
|
||||
#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */
|
||||
|
||||
#define rFPGA1_TxInfo 0x90C /* hal_mp.c */
|
||||
#define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */
|
||||
/* TX BeamForming */
|
||||
#define REG_BB_TX_PATH_SEL_1_8723F 0x93C /* rtl8723f_phy.c */
|
||||
#define REG_BB_TX_PATH_SEL_2_8723F 0x940 /* rtl8723f_phy.c */
|
||||
|
||||
/* TX BeamForming */
|
||||
#define REG_BB_TXBF_ANT_SET_BF1_8723F 0x19AC /* rtl8723f_phy.c */
|
||||
#define REG_BB_TXBF_ANT_SET_BF0_8723F 0x19B4 /* rtl8723f_phy.c */
|
||||
|
||||
#define rCCK0_System 0xA00
|
||||
#define rCCK0_AFESetting 0xA04
|
||||
|
||||
#define rCCK0_DSPParameter2 0xA1C
|
||||
#define rCCK0_TxFilter1 0xA20
|
||||
#define rCCK0_TxFilter2 0xA24
|
||||
#define rCCK0_DebugPort 0xA28
|
||||
#define rCCK0_FalseAlarmReport 0xA2C
|
||||
|
||||
#define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */
|
||||
#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */
|
||||
|
||||
#define rOFDM0_TRxPathEnable 0xC04
|
||||
#define rOFDM0_TRMuxPar 0xC08
|
||||
#define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */
|
||||
#define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */
|
||||
#define rOFDM0_ECCAThreshold 0xC4C /* phydm only */
|
||||
#define rOFDM0_XAAGCCore1 0xC50 /* phydm only */
|
||||
#define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */
|
||||
#define rOFDM0_XBAGCCore1 0xC58 /* phydm only */
|
||||
#define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */
|
||||
#define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
|
||||
|
||||
#define rOFDM1_LSTF 0xD00
|
||||
#define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */
|
||||
#define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8723f_phy.c) */
|
||||
#define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8723f_phy.c) */
|
||||
#define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8723f_phy.c) */
|
||||
#define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8723f_phy.c) */
|
||||
|
||||
#define rTxAGC_A_Rate18_06 0xE00
|
||||
#define rTxAGC_A_Rate54_24 0xE04
|
||||
#define rTxAGC_A_CCK1_Mcs32 0xE08
|
||||
#define rTxAGC_A_Mcs03_Mcs00 0xE10
|
||||
#define rTxAGC_A_Mcs07_Mcs04 0xE14
|
||||
#define rTxAGC_A_Mcs11_Mcs08 0xE18
|
||||
#define rTxAGC_A_Mcs15_Mcs12 0xE1C
|
||||
#define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */
|
||||
#define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */
|
||||
#define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */
|
||||
/* RFE */
|
||||
#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */
|
||||
#define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */
|
||||
#define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */
|
||||
#define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */
|
||||
#define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */
|
||||
#define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */
|
||||
#define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */
|
||||
#define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
|
||||
#define bMask_RFEInv_Jaguar 0x3FF00000
|
||||
#define bMask_AntselPathFollow_Jaguar 0x00030000
|
||||
|
||||
#define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/
|
||||
#define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/
|
||||
#define rA_RFE_Sel_Jaguar2 0x1990
|
||||
|
||||
/* Page1(0x100) */
|
||||
#define bBBResetB 0x100
|
||||
|
||||
/* Page8(0x800) */
|
||||
#define bCCKEn 0x1000000
|
||||
#define bOFDMEn 0x2000000
|
||||
/* Reg 0x80C rFPGA0_TxGainStage */
|
||||
#define bXBTxAGC 0xF00
|
||||
#define bXCTxAGC 0xF000
|
||||
#define bXDTxAGC 0xF0000
|
||||
|
||||
/* PageA(0xA00) */
|
||||
#define bCCKBBMode 0x3
|
||||
|
||||
#define bCCKScramble 0x8
|
||||
#define bCCKTxRate 0x3000
|
||||
|
||||
/* General */
|
||||
#define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */
|
||||
#define bMaskByte1 0xFF00 /* hal_mp.c & phydm */
|
||||
#define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */
|
||||
#define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */
|
||||
#define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */
|
||||
#define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */
|
||||
#define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */
|
||||
|
||||
#define bEnable 0x1 /* hal_mp.c, rtw_mp.c */
|
||||
#define bDisable 0x0 /* rtw_mp.c */
|
||||
|
||||
#define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */
|
||||
|
||||
#define Rx_Smooth_Factor 20 /* phydm only */
|
||||
|
||||
/*
|
||||
* RF Register definition
|
||||
*/
|
||||
#define RF_AC 0x00
|
||||
#define RF_AC_Jaguar 0x00 /* hal_mp.c */
|
||||
#define RF_CHNLBW 0x18 /* rtl8723f_phy.c */
|
||||
#define RF_ModeTableAddr 0x30 /* rtl8723f_phy.c */
|
||||
#define RF_ModeTableData0 0x31 /* rtl8723f_phy.c */
|
||||
#define RF_ModeTableData1 0x32 /* rtl8723f_phy.c */
|
||||
#define RF_0x52 0x52
|
||||
#define RF_WeLut_Jaguar 0xEF /* rtl8723f_phy.c */
|
||||
|
||||
/* rtw_lps_state_chk() @hal_com.c */
|
||||
#define BIT_PWRBIT_OW_EN BIT_WMAC_TCR_PWRMGT_CTL_8723F
|
||||
|
||||
/*
|
||||
* General Functions
|
||||
*/
|
||||
void rtl8723f_init_hal_spec(PADAPTER); /* hal/hal_com.c */
|
||||
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
/* MP Functions */
|
||||
#include <rtw_mp.h> /* struct mp_priv */
|
||||
void rtl8723f_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */
|
||||
void rtl8723f_mp_config_rfpath(PADAPTER); /* hal_mp.c */
|
||||
#endif
|
||||
void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus);
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#include <rtl8723fu_hal.h>
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
#include <rtl8723fs_hal.h>
|
||||
#endif
|
||||
|
||||
#endif /* _RTL8723F_HAL_H_ */
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8723FS_HAL_H_
|
||||
#define _RTL8723FS_HAL_H_
|
||||
|
||||
#include <drv_types.h> /* PADAPTER */
|
||||
|
||||
/* rtl8723fs_ops.c */
|
||||
void rtl8723fs_set_hal_ops(PADAPTER);
|
||||
|
||||
#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
|
||||
void rtl8723fs_disable_interrupt_but_cpwm2(PADAPTER adapter);
|
||||
#endif
|
||||
|
||||
/* rtl8723fs_xmit.c */
|
||||
s32 rtl8723fs_dequeue_writeport(PADAPTER);
|
||||
#define _dequeue_writeport(a) rtl8723fs_dequeue_writeport(a)
|
||||
|
||||
#endif /* _RTL8723FS_HAL_H_ */
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2019 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL8723FU_HAL_H_
|
||||
#define _RTL8723FU_HAL_H_
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#include <drv_types.h> /* PADAPTER */
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
#ifdef USB_PACKET_OFFSET_SZ
|
||||
#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
|
||||
#else
|
||||
#define PACKET_OFFSET_SZ (8)
|
||||
#endif
|
||||
#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
|
||||
#endif
|
||||
|
||||
/* undefine MAX_RECVBUF_SZ from rtl8723f_hal.h */
|
||||
#ifdef MAX_RECVBUF_SZ
|
||||
#undef MAX_RECVBUF_SZ
|
||||
#endif
|
||||
|
||||
/* recv_buffer must be large than usb agg size */
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k */
|
||||
#elif defined(CONFIG_PLATFORM_HISILICON)
|
||||
/* use 16k to workaround for HISILICON platform */
|
||||
#define MAX_RECVBUF_SZ (16384)
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (32768)
|
||||
#endif
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000)
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
/* rtl8723fu_ops.c */
|
||||
void rtl8723fu_set_hal_ops(PADAPTER padapter);
|
||||
void rtl8723fu_set_hw_type(struct dvobj_priv *pdvobj);
|
||||
|
||||
/* rtl8723fu_io.c */
|
||||
void rtl8723fu_set_intf_ops(struct _io_ops *pops);
|
||||
|
||||
#endif /* CONFIG_USB_HCI */
|
||||
|
||||
|
||||
#endif /* _RTL8723FU_HAL_H_ */
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8812A_CMD_H__
|
||||
#define __RTL8812A_CMD_H__
|
||||
|
||||
typedef enum _RTL8812_H2C_CMD {
|
||||
H2C_8812_RSVDPAGE = 0,
|
||||
H2C_8812_MSRRPT = 1,
|
||||
H2C_8812_SCAN = 2,
|
||||
H2C_8812_KEEP_ALIVE_CTRL = 3,
|
||||
H2C_8812_DISCONNECT_DECISION = 4,
|
||||
|
||||
H2C_8812_INIT_OFFLOAD = 6,
|
||||
H2C_8812_AP_OFFLOAD = 8,
|
||||
H2C_8812_BCN_RSVDPAGE = 9,
|
||||
H2C_8812_PROBERSP_RSVDPAGE = 10,
|
||||
|
||||
H2C_8812_SETPWRMODE = 0x20,
|
||||
H2C_8812_PS_TUNING_PARA = 0x21,
|
||||
H2C_8812_PS_TUNING_PARA2 = 0x22,
|
||||
H2C_8812_PS_LPS_PARA = 0x23,
|
||||
H2C_8812_P2P_PS_OFFLOAD = 0x24,
|
||||
H2C_8812_INACTIVE_PS = 0x27,
|
||||
H2C_8812_RA_MASK = 0x40,
|
||||
H2C_8812_TxBF = 0x41,
|
||||
H2C_8812_RSSI_REPORT = 0x42,
|
||||
H2C_8812_IQ_CALIBRATION = 0x45,
|
||||
H2C_8812_RA_PARA_ADJUST = 0x46,
|
||||
|
||||
H2C_8812_BT_FW_PATCH = 0x6a,
|
||||
|
||||
H2C_8812_WO_WLAN = 0x80,
|
||||
H2C_8812_REMOTE_WAKE_CTRL = 0x81,
|
||||
H2C_8812_AOAC_GLOBAL_INFO = 0x82,
|
||||
H2C_8812_AOAC_RSVDPAGE = 0x83,
|
||||
H2C_8812_FW_SWCHANNL = 0x87,
|
||||
|
||||
H2C_8812_TSF_RESET = 0xC0,
|
||||
|
||||
MAX_8812_H2CCMD
|
||||
} RTL8812_H2C_CMD;
|
||||
|
||||
struct cmd_msg_parm {
|
||||
u8 eid; /* element id */
|
||||
u8 sz; /* sz */
|
||||
u8 buf[6];
|
||||
};
|
||||
|
||||
enum {
|
||||
PWRS
|
||||
};
|
||||
|
||||
struct H2C_SS_RFOFF_PARAM {
|
||||
u8 ROFOn; /* 1: on, 0:off */
|
||||
u16 gpio_period; /* unit: 1024 us */
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
|
||||
/* _RSVDPAGE_LOC_CMD0 */
|
||||
#define SET_8812_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
/* _SETPWRMODE_PARM */
|
||||
#define SET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
|
||||
#define SET_8812_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
|
||||
#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value)
|
||||
#define SET_8812_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
|
||||
|
||||
#define GET_8812_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
|
||||
|
||||
/* _P2P_PS_OFFLOAD */
|
||||
#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
|
||||
#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
|
||||
#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_CTWINDOW_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
|
||||
#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA0_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
|
||||
#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_NOA1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
|
||||
#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
|
||||
#define SET_8812_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
|
||||
|
||||
|
||||
void set_ra_ldpc_8812(struct cmn_sta_info *cmn_sta_info, BOOLEAN bLDPC);
|
||||
|
||||
/* host message to firmware cmd */
|
||||
s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
|
||||
void rtl8812_set_FwPwrMode_cmd(PADAPTER padapter, u8 PSMode);
|
||||
void rtl8812_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus);
|
||||
u8 rtl8812_set_rssi_cmd(PADAPTER padapter, u8 *param);
|
||||
void rtl8812_set_wowlan_cmd(_adapter *padapter, u8 enable);
|
||||
u8 GetTxBufferRsvdPageNum8812(_adapter *padapter, bool wowlan);
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8812a_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter);
|
||||
#endif /* CONFIG_BT_COEXIST */
|
||||
#ifdef CONFIG_P2P_PS
|
||||
void rtl8812_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
|
||||
#endif /* CONFIG_P2P */
|
||||
|
||||
#ifdef CONFIG_FWLPS_IN_IPS
|
||||
void rtl8812_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param);
|
||||
#endif
|
||||
|
||||
/* ------------------------------------
|
||||
* C2H format
|
||||
* ------------------------------------ */
|
||||
|
||||
/* TX Beamforming */
|
||||
#define GET_8812_C2H_TXBF_ORIGINATE(_Header) LE_BITS_TO_1BYTE(_Header, 0, 8)
|
||||
#define GET_8812_C2H_TXBF_MACID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
|
||||
|
||||
|
||||
|
||||
/* / TX Feedback Content */
|
||||
#define USEC_UNIT_FOR_8812_C2H_TX_RPT_QUEUE_TIME 256
|
||||
|
||||
#define GET_8812_C2H_TX_RPT_QUEUE_SELECT(_Header) LE_BITS_TO_1BYTE((_Header + 0), 0, 5)
|
||||
#define GET_8812_C2H_TX_RPT_PKT_BROCAST(_Header) LE_BITS_TO_1BYTE((_Header + 0), 5, 1)
|
||||
#define GET_8812_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
|
||||
#define GET_8812_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
|
||||
#define GET_8812_C2H_TX_RPT_MAC_ID(_Header) LE_BITS_TO_1BYTE((_Header + 1), 0, 8)
|
||||
#define GET_8812_C2H_TX_RPT_DATA_RETRY_CNT(_Header) LE_BITS_TO_1BYTE((_Header + 2), 0, 6)
|
||||
#define GET_8812_C2H_TX_RPT_QUEUE_TIME(_Header) LE_BITS_TO_2BYTE((_Header + 3), 0, 16) /* In unit of 256 microseconds. */
|
||||
#define GET_8812_C2H_TX_RPT_FINAL_DATA_RATE(_Header) LE_BITS_TO_1BYTE((_Header + 5), 0, 8)
|
||||
|
||||
/* BT_FW_PATCH */
|
||||
#define SET_8812_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((u8 *)(__pH2CCmd), 0, 16, __Value)
|
||||
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+2, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+3, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+4, 0, 8, __Value)
|
||||
#define SET_8812_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((u8 *)(__pH2CCmd)+5, 0, 8, __Value)
|
||||
|
||||
s32 c2h_handler_8812a(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload);
|
||||
|
||||
#endif/* __RTL8812A_CMD_H__ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8812A_DM_H__
|
||||
#define __RTL8812A_DM_H__
|
||||
|
||||
void rtl8812_init_dm_priv(PADAPTER Adapter);
|
||||
void rtl8812_deinit_dm_priv(PADAPTER Adapter);
|
||||
void rtl8812_InitHalDm(PADAPTER Adapter);
|
||||
void rtl8812_HalDmWatchDog(PADAPTER Adapter);
|
||||
|
||||
/* void rtl8192c_dm_CheckTXPowerTracking(PADAPTER Adapter); */
|
||||
|
||||
/* void rtl8192c_dm_RF_Saving(PADAPTER pAdapter, u8 bForceInNormal); */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,369 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8812A_HAL_H__
|
||||
#define __RTL8812A_HAL_H__
|
||||
|
||||
/* #include "hal_com.h" */
|
||||
#include "hal_data.h"
|
||||
|
||||
/* include HAL Related header after HAL Related compiling flags */
|
||||
#include "rtl8812a_spec.h"
|
||||
#include "rtl8812a_rf.h"
|
||||
#include "rtl8812a_dm.h"
|
||||
#include "rtl8812a_recv.h"
|
||||
#include "rtl8812a_xmit.h"
|
||||
#include "rtl8812a_cmd.h"
|
||||
#include "rtl8812a_led.h"
|
||||
#include "Hal8812PwrSeq.h"
|
||||
#include "Hal8821APwrSeq.h" /* for 8821A/8811A */
|
||||
#include "Hal8812PhyReg.h"
|
||||
#include "Hal8812PhyCfg.h"
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
#include "rtl8812a_sreset.h"
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* RTL8812 Power Configuration CMDs for PCIe interface
|
||||
* --------------------------------------------------------------------- */
|
||||
#define Rtl8812_NIC_PWR_ON_FLOW rtl8812_power_on_flow
|
||||
#define Rtl8812_NIC_RF_OFF_FLOW rtl8812_radio_off_flow
|
||||
#define Rtl8812_NIC_DISABLE_FLOW rtl8812_card_disable_flow
|
||||
#define Rtl8812_NIC_ENABLE_FLOW rtl8812_card_enable_flow
|
||||
#define Rtl8812_NIC_SUSPEND_FLOW rtl8812_suspend_flow
|
||||
#define Rtl8812_NIC_RESUME_FLOW rtl8812_resume_flow
|
||||
#define Rtl8812_NIC_PDN_FLOW rtl8812_hwpdn_flow
|
||||
#define Rtl8812_NIC_LPS_ENTER_FLOW rtl8812_enter_lps_flow
|
||||
#define Rtl8812_NIC_LPS_LEAVE_FLOW rtl8812_leave_lps_flow
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* RTL8821 Power Configuration CMDs for PCIe interface
|
||||
* --------------------------------------------------------------------- */
|
||||
#define Rtl8821A_NIC_PWR_ON_FLOW rtl8821A_power_on_flow
|
||||
#define Rtl8821A_NIC_RF_OFF_FLOW rtl8821A_radio_off_flow
|
||||
#define Rtl8821A_NIC_DISABLE_FLOW rtl8821A_card_disable_flow
|
||||
#define Rtl8821A_NIC_ENABLE_FLOW rtl8821A_card_enable_flow
|
||||
#define Rtl8821A_NIC_SUSPEND_FLOW rtl8821A_suspend_flow
|
||||
#define Rtl8821A_NIC_RESUME_FLOW rtl8821A_resume_flow
|
||||
#define Rtl8821A_NIC_PDN_FLOW rtl8821A_hwpdn_flow
|
||||
#define Rtl8821A_NIC_LPS_ENTER_FLOW rtl8821A_enter_lps_flow
|
||||
#define Rtl8821A_NIC_LPS_LEAVE_FLOW rtl8821A_leave_lps_flow
|
||||
|
||||
|
||||
#if 1 /* download firmware related data structure */
|
||||
#define FW_SIZE_8812 0x8000 /* Compatible with RTL8723 Maximal RAM code size 24K. modified to 32k, TO compatible with 92d maximal fw size 32k */
|
||||
#define FW_START_ADDRESS 0x1000
|
||||
#define FW_END_ADDRESS 0x5FFF
|
||||
|
||||
|
||||
|
||||
typedef struct _RT_FIRMWARE_8812 {
|
||||
FIRMWARE_SOURCE eFWSource;
|
||||
#ifdef CONFIG_EMBEDDED_FWIMG
|
||||
u8 *szFwBuffer;
|
||||
#else
|
||||
u8 szFwBuffer[FW_SIZE_8812];
|
||||
#endif
|
||||
u32 ulFwLength;
|
||||
} RT_FIRMWARE_8812, *PRT_FIRMWARE_8812;
|
||||
|
||||
/*
|
||||
* This structure must be cared byte-ordering
|
||||
*
|
||||
* Added by tynli. 2009.12.04. */
|
||||
#define IS_FW_HEADER_EXIST_8812(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x9500)
|
||||
|
||||
#define IS_FW_HEADER_EXIST_8821(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE_8812(_pFwHdr) & 0xFFF0) == 0x2100)
|
||||
/* *****************************************************
|
||||
* Firmware Header(8-byte alinment required)
|
||||
* *****************************************************
|
||||
* --- LONG WORD 0 ---- */
|
||||
#define GET_FIRMWARE_HDR_SIGNATURE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */
|
||||
#define GET_FIRMWARE_HDR_CATEGORY_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */
|
||||
#define GET_FIRMWARE_HDR_FUNCTION_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */
|
||||
#define GET_FIRMWARE_HDR_VERSION_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */
|
||||
#define GET_FIRMWARE_HDR_SUB_VER_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */
|
||||
#define GET_FIRMWARE_HDR_RSVD1_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8)
|
||||
|
||||
/* --- LONG WORD 1 ---- */
|
||||
#define GET_FIRMWARE_HDR_MONTH_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */
|
||||
#define GET_FIRMWARE_HDR_DATE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */
|
||||
#define GET_FIRMWARE_HDR_HOUR_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */
|
||||
#define GET_FIRMWARE_HDR_MINUTE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */
|
||||
#define GET_FIRMWARE_HDR_ROMCODE_SIZE_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */
|
||||
#define GET_FIRMWARE_HDR_RSVD2_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16)
|
||||
|
||||
/* --- LONG WORD 2 ---- */
|
||||
#define GET_FIRMWARE_HDR_SVN_IDX_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */
|
||||
#define GET_FIRMWARE_HDR_RSVD3_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32)
|
||||
|
||||
/* --- LONG WORD 3 ---- */
|
||||
#define GET_FIRMWARE_HDR_RSVD4_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32)
|
||||
#define GET_FIRMWARE_HDR_RSVD5_8812(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32)
|
||||
|
||||
#endif /* download firmware related data structure */
|
||||
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8812 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8812 0x02
|
||||
|
||||
/* for 8812
|
||||
* TX 128K, RX 16K, Page size 512B for TX, 128B for RX */
|
||||
#define MAX_RX_DMA_BUFFER_SIZE_8812 0x3E80 /* RX 16K */
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/
|
||||
#else
|
||||
#define RESV_FMWF 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8812 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8812 0x0 /* 0B */
|
||||
#endif
|
||||
#define RX_DMA_BOUNDARY_8812 (MAX_RX_DMA_BUFFER_SIZE_8812 - RX_DMA_RESERVED_SIZE_8812 - 1)
|
||||
|
||||
#define PAGE_SIZE_TX_8812A PAGE_SIZE_512
|
||||
|
||||
/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8812A
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
|
||||
#define BCNQ_PAGE_NUM_8812 (MAX_BEACON_LEN / PAGE_SIZE_TX_8812A + 6) /*0x07*/
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, AOAC rpt: 1,PNO: 6
|
||||
* NS offload: 1 NDP info: 1
|
||||
*/
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8812 0x08
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8812 0x00
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_BEAMFORMER_FW_NDPA
|
||||
#define FW_NDPA_PAGE_NUM 0x02
|
||||
#else
|
||||
#define FW_NDPA_PAGE_NUM 0x00
|
||||
#endif
|
||||
|
||||
#ifdef DBG_FW_DEBUG_MSG_PKT
|
||||
#define FW_DBG_MSG_PKT_PAGE_NUM_8812 0x01
|
||||
#else
|
||||
#define FW_DBG_MSG_PKT_PAGE_NUM_8812 0x00
|
||||
#endif /*DBG_FW_DEBUG_MSG_PKT*/
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 - FW_NDPA_PAGE_NUM - FW_DBG_MSG_PKT_PAGE_NUM_8812)
|
||||
#define TX_PAGE_BOUNDARY_8812 (TX_TOTAL_PAGE_NUMBER_8812 + 1)
|
||||
|
||||
#define TX_PAGE_BOUNDARY_WOWLAN_8812 (0xFF - BCNQ_PAGE_NUM_8812 - WOWLAN_PAGE_NUM_8812 + 1)
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 TX_TOTAL_PAGE_NUMBER_8812
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8812 (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8812 + 1)
|
||||
|
||||
/* For Normal Chip Setting
|
||||
* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8812 */
|
||||
#define NORMAL_PAGE_NUM_LPQ_8812 0x10
|
||||
#define NORMAL_PAGE_NUM_HPQ_8812 0x10
|
||||
#define NORMAL_PAGE_NUM_NPQ_8812 0x00
|
||||
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8812 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8812 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8812 0x20
|
||||
|
||||
|
||||
/* for 8821A
|
||||
* TX 64K, RX 16K, Page size 256B for TX, 128B for RX */
|
||||
#define PAGE_SIZE_TX_8821A 256
|
||||
#define PAGE_SIZE_RX_8821A 128
|
||||
|
||||
#define MAX_RX_DMA_BUFFER_SIZE_8821 0x3E80 /* RX 16K */
|
||||
|
||||
#ifdef CONFIG_FW_C2H_DEBUG
|
||||
#define RX_DMA_RESERVED_SIZE_8821 0x100 /* 256B, reserved for c2h debug message */
|
||||
#else
|
||||
#define RX_DMA_RESERVED_SIZE_8821 0x0 /* 0B */
|
||||
#endif
|
||||
#define RX_DMA_BOUNDARY_8821 (MAX_RX_DMA_BUFFER_SIZE_8821 - RX_DMA_RESERVED_SIZE_8821 - 1)
|
||||
|
||||
/* Beacon:MAX_BEACON_LEN/PAGE_SIZE_TX_8821A
|
||||
* PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1,CTS-2-SELF,LTE QoS Null*/
|
||||
|
||||
#define BCNQ_PAGE_NUM_8821 (MAX_BEACON_LEN / PAGE_SIZE_TX_8821A + 6) /*0x08*/
|
||||
|
||||
|
||||
/* For WoWLan , more reserved page
|
||||
* ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:1,GTK EXT MEM:1, PNO: 6 */
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define WOWLAN_PAGE_NUM_8821 0x06
|
||||
#else
|
||||
#define WOWLAN_PAGE_NUM_8821 0x00
|
||||
#endif
|
||||
|
||||
#define TX_TOTAL_PAGE_NUMBER_8821 (0xFF - BCNQ_PAGE_NUM_8821 - WOWLAN_PAGE_NUM_8821)
|
||||
#define TX_PAGE_BOUNDARY_8821 (TX_TOTAL_PAGE_NUMBER_8821 + 1)
|
||||
/* #define TX_PAGE_BOUNDARY_WOWLAN_8821 0xE0 */
|
||||
|
||||
#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 TX_TOTAL_PAGE_NUMBER_8821
|
||||
#define WMM_NORMAL_TX_PAGE_BOUNDARY_8821 (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8821 + 1)
|
||||
|
||||
|
||||
/* (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
|
||||
#define NORMAL_PAGE_NUM_LPQ_8821 0x08/* 0x10 */
|
||||
#define NORMAL_PAGE_NUM_HPQ_8821 0x08/* 0x10 */
|
||||
#define NORMAL_PAGE_NUM_NPQ_8821 0x00
|
||||
#define NORMAL_PAGE_NUM_EPQ_8821 0x04
|
||||
|
||||
#define WMM_NORMAL_PAGE_NUM_HPQ_8821 0x30
|
||||
#define WMM_NORMAL_PAGE_NUM_LPQ_8821 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_NPQ_8821 0x20
|
||||
#define WMM_NORMAL_PAGE_NUM_EPQ_8821 0x00
|
||||
|
||||
#define MCC_NORMAL_PAGE_NUM_HPQ_8821 0x10
|
||||
#define MCC_NORMAL_PAGE_NUM_LPQ_8821 0x10
|
||||
#define MCC_NORMAL_PAGE_NUM_NPQ_8821 0x10
|
||||
|
||||
#define EFUSE_HIDDEN_812AU 0
|
||||
#define EFUSE_HIDDEN_812AU_VS 1
|
||||
#define EFUSE_HIDDEN_812AU_VL 2
|
||||
#define EFUSE_HIDDEN_812AU_VN 3
|
||||
|
||||
#if 0
|
||||
#define EFUSE_REAL_CONTENT_LEN_JAGUAR 1024
|
||||
#define HWSET_MAX_SIZE_JAGUAR 1024
|
||||
#else
|
||||
#define EFUSE_REAL_CONTENT_LEN_JAGUAR 512
|
||||
#define HWSET_MAX_SIZE_JAGUAR 512
|
||||
#endif
|
||||
|
||||
#define EFUSE_MAX_BANK_8812A 2
|
||||
#define EFUSE_MAP_LEN_JAGUAR 512
|
||||
#define EFUSE_MAX_SECTION_JAGUAR 64
|
||||
#define EFUSE_MAX_WORD_UNIT_JAGUAR 4
|
||||
#define EFUSE_IC_ID_OFFSET_JAGUAR 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */
|
||||
#define AVAILABLE_EFUSE_ADDR_8812(addr) (addr < EFUSE_REAL_CONTENT_LEN_JAGUAR)
|
||||
/* <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
|
||||
* 9bytes + 1byt + 5bytes and pre 1byte.
|
||||
* For worst case:
|
||||
* | 2byte|----8bytes----|1byte|--7bytes--| */ /* 92D */
|
||||
#define EFUSE_OOB_PROTECT_BYTES_JAGUAR 18 /* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
|
||||
#define EFUSE_PROTECT_BYTES_BANK_JAGUAR 16
|
||||
|
||||
#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
|
||||
#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
|
||||
|
||||
/* #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */
|
||||
|
||||
/* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */
|
||||
#define HAL_EFUSE_MEMORY
|
||||
|
||||
/* ********************************************************
|
||||
* EFUSE for BT definition
|
||||
* ******************************************************** */
|
||||
#define BANK_NUM 2
|
||||
#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512
|
||||
#define EFUSE_BT_REAL_CONTENT_LEN \
|
||||
(EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM)
|
||||
#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
|
||||
#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8)
|
||||
#define EFUSE_PROTECT_BYTES_BANK 16
|
||||
|
||||
#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_BT_REAL_CONTENT_LEN)
|
||||
|
||||
#ifdef CONFIG_FILE_FWIMG
|
||||
extern char *rtw_fw_file_path;
|
||||
#ifdef CONFIG_WOWLAN
|
||||
extern char *rtw_fw_wow_file_path;
|
||||
#endif
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
extern char *rtw_fw_mp_bt_file_path;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* rtl8812_hal_init.c */
|
||||
void _8051Reset8812(PADAPTER padapter);
|
||||
s32 FirmwareDownload8812(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw);
|
||||
void InitializeFirmwareVars8812(PADAPTER padapter);
|
||||
|
||||
s32 _LLTWrite_8812A(PADAPTER Adapter, u32 address, u32 data);
|
||||
s32 InitLLTTable8812A(PADAPTER padapter, u8 txpktbuf_bndy);
|
||||
void InitRDGSetting8812A(PADAPTER padapter);
|
||||
|
||||
void CheckAutoloadState8812A(PADAPTER padapter);
|
||||
|
||||
/* EFuse */
|
||||
u8 GetEEPROMSize8812A(PADAPTER padapter);
|
||||
void InitPGData8812A(PADAPTER padapter);
|
||||
void Hal_EfuseParseIDCode8812A(PADAPTER padapter, u8 *hwinfo);
|
||||
void Hal_ReadPROMVersion8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadTxPowerInfo8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadBoardType8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadThermalMeter_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadChannelPlan8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_EfuseParseXtal_8812A(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadAntennaDiversity8812A(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail);
|
||||
void Hal_ReadAmplifierType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadPAType_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_ReadRFEType_8812A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
void Hal_EfuseParseBTCoexistInfo8812A(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
void hal_ReadUsbType_8812AU(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
#ifdef CONFIG_MP_INCLUDED
|
||||
int FirmwareDownloadBT(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware);
|
||||
#endif
|
||||
void Hal_ReadRemoteWakeup_8812A(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
||||
|
||||
BOOLEAN HalDetectPwrDownMode8812(PADAPTER Adapter);
|
||||
void Hal_EfuseParseKFreeData_8821A(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail);
|
||||
|
||||
#ifdef CONFIG_WOWLAN
|
||||
void Hal_DetectWoWMode(PADAPTER pAdapter);
|
||||
#endif /* CONFIG_WOWLAN */
|
||||
|
||||
void _InitBeaconParameters_8812A(PADAPTER padapter);
|
||||
void SetBeaconRelatedRegisters8812A(PADAPTER padapter);
|
||||
|
||||
void ReadRFType8812A(PADAPTER padapter);
|
||||
void InitDefaultValue8821A(PADAPTER padapter);
|
||||
|
||||
u8 SetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
|
||||
void GetHwReg8812A(PADAPTER padapter, u8 variable, u8 *pval);
|
||||
u8 SetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
u8 GetHalDefVar8812A(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval);
|
||||
void rtl8812_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void init_hal_spec_8812a(_adapter *adapter);
|
||||
void init_hal_spec_8821a(_adapter *adapter);
|
||||
|
||||
u32 upload_txpktbuf_8812au(_adapter *adapter, u8 *buf, u32 buflen);
|
||||
|
||||
void rtl8812_start_thread(PADAPTER padapter);
|
||||
void rtl8812_stop_thread(PADAPTER padapter);
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
BOOLEAN InterruptRecognized8812AE(PADAPTER Adapter);
|
||||
void UpdateInterruptMask8812AE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1);
|
||||
void InitTRXDescHwAddress8812AE(PADAPTER Adapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BT_COEXIST
|
||||
void rtl8812a_combo_card_WifiOnlyHwInit(PADAPTER Adapter);
|
||||
#endif
|
||||
|
||||
void
|
||||
Hal_PatchwithJaguar_8812(
|
||||
PADAPTER Adapter,
|
||||
RT_MEDIA_STATUS MediaStatus
|
||||
);
|
||||
|
||||
#endif /* __RTL8188E_HAL_H__ */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8812A_LED_H__
|
||||
#define __RTL8812A_LED_H__
|
||||
#ifdef CONFIG_RTW_LED
|
||||
#ifdef CONFIG_RTW_SW_LED
|
||||
/* ********************************************************************************
|
||||
* Interface to manipulate LED objects.
|
||||
* ******************************************************************************** */
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8812au_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8812au_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
void rtl8812ae_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8812ae_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8821as_InitSwLeds(PADAPTER padapter);
|
||||
void rtl8821as_DeInitSwLeds(PADAPTER padapter);
|
||||
#endif
|
||||
#endif/*CONFIG_RTW_SW_LED*/
|
||||
#endif/*#ifdef CONFIG_RTW_LED*/
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
void rtl8821as_init_led_circuit(PADAPTER adapter);
|
||||
#endif
|
||||
|
||||
#endif /*__RTL8812A_LED_H__*/
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8812A_RECV_H__
|
||||
#define __RTL8812A_RECV_H__
|
||||
|
||||
#if defined(CONFIG_USB_HCI)
|
||||
|
||||
#ifndef MAX_RECVBUF_SZ
|
||||
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
|
||||
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
|
||||
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (32768) /*32k*/
|
||||
#endif
|
||||
/* #define MAX_RECVBUF_SZ (24576) */ /* 24k */
|
||||
/* #define MAX_RECVBUF_SZ (20480) */ /* 20K */
|
||||
/* #define MAX_RECVBUF_SZ (10240) */ /* 10K */
|
||||
/* #define MAX_RECVBUF_SZ (15360) */ /* 15k < 16k */
|
||||
/* #define MAX_RECVBUF_SZ (8192+1024) */ /* 8K+1k */
|
||||
#ifdef CONFIG_PLATFORM_NOVATEK_NT72668
|
||||
#undef MAX_RECVBUF_SZ
|
||||
#define MAX_RECVBUF_SZ (15360) /* 15k < 16k */
|
||||
#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */
|
||||
#else
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K */
|
||||
#endif
|
||||
#endif /* !MAX_RECVBUF_SZ */
|
||||
|
||||
#elif defined(CONFIG_PCI_HCI)
|
||||
/* #ifndef CONFIG_MINIMAL_MEMORY_USAGE */
|
||||
/* #define MAX_RECVBUF_SZ (9100) */
|
||||
/* #else */
|
||||
#define MAX_RECVBUF_SZ (4000) /* about 4K
|
||||
* #endif */
|
||||
|
||||
|
||||
#elif defined(CONFIG_SDIO_HCI)
|
||||
|
||||
#define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8821 + 1)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Rx smooth factor */
|
||||
#define Rx_Smooth_Factor (20)
|
||||
|
||||
/* DWORD 0 */
|
||||
#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 0, 14, __Value)
|
||||
#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 30, 1, __Value)
|
||||
#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxStatusDesc, 31, 1, __Value)
|
||||
|
||||
#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 14)
|
||||
#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 20, 3)
|
||||
#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 24, 2)
|
||||
#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 28, 1)
|
||||
#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc, 31, 1)
|
||||
|
||||
/* DWORD 1 */
|
||||
#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
|
||||
#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
|
||||
#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 14, 1)
|
||||
#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 15, 1)
|
||||
#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 16, 4)
|
||||
#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 20, 1)
|
||||
#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
|
||||
#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
|
||||
#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
|
||||
#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 24, 1)
|
||||
#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 25, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 26, 1)
|
||||
#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 27, 1)
|
||||
#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 28, 2)
|
||||
#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 31, 1)
|
||||
|
||||
/* DWORD 2 */
|
||||
#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 0, 12)
|
||||
#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 12, 4)
|
||||
#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 16, 1)
|
||||
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 18, 6)
|
||||
#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+8, 28, 1)
|
||||
|
||||
/* DWORD 3 */
|
||||
#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 0, 7)
|
||||
#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 10, 1)
|
||||
#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 11, 1)
|
||||
#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 12, 2)
|
||||
#ifdef CONFIG_USB_RX_AGGREGATION
|
||||
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+12, 16, 8)
|
||||
#endif
|
||||
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 29, 1)
|
||||
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 30, 1)
|
||||
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+12, 31, 1)
|
||||
|
||||
/* DWORD 6 */
|
||||
#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 0, 1)
|
||||
#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 1, 1)
|
||||
#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 2, 1)
|
||||
#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+16, 4, 2)
|
||||
|
||||
/* DWORD 5 */
|
||||
#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
|
||||
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
|
||||
|
||||
#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
|
||||
|
||||
|
||||
#ifdef CONFIG_SDIO_HCI
|
||||
s32 InitRecvPriv8821AS(PADAPTER padapter);
|
||||
void FreeRecvPriv8821AS(PADAPTER padapter);
|
||||
#endif /* CONFIG_SDIO_HCI */
|
||||
|
||||
#ifdef CONFIG_USB_HCI
|
||||
void rtl8812au_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf);
|
||||
s32 rtl8812au_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8812au_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
s32 rtl8812ae_init_recv_priv(PADAPTER padapter);
|
||||
void rtl8812ae_free_recv_priv(PADAPTER padapter);
|
||||
#endif
|
||||
|
||||
void rtl8812_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
|
||||
|
||||
#endif /* __RTL8812A_RECV_H__ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8812A_RF_H__
|
||||
#define __RTL8812A_RF_H__
|
||||
|
||||
void
|
||||
PHY_RF6052SetBandwidth8812(
|
||||
PADAPTER Adapter,
|
||||
enum channel_width Bandwidth);
|
||||
|
||||
|
||||
int
|
||||
PHY_RF6052_Config_8812(
|
||||
PADAPTER Adapter);
|
||||
|
||||
#endif/* __RTL8188E_RF_H__ */
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef __RTL8812A_SPEC_H__
|
||||
#define __RTL8812A_SPEC_H__
|
||||
|
||||
#include <drv_conf.h>
|
||||
|
||||
|
||||
/* ************************************************************
|
||||
* 8812 Regsiter offset definition
|
||||
* ************************************************************ */
|
||||
|
||||
/* ************************************************************
|
||||
*
|
||||
* ************************************************************ */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0000h ~ 0x00FFh System Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_SYS_CLKR_8812A 0x0008
|
||||
#define REG_AFE_PLL_CTRL_8812A 0x0028
|
||||
#define REG_HSIMR_8812 0x0058
|
||||
#define REG_HSISR_8812 0x005c
|
||||
#define REG_GPIO_EXT_CTRL 0x0060
|
||||
#define REG_GPIO_STATUS_8812 0x006C
|
||||
#define REG_SDIO_CTRL_8812 0x0070
|
||||
#define REG_OPT_CTRL_8812 0x0074
|
||||
#define REG_RF_B_CTRL_8812 0x0076
|
||||
#define REG_FW_DRV_MSG_8812 0x0088
|
||||
#define REG_HMEBOX_E2_E3_8812 0x008C
|
||||
#define REG_HIMR0_8812 0x00B0
|
||||
#define REG_HISR0_8812 0x00B4
|
||||
#define REG_HIMR1_8812 0x00B8
|
||||
#define REG_HISR1_8812 0x00BC
|
||||
#define REG_EFUSE_BURN_GNT_8812 0x00CF
|
||||
#define REG_SYS_CFG1_8812 0x00FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0100h ~ 0x01FFh MACTOP General Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_CR_8812A 0x100
|
||||
#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
|
||||
#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
|
||||
#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
|
||||
#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
|
||||
|
||||
#define REG_RSVD3_8812 0x0168
|
||||
#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
|
||||
#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
|
||||
#define REG_C2HEVT_CMD_LEN_88XX 0x01AE
|
||||
|
||||
#define REG_HMEBOX_EXT0_8812 0x01F0
|
||||
#define REG_HMEBOX_EXT1_8812 0x01F4
|
||||
#define REG_HMEBOX_EXT2_8812 0x01F8
|
||||
#define REG_HMEBOX_EXT3_8812 0x01FC
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0200h ~ 0x027Fh TXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_DWBCN0_CTRL_8812 REG_TDECTRL
|
||||
#define REG_DWBCN1_CTRL_8812 0x0228
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0280h ~ 0x02FFh RXDMA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_TDECTRL_8812A 0x0208
|
||||
#define REG_RXDMA_CONTROL_8812A 0x0286 /*Control the RX DMA.*/
|
||||
#define REG_RXDMA_PRO_8812 0x0290
|
||||
#define REG_EARLY_MODE_CONTROL_8812 0x02BC
|
||||
#define REG_RSVD5_8812 0x02F0
|
||||
#define REG_RSVD6_8812 0x02F4
|
||||
#define REG_RSVD7_8812 0x02F8
|
||||
#define REG_RSVD8_8812 0x02FC
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0300h ~ 0x03FFh PCIe
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_PCIE_CTRL_REG_8812A 0x0300
|
||||
#define REG_DBI_WDATA_8812 0x0348 /* DBI Write Data */
|
||||
#define REG_DBI_RDATA_8812 0x034C /* DBI Read Data */
|
||||
#define REG_DBI_ADDR_8812 0x0350 /* DBI Address */
|
||||
#define REG_DBI_FLAG_8812 0x0352 /* DBI Read/Write Flag */
|
||||
#define REG_MDIO_WDATA_8812 0x0354 /* MDIO for Write PCIE PHY */
|
||||
#define REG_MDIO_RDATA_8812 0x0356 /* MDIO for Reads PCIE PHY */
|
||||
#define REG_MDIO_CTL_8812 0x0358 /* MDIO for Control */
|
||||
#define REG_PCIE_HRPWM_8812A 0x0361 /* PCIe RPWM */
|
||||
#define REG_PCIE_HCPWM_8812A 0x0363 /* PCIe CPWM */
|
||||
|
||||
#define REG_PCIE_MULTIFET_CTRL_8812 0x036A /* PCIE Multi-Fethc Control */
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0400h ~ 0x047Fh Protocol Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_TXPKT_EMPTY_8812A 0x041A
|
||||
#define REG_FWHW_TXQ_CTRL_8812A 0x0420
|
||||
#define REG_TXBF_CTRL_8812A 0x042C
|
||||
#define REG_ARFR0_8812 0x0444
|
||||
#define REG_ARFR1_8812 0x044C
|
||||
#define REG_CCK_CHECK_8812 0x0454
|
||||
#define REG_AMPDU_MAX_TIME_8812 0x0456
|
||||
#define REG_TXPKTBUF_BCNQ_BDNY1_8812 0x0457
|
||||
|
||||
#define REG_AMPDU_MAX_LENGTH_8812 0x0458
|
||||
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8812 0x045D
|
||||
#define REG_NDPA_OPT_CTRL_8812A 0x045F
|
||||
#define REG_DATA_SC_8812 0x0483
|
||||
#ifdef CONFIG_WOWLAN
|
||||
#define REG_TXPKTBUF_IV_LOW 0x0484
|
||||
#define REG_TXPKTBUF_IV_HIGH 0x0488
|
||||
#endif
|
||||
#define REG_ARFR2_8812 0x048C
|
||||
#define REG_ARFR3_8812 0x0494
|
||||
#define REG_TXRPT_START_OFFSET 0x04AC
|
||||
#define REG_AMPDU_BURST_MODE_8812 0x04BC
|
||||
#define REG_HT_SINGLE_AMPDU_8812 0x04C7
|
||||
#define REG_MACID_PKT_DROP0_8812 0x04D0
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0500h ~ 0x05FFh EDCA Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_TXPAUSE_8812A 0x0522
|
||||
#define REG_CTWND_8812 0x0572
|
||||
#define REG_SECONDARY_CCA_CTRL_8812 0x0577
|
||||
#define REG_SCH_TXCMD_8812A 0x05F8
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* 0x0600h ~ 0x07FFh WMAC Configuration
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
#define REG_MAC_CR_8812 0x0600
|
||||
|
||||
#define REG_MAC_TX_SM_STATE_8812 0x06B4
|
||||
|
||||
/* Power */
|
||||
#define REG_BFMER0_INFO_8812A 0x06E4
|
||||
#define REG_BFMER1_INFO_8812A 0x06EC
|
||||
#define REG_CSI_RPT_PARAM_BW20_8812A 0x06F4
|
||||
#define REG_CSI_RPT_PARAM_BW40_8812A 0x06F8
|
||||
#define REG_CSI_RPT_PARAM_BW80_8812A 0x06FC
|
||||
|
||||
/* Hardware Port 2 */
|
||||
#define REG_BFMEE_SEL_8812A 0x0714
|
||||
#define REG_SND_PTCL_CTRL_8812A 0x0718
|
||||
|
||||
|
||||
/* -----------------------------------------------------
|
||||
*
|
||||
* Redifine register definition for compatibility
|
||||
*
|
||||
* ----------------------------------------------------- */
|
||||
|
||||
/* TODO: use these definition when using REG_xxx naming rule.
|
||||
* NOTE: DO NOT Remove these definition. Use later. */
|
||||
#define ISR_8812 REG_HISR0_8812
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
* 8195 IMR/ISR bits (offset 0xB0, 8bits)
|
||||
* ---------------------------------------------------------------------------- */
|
||||
#define IMR_DISABLED_8812 0
|
||||
/* IMR DW0(0x00B0-00B3) Bit 0-31 */
|
||||
#define IMR_TIMER2_8812 BIT31 /* Timeout interrupt 2 */
|
||||
#define IMR_TIMER1_8812 BIT30 /* Timeout interrupt 1 */
|
||||
#define IMR_PSTIMEOUT_8812 BIT29 /* Power Save Time Out Interrupt */
|
||||
#define IMR_GTINT4_8812 BIT28 /* When GTIMER4 expires, this bit is set to 1 */
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||||
#define IMR_GTINT3_8812 BIT27 /* When GTIMER3 expires, this bit is set to 1 */
|
||||
#define IMR_TXBCN0ERR_8812 BIT26 /* Transmit Beacon0 Error */
|
||||
#define IMR_TXBCN0OK_8812 BIT25 /* Transmit Beacon0 OK */
|
||||
#define IMR_TSF_BIT32_TOGGLE_8812 BIT24 /* TSF Timer BIT32 toggle indication interrupt */
|
||||
#define IMR_BCNDMAINT0_8812 BIT20 /* Beacon DMA Interrupt 0 */
|
||||
#define IMR_BCNDERR0_8812 BIT16 /* Beacon Queue DMA OK0 */
|
||||
#define IMR_HSISR_IND_ON_INT_8812 BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
|
||||
#define IMR_BCNDMAINT_E_8812 BIT14 /* Beacon DMA Interrupt Extension for Win7 */
|
||||
#define IMR_ATIMEND_8812 BIT12 /* CTWidnow End or ATIM Window End */
|
||||
#define IMR_C2HCMD_8812 BIT10 /* CPU to Host Command INT Status, Write 1 clear */
|
||||
#define IMR_CPWM2_8812 BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_CPWM_8812 BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
|
||||
#define IMR_HIGHDOK_8812 BIT7 /* High Queue DMA OK */
|
||||
#define IMR_MGNTDOK_8812 BIT6 /* Management Queue DMA OK */
|
||||
#define IMR_BKDOK_8812 BIT5 /* AC_BK DMA OK */
|
||||
#define IMR_BEDOK_8812 BIT4 /* AC_BE DMA OK */
|
||||
#define IMR_VIDOK_8812 BIT3 /* AC_VI DMA OK */
|
||||
#define IMR_VODOK_8812 BIT2 /* AC_VO DMA OK */
|
||||
#define IMR_RDU_8812 BIT1 /* Rx Descriptor Unavailable */
|
||||
#define IMR_ROK_8812 BIT0 /* Receive DMA OK */
|
||||
|
||||
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
|
||||
#define IMR_BCNDMAINT7_8812 BIT27 /* Beacon DMA Interrupt 7 */
|
||||
#define IMR_BCNDMAINT6_8812 BIT26 /* Beacon DMA Interrupt 6 */
|
||||
#define IMR_BCNDMAINT5_8812 BIT25 /* Beacon DMA Interrupt 5 */
|
||||
#define IMR_BCNDMAINT4_8812 BIT24 /* Beacon DMA Interrupt 4 */
|
||||
#define IMR_BCNDMAINT3_8812 BIT23 /* Beacon DMA Interrupt 3 */
|
||||
#define IMR_BCNDMAINT2_8812 BIT22 /* Beacon DMA Interrupt 2 */
|
||||
#define IMR_BCNDMAINT1_8812 BIT21 /* Beacon DMA Interrupt 1 */
|
||||
#define IMR_BCNDOK7_8812 BIT20 /* Beacon Queue DMA OK Interrup 7 */
|
||||
#define IMR_BCNDOK6_8812 BIT19 /* Beacon Queue DMA OK Interrup 6 */
|
||||
#define IMR_BCNDOK5_8812 BIT18 /* Beacon Queue DMA OK Interrup 5 */
|
||||
#define IMR_BCNDOK4_8812 BIT17 /* Beacon Queue DMA OK Interrup 4 */
|
||||
#define IMR_BCNDOK3_8812 BIT16 /* Beacon Queue DMA OK Interrup 3 */
|
||||
#define IMR_BCNDOK2_8812 BIT15 /* Beacon Queue DMA OK Interrup 2 */
|
||||
#define IMR_BCNDOK1_8812 BIT14 /* Beacon Queue DMA OK Interrup 1 */
|
||||
#define IMR_ATIMEND_E_8812 BIT13 /* ATIM Window End Extension for Win7 */
|
||||
#define IMR_TXERR_8812 BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
|
||||
#define IMR_RXERR_8812 BIT10 /* Rx Error Flag INT Status, Write 1 clear */
|
||||
#define IMR_TXFOVW_8812 BIT9 /* Transmit FIFO Overflow */
|
||||
#define IMR_RXFOVW_8812 BIT8 /* Receive FIFO Overflow */
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI_HCI
|
||||
/* #define IMR_RX_MASK (IMR_ROK_8812|IMR_RDU_8812|IMR_RXFOVW_8812) */
|
||||
#define IMR_TX_MASK (IMR_VODOK_8812 | IMR_VIDOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812 | IMR_MGNTDOK_8812 | IMR_HIGHDOK_8812)
|
||||
|
||||
#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8812 | IMR_TXBCN0OK_8812 | IMR_TXBCN0ERR_8812 | IMR_BCNDERR0_8812)
|
||||
|
||||
#define RT_AC_INT_MASKS (IMR_VIDOK_8812 | IMR_VODOK_8812 | IMR_BEDOK_8812 | IMR_BKDOK_8812)
|
||||
#endif
|
||||
|
||||
|
||||
/* ****************************************************************************
|
||||
* Regsiter Bit and Content definition
|
||||
* **************************************************************************** */
|
||||
|
||||
/* 2 ACMHWCTRL 0x05C0 */
|
||||
#define AcmHw_HwEn_8812 BIT(0)
|
||||
#define AcmHw_VoqEn_8812 BIT(1)
|
||||
#define AcmHw_ViqEn_8812 BIT(2)
|
||||
#define AcmHw_BeqEn_8812 BIT(3)
|
||||
#define AcmHw_VoqStatus_8812 BIT(5)
|
||||
#define AcmHw_ViqStatus_8812 BIT(6)
|
||||
#define AcmHw_BeqStatus_8812 BIT(7)
|
||||
|
||||
#endif /* __RTL8812A_SPEC_H__ */
|
||||
|
||||
#ifdef CONFIG_RTL8821A
|
||||
#include "rtl8821a_spec.h"
|
||||
#endif /* CONFIG_RTL8821A */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2017 Realtek Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef _RTL88812A_SRESET_H_
|
||||
#define _RTL8812A_SRESET_H_
|
||||
|
||||
#include <rtw_sreset.h>
|
||||
|
||||
#ifdef DBG_CONFIG_ERROR_DETECT
|
||||
extern void rtl8812_sreset_xmit_status_check(_adapter *padapter);
|
||||
extern void rtl8812_sreset_linked_status_check(_adapter *padapter);
|
||||
#endif
|
||||
#endif
|
||||
Loading…
Reference in New Issue