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ivanovborislav 2021-11-21 14:43:29 +02:00 committed by GitHub
parent 449d3d3398
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237
hal/phydm/ap_makefile.mk Normal file
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_PHYDM_FILES :=\
phydm/phydm.o \
phydm/phydm_dig.o\
phydm/phydm_antdiv.o\
phydm/phydm_soml.o\
phydm/phydm_smt_ant.o\
phydm/phydm_pathdiv.o\
phydm/phydm_rainfo.o\
phydm/phydm_dynamictxpower.o\
phydm/phydm_adaptivity.o\
phydm/phydm_debug.o\
phydm/phydm_interface.o\
phydm/phydm_phystatus.o\
phydm/phydm_hwconfig.o\
phydm/phydm_dfs.o\
phydm/phydm_cfotracking.o\
phydm/phydm_adc_sampling.o\
phydm/phydm_ccx.o\
phydm/phydm_primary_cca.o\
phydm/phydm_cck_pd.o\
phydm/phydm_rssi_monitor.o\
phydm/phydm_auto_dbg.o\
phydm/phydm_math_lib.o\
phydm/phydm_noisemonitor.o\
phydm/phydm_api.o\
phydm/phydm_pow_train.o\
phydm/phydm_lna_sat.o\
phydm/phydm_pmac_tx_setting.o\
phydm/phydm_mp.o\
phydm/phydm_cck_rx_pathdiv.o\
phydm/phydm_direct_bf.o\
phydm/txbf/phydm_hal_txbf_api.o\
EdcaTurboCheck.o\
phydm/halrf/halrf.o\
phydm/halrf/halrf_debug.o\
phydm/halrf/halphyrf_ap.o\
phydm/halrf/halrf_powertracking_ap.o\
phydm/halrf/halrf_powertracking.o\
phydm/halrf/halrf_kfree.o\
phydm/halrf/halrf_psd.o
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8188e/halhwimg8188e_bb.o\
phydm/rtl8188e/halhwimg8188e_mac.o\
phydm/rtl8188e/halhwimg8188e_rf.o\
phydm/rtl8188e/phydm_regconfig8188e.o\
phydm/rtl8188e/hal8188erateadaptive.o\
phydm/rtl8188e/phydm_rtl8188e.o\
phydm/halrf/rtl8188e/halrf_8188e_ap.o
endif
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += ./phydm/halrf/rtl8812a/halrf_8812a_ap.o
endif
_PHYDM_FILES += phydm/rtl8812a/phydm_rtl8812a.o
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
_PHYDM_FILES += phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
_PHYDM_FILES += \
phydm/halrf/rtl8192e/halrf_8192e_ap.o\
phydm/rtl8192e/phydm_rtl8192e.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_8814a_ap.o
rtl8192cd-objs += phydm/halrf/rtl8814a/halrf_iqk_8814a.o
rtl8192cd-objs += phydm/halrf/rtl8814a/halhwimg8814a_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
phydm/rtl8814a/halhwimg8814a_bb.o\
phydm/rtl8814a/halhwimg8814a_mac.o\
phydm/rtl8814a/phydm_regconfig8814a.o\
phydm/rtl8814a/phydm_rtl8814a.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8822BE),y)
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_8822b.o
_PHYDM_FILES += phydm/halrf/rtl8822b/halrf_iqk_8822b.o
_PHYDM_FILES += phydm/halrf/rtl8822b/halhwimg8822b_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822b/halhwimg8822b_bb.o\
phydm/rtl8822b/halhwimg8822b_mac.o\
phydm/rtl8822b/phydm_regconfig8822b.o\
phydm/rtl8822b/phydm_hal_api8822b.o\
phydm/rtl8822b/phydm_rtl8822b.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8822CE),y)
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_iqk_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_dpk_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halrf_rfk_init_8822c.o
_PHYDM_FILES += phydm/halrf/rtl8822c/halhwimg8822c_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8822c/halhwimg8822c_bb.o\
phydm/rtl8822c/phydm_regconfig8822c.o\
phydm/rtl8822c/phydm_hal_api8822c.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8812FE),y)
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_iqk_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_dpk_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_tssi_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halrf_rfk_init_8812f.o
_PHYDM_FILES += phydm/halrf/rtl8812f/halhwimg8812f_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8812f/halhwimg8812f_bb.o\
phydm/rtl8812f/phydm_regconfig8812f.o\
phydm/rtl8812f/phydm_hal_api8812f.o\
phydm/rtl8812f/phydm_rtl8812f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8821CE),y)
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_8821c.o
_PHYDM_FILES += phydm/halrf/rtl8821c/halrf_iqk_8821c.o
_PHYDM_FILES += phydm/halrf/rtl8821c/halhwimg8821c_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8821c/halhwimg8821c_bb.o\
phydm/rtl8821c/halhwimg8821c_mac.o\
phydm/rtl8821c/phydm_regconfig8821c.o\
phydm/rtl8821c/phydm_hal_api8821c.o\
phydm/rtl8821c/phydm_rtl8821c.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8197F),y)
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_iqk_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halrf_dpk_8197f.o
_PHYDM_FILES += phydm/halrf/rtl8197f/halhwimg8197f_rf.o
_PHYDM_FILES += efuse_97f/efuse.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8197f/halhwimg8197f_bb.o\
phydm/rtl8197f/halhwimg8197f_mac.o\
phydm/rtl8197f/phydm_hal_api8197f.o\
phydm/rtl8197f/phydm_regconfig8197f.o\
phydm/rtl8197f/phydm_rtl8197f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8192FE),y)
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_8192f.o
_PHYDM_FILES += phydm/halrf/rtl8192f/halrf_dpk_8192f.o
_PHYDM_FILES += phydm/halrf/rtl8192f/halhwimg8192f_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8192f/halhwimg8192f_bb.o\
phydm/rtl8192f/halhwimg8192f_mac.o\
phydm/rtl8192f/phydm_hal_api8192f.o\
phydm/rtl8192f/phydm_regconfig8192f.o\
phydm/rtl8192f/phydm_rtl8192f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8198F),y)
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_iqk_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_dpk_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halrf_rfk_init_8198f.o
_PHYDM_FILES += phydm/halrf/rtl8198f/halhwimg8198f_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8198f/phydm_hal_api8198f.o\
phydm/rtl8198f/halhwimg8198f_bb.o\
phydm/rtl8198f/halhwimg8198f_mac.o\
phydm/rtl8198f/phydm_regconfig8198f.o \
phydm/halrf/rtl8198f/halrf_8198f.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8814BE),y)
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_iqk_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_dpk_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_txgapk_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halrf_rfk_init_8814b.o
_PHYDM_FILES += phydm/halrf/rtl8814b/halhwimg8814b_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8814b/phydm_hal_api8814b.o\
phydm/rtl8814b/halhwimg8814b_bb.o\
phydm/rtl8814b/phydm_regconfig8814b.o \
phydm/rtl8814b/phydm_extraagc8814b.o \
phydm/halrf/rtl8814b/halrf_8814b.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8197G),y)
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_iqk_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_dpk_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_tssi_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halrf_rfk_init_8197g.o
_PHYDM_FILES += phydm/halrf/rtl8197g/halhwimg8197g_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8197g/phydm_hal_api8197g.o\
phydm/rtl8197g/halhwimg8197g_bb.o\
phydm/rtl8197g/halhwimg8197g_mac.o\
phydm/rtl8197g/phydm_regconfig8197g.o \
phydm/rtl8197g/phydm_rtl8197g.o \
phydm/halrf/rtl8197g/halrf_8197g.o
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8723FE),y)
_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_8723f.o
_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_iqk_8723f.o
_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_dpk_8723f.o
_PHYDM_FILES += phydm/halrf/rtl8723f/halrf_rfk_init_8723f.o
_PHYDM_FILES += phydm/halrf/rtl8723f/halhwimg8723f_rf.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
_PHYDM_FILES += \
phydm/rtl8723f/halhwimg8723f_bb.o\
phydm/rtl8723f/phydm_regconfig8723f.o\
phydm/rtl8723f/phydm_hal_api8723f.o
endif
endif

137
hal/phydm/halhwimg.h Normal file
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/******************************************************************************
*
* Copyright(c) 2016 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#pragma once
#ifndef __INC_HW_IMG_H
#define __INC_HW_IMG_H
/*@
* 2011/03/15 MH Add for different IC HW image file selection. code size consideration.
* */
#if RT_PLATFORM == PLATFORM_LINUX
#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 0
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 1
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 0
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 1
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 0
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#elif (DEV_BUS_TYPE == RT_USB_INTERFACE)
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 0
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 0
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 1
#define RTL8723S_HWIMG_SUPPORT 0
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE)
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 0
#define RTL8192CE_TEST_HWIMG_SUPPORT 0
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 0
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 0
#define RTL8192DE_TEST_HWIMG_SUPPORT 0
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 0
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 1
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#endif
#else /* PLATFORM_WINDOWS & MacOSX */
/* @For 92C */
#define RTL8192CE_HWIMG_SUPPORT 1
#define RTL8192CE_TEST_HWIMG_SUPPORT 1
#define RTL8192CU_HWIMG_SUPPORT 1
#define RTL8192CU_TEST_HWIMG_SUPPORT 1
/* @For 92D */
#define RTL8192DE_HWIMG_SUPPORT 1
#define RTL8192DE_TEST_HWIMG_SUPPORT 1
#define RTL8192DU_HWIMG_SUPPORT 1
#define RTL8192DU_TEST_HWIMG_SUPPORT 1
#if defined(UNDER_CE)
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 0
#define RTL8723U_HWIMG_SUPPORT 0
#define RTL8723S_HWIMG_SUPPORT 1
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 0
#define RTL8188EU_HWIMG_SUPPORT 0
#define RTL8188ES_HWIMG_SUPPORT 0
#else
/* @For 8723 */
#define RTL8723E_HWIMG_SUPPORT 1
/* @#define RTL_8723E_TEST_HWIMG_SUPPORT 1 */
#define RTL8723U_HWIMG_SUPPORT 1
/* @#define RTL_8723U_TEST_HWIMG_SUPPORT 1 */
#define RTL8723S_HWIMG_SUPPORT 1
/* @#define RTL_8723S_TEST_HWIMG_SUPPORT 1 */
/* @For 88E */
#define RTL8188EE_HWIMG_SUPPORT 1
#define RTL8188EU_HWIMG_SUPPORT 1
#define RTL8188ES_HWIMG_SUPPORT 1
#endif
#endif
#endif /* @__INC_HW_IMG_H */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/

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hal/phydm/phydm.c Normal file
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hal/phydm/phydm.h Normal file
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hal/phydm/phydm.mk Normal file
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EXTRA_CFLAGS += -I$(src)/hal/phydm
_PHYDM_FILES := hal/phydm/phydm_debug.o \
hal/phydm/phydm_antdiv.o\
hal/phydm/phydm_soml.o\
hal/phydm/phydm_smt_ant.o\
hal/phydm/phydm_antdect.o\
hal/phydm/phydm_interface.o\
hal/phydm/phydm_phystatus.o\
hal/phydm/phydm_hwconfig.o\
hal/phydm/phydm.o\
hal/phydm/phydm_dig.o\
hal/phydm/phydm_pathdiv.o\
hal/phydm/phydm_rainfo.o\
hal/phydm/phydm_dynamictxpower.o\
hal/phydm/phydm_adaptivity.o\
hal/phydm/phydm_cfotracking.o\
hal/phydm/phydm_noisemonitor.o\
hal/phydm/phydm_beamforming.o\
hal/phydm/phydm_direct_bf.o\
hal/phydm/phydm_dfs.o\
hal/phydm/txbf/halcomtxbf.o\
hal/phydm/txbf/haltxbfinterface.o\
hal/phydm/txbf/phydm_hal_txbf_api.o\
hal/phydm/phydm_adc_sampling.o\
hal/phydm/phydm_ccx.o\
hal/phydm/phydm_psd.o\
hal/phydm/phydm_primary_cca.o\
hal/phydm/phydm_cck_pd.o\
hal/phydm/phydm_rssi_monitor.o\
hal/phydm/phydm_auto_dbg.o\
hal/phydm/phydm_math_lib.o\
hal/phydm/phydm_api.o\
hal/phydm/phydm_pow_train.o\
hal/phydm/phydm_lna_sat.o\
hal/phydm/phydm_pmac_tx_setting.o\
hal/phydm/phydm_mp.o\
hal/phydm/phydm_cck_rx_pathdiv.o\
hal/phydm/halrf/halrf.o\
hal/phydm/halrf/halrf_debug.o\
hal/phydm/halrf/halphyrf_ce.o\
hal/phydm/halrf/halrf_powertracking_ce.o\
hal/phydm/halrf/halrf_powertracking.o\
hal/phydm/halrf/halrf_kfree.o\
hal/phydm/halrf/halrf_psd.o
ifeq ($(CONFIG_RTL8188E), y)
RTL871X = rtl8188e
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
hal/phydm/$(RTL871X)/phydm_rtl8188e.o
endif
ifeq ($(CONFIG_RTL8192E), y)
RTL871X = rtl8192e
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
hal/phydm/$(RTL871X)/phydm_rtl8192e.o
endif
ifeq ($(CONFIG_RTL8812A), y)
RTL871X = rtl8812a
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
hal/phydm/txbf/haltxbfjaguar.o
endif
ifeq ($(CONFIG_RTL8821A), y)
RTL871X = rtl8821a
_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
hal/phydm/rtl8821a/halhwimg8821a_bb.o\
hal/phydm/rtl8821a/halhwimg8821a_rf.o\
hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
hal/phydm/rtl8821a/phydm_regconfig8821a.o\
hal/phydm/rtl8821a/phydm_rtl8821a.o\
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
hal/phydm/txbf/haltxbfjaguar.o
endif
ifeq ($(CONFIG_RTL8723B), y)
RTL871X = rtl8723b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
hal/phydm/$(RTL871X)/phydm_rtl8723b.o
endif
ifeq ($(CONFIG_RTL8814A), y)
RTL871X = rtl8814a
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8814a_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
hal/phydm/txbf/haltxbf8814a.o
endif
ifeq ($(CONFIG_RTL8723C), y)
RTL871X = rtl8703b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
endif
ifeq ($(CONFIG_RTL8723D), y)
RTL871X = rtl8723d
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
endif
ifeq ($(CONFIG_RTL8710B), y)
RTL871X = rtl8710b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8710b_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
endif
ifeq ($(CONFIG_RTL8188F), y)
RTL871X = rtl8188f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
hal/phydm/$(RTL871X)/phydm_rtl8188f.o
endif
ifeq ($(CONFIG_RTL8822B), y)
RTL871X = rtl8822b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
hal/phydm/halrf/$(RTL871X)/halhwimg8822b_rf.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
hal/phydm/$(RTL871X)/phydm_rtl8822b.o
_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o
endif
ifeq ($(CONFIG_RTL8821C), y)
RTL871X = rtl8821c
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
hal/phydm/$(RTL871X)/phydm_rtl8821c.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8821c_rf.o \
hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
endif
ifeq ($(CONFIG_RTL8192F), y)
RTL871X = rtl8192f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8192f_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
endif
ifeq ($(CONFIG_RTL8198F), y)
RTL871X = rtl8198f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8198f.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8198f_rf.o
endif
ifeq ($(CONFIG_RTL8822C), y)
RTL871X = rtl8822c
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822c_bb.o\
hal/phydm/$(RTL871X)/phydm_hal_api8822c.o\
hal/phydm/$(RTL871X)/phydm_regconfig8822c.o\
hal/phydm/$(RTL871X)/phydm_rtl8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_tssi_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_dpk_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8822c.o\
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822c.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8822c_rf.o
endif
ifeq ($(CONFIG_RTL8814B), y)
RTL871X = rtl8814b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814b_bb.o\
hal/phydm/$(RTL871X)/phydm_hal_api8814b.o\
hal/phydm/$(RTL871X)/phydm_regconfig8814b.o\
hal/phydm/$(RTL871X)/phydm_extraagc8814b.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8814b_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8814b.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814b.o \
hal/phydm/halrf/$(RTL871X)/halrf_dpk_8814b.o\
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8814b.o\
hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8814b.o
endif
ifeq ($(CONFIG_RTL8723F), y)
RTL871X = rtl8723f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723f_bb.o\
hal/phydm/$(RTL871X)/phydm_hal_api8723f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8723f.o\
hal/phydm/$(RTL871X)/phydm_rtl8723f.o\
hal/phydm/halrf/$(RTL871X)/halrf_8723f.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8723f.o\
hal/phydm/halrf/$(RTL871X)/halrf_tssi_8723f.o\
hal/phydm/halrf/$(RTL871X)/halrf_dpk_8723f.o\
hal/phydm/halrf/$(RTL871X)/halrf_txgapk_8723f.o\
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8723f.o\
hal/phydm/halrf/$(RTL871X)/halhwimg8723f_rf.o
endif

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@ -0,0 +1,845 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if WPP_SOFTWARE_TRACE
#include "PhyDM_Adaptivity.tmh"
#endif
#endif
#ifdef PHYDM_SUPPORT_ADAPTIVITY
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
boolean
phydm_check_channel_plan(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
if (mgnt_info->RegEnableAdaptivity != 2)
return false;
if (!dm->carrier_sense_enable) { /*@check domain Code for adaptivity or CarrierSense*/
if ((*dm->band_type == ODM_BAND_5G) &&
!(adapt->regulation_5g == REGULATION_ETSI || adapt->regulation_5g == REGULATION_WW)) {
PHYDM_DBG(dm, DBG_ADPTVTY,
"adaptivity skip 5G domain code : %d\n",
adapt->regulation_5g);
return true;
} else if ((*dm->band_type == ODM_BAND_2_4G) &&
!(adapt->regulation_2g == REGULATION_ETSI || adapt->regulation_2g == REGULATION_WW)) {
PHYDM_DBG(dm, DBG_ADPTVTY,
"adaptivity skip 2.4G domain code : %d\n",
adapt->regulation_2g);
return true;
} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
PHYDM_DBG(dm, DBG_ADPTVTY,
"adaptivity neither 2G nor 5G band, return\n");
return true;
}
} else {
if ((*dm->band_type == ODM_BAND_5G) &&
!(adapt->regulation_5g == REGULATION_MKK || adapt->regulation_5g == REGULATION_WW)) {
PHYDM_DBG(dm, DBG_ADPTVTY,
"CarrierSense skip 5G domain code : %d\n",
adapt->regulation_5g);
return true;
} else if ((*dm->band_type == ODM_BAND_2_4G) &&
!(adapt->regulation_2g == REGULATION_MKK || adapt->regulation_2g == REGULATION_WW)) {
PHYDM_DBG(dm, DBG_ADPTVTY,
"CarrierSense skip 2.4G domain code : %d\n",
adapt->regulation_2g);
return true;
} else if ((*dm->band_type != ODM_BAND_2_4G) && (*dm->band_type != ODM_BAND_5G)) {
PHYDM_DBG(dm, DBG_ADPTVTY,
"CarrierSense neither 2G nor 5G band, return\n");
return true;
}
}
return false;
}
boolean
phydm_soft_ap_special_set(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
boolean disable_ap_adapt_setting = false;
if (dm->soft_ap_mode != NULL) {
if (*dm->soft_ap_mode != 0 &&
(dm->soft_ap_special_setting & BIT(0)))
disable_ap_adapt_setting = true;
else
disable_ap_adapt_setting = false;
PHYDM_DBG(dm, DBG_ADPTVTY,
"soft_ap_setting = %x, soft_ap = %d, dis_ap_adapt = %d\n",
dm->soft_ap_special_setting, *dm->soft_ap_mode,
disable_ap_adapt_setting);
}
return disable_ap_adapt_setting;
}
boolean
phydm_ap_num_check(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
boolean dis_adapt = false;
if (dm->ap_total_num > adapt->ap_num_th)
dis_adapt = true;
else
dis_adapt = false;
PHYDM_DBG(dm, DBG_ADPTVTY, "AP total num = %d, AP num threshold = %d\n",
dm->ap_total_num, adapt->ap_num_th);
return dis_adapt;
}
void phydm_check_adaptivity(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
boolean disable_adapt = false;
if (!adapt->mode_cvrt_en)
return;
if (phydm_check_channel_plan(dm) || phydm_ap_num_check(dm) ||
phydm_soft_ap_special_set(dm))
disable_adapt = true;
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE && disable_adapt)
*dm->edcca_mode = PHYDM_EDCCA_NORMAL_MODE;
else if (*dm->edcca_mode == PHYDM_EDCCA_NORMAL_MODE && !disable_adapt)
*dm->edcca_mode = PHYDM_EDCCA_ADAPT_MODE;
}
void phydm_set_l2h_th_ini_win(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
dm->th_l2h_ini = 45;
else if (dm->support_ic_type & ODM_RTL8814B)
dm->th_l2h_ini = 49;
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812)) {
dm->th_l2h_ini = -17;
} else {
if (*dm->band_type == ODM_BAND_5G)
dm->th_l2h_ini = -14;
else if (*dm->band_type == ODM_BAND_2_4G)
dm->th_l2h_ini = -9;
}
} else { /*ODM_IC_11N_SERIES*/
dm->th_l2h_ini = -9;
}
}
#endif
void phydm_dig_up_bound_lmt_en(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE ||
!dm->is_linked) {
adapt->igi_up_bound_lmt_cnt = 0;
adapt->igi_lmt_en = false;
return;
}
if (dm->total_tp > 1) {
adapt->igi_lmt_en = true;
adapt->igi_up_bound_lmt_cnt = adapt->igi_up_bound_lmt_val;
PHYDM_DBG(dm, DBG_ADPTVTY,
"TP >1, Start limit IGI upper bound\n");
} else {
if (adapt->igi_up_bound_lmt_cnt == 0)
adapt->igi_lmt_en = false;
else
adapt->igi_up_bound_lmt_cnt--;
}
PHYDM_DBG(dm, DBG_ADPTVTY, "IGI_lmt_cnt = %d\n",
adapt->igi_up_bound_lmt_cnt);
}
void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
odm_set_bb_reg(dm, R_0x84c, MASKBYTE2, (u8)L2H + 0x80);
odm_set_bb_reg(dm, R_0x84c, MASKBYTE3, (u8)H2L + 0x80);
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, R_0xc4c, MASKBYTE0, (u8)L2H);
odm_set_bb_reg(dm, R_0xc4c, MASKBYTE2, (u8)H2L);
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, R_0x8a4, MASKBYTE0, (u8)L2H);
odm_set_bb_reg(dm, R_0x8a4, MASKBYTE1, (u8)H2L);
}
}
void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (state == PHYDM_IGNORE_EDCCA) {
/*@ignore EDCCA*/
odm_set_mac_reg(dm, R_0x520, BIT(15), 1);
/*@enable EDCCA count down*/
odm_set_mac_reg(dm, R_0x524, BIT(11), 0);
} else { /*@don't set MAC ignore EDCCA signal*/
/*@don't ignore EDCCA*/
odm_set_mac_reg(dm, R_0x520, BIT(15), 0);
/*@disable EDCCA count down*/
odm_set_mac_reg(dm, R_0x524, BIT(11), 1);
}
PHYDM_DBG(dm, DBG_ADPTVTY, "EDCCA enable state = %d\n", state);
}
void phydm_search_pwdb_lower_bound(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
u32 value32 = 0, reg_value32 = 0;
u8 cnt = 0, try_count = 0;
u8 tx_edcca1 = 0;
boolean is_adjust = true;
s8 th_l2h, th_h2l, igi_target_dc = 0x32;
s8 diff = 0;
s8 IGI = adapt->igi_base + 30 + dm->th_l2h_ini - dm->th_edcca_hl_diff;
halrf_rf_lna_setting(dm, HALRF_LNA_DISABLE);
diff = igi_target_dc - IGI;
th_l2h = dm->th_l2h_ini + diff;
if (th_l2h > 10)
th_l2h = 10;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
ODM_delay_ms(30);
while (is_adjust) {
/*@check CCA status*/
/*set debug port to 0x0*/
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
reg_value32 = phydm_get_bb_dbg_port_val(dm);
while (reg_value32 & BIT(3) && try_count < 3) {
ODM_delay_ms(3);
try_count = try_count + 1;
reg_value32 = phydm_get_bb_dbg_port_val(dm);
}
phydm_release_bb_dbg_port(dm);
try_count = 0;
}
/*@count EDCCA signal = 1 times*/
for (cnt = 0; cnt < 20; cnt++) {
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1,
adapt->adaptivity_dbg_port)) {
value32 = phydm_get_bb_dbg_port_val(dm);
phydm_release_bb_dbg_port(dm);
}
if (value32 & BIT(30) && dm->support_ic_type &
(ODM_RTL8723B | ODM_RTL8188E))
tx_edcca1 = tx_edcca1 + 1;
else if (value32 & BIT(29))
tx_edcca1 = tx_edcca1 + 1;
}
if (tx_edcca1 > 1) {
IGI = IGI - 1;
th_l2h = th_l2h + 1;
if (th_l2h > 10)
th_l2h = 10;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
phydm_set_edcca_threshold(dm, th_h2l, th_l2h);
tx_edcca1 = 0;
if (th_l2h == 10)
is_adjust = false;
} else {
is_adjust = false;
}
}
adapt->adapt_igi_up = IGI - ADAPT_DC_BACKOFF;
adapt->h2l_lb = th_h2l + ADAPT_DC_BACKOFF;
adapt->l2h_lb = th_l2h + ADAPT_DC_BACKOFF;
halrf_rf_lna_setting(dm, HALRF_LNA_ENABLE);
phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
}
boolean phydm_re_search_condition(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
u8 adaptivity_igi_upper = adaptivity->adapt_igi_up + ADAPT_DC_BACKOFF;
if (adaptivity_igi_upper <= 0x26)
return true;
else
return false;
}
void phydm_set_l2h_th_ini(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/*@ [New Format: JGR3]IGI-idx:45 = RSSI:35 = -65dBm*/
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8723F))
dm->th_l2h_ini = 45;
else if (dm->support_ic_type & ODM_RTL8814B)
dm->th_l2h_ini = 49;
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*@ [Old Format] -11+base(50) = IGI_idx:39 = RSSI:29 = -71dBm*/
if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8812))
dm->th_l2h_ini = -17;
else
dm->th_l2h_ini = -14;
} else { /*ODM_IC_11N_SERIES*/
if (dm->support_ic_type & ODM_RTL8721D)
dm->th_l2h_ini = -14;
else
dm->th_l2h_ini = -11;
}
}
void phydm_set_l2h_th_ini_carrier_sense(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
dm->th_l2h_ini = 60; /*@ -50dBm*/
else
dm->th_l2h_ini = 10; /*@ -50dBm*/
}
void phydm_set_forgetting_factor(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
return;
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A |
ODM_RTL8195B))
odm_set_bb_reg(dm, R_0x8a0, BIT(1) | BIT(0), 0);
}
void phydm_edcca_decision_opt(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
return;
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, R_0x8dc, BIT(5), 0x1);
else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
odm_set_bb_reg(dm, R_0xce8, BIT(13), 0x1);
else if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
odm_set_bb_reg(dm, R_0x844, BIT(30) | BIT(29), 0x0);
}
void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
u32 used = *_used;
u32 out_len = *_out_len;
char help[] = "-h";
u32 dm_value[10] = {0};
u8 i = 0, input_idx = 0;
u32 reg_value32 = 0;
s8 h2l_diff = 0;
for (i = 0; i < 5; i++) {
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
input_idx++;
}
if (strcmp(input[1], help) == 0) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"Show adaptivity message: {0}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Enter debug mode: {1} {th_l2h_ini} {th_edcca_hl_diff}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Leave debug mode: {2}\n");
goto out;
}
if (input_idx == 0)
return;
if (dm_value[0] == PHYDM_ADAPT_DEBUG) {
adaptivity->debug_mode = true;
if (dm_value[1] != 0)
dm->th_l2h_ini = (s8)dm_value[1];
if (dm_value[2] != 0)
dm->th_edcca_hl_diff = (s8)dm_value[2];
PDM_SNPF(out_len, used, output + used, out_len - used,
"th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
dm->th_l2h_ini, dm->th_edcca_hl_diff);
} else if (dm_value[0] == PHYDM_ADAPT_RESUME) {
adaptivity->debug_mode = false;
dm->th_l2h_ini = adaptivity->th_l2h_ini_backup;
dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
} else if (dm_value[0] == PHYDM_ADAPT_MSG) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"debug_mode = %s, th_l2h_ini = %d\n",
(adaptivity->debug_mode ? "TRUE" : "FALSE"),
dm->th_l2h_ini);
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
reg_value32 = odm_get_bb_reg(dm, R_0x84c, MASKDWORD);
h2l_diff = (s8)((0x00ff0000 & reg_value32) >> 16) -
(s8)((0xff000000 & reg_value32) >> 24);
} else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
reg_value32 = odm_get_bb_reg(dm, R_0xc4c, MASKDWORD);
h2l_diff = (s8)(0x000000ff & reg_value32) -
(s8)((0x00ff0000 & reg_value32) >> 16);
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
reg_value32 = odm_get_bb_reg(dm, R_0x8a4, MASKDWORD);
h2l_diff = (s8)(0x000000ff & reg_value32) -
(s8)((0x0000ff00 & reg_value32) >> 8);
}
if (h2l_diff == 7)
PDM_SNPF(out_len, used, output + used, out_len - used,
"adaptivity enable\n");
else
PDM_SNPF(out_len, used, output + used, out_len - used,
"adaptivity disable\n");
}
out:
*_used = used;
*_out_len = out_len;
}
void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (val_len != 2) {
PHYDM_DBG(dm, ODM_COMP_API,
"[Error][adaptivity]Need val_len = 2\n");
return;
}
phydm_set_edcca_threshold(dm, (s8)val_buf[1], (s8)val_buf[0]);
}
boolean phydm_edcca_abort(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
u32 is_fw_in_psmode = false;
#endif
if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
PHYDM_DBG(dm, DBG_ADPTVTY, "adaptivity disable\n");
return true;
}
if (dm->pause_ability & ODM_BB_ADAPTIVITY) {
PHYDM_DBG(dm, DBG_ADPTVTY, "Return: Pause ADPTVTY in LV=%d\n",
dm->pause_lv_table.lv_adapt);
return true;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
((PADAPTER)adapter)->HalFunc.GetHwRegHandler(adapter,
HW_VAR_FW_PSMODE_STATUS,
(u8 *)(&is_fw_in_psmode));
/*@Disable EDCCA while under LPS mode, added by Roger, 2012.09.14.*/
if (is_fw_in_psmode)
return true;
#endif
return false;
}
void phydm_edcca_thre_calc_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
u8 igi = dig_t->cur_ig_value;
s8 th_l2h = 0, th_h2l = 0;
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
/*prevent pwdB clipping and result in Miss Detection*/
adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini - ADC_BACKOFF);
if (igi < adapt->l2h_dyn_min)
th_l2h = igi + ADC_BACKOFF;
else
th_l2h = dm->th_l2h_ini;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
} else {
th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
}
adapt->th_l2h = th_l2h;
adapt->th_h2l = th_h2l;
phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
}
void phydm_edcca_thre_calc(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
u8 igi = dig_t->cur_ig_value;
s8 th_l2h = 0, th_h2l = 0;
s8 diff = 0, igi_target = adapt->igi_base;
if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
/*@fix EDCCA hang issue*/
if (dm->support_ic_type & ODM_RTL8812) {
/*@ADC_mask disable*/
odm_set_bb_reg(dm, R_0x800, BIT(10), 1);
/*@ADC_mask enable*/
odm_set_bb_reg(dm, R_0x800, BIT(10), 0);
}
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
/*@Limit IGI upper bound for adaptivity*/
phydm_dig_up_bound_lmt_en(dm);
diff = igi_target - (s8)igi;
th_l2h = dm->th_l2h_ini + diff;
if (th_l2h > 10)
th_l2h = 10;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
} else {
th_l2h = 70 - igi;
th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
}
/*replace lower bound to prevent EDCCA always equal 1*/
if (th_h2l < adapt->h2l_lb)
th_h2l = adapt->h2l_lb;
if (th_l2h < adapt->l2h_lb)
th_l2h = adapt->l2h_lb;
PHYDM_DBG(dm, DBG_ADPTVTY,
"adapt_igi_up=0x%x, l2h_lb = %d dBm, h2l_lb = %d dBm\n",
adapt->adapt_igi_up,
IGI_2_DBM(adapt->l2h_lb + adapt->adapt_igi_up),
IGI_2_DBM(adapt->h2l_lb + adapt->adapt_igi_up));
} else { /* < JGR2 & N*/
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE) {
/*need to consider PwdB upper bound for 8814 later IC*/
adapt->l2h_dyn_min = (u8)(dm->th_l2h_ini + igi_target);
if (igi < adapt->l2h_dyn_min)
th_l2h = igi;
else
th_l2h = adapt->l2h_dyn_min;
th_h2l = th_l2h - dm->th_edcca_hl_diff;
} else {
th_l2h = MAX_2(igi + TH_L2H_DIFF_IGI, EDCCA_TH_L2H_LB);
th_h2l = th_l2h - EDCCA_HL_DIFF_NORMAL;
}
}
adapt->th_l2h = th_l2h;
adapt->th_h2l = th_h2l;
phydm_set_edcca_threshold(dm, adapt->th_h2l, adapt->th_l2h);
}
#endif
void phydm_set_edcca_threshold_api(void *dm_void)
{
#ifdef PHYDM_SUPPORT_ADAPTIVITY
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
if (*dm->edcca_mode != PHYDM_EDCCA_ADAPT_MODE)
return;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_edcca_thre_calc_jgr3(dm);
else
phydm_edcca_thre_calc(dm);
PHYDM_DBG(dm, DBG_ADPTVTY,
"API :IGI = 0x%x, th_l2h = %d, th_h2l = %d\n",
dm->dm_dig_table.cur_ig_value, adapt->th_l2h, adapt->th_h2l);
#endif
}
void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
switch (cmn_info) {
case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
dm->carrier_sense_enable = (boolean)value;
break;
case PHYDM_ADAPINFO_TH_L2H_INI:
dm->th_l2h_ini = (s8)value;
break;
case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
dm->th_edcca_hl_diff = (s8)value;
break;
case PHYDM_ADAPINFO_AP_NUM_TH:
adaptivity->ap_num_th = (u8)value;
break;
case PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND:
adaptivity->switch_th_l2h_ini_in_band = (u8)value;
break;
default:
break;
}
}
void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
/*This init variable may be changed in run time.*/
switch (cmn_info) {
case PHYDM_ADAPINFO_DOMAIN_CODE_2G:
adapt->regulation_2g = (u8)value;
break;
case PHYDM_ADAPINFO_DOMAIN_CODE_5G:
adapt->regulation_5g = (u8)value;
break;
default:
break;
}
}
void phydm_adaptivity_init(void *dm_void)
{
#ifdef PHYDM_SUPPORT_ADAPTIVITY
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
/* @[Config Adaptivity]*/
if (!dm->edcca_mode) {
pr_debug("[%s] warning!\n", __func__);
dm->edcca_mode = &dm->u8_dummy;
dm->support_ability &= ~ODM_BB_ADAPTIVITY;
return;
}
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
if (!dm->carrier_sense_enable) {
if (dm->th_l2h_ini == 0 &&
!adaptivity->switch_th_l2h_ini_in_band)
phydm_set_l2h_th_ini(dm);
} else {
phydm_set_l2h_th_ini_carrier_sense(dm);
}
if (dm->th_edcca_hl_diff == 0)
dm->th_edcca_hl_diff = 7;
if (dm->wifi_test & RT_WIFI_LOGO)
dm->support_ability &= ~ODM_BB_ADAPTIVITY;
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
adaptivity->mode_cvrt_en = true;
else
adaptivity->mode_cvrt_en = false;
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
if (!dm->carrier_sense_enable) {
if (dm->th_l2h_ini == 0)
phydm_set_l2h_th_ini(dm);
} else {
phydm_set_l2h_th_ini_carrier_sense(dm);
}
if (dm->th_edcca_hl_diff == 0)
dm->th_edcca_hl_diff = 7;
if (dm->wifi_test || *dm->mp_mode)
dm->support_ability &= ~ODM_BB_ADAPTIVITY;
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
if (dm->carrier_sense_enable) {
phydm_set_l2h_th_ini_carrier_sense(dm);
dm->th_edcca_hl_diff = 7;
} else {
dm->th_l2h_ini = dm->TH_L2H_default; /*set by mib*/
dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_default;
}
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
if (!dm->carrier_sense_enable) {
if (dm->th_l2h_ini == 0)
phydm_set_l2h_th_ini(dm);
} else {
phydm_set_l2h_th_ini_carrier_sense(dm);
}
if (dm->th_edcca_hl_diff == 0)
dm->th_edcca_hl_diff = 7;
#endif
adaptivity->debug_mode = false;
adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
adaptivity->igi_base = 0x32;
adaptivity->adapt_igi_up = 0;
adaptivity->h2l_lb = 0;
adaptivity->l2h_lb = 0;
adaptivity->l2h_dyn_min = 0;
adaptivity->th_l2h = 0x7f;
adaptivity->th_h2l = 0x7f;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
adaptivity->adaptivity_dbg_port = 0x208;
else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
adaptivity->adaptivity_dbg_port = 0x209;
if (dm->support_ic_type & ODM_IC_11N_SERIES &&
!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F)) {
/*set to page B1*/
odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x1);
/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
odm_set_bb_reg(dm, R_0xbc0, BIT(27) | BIT(26), 0x1);
odm_set_bb_reg(dm, R_0xe28, BIT(30), 0x0);
} else {
/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
odm_set_bb_reg(dm, R_0xe24, BIT(21) | BIT(20), 0x1);
}
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES &&
!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
/*@0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
odm_set_bb_reg(dm, R_0x944, BIT(29) | BIT(28), 0x1);
}
if (dm->support_ic_type & ODM_IC_PWDB_EDCCA) {
phydm_search_pwdb_lower_bound(dm);
if (phydm_re_search_condition(dm))
phydm_search_pwdb_lower_bound(dm);
} else {
/*resume to no link state*/
phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
}
/*@whether to ignore EDCCA*/
phydm_mac_edcca_state(dm, PHYDM_DONT_IGNORE_EDCCA);
/*@forgetting factor setting*/
phydm_set_forgetting_factor(dm);
/*@EDCCA behavior based on maximum or mean power*/
phydm_edcca_decision_opt(dm);
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
adaptivity->igi_up_bound_lmt_val = 180;
#else
adaptivity->igi_up_bound_lmt_val = 90;
#endif
adaptivity->igi_up_bound_lmt_cnt = 0;
adaptivity->igi_lmt_en = false;
#endif
}
void phydm_adaptivity(void *dm_void)
{
#ifdef PHYDM_SUPPORT_ADAPTIVITY
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_adaptivity_struct *adapt = &dm->adaptivity;
struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
if (phydm_edcca_abort(dm))
return;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
phydm_check_adaptivity(dm); /*@Check adaptivity enable*/
if (!dm->carrier_sense_enable &&
!adapt->debug_mode &&
adapt->switch_th_l2h_ini_in_band)
phydm_set_l2h_th_ini_win(dm);
#endif
PHYDM_DBG(dm, DBG_ADPTVTY, "%s ====>\n", __func__);
PHYDM_DBG(dm, DBG_ADPTVTY, "mode = %s, debug_mode = %d\n",
(*dm->edcca_mode ?
(dm->carrier_sense_enable ?
"CARRIER SENSE" :
"ADAPTIVITY") :
"NORMAL"),
adapt->debug_mode);
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_edcca_thre_calc_jgr3(dm);
else
phydm_edcca_thre_calc(dm);
if (*dm->edcca_mode == PHYDM_EDCCA_ADAPT_MODE)
PHYDM_DBG(dm, DBG_ADPTVTY,
"th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
dm->th_l2h_ini, dm->th_edcca_hl_diff);
if (dm->support_ic_type & ODM_IC_PWDB_EDCCA)
PHYDM_DBG(dm, DBG_ADPTVTY,
"IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
dig_t->cur_ig_value,
IGI_2_DBM(adapt->th_l2h + dig_t->cur_ig_value),
IGI_2_DBM(adapt->th_h2l + dig_t->cur_ig_value));
else
PHYDM_DBG(dm, DBG_ADPTVTY,
"IGI = 0x%x, th_l2h = %d dBm, th_h2l = %d dBm\n",
dig_t->cur_ig_value,
IGI_2_DBM(adapt->th_l2h),
IGI_2_DBM(adapt->th_h2l));
#endif
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "9.7.07" /*@20190321 changed by Kevin,
*add 8721D threshold l2h init
*/
#define ADC_BACKOFF 12
#define EDCCA_TH_L2H_LB 48
#define TH_L2H_DIFF_IGI 8
#define EDCCA_HL_DIFF_NORMAL 8
#define IGI_2_DBM(igi) (igi - 110)
/*@ [PHYDM-337][Old IC] EDCCA TH = IGI + REG setting*/
#define ODM_IC_PWDB_EDCCA (ODM_RTL8188E | ODM_RTL8723B | ODM_RTL8192E |\
ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8812)
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
#define ADAPT_DC_BACKOFF 2
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#define ADAPT_DC_BACKOFF 4
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
#define ADAPT_DC_BACKOFF 0
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
enum phydm_regulation_type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
};
#endif
enum phydm_edcca_mode {
PHYDM_EDCCA_NORMAL_MODE = 0,
PHYDM_EDCCA_ADAPT_MODE = 1
};
enum phydm_adapinfo {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_TH_L2H_INI,
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
PHYDM_ADAPINFO_AP_NUM_TH,
PHYDM_ADAPINFO_DOMAIN_CODE_2G,
PHYDM_ADAPINFO_DOMAIN_CODE_5G,
PHYDM_ADAPINFO_SWITCH_TH_L2H_INI_IN_BAND
};
enum phydm_mac_edcca_type {
PHYDM_IGNORE_EDCCA = 0,
PHYDM_DONT_IGNORE_EDCCA = 1
};
enum phydm_adaptivity_debug_mode {
PHYDM_ADAPT_MSG = 0,
PHYDM_ADAPT_DEBUG = 1,
PHYDM_ADAPT_RESUME = 2,
};
struct phydm_adaptivity_struct {
boolean mode_cvrt_en;
s8 th_l2h_ini_backup;
s8 th_edcca_hl_diff_backup;
s8 igi_base;
s8 h2l_lb;
s8 l2h_lb;
u8 ap_num_th;
u8 l2h_dyn_min;
u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/
u8 debug_mode;
u16 igi_up_bound_lmt_cnt; /*@When igi_up_bound_lmt_cnt !=0, limit IGI upper bound to "adapt_igi_up"*/
u16 igi_up_bound_lmt_val; /*@max value of igi_up_bound_lmt_cnt*/
boolean igi_lmt_en;
u8 adapt_igi_up;
u32 rvrt_val[2]; /*@all rvrt_val for pause API must set to u32*/
s8 th_l2h;
s8 th_h2l;
u8 regulation_2g;
u8 regulation_5g;
u8 switch_th_l2h_ini_in_band;
};
#ifdef PHYDM_SUPPORT_ADAPTIVITY
void phydm_adaptivity_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_set_edcca_val(void *dm_void, u32 *val_buf, u8 val_len);
#endif
void phydm_set_edcca_threshold_api(void *dm_void);
void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value);
void phydm_adaptivity_info_update(void *dm_void, enum phydm_adapinfo cmn_info,
u32 value);
void phydm_adaptivity_init(void *dm_void);
void phydm_adaptivity(void *dm_void);
#endif

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hal/phydm/phydm_adc_sampling.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_ADCSMP_H
#define __INC_ADCSMP_H
#if (PHYDM_LA_MODE_SUPPORT)
/* 2020.07.03 [8723F] Fix SD4 compile error*/
#define DYNAMIC_LA_MODE "4.2"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#if (RTL8197F_SUPPORT || RTL8198F_SUPPORT || RTL8197G_SUPPORT)
#define PHYDM_COMPILE_LA_STORE_IN_IMEM
#endif
#endif
#define PHYDM_LA_STORE_IN_IMEM_IC (ODM_RTL8197F | ODM_RTL8198F | ODM_RTL8197G)
#define FULL_BUFF_MODE_SUPPORT (ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
ODM_RTL8812F | ODM_RTL8814B)
/* @ ============================================================
* enumrate
* ============================================================
*/
enum la_dump_mode {
LA_BB_ADC_DUMP = 0,
LA_MAC_DBG_DUMP = 1
};
enum rt_adcsmp_trig_sel {
PHYDM_ADC_BB_TRIG = 0,
PHYDM_ADC_MAC_TRIG = 1,
PHYDM_ADC_RF0_TRIG = 2,
PHYDM_ADC_RF1_TRIG = 3,
PHYDM_MAC_TRIG = 4
};
enum rt_adcsmp_trig_sig_sel {
ADCSMP_TRIG_CRCOK = 0,
ADCSMP_TRIG_CRCFAIL = 1,
ADCSMP_TRIG_CCA = 2,
ADCSMP_TRIG_REG = 3
};
enum rt_adcsmp_state {
ADCSMP_STATE_IDLE = 0,
ADCSMP_STATE_SET = 1,
ADCSMP_STATE_QUERY = 2
};
enum la_buff_mode {
ADCSMP_BUFF_HALF = 0,
ADCSMP_BUFF_ALL = 1 /*Only use in MP Driver*/
};
/* @ ============================================================
* structure
* ============================================================
*/
struct rt_adcsmp_string {
u32 *octet;
u32 length;
u32 buffer_size;
u32 start_pos;
u32 end_pos; /*@buf addr*/
};
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct la_adv_trig {
boolean la_adv_bbtrigger_en;
boolean la_ori_bb_dis;
u8 la_and1_sel;
u8 la_and1_val;
boolean la_and1_inv;
u8 la_and2_sel;
u8 la_and2_val;
boolean la_and2_inv;
u8 la_and3_sel;
u8 la_and3_val;
boolean la_and3_inv;
u32 la_and4_mask;
u32 la_and4_bitmap;
boolean la_and4_inv;
};
#endif
struct rt_adcsmp {
struct rt_adcsmp_string adc_smp_buf;
enum rt_adcsmp_state adc_smp_state;
enum la_buff_mode la_buff_mode;
enum la_dump_mode la_dump_mode;
u8 la_trig_mode;
u32 la_trig_sig_sel;
u8 la_dma_type;
u32 la_trigger_time;
/*@1.BB mode: Dbg port header sel, 2.MAC mode: for reference mask*/
u32 la_mac_mask_or_hdr_sel;
u32 la_dbg_port;
u8 la_trigger_edge;
u8 la_smp_rate;
u32 la_count;
u32 smp_number;
u32 smp_number_max;
u32 txff_page;
boolean is_la_print;
boolean en_fake_trig;
#if (RTL8197F_SUPPORT)
u32 backup_dma;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
u8 la_work_item_index;
RT_WORK_ITEM adc_smp_work_item;
RT_WORK_ITEM adc_smp_work_item_1;
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
struct la_adv_trig adv_trig_table;
#endif
};
/* @ ============================================================
* Function Prototype
* ============================================================
*/
void phydm_la_set(void *dm_void);
void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
void phydm_la_stop(void *dm_void);
void phydm_la_init(void *dm_void);
void adc_smp_de_init(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
void adc_smp_work_item_callback(void *context);
#endif
#endif
#endif

888
hal/phydm/phydm_antdect.c Normal file
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@ -0,0 +1,888 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_ANT_DETECTION
/* @IS_ANT_DETECT_SUPPORT_SINGLE_TONE(adapter)
* IS_ANT_DETECT_SUPPORT_RSSI(adapter)
* IS_ANT_DETECT_SUPPORT_PSD(adapter) */
/* @1 [1. Single Tone method] =================================================== */
/*@
* Description:
* Set Single/Dual Antenna default setting for products that do not do detection in advance.
*
* Added by Joseph, 2012.03.22
* */
void odm_sw_ant_div_construct_scan_chnl(
void *adapter,
u8 scan_chnl)
{
}
u8 odm_sw_ant_div_select_scan_chnl(
void *adapter)
{
return 0;
}
void odm_single_dual_antenna_default_setting(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
void *adapter = dm->adapter;
u8 bt_ant_num = BT_GetPgAntNum(adapter);
/* Set default antenna A and B status */
if (bt_ant_num == 2) {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = true;
} else if (bt_ant_num == 1) {
/* Set antenna A as default */
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = false;
} else
RT_ASSERT(false, ("Incorrect antenna number!!\n"));
}
/* @2 8723A ANT DETECT
*
* Description:
* Implement IQK single tone for RF DPK loopback and BB PSD scanning.
* This function is cooperated with BB team Neil.
*
* Added by Roger, 2011.12.15
* */
boolean
odm_single_dual_antenna_detection(
void *dm_void,
u8 mode)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
u32 current_channel, rf_loop_reg;
u8 n;
u32 reg88c, regc08, reg874, regc50, reg948, regb2c, reg92c, reg930, reg064, afe_rrx_wait_cca;
u8 initial_gain = 0x5a;
u32 PSD_report_tmp;
u32 ant_a_report = 0x0, ant_b_report = 0x0, ant_0_report = 0x0;
boolean is_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
if (!(dm->support_ic_type & ODM_RTL8723B))
return is_result;
/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
if (!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(((PADAPTER)adapter)))
return is_result;
/* @1 Backup Current RF/BB Settings */
current_channel = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
rf_loop_reg = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
if (dm->support_ic_type & ODM_RTL8723B) {
reg92c = odm_get_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD);
reg930 = odm_get_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD);
reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
reg064 = odm_get_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29));
odm_set_bb_reg(dm, REG_DPDT_CONTROL, 0x3, 0x1);
odm_set_bb_reg(dm, rfe_ctrl_anta_src, 0xff, 0x77);
odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), 0x1); /* @dbg 7 */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0x3c0, 0x0); /* @dbg 8 */
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x0);
}
ODM_delay_us(10);
/* Store A path Register 88c, c08, 874, c50 */
reg88c = odm_get_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD);
regc08 = odm_get_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD);
reg874 = odm_get_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD);
regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
/* Store AFE Registers */
if (dm->support_ic_type & ODM_RTL8723B)
afe_rrx_wait_cca = odm_get_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD);
/* Set PSD 128 pts */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* @128 pts */
/* To SET CH1 to do */
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK, 0x7401); /* @channel 1 */
/* @AFE all on step */
if (dm->support_ic_type & ODM_RTL8723B)
odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, 0x01c00016);
/* @3 wire Disable */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, 0xCCF000C0);
/* @BB IQK setting */
odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, 0x000800E4);
odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, 0x22208000);
/* @IQK setting tone@ 4.34Mhz */
odm_set_bb_reg(dm, REG_TX_IQK_TONE_A, MASKDWORD, 0x10008C1C);
odm_set_bb_reg(dm, REG_TX_IQK, MASKDWORD, 0x01007c00);
/* Page B init */
odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x00080000);
odm_set_bb_reg(dm, REG_CONFIG_ANT_A, MASKDWORD, 0x0f600000);
odm_set_bb_reg(dm, REG_RX_IQK, MASKDWORD, 0x01004800);
odm_set_bb_reg(dm, REG_RX_IQK_TONE_A, MASKDWORD, 0x10008c1f);
if (dm->support_ic_type & ODM_RTL8723B) {
odm_set_bb_reg(dm, REG_TX_IQK_PI_A, MASKDWORD, 0x82150016);
odm_set_bb_reg(dm, REG_RX_IQK_PI_A, MASKDWORD, 0x28150016);
}
odm_set_bb_reg(dm, REG_IQK_AGC_RSP, MASKDWORD, 0x001028d0);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7f, initial_gain);
/* @IQK Single tone start */
odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x808000);
odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf9000000);
odm_set_bb_reg(dm, REG_IQK_AGC_PTS, MASKDWORD, 0xf8000000);
ODM_delay_us(10000);
/* PSD report of antenna A */
PSD_report_tmp = 0x0;
for (n = 0; n < 2; n++) {
PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
if (PSD_report_tmp > ant_a_report)
ant_a_report = PSD_report_tmp;
}
/* @change to Antenna B */
if (dm->support_ic_type & ODM_RTL8723B) {
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
}
ODM_delay_us(10);
/* PSD report of antenna B */
PSD_report_tmp = 0x0;
for (n = 0; n < 2; n++) {
PSD_report_tmp = phydm_get_psd_data(dm, 14, initial_gain);
if (PSD_report_tmp > ant_b_report)
ant_b_report = PSD_report_tmp;
}
/* @Close IQK Single Tone function */
odm_set_bb_reg(dm, REG_FPGA0_IQK, 0xffffff00, 0x000000);
/* @1 Return to antanna A */
if (dm->support_ic_type & ODM_RTL8723B) {
/* @external DPDT */
odm_set_bb_reg(dm, REG_DPDT_CONTROL, MASKDWORD, reg92c);
/* @internal S0/S1 */
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
odm_set_bb_reg(dm, rfe_ctrl_anta_src, MASKDWORD, reg930);
odm_set_mac_reg(dm, REG_SYM_WLBT_PAPE_SEL, BIT(29), reg064);
}
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, MASKDWORD, reg88c);
odm_set_bb_reg(dm, REG_OFDM_0_TR_MUX_PAR, MASKDWORD, regc08);
odm_set_bb_reg(dm, REG_FPGA0_XCD_RF_INTERFACE_SW, MASKDWORD, reg874);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, 0x7F, 0x40);
odm_set_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD, regc50);
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, current_channel);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_loop_reg);
/* Reload AFE Registers */
if (dm->support_ic_type & ODM_RTL8723B)
odm_set_bb_reg(dm, REG_RX_WAIT_CCA, MASKDWORD, afe_rrx_wait_cca);
if (dm->support_ic_type & ODM_RTL8723B) {
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_A[%d]= %d\n", 2416,
ant_a_report);
PHYDM_DBG(dm, DBG_ANT_DIV, "psd_report_B[%d]= %d\n", 2416,
ant_b_report);
/* @2 Test ant B based on ant A is ON */
if (ant_a_report >= 100 && ant_b_report >= 100 && ant_a_report <= 135 && ant_b_report <= 135) {
u8 TH1 = 2, TH2 = 6;
if ((ant_a_report - ant_b_report < TH1) || (ant_b_report - ant_a_report < TH1)) {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual Antenna\n",
__func__);
} else if (((ant_a_report - ant_b_report >= TH1) && (ant_a_report - ant_b_report <= TH2)) ||
((ant_b_report - ant_a_report >= TH1) && (ant_b_report - ant_a_report <= TH2))) {
dm_swat_table->ANTA_ON = false;
dm_swat_table->ANTB_ON = false;
is_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Need to check again\n",
__func__);
} else {
dm_swat_table->ANTA_ON = true;
dm_swat_table->ANTB_ON = false;
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Single Antenna\n", __func__);
}
dm->ant_detected_info.is_ant_detected = true;
dm->ant_detected_info.db_for_ant_a = ant_a_report;
dm->ant_detected_info.db_for_ant_b = ant_b_report;
dm->ant_detected_info.db_for_ant_o = ant_0_report;
} else {
PHYDM_DBG(dm, DBG_ANT_DIV, "return false!!\n");
is_result = false;
}
}
return is_result;
}
/* @1 [2. Scan AP RSSI method] ================================================== */
boolean
odm_sw_ant_div_check_before_link(
void *dm_void)
{
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
//PMGNT_INFO mgnt_info = &adapter->MgntInfo;
PMGNT_INFO mgnt_info = &(((PADAPTER)(adapter))->MgntInfo);
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
s8 score = 0;
PRT_WLAN_BSS p_tmp_bss_desc, p_test_bss_desc;
u8 power_target_L = 9, power_target_H = 16;
u8 tmp_power_diff = 0, power_diff = 0, avg_power_diff = 0, max_power_diff = 0, min_power_diff = 0xff;
u16 index, counter = 0;
static u8 scan_channel;
u32 tmp_swas_no_link_bk_reg948;
PHYDM_DBG(dm, DBG_ANT_DIV, "ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n",
dm->dm_swat_table.ANTA_ON, dm->dm_swat_table.ANTB_ON);
/* @if(HP id) */
{
if (dm->dm_swat_table.rssi_ant_dect_result == true && dm->support_ic_type == ODM_RTL8723B) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"8723B RSSI-based Antenna Detection is done\n");
return false;
}
if (dm->support_ic_type == ODM_RTL8723B) {
if (dm_swat_table->swas_no_link_bk_reg948 == 0xff)
dm_swat_table->swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
}
}
if (dm->adapter == NULL) { /* @For BSOD when plug/unplug fast. //By YJ,120413 */
/* The ODM structure is not initialized. */
return false;
}
/* Retrieve antenna detection registry info, added by Roger, 2012.11.27. */
if (!IS_ANT_DETECT_SUPPORT_RSSI(((PADAPTER)adapter)))
return false;
else
PHYDM_DBG(dm, DBG_ANT_DIV, "Antenna Detection: RSSI method\n");
/* Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. */
odm_acquire_spin_lock(dm, RT_RF_STATE_SPINLOCK);
if (hal_data->eRFPowerState != eRfOn || mgnt_info->RFChangeInProgress || mgnt_info->bMediaConnect) {
odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: rf_change_in_progress(%x), e_rf_power_state(%x)\n",
__func__, mgnt_info->RFChangeInProgress,
hal_data->eRFPowerState);
dm_swat_table->swas_no_link_state = 0;
return false;
} else
odm_release_spin_lock(dm, RT_RF_STATE_SPINLOCK);
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->swas_no_link_state = %d\n",
dm_swat_table->swas_no_link_state);
/* @1 Run AntDiv mechanism "Before Link" part. */
if (dm_swat_table->swas_no_link_state == 0) {
/* @1 Prepare to do Scan again to check current antenna state. */
/* Set check state to next step. */
dm_swat_table->swas_no_link_state = 1;
/* @Copy Current Scan list. */
mgnt_info->tmpNumBssDesc = mgnt_info->NumBssDesc;
PlatformMoveMemory((void *)mgnt_info->tmpbssDesc, (void *)mgnt_info->bssDesc, sizeof(RT_WLAN_BSS) * MAX_BSS_DESC);
/* @Go back to scan function again. */
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Scan one more time\n",
__func__);
mgnt_info->ScanStep = 0;
mgnt_info->bScanAntDetect = true;
scan_channel = odm_sw_ant_div_select_scan_chnl(adapter);
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
if (fat_tab->rx_idle_ant == MAIN_ANT)
odm_update_rx_idle_ant(dm, AUX_ANT);
else
odm_update_rx_idle_ant(dm, MAIN_ANT);
if (scan_channel == 0) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: No AP List Avaiable, Using ant(%s)\n",
__func__,
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"AUX_ANT" : "MAIN_ANT");
if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_5g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
} else {
dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV, "dm_swat_table->ant_2g=%s\n", (fat_tab->rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
}
return false;
}
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Change to %s for testing.\n", __func__,
((fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT"));
} else if (dm->support_ic_type & (ODM_RTL8723B)) {
/*Switch Antenna to another one.*/
tmp_swas_no_link_bk_reg948 = odm_read_4byte(dm, REG_S0_S1_PATH_SWITCH);
if (dm_swat_table->cur_antenna == MAIN_ANT && tmp_swas_no_link_bk_reg948 == 0x200) {
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, 0x280);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, BIT(31), 0x1);
dm_swat_table->cur_antenna = AUX_ANT;
} else {
PHYDM_DBG(dm, DBG_ANT_DIV,
"Reg[948]= (( %x )) was in wrong state\n",
tmp_swas_no_link_bk_reg948);
return false;
}
ODM_delay_us(10);
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Change to (( %s-ant)) for testing.\n",
__func__,
(dm_swat_table->cur_antenna == MAIN_ANT) ?
"MAIN" : "AUX");
}
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else { /* @dm_swat_table->swas_no_link_state == 1 */
/* @1 ScanComple() is called after antenna swiched. */
/* @1 Check scan result and determine which antenna is going */
/* @1 to be used. */
PHYDM_DBG(dm, DBG_ANT_DIV, " tmp_num_bss_desc= (( %d ))\n",
mgnt_info->tmpNumBssDesc); /* @debug for Dino */
for (index = 0; index < mgnt_info->tmpNumBssDesc; index++) {
p_tmp_bss_desc = &mgnt_info->tmpbssDesc[index]; /* @Antenna 1 */
p_test_bss_desc = &mgnt_info->bssDesc[index]; /* @Antenna 2 */
if (PlatformCompareMemory(p_test_bss_desc->bdBssIdBuf, p_tmp_bss_desc->bdBssIdBuf, 6) != 0) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: ERROR!! This shall not happen.\n",
__func__);
continue;
}
if (dm->support_ic_type != ODM_RTL8723B) {
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) {
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score++\n", __func__);
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
score++;
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
} else if (p_tmp_bss_desc->RecvSignalPower < p_test_bss_desc->RecvSignalPower) {
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Compare scan entry: score--\n", __func__);
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
score--;
} else {
if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp < 5000) {
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", p_tmp_bss_desc->bdSsIdBuf, p_tmp_bss_desc->bdSsIdLen);
PHYDM_DBG(dm, DBG_ANT_DIV, "at ch %d, Original: %d, Test: %d\n", p_tmp_bss_desc->ChannelNumber, p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_DBG(dm, DBG_ANT_DIV, "The 2nd Antenna didn't get this AP\n\n");
}
}
}
} else { /* @8723B */
if (p_tmp_bss_desc->ChannelNumber == scan_channel) {
PHYDM_DBG(dm, DBG_ANT_DIV, "channel_number == scan_channel->(( %d ))\n", p_tmp_bss_desc->ChannelNumber);
if (p_tmp_bss_desc->RecvSignalPower > p_test_bss_desc->RecvSignalPower) { /* Pow(Ant1) > Pow(Ant2) */
counter++;
tmp_power_diff = (u8)(p_tmp_bss_desc->RecvSignalPower - p_test_bss_desc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
#if 0
/* PHYDM_DBG(dm,DBG_ANT_DIV, "tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d))\n", tmp_power_diff,max_power_diff,min_power_diff); */
#endif
if (tmp_power_diff > max_power_diff)
max_power_diff = tmp_power_diff;
if (tmp_power_diff < min_power_diff)
min_power_diff = tmp_power_diff;
#if 0
/* PHYDM_DBG(dm,DBG_ANT_DIV, "max_power_diff: (( %d)),min_power_diff: (( %d))\n",max_power_diff,min_power_diff); */
#endif
PlatformMoveMemory(p_test_bss_desc, p_tmp_bss_desc, sizeof(RT_WLAN_BSS));
} else if (p_test_bss_desc->RecvSignalPower > p_tmp_bss_desc->RecvSignalPower) { /* Pow(Ant1) < Pow(Ant2) */
counter++;
tmp_power_diff = (u8)(p_test_bss_desc->RecvSignalPower - p_tmp_bss_desc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
if (tmp_power_diff > max_power_diff)
max_power_diff = tmp_power_diff;
if (tmp_power_diff < min_power_diff)
min_power_diff = tmp_power_diff;
} else { /* Pow(Ant1) = Pow(Ant2) */
if (p_test_bss_desc->bdTstamp > p_tmp_bss_desc->bdTstamp) { /* Stamp(Ant1) < Stamp(Ant2) */
PHYDM_DBG(dm, DBG_ANT_DIV, "time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
if (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp > 5000) {
counter++;
PHYDM_DBG(dm, DBG_ANT_DIV, "Original: %d, Test: %d\n", p_tmp_bss_desc->RecvSignalPower, p_test_bss_desc->RecvSignalPower);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "SSID:", p_tmp_bss_desc->bdSsIdBuf);
PHYDM_PRINT_ADDR(dm, DBG_ANT_DIV, "BSSID:", p_tmp_bss_desc->bdSsIdBuf);
min_power_diff = 0;
}
} else
PHYDM_DBG(dm, DBG_ANT_DIV, "[Error !!!]: Time_diff: %lld\n", (p_test_bss_desc->bdTstamp - p_tmp_bss_desc->bdTstamp) / 1000);
}
}
}
}
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8821)) {
if (mgnt_info->NumBssDesc != 0 && score < 0) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Using ant(%s)\n", __func__,
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT");
} else {
PHYDM_DBG(dm, DBG_ANT_DIV,
"%s: Remain ant(%s)\n", __func__,
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"AUX_ANT" : "MAIN_ANT");
if (fat_tab->rx_idle_ant == MAIN_ANT)
odm_update_rx_idle_ant(dm, AUX_ANT);
else
odm_update_rx_idle_ant(dm, MAIN_ANT);
}
if (IS_5G_WIRELESS_MODE(mgnt_info->dot11CurrentWirelessMode)) {
dm_swat_table->ant_5g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV,
"dm_swat_table->ant_5g=%s\n",
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT");
} else {
dm_swat_table->ant_2g = fat_tab->rx_idle_ant;
PHYDM_DBG(dm, DBG_ANT_DIV,
"dm_swat_table->ant_2g=%s\n",
(fat_tab->rx_idle_ant == MAIN_ANT) ?
"MAIN_ANT" : "AUX_ANT");
}
} else if (dm->support_ic_type == ODM_RTL8723B) {
if (counter == 0) {
if (dm->dm_swat_table.pre_aux_fail_detec == false) {
dm->dm_swat_table.pre_aux_fail_detec = true;
dm->dm_swat_table.rssi_ant_dect_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again\n");
/* @3 [ Scan again ] */
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else { /* pre_aux_fail_detec == true */
/* @2 [ Single Antenna ] */
dm->dm_swat_table.pre_aux_fail_detec = false;
dm->dm_swat_table.rssi_ant_dect_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "counter=(( 0 )) , [[ Still cannot find any AP ]]\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
}
dm->dm_swat_table.aux_fail_detec_counter++;
} else {
dm->dm_swat_table.pre_aux_fail_detec = false;
if (counter == 3) {
avg_power_diff = ((power_diff - max_power_diff - min_power_diff) >> 1) + ((max_power_diff + min_power_diff) >> 2);
PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
} else if (counter >= 4) {
avg_power_diff = (power_diff - max_power_diff - min_power_diff) / (counter - 2);
PHYDM_DBG(dm, DBG_ANT_DIV, "counter: (( %d )) , power_diff: (( %d ))\n", counter, power_diff);
PHYDM_DBG(dm, DBG_ANT_DIV, "[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d ))\n", avg_power_diff, max_power_diff, min_power_diff);
} else { /* @counter==1,2 */
avg_power_diff = power_diff / counter;
PHYDM_DBG(dm, DBG_ANT_DIV, "avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d ))\n", avg_power_diff, counter, power_diff);
}
/* @2 [ Retry ] */
if (avg_power_diff >= power_target_L && avg_power_diff <= power_target_H) {
dm->dm_swat_table.retry_counter++;
if (dm->dm_swat_table.retry_counter <= 3) {
dm->dm_swat_table.rssi_ant_dect_result = false;
PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]]\n", avg_power_diff);
/* @3 [ Scan again ] */
odm_sw_ant_div_construct_scan_chnl(adapter, scan_channel);
PlatformSetTimer(adapter, &mgnt_info->ScanTimer, 5);
return true;
} else {
dm->dm_swat_table.rssi_ant_dect_result = true;
PHYDM_DBG(dm, DBG_ANT_DIV, "[[ Still Low confidence result ]] (( retry_counter > 3 ))\n");
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
}
}
/* @2 [ Dual Antenna ] */
else if ((mgnt_info->NumBssDesc != 0) && (avg_power_diff < power_target_L)) {
dm->dm_swat_table.rssi_ant_dect_result = true;
if (dm->dm_swat_table.ANTB_ON == false) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = true;
}
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Dual antenna\n", __func__);
dm->dm_swat_table.dual_ant_counter++;
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
BT_SetBtCoexAntNum(adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
/* @3 [ Init antenna diversity ] */
dm->support_ability |= ODM_BB_ANT_DIV;
odm_ant_div_init(dm);
}
/* @2 [ Single Antenna ] */
else if (avg_power_diff > power_target_H) {
dm->dm_swat_table.rssi_ant_dect_result = true;
if (dm->dm_swat_table.ANTB_ON == true) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = false;
#if 0
/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 1); */
#endif
}
PHYDM_DBG(dm, DBG_ANT_DIV, "%s: Single antenna\n", __func__);
dm->dm_swat_table.single_ant_counter++;
}
}
#if 0
/* PHYDM_DBG(dm,DBG_ANT_DIV, "is_result=(( %d ))\n",dm->dm_swat_table.rssi_ant_dect_result); */
#endif
PHYDM_DBG(dm, DBG_ANT_DIV,
"dual_ant_counter = (( %d )), single_ant_counter = (( %d )) , retry_counter = (( %d )) , aux_fail_detec_counter = (( %d ))\n\n\n",
dm->dm_swat_table.dual_ant_counter,
dm->dm_swat_table.single_ant_counter,
dm->dm_swat_table.retry_counter,
dm->dm_swat_table.aux_fail_detec_counter);
/* @2 recover the antenna setting */
if (dm->dm_swat_table.ANTB_ON == false)
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, 0xfff, (dm_swat_table->swas_no_link_bk_reg948));
PHYDM_DBG(dm, DBG_ANT_DIV,
"is_result=(( %d )), Recover Reg[948]= (( %x ))\n\n",
dm->dm_swat_table.rssi_ant_dect_result,
dm_swat_table->swas_no_link_bk_reg948);
}
/* @Check state reset to default and wait for next time. */
dm_swat_table->swas_no_link_state = 0;
mgnt_info->bScanAntDetect = false;
return false;
}
#else
return false;
#endif
return false;
}
/* @1 [3. PSD method] ========================================================== */
void odm_single_dual_antenna_detection_psd(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 channel_ori;
u8 initial_gain = 0x36;
u8 tone_idx;
u8 tone_lenth_1 = 7, tone_lenth_2 = 4;
u16 tone_idx_1[7] = {88, 104, 120, 8, 24, 40, 56};
u16 tone_idx_2[4] = {8, 24, 40, 56};
u32 psd_report_main[11] = {0}, psd_report_aux[11] = {0};
/* u8 tone_lenth_1=4, tone_lenth_2=2; */
/* u16 tone_idx_1[4]={88, 120, 24, 56}; */
/* u16 tone_idx_2[2]={ 24, 56}; */
/* u32 psd_report_main[6]={0}, psd_report_aux[6]={0}; */
u32 PSD_report_temp, max_psd_report_main = 0, max_psd_report_aux = 0;
u32 PSD_power_threshold;
u32 main_psd_result = 0, aux_psd_result = 0;
u32 regc50, reg948, regb2c, regc14, reg908;
u32 i = 0, test_num = 8;
if (dm->support_ic_type != ODM_RTL8723B)
return;
PHYDM_DBG(dm, DBG_ANT_DIV, "%s============>\n", __func__);
/* @2 [ Backup Current RF/BB Settings ] */
channel_ori = odm_get_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, RFREGOFFSETMASK);
reg948 = odm_get_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD);
regb2c = odm_get_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD);
regc50 = odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKDWORD);
regc14 = odm_get_bb_reg(dm, R_0xc14, MASKDWORD);
reg908 = odm_get_bb_reg(dm, R_0x908, MASKDWORD);
/* @2 [ setting for doing PSD function (CH4)] */
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 0); /* @disable whole CCK block */
odm_write_1byte(dm, REG_TXPAUSE, 0xFF); /* Turn off TX -> Pause TX Queue */
odm_set_bb_reg(dm, R_0xc14, MASKDWORD, 0x0); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */
/* PHYTXON while loop */
odm_set_bb_reg(dm, R_0x908, MASKDWORD, 0x803);
while (odm_get_bb_reg(dm, R_0xdf4, BIT(6))) {
i++;
if (i > 1000000) {
PHYDM_DBG(dm, DBG_ANT_DIV,
"Wait in %s() more than %d times!\n",
__FUNCTION__, i);
break;
}
}
odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH4 & 40M */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */
odm_set_bb_reg(dm, REG_FPGA0_PSD_FUNCTION, BIT(14) | BIT15, 0x0); /* 128 pt */ /* Set PSD 128 ptss */
ODM_delay_us(3000);
/* @2 [ Doing PSD Function in (CH4)] */
/* @Antenna A */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH4)\n");
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
ODM_delay_us(10);
PHYDM_DBG(dm, DBG_ANT_DIV, "dbg\n");
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
/* @if( PSD_report_temp>psd_report_main[tone_idx] ) */
psd_report_main[tone_idx] += PSD_report_temp;
}
}
/* @Antenna B */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH4)\n");
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_1; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_1[tone_idx], initial_gain);
/* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */
psd_report_aux[tone_idx] += PSD_report_temp;
}
}
/* @2 [ Doing PSD Function in (CH8)] */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */
ODM_delay_us(3000);
odm_set_bb_reg(dm, R_0xc50, 0x7f, initial_gain);
odm_set_rf_reg(dm, RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); /* Set RF to CH8 & 40M */
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0xf); /* @3 wire Disable 88c[23:20]=0xf */
ODM_delay_us(3000);
/* @Antenna A */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Main-ant (CH8)\n");
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x200);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
/* @if( PSD_report_temp>psd_report_main[tone_idx] ) */
psd_report_main[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
/* @Antenna B */
PHYDM_DBG(dm, DBG_ANT_DIV, "Switch to Aux-ant (CH8)\n");
odm_set_bb_reg(dm, R_0x948, 0xfff, 0x280);
ODM_delay_us(10);
for (i = 0; i < test_num; i++) {
for (tone_idx = 0; tone_idx < tone_lenth_2; tone_idx++) {
PSD_report_temp = phydm_get_psd_data(dm, tone_idx_2[tone_idx], initial_gain);
/* @if( PSD_report_temp>psd_report_aux[tone_idx] ) */
psd_report_aux[tone_lenth_1 + tone_idx] += PSD_report_temp;
}
}
/* @2 [ Calculate Result ] */
PHYDM_DBG(dm, DBG_ANT_DIV, "\nMain PSD Result: (ALL)\n");
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
psd_report_main[tone_idx]);
main_psd_result += psd_report_main[tone_idx];
if (psd_report_main[tone_idx] > max_psd_report_main)
max_psd_report_main = psd_report_main[tone_idx];
}
PHYDM_DBG(dm, DBG_ANT_DIV,
"--------------------------- \nTotal_Main= (( %d ))\n",
main_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Main = (( %d ))\n",
max_psd_report_main);
PHYDM_DBG(dm, DBG_ANT_DIV, "\nAux PSD Result: (ALL)\n");
for (tone_idx = 0; tone_idx < (tone_lenth_1 + tone_lenth_2); tone_idx++) {
PHYDM_DBG(dm, DBG_ANT_DIV, "[Tone-%d]: %d,\n", (tone_idx + 1),
psd_report_aux[tone_idx]);
aux_psd_result += psd_report_aux[tone_idx];
if (psd_report_aux[tone_idx] > max_psd_report_aux)
max_psd_report_aux = psd_report_aux[tone_idx];
}
PHYDM_DBG(dm, DBG_ANT_DIV,
"--------------------------- \nTotal_Aux= (( %d ))\n",
aux_psd_result);
PHYDM_DBG(dm, DBG_ANT_DIV, "MAX_Aux = (( %d ))\n\n",
max_psd_report_aux);
/* @main_psd_result=main_psd_result-max_psd_report_main; */
/* @aux_psd_result=aux_psd_result-max_psd_report_aux; */
PSD_power_threshold = (main_psd_result * 7) >> 3;
PHYDM_DBG(dm, DBG_ANT_DIV,
"[ Main_result, Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n",
main_psd_result, aux_psd_result, PSD_power_threshold);
/* @3 [ Dual Antenna ] */
if (aux_psd_result >= PSD_power_threshold) {
if (dm->dm_swat_table.ANTB_ON == false) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = true;
}
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Dual antenna\n");
#if 0
/* set bt coexDM from 1ant coexDM to 2ant coexDM */
/* @bt_set_bt_coex_ant_num(adapter, BT_COEX_ANT_TYPE_DETECTED, 2); */
#endif
/* @Init antenna diversity */
dm->support_ability |= ODM_BB_ANT_DIV;
odm_ant_div_init(dm);
}
/* @3 [ Single Antenna ] */
else {
if (dm->dm_swat_table.ANTB_ON == true) {
dm->dm_swat_table.ANTA_ON = true;
dm->dm_swat_table.ANTB_ON = false;
}
PHYDM_DBG(dm, DBG_ANT_DIV,
"odm_sw_ant_div_check_before_link(): Single antenna\n");
}
/* @2 [ Recover all parameters ] */
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, channel_ori);
odm_set_bb_reg(dm, REG_FPGA0_ANALOG_PARAMETER4, 0xf00000, 0x0); /* @3 wire enable 88c[23:20]=0x0 */
odm_set_bb_reg(dm, R_0xc50, 0x7f, regc50);
odm_set_bb_reg(dm, REG_S0_S1_PATH_SWITCH, MASKDWORD, reg948);
odm_set_bb_reg(dm, REG_AGC_TABLE_SELECT, MASKDWORD, regb2c);
odm_set_bb_reg(dm, REG_FPGA0_RFMOD, BIT(24), 1); /* @enable whole CCK block */
odm_write_1byte(dm, REG_TXPAUSE, 0x0); /* Turn on TX */ /* Resume TX Queue */
odm_set_bb_reg(dm, R_0xc14, MASKDWORD, regc14); /* @[ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] */
odm_set_bb_reg(dm, R_0x908, MASKDWORD, reg908);
return;
}
void odm_sw_ant_detect_init(void *dm_void)
{
#if (RTL8723B_SUPPORT == 1)
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
if (dm->support_ic_type != ODM_RTL8723B)
return;
/* @dm_swat_table->pre_antenna = MAIN_ANT; */
/* @dm_swat_table->cur_antenna = MAIN_ANT; */
dm_swat_table->swas_no_link_state = 0;
dm_swat_table->pre_aux_fail_detec = false;
dm_swat_table->swas_no_link_bk_reg948 = 0xff;
#ifdef CONFIG_PSD_TOOL
phydm_psd_init(dm);
#endif
#endif
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "2.1"
#if (defined(CONFIG_ANT_DETECTION))
/* @#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) */
/* @ANT Test */
#define ANTTESTALL 0x00 /*@ant A or B will be Testing*/
#define ANTTESTA 0x01 /*@ant A will be Testing*/
#define ANTTESTB 0x02 /*@ant B will be testing*/
#define MAX_ANTENNA_DETECTION_CNT 10
struct _ANT_DETECTED_INFO {
boolean is_ant_detected;
u32 db_for_ant_a;
u32 db_for_ant_b;
u32 db_for_ant_o;
};
enum dm_swas {
antenna_a = 1,
antenna_b = 2,
antenna_max = 3,
};
/* @1 [1. Single Tone method] =================================================== */
void odm_single_dual_antenna_default_setting(
void *dm_void);
boolean
odm_single_dual_antenna_detection(
void *dm_void,
u8 mode);
/* @1 [2. Scan AP RSSI method] ================================================== */
#define sw_ant_div_check_before_link odm_sw_ant_div_check_before_link
boolean
odm_sw_ant_div_check_before_link(
void *dm_void);
/* @1 [3. PSD method] ========================================================== */
void odm_single_dual_antenna_detection_psd(
void *dm_void);
void odm_sw_ant_detect_init(void *dm_void);
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
/*@#define ANTDIV_VERSION "2.0" //2014.11.04*/
/*@#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
/*@#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
/*@#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen,remove 92c 92d 8723a*/
/*@#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna*/
/*@diversity when BT is enable for 8723B*/
/*@#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not*/
/*@need to check the antenna is control by BT,*/
/*@because antenna diversity only works when */
/*@BT is disable or radio off*/
/*@#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart */
/*@Antenna 2. Add 8188F SW S0S1 Antenna*/
/*@Diversity*/
/*@#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna*/
/*@detection result from BT-coex. for 8723B,*/
/*@not from PHYDM*/
/*@#define ANTDIV_VERSION "3.6"*/ /*@2015.11.16 Stanley */
/*@#define ANTDIV_VERSION "3.7" 2015.11.20 Dino Add SmartAnt FAT Patch */
/*@#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic*/
/*@training packet num */
/*@#define ANTDIV_VERSION "3.9" 2016.01.05 Dino, Add SmartAnt cmd for*/
/*@converting single & two smtant, and add cmd*/
/*@for adjust truth table */
#define ANTDIV_VERSION "4.0" /*@2017.05.25 Mark, Add SW antenna diversity*/
/*@for 8821c because HW transient issue */
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 /*@ant A or ant Main or S1*/
#define AUX_ANT 2 /*@AntB or ant Aux or S0*/
#define MAX_ANT 3 /* @3 for AP using*/
#define ANT1_2G 0
/* @= ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */
#define ANT2_2G 1
/* @= ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */
/*smart antenna*/
#define SUPPORT_RF_PATH_NUM 4
#define SUPPORT_BEAM_PATTERN_NUM 4
#define NUM_ANTENNA_8821A 2
#define SUPPORT_BEAM_SET_PATTERN_NUM 16
#define NO_FIX_TX_ANT 0
#define FIX_TX_AT_MAIN 1
#define FIX_AUX_AT_MAIN 2
/* @Antenna Diversty Control type */
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A |\
ODM_RTL8197F | ODM_RTL8721D | ODM_RTL8710C)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B |\
ODM_RTL8195B)
#define ODM_JGR3_ANTDIV_SUPPORT (ODM_RTL8197G | ODM_RTL8723F)
#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT |\
ODM_JGR3_ANTDIV_SUPPORT)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B |\
ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D |\
ODM_RTL8197F | ODM_RTL8197G|ODM_RTL8723F)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 |\
ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8195B|ODM_RTL8723F)
#define ODM_ANTDIV_SUPPORT_IC (ODM_ANTDIV_2G_SUPPORT_IC | ODM_ANTDIV_5G_SUPPORT_IC)
#define ODM_EVM_ANTDIV_IC (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8822B |\
ODM_RTL8197G)
#define ODM_ANTDIV_2G BIT(0)
#define ODM_ANTDIV_5G BIT(1)
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define ANT_PATH_A 0
#define ANT_PATH_B 1
#define ANT_PATH_AB 2
#define FAT_ON 1
#define FAT_OFF 0
#define TX_BY_DESC 1
#define TX_BY_REG 0
#define RSSI_METHOD 0
#define EVM_METHOD 1
#define CRC32_METHOD 2
#define TP_METHOD 3
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
#define CRC32_FAIL 1
#define CRC32_OK 0
#define evm_rssi_th_high 25
#define evm_rssi_th_low 20
#define NORMAL_STATE_MIAN 1
#define NORMAL_STATE_AUX 2
#define TRAINING_STATE 3
#define FORCE_RSSI_DIFF 10
#define HT_IDX 16
#define VHT_IDX 20
#define CSI_ON 1
#define CSI_OFF 0
#define DIVON_CSIOFF 1
#define DIVOFF_CSION 2
#define BDC_DIV_TRAIN_STATE 0
#define bdc_bfer_train_state 1
#define BDC_DECISION_STATE 2
#define BDC_BF_HOLD_STATE 3
#define BDC_DIV_HOLD_STATE 4
#define BDC_MODE_1 1
#define BDC_MODE_2 2
#define BDC_MODE_3 3
#define BDC_MODE_4 4
#define BDC_MODE_NULL 0xff
/*SW S0S1 antenna diversity*/
#define SWAW_STEP_INIT 0xff
#define SWAW_STEP_PEEK 0
#define SWAW_STEP_DETERMINE 1
#define RSSI_CHECK_RESET_PERIOD 10
#define RSSI_CHECK_THRESHOLD 50
/*@Hong Lin Smart antenna*/
#define HL_SMTANT_2WIRE_DATA_LEN 24
#if (RTL8723D_SUPPORT == 1 || RTL8710C_SUPPORT == 1)
#ifndef CONFIG_ANTDIV_PERIOD
#define CONFIG_ANTDIV_PERIOD 1
#endif
#endif
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct sw_antenna_switch {
u8 double_chk_flag;
/*@If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than*/
/*@check this antenna again*/
u8 try_flag;
s32 pre_rssi;
u8 cur_antenna;
u8 pre_ant;
u8 rssi_trying;
u8 reset_idx;
u8 train_time;
u8 train_time_flag;
/*@base on RSSI difference between two antennas*/
struct phydm_timer_list sw_antdiv_timer;
u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
boolean is_sw_ant_div_by_ctrl_frame;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM phydm_sw_antenna_switch_workitem;
#endif
#endif
/* @AntDect (Before link Antenna Switch check) need to be moved*/
u16 single_ant_counter;
u16 dual_ant_counter;
u16 aux_fail_detec_counter;
u16 retry_counter;
u8 swas_no_link_state;
u32 swas_no_link_bk_reg948;
boolean ANTA_ON; /*To indicate ant A is or not*/
boolean ANTB_ON; /*@To indicate ant B is on or not*/
boolean pre_aux_fail_detec;
boolean rssi_ant_dect_result;
u8 ant_5g;
u8 ant_2g;
};
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
struct _BF_DIV_COEX_ {
boolean w_bfer_client[ODM_ASSOCIATE_ENTRY_NUM];
boolean w_bfee_client[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
u32 MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
u8 bd_ccoex_type_wbfer;
u8 num_txbfee_client;
u8 num_txbfer_client;
u8 bdc_try_counter;
u8 bdc_hold_counter;
u8 bdc_mode;
u8 bdc_active_mode;
u8 BDC_state;
u8 bdc_rx_idle_update_counter;
u8 num_client;
u8 pre_num_client;
u8 num_bf_tar;
u8 num_div_tar;
boolean is_all_div_sta_idle;
boolean is_all_bf_sta_idle;
boolean bdc_try_flag;
boolean BF_pass;
boolean DIV_pass;
};
#endif
#endif
struct phydm_fat_struct {
u8 bssid[6];
u8 antsel_rx_keep_0;
u8 antsel_rx_keep_1;
u8 antsel_rx_keep_2;
u8 antsel_rx_keep_3;
u32 ant_sum_rssi[7];
u32 ant_rssi_cnt[7];
u32 ant_ave_rssi[7];
u8 fat_state;
u8 fat_state_cnt;
u32 train_idx;
u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_ht_cnt[HT_IDX];
u16 aux_ht_cnt[HT_IDX];
u16 main_vht_cnt[VHT_IDX];
u16 aux_vht_cnt[VHT_IDX];
u16 main_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 main_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u16 aux_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
u8 rx_idle_ant;
u8 rx_idle_ant2;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 ant_div_on_off;
u8 div_path_type;
boolean is_become_linked;
boolean get_stats;
u32 min_max_rssi;
u8 idx_ant_div_counter_2g;
u8 idx_ant_div_counter_5g;
u8 ant_div_2g_5g;
#ifdef ODM_EVM_ENHANCE_ANTDIV
/*@For 1SS RX phy rate*/
u32 main_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_evm_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 main_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_evm_cnt[ODM_ASSOCIATE_ENTRY_NUM];
/*@For 2SS RX phy rate*/
u32 main_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A1+B*/
u32 aux_evm_2ss_sum[ODM_ASSOCIATE_ENTRY_NUM][2];/*@2SS with A2+B*/
u32 main_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u32 aux_evm_2ss_cnt[ODM_ASSOCIATE_ENTRY_NUM];
boolean evm_method_enable;
u8 target_ant_evm;
u8 target_ant_crc32;
u8 target_ant_tp;
u8 target_ant_enhance;
u8 pre_target_ant_enhance;
u16 main_mpdu_ok_cnt;
u16 aux_mpdu_ok_cnt;
u32 crc32_ok_cnt;
u32 crc32_fail_cnt;
u32 main_crc32_ok_cnt;
u32 aux_crc32_ok_cnt;
u32 main_crc32_fail_cnt;
u32 aux_crc32_fail_cnt;
u32 main_tp;
u32 aux_tp;
u32 main_tp_cnt;
u32 aux_tp_cnt;
u8 pre_antdiv_rssi;
u8 pre_antdiv_tp;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
u32 cck_ctrl_frame_cnt_main;
u32 cck_ctrl_frame_cnt_aux;
u32 ofdm_ctrl_frame_cnt_main;
u32 ofdm_ctrl_frame_cnt_aux;
u32 main_ctrl_sum;
u32 aux_ctrl_sum;
u32 main_ctrl_cnt;
u32 aux_ctrl_cnt;
#endif
u8 b_fix_tx_ant;
boolean fix_ant_bfee;
boolean enable_ctrl_frame_antdiv;
boolean use_ctrl_frame_antdiv;
boolean *is_no_csi_feedback;
boolean force_antdiv_type;
u8 antdiv_type_dbg;
u8 hw_antsw_occur;
u8 *p_force_tx_by_desc;
u8 force_tx_by_desc;
/*@A temp value, will hook to driver team's outer parameter later*/
u8 *p_default_s0_s1;
u8 default_s0_s1;
u8 ant_idx_vec[3]; /* for SP3T only, added by Jiao Qi on June.6,2020*/
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum fat_state /*@Fast antenna training*/
{
FAT_BEFORE_LINK_STATE = 0,
FAT_PREPARE_STATE = 1,
FAT_TRAINING_STATE = 2,
FAT_DECISION_STATE = 3
};
enum ant_div_type {
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
S0S1_SW_ANTDIV = 0x06, /*@8723B intrnal switch S0 S1*/
S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/
HL_SW_SMART_ANT_TYPE1 = 0x10,
/*@Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys,*/
/*@and each ant. is equipped with 4 antenna patterns*/
HL_SW_SMART_ANT_TYPE2 = 0x11
/*@Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
};
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void odm_stop_antenna_switch_dm(void *dm_void);
void phydm_enable_antenna_diversity(void *dm_void);
void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C,....*/
);
#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
void odm_sw_ant_div_rest_after_link(void *dm_void);
void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path);
void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch);
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
void phydm_antdiv_reset_statistic(void *dm_void, u32 macid);
void odm_update_rx_idle_ant(void *dm_void, u8 ant);
void odm_update_rx_idle_ant_sp3t(void *dm_void, u8 ant);
void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant);
void phydm_set_antdiv_val(void *dm_void, u32 *val_buf, u8 val_len);
#if (RTL8723B_SUPPORT == 1)
void odm_update_rx_idle_ant_8723b(void *dm_void, u8 ant, u32 default_ant,
u32 optional_ant);
#endif
#if (RTL8188F_SUPPORT == 1)
void phydm_update_rx_idle_antenna_8188F(void *dm_void, u32 default_ant);
#endif
#if (RTL8723D_SUPPORT == 1)
void phydm_set_tx_ant_pwr_8723d(void *dm_void, u8 ant);
void odm_update_rx_idle_ant_8723d(void *dm_void, u8 ant, u32 default_ant,
u32 optional_ant);
#endif
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void odm_sw_antdiv_callback(struct phydm_timer_list *timer);
void odm_sw_antdiv_workitem_callback(void *context);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void odm_sw_antdiv_workitem_callback(void *context);
void odm_sw_antdiv_callback(void *function_context);
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
void odm_sw_antdiv_callback(void *dm_void);
#endif
void odm_s0s1_sw_ant_div_by_ctrl_frame(void *dm_void, u8 step);
void odm_antsel_statistics_ctrl(void *dm_void, u8 antsel_tr_mux,
u32 rx_pwdb_all);
void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(void *dm_void,
void *phy_info_void,
void *pkt_info_void);
#endif
#ifdef ODM_EVM_ENHANCE_ANTDIV
void phydm_evm_sw_antdiv_init(void *dm_void);
void phydm_rx_rate_for_antdiv(void *dm_void, void *pkt_info_void);
void phydm_antdiv_reset_rx_rate(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_evm_antdiv_callback(struct phydm_timer_list *timer);
void phydm_evm_antdiv_workitem_callback(void *context);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void phydm_evm_antdiv_callback(void *dm_void);
void phydm_evm_antdiv_workitem_callback(void *context);
#else
void phydm_evm_antdiv_callback(void *dm_void);
#endif
#endif
void odm_hw_ant_div(void *dm_void);
#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) ||\
(defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
void odm_fast_ant_training(
void *dm_void);
void odm_fast_ant_training_callback(void *dm_void);
void odm_fast_ant_training_work_item_callback(void *dm_void);
#endif
void odm_ant_div_init(void *dm_void);
void odm_ant_div(void *dm_void);
void odm_antsel_statistics(void *dm_void, void *phy_info_void,
u8 antsel_tr_mux, u32 mac_id, u32 utility, u8 method,
u8 is_cck_rate);
void odm_process_rssi_for_ant_div(void *dm_void, void *phy_info_void,
void *pkt_info_void);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
void odm_set_tx_ant_by_tx_info(void *dm_void, u8 *desc, u8 mac_id);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
struct tx_desc;
/*@declared tx_desc here or compile error happened when enabled 8822B*/
void odm_set_tx_ant_by_tx_info(struct rtl8192cd_priv *priv,
struct tx_desc *pdesc, unsigned short aid);
#if 1 /*@def def CONFIG_WLAN_HAL*/
void odm_set_tx_ant_by_tx_info_hal(struct rtl8192cd_priv *priv,
void *pdesc_data, u16 aid);
#endif /*@#ifdef CONFIG_WLAN_HAL*/
#endif
void odm_ant_div_config(void *dm_void);
void odm_ant_div_timers(void *dm_void, u8 state);
void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void odm_ant_div_reset(void *dm_void);
void odm_antenna_diversity_init(void *dm_void);
void odm_antenna_diversity(void *dm_void);
#endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/
#endif /*@#ifndef __ODMANTDIV_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_API_H__
#define __PHYDM_API_H__
/* 2019.10.22 Add get/shift rxagc API for 8822C*/
#define PHYDM_API_VERSION "2.3"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define N_IC_TX_OFFEST_5_BIT (ODM_RTL8188E | ODM_RTL8192E)
#define N_IC_TX_OFFEST_6_BIT (ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B |\
ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8195A |\
ODM_RTL8188F)
#define N_IC_TX_OFFEST_7_BIT (ODM_RTL8721D | ODM_RTL8710C)
#define CN_CNT_MAX 10 /*@max condition number threshold*/
#define FUNC_ENABLE 1
#define FUNC_DISABLE 2
/*@NBI API------------------------------------*/
#define NBI_128TONE 27 /*register table size*/
#define NBI_256TONE 59 /*register table size*/
#define NUM_START_CH_80M 7
#define NUM_START_CH_40M 14
#define CH_OFFSET_40M 2
#define CH_OFFSET_80M 6
#define FFT_128_TYPE 1
#define FFT_256_TYPE 2
#define FREQ_POSITIVE 1
#define FREQ_NEGATIVE 2
/*@------------------------------------------------*/
enum phystat_rpt {
PHY_PWDB = 0,
PHY_EVM = 1,
PHY_CFO = 2,
PHY_RXSNR = 3,
PHY_LGAIN = 4,
PHY_HT_AAGC_GAIN = 5,
};
#ifndef PHYDM_COMMON_API_SUPPORT
#define INVALID_RF_DATA 0xffffffff
#define INVALID_TXAGC_DATA 0xff
#endif
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_api_stuc {
u32 rxiqc_reg1; /*N-mode: for pathA REG0xc14*/
u32 rxiqc_reg2; /*N-mode: for pathB REG0xc1c*/
u8 tx_queue_bitmap; /*REG0x520[23:16]*/
u8 ccktx_path;
u8 pri_ch_idx;
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
enum channel_width phydm_rxsc_2_bw(void *dm_void, u8 rxsc);
void phydm_reset_bb_hw_cnt(void *dm_void);
void phydm_dynamic_ant_weighting(void *dm_void);
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void phydm_ant_weight_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
void phydm_trx_antenna_setting_init(void *dm_void, u8 num_rf_path);
void phydm_config_ofdm_rx_path(void *dm_void, enum bb_path path);
void phydm_config_cck_rx_path(void *dm_void, enum bb_path path);
void phydm_config_cck_rx_antenna_init(void *dm_void);
void phydm_config_trx_path(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_config_ofdm_tx_path(void *dm_void, enum bb_path path);
void phydm_config_cck_tx_path(void *dm_void, enum bb_path path);
void phydm_tx_2path(void *dm_void);
void phydm_stop_3_wire(void *dm_void, u8 set_type);
u8 phydm_stop_ic_trx(void *dm_void, u8 set_type);
void phydm_dis_cck_trx(void *dm_void, u8 set_type);
void phydm_bw_fixed_enable(void *dm_void, u8 enable);
void phydm_bw_fixed_setting(void *dm_void);
void phydm_set_ext_switch(void *dm_void, u32 ext_ant_switch);
void phydm_nbi_enable(void *dm_void, u32 enable);
u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
u32 sec_ch);
u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
u32 sec_ch);
void phydm_nbi_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_csi_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_stop_ck320(void *dm_void, u8 enable);
boolean
phydm_set_bb_txagc_offset(void *dm_void, s8 power_offset, u8 add_half_db);
boolean phydm_spur_case_mapping(void *dm_void);
enum odm_rf_band phydm_ch_to_rf_band(void *dm_void, u8 central_ch);
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
u32 phydm_rf_psd_jgr3(void *dm_void, u8 path, u32 tone_idx);
u8 phydm_csi_mask_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw,
u32 f_intf, u32 sec_ch, u8 wgt);
void phydm_set_csi_mask_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
u8 wgt);
u8 phydm_nbi_setting_jgr3(void *dm_void, u32 enable, u32 ch, u32 bw, u32 f_intf,
u32 sec_ch, u8 path);
void phydm_set_nbi_reg_jgr3(void *dm_void, u32 tone_idx_tmp, u8 tone_direction,
u8 path);
void phydm_nbi_enable_jgr3(void *dm_void, u32 enable, u8 path);
u8 phydm_phystat_rpt_jgr3(void *dm_void, enum phystat_rpt info,
enum rf_path ant_path);
void phydm_user_position_for_sniffer(void *dm_void, u8 user_position);
#endif
#ifdef PHYDM_COMMON_API_SUPPORT
void phydm_reset_txagc(void *dm_void);
boolean
phydm_api_shift_txagc(void *dm_void, u32 pwr_offset, enum rf_path path,
boolean is_positive);
boolean
phydm_api_set_txagc(void *dm_void, u32 power_index, enum rf_path path,
u8 hw_rate, boolean is_single_rate);
u8 phydm_api_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate);
#if (RTL8822C_SUPPORT)
void phydm_shift_rxagc_table(void *dm_void, boolean shift_up, u8 shift);
#endif
boolean
phydm_api_switch_bw_channel(void *dm_void, u8 central_ch, u8 primary_ch_idx,
enum channel_width bandwidth);
boolean
phydm_api_trx_mode(void *dm_void, enum bb_path tx_path, enum bb_path rx_path,
enum bb_path tx_path_ctrl);
#endif
#ifdef PHYDM_COMMON_API_NOT_SUPPORT
u8 config_phydm_read_txagc_n(void *dm_void, enum rf_path path, u8 hw_rate);
#endif
#ifdef CONFIG_MCC_DM
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void phydm_dynamic_ant_weighting_mcc_8822b(void *dm_void);
#endif /*#ifdef DYN_ANT_WEIGHTING_SUPPORT*/
void phydm_fill_mcccmd(void *dm_void, u8 regid, u16 reg_add,
u8 val0, u8 val1);
u8 phydm_check(void *dm_void);
void phydm_mcc_init(void *dm_void);
void phydm_mcc_switch(void *dm_void);
#endif /*#ifdef CONFIG_MCC_DM*/
#endif

725
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@ -0,0 +1,725 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_AUTO_DEGBUG
void phydm_check_hang_reset(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
atd_t->dbg_step = 0;
atd_t->auto_dbg_type = AUTO_DBG_STOP;
phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
dm->debug_components &= (~ODM_COMP_API);
}
void phydm_check_hang_init(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
atd_t->dbg_step = 0;
atd_t->auto_dbg_type = AUTO_DBG_STOP;
phydm_pause_dm_watchdog(dm, PHYDM_RESUME);
}
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
void phydm_auto_check_hang_engine_n(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
struct n_dbgport_803 dbgport_803 = {0};
u32 value32_tmp = 0, value32_tmp_2 = 0;
u8 i;
u32 curr_dbg_port_val[DBGPORT_CHK_NUM] = {0, 0, 0, 0, 0, 0};
u16 curr_ofdm_t_cnt;
u16 curr_ofdm_r_cnt;
u16 curr_cck_t_cnt;
u16 curr_cck_r_cnt;
u16 curr_ofdm_crc_error_cnt;
u16 curr_cck_crc_error_cnt;
u16 diff_ofdm_t_cnt;
u16 diff_ofdm_r_cnt;
u16 diff_cck_t_cnt;
u16 diff_cck_r_cnt;
u16 diff_ofdm_crc_error_cnt;
u16 diff_cck_crc_error_cnt;
u8 rf_mode;
if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
return;
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
phydm_check_hang_reset(dm);
return;
}
if (atd_t->dbg_step == 0) {
pr_debug("dbg_step=0\n\n");
/*Reset all packet counter*/
odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
} else if (atd_t->dbg_step == 1) {
pr_debug("dbg_step=1\n\n");
/*Check packet counter Register*/
atd_t->ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
atd_t->ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
atd_t->ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
MASKHWORD);
atd_t->cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
atd_t->cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
atd_t->cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
0x3fff);
/*Check Debug Port*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
(u32)atd_t->dbg_port_table[i])
) {
atd_t->dbg_port_val[i] =
phydm_get_bb_dbg_port_val(dm);
phydm_release_bb_dbg_port(dm);
}
}
} else if (atd_t->dbg_step == 2) {
pr_debug("dbg_step=2\n\n");
/*Check packet counter Register*/
curr_ofdm_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9cc, MASKHWORD);
curr_ofdm_r_cnt = (u16)odm_get_bb_reg(dm, R_0xf94, MASKLWORD);
curr_ofdm_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf94,
MASKHWORD);
curr_cck_t_cnt = (u16)odm_get_bb_reg(dm, R_0x9d0, MASKHWORD);
curr_cck_r_cnt = (u16)odm_get_bb_reg(dm, R_0xfa0, MASKHWORD);
curr_cck_crc_error_cnt = (u16)odm_get_bb_reg(dm, R_0xf84,
0x3fff);
/*Check Debug Port*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3,
(u32)atd_t->dbg_port_table[i])
) {
curr_dbg_port_val[i] =
phydm_get_bb_dbg_port_val(dm);
phydm_release_bb_dbg_port(dm);
}
}
/*=== Make check hang decision ===============================*/
pr_debug("Check Hang Decision\n\n");
/* ----- Check RF Register -----------------------------------*/
for (i = 0; i < dm->num_rf_path; i++) {
rf_mode = (u8)odm_get_rf_reg(dm, i, RF_0x0, 0xf0000);
pr_debug("RF0x0[%d] = 0x%x\n", i, rf_mode);
if (rf_mode > 3) {
pr_debug("Incorrect RF mode\n");
pr_debug("ReasonCode:RHN-1\n");
}
}
value32_tmp = odm_get_rf_reg(dm, 0, RF_0xb0, 0xf0000);
if (dm->support_ic_type == ODM_RTL8188E) {
if (value32_tmp != 0xff8c8) {
pr_debug("ReasonCode:RHN-3\n");
}
}
/* ----- Check BB Register ----------------------------------*/
/*BB mode table*/
value32_tmp = odm_get_bb_reg(dm, R_0x824, 0xe);
value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0xe);
pr_debug("BB TX mode table {A, B}= {%d, %d}\n",
value32_tmp, value32_tmp_2);
if (value32_tmp > 3 || value32_tmp_2 > 3) {
pr_debug("ReasonCode:RHN-2\n");
}
value32_tmp = odm_get_bb_reg(dm, R_0x824, 0x700000);
value32_tmp_2 = odm_get_bb_reg(dm, R_0x82c, 0x700000);
pr_debug("BB RX mode table {A, B}= {%d, %d}\n", value32_tmp,
value32_tmp_2);
if (value32_tmp > 3 || value32_tmp_2 > 3) {
pr_debug("ReasonCode:RHN-2\n");
}
/*BB HW Block*/
value32_tmp = odm_get_bb_reg(dm, R_0x800, MASKDWORD);
if (!(value32_tmp & BIT(24))) {
pr_debug("Reg0x800[24] = 0, CCK BLK is disabled\n");
pr_debug("ReasonCode: THN-3\n");
}
if (!(value32_tmp & BIT(25))) {
pr_debug("Reg0x800[24] = 0, OFDM BLK is disabled\n");
pr_debug("ReasonCode:THN-3\n");
}
/*BB Continue TX*/
value32_tmp = odm_get_bb_reg(dm, R_0xd00, 0x70000000);
pr_debug("Continue TX=%d\n", value32_tmp);
if (value32_tmp != 0) {
pr_debug("ReasonCode: THN-4\n");
}
/* ----- Check Packet Counter --------------------------------*/
diff_ofdm_t_cnt = curr_ofdm_t_cnt - atd_t->ofdm_t_cnt;
diff_ofdm_r_cnt = curr_ofdm_r_cnt - atd_t->ofdm_r_cnt;
diff_ofdm_crc_error_cnt = curr_ofdm_crc_error_cnt -
atd_t->ofdm_crc_error_cnt;
diff_cck_t_cnt = curr_cck_t_cnt - atd_t->cck_t_cnt;
diff_cck_r_cnt = curr_cck_r_cnt - atd_t->cck_r_cnt;
diff_cck_crc_error_cnt = curr_cck_crc_error_cnt -
atd_t->cck_crc_error_cnt;
pr_debug("OFDM[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->ofdm_t_cnt, atd_t->ofdm_r_cnt,
atd_t->ofdm_crc_error_cnt);
pr_debug("OFDM[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_ofdm_t_cnt, curr_ofdm_r_cnt,
curr_ofdm_crc_error_cnt);
pr_debug("OFDM_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_ofdm_t_cnt, diff_ofdm_r_cnt,
diff_ofdm_crc_error_cnt);
pr_debug("CCK[t=0~1] {TX, RX, CRC_error} = {%d, %d, %d}\n",
atd_t->cck_t_cnt, atd_t->cck_r_cnt,
atd_t->cck_crc_error_cnt);
pr_debug("CCK[t=1~2] {TX, RX, CRC_error} = {%d, %d, %d}\n",
curr_cck_t_cnt, curr_cck_r_cnt,
curr_cck_crc_error_cnt);
pr_debug("CCK_diff {TX, RX, CRC_error} = {%d, %d, %d}\n",
diff_cck_t_cnt, diff_cck_r_cnt,
diff_cck_crc_error_cnt);
/* ----- Check Dbg Port --------------------------------*/
for (i = 0; i < DBGPORT_CHK_NUM; i++) {
pr_debug("Dbg_port=((0x%x))\n",
atd_t->dbg_port_table[i]);
pr_debug("Val{pre, curr}={0x%x, 0x%x}\n",
atd_t->dbg_port_val[i], curr_dbg_port_val[i]);
if (atd_t->dbg_port_table[i] == 0) {
if (atd_t->dbg_port_val[i] ==
curr_dbg_port_val[i]) {
pr_debug("BB state hang\n");
pr_debug("ReasonCode:\n");
}
} else if (atd_t->dbg_port_table[i] == 0x803) {
if (atd_t->dbg_port_val[i] ==
curr_dbg_port_val[i]) {
/* dbgport_803 = */
/* (struct n_dbgport_803 ) */
/* (atd_t->dbg_port_val[i]); */
odm_move_memory(dm, &dbgport_803,
&atd_t->dbg_port_val[i],
sizeof(struct n_dbgport_803));
pr_debug("RSTB{BB, GLB, OFDM}={%d, %d,%d}\n",
dbgport_803.bb_rst_b,
dbgport_803.glb_rst_b,
dbgport_803.ofdm_rst_b);
pr_debug("{ofdm_tx_en, cck_tx_en, phy_tx_on}={%d, %d, %d}\n",
dbgport_803.ofdm_tx_en,
dbgport_803.cck_tx_en,
dbgport_803.phy_tx_on);
pr_debug("CCA_PP{OFDM, CCK}={%d, %d}\n",
dbgport_803.ofdm_cca_pp,
dbgport_803.cck_cca_pp);
if (dbgport_803.phy_tx_on)
pr_debug("Maybe TX Hang\n");
else if (dbgport_803.ofdm_cca_pp ||
dbgport_803.cck_cca_pp)
pr_debug("Maybe RX Hang\n");
}
} else if (atd_t->dbg_port_table[i] == 0x208) {
if ((atd_t->dbg_port_val[i] & BIT(30)) &&
(curr_dbg_port_val[i] & BIT(30))) {
pr_debug("EDCCA Pause TX\n");
pr_debug("ReasonCode: THN-2\n");
}
} else if (atd_t->dbg_port_table[i] == 0xab0) {
/* atd_t->dbg_port_val[i] & 0xffffff == 0 */
/* curr_dbg_port_val[i] & 0xffffff == 0 */
if (((atd_t->dbg_port_val[i] &
MASK24BITS) == 0) ||
((curr_dbg_port_val[i] &
MASK24BITS) == 0)) {
pr_debug("Wrong L-SIG formate\n");
pr_debug("ReasonCode: THN-1\n");
}
}
}
phydm_check_hang_reset(dm);
}
atd_t->dbg_step++;
}
void phydm_bb_auto_check_hang_start_n(
void *dm_void,
u32 *_used,
char *output,
u32 *_out_len)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"PHYDM auto check hang (N-series) is started, Please check the system log\n");
dm->debug_components |= ODM_COMP_API;
atd_t->auto_dbg_type = AUTO_DBG_CHECK_HANG;
atd_t->dbg_step = 0;
phydm_pause_dm_watchdog(dm, PHYDM_PAUSE);
*_used = used;
*_out_len = out_len;
}
void phydm_dbg_port_dump_n(void *dm_void, u32 *_used, char *output,
u32 *_out_len)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
return;
PDM_SNPF(out_len, used, output + used, out_len - used,
"not support now\n");
*_used = used;
*_out_len = out_len;
}
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
void phydm_dbg_port_dump_ac(void *dm_void, u32 *_used, char *output,
u32 *_out_len)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
if (dm->support_ic_type & ODM_IC_11N_SERIES)
return;
value32 = odm_get_bb_reg(dm, R_0xf80, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32);
if (dm->support_ic_type & ODM_RTL8822B)
odm_set_bb_reg(dm, R_0x198c, BIT(2) | BIT(1) | BIT(0), 7);
/* dbg_port = basic state machine */
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x000);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "basic state machine", value32);
}
/* dbg_port = state machine */
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x007);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "state machine", value32);
}
/* dbg_port = CCA-related*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x204);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "CCA-related", value32);
}
/* dbg_port = edcca/rxd*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x278);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "edcca/rxd", value32);
}
/* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x290);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x",
"rx_state/mux_state/ADC_MASK_OFDM", value32);
}
/* dbg_port = bf-related*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B2);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "bf-related", value32);
}
/* dbg_port = bf-related*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x2B8);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "bf-related", value32);
}
/* dbg_port = txon/rxd*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA03);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "txon/rxd", value32);
}
/* dbg_port = l_rate/l_length*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0B);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "l_rate/l_length", value32);
}
/* dbg_port = rxd/rxd_hit*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xA0D);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rxd/rxd_hit", value32);
}
/* dbg_port = dis_cca*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAA0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "dis_cca", value32);
}
/* dbg_port = tx*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAB0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "tx", value32);
}
/* dbg_port = rx plcp*/
{
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD0);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD1);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD2);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0xAD3);
value32 = odm_get_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "0x8fc", value32);
value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
PDM_SNPF(out_len, used, output + used, out_len - used,
"\r\n %-35s = 0x%x", "rx plcp", value32);
}
*_used = used;
*_out_len = out_len;
}
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_dbg_port_dump_jgr3(void *dm_void, u32 *_used, char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
/*u32 dbg_port_idx_all[3] = {0x000, 0x001, 0x002};*/
u32 val = 0;
u32 dbg_port_idx = 0;
u32 i = 0;
if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
return;
PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
"%-17s = %s\n", "DbgPort index", "Value");
#if 0
/*0x000/0x001/0x002*/
for (i = 0; i < 3; i++) {
dbg_port_idx = dbg_port_idx_all[i];
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
val = phydm_get_bb_dbg_port_val(dm);
PDM_SNPF(out_len, used, output + used, out_len - used,
"0x%-15x = 0x%x\n", dbg_port_idx, val);
phydm_release_bb_dbg_port(dm);
}
}
#endif
for (dbg_port_idx = 0x0; dbg_port_idx <= 0xfff; dbg_port_idx++) {
if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port_idx)) {
val = phydm_get_bb_dbg_port_val(dm);
PDM_VAST_SNPF(out_len, used, output + used,
out_len - used,
"0x%-15x = 0x%x\n", dbg_port_idx, val);
phydm_release_bb_dbg_port(dm);
}
}
*_used = used;
*_out_len = out_len;
}
#endif
void phydm_dbg_port_dump(void *dm_void, u32 *_used, char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
PDM_VAST_SNPF(out_len, used, output + used, out_len - used,
"------ BB debug port start ------\n");
switch (dm->ic_ip_series) {
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
case PHYDM_IC_JGR3:
phydm_dbg_port_dump_jgr3(dm, &used, output, &out_len);
break;
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
case PHYDM_IC_AC:
phydm_dbg_port_dump_ac(dm, &used, output, &out_len);
break;
#endif
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
case PHYDM_IC_N:
phydm_dbg_port_dump_n(dm, &used, output, &out_len);
break;
#endif
default:
break;
}
*_used = used;
*_out_len = out_len;
}
void phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"hang: {1} {1:Show DbgPort, 2:Auto check hang}\n");
return;
} else if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
if (var1[1] == 1) {
phydm_dbg_port_dump(dm, &used, output, &out_len);
} else if (var1[1] == 2) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
PDM_SNPF(out_len, used, output + used,
out_len - used, "Not support\n");
} else {
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_bb_auto_check_hang_start_n(dm, &used,
output,
&out_len);
#else
PDM_SNPF(out_len, used, output + used,
out_len - used, "Not support\n");
#endif
}
}
}
*_used = used;
*_out_len = out_len;
}
void phydm_auto_dbg_engine(void *dm_void)
{
u32 value32 = 0;
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
if (atd_t->auto_dbg_type == AUTO_DBG_STOP)
return;
pr_debug("%s ======>\n", __func__);
if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_HANG) {
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
pr_debug("Not Support\n");
} else {
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
phydm_auto_check_hang_engine_n(dm);
#else
pr_debug("Not Support\n");
#endif
}
} else if (atd_t->auto_dbg_type == AUTO_DBG_CHECK_RA) {
pr_debug("Not Support\n");
}
}
void phydm_auto_dbg_engine_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_auto_dbg_struct *atd_t = &dm->auto_dbg_table;
u16 dbg_port_table[DBGPORT_CHK_NUM] = {0x0, 0x803, 0x208, 0xab0,
0xab1, 0xab2};
PHYDM_DBG(dm, ODM_COMP_API, "%s ======>\n", __func__);
odm_move_memory(dm, &atd_t->dbg_port_table[0],
&dbg_port_table[0], (DBGPORT_CHK_NUM * 2));
phydm_check_hang_init(dm);
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_AUTO_DBG_H__
#define __PHYDM_AUTO_DBG_H__
#define AUTO_DBG_VERSION "1.0" /* @2017.05.015 Dino, Add phydm_auto_dbg.h*/
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define AUTO_CHK_HANG_STEP_MAX 3
#define DBGPORT_CHK_NUM 6
#ifdef PHYDM_AUTO_DEGBUG
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum auto_dbg_type_e {
AUTO_DBG_STOP = 0,
AUTO_DBG_CHECK_HANG = 1,
AUTO_DBG_CHECK_RA = 2,
AUTO_DBG_CHECK_DIG = 3
};
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct n_dbgport_803 {
/*@BYTE 3*/
u8 bb_rst_b : 1;
u8 glb_rst_b : 1;
u8 zero_1bit_1 : 1;
u8 ofdm_rst_b : 1;
u8 cck_txpe : 1;
u8 ofdm_txpe : 1;
u8 phy_tx_on : 1;
u8 tdrdy : 1;
/*@BYTE 2*/
u8 txd : 8;
/*@BYTE 1*/
u8 cck_cca_pp : 1;
u8 ofdm_cca_pp : 1;
u8 rx_rst : 1;
u8 rdrdy : 1;
u8 rxd_7_4 : 4;
/*@BYTE 0*/
u8 rxd_3_0 : 4;
u8 ofdm_tx_en : 1;
u8 cck_tx_en : 1;
u8 zero_1bit_2 : 1;
u8 clk_80m : 1;
};
struct phydm_auto_dbg_struct {
enum auto_dbg_type_e auto_dbg_type;
u8 dbg_step;
u16 dbg_port_table[DBGPORT_CHK_NUM];
u32 dbg_port_val[DBGPORT_CHK_NUM];
u16 ofdm_t_cnt;
u16 ofdm_r_cnt;
u16 cck_t_cnt;
u16 cck_r_cnt;
u16 ofdm_crc_error_cnt;
u16 cck_crc_error_cnt;
};
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_dbg_port_dump(void *dm_void, u32 *used, char *output, u32 *out_len);
void phydm_auto_dbg_console(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len);
void phydm_auto_dbg_engine(void *dm_void);
void phydm_auto_dbg_engine_init(void *dm_void);
#endif
#endif

1989
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363
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __INC_PHYDM_BEAMFORMING_H
#define __INC_PHYDM_BEAMFORMING_H
/*@Beamforming Related*/
#include "txbf/halcomtxbf.h"
#include "txbf/haltxbfjaguar.h"
#include "txbf/haltxbf8192e.h"
#include "txbf/haltxbf8814a.h"
#include "txbf/haltxbf8822b.h"
#include "txbf/haltxbfinterface.h"
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
#endif
#define MAX_BEAMFORMEE_SU 2
#define MAX_BEAMFORMER_SU 2
#if ((RTL8822B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1))
#define MAX_BEAMFORMEE_MU 6
#define MAX_BEAMFORMER_MU 1
#else
#define MAX_BEAMFORMEE_MU 0
#define MAX_BEAMFORMER_MU 0
#endif
#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
/*@for different naming between WIN and CE*/
#define BEACON_QUEUE BCN_QUEUE_INX
#define NORMAL_QUEUE MGT_QUEUE_INX
#define RT_DISABLE_FUNC RTW_DISABLE_FUNC
#define RT_ENABLE_FUNC RTW_ENABLE_FUNC
#endif
enum beamforming_entry_state {
BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
BEAMFORMING_ENTRY_STATE_INITIALIZEING,
BEAMFORMING_ENTRY_STATE_INITIALIZED,
BEAMFORMING_ENTRY_STATE_PROGRESSING,
BEAMFORMING_ENTRY_STATE_PROGRESSED
};
enum beamforming_notify_state {
BEAMFORMING_NOTIFY_NONE,
BEAMFORMING_NOTIFY_ADD,
BEAMFORMING_NOTIFY_DELETE,
BEAMFORMEE_NOTIFY_ADD_SU,
BEAMFORMEE_NOTIFY_DELETE_SU,
BEAMFORMEE_NOTIFY_ADD_MU,
BEAMFORMEE_NOTIFY_DELETE_MU,
BEAMFORMING_NOTIFY_RESET
};
enum beamforming_cap {
BEAMFORMING_CAP_NONE = 0x0,
BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er & peer ee */
BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */
BEAMFORMER_CAP = BIT(9),
BEAMFORMEE_CAP = BIT(10),
};
enum sounding_mode {
SOUNDING_SW_VHT_TIMER = 0x0,
SOUNDING_SW_HT_TIMER = 0x1,
sounding_stop_all_timer = 0x2,
SOUNDING_HW_VHT_TIMER = 0x3,
SOUNDING_HW_HT_TIMER = 0x4,
SOUNDING_STOP_OID_TIMER = 0x5,
SOUNDING_AUTO_VHT_TIMER = 0x6,
SOUNDING_AUTO_HT_TIMER = 0x7,
SOUNDING_FW_VHT_TIMER = 0x8,
SOUNDING_FW_HT_TIMER = 0x9,
};
struct _RT_BEAMFORM_STAINFO {
u8 *ra;
u16 aid;
u16 mac_id;
u8 my_mac_addr[6];
/*WIRELESS_MODE wireless_mode;*/
enum channel_width bw;
enum beamforming_cap beamform_cap;
u8 ht_beamform_cap;
u16 vht_beamform_cap;
u8 cur_beamform;
u16 cur_beamform_vht;
};
struct _RT_BEAMFORMEE_ENTRY {
boolean is_used;
boolean is_txbf;
boolean is_sound;
u16 aid; /*Used to construct AID field of NDPA packet.*/
u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id; /*Used to fill Tx DESC*/
u8 my_mac_addr[6];
u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
enum channel_width sound_bw; /*Sounding band_width*/
u16 sound_period;
enum beamforming_cap beamform_entry_cap;
enum beamforming_entry_state beamform_entry_state;
boolean is_beamforming_in_progress;
/*@u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/
/*@u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
/*@u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
u16 log_status_fail_cnt : 5; /* @0~21 */
u16 default_csi_cnt : 5; /* @0~21 */
u8 csi_matrix[327];
u16 csi_matrix_len;
u8 num_of_sounding_dim;
u8 comp_steering_num_of_bfer;
u8 su_reg_index;
/*@For MU-MIMO*/
boolean is_mu_sta;
u8 mu_reg_index;
u8 gid_valid[8];
u8 user_position[16];
};
struct _RT_BEAMFORMER_ENTRY {
boolean is_used;
/*P_AID of BFer entry is probably not used*/
u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
u8 g_id;
u8 my_mac_addr[6];
u8 mac_addr[6];
enum beamforming_cap beamform_entry_cap;
u8 num_of_sounding_dim;
u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/
u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/
u8 log_seq; /*@Modified by Jeffery @2014-10-29*/
u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/
u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/
u8 su_reg_index;
/*@For MU-MIMO*/
boolean is_mu_ap;
u8 gid_valid[8];
u8 user_position[16];
u16 aid;
};
struct _RT_SOUNDING_INFO {
u8 sound_idx;
enum channel_width sound_bw;
enum sounding_mode sound_mode;
u16 sound_period;
};
struct _RT_BEAMFORMING_OID_INFO {
u8 sound_oid_idx;
enum channel_width sound_oid_bw;
enum sounding_mode sound_oid_mode;
u16 sound_oid_period;
};
struct _RT_BEAMFORMING_INFO {
enum beamforming_cap beamform_cap;
struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
struct _RT_BEAMFORM_STAINFO beamform_sta_info;
u8 beamformee_cur_idx;
struct phydm_timer_list beamforming_timer;
struct phydm_timer_list mu_timer;
struct _RT_SOUNDING_INFO sounding_info;
struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
struct _HAL_TXBF_INFO txbf_info;
u8 sounding_sequence;
u8 beamformee_su_cnt;
u8 beamformer_su_cnt;
u32 beamformee_su_reg_maping;
u32 beamformer_su_reg_maping;
/*@For MU-MINO*/
u8 beamformee_mu_cnt;
u8 beamformer_mu_cnt;
u32 beamformee_mu_reg_maping;
u8 mu_ap_index;
boolean is_mu_sounding;
u8 first_mu_bfee_index;
boolean is_mu_sounding_in_progress;
boolean dbg_disable_mu_tx;
boolean apply_v_matrix;
boolean snding3ss;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *source_adapter;
#endif
/* @Control register */
u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */
u8 tx_bf_data_rate;
u8 last_usb_hub;
};
void phydm_get_txbf_device_num(
void *dm_void,
u8 macid);
struct _RT_NDPA_STA_INFO {
u16 aid : 12;
u16 feedback_type : 1;
u16 nc_index : 3;
};
enum phydm_acting_type {
phydm_acting_as_ibss = 0,
phydm_acting_as_ap = 1
};
enum beamforming_cap
phydm_beamforming_get_entry_beam_cap_by_mac_id(
void *dm_void,
u8 mac_id);
struct _RT_BEAMFORMEE_ENTRY *
phydm_beamforming_get_bfee_entry_by_addr(
void *dm_void,
u8 *RA,
u8 *idx);
struct _RT_BEAMFORMER_ENTRY *
phydm_beamforming_get_bfer_entry_by_addr(
void *dm_void,
u8 *TA,
u8 *idx);
void phydm_beamforming_notify(
void *dm_void);
boolean
phydm_acting_determine(
void *dm_void,
enum phydm_acting_type type);
void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr);
void beamforming_leave(
void *dm_void,
u8 *RA);
boolean
beamforming_start_fw(
void *dm_void,
u8 idx);
void beamforming_check_sounding_success(
void *dm_void,
boolean status);
void phydm_beamforming_end_sw(
void *dm_void,
boolean status);
void beamforming_timer_callback(
void *dm_void);
void phydm_beamforming_init(
void *dm_void);
enum beamforming_cap
phydm_beamforming_get_beam_cap(
void *dm_void,
struct _RT_BEAMFORMING_INFO *beam_info);
enum beamforming_cap
phydm_get_beamform_cap(
void *dm_void);
boolean
beamforming_control_v1(
void *dm_void,
u8 *RA,
u8 AID,
u8 mode,
enum channel_width BW,
u8 rate);
boolean
phydm_beamforming_control_v2(
void *dm_void,
u8 idx,
u8 mode,
enum channel_width BW,
u16 period);
void phydm_beamforming_watchdog(
void *dm_void);
void beamforming_sw_timer_callback(
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct phydm_timer_list *timer
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void *function_context
#endif
);
boolean
beamforming_send_ht_ndpa_packet(
void *dm_void,
u8 *RA,
enum channel_width BW,
u8 q_idx);
boolean
beamforming_send_vht_ndpa_packet(
void *dm_void,
u8 *RA,
u16 AID,
enum channel_width BW,
u8 q_idx);
#else
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
#define beamforming_gid_paid(adapter, tcb)
#define phydm_acting_determine(dm, type) false
#define beamforming_enter(dm, sta_idx, my_mac_addr)
#define beamforming_leave(dm, RA)
#define beamforming_end_fw(dm)
#define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
#define beamforming_control_v2(dm, idx, mode, BW, period) true
#define phydm_beamforming_end_sw(dm, _status)
#define beamforming_timer_callback(dm)
#define phydm_beamforming_init(dm)
#define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
#define beamforming_watchdog(dm)
#define phydm_beamforming_watchdog(dm)
#endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
#endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_CCK_PD_H__
#define __PHYDM_CCK_PD_H__
/* 2019.12.25 decrease CS_ratio in 8822C due to Lenovo test result(PCIE-5136).*/
#define CCK_PD_VERSION "4.0"
/*@
* 1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define CCK_FA_MA_RESET 0xffffffff
#define INVALID_CS_RATIO_0 0x1b /* @ only for type4 ICs*/
#define INVALID_CS_RATIO_1 0x1d /* @ only for type4 ICs*/
#define MAXVALID_CS_RATIO 0x1f
/*@Run time flag of CCK_PD HW type*/
#define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\
ODM_RTL8195A | ODM_RTL8188F)
#define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
#define CCK_PD_IC_TYPE3 (ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C)
/*@extend for different bw & path*/
#define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
#define CCK_PD_IC_TYPE5 (ODM_RTL8723F) /*@extend for different CR*/
/*@Compile time flag of CCK_PD HW type*/
#if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\
RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\
RTL8195A_SUPPORT || RTL8188F_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/
#endif
#if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\
RTL8710B_SUPPORT || RTL8195B_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
#endif
#if (RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
#define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
#endif
#if (RTL8723F_SUPPORT)
#define PHYDM_COMPILE_CCKPD_TYPE5 /*@extend for different & path*/
#endif
/*@
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum cckpd_lv {
CCK_PD_LV_INIT = 0xff,
CCK_PD_LV_0 = 0,
CCK_PD_LV_1 = 1,
CCK_PD_LV_2 = 2,
CCK_PD_LV_3 = 3,
CCK_PD_LV_4 = 4,
CCK_PD_LV_MAX = 5
};
enum cckpd_mode {
CCK_BW20_1R = 0,
CCK_BW20_2R = 1,
CCK_BW20_3R = 2,
CCK_BW20_4R = 3,
CCK_BW40_1R = 4,
CCK_BW40_2R = 5,
CCK_BW40_3R = 6,
CCK_BW40_4R = 7
};
enum dcc_mode {
DCC_DIG = 0,
DCC_CCK_PD = 1
};
enum phydm_cck_pd_trend {
CCKPD_STABLE = 0,
CCKPD_INCREASING = 1,
CCKPD_DECREASING = 2
};
/*@
* 1 ============================================================
* 1 structure
* 1 ============================================================
*/
#ifdef PHYDM_SUPPORT_CCKPD
#ifdef PHYDM_DCC_ENHANCE
struct phydm_dcc_struct { /*DIG CCK_PD coexistence*/
boolean dcc_en;
enum dcc_mode dcc_mode;
u32 dig_execute_cnt;
u8 dcc_ratio;
};
#endif
struct phydm_cckpd_struct {
u8 cckpd_hw_type;
u8 cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
u32 cck_fa_ma;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 pause_lv;
u8 cck_n_rx;
u16 cck_fa_th[2];
enum channel_width cck_bw;
enum cckpd_lv cck_pd_lv;
#ifdef PHYDM_COMPILE_CCKPD_TYPE2
u8 cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/
u8 aaa_default; /*@Init cs_ratio value - 0xaaa*/
#endif
#ifdef PHYDM_COMPILE_CCKPD_TYPE3
/*Default value*/
u8 cck_pd_20m_1r;
u8 cck_pd_20m_2r;
u8 cck_pd_40m_1r;
u8 cck_pd_40m_2r;
u8 cck_cs_ratio_20m_1r;
u8 cck_cs_ratio_20m_2r;
u8 cck_cs_ratio_40m_1r;
u8 cck_cs_ratio_40m_2r;
u8 cck_din_shift_opt;
/*Current value*/
u8 cur_cck_pd_20m_1r;
u8 cur_cck_pd_20m_2r;
u8 cur_cck_pd_40m_1r;
u8 cur_cck_pd_40m_2r;
u8 cur_cck_cs_ratio_20m_1r;
u8 cur_cck_cs_ratio_20m_2r;
u8 cur_cck_cs_ratio_40m_1r;
u8 cur_cck_cs_ratio_40m_2r;
#endif
#ifdef PHYDM_COMPILE_CCKPD_TYPE4
/*@[bw][nrx][0:PD/1:CS][lv]*/
u8 cckpd_jgr3[2][4][2][CCK_PD_LV_MAX];
#endif
#ifdef PHYDM_COMPILE_CCKPD_TYPE5
/*@[bw][nrx][0:PD/1:CS][lv]*/
u8 cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];
#endif
};
#endif
/*@
* 1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
void phydm_cck_pd_th(void *dm_void);
void phydm_cck_pd_init(void *dm_void);
#ifdef PHYDM_DCC_ENHANCE
void phydm_cckpd_type4_dcc(void *dm_void);
void phydm_dig_cckpd_coex(void *dm_void);
void phydm_dig_cckpd_coex_init(void *dm_void);
void phydm_dig_cckpd_coex_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_CCK_RX_PATHDIV_SUPPORT /* @PHYDM-342*/
void phydm_cck_rx_pathdiv_manaul(void *dm_void, boolean en_cck_rx_pathdiv)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* @Can not apply for 98F/14B/97G from DD YC*/
if (en_cck_rx_pathdiv) {
odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x0);
odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x1);
} else {
odm_set_bb_reg(dm, R_0x1a14, BIT(7), 0x1);
odm_set_bb_reg(dm, R_0x1a74, BIT(8), 0x0);
}
}
void phydm_cck_rx_pathdiv_watchdog(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
u8 rssi_th = 0;
u32 rssi_a = 0, rssi_b = 0, rssi_avg = 0;
if (!cckrx_t->en_cck_rx_pathdiv)
return;
rssi_a = PHYDM_DIV(cckrx_t->path_a_sum, cckrx_t->path_a_cnt);
rssi_b = PHYDM_DIV(cckrx_t->path_b_sum, cckrx_t->path_b_cnt);
rssi_avg = (rssi_a + rssi_b) >> 1;
pr_debug("Rx-A:%d, Rx-B:%d, avg:%d\n", rssi_a, rssi_b, rssi_avg);
cckrx_t->path_a_cnt = 0;
cckrx_t->path_a_sum = 0;
cckrx_t->path_b_cnt = 0;
cckrx_t->path_b_sum = 0;
if (fa_t->cnt_all >= 100)
rssi_th = cckrx_t->rssi_fa_th;
else
rssi_th = cckrx_t->rssi_th;
if (dm->phy_dbg_info.num_qry_beacon_pkt > 14 && rssi_avg <= rssi_th)
phydm_cck_rx_pathdiv_manaul(dm, true);
else
phydm_cck_rx_pathdiv_manaul(dm, false);
}
void phydm_cck_rx_pathdiv_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
cckrx_t->en_cck_rx_pathdiv = false;
cckrx_t->path_a_cnt = 0;
cckrx_t->path_a_sum = 0;
cckrx_t->path_b_cnt = 0;
cckrx_t->path_b_sum = 0;
cckrx_t->rssi_fa_th = 45;
cckrx_t->rssi_th = 25;
}
void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
void *pkt_info_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_phyinfo_struct *phy_info = NULL;
struct phydm_perpkt_info_struct *pktinfo = NULL;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
if (!(pktinfo->is_packet_to_self || pktinfo->is_packet_match_bssid))
return;
if (pktinfo->is_cck_rate)
return;
cckrx_t->path_a_sum += phy_info->rx_mimo_signal_strength[0];
cckrx_t->path_a_cnt++;
cckrx_t->path_b_sum += phy_info->rx_mimo_signal_strength[1];
cckrx_t->path_b_cnt++;
}
void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cck_rx_pathdiv *cckrx_t = &dm->dm_cck_rx_pathdiv_table;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
if (!(dm->support_ic_type & ODM_RTL8822C))
return;
for (i = 0; i < 3; i++) {
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
}
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"CCK rx pathdiv manual on: {1} {En}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"CCK rx pathdiv watchdog on: {2} {En}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"CCK rx pathdiv rssi_th : {3} {th} {fa_th}\n");
} else if (var1[0] == 1) {
if (var1[1] == 1)
phydm_cck_rx_pathdiv_manaul(dm, true);
else
phydm_cck_rx_pathdiv_manaul(dm, false);
} else if (var1[0] == 2) {
if (var1[1] == 1) {
cckrx_t->en_cck_rx_pathdiv = true;
} else {
cckrx_t->en_cck_rx_pathdiv = false;
phydm_cck_rx_pathdiv_manaul(dm, false);
}
} else if (var1[0] == 3) {
cckrx_t->rssi_th = (u8)var1[1];
cckrx_t->rssi_fa_th = (u8)var1[2];
}
*_used = used;
*_out_len = out_len;
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_CCK_RX_PATHDIV_H__
#define __PHYDM_CCK_RX_PATHDIV_H__
#define CCK_RX_PATHDIV_VERSION "1.1"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_cck_rx_pathdiv {
boolean en_cck_rx_pathdiv;
u32 path_a_sum;
u32 path_b_sum;
u16 path_a_cnt;
u16 path_b_cnt;
u8 rssi_fa_th;
u8 rssi_th;
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_cck_rx_pathdiv_watchdog(void *dm_void);
void phydm_cck_rx_pathdiv_init(void *dm_void);
void phydm_process_rssi_for_cck_rx_pathdiv(void *dm_void, void *phy_info_void,
void *pkt_info_void);
void phydm_cck_rx_pathdiv_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMCCX_H__
#define __PHYDMCCX_H__
/* 2020.08.12 split env_mntr api into set_env_mntr and result_env_mntr api for dig_fa_source*/
#define CCX_VERSION "4.7"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define CCX_EN 1
#define MAX_ENV_MNTR_TIME 8 /*second*/
#define MS_TO_US 1000
#define MS_TO_4US_RATIO 250
#define CCA_CAP 14
/*CLM*/
#define CLM_MAX_REPORT_TIME 10
#define CLM_PERIOD_MAX 65535
/*NHM*/
#define NHM_PERIOD_MAX 65534
#define NHM_TH_NUM 11 /*threshold number of NHM*/
#define NHM_RPT_NUM 12
#define NHM_IC_NOISE_TH 60 /*60/2 - 10 = 20 = -80 dBm*/
#define NHM_RPT_MAX 255
#ifdef NHM_DYM_PW_TH_SUPPORT
#define DYM_PWTH_CCA_CAP 24
#endif
#define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM/FAHM threshold = IGI * 2*/
#define NTH_TH_2_RSSI(th) ((th >> 1) - 10)
/*FAHM*/
#define FAHM_INCLU_FA BIT(0)
#define FAHM_INCLU_CRC_OK BIT(1)
#define FAHM_INCLU_CRC_ERR BIT(2)
#define FAHM_PERIOD_MAX 65534
#define FAHM_TH_NUM 11 /*threshold number of FAHM*/
#define FAHM_RPT_NUM 12
/*IFS-CLM*/
#define IFS_CLM_PERIOD_MAX 65535
#define IFS_CLM_NUM 4
#define NHM_SUCCESS BIT(0)
#define CLM_SUCCESS BIT(1)
#define FAHM_SUCCESS BIT(2)
#define IFS_CLM_SUCCESS BIT(3)
#define ENV_MNTR_FAIL 0xff
/* @1 ============================================================
* 1 enumrate
* 1 ============================================================
*/
enum phydm_clm_level {
CLM_RELEASE = 0,
CLM_LV_1 = 1, /* @Low Priority function */
CLM_LV_2 = 2, /* @Middle Priority function */
CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */
CLM_LV_4 = 4, /* @Debug function (the highest priority) */
CLM_MAX_NUM = 5
};
enum phydm_nhm_level {
NHM_RELEASE = 0,
NHM_LV_1 = 1, /* @Low Priority function */
NHM_LV_2 = 2, /* @Middle Priority function */
NHM_LV_3 = 3, /* @High priority function (ex: Check hang function) */
NHM_LV_4 = 4, /* @Debug function (the highest priority) */
NHM_MAX_NUM = 5
};
enum phydm_fahm_level {
FAHM_RELEASE = 0,
FAHM_LV_1 = 1, /* Low Priority function */
FAHM_LV_2 = 2, /* Middle Priority function */
FAHM_LV_3 = 3, /* High priority function (ex: Check hang function) */
FAHM_LV_4 = 4, /* Debug function (the highest priority) */
FAHM_MAX_NUM = 5
};
enum phydm_ifs_clm_level {
IFS_CLM_RELEASE = 0,
IFS_CLM_LV_1 = 1, /* @Low Priority function */
IFS_CLM_LV_2 = 2, /* @Middle Priority function */
IFS_CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */
IFS_CLM_LV_4 = 4, /* @Debug function (the highest priority) */
IFS_CLM_MAX_NUM = 5
};
enum nhm_divider_opt_all {
NHM_CNT_ALL = 0, /*nhm SUM report <= 255*/
NHM_VALID = 1, /*nhm SUM report = 255*/
NHM_CNT_INIT
};
enum nhm_setting {
SET_NHM_SETTING,
STORE_NHM_SETTING,
RESTORE_NHM_SETTING
};
enum nhm_option_cca_all {
NHM_EXCLUDE_CCA = 0,
NHM_INCLUDE_CCA = 1,
NHM_CCA_INIT
};
enum nhm_option_txon_all {
NHM_EXCLUDE_TXON = 0,
NHM_INCLUDE_TXON = 1,
NHM_TXON_INIT
};
enum nhm_application {
NHM_BACKGROUND = 0,/*@default*/
NHM_ACS = 1,
IEEE_11K_HIGH = 2,
IEEE_11K_LOW = 3,
INTEL_XBOX = 4,
NHM_DBG = 5, /*@manual trigger*/
};
enum clm_application {
CLM_BACKGROUND = 0,/*@default*/
CLM_ACS = 1,
};
enum fahm_application {
FAHM_BACKGROUND = 0,/*default*/
FAHM_ACS = 1,
FAHM_DBG = 2, /*manual trigger*/
};
enum ifs_clm_application {
IFS_CLM_BACKGROUND = 0,/*default*/
IFS_CLM_ACS = 1,
IFS_CLM_HP_TAS = 2,
IFS_CLM_DBG = 3,
};
enum clm_monitor_mode {
CLM_DRIVER_MNTR = 1,
CLM_FW_MNTR = 2
};
enum phydm_ifs_clm_unit {
IFS_CLM_4 = 0, /*4us*/
IFS_CLM_8 = 1, /*8us*/
IFS_CLM_12 = 2, /*12us*/
IFS_CLM_16 = 3, /*16us*/
IFS_CLM_INIT
};
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct env_trig_rpt {
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
};
struct env_mntr_rpt {
u8 nhm_ratio;
u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
u8 nhm_result[NHM_RPT_NUM];
u8 clm_ratio;
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
u8 nhm_noise_pwr; /*including r[0]~r[10]*/
u8 nhm_pwr; /*including r[0]~r[11]*/
};
struct enhance_mntr_trig_rpt {
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
u8 fahm_rpt_stamp;
u8 ifs_clm_rpt_stamp;
};
struct enhance_mntr_rpt {
u8 nhm_ratio;
u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
u8 nhm_result[NHM_RPT_NUM];
u8 clm_ratio;
u8 nhm_rpt_stamp;
u8 clm_rpt_stamp;
u8 nhm_noise_pwr; /*including r[0]~r[10]*/
u8 nhm_pwr; /*including r[0]~r[11]*/
u16 fahm_result[NHM_RPT_NUM];
u8 fahm_rpt_stamp;
u8 fahm_pwr;
u8 fahm_ratio;
u8 fahm_denom_ratio;
u8 fahm_inclu_cck;
u8 ifs_clm_rpt_stamp;
u8 ifs_clm_tx_ratio;
u8 ifs_clm_edcca_excl_cca_ratio;
u8 ifs_clm_cck_fa_ratio;
u8 ifs_clm_cck_cca_excl_fa_ratio;
u8 ifs_clm_ofdm_fa_ratio;
u8 ifs_clm_ofdm_cca_excl_fa_ratio;
};
struct nhm_para_info {
enum nhm_option_txon_all incld_txon; /*@Include TX on*/
enum nhm_option_cca_all incld_cca; /*@Include CCA*/
enum nhm_divider_opt_all div_opt; /*@divider option*/
enum nhm_application nhm_app;
enum phydm_nhm_level nhm_lv;
u16 mntr_time; /*@0~262 unit ms*/
boolean en_1db_mode;
u8 nhm_th0_manual; /* for 1-db mode*/
};
struct clm_para_info {
enum clm_application clm_app;
enum phydm_clm_level clm_lv;
u16 mntr_time; /*@0~262 unit ms*/
};
struct fahm_para_info {
enum fahm_application app;
enum phydm_fahm_level lv;
u16 mntr_time; /*0~262 unit ms*/
u8 numer_opt;
u8 denom_opt;
boolean en_1db_mode;
u8 th0_manual;/* for 1-db mode*/
};
struct ifs_clm_para_info {
enum ifs_clm_application ifs_clm_app;
enum phydm_ifs_clm_level ifs_clm_lv;
enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*unit*/
u16 mntr_time; /*ms*/
boolean ifs_clm_th_en[IFS_CLM_NUM];
u16 ifs_clm_th_low[IFS_CLM_NUM];
u16 ifs_clm_th_high[IFS_CLM_NUM];
s16 th_shift;
};
struct ccx_info {
u32 nhm_trigger_time;
u32 clm_trigger_time;
u32 fahm_trigger_time;
u32 ifs_clm_trigger_time;
u64 start_time; /*@monitor for the test duration*/
u8 ccx_watchdog_result;
#ifdef NHM_SUPPORT
enum nhm_application nhm_app;
enum nhm_option_txon_all nhm_include_txon;
enum nhm_option_cca_all nhm_include_cca;
enum nhm_divider_opt_all nhm_divider_opt;
/*Report*/
u8 nhm_th[NHM_TH_NUM];
u8 nhm_result[NHM_RPT_NUM];
u8 nhm_wgt[NHM_RPT_NUM];
u16 nhm_period; /* @4us per unit */
u8 nhm_igi;
u8 nhm_manual_ctrl;
u8 nhm_ratio; /*@1% per nuit, it means the interference igi can't overcome.*/
u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/
u8 nhm_rpt_sum;
u8 nhm_set_lv;
boolean nhm_ongoing;
u8 nhm_rpt_stamp;
u8 nhm_level; /*including r[0]~r[10]*/
u8 nhm_level_valid;
u8 nhm_pwr; /*including r[0]~r[11]*/
#ifdef NHM_DYM_PW_TH_SUPPORT
boolean nhm_dym_pw_th_en;
boolean dym_pwth_manual_ctrl;
u8 pw_th_rf20_ori;
u8 pw_th_rf20_cur;
u8 nhm_pw_th_max;
u8 nhm_period_decre;
u8 nhm_sl_pw_th;
#endif
#endif
#ifdef CLM_SUPPORT
enum clm_application clm_app;
u8 clm_manual_ctrl;
u8 clm_set_lv;
boolean clm_ongoing;
u16 clm_period; /* @4us per unit */
u16 clm_result;
u8 clm_ratio;
u32 clm_fw_result_acc;
u8 clm_fw_result_cnt;
enum clm_monitor_mode clm_mntr_mode;
u8 clm_rpt_stamp;
#endif
#ifdef FAHM_SUPPORT
enum fahm_application fahm_app;
boolean fahm_ongoing;
u8 fahm_numer_opt;
u8 fahm_denom_opt;
boolean fahm_inclu_cck;
u8 fahm_th[NHM_TH_NUM];
u16 fahm_result[NHM_RPT_NUM];
u16 fahm_result_sum;
u16 fahm_denom_result;
u16 fahm_period; /*unit: 4us*/
u8 fahm_igi;
u8 fahm_manual_ctrl;
u8 fahm_set_lv;
u8 fahm_rpt_stamp;
u8 fahm_pwr; /*including r[0]~r[11]*/
u8 fahm_ratio;
u8 fahm_denom_ratio;
#endif
#ifdef IFS_CLM_SUPPORT
enum ifs_clm_application ifs_clm_app;
/*Control*/
enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*4,8,12,16us per unit*/
u16 ifs_clm_period;
boolean ifs_clm_th_en[IFS_CLM_NUM];
u16 ifs_clm_th_low[IFS_CLM_NUM];
u16 ifs_clm_th_high[IFS_CLM_NUM];
/*Flow control*/
u8 ifs_clm_set_lv;
u8 ifs_clm_manual_ctrl;
boolean ifs_clm_ongoing;
/*Report*/
u8 ifs_clm_rpt_stamp;
u16 ifs_clm_tx;
u16 ifs_clm_edcca_excl_cca;
u16 ifs_clm_ofdmfa;
u16 ifs_clm_ofdmcca_excl_fa;
u16 ifs_clm_cckfa;
u16 ifs_clm_cckcca_excl_fa;
u8 ifs_clm_his[IFS_CLM_NUM]; /*trx_neg_edge to CCA/FA posedge per times*/
u16 ifs_clm_total_cca;
u16 ifs_clm_avg[IFS_CLM_NUM]; /*4,8,12,16us per unit*/
u16 ifs_clm_avg_cca[IFS_CLM_NUM]; /*4,8,12,16us per unit*/
u8 ifs_clm_tx_ratio;
u8 ifs_clm_edcca_excl_cca_ratio;
u8 ifs_clm_cck_fa_ratio;
u8 ifs_clm_cck_cca_excl_fa_ratio;
u8 ifs_clm_ofdm_fa_ratio;
u8 ifs_clm_ofdm_cca_excl_fa_ratio;
#endif
};
/* @1 ============================================================
* 1 Function Prototype
* 1 ============================================================
*/
u8 phydm_env_mntr_get_802_11_k_rsni(void *dm_void, s8 rcpi, s8 anpi);
#ifdef FAHM_SUPPORT
void phydm_fahm_init(void *dm_void);
void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
#ifdef NHM_SUPPORT
void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
u8 phydm_get_igi(void *dm_void, enum bb_path path);
#endif
#ifdef CLM_SUPPORT
void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
#endif
u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para,
struct clm_para_info *clm_para,
struct env_trig_rpt *rpt);
u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt);
void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#ifdef IFS_CLM_SUPPORT
void phydm_ifs_clm_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
u8 phydm_enhance_mntr_trigger(void *dm_void,
struct nhm_para_info *nhm_para,
struct clm_para_info *clm_para,
struct fahm_para_info *fahm_para,
struct ifs_clm_para_info *ifs_clm_para,
struct enhance_mntr_trig_rpt *trig_rpt);
u8 phydm_enhance_mntr_result(void *dm_void, struct enhance_mntr_rpt *rpt);
void phydm_enhance_mntr_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_env_mntr_result_watchdog(void *dm_void);
void phydm_env_mntr_set_watchdog(void *dm_void);
void phydm_env_monitor_init(void *dm_void);
#endif

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hal/phydm/phydm_cfotracking.c Normal file
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@ -0,0 +1,623 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
s32 phydm_get_cfo_hz(void *dm_void, u32 val, u8 bit_num, u8 frac_num)
{
s32 val_s = 0;
val_s = phydm_cnvrt_2_sign(val, bit_num);
if (frac_num == 10) /*@ (X*312500)/1024 ~= X*305*/
val_s *= 305;
else if (frac_num == 11) /*@ (X*312500)/2048 ~= X*152*/
val_s *= 152;
else if (frac_num == 12) /*@ (X*312500)/4096 ~= X*76*/
val_s *= 76;
return val_s;
}
#if (ODM_IC_11AC_SERIES_SUPPORT)
void phydm_get_cfo_info_ac(void *dm_void, struct phydm_cfo_rpt *cfo)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
u32 val[4] = {0};
u32 val_1[4] = {0};
u32 val_2[4] = {0};
u32 val_tmp = 0;
val[0] = odm_read_4byte(dm, R_0xd0c);
val_1[0] = odm_read_4byte(dm, R_0xd10);
val_2[0] = odm_get_bb_reg(dm, R_0xd14, 0x1fff0000);
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
val[1] = odm_read_4byte(dm, R_0xd4c);
val_1[1] = odm_read_4byte(dm, R_0xd50);
val_2[1] = odm_get_bb_reg(dm, R_0xd54, 0x1fff0000);
#endif
#if (defined(PHYDM_COMPILE_ABOVE_3SS))
val[2] = odm_read_4byte(dm, R_0xd8c);
val_1[2] = odm_read_4byte(dm, R_0xd90);
val_2[2] = odm_get_bb_reg(dm, R_0xd94, 0x1fff0000);
#endif
#if (defined(PHYDM_COMPILE_ABOVE_4SS))
val[3] = odm_read_4byte(dm, R_0xdcc);
val_1[3] = odm_read_4byte(dm, R_0xdd0);
val_2[3] = odm_get_bb_reg(dm, R_0xdd4, 0x1fff0000);
#endif
for (i = 0; i < dm->num_rf_path; i++) {
val_tmp = val[i] & 0xfff; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[i] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = val[i] >> 16; /*@ Long CFO, S(13,12)*/
cfo->cfo_rpt_l[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val_1[i] & 0x7ff; /*@ SCFO, S(11,10)*/
cfo->cfo_rpt_sec[i] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
val_tmp = val_1[i] >> 16; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_acq[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val_2[i]; /*@ End CFO, S(13,12)*/
cfo->cfo_rpt_end[i] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
}
}
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
void phydm_get_cfo_info_n(void *dm_void, struct phydm_cfo_rpt *cfo)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 val[5] = {0};
u32 val_tmp = 0;
odm_set_bb_reg(dm, R_0xd00, BIT(26), 1);
val[0] = odm_read_4byte(dm, R_0xdac); /*@ Short CFO*/
val[1] = odm_read_4byte(dm, R_0xdb0); /*@ Long CFO*/
val[2] = odm_read_4byte(dm, R_0xdb8); /*@ Sec CFO*/
val[3] = odm_read_4byte(dm, R_0xde0); /*@ Acq CFO*/
val[4] = odm_read_4byte(dm, R_0xdbc); /*@ End CFO*/
/*@[path-A]*/
if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[1] & 0x0fff0000) >> 16; /*@ Long CFO, S(12,11)*/
cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[2] & 0x0fff0000) >> 16; /*@ Sec CFO, S(12,11)*/
cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[3] & 0x0fff0000) >> 16; /*@ Acq CFO, S(12,11)*/
cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[4] & 0x0fff0000) >> 16; /*@ Acq CFO, S(12,11)*/
cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
} else {
val_tmp = (val[0] & 0x0fff0000) >> 16; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[0] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = (val[1] & 0x1fff0000) >> 16; /*@ Long CFO, S(13,12)*/
cfo->cfo_rpt_l[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = (val[2] & 0x7ff0000) >> 16; /*@ Sec CFO, S(11,10)*/
cfo->cfo_rpt_sec[0] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
val_tmp = (val[3] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_acq[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = (val[4] & 0x1fff0000) >> 16; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_end[0] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
}
#if (defined(PHYDM_COMPILE_ABOVE_2SS))
/*@[path-B]*/
val_tmp = val[0] & 0xfff; /*@ Short CFO, S(12,11)*/
cfo->cfo_rpt_s[1] = phydm_get_cfo_hz(dm, val_tmp, 12, 11);
val_tmp = val[1] & 0x1fff; /*@ Long CFO, S(13,12)*/
cfo->cfo_rpt_l[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val[2] & 0x7ff; /*@ Sec CFO, S(11,10)*/
cfo->cfo_rpt_sec[1] = phydm_get_cfo_hz(dm, val_tmp, 11, 10);
val_tmp = val[3] & 0x1fff; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_acq[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
val_tmp = val[4] & 0x1fff; /*@ Acq CFO, S(13,12)*/
cfo->cfo_rpt_end[1] = phydm_get_cfo_hz(dm, val_tmp, 13, 12);
#endif
}
void phydm_set_atc_status(void *dm_void, boolean atc_status)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
u32 reg_tmp = 0;
u32 mask_tmp = 0;
PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]ATC_en=%d\n", __func__, atc_status);
if (cfo_track->is_atc_status == atc_status)
return;
reg_tmp = ODM_REG(BB_ATC, dm);
mask_tmp = ODM_BIT(BB_ATC, dm);
odm_set_bb_reg(dm, reg_tmp, mask_tmp, atc_status);
cfo_track->is_atc_status = atc_status;
}
boolean
phydm_get_atc_status(void *dm_void)
{
boolean atc_status = false;
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 reg_tmp = 0;
u32 mask_tmp = 0;
reg_tmp = ODM_REG(BB_ATC, dm);
mask_tmp = ODM_BIT(BB_ATC, dm);
atc_status = (boolean)odm_get_bb_reg(dm, reg_tmp, mask_tmp);
PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]atc_status=%d\n", __func__, atc_status);
return atc_status;
}
#endif
void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
switch (dm->ic_ip_series) {
#if (ODM_IC_11N_SERIES_SUPPORT)
case PHYDM_IC_N:
phydm_get_cfo_info_n(dm, cfo);
break;
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT)
case PHYDM_IC_AC:
phydm_get_cfo_info_ac(dm, cfo);
break;
#endif
default:
break;
}
}
boolean
phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
u32 reg_val = 0;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8721D | ODM_RTL8710C|ODM_RTL8723F)) {
crystal_cap &= 0x7F;
reg_val = crystal_cap | (crystal_cap << 7);
} else {
crystal_cap &= 0x3F;
reg_val = crystal_cap | (crystal_cap << 6);
}
cfo_track->crystal_cap = crystal_cap;
if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) {
#if (RTL8188E_SUPPORT || RTL8188F_SUPPORT)
/* write 0x24[22:17] = 0x24[16:11] = crystal_cap */
odm_set_mac_reg(dm, R_0x24, 0x7ff800, reg_val);
#endif
}
#if (RTL8812A_SUPPORT)
else if (dm->support_ic_type & ODM_RTL8812) {
/* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */
odm_set_mac_reg(dm, R_0x2c, 0x7FF80000, reg_val);
}
#endif
#if (RTL8703B_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
RTL8821A_SUPPORT || RTL8723D_SUPPORT)
else if ((dm->support_ic_type &
(ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 |
ODM_RTL8723D))) {
/* @0x2C[23:18] = 0x2C[17:12] = crystal_cap */
odm_set_mac_reg(dm, R_0x2c, 0x00FFF000, reg_val);
}
#endif
#if (RTL8814A_SUPPORT)
else if (dm->support_ic_type & ODM_RTL8814A) {
/* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */
odm_set_mac_reg(dm, R_0x2c, 0x07FF8000, reg_val);
}
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT || RTL8197G_SUPPORT || RTL8198F_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C |
ODM_RTL8197F | ODM_RTL8192F | ODM_RTL8197G | ODM_RTL8198F)) {
/* write 0x24[30:25] = 0x28[6:1] = crystal_cap */
odm_set_mac_reg(dm, R_0x24, 0x7e000000, crystal_cap);
odm_set_mac_reg(dm, R_0x28, 0x7e, crystal_cap);
}
#endif
#if (RTL8710B_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8710B)) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
/* write 0x60[29:24] = 0x60[23:18] = crystal_cap */
HAL_SetSYSOnReg(dm->adapter, R_0x60, 0x3FFC0000, reg_val);
#endif
}
#endif
#if (RTL8195B_SUPPORT)
else if (dm->support_ic_type & ODM_RTL8195B) {
phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
}
#endif
#if (RTL8721D_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8721D)) {
/* write 0x4800_0228[30:24] crystal_cap */
/*HAL_SetSYSOnReg(dm->adapter, */
/*REG_SYS_XTAL_8721d, 0x7F000000, crystal_cap);*/
u32 temp_val = HAL_READ32(SYSTEM_CTRL_BASE_LP,
REG_SYS_EFUSE_SYSCFG2);
temp_val = ((crystal_cap << 24) & 0x7F000000)
| (temp_val & (~0x7F000000));
HAL_WRITE32(SYSTEM_CTRL_BASE_LP, REG_SYS_EFUSE_SYSCFG2,
temp_val);
}
#endif
#if (RTL8710C_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8710C)) {
/* write MAC reg 0x28[13:7][6:0] crystal_cap */
phydm_set_crystalcap(dm, (u8)(reg_val & 0x7f));
}
#endif
#if (RTL8723F_SUPPORT)
else if (dm->support_ic_type & ODM_RTL8723F) {
/* write 0x103c[23:17] = 0x103c[16:10] = crystal_cap */
odm_set_mac_reg(dm, R_0x103c, 0x00FFFC00, reg_val);
}
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
else if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8812F)) {
/* write 0x1040[23:17] = 0x1040[16:10] = crystal_cap */
odm_set_mac_reg(dm, R_0x1040, 0x00FFFC00, reg_val);
} else {
return false;
}
#endif
return true;
}
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
if (cfo_track->crystal_cap == crystal_cap)
return;
if (phydm_set_crystal_cap_reg(dm, crystal_cap))
PHYDM_DBG(dm, DBG_CFO_TRK, "Set crystal_cap = 0x%x\n",
cfo_track->crystal_cap);
else
PHYDM_DBG(dm, DBG_CFO_TRK, "Set fail\n");
}
void phydm_cfo_tracking_reset(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F))
cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x7f;
else
cfo_track->def_x_cap = cfo_track->crystal_cap_default & 0x3f;
cfo_track->is_adjust = true;
if (cfo_track->crystal_cap > cfo_track->def_x_cap) {
phydm_set_crystal_cap(dm, cfo_track->crystal_cap - 1);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to Init-val (0x%x)\n",
cfo_track->crystal_cap);
} else if (cfo_track->crystal_cap < cfo_track->def_x_cap) {
phydm_set_crystal_cap(dm, cfo_track->crystal_cap + 1);
PHYDM_DBG(dm, DBG_CFO_TRK, "approch to init-val 0x%x\n",
cfo_track->crystal_cap);
}
#if ODM_IC_11N_SERIES_SUPPORT
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (dm->support_ic_type & ODM_IC_11N_SERIES)
phydm_set_atc_status(dm, true);
#endif
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
if (dm->support_ic_type & ODM_RTL8814B) {
/*Disable advance time for CFO residual*/
odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
}
#endif
#endif
}
void phydm_cfo_tracking_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
PHYDM_DBG(dm, DBG_CFO_TRK, "[%s]=========>\n", __func__);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B | ODM_RTL8195B |
ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F))
cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x7f;
else
cfo_track->crystal_cap = cfo_track->crystal_cap_default & 0x3f;
cfo_track->def_x_cap = cfo_track->crystal_cap;
cfo_track->is_adjust = true;
PHYDM_DBG(dm, DBG_CFO_TRK, "crystal_cap=0x%x\n", cfo_track->def_x_cap);
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
/* @Crystal cap. control by WiFi */
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C))
odm_set_mac_reg(dm, R_0x10, 0x40, 0x1);
#endif
}
void phydm_cfo_tracking(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
s32 cfo_avg = 0, cfo_path_sum = 0, cfo_abs = 0;
u32 cfo_rpt_sum = 0, cfo_khz_avg[4] = {0};
s8 crystal_cap = cfo_track->crystal_cap;
u8 i = 0, valid_path_cnt = 0;
if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
return;
PHYDM_DBG(dm, DBG_CFO_TRK, "%s ======>\n", __func__);
if (!dm->is_linked || !dm->is_one_entry_only) {
phydm_cfo_tracking_reset(dm);
PHYDM_DBG(dm, DBG_CFO_TRK, "is_linked=%d, one_entry_only=%d\n",
dm->is_linked, dm->is_one_entry_only);
} else {
/* No new packet */
if (cfo_track->packet_count == cfo_track->packet_count_pre) {
PHYDM_DBG(dm, DBG_CFO_TRK, "Pkt cnt doesn't change\n");
return;
}
cfo_track->packet_count_pre = cfo_track->packet_count;
/*@Calculate CFO */
for (i = 0; i < dm->num_rf_path; i++) {
if (!(dm->rx_ant_status & BIT(i)))
continue;
valid_path_cnt++;
if (cfo_track->CFO_tail[i] < 0)
cfo_abs = 0 - cfo_track->CFO_tail[i];
else
cfo_abs = cfo_track->CFO_tail[i];
cfo_rpt_sum = (u32)CFO_HW_RPT_2_KHZ(cfo_abs);
cfo_khz_avg[i] = PHYDM_DIV(cfo_rpt_sum,
cfo_track->CFO_cnt[i]);
PHYDM_DBG(dm, DBG_CFO_TRK,
"[Path-%d] CFO_sum=((%d)), cnt=((%d)), CFO_avg=((%s%d))kHz\n",
i, cfo_rpt_sum, cfo_track->CFO_cnt[i],
((cfo_track->CFO_tail[i] < 0) ? "-" : " "),
cfo_khz_avg[i]);
if (cfo_track->CFO_tail[i] < 0)
cfo_path_sum += (0 - (s32)cfo_khz_avg[i]);
else
cfo_path_sum += (s32)cfo_khz_avg[i];
}
if (valid_path_cnt >= 2)
cfo_avg = cfo_path_sum / valid_path_cnt;
else
cfo_avg = cfo_path_sum;
cfo_track->CFO_ave_pre = cfo_avg;
PHYDM_DBG(dm, DBG_CFO_TRK, "path_cnt=%d, CFO_avg_path=%d kHz\n",
valid_path_cnt, cfo_avg);
/*reset counter*/
for (i = 0; i < dm->num_rf_path; i++) {
cfo_track->CFO_tail[i] = 0;
cfo_track->CFO_cnt[i] = 0;
}
/* To adjust crystal cap or not */
if (!cfo_track->is_adjust) {
if (cfo_avg > CFO_TRK_ENABLE_TH ||
cfo_avg < (-CFO_TRK_ENABLE_TH))
cfo_track->is_adjust = true;
} else {
if (cfo_avg <= CFO_TRK_STOP_TH &&
cfo_avg >= (-CFO_TRK_STOP_TH))
cfo_track->is_adjust = false;
}
#ifdef ODM_CONFIG_BT_COEXIST
/*@BT case: Disable CFO tracking */
if (dm->bt_info_table.is_bt_enabled) {
cfo_track->is_adjust = false;
phydm_set_crystal_cap(dm, cfo_track->def_x_cap);
PHYDM_DBG(dm, DBG_CFO_TRK, "[BT]Disable CFO_track\n");
}
#endif
/*@Adjust Crystal Cap. */
if (cfo_track->is_adjust) {
if (cfo_avg > CFO_TRK_STOP_TH)
crystal_cap += 1;
else if (cfo_avg < (-CFO_TRK_STOP_TH))
crystal_cap -= 1;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8814B |
ODM_RTL8195B | ODM_RTL8812F | ODM_RTL8710C | ODM_RTL8721D | ODM_RTL8723F)) {
if (crystal_cap > 0x7F)
crystal_cap = 0x7F;
} else {
if (crystal_cap > 0x3F)
crystal_cap = 0x3F;
}
if (crystal_cap < 0)
crystal_cap = 0;
phydm_set_crystal_cap(dm, (u8)crystal_cap);
}
PHYDM_DBG(dm, DBG_CFO_TRK, "X_cap{Curr,Default}={0x%x,0x%x}\n",
cfo_track->crystal_cap, cfo_track->def_x_cap);
/* @Dynamic ATC switch */
#if ODM_IC_11N_SERIES_SUPPORT
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (cfo_avg < CFO_TH_ATC && cfo_avg > -CFO_TH_ATC)
phydm_set_atc_status(dm, false);
else
phydm_set_atc_status(dm, true);
}
#endif
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_AP))
if (dm->support_ic_type & ODM_RTL8814B) {
//Disable advance time for CFO residual
odm_set_bb_reg(dm, R_0xc2c, BIT29, 0x0);
}
#endif
#endif
}
}
void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
u8 num_ss)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_perpkt_info_struct *pktinfo = NULL;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
boolean valid_info = false;
u8 i = 0;
if (!(dm->support_ability & ODM_BB_CFO_TRACKING))
return;
pktinfo = (struct phydm_perpkt_info_struct *)pktinfo_void;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE | ODM_IOT))
if (pktinfo->is_packet_match_bssid)
valid_info = true;
#else
if (dm->number_active_client == 1)
valid_info = true;
#endif
if (valid_info) {
if (num_ss > dm->num_rf_path) /*@For fool proof*/
num_ss = dm->num_rf_path;
#if 0
PHYDM_DBG(dm, DBG_CFO_TRK, "num_ss=%d, num_rf_path=%d\n",
num_ss, dm->num_rf_path);
#endif
/* @ Update CFO report for path-A & path-B */
/* Only paht-A and path-B have CFO tail and short CFO */
for (i = 0; i < dm->num_rf_path; i++) {
if (!(dm->rx_ant_status & BIT(i)))
continue;
cfo_track->CFO_tail[i] += pcfotail[i];
cfo_track->CFO_cnt[i]++;
#if 0
PHYDM_DBG(dm, DBG_CFO_TRK,
"[ID %d][path %d][rate 0x%x] CFO_tail = ((%d)), CFO_tail_sum = ((%d)), CFO_cnt = ((%d))\n",
pktinfo->station_id, i, pktinfo->data_rate,
pcfotail[i], cfo_track->CFO_tail[i],
cfo_track->CFO_cnt[i]);
#endif
}
/* @ Update packet counter */
if (cfo_track->packet_count == 0xffffffff)
cfo_track->packet_count = 0;
else
cfo_track->packet_count++;
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!phydm_set_crystal_cap_reg(dm, crystal_cap))
RT_TRACE_F(COMP_INIT, DBG_SERIOUS,
("Crystal is not initialized!\n"));
}
#endif
void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_cfo_track_struct *cfo_track = &dm->dm_cfo_track;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"set Xcap: {1}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"show Xcap: {100}\n");
} else {
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
phydm_set_crystal_cap(dm, (u8)var1[1]);
PDM_SNPF(out_len, used, output + used, out_len - used,
"Set X_cap=0x%x\n", cfo_track->crystal_cap);
} else if (var1[0] == 100) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"X_cap=0x%x\n", cfo_track->crystal_cap);
}
}
*_used = used;
*_out_len = out_len;
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
/* 2019.03.28 fix 8197G crystal_cap register address*/
#define CFO_TRACKING_VERSION "2.4"
#define CFO_TRK_ENABLE_TH 20 /* @kHz enable CFO_Track threshold*/
#define CFO_TRK_STOP_TH 10 /* @kHz disable CFO_Track threshold*/
#define CFO_TH_ATC 80 /* @kHz */
struct phydm_cfo_track_struct {
boolean is_atc_status;
boolean is_adjust; /*@already modify crystal cap*/
u8 crystal_cap;
u8 crystal_cap_default;
u8 def_x_cap;
s32 CFO_tail[4];
u32 CFO_cnt[4];
s32 CFO_ave_pre;
u32 packet_count;
u32 packet_count_pre;
};
struct phydm_cfo_rpt {
s32 cfo_rpt_s[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_l[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_acq[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_sec[PHYDM_MAX_RF_PATH];
s32 cfo_rpt_end[PHYDM_MAX_RF_PATH];
};
void phydm_get_cfo_info(void *dm_void, struct phydm_cfo_rpt *cfo);
boolean phydm_set_crystal_cap_reg(void *dm_void, u8 crystal_cap);
void phydm_set_crystal_cap(void *dm_void, u8 crystal_cap);
void phydm_cfo_tracking_init(void *dm_void);
void phydm_cfo_tracking(void *dm_void);
void phydm_parsing_cfo(void *dm_void, void *pktinfo_void, s8 *pcfotail,
u8 num_ss);
void phydm_cfo_tracking_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phy_Init_crystal_capacity(void *dm_void, u8 crystal_cap);
#endif
#endif

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484
hal/phydm/phydm_debug.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
/*#define DEBUG_VERSION "1.3"*/ /*2016.04.28 YuChen*/
/*#define DEBUG_VERSION "1.4"*/ /*2017.03.13 Dino*/
/*#define DEBUG_VERSION "2.0"*/ /*2018.01.10 Dino*/
/*2020.07.03 fix cck report bug due to 8723F coding error*/
#define DEBUG_VERSION "4.6"
/*@
* ============================================================
* Definition
* ============================================================
*/
/*@FW DBG MSG*/
#define RATE_DECISION 1
#define INIT_RA_TABLE 2
#define RATE_UP 4
#define RATE_DOWN 8
#define TRY_DONE 16
#define RA_H2C 32
#define F_RATE_AP_RPT 64
#define DBC_FW_CLM 9
#define PHYDM_SNPRINT_SIZE 64
/* @----------------------------------------------------------------------------
* Define the tracing components
*
* -----------------------------------------------------------------------------
* BB FW Functions
*/
#define PHYDM_FW_COMP_RA BIT(0)
#define PHYDM_FW_COMP_MU BIT(1)
#define PHYDM_FW_COMP_PATH_DIV BIT(2)
#define PHYDM_FW_COMP_PT BIT(3)
/*@------------------------Export Marco Definition---------------------------*/
#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (DBG_CMD_SUPPORT == 1)
extern VOID DCMD_Printf(const char *pMsg);
#else
#define DCMD_Printf(_pMsg)
#endif
#if OS_WIN_FROM_WIN10(OS_VERSION)
#define pr_debug(fmt, ...) DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, fmt, ##__VA_ARGS__)
#else
#define pr_debug DbgPrint
#endif
#define dcmd_printf DCMD_Printf
#define dcmd_scanf DCMD_Scanf
#define RT_PRINTK pr_debug
#define PRINT_MAX_SIZE 512
#define PHYDM_SNPRINTF RT_SPRINTF
#define PHYDM_TRACE(_MSG_) EXhalPHYDMoutsrc_Print(_MSG_)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#define PHYDM_SNPRINTF snprintf
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#undef pr_debug
#define pr_debug printk
#define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args)
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_TRACE(adapter, comp, drv_level, fmt, args...) \
RTW_INFO(fmt, ## args)
#define PHYDM_SNPRINTF snprintf
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define pr_debug(fmt, args...) RTW_PRINT_MSG(fmt, ## args)
#define RT_DEBUG(comp, drv_level, fmt, args...) \
RTW_PRINT_MSG(fmt, ## args)
#define PHYDM_SNPRINTF snprintf
#else
#define pr_debug panic_printk
/*@#define RT_PRINTK(fmt, args...) pr_debug("%s(): " fmt, __FUNCTION__, ## args);*/
#define RT_PRINTK(fmt, args...) pr_debug(fmt, ## args)
#define PHYDM_SNPRINTF snprintf
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
pr_debug("[PHYDM] "); \
RT_PRINTK(fmt, ## args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_PRINTK(fmt, ## args); \
} \
} while (0)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
if ((comp) & dm->debug_components) { \
int __i; \
u8 *__ptr = (u8 *)addr; \
pr_debug("[PHYDM] "); \
pr_debug(title_str); \
pr_debug(" "); \
for (__i = 0; __i < 6; __i++) \
pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\
pr_debug("\n"); \
} \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void PHYDM_DBG(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->debug_components) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
return;
}
#if OS_WIN_FROM_WIN10(OS_VERSION)
DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
#else
DbgPrint("%s", buf);
#endif
}
static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->debug_components) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
/*@DbgPrint("DM Print Fail\n");*/
return;
}
#if OS_WIN_FROM_WIN10(OS_VERSION)
DbgPrintEx(DPFLTR_IHVNETWORK_ID, DPFLTR_ERROR_LEVEL, "%s", buf);
#else
DbgPrint("%s", buf);
#endif
}
#define PHYDM_PRINT_ADDR(p_dm, comp, title_str, ptr) \
do { \
if ((comp) & p_dm->debug_components) { \
\
int __i; \
u8 *__ptr = (u8 *)ptr; \
pr_debug("[PHYDM] "); \
pr_debug(title_str); \
pr_debug(" "); \
for (__i = 0; __i < 6; __i++) \
pr_debug("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \
pr_debug("\n"); \
} \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_DEBUG(COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " fmt, ##args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
if ((comp) & dm->debug_components) { \
RT_DEBUG(COMP_PHYDM, \
DBG_DMESG, fmt, ##args); \
} \
} while (0)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
if ((comp) & dm->debug_components) { \
RT_DEBUG(COMP_PHYDM, \
DBG_DMESG, "[PHYDM] " title_str "%pM\n", \
addr); \
} \
} while (0)
#elif defined(DM_ODM_CE_MAC80211_V2)
#define PHYDM_DBG(dm, comp, fmt, args...)
#define PHYDM_DBG_F(dm, comp, fmt, args...)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr)
#else
#define PHYDM_DBG(dm, comp, fmt, args...) \
do { \
struct dm_struct *__dm = (dm); \
if ((comp) & __dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter),\
COMP_PHYDM, DBG_DMESG, \
"[PHYDM] " fmt, ##args); \
} \
} while (0)
#define PHYDM_DBG_F(dm, comp, fmt, args...) \
do { \
struct dm_struct *__dm = (dm); \
if ((comp) & __dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter),\
COMP_PHYDM, DBG_DMESG, fmt, ##args); \
} \
} while (0)
#define PHYDM_PRINT_ADDR(dm, comp, title_str, addr) \
do { \
struct dm_struct *__dm = (dm); \
if ((comp) & __dm->debug_components) { \
RT_TRACE(((struct rtl_priv *)__dm->adapter),\
COMP_PHYDM, DBG_DMESG, \
"[PHYDM] " title_str "%pM\n", addr);\
} \
} while (0)
#endif
#else /*@#if DBG*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if ((comp & dm->debug_components) == 0)
return;
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
DbgPrint("Failed (%d) to print message to buffer\n", rt_status);
return;
}
PHYDM_TRACE(buf);
}
static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
{
}
#else
#define PHYDM_DBG(dm, comp, fmt, args...)
#define PHYDM_DBG_F(dm, comp, fmt, args...)
#endif
#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)
#endif
#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/
#define DBGPORT_PRI_2 2 /*@Check hang function & Strong function*/
#define DBGPORT_PRI_1 1 /*Watch dog function*/
#define DBGPORT_RELEASE 0 /*@Init value (the lowest priority)*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define PHYDM_DBGPRINT 0
#define PHYDM_SSCANF(x, y, z) dcmd_scanf(x, y, z)
#define PDM_VAST_SNPF PDM_SNPF
#if (PHYDM_DBGPRINT == 1)
#define PDM_SNPF(msg) \
do {\
rsprintf msg;\
pr_debug("%s", output);\
} while (0)
#else
static __inline void PDM_SNPF(u32 out_len, u32 used, char *buff, int len,
char *fmt, ...)
{
RT_STATUS rt_status;
va_list args;
char buf[PRINT_MAX_SIZE] = {0};
if (fmt == NULL)
return;
va_start(args, fmt);
rt_status = (RT_STATUS)RtlStringCbVPrintfA(buf, PRINT_MAX_SIZE, fmt, args);
va_end(args);
if (rt_status != RT_STATUS_SUCCESS) {
/*@DbgPrint("DM Print Fail\n");*/
return;
}
DCMD_Printf(buf);
}
#endif /*@#if (PHYDM_DBGPRINT == 1)*/
#else /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) || defined(__OSK__)
#define PHYDM_DBGPRINT 0
#else
#define PHYDM_DBGPRINT 1
#endif
#define MAX_ARGC 20
#define MAX_ARGV 16
#define DCMD_DECIMAL "%d"
#define DCMD_CHAR "%c"
#define DCMD_HEX "%x"
#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) RT_PRINTK(fmt, ## args)
#elif (DM_ODM_SUPPORT_TYPE & ODM_IOT)
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \
do { \
RT_DEBUG(COMP_PHYDM, DBG_DMESG, fmt, ##args); \
} while (0)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...)
#else
#define PDM_VAST_SNPF(out_len, used, buff, len, fmt, args...) \
RT_TRACE(((struct rtl_priv *)dm->adapter), COMP_PHYDM, \
DBG_DMESG, fmt, ##args)
#endif
#if (PHYDM_DBGPRINT == 1)
#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \
do { \
snprintf(buff, len, fmt, ##args); \
pr_debug("%s", output); \
} while (0)
#else
#define PDM_SNPF(out_len, used, buff, len, fmt, args...) \
do { \
u32 *__pdm_snpf_u = &(used); \
if (out_len > *__pdm_snpf_u) \
*__pdm_snpf_u += snprintf(buff, len, fmt, ##args);\
} while (0)
#endif
#endif
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum auto_detection_state { /*@Fast antenna training*/
AD_LEGACY_MODE = 0,
AD_HT_MODE = 1,
AD_VHT_MODE = 2
};
/*@
* ============================================================
* 1 structure
* ============================================================
*/
#ifdef CONFIG_PHYDM_DEBUG_FUNCTION
u8 phydm_get_l_sig_rate(void *dm_void, u8 rate_idx_l_sig);
#endif
void phydm_init_debug_setting(struct dm_struct *dm);
void phydm_bb_dbg_port_header_sel(void *dm_void, u32 header_idx);
u32 phydm_get_bb_dbg_port_idx(void *dm_void);
u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
void phydm_release_bb_dbg_port(void *dm_void);
u32 phydm_get_bb_dbg_port_val(void *dm_void);
void phydm_reset_rx_rate_distribution(struct dm_struct *dm);
void phydm_rx_rate_distribution(void *dm_void);
u16 phydm_rx_avg_phy_rate(void *dm_void);
void phydm_show_phy_hitogram(void *dm_void);
void phydm_get_avg_phystatus_val(void *dm_void);
void phydm_get_phy_statistic(void *dm_void);
void phydm_dm_summary(void *dm_void, u8 macid);
void phydm_basic_dbg_message(void *dm_void);
void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
u32 *_out_len);
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))
s32 phydm_cmd(struct dm_struct *dm, char *input, u32 in_len, u8 flag,
char *output, u32 out_len);
#endif
void phydm_cmd_parser(struct dm_struct *dm, char input[][16], u32 input_num,
u8 flag, char *output, u32 out_len);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_basic_dbg_msg_cli_win(void *dm_void, char *buf);
void phydm_sbd_check(
struct dm_struct *dm);
void phydm_sbd_callback(
struct phydm_timer_list *timer);
void phydm_sbd_workitem_callback(
void *context);
#endif
void phydm_fw_trace_en_h2c(void *dm_void, boolean enable,
u32 fw_debug_component, u32 monitor_mode, u32 macid);
void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
#endif /* @__ODM_DBG_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_DFS_H__
#define __PHYDM_DFS_H__
#define DFS_VERSION "1.1"
/*@
* ============================================================
* Definition
* ============================================================
*/
/*@
* ============================================================
* 1 structure
* ============================================================
*/
struct _DFS_STATISTICS {
u8 mask_idx;
u8 igi_cur;
u8 igi_pre;
u8 st_l2h_cur;
u16 fa_count_pre;
u16 fa_inc_hist[5];
u16 short_pulse_cnt_pre;
u16 long_pulse_cnt_pre;
u8 pwdb_th;
u8 pwdb_th_cur;
u8 pwdb_scalar_factor;
u8 peak_th;
u8 short_pulse_cnt_th;
u8 long_pulse_cnt_th;
u8 peak_window;
u8 three_peak_opt;
u8 three_peak_th2;
u8 fa_mask_th;
u8 st_l2h_max;
u8 st_l2h_min;
u8 dfs_polling_time;
u8 mask_hist_checked : 3;
boolean pulse_flag_hist[5];
boolean pulse_type_hist[5];
boolean radar_det_mask_hist[5];
boolean idle_mode;
boolean force_TP_mode;
boolean dbg_mode;
boolean sw_trigger_mode;
boolean det_print;
boolean det_print2;
boolean radar_type;
boolean print_hist_rpt;
boolean hist_cond_on;
/*@dfs histogram*/
boolean pri_cond1;
boolean pri_cond2;
boolean pri_cond3;
boolean pri_cond4;
boolean pri_cond5;
boolean pw_cond1;
boolean pw_cond2;
boolean pw_cond3;
boolean pri_type3_4_cond1; /*@for ETSI*/
boolean pri_type3_4_cond2; /*@for ETSI*/
boolean pw_long_cond1; /*@for long radar*/
boolean pw_long_cond2; /*@for long radar*/
boolean pri_long_cond1; /*@for long radar*/
boolean pw_flag;
boolean pri_flag;
boolean pri_type3_4_flag; /*@for ETSI*/
boolean long_radar_flag;
u8 pri_hold_sum[6];
u8 pw_hold_sum[6];
u8 pri_long_hold_sum[6];
u8 pw_long_hold_sum[6];
u8 hist_idx;
u8 hist_long_idx;
u8 pw_hold[4][6];
u8 pri_hold[4][6];
u8 pw_std; /*@The std(var) of reasonable num of pw group*/
u8 pri_std;/*@The std(var) of reasonable num of pri group*/
/*@dfs histogram threshold*/
u8 pri_hist_th : 3;
u8 pri_sum_g1_th : 4;
u8 pri_sum_g5_th : 4;
u8 pri_sum_g1_fcc_th : 3;
u8 pri_sum_g3_fcc_th : 3;
u8 pri_sum_safe_fcc_th : 7;
u8 pri_sum_type4_th : 5;
u8 pri_sum_type6_th : 5;
u8 pri_sum_safe_th : 6;
u8 pri_sum_g5_under_g1_th : 3;
u8 pri_pw_diff_th : 3;
u8 pri_pw_diff_fcc_th : 4;
u8 pri_pw_diff_fcc_idle_th : 2;
u8 pri_pw_diff_w53_th : 4;
u8 pri_type1_low_fcc_th : 7;
u8 pri_type1_upp_fcc_th : 7;
u8 pri_type1_cen_fcc_th : 7;
u8 pw_g0_th : 4;
u8 pw_long_lower_20m_th : 4;
u8 pw_long_lower_th : 3;
u8 pri_long_upper_th : 6;
u8 pw_long_sum_upper_th : 7;
u8 pw_std_th : 4;
u8 pw_std_idle_th : 4;
u8 pri_std_th : 4;
u8 pri_std_idle_th : 4;
u8 type4_pw_max_cnt : 4;
u8 type4_safe_pri_sum_th : 3;
};
/*@
* ============================================================
* enumeration
* ============================================================
*/
enum phydm_dfs_region_domain {
PHYDM_DFS_DOMAIN_UNKNOWN = 0,
PHYDM_DFS_DOMAIN_FCC = 1,
PHYDM_DFS_DOMAIN_MKK = 2,
PHYDM_DFS_DOMAIN_ETSI = 3,
};
/*@
* ============================================================
* function prototype
* ============================================================
*/
#if defined(CONFIG_PHYDM_DFS_MASTER)
void phydm_radar_detect_reset(void *dm_void);
void phydm_radar_detect_disable(void *dm_void);
void phydm_radar_detect_enable(void *dm_void);
boolean phydm_radar_detect(void *dm_void);
void phydm_dfs_histogram_radar_distinguish(void *dm_void);
boolean phydm_dfs_hist_log(void *dm_void, u8 index);
void phydm_dfs_parameter_init(void *dm_void);
void phydm_dfs_hist_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_dfs_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
u8 phydm_dfs_polling_time(void *dm_void);
#endif /* @defined(CONFIG_PHYDM_DFS_MASTER) */
boolean
phydm_dfs_is_meteorology_channel(void *dm_void);
void
phydm_dfs_segment_distinguish(void *dm_void, enum rf_syn syn_path);
void
phydm_dfs_segment_flag_reset(void *dm_void);
boolean
phydm_is_dfs_band(void *dm_void);
boolean
phydm_dfs_master_enabled(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_dfs_ap_reset_radar_detect_counter_and_flag(void *dm_void);
#endif
#endif
#endif /*@#ifndef __PHYDM_DFS_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
/* 2020.08.13 Add IFS-CLM/FAHM in dig fa source for more accurate fa info*/
#define DIG_VERSION "3.9"
#define DIG_HW 0
#define DIG_LIMIT_PERIOD 60 /*60 sec*/
/*@--------------------Define ---------------------------------------*/
/*@=== [DIG Boundary] ========================================*/
/*@DIG coverage mode*/
#define DIG_MAX_COVERAGR 0x26
#define DIG_MIN_COVERAGE 0x1c
#define DIG_MAX_OF_MIN_COVERAGE 0x22
/*@[DIG Balance mode]*/
#if (DIG_HW == 1)
#define DIG_MAX_BALANCE_MODE 0x32
#else
#define DIG_MAX_BALANCE_MODE 0x3e
#endif
#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a
/*@[DIG Performance mode]*/
#define DIG_MAX_PERFORMANCE_MODE 0x5a
#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*@[WLANBB-871]*/
#define DIG_MIN_PERFORMANCE 0x20
/*@DIG DFS function*/
#define DIG_MAX_DFS 0x28
#define DIG_MIN_DFS 0x20
/*@DIG LPS function*/
#define DIG_MAX_LPS 0x3e
#define DIG_MIN_LPS 0x20
#ifdef PHYDM_TDMA_DIG_SUPPORT
#define DIG_NUM_OF_TDMA_STATES 2 /*@L, H state*/
#define DIG_TIMER_MS 250
#define ONE_SEC_MS 1000
#endif
/*@=== [DIG FA Threshold] ======================================*/
/*Normal*/
#define DM_DIG_FA_TH0 500
#define DM_DIG_FA_TH1 750
/*@LPS*/
#define DM_DIG_FA_TH0_LPS 4 /* @-> 4 lps */
#define DM_DIG_FA_TH1_LPS 15 /* @-> 15 lps */
#define DM_DIG_FA_TH2_LPS 30 /* @-> 30 lps */
#define RSSI_OFFSET_DIG_LPS 5
#define DIG_RECORD_NUM 4
/*==== [FA duration] =======================================*/
/*[PHYDM-406]*/
#define OFDM_FA_EXP_DURATION 12 /*us*/
#define CCK_FA_EXP_DURATION 175 /*us*/
/*@--------------------Enum-----------------------------------*/
enum phydm_dig_mode {
PHYDM_DIG_PERFORAMNCE_MODE = 0,
PHYDM_DIG_COVERAGE_MODE = 1,
};
enum phydm_dig_trend {
DIG_STABLE = 0,
DIG_INCREASING = 1,
DIG_DECREASING = 2
};
enum phydm_fw_dig_mode_e {
DIG_PERFORMANCE_MODE = 0,
DIG_COVERAGE_MODE = 1,
DIG_LPS_MODE = 2
};
#ifdef PHYDM_TDMA_DIG_SUPPORT
enum upd_type {
ENABLE_TDMA,
MODE_DECISION
};
enum tdma_opmode {
MODE_PERFORMANCE = 1,
MODE_COVERAGE = 2
};
#ifdef IS_USE_NEW_TDMA
enum tdma_dig_timer {
INIT_TDMA_DIG_TIMMER,
CANCEL_TDMA_DIG_TIMMER,
RELEASE_TDMA_DIG_TIMMER
};
enum tdma_dig_state {
TDMA_DIG_LOW_STATE = 0,
TDMA_DIG_HIGH_STATE = 1,
NORMAL_DIG = 2
};
#endif
#endif
/*@--------------------Define Struct-----------------------------------*/
#ifdef CFG_DIG_DAMPING_CHK
struct phydm_dig_recorder_strcut {
u8 igi_bitmap; /*@Don't add any new parameter before this*/
u8 igi_history[DIG_RECORD_NUM];
u32 fa_history[DIG_RECORD_NUM];
u8 damping_limit_en;
u8 damping_limit_val; /*@Limit IGI_dyn_min*/
u32 limit_time;
u8 limit_rssi;
};
#endif
struct phydm_mcc_dig {
u8 mcc_rssi_A;
u8 mcc_rssi_B;
};
struct phydm_dig_struct {
#ifdef CFG_DIG_DAMPING_CHK
struct phydm_dig_recorder_strcut dig_recorder_t;
u8 dig_dl_en; /*@damping limit function enable*/
#endif
boolean fw_dig_enable;
boolean is_dbg_fa_th;
u8 cur_ig_value;
boolean igi_dyn_up_hit;
u8 igi_trend;
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
u8 igi_backup;
u8 rx_gain_range_max; /*@dig_dynamic_max*/
u8 rx_gain_range_min; /*@dig_dynamic_min*/
u8 dm_dig_max; /*@Absolutly upper bound*/
u8 dm_dig_min; /*@Absolutly lower bound*/
u8 dig_max_of_min; /*@Absolutly max of min*/
u32 ant_div_rssi_max;
u8 *is_p2p_in_process;
u32 fa_th[3];
u32 dm_dig_fa_th1;
u8 fa_source;
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8198F_SUPPORT || RTL8192F_SUPPORT || RTL8195B_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8721D_SUPPORT ||\
RTL8710C_SUPPORT || RTL8812F_SUPPORT || RTL8197G_SUPPORT ||\
RTL8723F_SUPPORT)
u8 rf_gain_idx;
u8 agc_table_idx;
u8 big_jump_lmt[16];
u8 enable_adjust_big_jump:1;
u8 big_jump_step1:3;
u8 big_jump_step2:2;
u8 big_jump_step3:2;
#endif
u8 upcheck_init_val;
u8 lv0_ratio_reciprocal;
u8 lv1_ratio_reciprocal;
#ifdef PHYDM_TDMA_DIG_SUPPORT
u8 cur_ig_value_tdma;
u8 low_ig_value;
u8 tdma_dig_state; /*@To distinguish which state is now.(L-sate or H-state)*/
u8 tdma_dig_cnt; /*@for phydm_tdma_dig_timer_check use*/
u8 pre_tdma_dig_cnt;
u8 sec_factor;
u32 cur_timestamp;
u32 pre_timestamp;
u32 fa_start_timestamp;
u32 fa_end_timestamp;
u32 fa_acc_1sec_timestamp;
#ifdef IS_USE_NEW_TDMA
u8 tdma_dig_block_cnt;/*@for 1 second dump indicator use*/
/*@dynamic upper bound for L/H state*/
u8 tdma_rx_gain_max[DIG_NUM_OF_TDMA_STATES];
/*@dynamic lower bound for L/H state*/
u8 tdma_rx_gain_min[DIG_NUM_OF_TDMA_STATES];
/*To distinguish current state(L-sate or H-state)*/
#endif
u8 tdma_force_l_igi;
u8 tdma_force_h_igi;
#endif
};
struct phydm_fa_struct {
u32 cnt_parity_fail;
u32 cnt_rate_illegal;
u32 cnt_crc8_fail;
u32 cnt_crc8_fail_vhta;
u32 cnt_crc8_fail_vhtb;
u32 cnt_mcs_fail;
u32 cnt_mcs_fail_vht;
u32 cnt_ofdm_fail;
u32 cnt_ofdm_fail_pre; /* @For RTL8881A */
u32 cnt_cck_fail;
u32 cnt_all;
u32 cnt_all_accumulated;
u32 cnt_all_pre;
u32 cnt_fast_fsync;
u32 cnt_sb_search_fail;
u32 cnt_ofdm_cca;
u32 cnt_cck_cca;
u32 cnt_cca_all;
u32 cnt_bw_usc;
u32 cnt_bw_lsc;
u32 cnt_cck_crc32_error;
u32 cnt_cck_crc32_ok;
u32 cnt_ofdm_crc32_error;
u32 cnt_ofdm_crc32_ok;
u32 cnt_ht_crc32_error;
u32 cnt_ht_crc32_ok;
u32 cnt_ht_crc32_error_agg;
u32 cnt_ht_crc32_ok_agg;
u32 cnt_vht_crc32_error;
u32 cnt_vht_crc32_ok;
u32 cnt_crc32_error_all;
u32 cnt_crc32_ok_all;
u32 time_fa_all;
u32 time_fa_exp; /*FA duration, [PHYDM-406]*/
u32 time_fa_ifs_clm; /*FA duration, [PHYDM-406]*/
u32 time_fa_fahm; /*FA duration, [PHYDM-406]*/
boolean cck_block_enable;
boolean ofdm_block_enable;
u32 dbg_port0;
boolean edcca_flag;
u8 ofdm2_rate_idx;
u32 cnt_ofdm2_crc32_error;
u32 cnt_ofdm2_crc32_ok;
u8 ofdm2_pcr;
u8 ht2_rate_idx;
u32 cnt_ht2_crc32_error;
u32 cnt_ht2_crc32_ok;
u8 ht2_pcr;
u8 vht2_rate_idx;
u32 cnt_vht2_crc32_error;
u32 cnt_vht2_crc32_ok;
u8 vht2_pcr;
u32 cnt_cck_txen;
u32 cnt_cck_txon;
u32 cnt_ofdm_txen;
u32 cnt_ofdm_txon;
};
#ifdef PHYDM_TDMA_DIG_SUPPORT
struct phydm_fa_acc_struct {
u32 cnt_parity_fail;
u32 cnt_rate_illegal;
u32 cnt_crc8_fail;
u32 cnt_mcs_fail;
u32 cnt_ofdm_fail;
u32 cnt_ofdm_fail_pre; /*@For RTL8881A*/
u32 cnt_cck_fail;
u32 cnt_all;
u32 cnt_all_pre;
u32 cnt_fast_fsync;
u32 cnt_sb_search_fail;
u32 cnt_ofdm_cca;
u32 cnt_cck_cca;
u32 cnt_cca_all;
u32 cnt_cck_crc32_error;
u32 cnt_cck_crc32_ok;
u32 cnt_ofdm_crc32_error;
u32 cnt_ofdm_crc32_ok;
u32 cnt_ht_crc32_error;
u32 cnt_ht_crc32_ok;
u32 cnt_vht_crc32_error;
u32 cnt_vht_crc32_ok;
u32 cnt_crc32_error_all;
u32 cnt_crc32_ok_all;
u32 cnt_all_1sec;
u32 cnt_cca_all_1sec;
u32 cnt_cck_fail_1sec;
};
#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
/*@--------------------Function declaration-----------------------------*/
void phydm_write_dig_reg(void *dm_void, u8 igi);
void odm_write_dig(void *dm_void, u8 current_igi);
u8 phydm_get_igi(void *dm_void, enum bb_path path);
void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len);
void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
enum phydm_pause_level pause_level, u8 igi_value);
#ifdef PHYDM_HW_IGI
void phydm_hwigi(void *dm_void);
void phydm_hwigi_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
void phydm_dig_init(void *dm_void);
void phydm_dig(void *dm_void);
void phydm_dig_lps_32k(void *dm_void);
void phydm_dig_by_rssi_lps(void *dm_void);
void phydm_get_dig_coverage(void *dm_void, u8 *max, u8 *min);
u8 phydm_get_igi_for_target_pin_scan(void *dm_void, u8 rssi);
void phydm_false_alarm_counter_statistics(void *dm_void);
u32 phydm_get_edcca_report(void * dm_void);
#ifdef PHYDM_TDMA_DIG_SUPPORT
void phydm_set_tdma_dig_timer(void *dm_void);
void phydm_tdma_dig_timer_check(void *dm_void);
void phydm_tdma_dig(void *dm_void);
void phydm_tdma_false_alarm_counter_check(void *dm_void);
void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void);
void phydm_false_alarm_counter_reset(void *dm_void);
void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en);
void phydm_false_alarm_counter_acc_reset(void *dm_void);
void phydm_tdma_dig_para_upd(void *dm_void, enum upd_type type, u8 input);
#ifdef IS_USE_NEW_TDMA
void phydm_tdma_dig_timers(void *dm_void, u8 state);
void phydm_tdma_dig_cbk(void *dm_void);
void phydm_tdma_dig_workitem_callback(void *dm_void);
void phydm_tdma_fa_cnt_chk(void *dm_void);
void phydm_tdma_low_dig(void *dm_void);
void phydm_tdma_high_dig(void *dm_void);
void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
u8 cur_tdma_dig_state);
#endif /*@#ifdef IS_USE_NEW_TDMA*/
#endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
void phydm_set_ofdm_agc_tab(void *dm_void, u8 tab_sel);
void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
void phydm_fill_fw_dig_info(void *dm_void, boolean *enable,
u8 *para4, u8 *para8);
void phydm_crc32_cnt_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#ifdef CONFIG_MCC_DM
void phydm_mcc_igi_cal(void *dm_void);
#endif
#endif

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@ -0,0 +1,366 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
***************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_DIRECTIONAL_BF
#ifdef PHYDM_COMPILE_IC_2SS
void phydm_iq_gen_en(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
enum rf_path i = RF_PATH_A;
enum rf_path path = RF_PATH_A;
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822B) {
for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x1);
/*Select RX mode*/
odm_set_rf_reg(dm, path, RF_0x33, 0xF, 3);
/*Set Table data*/
odm_set_rf_reg(dm, path, RF_0x3e, 0xfffff, 0x00036);
/*Set Table data*/
odm_set_rf_reg(dm, path, RF_0x3f, 0xfffff, 0x5AFCE);
/*RF mode table write disable*/
odm_set_rf_reg(dm, path, RF_0xef, BIT(19), 0x0);
}
}
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_RTL8192F) {
/*RF mode table write enable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
/* Path A */
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x08000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0005f);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x01042);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0004f);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
/* Path B */
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00050);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x00040);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
/*RF mode table write disable*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
}
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_RTL8197G) {
/*RF mode table write enable*/
/* Path A */
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x000cf);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x71fc2);
odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, 0x80000, 0x0);
/* Path B */
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000cf);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x71fc2);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x08000);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x000ef);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x01042);
odm_set_rf_reg(dm, RF_PATH_B, RF_0xef, 0x80000, 0x0);
}
#endif
}
void phydm_dis_cdd(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, R_0x808, 0x3ffff00, 0);
odm_set_bb_reg(dm, R_0x9ac, 0x1fff, 0);
odm_set_bb_reg(dm, R_0x9ac, BIT(13), 1);
}
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
odm_set_bb_reg(dm, R_0x90c, 0xffffffff, 0x83321333);
/* Set Tx delay setting for CCK pathA,B*/
odm_set_bb_reg(dm, R_0xa2c, 0xf0000000, 0);
/*Enable Tx CDD for HT part when spatial expansion is applied*/
odm_set_bb_reg(dm, R_0xd00, BIT(8), 0);
/* Tx CDD for Legacy*/
odm_set_bb_reg(dm, R_0xd04, 0xf0000, 0);
/* Tx CDD for non-HT*/
odm_set_bb_reg(dm, R_0xd0c, 0x3c0, 0);
/* Tx CDD for HT SS1*/
odm_set_bb_reg(dm, R_0xd0c, 0xf8000, 0);
}
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
/* Tx CDD for Legacy Preamble*/
odm_set_bb_reg(dm, R_0x1cc0, 0xffffffff, 0x24800000);
/* Tx CDD for HT Preamble*/
odm_set_bb_reg(dm, R_0x1cb0, 0xffffffff, 0);
}
#endif
}
void phydm_pathb_q_matrix_rotate_en(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phydm_iq_gen_en(dm);
/*#ifdef PHYDM_COMMON_API_SUPPORT*/
/*path selection is controlled by driver*/
#if 0
if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
return;
#endif
phydm_dis_cdd(dm);
phydm_pathb_q_matrix_rotate(dm, 0);
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
/*Set Q matrix r_v11 =1*/
odm_set_bb_reg(dm, R_0x195c, MASKDWORD, 0x40000);
/*Set Q matrix enable*/
odm_set_bb_reg(dm, R_0x191c, BIT(7), 1);
}
#endif
}
void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (ODM_IC_11AC_SERIES_SUPPORT)
u32 phase_table_0[ANGLE_NUM] = {0x40000, 0x376CF, 0x20000, 0x00000,
0xFE0000, 0xFC8930, 0xFC0000,
0xFC8930, 0xFDFFFF, 0x000000,
0x020000, 0x0376CF};
u32 phase_table_1[ANGLE_NUM] = {0x00000, 0x1FFFF, 0x376CF, 0x40000,
0x0376CF, 0x01FFFF, 0x000000,
0xFDFFFF, 0xFC8930, 0xFC0000,
0xFC8930, 0xFDFFFF};
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
u32 phase_table_n_0[ANGLE_NUM] = {0x00, 0x0B, 0x02, 0x00, 0x02, 0x02,
0x04, 0x02, 0x0D, 0x09, 0x04, 0x0B};
u32 phase_table_n_1[ANGLE_NUM] = {0x40000100, 0x377F00DD, 0x201D8880,
0x00000000, 0xE01D8B80, 0xC8BF0322,
0xC000FF00, 0xC8BF0322, 0xDFE2777F,
0xFFC003FF, 0x20227480, 0x377F00DD};
u32 phase_table_n_2[ANGLE_NUM] = {0x00, 0x1E, 0x3C, 0x4C, 0x3C, 0x1E,
0x0F, 0xD2, 0xC3, 0xC4, 0xC3, 0xD2};
#endif
if (idx >= ANGLE_NUM) {
pr_debug("[%s]warning Phase Set Error: %d\n", __func__, idx);
return;
}
switch (dm->ic_ip_series) {
#if (ODM_IC_11AC_SERIES_SUPPORT == 1)
case PHYDM_IC_AC:
/*Set Q matrix r_v21*/
odm_set_bb_reg(dm, R_0x1954, 0xffffff, phase_table_0[idx]);
odm_set_bb_reg(dm, R_0x1950, 0xffffff, phase_table_1[idx]);
break;
#endif
#if (ODM_IC_11N_SERIES_SUPPORT == 1)
case PHYDM_IC_N:
/*Set Q matrix r_v21*/
odm_set_bb_reg(dm, R_0xc4c, 0xff000000, phase_table_n_0[idx]);
odm_set_bb_reg(dm, R_0xc88, 0xffffffff, phase_table_n_1[idx]);
odm_set_bb_reg(dm, R_0xc9c, 0xff000000, phase_table_n_2[idx]);
break;
#endif
default:
break;
}
}
/*Before use this API, Fill correct Tx Des. and Disable STBC in advance*/
void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (RTL8822B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822B) {
#if 0
u8 phi[13] = {0x0, 0x5, 0xa, 0xf, 0x15, 0x1a, 0x1f, 0x25,
0x2a, 0x2f, 0x35, 0x3a, 0x0};
u8 psi[13] = {0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7,
0x7, 0x7, 0x7, 0x7};
u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
#endif
u16 ns[3] = {52, 108, 234}; //20/40/80 MHz subcarrier number
u16 psiphi[13] = {0x1c0, 0x1c5, 0x1ca, 0x1cf, 0x1d5, 0x1da,
0x1df, 0x1e5, 0x1ea, 0x1ef, 0x1f5, 0x1fa,
0x1c0}; //{Psi_4bit, Phi_6bit} of 0~360
u16 psiphiR;
u8 i;
u8 snr = 0x12; // for 1SS BF
u8 nc = 0x0; //bit 2-0
u8 nr = 0x1; //bit 5-3
u8 ng = 0x0; //bit 7-6
u8 cb = 0x1; //bit 9-8; 1 => phi:6, psi:4;
u32 bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
u8 userid = su_idx; //bit 12
u32 csi_report = 0x0;
u32 ndp_bw = odm_get_bb_reg(dm, R_0x8ac, 0x3); //bit 11-10
u8 ndp_sc = 0; //bit 11-10
u32 ndp_info = 0x0;
u16 mem_num = 0;
u8 mem_move = 0;
u8 mem_sel = 0;
u16 mem_addr = 0;
u32 dw0, dw1;
u64 vm_info = 0;
u64 temp = 0;
u8 vm_cnt = 0;
mem_num = ((8 + (6 + 4) * ns[bw]) >> 6) + 1; // SU codebook 1
/* setting NDP BW/SC info*/
ndp_info = (ndp_bw & 0x3) | (ndp_bw & 0x3) << 6 |
(ndp_bw & 0x3) << 12 | (ndp_sc & 0xf) << 2 |
(ndp_sc & 0xf) << 8 | (ndp_sc & 0xf) << 14;
odm_set_bb_reg(dm, R_0xb58, 0x000FFFFC, ndp_info);
odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 1);
ODM_delay_ms(1); // delay 1ms
odm_set_bb_reg(dm, R_0x19f8, 0x00010000, 0);
/* setting CSI report info*/
csi_report = (userid & 0x1) << 12 | (bw & 0x3) << 10 |
(cb & 0x3) << 8 | (ng & 0x3) << 6 |
(nr & 0x7) << 3 | (nc & 0x7);
odm_set_bb_reg(dm, R_0x72c, 0x1FFF, csi_report);
odm_set_bb_reg(dm, R_0x71c, 0x80000000, 1);
PHYDM_DBG(dm, DBG_TXBF, "[%s] direct BF csi report 0x%x\n",
__func__, csi_report);
/*========================*/
odm_set_bb_reg(dm, R_0x19b8, 0x40, 1); //0x19b8[6]:1 to csi_rpt
odm_set_bb_reg(dm, R_0x19e0, 0x3FC0, 0xFF); //gated_clk off
odm_set_bb_reg(dm, R_0x9e8, 0x2000000, 1); //abnormal txbf
odm_set_bb_reg(dm, R_0x9e8, 0x1000000, 0); //read phi psi
odm_set_bb_reg(dm, R_0x9e8, 0x70000000, su_idx); //SU user 0
odm_set_bb_reg(dm, R_0x1910, 0x8000, 0); //BFer
dw0 = 0; // for 0x9ec
dw1 = 0; // for 0x1900
mem_addr = 0;
mem_sel = 0;
mem_move = 0;
vm_info = vm_info | (snr & 0xff); //V matrix info
vm_cnt = 8; // V matrix length counter
psiphiR = (psiphi[phs_idx] & 0x3ff);
while (mem_addr < mem_num) {
while (vm_cnt <= 32) {
// shift only max. 32 bit
if (vm_cnt >= 20) {
temp = psiphiR << 20;
temp = temp << (vm_cnt - 20);
} else {
temp = psiphiR << vm_cnt;
}
vm_info |= temp;
vm_cnt += 10;
}
if (mem_sel == 0) {
dw0 = vm_info & 0xffffffff;
vm_info = vm_info >> 32;
vm_cnt -= 32;
mem_sel = 1;
mem_move = 0;
} else {
dw1 = vm_info & 0xffffffff;
vm_info = vm_info >> 32;
vm_cnt -= 32;
mem_sel = 0;
mem_move = 1;
}
if (mem_move == 1) {
odm_set_bb_reg(dm, 0x9e8, 0x1000000, 0);
//read phi psi
odm_set_bb_reg(dm, 0x1910, 0x3FF0000,
mem_addr);
odm_set_bb_reg(dm, 0x09ec, 0xFFFFFFFF, dw0);
odm_set_bb_reg(dm, 0x1900, 0xFFFFFFFF, dw1);
odm_set_bb_reg(dm, 0x9e8, 0x1000000, 1);
//write phi psi
mem_move = 0;
mem_addr += 1;
}
}
odm_set_bb_reg(dm, 0x9e8, 0x2000000, 0); //normal txbf
}
#endif
} //end function
/*Before use this API, Disable STBC in advance*/
/*only 1SS rate can improve performance*/
void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#if (RTL8197G_SUPPORT)
if (dm->support_ic_type & ODM_RTL8197G) {
phydm_iq_gen_en(dm);
/*#ifdef PHYDM_COMMON_API_SUPPORT*/
/*path selection is controlled by driver, use 1ss 2Tx*/
#if 0
if (!phydm_api_trx_mode(dm, BB_PATH_AB, BB_PATH_AB, BB_PATH_AB))
return;
#endif
phydm_dis_cdd(dm);
if (enable)
odm_set_bb_reg(dm, R_0x1d90, 0x8000, 1);
else
odm_set_bb_reg(dm, R_0x1d90, 0x8000, 0);
}
#endif
} //end function
#endif
#endif

44
hal/phydm/phydm_direct_bf.h Normal file
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@ -0,0 +1,44 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_DIR_BF_H__
#define __PHYDM_DIR_BF_H__
#ifdef CONFIG_DIRECTIONAL_BF
#define ANGLE_NUM 12
/*@
* ============================================================
* function prototype
* ============================================================
*/
void phydm_iq_gen_en(void *dm_void);
void phydm_dis_cdd(void *dm_void);
void phydm_pathb_q_matrix_rotate_en(void *dm_void);
void phydm_pathb_q_matrix_rotate(void *dm_void, u16 idx);
void phydm_set_direct_bfer(void *dm_void, u16 phs_idx, u8 su_idx);
void phydm_set_direct_bfer_txdesc_en(void *dm_void, u8 enable);
#endif
#endif

795
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_DYNAMIC_TX_TWR
#ifdef BB_RAM_SUPPORT
void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
boolean pwr_ofst0_en = false;
boolean pwr_ofst1_en = false;
s8 pwr_ofst0 = 0;
s8 pwr_ofst1 = 0;
pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(23));
pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x1e70, BIT(31));
pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f0000);
pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x1e70, 0x7f000000);
PDM_SNPF(out_len, used, output + used, out_len - used,
"reg0: en:%d, pwr_ofst:0x%x, reg1: en:%d, pwr_ofst:0x%x\n",
pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
*_used = used;
*_out_len = out_len;
};
void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
s8 pwr_ofst)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
u8 reg_0x1e70 = 0;
if (!is_ofst1) {
bb_ctrl->tx_pwr_ofst_reg0_en = pwr_ofst_en;
bb_ctrl->tx_pwr_ofst_reg0 = pwr_ofst;
reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
odm_set_bb_reg(dm, R_0x1e70, 0x00ff0000, reg_0x1e70);
} else {
bb_ctrl->tx_pwr_ofst_reg1_en = pwr_ofst_en;
bb_ctrl->tx_pwr_ofst_reg1 = pwr_ofst;
reg_0x1e70 |= (pwr_ofst_en << 7) + (pwr_ofst & 0x7f);
odm_set_bb_reg(dm, R_0x1e70, 0xff000000, reg_0x1e70);
}
};
void phydm_rd_ram_pwr(void *dm_void, u8 macid, u32 *_used, char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 used = *_used;
u32 out_len = *_out_len;
boolean pwr_ofst0_en = false;
boolean pwr_ofst1_en = false;
s8 pwr_ofst0 = 0;
s8 pwr_ofst1 = 0;
u32 reg_0x1e84 = 0;
reg_0x1e84 |= (macid & 0x3f) << 24; /* macid*/
reg_0x1e84 |= BIT(31); /* read_en*/
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
pwr_ofst0_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(23));
pwr_ofst1_en = (boolean)odm_get_bb_reg(dm, R_0x2de8, BIT(31));
pwr_ofst0 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f0000);
pwr_ofst1 = (s8)odm_get_bb_reg(dm, R_0x2de8, 0x7f000000);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
PDM_SNPF(out_len, used, output + used, out_len - used,
"(macid:%d) ram0: en:%d, pwr_ofst:0x%x, ram1: en:%d, pwr_ofst:0x%x\n",
macid, pwr_ofst0_en, pwr_ofst0, pwr_ofst1_en, pwr_ofst1);
*_used = used;
*_out_len = out_len;
};
void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1,
boolean pwr_ofst_en, s8 pwr_ofst)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
u32 reg_0x1e84 = 0;
boolean pwr_ofst_ano_en = false;
s8 pwr_ofst_ano = 0;
if (macid > 63)
macid = 63;
dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) + dm_ram_per_sta->hw_igi;
if (!is_ofst1) {
dm_ram_per_sta->tx_pwr_offset0_en = pwr_ofst_en;
dm_ram_per_sta->tx_pwr_offset0 = pwr_ofst;
pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset1_en;
pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset1;
reg_0x1e84 |= (pwr_ofst_en << 15) + ((pwr_ofst & 0x7f) << 8) +
(pwr_ofst_ano_en << 23) +
((pwr_ofst_ano & 0x7f) << 16);
} else {
dm_ram_per_sta->tx_pwr_offset1_en = pwr_ofst_en;
dm_ram_per_sta->tx_pwr_offset1 = pwr_ofst;
pwr_ofst_ano_en = dm_ram_per_sta->tx_pwr_offset0_en;
pwr_ofst_ano = dm_ram_per_sta->tx_pwr_offset0;
reg_0x1e84 |= (pwr_ofst_ano_en << 15) +
((pwr_ofst_ano & 0x7f) << 8) +
(pwr_ofst_en << 23) + ((pwr_ofst & 0x7f) << 16);
}
reg_0x1e84 |= (macid & 0x3f) << 24;/* macid*/
reg_0x1e84 |= BIT(30); /* write_en*/
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000); /* read_en*/
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0); /* disable rd/wt*/
};
void phydm_rst_ram_pwr(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
u32 reg_0x1e84 = 0;
u8 i = 0;
for (i = 0; i < 64; i++) {
dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[i];
dm_ram_per_sta->tx_pwr_offset0_en = false;
dm_ram_per_sta->tx_pwr_offset1_en = false;
dm_ram_per_sta->tx_pwr_offset0 = 0x0;
dm_ram_per_sta->tx_pwr_offset1 = 0x0;
reg_0x1e84 = (dm_ram_per_sta->hw_igi_en << 7) +
dm_ram_per_sta->hw_igi;
reg_0x1e84 |= (i & 0x3f) << 24;
reg_0x1e84 |= BIT(30);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, reg_0x1e84);
}
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x80000000);
odm_set_bb_reg(dm, R_0x1e84, MASKDWORD, 0x0);
};
u8 phydm_pwr_lv_mapping_2nd(u8 tx_pwr_lv)
{
if (tx_pwr_lv == tx_high_pwr_level_level3)
return PHYDM_2ND_OFFSET_MINUS_11DB;
else if (tx_pwr_lv == tx_high_pwr_level_level2)
return PHYDM_2ND_OFFSET_MINUS_7DB;
else if (tx_pwr_lv == tx_high_pwr_level_level1)
return PHYDM_2ND_OFFSET_MINUS_3DB;
else
return PHYDM_2ND_OFFSET_ZERO;
}
void phydm_pwr_lv_ctrl(void *dm_void, u8 macid, u8 tx_pwr_lv)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
s8 pwr_offset = 0;
if (tx_pwr_lv == tx_high_pwr_level_level3)
pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_11DB;
else if (tx_pwr_lv == tx_high_pwr_level_level2)
pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_7DB;
else if (tx_pwr_lv == tx_high_pwr_level_level1)
pwr_offset = PHYDM_BBRAM_OFFSET_MINUS_3DB;
else
pwr_offset = PHYDM_BBRAM_OFFSET_ZERO;
phydm_wt_ram_pwr(dm, macid, RAM_PWR_OFST0, true, pwr_offset);
}
void phydm_dtp_fill_cmninfo_2nd(void *dm_void, u8 sta_id, u8 dtp_lvl)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
struct dtp_info *dtp = NULL;
if (!is_sta_active(sta))
return;
dtp = &dm->phydm_sta_info[sta_id]->dtp_stat;
dtp->dyn_tx_power = phydm_pwr_lv_mapping_2nd(dtp_lvl);
phydm_pwr_lv_ctrl(dm, sta->mac_id, dtp_lvl);
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
sta_id, sta->mac_id, dtp->dyn_tx_power);
}
void phydm_dtp_init_2nd(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
#if (RTL8822C_SUPPORT || RTL8812F_SUPPORT)
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F)) {
phydm_rst_ram_pwr(dm);
/* rsp tx use type 0*/
odm_set_mac_reg(dm, R_0x6d8, BIT(19) | BIT(18), RAM_PWR_OFST0);
}
#endif
};
#endif
boolean
phydm_check_rates(void *dm_void, u8 rate_idx)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/
u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/
u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/
u32 bitmap_result;
#if (RTL8822B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8822B) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0xfffff000;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8197F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8197F) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8192E_SUPPORT)
if (dm->support_ic_type & ODM_RTL8192E) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8192F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8192F) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x0fffffff;
}
#endif
#if (RTL8721D_SUPPORT)
if (dm->support_ic_type & ODM_RTL8721D) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0;
check_rate_bitmap0 &= 0x000fffff;
}
#endif
#if (RTL8821C_SUPPORT)
if (dm->support_ic_type & ODM_RTL8821C) {
check_rate_bitmap2 &= 0;
check_rate_bitmap1 &= 0x003ff000;
check_rate_bitmap0 &= 0x000fffff;
}
#endif
if (rate_idx >= 64)
bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;
else if (rate_idx >= 32)
bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1;
else if (rate_idx <= 31)
bitmap_result = BIT(rate_idx) & check_rate_bitmap0;
if (bitmap_result != 0)
return true;
else
return false;
}
enum rf_path
phydm_check_paths(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
enum rf_path max_path = RF_PATH_A;
if (dm->num_rf_path == 1)
max_path = RF_PATH_A;
if (dm->num_rf_path == 2)
max_path = RF_PATH_B;
if (dm->num_rf_path == 3)
max_path = RF_PATH_C;
if (dm->num_rf_path == 4)
max_path = RF_PATH_D;
return max_path;
}
#ifdef PHYDM_COMMON_API_NOT_SUPPORT
u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 ret = 0xff;
ret = config_phydm_read_txagc_n(dm, path, hw_rate);
return ret;
}
#endif
u8 phydm_search_min_power_index(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
enum rf_path path;
enum rf_path max_path;
u8 min_gain_index = 0x3f;
u8 gain_index = 0;
u8 i;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__);
max_path = phydm_check_paths(dm);
for (path = 0; path <= max_path; path++)
for (i = 0; i < 84; i++)
if (phydm_check_rates(dm, i)) {
if (dm->support_ic_type & PHYDM_COMMON_API_IC) {
#ifdef PHYDM_COMMON_API_SUPPORT
/*97F,8822B,92F,8821C*/
gain_index = phydm_api_get_txagc(dm, path, i);
#endif
} else {
/*92E*/
#ifdef PHYDM_COMMON_API_NOT_SUPPORT
gain_index = phydm_dtp_get_txagc(dm, path, i);
#endif
}
if (gain_index == 0xff) {
min_gain_index = 0x20;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Error Gain idx!! Rewite to: ((%d))\n",
min_gain_index);
break;
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Support Rate: ((%d)) -> Gain idx: ((%d))\n",
i, gain_index);
if (gain_index < min_gain_index)
min_gain_index = gain_index;
}
return min_gain_index;
}
void phydm_dynamic_tx_power_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 i = 0;
dm->last_dtp_lvl = tx_high_pwr_level_normal;
dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
switch (dm->ic_ip_series) {
#ifdef BB_RAM_SUPPORT
case PHYDM_IC_JGR3:
dm->set_pwr_th[0] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL1;
dm->set_pwr_th[1] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL2;
dm->set_pwr_th[2] = TX_PWR_NEAR_FIELD_TH_JGR3_LVL3;
phydm_dtp_init_2nd(dm);
break;
#endif
default:
for (i = 0; i < 3; i++)
dm->enhance_pwr_th[i] = 0xff;
dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
dm->set_pwr_th[2] = 0xff;
dm->min_power_index = phydm_search_min_power_index(dm);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
dm->min_power_index);
break;
}
}
void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (noisy_state == 0) {
dm->enhance_pwr_th[0] = dm->set_pwr_th[0];
dm->enhance_pwr_th[1] = dm->set_pwr_th[1];
dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
} else {
dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8;
dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5;
dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"DTP hp_enhance_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],
dm->enhance_pwr_th[2]);
}
u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi, u8 last_pwr_lv)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 th[DTP_POWER_LEVEL_SIZE];
u8 i;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
th[i] = dm->set_pwr_th[i];
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Ori-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
th[0], th[1], th[2]);
for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
if (i >= (last_pwr_lv))
th[i] += DTP_FLOOR_UP_GAP;
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Mod-DTP th: Lv1_th = %d, Lv2_th = %d, Lv3_th = %d\n",
th[0], th[1], th[2]);
} else {
for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++)
th[i] = dm->enhance_pwr_th[i];
for (i = 0; i < DTP_POWER_LEVEL_SIZE; i++) {
if (i >= (last_pwr_lv))
th[i] += DTP_FLOOR_UP_GAP;
}
}
if (input_rssi >= th[2])
return tx_high_pwr_level_level3;
else if (input_rssi < th[2] && input_rssi >= th[1])
return tx_high_pwr_level_level2;
else if (input_rssi < th[1] && input_rssi >= th[0])
return tx_high_pwr_level_level1;
else
return tx_high_pwr_level_normal;
}
u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
{
if (tx_pwr_lv == tx_high_pwr_level_level3)
return PHYDM_OFFSET_MINUS_11DB;
else if (tx_pwr_lv == tx_high_pwr_level_level2)
return PHYDM_OFFSET_MINUS_7DB;
else if (tx_pwr_lv == tx_high_pwr_level_level1)
return PHYDM_OFFSET_MINUS_3DB;
else
return PHYDM_OFFSET_ZERO;
}
void phydm_dynamic_response_power(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 rpwr = 0;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (dm->dynamic_tx_high_power_lvl == dm->last_dtp_lvl) {
PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
return;
}
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
dm->dynamic_tx_high_power_lvl);
dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);
odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18),
rpwr);
PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n",
dm->dynamic_tx_high_power_lvl);
}
void phydm_dtp_fill_cmninfo(void *dm_void, u8 sta_id, u8 dtp_lvl)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
struct dtp_info *dtp = NULL;
if (!is_sta_active(sta))
return;
dtp = &sta->dtp_stat;
dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"Fill cmninfo TxPwr: sta_id=(%d), macid=(%d), PwrLv (%d)\n",
sta_id, sta->mac_id, dtp->dyn_tx_power);
}
void phydm_dtp_per_sta(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = NULL;
struct dtp_info *dtp = NULL;
struct rssi_info *rssi = NULL;
struct phydm_bb_ram_ctrl *bb_ctrl = &dm->p_bb_ram_ctrl;
u8 sta_cnt = 0;
u8 i = 0;
u8 curr_pwr_lv = 0;
u8 last_pwr_lv = 0;
u8 mac_id_cnt = 0;
u64 macid_cur = 0;
u64 macid_diff = 0;
u64 macid_mask = 0;
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
sta = dm->phydm_sta_info[i];
if (is_sta_active(sta)) {
sta_cnt++;
dtp = &sta->dtp_stat;
rssi = &sta->rssi_stat;
macid_mask = (u64)BIT(sta->mac_id);
if (!(bb_ctrl->macid_is_linked & macid_mask))
dtp->sta_last_dtp_lvl = tx_high_pwr_level_normal;
last_pwr_lv = dtp->sta_last_dtp_lvl;
curr_pwr_lv = phydm_pwr_lvl_check(dm, rssi->rssi,
last_pwr_lv);
dtp->sta_tx_high_power_lvl = curr_pwr_lv;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"STA_id=%d, MACID=%d , RSSI: %d , GetPwrLv: %d\n",
i, sta->mac_id, rssi->rssi, curr_pwr_lv);
bb_ctrl->macid_is_linked |= macid_mask;
macid_cur |= macid_mask;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"macid_is_linked: (0x%llx), macid_cur: (0x%llx)\n",
bb_ctrl->macid_is_linked, macid_cur);
if (curr_pwr_lv == last_pwr_lv && dtp->sta_is_alive) {
dtp->sta_tx_high_power_lvl = last_pwr_lv;
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"DTP_lv not change: ((%d))\n",
curr_pwr_lv);
} else {
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"DTP_lv update: ((%d)) -> ((%d))\n",
last_pwr_lv, curr_pwr_lv);
dtp->sta_last_dtp_lvl = curr_pwr_lv;
switch (dm->ic_ip_series) {
#ifdef BB_RAM_SUPPORT
case PHYDM_IC_JGR3:
phydm_dtp_fill_cmninfo_2nd(dm, i, curr_pwr_lv);
break;
#endif
default:
phydm_dtp_fill_cmninfo(dm, i, curr_pwr_lv);
break;
}
if(!dtp->sta_is_alive)
dtp->sta_is_alive = true;
}
if (sta_cnt == dm->number_linked_client)
break;
}
}
macid_diff = bb_ctrl->macid_is_linked ^ macid_cur;
if (macid_diff)
bb_ctrl->macid_is_linked &= ~macid_diff;
while (macid_diff) {
if (macid_diff & 0x1)
phydm_pwr_lv_ctrl(dm, mac_id_cnt, tx_high_pwr_level_normal);
mac_id_cnt++;
macid_diff >>= 1;
}
}
void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 sta_id)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = dm->phydm_sta_info[sta_id];
struct dtp_info *dtp = NULL;
if (!is_sta_active(sta))
return;
dtp = &sta->dtp_stat;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (dm->fill_desc_dyntxpwr)
dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);
else
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"%s: fill_desc_dyntxpwr is null!\n", __func__);
if (dtp->last_tx_power != dtp->dyn_tx_power) {
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"%s: last_offset=%d, txpwr_offset=%d\n", __func__,
dtp->last_tx_power, dtp->dyn_tx_power);
dtp->last_tx_power = dtp->dyn_tx_power;
}
}
void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len)
{
u32 used = *_used;
u32 out_len = *_out_len;
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[7] = {0};
u8 set_pwr_th1, set_pwr_th2, set_pwr_th3;
u8 i = 0;
#ifdef BB_RAM_SUPPORT
s8 pwr_ofst_tmp = 0x0;
#endif
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"Set DTP threhosld: {1} {Lv1_th} {Lv2_th} {Lv3_th}\n");
#ifdef BB_RAM_SUPPORT
PDM_SNPF(out_len, used, output + used, out_len - used,
"Set pwr_tx_offset: {2} {0:reg 1:macid} {en} {offset 0/1} {0:-, 1:+} {Pwr Offset} {macid}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Read pwr_tx_offset : {3} {0:reg 1:macid} {macid(0~63), 255:all}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"Reset all ram pwr_tx_offset : {4}\n");
#endif
} else {
for (i = 0; i < 7; i++) {
if (input[i + 1])
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
&var1[i]);
}
switch (var1[0]) {
case 1:
for (i = 0; i < 3; i++) {
if (var1[i] == 0 || var1[i] > 100)
dm->set_pwr_th[i] = 0xff;
else
dm->set_pwr_th[i] = (u8)var1[1 + i];
}
PDM_SNPF(out_len, used, output + used, out_len - used,
"DTP_TH[0:2] = {%d, %d, %d}\n",
dm->set_pwr_th[0], dm->set_pwr_th[1],
dm->set_pwr_th[2]);
break;
#ifdef BB_RAM_SUPPORT
case 2:
if ((boolean)var1[4])
pwr_ofst_tmp = (s8)var1[5];
else
pwr_ofst_tmp = 0x0 - (s8)var1[5];
if ((boolean)var1[1])
phydm_wt_ram_pwr(dm, (u8)var1[6],
(boolean)var1[3],
(boolean)var1[2],
pwr_ofst_tmp);
else
phydm_wt_reg_pwr(dm, (boolean)var1[3],
(boolean)var1[2],
pwr_ofst_tmp);
break;
case 3:
if ((boolean)var1[1]) {
if ((u8)var1[2] == 0xff)
for (i = 0; i < 64; i++)
phydm_rd_ram_pwr(dm, i, &used,
output,
&out_len);
else
phydm_rd_ram_pwr(dm, (u8)var1[2], &used,
output, &out_len);
} else {
phydm_rd_reg_pwr(dm, &used, output, &out_len);
}
break;
case 4:
phydm_rst_ram_pwr(dm);
break;
#endif
}
}
*_used = used;
*_out_len = out_len;
}
void phydm_dynamic_tx_power(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = NULL;
u8 i = 0;
u8 rssi_min = dm->rssi_min;
u8 rssi_tmp = 0;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
PHYDM_DBG(dm, DBG_DYN_TXPWR,
"[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__,
rssi_min, dm->noisy_decision);
phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
/* Response Power */
dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm,
rssi_min,
dm->last_dtp_lvl);
phydm_dynamic_response_power(dm);
}
/* Per STA Tx power */
phydm_dtp_per_sta(dm);
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_dynamic_tx_power_init_win(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
mgnt_info->bDynamicTxPowerEnable = false;
#if DEV_BUS_TYPE == RT_USB_INTERFACE
if (RT_GetInterfaceSelection((PADAPTER)adapter) ==
INTF_SEL1_USB_High_Power) {
mgnt_info->bDynamicTxPowerEnable = true;
}
#endif
hal_data->LastDTPLvl = tx_high_pwr_level_normal;
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__,
mgnt_info->bDynamicTxPowerEnable);
}
void phydm_dynamic_tx_power_win(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
return;
#if (RTL8814A_SUPPORT)
if (dm->support_ic_type == ODM_RTL8814A)
odm_dynamic_tx_power_8814a(dm);
#endif
#if (RTL8821A_SUPPORT)
if (dm->support_ic_type & ODM_RTL8821) {
void *adapter = dm->adapter;
PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
if (mgnt_info->RegRspPwr == 1) {
if (dm->rssi_min > 60) {
/*Resp TXAGC offset = -3dB*/
odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 1);
} else if (dm->rssi_min < 55) {
/*Resp TXAGC offset = 0dB*/
odm_set_mac_reg(dm, R_0x6d8, 0x1C0000, 0);
}
}
}
#endif
}
#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMDYNAMICTXPOWER_H__
#define __PHYDMDYNAMICTXPOWER_H__
#ifdef CONFIG_DYNAMIC_TX_TWR
/* @============================================================
* Definition
* ============================================================
*/
/* 2020.6.23, Let gain_idx be initialized to 0 for linux compile warning*/
#define DYNAMIC_TXPWR_VERSION "2.1"
#define DTP_POWER_LEVEL_SIZE 3
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 60
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 80
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 63
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 55
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL3 90
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL2 85
#define TX_PWR_NEAR_FIELD_TH_JGR3_LVL1 80
#endif
#define tx_high_pwr_level_normal 0
#define tx_high_pwr_level_level1 1
#define tx_high_pwr_level_level2 2
#define tx_high_pwr_level_level3 3
#define tx_high_pwr_level_unchange 4
#define DTP_FLOOR_UP_GAP 3
/* @============================================================
* enumrate
* ============================================================
*/
enum phydm_dtp_power_offset {
PHYDM_OFFSET_ZERO = 0,
PHYDM_OFFSET_MINUS_3DB = 1,
PHYDM_OFFSET_MINUS_7DB = 2,
PHYDM_OFFSET_MINUS_11DB = 3,
PHYDM_OFFSET_ADD_3DB = 4,
PHYDM_OFFSET_ADD_6DB = 5
};
enum phydm_dtp_power_offset_2nd {
PHYDM_2ND_OFFSET_ZERO = 0,
PHYDM_2ND_OFFSET_MINUS_3DB = 1,
PHYDM_2ND_OFFSET_MINUS_7DB = 2,
PHYDM_2ND_OFFSET_MINUS_11DB = 3
};
enum phydm_dtp_power_offset_bbram {
/*@ HW min use 1dB*/
PHYDM_BBRAM_OFFSET_ZERO = 0,
PHYDM_BBRAM_OFFSET_MINUS_3DB = -3,
PHYDM_BBRAM_OFFSET_MINUS_7DB = -7,
PHYDM_BBRAM_OFFSET_MINUS_11DB = -11
};
enum phydm_dtp_power_pkt_type {
RAM_PWR_OFST0 = 0,
RAM_PWR_OFST1 = 1,
REG_PWR_OFST0 = 2,
REG_PWR_OFST1 = 3
};
/* @============================================================
* structure
* ============================================================
*/
/* @============================================================
* Function Prototype
* ============================================================
*/
extern void
odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 mac_id);
void phydm_dynamic_tx_power(void *dm_void);
void phydm_dynamic_tx_power_init(void *dm_void);
void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
void phydm_rd_reg_pwr(void *dm_void, u32 *_used, char *output, u32 *_out_len);
void phydm_wt_reg_pwr(void *dm_void, boolean is_ofst1, boolean pwr_ofst_en,
s8 pwr_ofst);
void phydm_wt_ram_pwr(void *dm_void, u8 macid, boolean is_ofst1,
boolean pwr_ofst_en, s8 pwr_ofst);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void odm_dynamic_tx_power_win(void *dm_void);
#endif
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_H__
#define __PHYDM_FEATURES_H__
#define CONFIG_RUN_IN_DRV
#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | \
ODM_RTL8710B | \
ODM_RTL8192F | \
ODM_RTL8821C | \
ODM_RTL8822B | \
ODM_RTL8721D | \
ODM_RTL8723D | \
ODM_RTL8710C)
#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#define ODM_DYM_BW_INDICATION_SUPPORT (ODM_RTL8821C | \
ODM_RTL8822B | \
ODM_RTL8822C)
/*@20170103 YuChen add for FW API*/
#define PHYDM_FW_API_ENABLE_8822B 1
#define PHYDM_FW_API_FUNC_ENABLE_8822B 1
#define PHYDM_FW_API_ENABLE_8821C 1
#define PHYDM_FW_API_FUNC_ENABLE_8821C 1
#define PHYDM_FW_API_ENABLE_8195B 1
#define PHYDM_FW_API_FUNC_ENABLE_8195B 1
#define PHYDM_FW_API_ENABLE_8198F 1
#define PHYDM_FW_API_FUNC_ENABLE_8198F 1
#define PHYDM_FW_API_ENABLE_8822C 1
#define PHYDM_FW_API_FUNC_ENABLE_8822C 1
#define PHYDM_FW_API_ENABLE_8814B 1
#define PHYDM_FW_API_FUNC_ENABLE_8814B 1
#define PHYDM_FW_API_ENABLE_8812F 1
#define PHYDM_FW_API_FUNC_ENABLE_8812F 1
#define PHYDM_FW_API_ENABLE_8197G 1
#define PHYDM_FW_API_FUNC_ENABLE_8197G 1
#define PHYDM_FW_API_ENABLE_8723F 1
#define PHYDM_FW_API_FUNC_ENABLE_8723F 1
#define CONFIG_POWERSAVING 0
#ifdef BEAMFORMING_SUPPORT
#if (BEAMFORMING_SUPPORT)
#define PHYDM_BEAMFORMING_SUPPORT
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "phydm_features_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "phydm_features_ce.h"
/*@#include "phydm_features_ce2_kernel.h"*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "phydm_features_ap.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#include "phydm_features_iot.h"
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_AP_H__
#define __PHYDM_FEATURES_AP_H__
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\
RTL8197G_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT || RTL8198F_SUPPORT || RTL8814B_SUPPORT ||\
RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT)
#define FAHM_SUPPORT
#endif
#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8723F_SUPPORT)
#define IFS_CLM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8812F_SUPPORT)
/*#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
#endif
#if (RTL8197F_SUPPORT)
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#endif
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT ||\
RTL8197G_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_TDMA_DIG_SUPPORT 1
#ifdef PHYDM_TDMA_DIG_SUPPORT
#define IS_USE_NEW_TDMA /*new tdma dig test*/
#endif
#endif
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT ||\
RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#define PHYDM_LNA_SAT_CHK_SUPPORT
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#define PHYDM_LNA_SAT_CHK_TYPE1
#endif
#endif
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_POWER_TRAINING_SUPPORT*/
#endif
#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_PMAC_TX_SETTING_SUPPORT
#endif
#if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
/*#define CONFIG_RA_FW_DBG_CODE*/
#endif
#if (RTL8192F_SUPPORT == 1)
/*#define CONFIG_8912F_SPUR_CALIBRATION*/
#endif
#if (RTL8822B_SUPPORT == 1)
/* #define CONFIG_8822B_SPUR_CALIBRATION */
#endif
#if (RTL8197G_SUPPORT)
#define CONFIG_DIRECTIONAL_BF
#endif
#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT)
#define CONFIG_DYNAMIC_TX_TWR
#endif
#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT)
#define PHYDM_HW_IGI
#endif
#if (RTL8197G_SUPPORT || RTL8812F_SUPPORT)
#define CONFIG_DYNAMIC_TXCOLLISION_TH
#endif
/*#define CONFIG_PSD_TOOL*/
#define PHYDM_SUPPORT_CCKPD
#define PHYDM_SUPPORT_ADAPTIVITY
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
/*#define CONFIG_RA_DYNAMIC_RATE_ID*/
#define CONFIG_BB_TXBF_API
/*#define ODM_CONFIG_BT_COEXIST*/
#define PHYDM_SUPPORT_RSSI_MONITOR
#if !defined(CONFIG_DISABLE_PHYDM_DEBUG_FUNCTION)
#define CONFIG_PHYDM_DEBUG_FUNCTION
#endif
/* [ Configure Antenna Diversity ] */
#if (RTL8188F_SUPPORT)
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#endif
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) || defined(CONFIG_RTL_8197F_ANT_SWITCH) || defined(CONFIG_RTL_8197G_ANT_SWITCH)
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#define ODM_EVM_ENHANCE_ANTDIV
/*#define SKIP_EVM_ANTDIV_TRAINING_PATCH*/
/*----------*/
#ifdef CONFIG_NO_2G_DIVERSITY_8197F
#define CONFIG_NO_2G_DIVERSITY
#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197F)
#define CONFIG_2G_CGCS_RX_DIVERSITY
#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197F)
#define CONFIG_2G_CG_TRX_DIVERSITY
#endif
/*----------*/
#ifdef CONFIG_NO_2G_DIVERSITY_8197G
#define CONFIG_NO_2G_DIVERSITY
#elif defined(CONFIG_2G_CGCS_RX_DIVERSITY_8197G)
#define CONFIG_2G_CGCS_RX_DIVERSITY
#elif defined(CONFIG_2G_CG_TRX_DIVERSITY_8197G)
#define CONFIG_2G_CG_TRX_DIVERSITY
#endif
#if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_2G_DIVERSITY
#endif
#ifdef CONFIG_NO_5G_DIVERSITY_8881A
#define CONFIG_NO_5G_DIVERSITY
#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
#define CONFIG_5G_CGCS_RX_DIVERSITY
#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
#define CONFIG_5G_CG_TRX_DIVERSITY
#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
#define CONFIG_2G5G_CG_TRX_DIVERSITY
#endif
#if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_5G_DIVERSITY
#endif
/*----------*/
#if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
#define CONFIG_NOT_SUPPORT_ANTDIV
#elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY))
#define CONFIG_2G_SUPPORT_ANTDIV
#elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY))
#define CONFIG_5G_SUPPORT_ANTDIV
#elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY))
#define CONFIG_2G5G_SUPPORT_ANTDIV
#endif
/*----------*/
#endif /*Antenna Diveristy*/
/*[SmartAntenna]*/
/*#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
#define CFG_DIG_DAMPING_CHK
/* --------------------------------------------------*/
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8814B_SUPPORT || RTL8812F_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_CE_H__
#define __PHYDM_FEATURES_CE_H__
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\
RTL8814B_SUPPORT || RTL8723F_SUPPORT)
#define FAHM_SUPPORT
#endif
#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
#define IFS_CLM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822C_SUPPORT)
#define NHM_DYM_PW_TH_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
/*@#define PHYDM_PHYSTAUS_AUTO_SWITCH*/
#endif
/*@#define PHYDM_TDMA_DIG_SUPPORT*/
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822C_SUPPORT || RTL8723D_SUPPORT )
#ifdef CONFIG_TDMADIG
#define PHYDM_TDMA_DIG_SUPPORT
#ifdef PHYDM_TDMA_DIG_SUPPORT
#define IS_USE_NEW_TDMA /*new tdma dig test*/
#endif
#endif
#endif
#if (RTL8814B_SUPPORT)
/*@#define PHYDM_TDMA_DIG_SUPPORT*/
#ifdef PHYDM_TDMA_DIG_SUPPORT
/*@#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
#endif
#endif
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#if (RTL8814B_SUPPORT)
/*@#define PHYDM_LNA_SAT_CHK_TYPE1*/
#endif
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8723D_SUPPORT)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_PMAC_TX_SETTING_SUPPORT
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#define PHYDM_CCK_RX_PATHDIV_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define CONFIG_RECEIVER_BLOCKING
#endif
#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT)
#define CONFIG_BW_INDICATION
#endif
#if (RTL8192F_SUPPORT)
/*#define CONFIG_8912F_SPUR_CALIBRATION*/
#endif
#if (RTL8822B_SUPPORT)
#define CONFIG_8822B_SPUR_CALIBRATION
#endif
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
#define CONFIG_DYNAMIC_TX_TWR
#endif
#if (RTL8822C_SUPPORT)
#define PHYDM_HW_IGI
#endif
#define PHYDM_SUPPORT_CCKPD
#define PHYDM_SUPPORT_ADAPTIVITY
/*@Antenna Diversity*/
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
RTL8188F_SUPPORT || RTL8821C_SUPPORT ||\
RTL8723D_SUPPORT||RTL8723F_SUPPORT)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8821A_SUPPORT)
/*@#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*@#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_PATH_DIVERSITY
#endif
/*@[SmartAntenna]*/
/*@#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
/*@#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* @--------------------------------------------------*/
#ifdef CONFIG_DFS_MASTER
#define CONFIG_PHYDM_DFS_MASTER
#endif
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
/*@#define CONFIG_RA_FW_DBG_CODE*/
#endif
#define CONFIG_PSD_TOOL
/*@#define CONFIG_ANT_DETECTION*/
/*@#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_SUPPORT_RSSI_MONITOR
#define PHYDM_AUTO_DEGBUG
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\
RTL8814A_SUPPORT || RTL8881A_SUPPORT)
#define PHYDM_BEAMFORMING_VERSION1
#endif
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT)
#ifdef CONFIG_MCC_MODE
#define CONFIG_MCC_DM
#endif
#endif
#if (RTL8822B_SUPPORT)
#ifdef CONFIG_DYNAMIC_BYPASS_MODE
#define CONFIG_DYNAMIC_BYPASS
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_DIRECTIONAL_BF
#endif
#if (RTL8822C_SUPPORT)
#define CONFIG_MU_RSOML
#endif
#endif

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hal/phydm/phydm_features_ce2_kernel.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_CE_H__
#define __PHYDM_FEATURES_CE_H__
#define PHYDM_LA_MODE_SUPPORT 0
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8192F_SUPPORT == 1)
/*#define CONFIG_8912F_SPUR_CALIBRATION*/
#endif
#if (RTL8822B_SUPPORT == 1)
/* #define CONFIG_8822B_SPUR_CALIBRATION */
#endif
#define PHYDM_SUPPORT_CCKPD
#define PHYDM_SUPPORT_ADAPTIVITY
#ifdef CONFIG_DFS_MASTER
#define CONFIG_PHYDM_DFS_MASTER
#endif
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DEBUG_FUNCTION
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_SUPPORT_RSSI_MONITOR
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_IOT_H__
#define __PHYDM_FEATURES_IOT_H__
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8195B_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT)
#define FAHM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
/* #define PHYDM_PMAC_TX_SETTING_SUPPORT */
#endif
#if (RTL8822C_SUPPORT)
/* #define PHYDM_MP_SUPPORT */
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8822B_SUPPORT)
/*#define CONFIG_DYNAMIC_RX_PATH*/
#endif
#if (RTL8822B_SUPPORT == 1)
/* #define CONFIG_8822B_SPUR_CALIBRATION */
#endif
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define CONFIG_RECEIVER_BLOCKING
#endif
#ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR
#define CONFIG_DYNAMIC_TX_TWR
#endif
#define PHYDM_SUPPORT_CCKPD
#define PHYDM_SUPPORT_ADAPTIVITY
/*Antenna Diversity*/
#ifdef CONFIG_ANTENNA_DIVERSITY
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT ||\
RTL8188F_SUPPORT || RTL8821C_SUPPORT || RTL8195B_SUPPORT)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8710C_SUPPORT)
//#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8821A_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
#endif
#endif
/*[SmartAntenna]*/
/*#define CONFIG_SMART_ANTENNA*/
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
#ifdef CONFIG_DFS_MASTER
#define CONFIG_PHYDM_DFS_MASTER
#endif
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
/*#define CONFIG_RA_FW_DBG_CODE*/
#endif
#define CONFIG_PSD_TOOL
/*#define CONFIG_RA_DBG_CMD*/
/*#define CONFIG_ANT_DETECTION*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
//#define CONFIG_BB_TXBF_API
#if DBG
#define CONFIG_PHYDM_DEBUG_FUNCTION
#endif
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST
#endif
#define PHYDM_SUPPORT_RSSI_MONITOR
/*#define PHYDM_AUTO_DEGBUG*/
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#define CONFIG_BB_TXBF_API
#endif
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDM_FEATURES_WIN_H__
#define __PHYDM_FEATURES_WIN_H__
#if (RTL8814A_SUPPORT || RTL8821C_SUPPORT || RTL8822B_SUPPORT ||\
RTL8197F_SUPPORT || RTL8192F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_LA_MODE_SUPPORT 1
#else
#define PHYDM_LA_MODE_SUPPORT 0
#endif
#if (RTL8822B_SUPPORT || RTL8812A_SUPPORT || RTL8197F_SUPPORT ||\
RTL8192F_SUPPORT)
#define DYN_ANT_WEIGHTING_SUPPORT
#endif
#if (RTL8822B_SUPPORT || RTL8821C_SUPPORT || RTL8822C_SUPPORT ||\
RTL8814B_SUPPORT || RTL8723F_SUPPORT)
#define FAHM_SUPPORT
#endif
#if (RTL8822C_SUPPORT || RTL8723F_SUPPORT)
#define IFS_CLM_SUPPORT
#endif
#define NHM_SUPPORT
#define CLM_SUPPORT
#if (RTL8822C_SUPPORT)
#define NHM_DYM_PW_TH_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#define PHYDM_PHYSTAUS_AUTO_SWITCH
#endif
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#if (RTL8814B_SUPPORT)
/*#define PHYDM_TDMA_DIG_SUPPORT*/
#ifdef PHYDM_TDMA_DIG_SUPPORT
/*#define IS_USE_NEW_TDMA*/ /*new tdma dig test*/
#endif
#endif
#if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8814B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT*/
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
#if (RTL8197F_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_SUPPORT_TYPE1*/
#endif
#if (RTL8822B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE2*/
#endif
#if (RTL8814B_SUPPORT)
/*#define PHYDM_LNA_SAT_CHK_TYPE1*/
#endif
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8710B_SUPPORT || RTL8723D_SUPPORT ||\
RTL8192F_SUPPORT)
#define PHYDM_POWER_TRAINING_SUPPORT
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_PMAC_TX_SETTING_SUPPORT
#endif
#if (RTL8822C_SUPPORT || RTL8814B_SUPPORT || RTL8723F_SUPPORT)
#define PHYDM_MP_SUPPORT
#endif
#if (RTL8822C_SUPPORT)
#define PHYDM_CCK_RX_PATHDIV_SUPPORT
#endif
#if (RTL8822B_SUPPORT)
#define PHYDM_TXA_CALIBRATION
#endif
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define PHYDM_PRIMARY_CCA
#endif
#if (RTL8188F_SUPPORT || RTL8710B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8192F_SUPPORT)
#define PHYDM_DC_CANCELLATION
#endif
#if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_ADAPTIVE_SOML
#endif
#if (RTL8192F_SUPPORT)
#define CONFIG_8912F_SPUR_CALIBRATION
#endif
/*Antenna Diversity*/
#define CONFIG_PHYDM_ANTENNA_DIVERSITY
#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
#if (RTL8723B_SUPPORT || RTL8821A_SUPPORT || RTL8188F_SUPPORT ||\
RTL8821C_SUPPORT || RTL8723D_SUPPORT)
#define CONFIG_S0S1_SW_ANTENNA_DIVERSITY
#endif
#if (RTL8822B_SUPPORT)
/*#define ODM_EVM_ENHANCE_ANTDIV*/
/*#define CONFIG_2T3R_ANTENNA*/
/*#define CONFIG_2T4R_ANTENNA*/
#endif
/* --[SmtAnt]-----------------------------------------*/
#if (RTL8821A_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
#define CONFIG_FAT_PATCH
#endif
#if (RTL8822B_SUPPORT)
/*#define CONFIG_HL_SMART_ANTENNA_TYPE2*/
#endif
#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1) || defined(CONFIG_HL_SMART_ANTENNA_TYPE2))
#define CONFIG_HL_SMART_ANTENNA
#endif
/* --------------------------------------------------*/
#endif
#if (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8192F_SUPPORT)
#define CONFIG_PATH_DIVERSITY
#endif
/*[SmartAntenna]*/
#define CONFIG_SMART_ANTENNA
#ifdef CONFIG_SMART_ANTENNA
/*#define CONFIG_CUMITEK_SMART_ANTENNA*/
#endif
/* --------------------------------------------------*/
#if (RTL8188E_SUPPORT || RTL8192E_SUPPORT)
#define CONFIG_RECEIVER_BLOCKING
#endif
#if (RTL8821C_SUPPORT || RTL8822C_SUPPORT || RTL8822B_SUPPORT)
#define CONFIG_BW_INDICATION
#endif
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8881A_SUPPORT ||\
RTL8192E_SUPPORT || RTL8723B_SUPPORT)
#define CONFIG_RA_FW_DBG_CODE
#endif
/* #ifdef CONFIG_SUPPORT_DYNAMIC_TXPWR */
#define CONFIG_DYNAMIC_TX_TWR
/* #endif */
#if (RTL8822C_SUPPORT)
#define PHYDM_HW_IGI
#endif
#define CONFIG_PSD_TOOL
#define PHYDM_SUPPORT_ADAPTIVITY
#define PHYDM_SUPPORT_CCKPD
#if (defined(PHYDM_SUPPORT_CCKPD) && RTL8822C_SUPPORT)
#define PHYDM_DCC_ENHANCE
#endif
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_ANT_DETECTION
#define CONFIG_BB_TXBF_API
#define ODM_CONFIG_BT_COEXIST
#define CONFIG_PHYDM_DFS_MASTER
#define PHYDM_SUPPORT_RSSI_MONITOR
#define PHYDM_AUTO_DEGBUG
#define CONFIG_PHYDM_DEBUG_FUNCTION
#define CFG_DIG_DAMPING_CHK
#ifdef PHYDM_BEAMFORMING_SUPPORT
#if (RTL8812A_SUPPORT || RTL8821A_SUPPORT || RTL8192E_SUPPORT ||\
RTL8814A_SUPPORT || RTL8881A_SUPPORT)
#define PHYDM_BEAMFORMING_VERSION1
#endif
#if (RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8821C_SUPPORT ||\
RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8198F_SUPPORT ||\
RTL8822C_SUPPORT || RTL8814B_SUPPORT)
#define DRIVER_BEAMFORMING_VERSION2
#endif
#endif
#if (RTL8822B_SUPPORT || RTL8192F_SUPPORT)
/*#define CONFIG_DIRECTIONAL_BF*/
#endif
#if (RTL8822C_SUPPORT)
#define CONFIG_MU_RSOML
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*@--------------------------Define -------------------------------------------*/
#define AGC_DIFF_CONFIG_MP(ic, band) \
(odm_read_and_config_mp_##ic##_agc_tab_diff(dm, \
array_mp_##ic##_agc_tab_diff_##band, \
sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
#define AGC_DIFF_CONFIG_TC(ic, band) \
(odm_read_and_config_tc_##ic##_agc_tab_diff(dm, \
array_tc_##ic##_agc_tab_diff_##band, \
sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
#if defined(DM_ODM_CE_MAC80211)
#else
#define AGC_DIFF_CONFIG(ic, band) \
do { \
if (dm->is_mp_chip) \
AGC_DIFF_CONFIG_MP(ic, band); \
else \
AGC_DIFF_CONFIG_TC(ic, band); \
} while (0)
#endif
/*@************************************************************
* structure and define
************************************************************/
enum hal_status
odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm);
enum hal_status
odm_config_rf_with_header_file(struct dm_struct *dm,
enum odm_rf_config_type config_type,
u8 e_rf_path);
enum hal_status
odm_config_bb_with_header_file(struct dm_struct *dm,
enum odm_bb_config_type config_type);
enum hal_status
odm_config_mac_with_header_file(struct dm_struct *dm);
u32 odm_get_hw_img_version(struct dm_struct *dm);
u32 query_phydm_trx_capability(struct dm_struct *dm);
u32 query_phydm_stbc_capability(struct dm_struct *dm);
u32 query_phydm_ldpc_capability(struct dm_struct *dm);
u32 query_phydm_txbf_parameters(struct dm_struct *dm);
u32 query_phydm_txbf_capability(struct dm_struct *dm);
#endif /*@#ifndef __HALHWOUTSRC_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
#define INTERFACE_VERSION "1.2"
#define pdm_set_reg odm_set_bb_reg
/*@=========== Constant/Structure/Enum/... Define*/
enum phydm_h2c_cmd {
PHYDM_H2C_RA_MASK = 0x40,
PHYDM_H2C_TXBF = 0x41,
ODM_H2C_RSSI_REPORT = 0x42,
ODM_H2C_IQ_CALIBRATION = 0x45,
PHYDM_RA_MASK_ABOVE_3SS = 0x46,
ODM_H2C_RA_PARA_ADJUST = 0x47,
PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
PHYDM_H2C_FW_TRACE_EN = 0x49,
ODM_H2C_WIFI_CALIBRATION = 0x6d,
PHYDM_H2C_MU = 0x4a,
PHYDM_H2C_FW_GENERAL_INIT = 0x4c,
PHYDM_H2C_FW_CLM_MNTR = 0x4d,
PHYDM_H2C_MCC = 0x4f,
PHYDM_H2C_RESP_TX_PATH_CTRL = 0x50,
PHYDM_H2C_RESP_TX_ANT_CTRL = 0x51,
PHYDM_H2C_FW_DM_CTRL = 0x55,
ODM_MAX_H2CCMD
};
enum phydm_c2h_evt {
PHYDM_C2H_DBG = 0,
PHYDM_C2H_LB = 1,
PHYDM_C2H_XBF = 2,
PHYDM_C2H_TX_REPORT = 3,
PHYDM_C2H_INFO = 9,
PHYDM_C2H_BT_MP = 11,
PHYDM_C2H_RA_RPT = 12,
PHYDM_C2H_RA_PARA_RPT = 14,
PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
PHYDM_C2H_IQK_FINISH = 17, /*@0x11*/
PHYDM_C2H_CLM_MONITOR = 0x2a,
PHYDM_C2H_DBG_CODE = 0xFE,
PHYDM_C2H_EXTEND = 0xFF,
};
enum phydm_extend_c2h_evt {
PHYDM_EXTEND_C2H_DBG_PRINT = 0
};
enum phydm_halmac_param {
PHYDM_HALMAC_CMD_MAC_W8 = 0,
PHYDM_HALMAC_CMD_MAC_W16 = 1,
PHYDM_HALMAC_CMD_MAC_W32 = 2,
PHYDM_HALMAC_CMD_BB_W8,
PHYDM_HALMAC_CMD_BB_W16,
PHYDM_HALMAC_CMD_BB_W32,
PHYDM_HALMAC_CMD_RF_W,
PHYDM_HALMAC_CMD_DELAY_US,
PHYDM_HALMAC_CMD_DELAY_MS,
PHYDM_HALMAC_CMD_END = 0XFF,
};
/*@=========== Macro Define*/
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
#if defined(DM_ODM_CE_MAC80211)
#define ODM_BIT(name, dm) \
((dm->support_ic_type & ODM_IC_11N_SERIES) ? \
ODM_BIT_##name##_11N : ODM_BIT_##name##_11AC)
#define ODM_REG(name, dm) \
((dm->support_ic_type & ODM_IC_11N_SERIES) ? \
ODM_REG_##name##_11N : ODM_REG_##name##_11AC)
#else
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#ifdef __ECOS
#define _rtk_cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name))
#else
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \
_func##_11AC(_name))
#endif
/*@
* only sample code
*#define _cat(_name, _ic_type, _func) \
* ( \
* ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) :\
* _func##_ic(_name, _8195) \
* )
*/
/* @_name: name of register or bit.
* Example: "ODM_REG(R_A_AGC_CORE1, dm)"
* gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C",
* depends on support_ic_type.
*/
#ifdef __ECOS
#define ODM_REG(_name, _pdm_odm) \
_rtk_cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) \
_rtk_cat(_name, _pdm_odm->support_ic_type, _bit)
#else
#define ODM_REG(_name, _pdm_odm) \
_cat(_name, _pdm_odm->support_ic_type, _reg)
#define ODM_BIT(_name, _pdm_odm) \
_cat(_name, _pdm_odm->support_ic_type, _bit)
#endif
#endif
/*@
* =========== Extern Variable ??? It should be forbidden.
*/
/*@
* =========== EXtern Function Prototype
*/
u8 odm_read_1byte(struct dm_struct *dm, u32 reg_addr);
u16 odm_read_2byte(struct dm_struct *dm, u32 reg_addr);
u32 odm_read_4byte(struct dm_struct *dm, u32 reg_addr);
void odm_write_1byte(struct dm_struct *dm, u32 reg_addr, u8 data);
void odm_write_2byte(struct dm_struct *dm, u32 reg_addr, u16 data);
void odm_write_4byte(struct dm_struct *dm, u32 reg_addr, u32 data);
void odm_set_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask,
u32 data);
u32 odm_get_mac_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
void odm_set_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask, u32 data);
u32 odm_get_bb_reg(struct dm_struct *dm, u32 reg_addr, u32 bit_mask);
void odm_set_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
u32 bit_mask, u32 data);
u32 odm_get_rf_reg(struct dm_struct *dm, u8 e_rf_path, u32 reg_addr,
u32 bit_mask);
/*@
* Memory Relative Function.
*/
void odm_allocate_memory(struct dm_struct *dm, void **ptr, u32 length);
void odm_free_memory(struct dm_struct *dm, void *ptr, u32 length);
void odm_move_memory(struct dm_struct *dm, void *dest, void *src, u32 length);
s32 odm_compare_memory(struct dm_struct *dm, void *buf1, void *buf2,
u32 length);
void odm_memory_set(struct dm_struct *dm, void *pbuf, s8 value, u32 length);
/*@
* ODM MISC-spin lock relative API.
*/
void odm_acquire_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
void odm_release_spin_lock(struct dm_struct *dm, enum rt_spinlock_type type);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
/*@
* ODM MISC-workitem relative API.
*/
void odm_initialize_work_item(
struct dm_struct *dm,
PRT_WORK_ITEM p_rt_work_item,
RT_WORKITEM_CALL_BACK rt_work_item_callback,
void *context,
const char *sz_id);
void odm_start_work_item(
PRT_WORK_ITEM p_rt_work_item);
void odm_stop_work_item(
PRT_WORK_ITEM p_rt_work_item);
void odm_free_work_item(
PRT_WORK_ITEM p_rt_work_item);
void odm_schedule_work_item(
PRT_WORK_ITEM p_rt_work_item);
boolean
odm_is_work_item_scheduled(
PRT_WORK_ITEM p_rt_work_item);
#endif
/*@
* ODM Timer relative API.
*/
void ODM_delay_ms(u32 ms);
void ODM_delay_us(u32 us);
void ODM_sleep_ms(u32 ms);
void ODM_sleep_us(u32 us);
void odm_set_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
u32 ms_delay);
void odm_initialize_timer(struct dm_struct *dm, struct phydm_timer_list *timer,
void *call_back_func, void *context,
const char *sz_id);
void odm_cancel_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
void odm_release_timer(struct dm_struct *dm, struct phydm_timer_list *timer);
/*ODM FW relative API.*/
enum hal_status
phydm_set_reg_by_fw(struct dm_struct *dm, enum phydm_halmac_param config_type,
u32 offset, u32 data, u32 mask, enum rf_path e_rf_path,
u32 delay_time);
void odm_fill_h2c_cmd(struct dm_struct *dm, u8 element_id, u32 cmd_len,
u8 *cmd_buffer);
u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len,
u8 *tmp_buf);
u64 odm_get_current_time(struct dm_struct *dm);
u64 odm_get_progressing_time(struct dm_struct *dm, u64 start_time);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) && \
(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
void phydm_set_hw_reg_handler_interface(struct dm_struct *dm, u8 reg_Name,
u8 *val);
void phydm_get_hal_def_var_handler_interface(struct dm_struct *dm,
enum _HAL_DEF_VARIABLE e_variable,
void *value);
#endif
void odm_set_tx_power_index_by_rate_section(struct dm_struct *dm,
enum rf_path path, u8 channel,
u8 rate_section);
u8 odm_get_tx_power_index(struct dm_struct *dm, enum rf_path path, u8 tx_rate,
u8 band_width, u8 channel);
u8 odm_efuse_one_byte_read(struct dm_struct *dm, u16 addr, u8 *data,
boolean b_pseu_do_test);
void odm_efuse_logical_map_read(struct dm_struct *dm, u8 type, u16 offset,
u32 *data);
enum hal_status
odm_iq_calibrate_by_fw(struct dm_struct *dm, u8 clear, u8 segment);
enum hal_status
odm_dpk_by_fw(struct dm_struct *dm);
void phydm_cmn_sta_info_hook(struct dm_struct *dm, u8 index,
struct cmn_sta_info *pcmn_sta_info);
void phydm_macid2sta_idx_table(struct dm_struct *dm, u8 entry_idx,
struct cmn_sta_info *pcmn_sta_info);
void phydm_add_interrupt_mask_handler(struct dm_struct *dm, u8 interrupt_type);
void phydm_enable_rx_related_interrupt_handler(struct dm_struct *dm);
void phydm_iqk_wait(struct dm_struct *dm, u32 timeout);
u8 phydm_get_hwrate_to_mrate(struct dm_struct *dm, u8 rate);
void phydm_set_crystalcap(struct dm_struct *dm, u8 crystal_cap);
void phydm_run_in_thread_cmd(struct dm_struct *dm, void (*func)(void *),
void *context);
u8 phydm_get_tx_rate(struct dm_struct *dm);
u8 phydm_get_tx_power_dbm(struct dm_struct *dm, u8 rf_path,
u8 rate, u8 bandwidth, u8 channel);
s16 phydm_get_tx_power_mdbm(struct dm_struct *dm, u8 rf_path,
u8 rate, u8 bandwidth, u8 channel);
u32 phydm_rfe_ctrl_gpio(struct dm_struct *dm, u8 gpio_num);
u64 phydm_division64(u64 x, u64 y);
#endif /* @__ODM_INTERFACE_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_LNA_SAT_H__
#define __PHYDM_LNA_SAT_H__
#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define LNA_SAT_VERSION "1.1"
/*@LNA saturation check*/
#define OFDM_AGC_TAB_0 0
#define OFDM_AGC_TAB_2 2
#define DIFF_RSSI_TO_IGI 10
#define ONE_SEC_MS 1000
#define LNA_CHK_PERIOD 100 /*@ms*/
#define LNA_CHK_CNT 10 /*@checks per callback*/
#define LNA_CHK_DUTY_CYCLE 5 /*@percentage*/
#define DELTA_STD 2
#define DELTA_MEAN 2
#define SNR_STATISTIC_SHIFT 8
#define SNR_RPT_MAX 256
/* @1 ============================================================
* 1 enumrate
* 1 ============================================================
*/
enum lna_sat_timer_state {
INIT_LNA_SAT_CHK_TIMMER,
CANCEL_LNA_SAT_CHK_TIMMER,
RELEASE_LNA_SAT_CHK_TIMMER
};
#ifdef PHYDM_LNA_SAT_CHK_TYPE2
enum lna_sat_chk_type2_status {
ORI_TABLE_MONITOR,
ORI_TABLE_TRAINING,
SAT_TABLE_MONITOR,
SAT_TABLE_TRAINING,
SAT_TABLE_TRY_FAIL,
ORI_TABLE_TRY_FAIL
};
#endif
enum lna_sat_type {
LNA_SAT_WITH_PEAK_DET = 1, /*type1*/
LNA_SAT_WITH_TRAIN = 2, /*type2*/
};
#ifdef PHYDM_HW_SWITCH_AGC_TAB
enum lna_pd_th_level {
LNA_PD_TH_LEVEL0 = 0,
LNA_PD_TH_LEVEL1 = 1,
LNA_PD_TH_LEVEL2 = 2,
LNA_PD_TH_LEVEL3 = 3
};
enum agc_tab_switch_state {
AGC_SWH_IDLE,
AGC_SWH_CCK,
AGC_SWH_OFDM
};
#endif
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_lna_sat_t {
#ifdef PHYDM_LNA_SAT_CHK_TYPE1
u8 chk_cnt;
u8 chk_duty_cycle;
u32 chk_period;/*@ms*/
boolean is_disable_lna_sat_chk;
boolean dis_agc_table_swh;
#endif
#ifdef PHYDM_LNA_SAT_CHK_TYPE2
u8 force_traget_macid;
u32 snr_var_thd;
u32 delta_snr_mean;
u16 ori_table_try_fail_times;
u16 cnt_lower_snr_statistic;
u16 sat_table_monitor_times;
u16 force_change_period;
u8 is_snr_detail_en;
u8 is_force_lna_sat_table;
u8 lwr_snr_ratio_bit_shift;
u8 cnt_snr_statistic;
u16 snr_statistic_sqr[SNR_RPT_MAX];
u8 snr_statistic[SNR_RPT_MAX];
u8 is_sm_done;
u8 is_snr_done;
u32 cur_snr_var;
u8 total_bit_shift;
u8 total_cnt_snr;
u32 cur_snr_mean;
u8 cur_snr_var0;
u32 cur_lower_snr_mean;
u32 pre_snr_mean;
u32 pre_snr_var;
u32 pre_lower_snr_mean;
u8 nxt_state;
u8 pre_state;
#endif
enum lna_sat_type lna_sat_type;
u32 sat_cnt_acc_patha;
u32 sat_cnt_acc_pathb;
#ifdef PHYDM_IC_ABOVE_3SS
u32 sat_cnt_acc_pathc;
#endif
#ifdef PHYDM_IC_ABOVE_4SS
u32 sat_cnt_acc_pathd;
#endif
u32 check_time;
boolean pre_sat_status;
boolean cur_sat_status;
#ifdef PHYDM_HW_SWITCH_AGC_TAB
boolean hw_swh_tab_on;
enum odm_rf_band cur_rf_band;
#endif
struct phydm_timer_list phydm_lna_sat_chk_timer;
u32 cur_timer_check_cnt;
u32 pre_timer_check_cnt;
};
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_lna_sat_chk_init(void *dm_void);
u8 phydm_get_ofdm_agc_tab(void *dm_void);
void phydm_lna_sat_chk(void *dm_void);
void phydm_lna_sat_chk_timers(void *dm_void, u8 state);
#ifdef PHYDM_LNA_SAT_CHK_TYPE1
#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)
void phydm_lna_sat_chk_bb_init(void *dm_void);
void phydm_set_ofdm_agc_tab_path(void *dm_void,
u8 tab_sel, enum rf_path path);
u8 phydm_get_ofdm_agc_tab_path(void *dm_void, enum rf_path path);
#endif /*@#if (RTL8198F_SUPPORT || RTL8814B_SUPPORT)*/
#endif
#ifdef PHYDM_LNA_SAT_CHK_TYPE2
void phydm_parsing_snr(void *dm_void, void *pktinfo_void, s8 *rx_snr);
#endif
void phydm_lna_sat_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_lna_sat_chk_watchdog(void *dm_void);
void phydm_lna_sat_check_init(void *dm_void);
#ifdef PHYDM_HW_SWITCH_AGC_TAB
void phydm_auto_agc_tab_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif
#endif /*@#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
const u32 db_invert_table[12][8] = {
{10, 13, 16, 20, 25, 32, 40, 50}, /* @U(32,3) */
{64, 80, 101, 128, 160, 201, 256, 318}, /* @U(32,3) */
{401, 505, 635, 800, 1007, 1268, 1596, 2010}, /* @U(32,3) */
{316, 398, 501, 631, 794, 1000, 1259, 1585}, /* @U(32,0) */
{1995, 2512, 3162, 3981, 5012, 6310, 7943, 10000}, /* @U(32,0) */
{12589, 15849, 19953, 25119, 31623, 39811, 50119, 63098}, /* @U(32,0) */
{79433, 100000, 125893, 158489, 199526, 251189, 316228,
398107}, /* @U(32,0) */
{501187, 630957, 794328, 1000000, 1258925, 1584893, 1995262,
2511886}, /* @U(32,0) */
{3162278, 3981072, 5011872, 6309573, 7943282, 1000000, 12589254,
15848932}, /* @U(32,0) */
{19952623, 25118864, 31622777, 39810717, 50118723, 63095734,
79432823, 100000000}, /* @U(32,0) */
{125892541, 158489319, 199526232, 251188643, 316227766, 398107171,
501187234, 630957345}, /* @U(32,0) */
{794328235, 1000000000, 1258925412, 1584893192, 1995262315,
2511886432U, 3162277660U, 3981071706U} }; /* @U(32,0) */
/*Y = 10*log(X)*/
s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
{
s32 Y, integer = 0, decimal = 0;
u32 i;
if (X == 0)
X = 1; /* @log2(x), x can't be 0 */
for (i = (total_bit - 1); i > 0; i--) {
if (X & BIT(i)) {
integer = i;
if (i > 0) {
/*decimal is 0.5dB*3=1.5dB~=2dB */
decimal = (X & BIT(i - 1)) ? 2 : 0;
}
break;
}
}
Y = 3 * (integer - decimal_bit) + decimal; /* @10*log(x)=3*log2(x), */
return Y;
}
s32 odm_sign_conversion(s32 value, u32 total_bit)
{
if (value & BIT(total_bit - 1))
value -= BIT(total_bit);
return value;
}
/*threshold must form low to high*/
u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u16 i = 0;
u16 ret_val = 0;
u16 max_th = threshold[th_len - 1];
for (i = 0; i < th_len; i++) {
if (val < threshold[i]) {
ret_val = i;
break;
} else if (val >= max_th) {
ret_val = th_len;
break;
}
}
return ret_val;
}
void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
u8 seq_length)
{
u8 i = 0, j = 0;
u32 tmp_a, tmp_b;
u32 tmp_idx_a, tmp_idx_b;
for (i = 0; i < seq_length; i++)
rank_idx[i] = i;
for (i = 0; i < (seq_length - 1); i++) {
for (j = 0; j < (seq_length - 1 - i); j++) {
tmp_a = value[j];
tmp_b = value[j + 1];
tmp_idx_a = rank_idx[j];
tmp_idx_b = rank_idx[j + 1];
if (tmp_a < tmp_b) {
value[j] = tmp_b;
value[j + 1] = tmp_a;
rank_idx[j] = tmp_idx_b;
rank_idx[j + 1] = tmp_idx_a;
}
}
}
for (i = 0; i < seq_length; i++)
idx_out[rank_idx[i]] = i + 1;
}
u32 odm_convert_to_db(u64 value)
{
u8 i;
u8 j;
u32 dB;
if (value >= db_invert_table[11][7])
return 96; /* @maximum 96 dB */
for (i = 0; i < 12; i++) {
if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][7])
break;
else if (i > 2 && value <= db_invert_table[i][7])
break;
}
for (j = 0; j < 8; j++) {
if (i <= 2 && (value << FRAC_BITS) <= db_invert_table[i][j])
break;
else if (i > 2 && i < 12 && value <= db_invert_table[i][j])
break;
}
/*special cases*/
if (j == 0 && i == 0)
goto end;
if (i == 3 && j == 0) {
if (db_invert_table[3][0] - value >
value - (db_invert_table[2][7] >> FRAC_BITS)) {
i = 2;
j = 7;
}
goto end;
}
if (i < 3)
value = value << FRAC_BITS; /*@elements of row 0~2 shift left*/
/*compare difference to get precise dB*/
if (j == 0) {
if (db_invert_table[i][j] - value >
value - db_invert_table[i - 1][7]) {
i = i - 1;
j = 7;
}
} else {
if (db_invert_table[i][j] - value >
value - db_invert_table[i][j - 1]) {
j = j - 1;
}
}
end:
dB = (i << 3) + j + 1;
return dB;
}
u64 phydm_db_2_linear(u32 value)
{
u8 i = 0;
u8 j = 0;
u64 linear = 0;
value = value & 0xFF;
/* @1dB~96dB */
if (value > 96) {
value = 96;
} else if (value < 1) {
linear = 1;
return linear;
}
i = (u8)((value - 1) >> 3);
j = (u8)(value - 1) - (i << 3);
linear = db_invert_table[i][j];
if (i > 2)
linear = linear << FRAC_BITS;
return linear;
}
u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num)
{
u8 i = 0;
u16 val = 0;
u16 base = 5000;
for (i = bit_num; i > 0; i--) {
if (frac_val & BIT(i - 1))
val += (base >> (bit_num - i));
}
return val;
}
u16 phydm_ones_num_in_bitmap(u64 val, u8 size)
{
u8 i = 0;
u8 ones_num = 0;
for (i = 0; i < size; i++) {
if (val & BIT(0))
ones_num++;
val = val >> 1;
}
return ones_num;
}
u64 phydm_gen_bitmask(u8 mask_num)
{
u8 i = 0;
u64 bitmask = 0;
if (mask_num > 64)
return 1;
for (i = 0; i < mask_num; i++)
bitmask = (bitmask << 1) | BIT(0);
return bitmask;
}
s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num)
{
if (bit_num >= 32)
return (s32)val;
if (val & BIT(bit_num - 1)) /*Sign BIT*/
val -= (1 << bit_num); /*@2's*/
return val;
}
s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num)
{
u64 one = 1;
s64 val_sign = (s64)val;
if (bit_num >= 64)
return (s64)val;
if (val & (one << (bit_num - 1))) /*Sign BIT*/
val_sign = val - (one << bit_num); /*@2's*/
return val_sign;
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_MATH_LIB_H__
#define __PHYDM_MATH_LIB_H__
/* @2019.01.24 remove linear2db debug log*/
#define AUTO_MATH_LIB_VERSION "1.2"
/*@
* 1 ============================================================
* 1 Definition
* 1 ============================================================
*/
#define PHYDM_DIV(a, b) ((b) ? ((a) / (b)) : 0)
#define DIVIDED_2(X) ((X) >> 1)
/*@1/3 ~ 11/32*/
#if defined(DM_ODM_CE_MAC80211)
#define DIVIDED_3(X) ({ \
u32 div_3_tmp = (X); \
(((div_3_tmp) + ((div_3_tmp) << 1) + ((div_3_tmp) << 3)) >> 5); })
#else
#define DIVIDED_3(X) (((X) + ((X) << 1) + ((X) << 3)) >> 5)
#endif
#define DIVIDED_4(X) ((X) >> 2)
/*Store Ori Value*/
#if defined(DM_ODM_CE_MAC80211)
#define WEIGHTING_AVG(v1, w1, v2, w2) \
__WEIGHTING_AVG(v1, w1, v2, w2, typeof(v1), typeof(w1), typeof(v2), \
typeof(w2))
#define __WEIGHTING_AVG(v1, w1, v2, w2, t1, t2, t3, t4) ({ \
t1 __w_a_v1 = (v1); \
t2 __w_a_w1 = (w1); \
t3 __w_a_v2 = (v2); \
t4 __w_a_w2 = (w2); \
((__w_a_v1) * (__w_a_w1) + (__w_a_v2) * (__w_a_w2)) \
/ ((__w_a_w2) + (__w_a_w1)); })
#else
#define WEIGHTING_AVG(v1, w1, v2, w2) \
(((v1) * (w1) + (v2) * (w2)) / ((w2) + (w1)))
#endif
/*Store 2^ma x Value*/
#if defined(DM_ODM_CE_MAC80211)
#define MA_ACC(old, new_val, ma) ({ \
s16 __ma_acc_o = (old); \
(__ma_acc_o) - ((__ma_acc_o) >> (ma)) + (new_val); })
#define GET_MA_VAL(val, ma) ({ \
s16 __get_ma_tmp = (ma);\
((val) + (1 << ((__get_ma_tmp) - 1))) >> (__get_ma_tmp); })
#else
#define MA_ACC(old, new_val, ma) ((old) - ((old) >> (ma)) + (new_val))
#define GET_MA_VAL(val, ma) (((val) + (1 << ((ma) - 1))) >> (ma))
#endif
#define FRAC_BITS 3
/*@
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
/*@
* 1 ============================================================
* 1 structure
* 1 ============================================================
*/
/*@
* 1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
s32 odm_sign_conversion(s32 value, u32 total_bit);
u16 phydm_find_intrvl(void *dm_void, u16 val, u16 *threshold, u16 th_len);
void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
u8 seq_length);
u32 odm_convert_to_db(u64 value);
u64 phydm_db_2_linear(u32 value);
u16 phydm_show_fraction_num(u32 frac_val, u8 bit_num);
u16 phydm_ones_num_in_bitmap(u64 val, u8 size);
u64 phydm_gen_bitmask(u8 mask_num);
s32 phydm_cnvrt_2_sign(u32 val, u8 bit_num);
s64 phydm_cnvrt_2_sign_64(u64 val, u8 bit_num);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_MP_SUPPORT
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_mp_set_single_tone_jgr3(void *dm_void, boolean is_single_tone,
u8 path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
u8 start = RF_PATH_A, end = RF_PATH_A;
u8 i = 0;
u8 central_ch = 0;
boolean is_2g_ch = false;
switch (path) {
case RF_PATH_A:
case RF_PATH_B:
case RF_PATH_C:
case RF_PATH_D:
start = path;
end = path;
break;
case RF_PATH_AB:
start = RF_PATH_A;
end = RF_PATH_B;
break;
#if (defined(PHYDM_COMPILE_IC_4SS))
case RF_PATH_AC:
start = RF_PATH_A;
end = RF_PATH_C;
break;
case RF_PATH_AD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_BC:
start = RF_PATH_B;
end = RF_PATH_C;
break;
case RF_PATH_BD:
start = RF_PATH_B;
end = RF_PATH_D;
break;
case RF_PATH_CD:
start = RF_PATH_C;
end = RF_PATH_D;
break;
case RF_PATH_ABC:
start = RF_PATH_A;
end = RF_PATH_C;
break;
case RF_PATH_ABD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_ACD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
case RF_PATH_BCD:
start = RF_PATH_B;
end = RF_PATH_D;
break;
case RF_PATH_ABCD:
start = RF_PATH_A;
end = RF_PATH_D;
break;
#endif
}
central_ch = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff);
is_2g_ch = (central_ch <= 14) ? true : false;
if (is_single_tone) {
/*Disable CCA*/
if (is_2g_ch) { /*CCK RxIQ weighting = [0,0]*/
if(dm->support_ic_type & ODM_RTL8723F) {
odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x1); /*CCK*/
} else {
odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x0);
odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
}
}
odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x1ff); /*OFDM*/
if (dm->support_ic_type & ODM_RTL8723F) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x0);
for (i = start; i <= end; i++) {
mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
/*Tx mode: RF0x00[19:16]=4'b0010 */
odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
/*Lowest RF gain index: RF_0x1[5:0] TX power*/
mp->rf1[i] = odm_get_rf_reg(dm, i, RF_0x1, RFREG_MASK);
odm_set_rf_reg(dm, i, RF_0x1, 0x3f, 0x0);//TX power
/*RF LO enabled */
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
}
} else {
for (i = start; i <= end; i++) {
mp->rf0[i] = odm_get_rf_reg(dm, i, RF_0x0, RFREG_MASK);
/*Tx mode: RF0x00[19:16]=4'b0010 */
odm_set_rf_reg(dm, i, RF_0x0, 0xF0000, 0x2);
/*Lowest RF gain index: RF_0x0[4:0] = 0*/
odm_set_rf_reg(dm, i, RF_0x0, 0x1f, 0x0);
/*RF LO enabled */
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x1);
}
}
#if (RTL8814B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8814B) {
mp->rf0_syn[RF_SYN0] = config_phydm_read_syn_reg_8814b(
dm, RF_SYN0, RF_0x0, RFREG_MASK);
/*Lowest RF gain index: RF_0x0[4:0] = 0x0*/
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
0x1f, 0x0);
/*RF LO enabled */
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
BIT(1), 0x1);
/*SYN1*/
if (*dm->band_width == CHANNEL_WIDTH_80_80) {
mp->rf0_syn[RF_SYN1] = config_phydm_read_syn_reg_8814b(
dm, RF_SYN1, RF_0x0,
RFREG_MASK);
config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
RF_0x0, 0x1f,
0x0);
config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
RF_0x58, BIT(1),
0x1);
}
}
#endif
} else {
/*Enable CCA*/
if (is_2g_ch) { /*CCK RxIQ weighting = [1,1]*/
if(dm->support_ic_type & ODM_RTL8723F) {
odm_set_bb_reg(dm, R_0x2a24, BIT(13), 0x0); /*CCK*/
} else {
odm_set_bb_reg(dm, R_0x1a9c, BIT(20), 0x1);
odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
}
}
odm_set_bb_reg(dm, R_0x1d58, 0xff8, 0x0); /*OFDM*/
if(dm->support_ic_type & ODM_RTL8723F) {
for (i = start; i <= end; i++) {
odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
odm_set_rf_reg(dm, i, RF_0x1, RFREG_MASK, mp->rf1[i]);
/*RF LO disabled */
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
}
odm_set_rf_reg(dm, RF_PATH_A, RF_0x5, BIT(0), 0x1);
} else {
for (i = start; i <= end; i++) {
odm_set_rf_reg(dm, i, RF_0x0, RFREG_MASK, mp->rf0[i]);
/*RF LO disabled */
odm_set_rf_reg(dm, i, RF_0x58, BIT(1), 0x0);
}
}
#if (RTL8814B_SUPPORT)
if (dm->support_ic_type & ODM_RTL8814B) {
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x0,
RFREG_MASK,
mp->rf0_syn[RF_SYN0]);
config_phydm_write_rf_syn_8814b(dm, RF_SYN0, RF_0x58,
BIT(1), 0x0);
/*SYN1*/
if (*dm->band_width == CHANNEL_WIDTH_80_80) {
config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
RF_0x0,
RFREG_MASK,
mp->rf0_syn[RF_SYN1]);
config_phydm_write_rf_syn_8814b(dm, RF_SYN1,
RF_0x58, BIT(1),
0x0);
}
}
#endif
}
}
void phydm_mp_set_carrier_supp_jgr3(void *dm_void, boolean is_carrier_supp,
u32 rate_index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
if (is_carrier_supp) {
if (phydm_is_cck_rate(dm, (u8)rate_index)) {
/*if CCK block on? */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 1);
if(dm->support_ic_type & ODM_RTL8723F){
/* @Carrier suppress tx */
odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x1);
/*turn off scramble setting */
odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x1);
/*Set CCK Tx Test Rate, set TxRate to 2Mbps */
odm_set_bb_reg(dm, R_0x2a08, 0x300000, 0x1);
/* BB and PMAC cont tx */
odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
/* TX CCK ON */
odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
}
else {
/*Turn Off All Test mode */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
/*transmit mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2);
/*turn off scramble setting */
odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x0);
/*Set CCK Tx Test Rate, set TxRate to 1Mbps */
odm_set_bb_reg(dm, R_0x1a00, 0x3000, 0x0);
}
}
} else { /*Stop Carrier Suppression. */
if (phydm_is_cck_rate(dm, (u8)rate_index)) {
if(dm->support_ic_type & ODM_RTL8723F) {
/* TX Stop */
odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
/* Clear BB cont tx */
odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
/* Clear PMAC cont tx */
odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
/* Clear TX Stop */
odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
/* normal mode */
odm_set_bb_reg(dm, R_0x2a08, BIT(18), 0x0);
/* turn on scramble setting */
odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
}
else {
/*normal mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
/*turn on scramble setting */
odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
}
/*BB Reset */
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
}
}
}
void phydm_mp_set_single_carrier_jgr3(void *dm_void, boolean is_single_carrier)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
if (is_single_carrier) {
/*1. if OFDM block on? */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 1);
if (dm->support_ic_type & ODM_RTL8723F) {
/*3. turn on scramble setting */
odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0);
/*4. Turn On single carrier. */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
}
else {
/*2. set CCK test mode off, set to CCK normal mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0);
/*3. turn on scramble setting */
odm_set_bb_reg(dm, R_0x1a00, BIT(3), 1);
/*4. Turn On single carrier. */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_SINGLE_CARRIER);
}
} else {
/*Turn off all test modes. */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, OFDM_OFF);
/*Delay 10 ms */
ODM_delay_ms(10);
/*BB Reset*/
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
}
}
void phydm_mp_get_tx_ok_jgr3(void *dm_void, u32 rate_index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
if (phydm_is_cck_rate(dm, (u8)rate_index))
mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
else
mp->tx_phy_ok_cnt = odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
}
void phydm_mp_get_rx_ok_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_mp *mp = &dm->dm_mp_table;
u32 cck_ok = 0, ofdm_ok = 0, ht_ok = 0, vht_ok = 0;
u32 cck_err = 0, ofdm_err = 0, ht_err = 0, vht_err = 0;
if(dm->support_ic_type & ODM_RTL8723F)
cck_ok = odm_get_bb_reg(dm, R_0x2aac, MASKLWORD);
else
cck_ok = odm_get_bb_reg(dm, R_0x2c04, MASKLWORD);
ofdm_ok = odm_get_bb_reg(dm, R_0x2c14, MASKLWORD);
ht_ok = odm_get_bb_reg(dm, R_0x2c10, MASKLWORD);
vht_ok = odm_get_bb_reg(dm, R_0x2c0c, MASKLWORD);
if(dm->support_ic_type & ODM_RTL8723F)
cck_err = odm_get_bb_reg(dm, R_0x2aac, MASKHWORD);
else
cck_err = odm_get_bb_reg(dm, R_0x2c04, MASKHWORD);
ofdm_err = odm_get_bb_reg(dm, R_0x2c14, MASKHWORD);
ht_err = odm_get_bb_reg(dm, R_0x2c10, MASKHWORD);
vht_err = odm_get_bb_reg(dm, R_0x2c0c, MASKHWORD);
mp->rx_phy_ok_cnt = cck_ok + ofdm_ok + ht_ok + vht_ok;
mp->rx_phy_crc_err_cnt = cck_err + ofdm_err + ht_err + vht_err;
mp->io_value = (u32)mp->rx_phy_ok_cnt;
}
#endif
void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phydm_set_crystal_cap(dm, crystal_cap);
}
void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_mp_set_single_tone_jgr3(dm, is_single_tone, path);
}
void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
u32 rate_index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_mp_set_carrier_supp_jgr3(dm, is_carrier_supp, rate_index);
}
void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_mp_set_single_carrier_jgr3(dm, is_single_carrier);
}
void phydm_mp_reset_rx_counters_phy(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phydm_reset_bb_hw_cnt(dm);
}
void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_mp_get_tx_ok_jgr3(dm, rate_index);
}
void phydm_mp_get_rx_ok(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_mp_get_rx_ok_jgr3(dm);
}
#endif

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hal/phydm/phydm_mp.h Normal file
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@ -0,0 +1,83 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_MP_H__
#define __PHYDM_MP_H__
/*2020.04.27 Refine single tone Tx flow*/
#define MP_VERSION "1.5"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_mp {
/*Rx OK count, statistics used in Mass Production Test.*/
u64 tx_phy_ok_cnt;
u64 rx_phy_ok_cnt;
/*Rx CRC32 error count, statistics used in Mass Production Test.*/
u64 rx_phy_crc_err_cnt;
/*The Value of IO operation is depend of MptActType.*/
u32 io_value;
u32 rf0[RF_PATH_MEM_SIZE];
#if (RTL8814B_SUPPORT)
u32 rf0_syn[2];
#endif
u32 rf1[RF_PATH_MEM_SIZE];
};
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum TX_MODE_OFDM {
OFDM_OFF = 0,
OFDM_CONT_TX = 1,
OFDM_SINGLE_CARRIER = 2,
OFDM_SINGLE_TONE = 4,
};
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_mp_set_crystal_cap(void *dm_void, u8 crystal_cap);
void phydm_mp_set_single_tone(void *dm_void, boolean is_single_tone, u8 path);
void phydm_mp_set_carrier_supp(void *dm_void, boolean is_carrier_supp,
u32 rate_index);
void phydm_mp_set_single_carrier(void *dm_void, boolean is_single_carrier);
void phydm_mp_reset_rx_counters_phy(void *dm_void);
void phydm_mp_get_tx_ok(void *dm_void, u32 rate_index);
void phydm_mp_get_rx_ok(void *dm_void);
#endif

467
hal/phydm/phydm_noisemonitor.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
/**************************************************
* This function is for inband noise test utility only
* To obtain the inband noise level(dbm), do the following.
* 1. disable DIG and Power Saving
* 2. Set initial gain = 0x1a
* 3. Stop updating idle time pwer report (for driver read)
* - 0x80c[25]
*
*************************************************/
void phydm_set_noise_data_sum(struct noise_level *noise_data, u8 max_rf_path)
{
u8 i = 0;
for (i = RF_PATH_A; i < max_rf_path; i++) {
if (noise_data->valid_cnt[i])
noise_data->sum[i] /= noise_data->valid_cnt[i];
else
noise_data->sum[i] = 0;
}
}
#if (ODM_IC_11N_SERIES_SUPPORT)
s16 odm_inband_noise_monitor_n(struct dm_struct *dm, u8 is_pause_dig, u8 igi,
u32 max_time)
{
u32 tmp4b;
u8 max_rf_path = 0, i = 0;
u8 reg_c50, reg_c58, valid_done = 0;
struct noise_level noise_data;
u64 start = 0, func_start = 0, func_end = 0;
s8 val_s8 = 0;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
max_rf_path = 2;
else
max_rf_path = 1;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"odm_DebugControlInbandNoise_Nseries() ==>\n");
odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
/* step 1. Disable DIG && Set initial gain. */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
/* step 3. Get noise power level */
start = odm_get_current_time(dm);
while (1) {
/* Stop updating idle time pwer report (for driver read) */
odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 1);
/* Read Noise Floor Report */
tmp4b = odm_get_bb_reg(dm, R_0x8f8, MASKDWORD);
/* update idle time pwer report per 5us */
odm_set_bb_reg(dm, REG_FPGA0_TX_GAIN_STAGE, BIT(25), 0);
ODM_delay_us(5);
noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
for (i = RF_PATH_A; i < max_rf_path; i++) {
noise_data.sval[i] = (s8)noise_data.value[i];
noise_data.sval[i] /= 2;
}
for (i = RF_PATH_A; i < max_rf_path; i++) {
if (noise_data.valid_cnt[i] >= VALID_CNT)
continue;
noise_data.valid_cnt[i]++;
noise_data.sum[i] += noise_data.sval[i];
PHYDM_DBG(dm, DBG_ENV_MNTR,
"rf_path:%d Valid sval=%d\n", i,
noise_data.sval[i]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n",
noise_data.sum[i]);
if (noise_data.valid_cnt[i] == VALID_CNT)
valid_done++;
}
if (valid_done == max_rf_path ||
(odm_get_progressing_time(dm, start) > max_time)) {
phydm_set_noise_data_sum(&noise_data, max_rf_path);
break;
}
}
reg_c50 = (u8)odm_get_bb_reg(dm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
reg_c50 &= ~BIT(7);
val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
dm->noise_level.noise[RF_PATH_A] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
if (max_rf_path == 2) {
reg_c58 = (u8)odm_get_bb_reg(dm, R_0xc58, MASKBYTE0);
reg_c58 &= ~BIT(7);
val_s8 = (s8)(-110 + reg_c58 + noise_data.sum[RF_PATH_B]);
dm->noise_level.noise[RF_PATH_B] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
}
dm->noise_level.noise_all /= max_rf_path;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A],
dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
/* step 4. Recover the Dig */
if (is_pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
return dm->noise_level.noise_all;
}
#endif
#if (ODM_IC_11AC_SERIES_SUPPORT)
s16 phydm_idle_noise_measure_ac(struct dm_struct *dm, u8 pause_dig,
u8 igi, u32 max_time)
{
u32 tmp4b;
u8 max_rf_path = 0, i = 0;
u8 reg_c50, reg_e50, valid_done = 0;
u64 start = 0, func_start = 0, func_end = 0;
struct noise_level noise_data;
s8 val_s8 = 0;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
if (dm->rf_type == RF_1T2R || dm->rf_type == RF_2T2R)
max_rf_path = 2;
else
max_rf_path = 1;
PHYDM_DBG(dm, DBG_ENV_MNTR, "%s==>\n", __func__);
odm_memory_set(dm, &noise_data, 0, sizeof(struct noise_level));
/*Step 1. Disable DIG && Set initial gain.*/
if (pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
/*Step 2. Get noise power level*/
start = odm_get_current_time(dm);
while (1) {
/*Stop updating idle time pwer report (for driver read)*/
odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x1);
/*Read Noise Floor Report*/
tmp4b = odm_get_bb_reg(dm, R_0xff0, MASKDWORD);
/*update idle time pwer report per 5us*/
odm_set_bb_reg(dm, R_0x9e4, BIT(30), 0x0);
ODM_delay_us(5);
noise_data.value[RF_PATH_A] = (u8)(tmp4b & 0xff);
noise_data.value[RF_PATH_B] = (u8)((tmp4b & 0xff00) >> 8);
for (i = RF_PATH_A; i < max_rf_path; i++) {
noise_data.sval[i] = (s8)noise_data.value[i];
noise_data.sval[i] = noise_data.sval[i] >> 1;
}
for (i = RF_PATH_A; i < max_rf_path; i++) {
if (noise_data.valid_cnt[i] >= VALID_CNT)
continue;
noise_data.valid_cnt[i]++;
noise_data.sum[i] += noise_data.sval[i];
PHYDM_DBG(dm, DBG_ENV_MNTR, "Path:%d Valid sval = %d\n",
i, noise_data.sval[i]);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d\n",
noise_data.sum[i]);
if (noise_data.valid_cnt[i] == VALID_CNT)
valid_done++;
}
if (valid_done == max_rf_path ||
(odm_get_progressing_time(dm, start) > max_time)) {
phydm_set_noise_data_sum(&noise_data, max_rf_path);
break;
}
}
reg_c50 = (u8)odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
reg_c50 &= ~BIT(7);
val_s8 = (s8)(-110 + reg_c50 + noise_data.sum[RF_PATH_A]);
dm->noise_level.noise[RF_PATH_A] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_A];
if (max_rf_path == 2) {
reg_e50 = (u8)odm_get_bb_reg(dm, R_0xe50, MASKBYTE0);
reg_e50 &= ~BIT(7);
val_s8 = (s8)(-110 + reg_e50 + noise_data.sum[RF_PATH_B]);
dm->noise_level.noise[RF_PATH_B] = val_s8;
dm->noise_level.noise_all += dm->noise_level.noise[RF_PATH_B];
}
dm->noise_level.noise_all /= max_rf_path;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"noise_a = %d, noise_b = %d, noise_all = %d\n",
dm->noise_level.noise[RF_PATH_A],
dm->noise_level.noise[RF_PATH_B], dm->noise_level.noise_all);
/*Step 3. Recover the Dig*/
if (pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "end\n");
return dm->noise_level.noise_all;
}
s16 odm_inband_noise_monitor_ac(struct dm_struct *dm, u8 pause_dig, u8 igi,
u32 max_time)
{
s32 rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
s32 value32, pwdb_A = 0, sval, noise, sum = 0;
boolean pd_flag;
u8 valid_cnt = 0;
u8 invalid_cnt = 0;
u64 start = 0, func_start = 0, func_end = 0, proc_time = 0;
s32 val_s32 = 0;
s16 rpt = 0;
u8 val_u8 = 0;
if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) {
rpt = phydm_idle_noise_measure_ac(dm, pause_dig, igi, max_time);
return rpt;
}
if (!(dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A)))
return 0;
func_start = odm_get_current_time(dm);
dm->noise_level.noise_all = 0;
PHYDM_DBG(dm, DBG_ENV_MNTR, "%s ==>\n", __func__);
/* step 1. Disable DIG && Set initial gain. */
if (pause_dig)
odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, igi);
/* step 3. Get noise power level */
start = odm_get_current_time(dm);
/* step 3. Get noise power level */
while (1) {
/*Set IGI=0x1C */
odm_write_dig(dm, 0x1C);
/*stop CK320&CK88 */
odm_set_bb_reg(dm, R_0x8b4, BIT(6), 1);
/*Read path-A */
/*set debug port*/
odm_set_bb_reg(dm, R_0x8fc, MASKDWORD, 0x200);
/*read debug port*/
value32 = odm_get_bb_reg(dm, R_0xfa0, MASKDWORD);
/*rxi_buf_anta=RegFA0[19:10]*/
rxi_buf_anta = (value32 & 0xFFC00) >> 10;
rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
pd_flag = (boolean)((value32 & BIT(31)) >> 31);
/*Not in packet detection period or Tx state */
if (!pd_flag || rxi_buf_anta != 0x200) {
/*sign conversion*/
rxi_buf_anta = odm_sign_conversion(rxi_buf_anta, 10);
rxq_buf_anta = odm_sign_conversion(rxq_buf_anta, 10);
val_s32 = rxi_buf_anta * rxi_buf_anta +
rxq_buf_anta * rxq_buf_anta;
/*S(10,9)*S(10,9)=S(20,18)*/
pwdb_A = odm_pwdb_conversion(val_s32, 20, 18);
PHYDM_DBG(dm, DBG_ENV_MNTR,
"pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n",
pwdb_A, rxi_buf_anta & 0x3FF,
rxq_buf_anta & 0x3FF);
}
/*Start CK320&CK88*/
odm_set_bb_reg(dm, R_0x8b4, BIT(6), 0);
/*@BB Reset*/
val_u8 = odm_read_1byte(dm, 0x02) & (~BIT(0));
odm_write_1byte(dm, 0x02, val_u8);
val_u8 = odm_read_1byte(dm, 0x02) | BIT(0);
odm_write_1byte(dm, 0x02, val_u8);
/*PMAC Reset*/
val_u8 = odm_read_1byte(dm, 0xB03) & (~BIT(0));
odm_write_1byte(dm, 0xB03, val_u8);
val_u8 = odm_read_1byte(dm, 0xB03) | BIT(0);
odm_write_1byte(dm, 0xB03, val_u8);
/*@CCK Reset*/
if (odm_read_1byte(dm, 0x80B) & BIT(4)) {
val_u8 = odm_read_1byte(dm, 0x80B) & (~BIT(4));
odm_write_1byte(dm, 0x80B, val_u8);
val_u8 = odm_read_1byte(dm, 0x80B) | BIT(4);
odm_write_1byte(dm, 0x80B, val_u8);
}
sval = pwdb_A;
if ((sval < 0 && sval >= -27) && valid_cnt < VALID_CNT) {
valid_cnt++;
sum += sval;
PHYDM_DBG(dm, DBG_ENV_MNTR, "Valid sval = %d\n", sval);
PHYDM_DBG(dm, DBG_ENV_MNTR, "Sum of sval = %d,\n", sum);
if (valid_cnt >= VALID_CNT ||
(odm_get_progressing_time(dm, start) > max_time)) {
sum /= VALID_CNT;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"After divided, sum = %d\n", sum);
break;
}
} else {
/*Invalid sval and return -110 dBm*/
invalid_cnt++;
PHYDM_DBG(dm, DBG_ENV_MNTR, "Invalid sval\n");
if (invalid_cnt >= VALID_CNT + 5) {
PHYDM_DBG(dm, DBG_ENV_MNTR,
"Invalid count > TH, Return -110, Break!!\n");
return -110;
}
}
}
/*@ADC backoff is 12dB,*/
/*Ptarget=0x1C-110=-82dBm*/
noise = sum + 12 + 0x1C - 110;
/*Offset*/
noise = noise - 3;
PHYDM_DBG(dm, DBG_ENV_MNTR, "noise = %d\n", noise);
dm->noise_level.noise_all = (s16)noise;
/* step 4. Recover the Dig*/
if (pause_dig)
odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, igi);
func_end = odm_get_progressing_time(dm, func_start);
PHYDM_DBG(dm, DBG_ENV_MNTR, "%s <==\n", __func__);
return dm->noise_level.noise_all;
}
#endif
s16 odm_inband_noise_monitor(void *dm_void, u8 pause_dig, u8 igi,
u32 max_time)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
s16 val = 0;
igi = 0x32;
/* since HW ability is about +15~-35,
* we fix IGI = -60 for maximum coverage
*/
#if (ODM_IC_11AC_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11AC_SERIES)
val = odm_inband_noise_monitor_ac(dm, pause_dig, igi, max_time);
#endif
#if (ODM_IC_11N_SERIES_SUPPORT)
if (dm->support_ic_type & ODM_IC_11N_SERIES)
val = odm_inband_noise_monitor_n(dm, pause_dig, igi, max_time);
#endif
return val;
}
void phydm_noisy_detection(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 total_fa_cnt, total_cca_cnt;
u32 score = 0, i, score_smooth;
total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
total_fa_cnt = dm->false_alm_cnt.cnt_all;
#if 0
if (total_fa_cnt * 16 >= total_cca_cnt * 14) /* @87.5 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 12) /* @75 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 10) /* @56.25 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 8) /* @50 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 7) /* @43.75 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 6) /* @37.5 */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 5) /* @31.25% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 4) /* @25% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 3) /* @18.75% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 2) /* @12.5% */
;
else if (total_fa_cnt * 16 >= total_cca_cnt * 1) /* @6.25% */
;
#endif
for (i = 0; i <= 16; i++) {
if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
score = 16 - i;
break;
}
}
/* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
dm->noisy_decision_smooth = (dm->noisy_decision_smooth >> 1) +
(score << 2);
/* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
if (total_cca_cnt >= 300)
score_smooth = (dm->noisy_decision_smooth + 3) >> 3;
else
score_smooth = 0;
dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
PHYDM_DBG(dm, DBG_ENV_MNTR,
"[NoisyDetection] CCA_cnt=%d,FA_cnt=%d, noisy_dec_smooth=%d, score=%d, score_smooth=%d, noisy_dec=%d\n",
total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
score_smooth, dm->noisy_decision);
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODMNOISEMONITOR_H__
#define __ODMNOISEMONITOR_H__
#define VALID_CNT 5
struct noise_level {
u8 value[PHYDM_MAX_RF_PATH];
s8 sval[PHYDM_MAX_RF_PATH];
s32 sum[PHYDM_MAX_RF_PATH];
u8 valid[PHYDM_MAX_RF_PATH];
u8 valid_cnt[PHYDM_MAX_RF_PATH];
};
struct odm_noise_monitor {
s8 noise[PHYDM_MAX_RF_PATH];
s16 noise_all;
};
s16 odm_inband_noise_monitor(void *dm_void, u8 is_pause_dig, u8 igi_value,
u32 max_time);
void phydm_noisy_detection(void *dm_void);
#endif

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hal/phydm/phydm_pathdiv.c Normal file
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hal/phydm/phydm_pathdiv.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMPATHDIV_H__
#define __PHYDMPATHDIV_H__
#ifdef CONFIG_PATH_DIVERSITY
/* @2019.03.07 open resp tx path h2c only for 1ss status*/
#define PATHDIV_VERSION "4.4"
#if (RTL8192F_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\
RTL8812F_SUPPORT || RTL8197G_SUPPORT)
#define PHYDM_CONFIG_PATH_DIV_V2
#endif
#define USE_PATH_A_AS_DEFAULT_ANT /* @for 8814 dynamic TX path selection */
#define NUM_RESET_DTP_PERIOD 5
#define ANT_DECT_RSSI_TH 3
#define PATH_A 1
#define PATH_B 2
#define PATH_C 3
#define PATH_D 4
#define PHYDM_AUTO_PATH 0
#define PHYDM_FIX_PATH 1
#define NUM_CHOOSE2_FROM4 6
#define NUM_CHOOSE3_FROM4 4
enum phydm_dtp_state {
PHYDM_DTP_INIT = 1,
PHYDM_DTP_RUNNING_1
};
enum phydm_path_div_type {
PHYDM_2R_PATH_DIV = 1,
PHYDM_4R_PATH_DIV = 2
};
enum phydm_path_ctrl {
TX_PATH_BY_REG = 0,
TX_PATH_BY_DESC = 1,
TX_PATH_CTRL_INIT
};
struct path_txdesc_ctrl {
u8 ant_map_a : 2;
u8 ant_map_b : 2;
u8 ntx_map : 4;
};
struct _ODM_PATH_DIVERSITY_ {
boolean stop_path_div; /*@Limit by enabled path number*/
boolean path_div_in_progress;
boolean cck_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
boolean ofdm_fix_path_en; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
enum bb_path cck_fix_path_sel; /*@ BB Reg for Adv-Ctrl (or debug mode)*/
enum bb_path ofdm_fix_path_sel;/*@ BB Reg for Adv-Ctrl (or debug mode)*/
enum phydm_path_ctrl tx_path_ctrl;
enum bb_path default_tx_path;
enum bb_path path_sel[ODM_ASSOCIATE_ENTRY_NUM];
u32 path_a_sum[ODM_ASSOCIATE_ENTRY_NUM];
u32 path_b_sum[ODM_ASSOCIATE_ENTRY_NUM];
u16 path_a_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u16 path_b_cnt[ODM_ASSOCIATE_ENTRY_NUM];
u8 phydm_path_div_type;
boolean force_update;
#if RTL8814A_SUPPORT
u32 path_a_sum_all;
u32 path_b_sum_all;
u32 path_c_sum_all;
u32 path_d_sum_all;
u32 path_a_cnt_all;
u32 path_b_cnt_all;
u32 path_c_cnt_all;
u32 path_d_cnt_all;
u8 dtp_period;
boolean is_become_linked;
boolean is_u3_mode;
u8 num_tx_path;
u8 default_path;
u8 num_candidate;
u8 ant_candidate_1;
u8 ant_candidate_2;
u8 ant_candidate_3;
u8 phydm_dtp_state;
u8 dtp_check_patha_counter;
boolean fix_path_bfer;
u8 search_space_2[NUM_CHOOSE2_FROM4];
u8 search_space_3[NUM_CHOOSE3_FROM4];
u8 pre_tx_path;
u8 use_path_a_as_default_ant;
boolean is_path_a_exist;
#endif
};
void phydm_set_tx_path_by_bb_reg(void *dm_void, enum bb_path tx_path_sel_1ss);
void phydm_get_tx_path_txdesc_jgr3(void *dm_void, u8 macid,
struct path_txdesc_ctrl *desc);
void phydm_c2h_dtp_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void phydm_tx_path_diversity_init(void *dm_void);
void phydm_tx_path_diversity(void *dm_void);
void phydm_process_rssi_for_path_div(void *dm_void, void *phy_info_void,
void *pkt_info_void);
void phydm_pathdiv_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif /* @#ifdef CONFIG_PATH_DIVERSITY */
#endif /* @#ifndef __PHYDMPATHDIV_H__ */

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hal/phydm/phydm_pmac_tx_setting.c Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_PMAC_TX_SETTING_SUPPORT
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_start_cck_cont_tx_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u8 rate = tx_info->tx_rate; /* HW rate */
/* if CCK block on? */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(1)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(1), 0x1);
if (dm->support_ic_type & ODM_RTL8723F) {
odm_set_bb_reg(dm, R_0x2a08, BIT(21)|BIT(20), rate);
odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
} else {
/* Turn Off All Test mode */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
odm_set_bb_reg(dm, R_0x1a00, 0x3000, rate);
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x2); /* transmit mode */
odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
/* Fix rate selection issue */
odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x1);
/* set RX weighting for path I & Q to 0 */
odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x3);
/* set loopback mode */
odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x1);
}
pmac_tx->cck_cont_tx = true;
pmac_tx->ofdm_cont_tx = false;
}
void phydm_stop_cck_cont_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
pmac_tx->cck_cont_tx = false;
pmac_tx->ofdm_cont_tx = false;
if (dm->support_ic_type & ODM_RTL8723F) {
/* @Disable pmac tx_en*/
odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0); /* turn on scrambler*/
} else {
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0); /* normal mode */
odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1); /* turn on scrambler*/
/* back to default */
odm_set_bb_reg(dm, R_0x1a70, BIT(14), 0x0);
odm_set_bb_reg(dm, R_0x1a14, 0x300, 0x0);
odm_set_bb_reg(dm, R_0x1c3c, BIT(4), 0x0);
}
/* BB Reset */
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
}
void phydm_start_ofdm_cont_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
/* 1. if OFDM block on */
if (!odm_get_bb_reg(dm, R_0x1c3c, BIT(0)))
odm_set_bb_reg(dm, R_0x1c3c, BIT(0), 0x1);
if (!(dm->support_ic_type & ODM_RTL8723F)) {
/* 2. set CCK test mode off, set to CCK normal mode */
odm_set_bb_reg(dm, R_0x1a00, 0x3, 0x0);
/* 3. turn on scramble setting */
odm_set_bb_reg(dm, R_0x1a00, BIT(3), 0x1);
}
/* 4. Turn On Continue Tx and turn off the other test modes. */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x1);
pmac_tx->cck_cont_tx = false;
pmac_tx->ofdm_cont_tx = true;
}
void phydm_stop_ofdm_cont_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
pmac_tx->cck_cont_tx = false;
pmac_tx->ofdm_cont_tx = false;
/* Turn Off All Test mode */
odm_set_bb_reg(dm, R_0x1ca4, 0x7, 0x0);
/* Delay 10 ms */
ODM_delay_ms(10);
/* BB Reset */
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x0);
odm_set_bb_reg(dm, R_0x1d0c, BIT(16), 0x1);
}
void phydm_stop_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x2); /* TX Stop */
if (dm->support_ic_type & ODM_RTL8723F) {
if (tx_info->mode == CONT_TX) {
if (pmac_tx->is_cck_rate) {
/* TX Stop */
odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x1);
/* Clear BB cont tx */
odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x0);
/* Clear PMAC cont tx */
odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x0);
/* Clear TX Stop */
odm_set_bb_reg(dm, R_0x2a00, BIT(0), 0x0);
phydm_stop_cck_cont_tx_jgr3(dm);
} else
phydm_stop_ofdm_cont_tx_jgr3(dm);
} else {
if (pmac_tx->is_cck_rate) {
/* packet_count = 0x1 */
odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, 0x1);
/* @Disable pmac tx_en*/
odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
/* @Enable pmac tx_en*/
odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
phydm_stop_cck_cont_tx_jgr3(dm);
}
}
}else {
if (tx_info->mode == CONT_TX) {
if (pmac_tx->is_cck_rate)
phydm_stop_cck_cont_tx_jgr3(dm);
else
phydm_stop_ofdm_cont_tx_jgr3(dm);
}
}
}
void phydm_set_mac_phy_txinfo_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
odm_set_bb_reg(dm, R_0xa58, 0x003f8000, tx_info->tx_rate);
/*0x900[1] ndp_sound */
odm_set_bb_reg(dm, R_0x900, BIT(1), tx_info->ndp_sound);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
tx_info->m_stbc = tx_info->m_stbc - 1;
#endif
/*0x900[27:24] txsc [29:28] bw [31:30] m_stbc */
tmp = (tx_info->tx_sc) | ((tx_info->bw) << 4) |
((tx_info->m_stbc) << 6);
odm_set_bb_reg(dm, R_0x900, 0xff000000, tmp);
if (tx_info->tx_sc == 1) /*upper*/
odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x5);
else if (tx_info->tx_sc == 2) /*lower*/
odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x6);
else /* duplicate*/
odm_set_bb_reg(dm, R_0x1ae0, 0x7000, 0x0);
if (pmac_tx->is_ht_rate) {
odm_set_bb_reg(dm, R_0x900, BIT(0), 0x1);
odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
} else if (pmac_tx->is_vht_rate) {
odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
odm_set_bb_reg(dm, R_0x900, BIT(2), 0x1);
} else {
odm_set_bb_reg(dm, R_0x900, BIT(0), 0x0);
odm_set_bb_reg(dm, R_0x900, BIT(2), 0x0);
}
/* for TX interval */
odm_set_bb_reg(dm, R_0x9b8, MASKHWORD, tx_info->packet_period);
}
void phydm_set_sig_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
if (pmac_tx->is_cck_rate)
return;
odm_set_bb_reg(dm, R_0x1eb4, 0xfffff, tx_info->packet_count);
/* L-SIG */
tmp = BYTE_2_DWORD(0, tx_info->lsig[2], tx_info->lsig[1],
tx_info->lsig[0]);
odm_set_bb_reg(dm, R_0x908, 0xffffff, tmp);
if (pmac_tx->is_ht_rate) {
/* HT SIG */
tmp = BYTE_2_DWORD(0, tx_info->ht_sig[2], tx_info->ht_sig[1],
tx_info->ht_sig[0]);
odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
tmp = BYTE_2_DWORD(0, tx_info->ht_sig[5], tx_info->ht_sig[4],
tx_info->ht_sig[3]);
odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
} else if (pmac_tx->is_vht_rate) {
/* VHT SIG A/B/serv_field/delimiter */
tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[2],
tx_info->vht_sig_a[1],
tx_info->vht_sig_a[0]);
odm_set_bb_reg(dm, R_0x90c, 0xffffff, tmp);
tmp = BYTE_2_DWORD(0, tx_info->vht_sig_a[5],
tx_info->vht_sig_a[4],
tx_info->vht_sig_a[3]);
odm_set_bb_reg(dm, R_0x910, 0xffffff, tmp);
tmp = BYTE_2_DWORD(tx_info->vht_sig_b[3], tx_info->vht_sig_b[2],
tx_info->vht_sig_b[1],
tx_info->vht_sig_b[0]);
odm_set_bb_reg(dm, R_0x914, 0x1fffffff, tmp);
odm_set_bb_reg(dm, R_0x938, 0xff00, tx_info->vht_sig_b_crc);
tmp = BYTE_2_DWORD(tx_info->vht_delimiter[3],
tx_info->vht_delimiter[2],
tx_info->vht_delimiter[1],
tx_info->vht_delimiter[0]);
odm_set_bb_reg(dm, R_0x940, MASKDWORD, tmp);
}
}
void phydm_set_cck_preamble_hdr_jgr3(void *dm_void,
struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
u32 tmp = 0;
u8 rate = tx_info->tx_rate; /* HW rate */
if (!pmac_tx->is_cck_rate)
return;
if (dm->support_ic_type & ODM_RTL8723F) {
#if (RTL8723F_SUPPORT)
odm_set_bb_reg(dm, R_0x2a04, 0x03ff0000, tx_info->packet_count);
odm_set_bb_reg(dm, R_0x2a08, BIT(22), tx_info->service_field_bit2);
odm_set_bb_reg(dm, R_0x2a08, BIT(21) | BIT(20), rate);
odm_set_bb_reg(dm, R_0x2a08, 0x1ffff, tx_info->packet_length);
/* turn on scrambler */
odm_set_bb_reg(dm, R_0x2a04, BIT(5), 0x0);
if (tx_info->is_short_preamble)
odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x1);
else
odm_set_bb_reg(dm, R_0x2a08, BIT(19), 0x0);
#endif
} else {
tmp = tx_info->packet_count | (tx_info->sfd << 16);
odm_set_bb_reg(dm, R_0x1e64, MASKDWORD, tmp);
tmp = tx_info->signal_field | (tx_info->service_field << 8) |
(tx_info->length << 16);
odm_set_bb_reg(dm, R_0x1e68, MASKDWORD, tmp);
tmp = BYTE_2_DWORD(0, 0, tx_info->crc16[1], tx_info->crc16[0]);
odm_set_bb_reg(dm, R_0x1e6c, MASKLWORD, tmp);
if (tx_info->is_short_preamble)
odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x0);
else
odm_set_bb_reg(dm, R_0x1e6c, BIT(16), 0x1);
}
}
void phydm_set_mode_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum phydm_pmac_mode mode)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
if (mode == CONT_TX) {
tx_info->packet_count = 1;
if (pmac_tx->is_cck_rate)
phydm_start_cck_cont_tx_jgr3(dm, tx_info);
else
phydm_start_ofdm_cont_tx_jgr3(dm);
}
}
void phydm_set_pmac_txon_jgr3(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x1); /*Turn on PMAC */
if (dm->support_ic_type & ODM_RTL8723F) {
if (pmac_tx->is_cck_rate) {
if (tx_info->mode == CONT_TX) {
/* BB and PMAC cont tx */
odm_set_bb_reg(dm, R_0x2a08, BIT(17), 0x1);
odm_set_bb_reg(dm, R_0x2a00, BIT(28), 0x1);
}
/* TX CCK ON */
odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x0);
odm_set_bb_reg(dm, R_0x2a08, BIT(31), 0x1);
} else {
odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x0); /*TX Ofdm OFF */
odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
}
} else {
/*mac scramble seed setting, only in 8198F */
#if (RTL8198F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8198F)
if (!odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x1);
#endif
if (pmac_tx->is_cck_rate){
odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x8); /*TX CCK ON */
odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x0);
} else {
odm_set_bb_reg(dm, R_0x1e70, 0xf, 0x4); /*TX Ofdm ON */
}
}
}
void phydm_set_pmac_tx_jgr3(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_tx *pmac_tx = &dm->dm_pmac_tx_table;
pmac_tx->is_cck_rate = phydm_is_cck_rate(dm, tx_info->tx_rate);
pmac_tx->is_ofdm_rate = phydm_is_ofdm_rate(dm, tx_info->tx_rate);
pmac_tx->is_ht_rate = phydm_is_ht_rate(dm, tx_info->tx_rate);
pmac_tx->is_vht_rate = phydm_is_vht_rate(dm, tx_info->tx_rate);
pmac_tx->path = mpt_rf_path;
if (!tx_info->en_pmac_tx) {
phydm_stop_pmac_tx_jgr3(dm, tx_info);
return;
}
phydm_set_mode_jgr3(dm, tx_info, tx_info->mode);
if (pmac_tx->is_cck_rate)
phydm_set_cck_preamble_hdr_jgr3(dm, tx_info);
else
phydm_set_sig_jgr3(dm, tx_info);
phydm_set_mac_phy_txinfo_jgr3(dm, tx_info);
phydm_set_pmac_txon_jgr3(dm, tx_info);
}
void phydm_set_tmac_tx_jgr3(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/* Turn on TMAC */
if (odm_get_bb_reg(dm, R_0x1d08, BIT(0)))
odm_set_bb_reg(dm, R_0x1d08, BIT(0), 0x0);
/* mac scramble seed setting, only in 8198F */
#if (RTL8198F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8198F)
if (odm_get_bb_reg(dm, R_0x1d10, BIT(16)))
odm_set_bb_reg(dm, R_0x1d10, BIT(16), 0x0);
#endif
/* Turn on TMAC CCK */
if (!(dm->support_ic_type & ODM_RTL8723F)) {
if (!odm_get_bb_reg(dm, R_0x1a84, BIT(31)))
odm_set_bb_reg(dm, R_0x1a84, BIT(31), 0x1);
}
}
#endif
void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_start_cck_cont_tx_jgr3(dm, tx_info);
#endif
}
void phydm_stop_cck_cont_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_stop_cck_cont_tx_jgr3(dm);
#endif
}
void phydm_start_ofdm_cont_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_start_ofdm_cont_tx_jgr3(dm);
#endif
}
void phydm_stop_ofdm_cont_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_stop_ofdm_cont_tx_jgr3(dm);
#endif
}
void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_set_pmac_tx_jgr3(dm, tx_info, mpt_rf_path);
#endif
}
void phydm_set_tmac_tx(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
phydm_set_tmac_tx_jgr3(dm);
#endif
}
void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pmac_info tx_info;
char help[] = "-h";
char dbg_buf[PHYDM_SNPRINT_SIZE] = {0};
u32 var[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
u32 tx_cnt = 0x0;
u8 poll_cnt = 0x0;
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var[0]);
if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
return;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"[pmac_tx] basic : {1} {rate_idx}(only 1M & 6M) {count}\n");
} else {
for (i = 1; i < 7; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
&var[i]);
}
}
tx_info.en_pmac_tx = true;
tx_info.mode = PKTS_TX;
tx_info.ndp_sound = false;
tx_info.bw = CHANNEL_WIDTH_20;
tx_info.tx_sc = 0x0; /*duplicate*/
tx_info.m_stbc = 0x0; /*disable*/
tx_info.packet_period = 2000; /*d'500 us*/
tx_info.tx_rate = (u8)var[1];
tx_info.packet_count = (u32)var[2];
if (tx_info.tx_rate == ODM_RATE1M) {
tx_info.signal_field = 0xa; /*rate = 1M*/
tx_info.service_field = 0x0;
if (dm->support_ic_type & ODM_RTL8723F) {
tx_info.service_field_bit2= 0x1;
tx_info.packet_length = 1000; /*1000 bytes*/
}
tx_info.length = 8000; /*d'8000 us=1000 bytes*/
tx_info.crc16[0] = 0x60;
tx_info.crc16[1] = 0x8e;
/*long preamble*/
tx_info.is_short_preamble = false;
tx_info.sfd = 0xf3a0;
} else if (tx_info.tx_rate == ODM_RATE6M) {
/*l-sig[3:0] = rate = 6M = 0xb*/
/*l-sig[16:5] = length = 1000 bytes*/
/*l-sig[17] = parity = 1*/
tx_info.lsig[0] = 0xb;
tx_info.lsig[1] = 0x7d;
tx_info.lsig[2] = 0x2;
}
phydm_print_rate_2_buff(dm, tx_info.tx_rate, dbg_buf,
PHYDM_SNPRINT_SIZE);
PDM_SNPF(out_len, used, output + used, out_len - used,
"rate=%s, count=%d, pkt_interval=500(us), length=1000(bytes)\n",
dbg_buf, tx_info.packet_count);
if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"check trx idle failed, please try again.\n");
return;
}
phydm_reset_bb_hw_cnt(dm);
phydm_set_pmac_tx_jgr3(dm, &tx_info, RF_PATH_A);
PDM_SNPF(out_len, used, output + used, out_len - used,
"pmac_tx enabled, please wait for tx_cnt = %d\n",
tx_info.packet_count);
while (1) {
if (phydm_is_cck_rate(dm, tx_info.tx_rate))
tx_cnt = odm_get_bb_reg(dm, R_0x2de4,
MASKLWORD);
else
tx_cnt = odm_get_bb_reg(dm, R_0x2de0,
MASKLWORD);
if (tx_cnt >= tx_info.packet_count || poll_cnt >= 10)
break;
ODM_delay_ms(100);
poll_cnt++;
}
if (tx_cnt < tx_info.packet_count)
PDM_SNPF(out_len, used, output + used, out_len - used,
"polling time out(1s), tx_cnt = %d\n", tx_cnt);
else
PDM_SNPF(out_len, used, output + used, out_len - used,
"pmac_tx finished, poll_cnt = %d\n", poll_cnt);
tx_info.en_pmac_tx = false;
phydm_set_pmac_tx(dm, &tx_info, RF_PATH_A);
phydm_set_tmac_tx(dm);
PDM_SNPF(out_len, used, output + used, out_len - used,
"Stop pmac_tx and turn on true mac mode.\n");
phydm_stop_ic_trx(dm, PHYDM_REVERT);
}
*_used = used;
*_out_len = out_len;
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_PMAC_TX_SETTING_H__
#define __PHYDM_PMAC_TX_SETTING_H__
/*2020.03.16 Fix TxInfo content in B mode*/
#define PMAC_TX_SETTING_VERSION "2.1"
/* 1 ============================================================
* 1 Definition
* 1 ============================================================
*/
/* 1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct phydm_pmac_info {
u8 en_pmac_tx:1; /*0: disable pmac 1: enable pmac */
u8 mode:3; /*0: Packet TX 3:Continuous TX */
u8 tx_rate; /*should be HW rate*/
u8 tx_sc;
u8 is_short_preamble:1;
u8 ndp_sound:1;
u8 bw:3; /* 0:20 1:40 2:80Mhz */
u8 m_stbc; /* bSTBC + 1 for WIN/CE, bSTBC for others*/
u16 packet_period;
u32 packet_count;
u32 packet_length;
u8 packet_pattern;
u16 sfd;
u8 signal_field;
u8 service_field;
u8 service_field_bit2:1;
u16 length;
u8 crc16[2];
u8 lsig[3];
u8 ht_sig[6];
u8 vht_sig_a[6];
u8 vht_sig_b[4];
u8 vht_sig_b_crc;
u8 vht_delimiter[4];
};
struct phydm_pmac_tx {
boolean is_cck_rate;
boolean is_ofdm_rate;
boolean is_ht_rate;
boolean is_vht_rate;
boolean cck_cont_tx;
boolean ofdm_cont_tx;
u8 path;
};
/* 1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
enum phydm_pmac_mode {
NONE_TEST,
PKTS_TX,
PKTS_RX,
CONT_TX,
OFDM_SINGLE_TONE_TX,
CCK_CARRIER_SIPPRESSION_TX
};
/* 1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_start_cck_cont_tx(void *dm_void, struct phydm_pmac_info *tx_info);
void phydm_stop_cck_cont_tx(void *dm_void);
void phydm_start_ofdm_cont_tx(void *dm_void);
void phydm_stop_ofdm_cont_tx(void *dm_void);
void phydm_set_pmac_tx(void *dm_void, struct phydm_pmac_info *tx_info,
enum rf_path mpt_rf_path);
void phydm_set_tmac_tx(void *dm_void);
void phydm_pmac_tx_dbg(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_POWER_TRAINING_SUPPORT
void phydm_reset_pt_para(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
pt_t->pow_train_score = 0;
}
void phydm_update_power_training_state(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
struct phydm_fa_struct *fa_cnt = &dm->false_alm_cnt;
struct ccx_info *ccx = &dm->dm_ccx_info;
u32 pt_score_tmp = ENABLE_PT_SCORE;
u32 crc_ok_cnt = 0;
u32 cca_cnt = 0;
/*@is_disable_power_training is the key to H2C to disable/enable PT*/
/*@if is_disable_power_training == 1, it will use largest power*/
if (!(dm->support_ability & ODM_BB_PWR_TRAIN) || !dm->is_linked) {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
return;
}
PHYDM_DBG(dm, DBG_PWR_TRAIN, "%s ======>\n", __func__);
if (pt_t->pt_state == DISABLE_POW_TRAIN) {
dm->is_disable_power_training = true;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Disable PT\n");
return;
} else if (pt_t->pt_state == ENABLE_POW_TRAIN) {
dm->is_disable_power_training = false;
phydm_reset_pt_para(dm);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Enable PT\n");
return;
} else if (pt_t->pt_state == DYNAMIC_POW_TRAIN) {
PHYDM_DBG(dm, DBG_PWR_TRAIN, "Dynamic PT\n");
/* @Compute score */
crc_ok_cnt = dm->phy_dbg_info.num_qry_phy_status_ofdm +
dm->phy_dbg_info.num_qry_phy_status_cck;
cca_cnt = fa_cnt->cnt_cca_all;
#if 0
if (crc_ok_cnt > cca_cnt) { /*invalid situation*/
pt_score_tmp = KEEP_PRE_PT_SCORE;
return;
} else if ((crc_ok_cnt + (crc_ok_cnt >> 1)) <= cca_cnt) {
/* @???crc_ok <= (2/3)*cca */
pt_score_tmp = DISABLE_PT_SCORE;
dm->is_disable_power_training = true;
} else if ((crc_ok_cnt + (crc_ok_cnt >> 2)) <= cca_cnt) {
/* @???crc_ok <= (4/5)*cca */
pt_score_tmp = KEEP_PRE_PT_SCORE;
} else {
/* @???crc_ok > (4/5)*cca */
pt_score_tmp = ENABLE_PT_SCORE;
dm->is_disable_power_training = false;
}
#endif
if (ccx->nhm_ratio > 10) {
pt_score_tmp = DISABLE_PT_SCORE;
dm->is_disable_power_training = true;
} else if (ccx->nhm_ratio < 5) {
pt_score_tmp = ENABLE_PT_SCORE;
dm->is_disable_power_training = false;
} else {
pt_score_tmp = KEEP_PRE_PT_SCORE;
}
PHYDM_DBG(dm, DBG_PWR_TRAIN,
"pkt_cnt{ofdm,cck,all} = {%d, %d, %d}, cnt_cca_all=%d\n",
dm->phy_dbg_info.num_qry_phy_status_ofdm,
dm->phy_dbg_info.num_qry_phy_status_cck,
crc_ok_cnt, cca_cnt);
PHYDM_DBG(dm, DBG_PWR_TRAIN, "pt_score_tmp=%d\n", pt_score_tmp);
/* smoothing */
pt_t->pow_train_score = (pt_score_tmp << 4) +
(pt_t->pow_train_score >> 1) +
(pt_t->pow_train_score >> 2);
pt_score_tmp = (pt_t->pow_train_score + 32) >> 6;
PHYDM_DBG(dm, DBG_PWR_TRAIN,
"pow_train_score = %d, score after smoothing = %d, is_disable_PT = %d\n",
pt_t->pow_train_score, pt_score_tmp,
dm->is_disable_power_training);
} else {
PHYDM_DBG(dm, DBG_PWR_TRAIN, "[%s]warning\n", __func__);
}
}
void phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pow_train_stuc *pt_t = &dm->pow_train_table;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u32 i;
if ((strcmp(input[1], help) == 0)) {
PDM_SNPF(out_len, used, output + used, out_len - used,
"{0: Auto PT, 1:enable, 2: disable}\n");
} else {
for (i = 0; i < 10; i++) {
if (input[i + 1])
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
}
if (var1[0] == 0)
pt_t->pt_state = DYNAMIC_POW_TRAIN;
else if (var1[0] == 1)
pt_t->pt_state = ENABLE_POW_TRAIN;
else if (var1[0] == 2)
pt_t->pt_state = DISABLE_POW_TRAIN;
PDM_SNPF(out_len, used, output + used, out_len - used,
"PT state = %d\n", pt_t->pt_state);
}
*_used = used;
*_out_len = out_len;
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_POW_TRAIN_H__
#define __PHYDM_POW_TRAIN_H__
#define POW_TRAIN_VERSION "1.0" /* @2017.07.0141 Dino, Add phydm_pow_train.h*/
/****************************************************************
* 1 ============================================================
* 1 Definition
* 1 ============================================================
***************************************************************/
#ifdef PHYDM_POWER_TRAINING_SUPPORT
/****************************************************************
* 1 ============================================================
* 1 structure
* 1 ============================================================
***************************************************************/
struct phydm_pow_train_stuc {
u8 pt_state;
u32 pow_train_score;
};
/****************************************************************
* 1 ============================================================
* 1 enumeration
* 1 ============================================================
***************************************************************/
enum pow_train_state {
DYNAMIC_POW_TRAIN = 0,
ENABLE_POW_TRAIN = 1,
DISABLE_POW_TRAIN = 2
};
enum power_training_score {
DISABLE_PT_SCORE = 0,
KEEP_PRE_PT_SCORE = 1,
ENABLE_PT_SCORE = 2
};
/****************************************************************
* 1 ============================================================
* 1 function prototype
* 1 ============================================================
***************************************************************/
void phydm_update_power_training_state(
void *dm_void);
void phydm_pow_train_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len);
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "phydm_types.h"
#include "halrf/halrf_features.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Precomp.h" /* @We need to include mp_precomp.h due to batch file setting. */
#else
#define TEST_FALG___ 1
#endif
/* @2 Config Flags and Structs - defined by each ODM type */
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#include "../8192cd_hw.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
#define INIT_TIMER_EVENT_ENTRY(_entry, _func, _data) \
do { \
_rtw_init_listhead(&(_entry)->list); \
(_entry)->data = (_data); \
(_entry)->function = (_func); \
} while (0)
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
#include "../wifi.h"
#include "rtl_phydm.h"
#elif defined(DM_ODM_CE_MAC80211_V2)
#include "../main.h"
#include "../hw.h"
#include "../fw.h"
#endif
#define __PACK
#define __WLAN_ATTRIB_PACK__
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "mp_precomp.h"
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#define __PACK
#define __WLAN_ATTRIB_PACK__
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#include <drv_types.h>
#include <wifi.h>
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#define __PACK
#endif
/* @2 OutSrc Header Files */
#include "phydm.h"
#include "phydm_hwconfig.h"
#include "phydm_phystatus.h"
#include "phydm_debug.h"
#include "phydm_regdefine11ac.h"
#include "phydm_regdefine11n.h"
#include "phydm_interface.h"
#include "phydm_reg.h"
#include "halrf/halrf_debug.h"
#ifndef RTL8188E_SUPPORT
#define RTL8188E_SUPPORT 0
#endif
#ifndef RTL8812A_SUPPORT
#define RTL8812A_SUPPORT 0
#endif
#ifndef RTL8821A_SUPPORT
#define RTL8821A_SUPPORT 0
#endif
#ifndef RTL8192E_SUPPORT
#define RTL8192E_SUPPORT 0
#endif
#ifndef RTL8723B_SUPPORT
#define RTL8723B_SUPPORT 0
#endif
#ifndef RTL8814A_SUPPORT
#define RTL8814A_SUPPORT 0
#endif
#ifndef RTL8881A_SUPPORT
#define RTL8881A_SUPPORT 0
#endif
#ifndef RTL8822B_SUPPORT
#define RTL8822B_SUPPORT 0
#endif
#ifndef RTL8703B_SUPPORT
#define RTL8703B_SUPPORT 0
#endif
#ifndef RTL8195A_SUPPORT
#define RTL8195A_SUPPORT 0
#endif
#ifndef RTL8188F_SUPPORT
#define RTL8188F_SUPPORT 0
#endif
#ifndef RTL8723D_SUPPORT
#define RTL8723D_SUPPORT 0
#endif
#ifndef RTL8197F_SUPPORT
#define RTL8197F_SUPPORT 0
#endif
#ifndef RTL8821C_SUPPORT
#define RTL8821C_SUPPORT 0
#endif
#ifndef RTL8814B_SUPPORT
#define RTL8814B_SUPPORT 0
#endif
#ifndef RTL8198F_SUPPORT
#define RTL8198F_SUPPORT 0
#endif
#ifndef RTL8710B_SUPPORT
#define RTL8710B_SUPPORT 0
#endif
#ifndef RTL8192F_SUPPORT
#define RTL8192F_SUPPORT 0
#endif
#ifndef RTL8822C_SUPPORT
#define RTL8822C_SUPPORT 0
#endif
#ifndef RTL8195B_SUPPORT
#define RTL8195B_SUPPORT 0
#endif
#ifndef RTL8812F_SUPPORT
#define RTL8812F_SUPPORT 0
#endif
#ifndef RTL8197G_SUPPORT
#define RTL8197G_SUPPORT 0
#endif
#ifndef RTL8721D_SUPPORT
#define RTL8721D_SUPPORT 0
#endif
#ifndef RTL8710C_SUPPORT
#define RTL8710C_SUPPORT 0
#endif
#ifndef RTL8723F_SUPPORT
#define RTL8723F_SUPPORT 0
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_CE) && \
(!defined(DM_ODM_CE_MAC80211) && !defined(DM_ODM_CE_MAC80211_V2))
void phy_set_tx_power_limit(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit);
void phy_set_tx_power_limit_ex(struct dm_struct *dm, u8 regulation, u8 band,
u8 bandwidth, u8 rate_section, u8 rf_path,
u8 channel, s8 power_limit);
enum hal_status
rtw_phydm_fw_iqk(
struct dm_struct *dm,
u8 clear,
u8 segment);
enum hal_status
rtw_phydm_fw_dpk(
struct dm_struct *dm);
enum hal_status
rtw_phydm_cfg_phy_para(
struct dm_struct *dm,
enum phydm_halmac_param config_type,
u32 offset,
u32 data,
u32 mask,
enum rf_path e_rf_path,
u32 delay_time);
#endif
#if RTL8188E_SUPPORT == 1
#define RTL8188E_T_SUPPORT 1
#ifdef CONFIG_SFW_SUPPORTED
#define RTL8188E_S_SUPPORT 1
#else
#define RTL8188E_S_SUPPORT 0
#endif
#include "rtl8188e/hal8188erateadaptive.h" /* @for RA,Power training */
#include "rtl8188e/halhwimg8188e_mac.h"
#include "rtl8188e/halhwimg8188e_rf.h"
#include "rtl8188e/halhwimg8188e_bb.h"
#include "rtl8188e/phydm_regconfig8188e.h"
#include "rtl8188e/phydm_rtl8188e.h"
#include "rtl8188e/hal8188ereg.h"
#include "rtl8188e/version_rtl8188e.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8188e_hal.h"
#include "halrf/rtl8188e/halrf_8188e_ce.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8188e/halrf_8188e_win.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8188e/halrf_8188e_ap.h"
#endif
#endif /* @88E END */
#if (RTL8192E_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8192e/halrf_8192e_win.h" /*@FOR_8192E_IQK*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8192e/halrf_8192e_ap.h" /*@FOR_8192E_IQK*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8192e/halrf_8192e_ce.h" /*@FOR_8192E_IQK*/
#endif
#include "rtl8192e/phydm_rtl8192e.h" /* @FOR_8192E_IQK */
#include "rtl8192e/version_rtl8192e.h"
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8192e/halhwimg8192e_bb.h"
#include "rtl8192e/halhwimg8192e_mac.h"
#include "rtl8192e/halhwimg8192e_rf.h"
#include "rtl8192e/phydm_regconfig8192e.h"
#include "rtl8192e/hal8192ereg.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8192e_hal.h"
#endif
#endif /* @92E END */
#if (RTL8812A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8812a/halrf_8812a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8812a/halrf_8812a_ap.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8812a/halrf_8812a_ce.h"
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8812a/halhwimg8812a_bb.h"
#include "rtl8812a/halhwimg8812a_mac.h"
#include "rtl8812a/halhwimg8812a_rf.h"
#include "rtl8812a/phydm_regconfig8812a.h"
#endif
#include "rtl8812a/phydm_rtl8812a.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8812a_hal.h"
#endif
#include "rtl8812a/version_rtl8812a.h"
#endif /* @8812 END */
#if (RTL8814A_SUPPORT == 1)
#include "rtl8814a/halhwimg8814a_mac.h"
#include "rtl8814a/halhwimg8814a_bb.h"
#include "rtl8814a/version_rtl8814a.h"
#include "rtl8814a/phydm_rtl8814a.h"
#include "halrf/rtl8814a/halhwimg8814a_rf.h"
#include "halrf/rtl8814a/version_rtl8814a_rf.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8814a/halrf_8814a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8814a/halrf_8814a_ce.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8814a/halrf_8814a_ap.h"
#endif
#include "rtl8814a/phydm_regconfig8814a.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8814a_hal.h"
#include "halrf/rtl8814a/halrf_iqk_8814a.h"
#endif
#endif /* @8814 END */
#if (RTL8881A_SUPPORT == 1)/* @FOR_8881_IQK */
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8821a/halrf_iqk_8821a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"
#else
#include "halrf/rtl8821a/halrf_iqk_8821a_ap.h"
#endif
#endif
#if (RTL8723B_SUPPORT == 1)
#include "rtl8723b/halhwimg8723b_mac.h"
#include "rtl8723b/halhwimg8723b_rf.h"
#include "rtl8723b/halhwimg8723b_bb.h"
#include "rtl8723b/phydm_regconfig8723b.h"
#include "rtl8723b/phydm_rtl8723b.h"
#include "rtl8723b/hal8723breg.h"
#include "rtl8723b/version_rtl8723b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8723b/halrf_8723b_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8723b/halrf_8723b_ce.h"
#include "rtl8723b/halhwimg8723b_mp.h"
#include "rtl8723b_hal.h"
#else
#include "halrf/rtl8723b/halrf_8723b_ap.h"
#endif
#endif
#if (RTL8821A_SUPPORT == 1)
#include "rtl8821a/halhwimg8821a_mac.h"
#include "rtl8821a/halhwimg8821a_rf.h"
#include "rtl8821a/halhwimg8821a_bb.h"
#include "rtl8821a/phydm_regconfig8821a.h"
#include "rtl8821a/phydm_rtl8821a.h"
#include "rtl8821a/version_rtl8821a.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "halrf/rtl8821a/halrf_8821a_win.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "halrf/rtl8821a/halrf_8821a_ce.h"
#include "halrf/rtl8821a/halrf_iqk_8821a_ce.h"/*@for IQK*/
#include "halrf/rtl8812a/halrf_8812a_ce.h"/*@for IQK,LCK,Power-tracking*/
#include "rtl8812a_hal.h"
#else
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#include "../halmac/halmac_reg2.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
#include "../halmac/halmac_reg2.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "rtl8822b/halhwimg8822b_mac.h"
#include "rtl8822b/halhwimg8822b_bb.h"
#include "rtl8822b/phydm_regconfig8822b.h"
#include "halrf/rtl8822b/halrf_8822b.h"
#include "halrf/rtl8822b/halhwimg8822b_rf.h"
#include "halrf/rtl8822b/version_rtl8822b_rf.h"
#include "rtl8822b/phydm_rtl8822b.h"
#include "rtl8822b/phydm_hal_api8822b.h"
#include "rtl8822b/version_rtl8822b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
#include "../halmac/halmac_reg_8822b.h"
#elif defined(DM_ODM_CE_MAC80211_V2)
#include "../halmac/halmac_reg_8822b.h"
#else
#include <hal_data.h> /* @struct HAL_DATA_TYPE */
#include <rtl8822b_hal.h> /* @RX_SMOOTH_FACTOR, reg definition and etc.*/
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#endif
#endif
#if (RTL8703B_SUPPORT == 1)
#include "rtl8703b/phydm_rtl8703b.h"
#include "rtl8703b/phydm_regconfig8703b.h"
#include "rtl8703b/halhwimg8703b_mac.h"
#include "rtl8703b/halhwimg8703b_rf.h"
#include "rtl8703b/halhwimg8703b_bb.h"
#include "halrf/rtl8703b/halrf_8703b.h"
#include "rtl8703b/version_rtl8703b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8703b_hal.h"
#endif
#endif
#if (RTL8188F_SUPPORT == 1)
#include "rtl8188f/halhwimg8188f_mac.h"
#include "rtl8188f/halhwimg8188f_rf.h"
#include "rtl8188f/halhwimg8188f_bb.h"
#include "rtl8188f/hal8188freg.h"
#include "rtl8188f/phydm_rtl8188f.h"
#include "rtl8188f/phydm_regconfig8188f.h"
#include "halrf/rtl8188f/halrf_8188f.h" /*@for IQK,LCK,Power-tracking*/
#include "rtl8188f/version_rtl8188f.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8188f_hal.h"
#endif
#endif
#if (RTL8723D_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8723d/halhwimg8723d_bb.h"
#include "rtl8723d/halhwimg8723d_mac.h"
#include "rtl8723d/halhwimg8723d_rf.h"
#include "rtl8723d/phydm_regconfig8723d.h"
#include "rtl8723d/hal8723dreg.h"
#include "rtl8723d/phydm_rtl8723d.h"
#include "halrf/rtl8723d/halrf_8723d.h"
#include "rtl8723d/version_rtl8723d.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
#else
#include "rtl8723d_hal.h"
#endif
#endif
#endif /* @8723D End */
#if (RTL8710B_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8710b/halhwimg8710b_bb.h"
#include "rtl8710b/halhwimg8710b_mac.h"
#include "rtl8710b/phydm_regconfig8710b.h"
#include "rtl8710b/hal8710breg.h"
#include "rtl8710b/phydm_rtl8710b.h"
#include "halrf/rtl8710b/halrf_8710b.h"
#include "halrf/rtl8710b/halhwimg8710b_rf.h"
#include "halrf/rtl8710b/version_rtl8710b_rf.h"
#include "rtl8710b/version_rtl8710b.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8710b_hal.h"
#endif
#endif /* @8710B End */
#if (RTL8197F_SUPPORT == 1)
#include "rtl8197f/halhwimg8197f_mac.h"
#include "rtl8197f/halhwimg8197f_bb.h"
#include "rtl8197f/phydm_hal_api8197f.h"
#include "rtl8197f/version_rtl8197f.h"
#include "rtl8197f/phydm_rtl8197f.h"
#include "rtl8197f/phydm_regconfig8197f.h"
#include "halrf/rtl8197f/halrf_8197f.h"
#include "halrf/rtl8197f/halrf_iqk_8197f.h"
#include "halrf/rtl8197f/halrf_dpk_8197f.h"
#include "halrf/rtl8197f/halhwimg8197f_rf.h"
#include "halrf/rtl8197f/version_rtl8197f_rf.h"
#endif
#if (RTL8821C_SUPPORT == 1)
#include "rtl8821c/phydm_hal_api8821c.h"
#include "rtl8821c/halhwimg8821c_mac.h"
#include "rtl8821c/halhwimg8821c_bb.h"
#include "rtl8821c/phydm_regconfig8821c.h"
#include "rtl8821c/phydm_rtl8821c.h"
#include "halrf/rtl8821c/halrf_8821c.h"
#include "halrf/rtl8821c/halhwimg8821c_rf.h"
#include "halrf/rtl8821c/version_rtl8821c_rf.h"
#include "rtl8821c/version_rtl8821c.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#ifdef DM_ODM_CE_MAC80211
#include "../halmac/halmac_reg_8821c.h"
#else
#include "rtl8821c_hal.h"
#endif
#endif
#endif
#if (RTL8192F_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8192f_hal.h"/*need to before rf.h*/
#endif
#include "rtl8192f/halhwimg8192f_mac.h"
#include "rtl8192f/halhwimg8192f_bb.h"
#include "rtl8192f/phydm_hal_api8192f.h"
#include "rtl8192f/version_rtl8192f.h"
#include "rtl8192f/phydm_rtl8192f.h"
#include "rtl8192f/phydm_regconfig8192f.h"
#include "halrf/rtl8192f/halrf_8192f.h"
#include "halrf/rtl8192f/halhwimg8192f_rf.h"
#include "halrf/rtl8192f/version_rtl8192f_rf.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8192f/halrf_dpk_8192f.h"
#endif
#endif
#if (RTL8721D_SUPPORT == 1)
#include "halrf/rtl8721d/halrf_btiqk_8721d.h"
#include "halrf/rtl8721d/halrf_rfk_init_8721d.h"
#include "halrf/rtl8721d/halrf_dpk_8721d.h"
#include "halrf/rtl8721d/halrf_8721d.h"
#include "halrf/rtl8721d/halhwimg8721d_rf.h"
#include "halrf/rtl8721d/version_rtl8721d_rf.h"
#include "rtl8721d/phydm_hal_api8721d.h"
#include "rtl8721d/phydm_regconfig8721d.h"
#include "rtl8721d/halhwimg8721d_mac.h"
#include "rtl8721d/halhwimg8721d_bb.h"
#include "rtl8721d/version_rtl8721d.h"
#include "rtl8721d/phydm_rtl8721d.h"
#include "rtl8721d/hal8721dreg.h"
#include <hal_data.h>
#if 0
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8721d_hal.h"
#endif
#endif
#endif
#if (RTL8710C_SUPPORT == 1)
#include "halrf/rtl8710c/halrf_8710c.h"
#include "halrf/rtl8710c/halhwimg8710c_rf.h"
//#include "halrf/rtl8710c/version_rtl8710c_rf.h"
#include "rtl8710c/phydm_hal_api8710c.h"
#include "rtl8710c/phydm_regconfig8710c.h"
#include "rtl8710c/halhwimg8710c_mac.h"
#include "rtl8710c/halhwimg8710c_bb.h"
#include "rtl8710c/version_rtl8710c.h"
#include "rtl8710c/phydm_rtl8710c.h"
//#include "rtl8710c/hal87100creg.h"
#include <hal_data.h> /*@HAL_DATA_TYPE*/
#if 0
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "halrf/rtl8710c/halrf_dpk_8710c.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8710c_hal.h"
#endif
#endif
#endif
#if (RTL8195B_SUPPORT == 1)
#include "halrf/rtl8195b/halrf_8195b.h"
#include "halrf/rtl8195b/halhwimg8195b_rf.h"
#include "halrf/rtl8195b/version_rtl8195b_rf.h"
#include "rtl8195b/phydm_hal_api8195b.h"
#include "rtl8195b/phydm_regconfig8195b.h"
#include "rtl8195b/halhwimg8195b_mac.h"
#include "rtl8195b/halhwimg8195b_bb.h"
#include "rtl8195b/version_rtl8195b.h"
#include <hal_data.h> /*@HAL_DATA_TYPE*/
#endif
#if (RTL8198F_SUPPORT == 1)
#include "rtl8198f/phydm_regconfig8198f.h"
#include "rtl8198f/phydm_hal_api8198f.h"
#include "rtl8198f/halhwimg8198f_mac.h"
#include "rtl8198f/halhwimg8198f_bb.h"
#include "rtl8198f/version_rtl8198f.h"
#include "halrf/rtl8198f/halrf_8198f.h"
#include "halrf/rtl8198f/halrf_iqk_8198f.h"
#include "halrf/rtl8198f/halhwimg8198f_rf.h"
#include "halrf/rtl8198f/version_rtl8198f_rf.h"
#endif
#if (RTL8822C_SUPPORT)
#include "rtl8822c/halhwimg8822c_bb.h"
#include "rtl8822c/phydm_regconfig8822c.h"
#include "rtl8822c/phydm_hal_api8822c.h"
#include "rtl8822c/version_rtl8822c.h"
#include "rtl8822c/phydm_rtl8822c.h"
#include "halrf/rtl8822c/halrf_8822c.h"
#include "halrf/rtl8822c/halhwimg8822c_rf.h"
#include "halrf/rtl8822c/version_rtl8822c_rf.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
/* @struct HAL_DATA_TYPE */
#include <hal_data.h>
/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
#include <rtl8822c_hal.h>
#endif
#endif
#if (RTL8814B_SUPPORT == 1)
#include "rtl8814b/halhwimg8814b_bb.h"
#include "rtl8814b/phydm_regconfig8814b.h"
#include "halrf/rtl8814b/halrf_8814b.h"
#include "halrf/rtl8814b/halhwimg8814b_rf.h"
#include "halrf/rtl8814b/version_rtl8814b_rf.h"
#include "rtl8814b/phydm_hal_api8814b.h"
#include "rtl8814b/version_rtl8814b.h"
#include "rtl8814b/phydm_extraagc8814b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <hal_data.h> /* @struct HAL_DATA_TYPE */
#include <rtl8814b_hal.h> /* @RX_SMOOTH_FACTOR, reg definition and etc.*/
#endif
#endif
#if (RTL8812F_SUPPORT)
#include "rtl8812f/halhwimg8812f_bb.h"
#include "rtl8812f/phydm_regconfig8812f.h"
#include "halrf/rtl8812f/halrf_8812f.h"
#include "halrf/rtl8812f/halhwimg8812f_rf.h"
#include "halrf/rtl8812f/version_rtl8812f_rf.h"
#include "rtl8812f/phydm_hal_api8812f.h"
#include "rtl8812f/version_rtl8812f.h"
#include "rtl8812f/phydm_rtl8812f.h"
#endif
#if (RTL8197G_SUPPORT)
#include "rtl8197g/halhwimg8197g_bb.h"
#include "rtl8197g/halhwimg8197g_mac.h"
#include "rtl8197g/phydm_regconfig8197g.h"
#include "halrf/rtl8197g/halrf_8197g.h"
#include "halrf/rtl8197g/halhwimg8197g_rf.h"
#include "halrf/rtl8197g/version_rtl8197g_rf.h"
#include "rtl8197g/phydm_hal_api8197g.h"
#include "rtl8197g/version_rtl8197g.h"
#include "rtl8197g/phydm_rtl8197g.h"
#endif
#if (RTL8723F_SUPPORT)
#include "rtl8723f/halhwimg8723f_bb.h"
#include "rtl8723f/halhwimg8723f_mac.h"
#include "rtl8723f/phydm_regconfig8723f.h"
#include "halrf/rtl8723f/halrf_8723f.h"
#include "halrf/rtl8723f/halhwimg8723f_rf.h"
#include "halrf/rtl8723f/version_rtl8723f_rf.h"
#include "halrf/rtl8723f/halrf_iqk_8723f.h"
#include "halrf/rtl8723f/halrf_dpk_8723f.h"
#include "halrf/rtl8723f/halrf_txgapk_8723f.h"
#include "halrf/rtl8723f/halrf_tssi_8723f.h"
#include "halrf/rtl8723f/halrf_rfk_init_8723f.h"
#include "rtl8723f/phydm_hal_api8723f.h"
#include "rtl8723f/version_rtl8723f.h"
#include "rtl8723f/phydm_rtl8723f.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
/* @struct HAL_DATA_TYPE */
#include <hal_data.h>
/* @RX_SMOOTH_FACTOR, reg definition and etc.*/
#include <rtl8723f_hal.h>
#endif
#endif
#endif /* @__ODM_PRECOMP_H__ */

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_PRIMARY_CCA
void phydm_write_dynamic_cca(
void *dm_void,
u8 curr_mf_state
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
if (pri_cca->mf_state == curr_mf_state)
return;
if (dm->support_ic_type & ODM_IC_11N_SERIES) {
if (curr_mf_state == MF_USC_LSC) {
odm_set_bb_reg(dm, R_0xc6c, 0x180, MF_USC_LSC);
/*@40M OFDM MF CCA threshold*/
odm_set_bb_reg(dm, R_0xc84, 0xf0000000,
pri_cca->cca_th_40m_bkp);
} else {
odm_set_bb_reg(dm, R_0xc6c, 0x180, curr_mf_state);
/*@40M OFDM MF CCA threshold*/
odm_set_bb_reg(dm, R_0xc84, 0xf0000000, 0);
}
}
pri_cca->mf_state = curr_mf_state;
PHYDM_DBG(dm, DBG_PRI_CCA, "Set CCA at ((%s SB)), 0xc6c[8:7]=((%d))\n",
((curr_mf_state == MF_USC_LSC) ? "D" :
((curr_mf_state == MF_LSC) ? "L" : "U")), curr_mf_state);
}
void phydm_primary_cca_reset(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Reset\n");
pri_cca->mf_state = 0xff;
pri_cca->pre_bw = (enum channel_width)0xff;
phydm_write_dynamic_cca(dm, MF_USC_LSC);
}
void phydm_primary_cca_11n(
void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
enum channel_width curr_bw = (enum channel_width)*dm->band_width;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
if (!dm->is_linked) {
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][No Link!!!]\n");
if (pri_cca->pri_cca_is_become_linked) {
phydm_primary_cca_reset(dm);
pri_cca->pri_cca_is_become_linked = dm->is_linked;
}
return;
} else {
if (!pri_cca->pri_cca_is_become_linked) {
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA][Linked !!!]\n");
pri_cca->pri_cca_is_become_linked = dm->is_linked;
}
}
if (curr_bw != pri_cca->pre_bw) {
PHYDM_DBG(dm, DBG_PRI_CCA, "[Primary CCA] start ==>\n");
pri_cca->pre_bw = curr_bw;
if (curr_bw == CHANNEL_WIDTH_40) {
if (*dm->sec_ch_offset == SECOND_CH_AT_LSB) {
/* Primary CH @ upper sideband*/
PHYDM_DBG(dm, DBG_PRI_CCA,
"BW40M, Primary CH at USB\n");
phydm_write_dynamic_cca(dm, MF_USC);
} else {
/*Primary CH @ lower sideband*/
PHYDM_DBG(dm, DBG_PRI_CCA,
"BW40M, Primary CH at LSB\n");
phydm_write_dynamic_cca(dm, MF_LSC);
}
} else {
PHYDM_DBG(dm, DBG_PRI_CCA, "Not BW40M, USB + LSB\n");
phydm_primary_cca_reset(dm);
}
}
}
boolean
odm_dynamic_primary_cca_dup_rts(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
return pri_cca->dup_rts_flag;
}
void phydm_primary_cca_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct phydm_pricca_struct *pri_cca = &dm->dm_pri_cca;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
return;
PHYDM_DBG(dm, DBG_PRI_CCA, "[PriCCA] Init ==>\n");
#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
pri_cca->dup_rts_flag = 0;
pri_cca->intf_flag = 0;
pri_cca->intf_type = 0;
pri_cca->monitor_flag = 0;
pri_cca->pri_cca_flag = 0;
pri_cca->ch_offset = 0;
#endif
pri_cca->mf_state = 0xff;
pri_cca->pre_bw = (enum channel_width)0xff;
pri_cca->cca_th_40m_bkp = (u8)odm_get_bb_reg(dm, R_0xc84, 0xf0000000);
}
void phydm_primary_cca(void *dm_void)
{
#ifdef PHYDM_PRIMARY_CCA
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
return;
if (!(dm->support_ability & ODM_BB_PRIMARY_CCA))
return;
phydm_primary_cca_11n(dm);
#endif
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_PRIMARYCCA_H__
#define __PHYDM_PRIMARYCCA_H__
#ifdef PHYDM_PRIMARY_CCA
#define PRIMARYCCA_VERSION "2.0"
/*@============================================================*/
/*@Definition */
/*@============================================================*/
#define OFDMCCA_TH 500
#define bw_ind_bias 500
#define PRI_CCA_MONITOR_TIME 30
/*@============================================================*/
/*structure and define*/
/*@============================================================*/
enum primary_cca_ch_position { /*N-series REG0xc6c[8:7]*/
MF_USC_LSC = 0,
MF_LSC = 1,
MF_USC = 2
};
struct phydm_pricca_struct {
#if (RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1)
u8 pri_cca_flag;
u8 intf_flag;
u8 intf_type;
u8 monitor_flag;
u8 ch_offset;
#endif
u8 dup_rts_flag;
u8 cca_th_40m_bkp; /*@c84[31:28]*/
enum channel_width pre_bw;
u8 pri_cca_is_become_linked;
u8 mf_state;
};
/*@============================================================*/
/*@function prototype*/
/*@============================================================*/
void phydm_write_dynamic_cca(void *dm_void, u8 curr_mf_state);
boolean odm_dynamic_primary_cca_dup_rts(void *dm_void);
void phydm_primary_cca_init(void *dm_void);
void phydm_primary_cca(void *dm_void);
#endif /*@#ifdef PHYDM_PRIMARY_CCA*/
#endif /*@#ifndef __PHYDM_PRIMARYCCA_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/******************************************************************************
* include files
*****************************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef CONFIG_PSD_TOOL
u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u32 psd_report = 0;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
#if(RTL8723F_SUPPORT)
if (dm->support_ic_type & (ODM_RTL8723F)) {
odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff80000, psd_tone_idx & 0x7ff);
/*PSD trigger start*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 1);
ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
/*PSD trigger stop*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(16), 0);
}
#endif
#if 0
odm_set_bb_reg(dm, R_0x1e8c, 0x3ff, psd_tone_idx & 0x3ff);
odm_set_bb_reg(dm, R_0x1e88, BIT(27) | BIT(26),
psd_tone_idx >> 10);
/*PSD trigger start*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 1);
ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
/*PSD trigger stop*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(18), 0);
#endif
} else if (dm->support_ic_type & (ODM_RTL8721D |
ODM_RTL8710C)) {
odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0xfff, psd_tone_idx);
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 1);
/*PSD trigger start*/
ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(28), 0);
/*PSD trigger stop*/
} else {
odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
/*PSD trigger start*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 1);
ODM_delay_us(10 << (dm_psd_table->fft_smp_point >> 7));
/*PSD trigger stop*/
odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22), 0);
}
/*Get PSD Report*/
if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8721D |
ODM_RTL8710C)) {
psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
0xffffff);
psd_report = psd_report >> 5;
} else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
#if(RTL8723F_SUPPORT)
if (dm->support_ic_type & (ODM_RTL8723F)) {
psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
0x1ffffff);
}
#endif
#if 0
psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
0xffffff);
#endif
} else {
psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg,
0xffff);
}
psd_report = odm_convert_to_db((u64)psd_report) + igi;
return psd_report;
}
u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u32 i = 0, mod_tone_idx = 0;
u32 t = 0;
u16 fft_max_half_bw = 0;
u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
u8 ag_rf_mode_reg = 0;
u8 is_5G = 0;
u32 psd_result_tmp = 0;
u8 psd_result = 0;
u8 psd_result_cali_tone[7] = {0};
u8 psd_result_cali_val[7] = {0};
u8 noise_idx = 0;
u8 set_result = 0;
u32 igi_tmp = 0x6e;
if (dm->support_ic_type == ODM_RTL8821) {
odm_move_memory(dm, psd_result_cali_tone,
psd_result_cali_tone_8821, 7);
odm_move_memory(dm, psd_result_cali_val,
psd_result_cali_val_8821, 7);
}
dm_psd_table->psd_in_progress = 1;
PHYDM_DBG(dm, ODM_COMP_API, "PSD Start =>\n");
/* @[Stop DIG]*/
/* @IGI target at 0dBm & make it can't CCA*/
if (phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_3, 1,
&igi_tmp) == PAUSE_FAIL) {
return PHYDM_SET_FAIL;
}
ODM_delay_us(10);
if (phydm_stop_ic_trx(dm, PHYDM_SET) == PHYDM_SET_FAIL) {
phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3,
1, &igi_tmp);
return PHYDM_SET_FAIL;
}
/* @[Set IGI]*/
phydm_write_dig_reg(dm, (u8)igi);
/* @[Backup RF Reg]*/
dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18,
RFREG_MASK);
dm_psd_table->rf_0x18_bkp_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18,
RFREG_MASK);
if (psd_fc_channel > 14) {
is_5G = 1;
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)) {
#if 0
if (psd_fc_channel < 80)
ag_rf_mode_reg = 0x1;
else if (psd_fc_channel >= 80 && psd_fc_channel <= 140)
ag_rf_mode_reg = 0x3;
else if (psd_fc_channel > 140)
ag_rf_mode_reg = 0x5;
#endif
} else if (dm->support_ic_type & ODM_RTL8723F) {
if (psd_fc_channel < 80)
ag_rf_mode_reg = 0x1;
else if (psd_fc_channel >= 80 && psd_fc_channel <= 144)
ag_rf_mode_reg = 0x5;
else if (psd_fc_channel > 144)
ag_rf_mode_reg = 0x9;
} else if (dm->support_ic_type == ODM_RTL8721D) {
if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
ag_rf_mode_reg = 0x1;
else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
ag_rf_mode_reg = 0x5;
else if (psd_fc_channel > 140)
ag_rf_mode_reg = 0x9;
} else {
if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
ag_rf_mode_reg = 0x1;
else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
ag_rf_mode_reg = 0x3;
else if (psd_fc_channel > 140)
ag_rf_mode_reg = 0x5;
}
}
/* Set RF fc*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xff, psd_fc_channel);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xff, psd_fc_channel);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x300, is_5G);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x300, is_5G);
if (dm->support_ic_type & (ODM_RTL8822C | ODM_RTL8812F |
ODM_RTL8197G)) {
#if 0
/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x3000,
dm_psd_table->psd_bw_rf_reg);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x3000,
dm_psd_table->psd_bw_rf_reg);
/* Set RF ag fc mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x70000,
ag_rf_mode_reg);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x70000,
ag_rf_mode_reg);
#endif
} else if (dm->support_ic_type & ODM_RTL8723F) {
/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
dm_psd_table->psd_bw_rf_reg);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x1c00,
dm_psd_table->psd_bw_rf_reg);
/* Set RF ag fc mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x30000, 1);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0x30000, 1);
if(ag_rf_mode_reg == 1) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 0);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 0);
}
else if(ag_rf_mode_reg == 5){
odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 1);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 1);
}
else {
odm_set_rf_reg(dm, RF_PATH_A, RF_0x19, 0xc0000, 2);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x19, 0xc0000, 2);
}
} else {
/* @2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
if (dm->support_ic_type == ODM_RTL8721D) {
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0x1c00,
dm_psd_table->psd_bw_rf_reg);
#if (RTL8710C_SUPPORT == 1)
} else if (dm->support_ic_type == ODM_RTL8710C) {
odm_set_rf_reg(dm, RF_PATH_A,
RF_0x18, 0x1c00,
dm_psd_table->psd_bw_rf_reg);
#endif
} else {
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xc00,
dm_psd_table->psd_bw_rf_reg);
}
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xc00,
dm_psd_table->psd_bw_rf_reg);
/* Set RF ag fc mode*/
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xf0000,
ag_rf_mode_reg);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xf0000,
ag_rf_mode_reg);
}
if (dm->support_ic_type & ODM_IC_JGR3_SERIES){
if (dm->support_ic_type & ODM_RTL8723F) {
PHYDM_DBG(dm, ODM_COMP_API, "0x1d70=((0x%x))\n",
odm_get_bb_reg(dm, R_0x1d70, MASKDWORD));
PHYDM_DBG(dm, ODM_COMP_API, "RF0x19=((0x%x))\n",
odm_get_rf_reg(dm, RF_PATH_A, RF_0x19, RFREG_MASK));
}
} else
PHYDM_DBG(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
odm_get_bb_reg(dm, R_0xc50, MASKDWORD));
PHYDM_DBG(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK));
/* @[Stop 3-wires]*/
phydm_stop_3_wire(dm, PHYDM_SET);
ODM_delay_us(10);
if (stop_point > (dm_psd_table->fft_smp_point - 1))
stop_point = (dm_psd_table->fft_smp_point - 1);
if (start_point > (dm_psd_table->fft_smp_point - 1))
start_point = (dm_psd_table->fft_smp_point - 1);
if (start_point > stop_point)
stop_point = start_point;
for (i = start_point; i <= stop_point; i++) {
fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
if (i < fft_max_half_bw)
mod_tone_idx = i + fft_max_half_bw;
else
mod_tone_idx = i - fft_max_half_bw;
psd_result_tmp = 0;
for (t = 0; t < dm_psd_table->sw_avg_time; t++)
psd_result_tmp += phydm_get_psd_data(dm, mod_tone_idx,
igi);
psd_result =
(u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
dm_psd_table->psd_pwr_common_offset;
if (dm_psd_table->fft_smp_point == 128 &&
dm_psd_table->noise_k_en) {
if (i > psd_result_cali_tone[noise_idx])
noise_idx++;
if (noise_idx > 6)
noise_idx = 6;
if (psd_result >= psd_result_cali_val[noise_idx])
psd_result = psd_result -
psd_result_cali_val[noise_idx];
else
psd_result = 0;
dm_psd_table->psd_result[i] = psd_result;
}
PHYDM_DBG(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
mod_tone_idx, psd_result_cali_val[noise_idx],
psd_result);
}
/*@[Start 3-wires]*/
phydm_stop_3_wire(dm, PHYDM_REVERT);
ODM_delay_us(10);
/*@[Revert Reg]*/
set_result = phydm_stop_ic_trx(dm, PHYDM_REVERT);
odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, RFREG_MASK,
dm_psd_table->rf_0x18_bkp);
odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, RFREG_MASK,
dm_psd_table->rf_0x18_bkp_b);
PHYDM_DBG(dm, ODM_COMP_API, "PSD finished\n\n");
phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_3, 1,
&igi_tmp);
dm_psd_table->psd_in_progress = 0;
return PHYDM_SET_SUCCESS;
}
void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
u8 psd_input, u8 channel, u8 noise_k_en)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u8 fft_smp_point_idx = 0;
dm_psd_table->fft_smp_point = fft_smp_point;
if (sw_avg_time == 0)
sw_avg_time = 1;
dm_psd_table->sw_avg_time = sw_avg_time;
dm_psd_table->psd_fc_channel = channel;
dm_psd_table->noise_k_en = noise_k_en;
if (dm->support_ic_type & ODM_RTL8723F) {
if (fft_smp_point == 128)
fft_smp_point_idx = 3;
else if (fft_smp_point == 256)
fft_smp_point_idx = 2;
else if (fft_smp_point == 512)
fft_smp_point_idx = 1;
else if (fft_smp_point == 1024)
fft_smp_point_idx = 0;
}
else {
if (fft_smp_point == 128)
fft_smp_point_idx = 0;
else if (fft_smp_point == 256)
fft_smp_point_idx = 1;
else if (fft_smp_point == 512)
fft_smp_point_idx = 2;
else if (fft_smp_point == 1024)
fft_smp_point_idx = 3;
}
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
#if (RTL8723F_SUPPORT)
odm_set_bb_reg(dm, R_0x1e8c, BIT(12) | BIT(11), hw_avg_time);
odm_set_bb_reg(dm, R_0x1e8c, BIT(14) | BIT(13),
fft_smp_point_idx);
odm_set_bb_reg(dm, R_0x1e8c, BIT(18) | BIT(17), ant_sel);
odm_set_bb_reg(dm, R_0x1e88, BIT(25) | BIT(24), psd_input);
#else
#if 0
odm_set_bb_reg(dm, R_0x1e8c, BIT(11) | BIT(10), i_q_setting);
odm_set_bb_reg(dm, R_0x1e8c, BIT(13) | BIT(12), hw_avg_time);
if (fft_smp_point == 4096) {
odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x2);
} else if (fft_smp_point == 2048) {
odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x1);
} else {
odm_set_bb_reg(dm, R_0x1e88, BIT(31) | BIT(30), 0x0);
odm_set_bb_reg(dm, R_0x1e8c, BIT(15) | BIT(14),
fft_smp_point_idx);
}
odm_set_bb_reg(dm, R_0x1e8c, BIT(17) | BIT(16), ant_sel);
odm_set_bb_reg(dm, R_0x1e8c, BIT(23) | BIT(22), psd_input);
#endif
#endif
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
odm_set_bb_reg(dm, R_0x910, BIT(11) | BIT(10), i_q_setting);
odm_set_bb_reg(dm, R_0x910, BIT(13) | BIT(12), hw_avg_time);
odm_set_bb_reg(dm, R_0x910, BIT(15) | BIT(14),
fft_smp_point_idx);
odm_set_bb_reg(dm, R_0x910, BIT(17) | BIT(16), ant_sel);
odm_set_bb_reg(dm, R_0x910, BIT(23), psd_input);
} else if (dm->support_ic_type & (ODM_RTL8721D | ODM_RTL8710C)) {
odm_set_bb_reg(dm, R_0x808, BIT(19) | BIT(18), i_q_setting);
odm_set_bb_reg(dm, R_0x808, BIT(21) | BIT(20), hw_avg_time);
odm_set_bb_reg(dm, R_0x808, BIT(23) | BIT(22),
fft_smp_point_idx);
odm_set_bb_reg(dm, R_0x804, BIT(5) | BIT(4), ant_sel);
odm_set_bb_reg(dm, R_0x80c, BIT(23), psd_input);
#if 0
} else { /*ODM_IC_11N_SERIES*/
#endif
}
/*@bw = (*dm->band_width); //ODM_BW20M */
/*@channel = *(dm->channel);*/
}
void phydm_psd_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
PHYDM_DBG(dm, ODM_COMP_API, "PSD para init\n");
dm_psd_table->psd_in_progress = false;
if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
#if (RTL8723F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8723F) {
dm_psd_table->psd_reg = R_0x1e8c;
dm_psd_table->psd_report_reg = R_0x2d90;
/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
dm_psd_table->psd_bw_rf_reg = 2;
}
#else
#if 0
dm_psd_table->psd_reg = R_0x1e8c;
dm_psd_table->psd_report_reg = R_0x2d90;
/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
dm_psd_table->psd_bw_rf_reg = 1;
#endif
return;
#endif
} else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
dm_psd_table->psd_reg = R_0x910;
dm_psd_table->psd_report_reg = R_0xf44;
/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
if (ODM_IC_11AC_2_SERIES)
dm_psd_table->psd_bw_rf_reg = 1;
else
dm_psd_table->psd_bw_rf_reg = 2;
} else {
dm_psd_table->psd_reg = R_0x808;
dm_psd_table->psd_report_reg = R_0x8b4;
/*@2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
dm_psd_table->psd_bw_rf_reg = 2;
}
dm_psd_table->psd_pwr_common_offset = 0;
phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
#if 0
/*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
#endif
}
void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
char help[] = "-h";
u32 var1[10] = {0};
u32 used = *_used;
u32 out_len = *_out_len;
u8 i = 0;
if ((strcmp(input[1], help) == 0)) {
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
#if (RTL8723F_SUPPORT)
if (dm->support_ic_type & ODM_RTL8723F)
PDM_SNPF(out_len, used, output + used, out_len - used,
"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
#endif
#if 0
if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
PDM_SNPF(out_len, used, output + used, out_len - used,
"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4) 2048 4096}\n{path_sel 0~3} {0:ADC, 1:rxdata_fir_in, 2:rx_nbi_nf_stage2} {CH} {noise_k}\n\n");
else
#endif
#endif
PDM_SNPF(out_len, used, output + used, out_len - used,
"{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
PDM_SNPF(out_len, used, output + used, out_len - used,
"{1} {IGI(hex)} {start_point} {stop_point}\n");
goto out;
}
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if (var1[0] == 0) {
for (i = 1; i < 10; i++) {
PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
&var1[i]);
}
PDM_SNPF(out_len, used, output + used, out_len - used,
"sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
var1[1], var1[2], var1[3], var1[4], var1[5],
var1[6], (u8)var1[7], (u8)var1[8]);
phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
(u8)var1[3], (u16)var1[4],
(u8)var1[5], (u8)var1[6],
(u8)var1[7], (u8)var1[8]);
} else if (var1[0] == 1) {
PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
PDM_SNPF(out_len, used, output + used, out_len - used,
"IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
var1[1], var1[2], var1[3]);
dm->debug_components |= ODM_COMP_API;
if (phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]) ==
PHYDM_SET_FAIL)
PDM_SNPF(out_len, used, output + used, out_len - used,
"PSD_SET_FAIL\n");
dm->debug_components &= ~(ODM_COMP_API);
}
out:
*_used = used;
*_out_len = out_len;
}
u8 phydm_get_psd_result_table(void *dm_void, int index)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct psd_info *dm_psd_table = &dm->dm_psd_table;
u8 result = 0;
if (index < 128)
result = dm_psd_table->psd_result[index];
return result;
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMPSD_H__
#define __PHYDMPSD_H__
/*@#define PSD_VERSION "1.0"*/ /*@2016.09.22 Dino*/
/*@2016.10.07 Dino, Add Option for PSD Tone index Selection */
/*@2019.04.26 Early return & "IF0" for JGR3 ICs */
#define PSD_VERSION "1.2"
#ifdef CONFIG_PSD_TOOL
struct psd_info {
u8 psd_in_progress;
u32 psd_reg;
u32 psd_report_reg;
u8 psd_pwr_common_offset;
u16 sw_avg_time;
u16 fft_smp_point;
u32 rf_0x18_bkp;
u32 rf_0x18_bkp_b;
u16 psd_fc_channel;
u32 psd_bw_rf_reg;
u8 psd_result[128];
u8 noise_k_en;
};
u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi);
void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
u8 phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point);
void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
u8 psd_input, u8 channel, u8 noise_k_en);
void phydm_psd_init(void *dm_void);
u8 phydm_get_psd_result_table(void *dm_void, int index);
#endif
#endif

2432
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333
hal/phydm/phydm_rainfo.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMRAINFO_H__
#define __PHYDMRAINFO_H__
/* 2020.08.05 Fix ARFR bug due to rate_id error for 2.4G VHT mode*/
#define RAINFO_VERSION "8.8"
#define FORCED_UPDATE_RAMASK_PERIOD 5
#define H2C_MAX_LENGTH 7
#define RA_FLOOR_UP_GAP 3
#define RA_FLOOR_TABLE_SIZE 7
#define ACTIVE_TP_THRESHOLD 1
#define RA_RETRY_DESCEND_NUM 2
#define RA_RETRY_LIMIT_LOW 4
#define RA_RETRY_LIMIT_HIGH 32
#define PHYDM_IS_LEGACY_RATE(rate) ((rate <= ODM_RATE54M) ? true : false)
#define PHYDM_IS_CCK_RATE(rate) ((rate <= ODM_RATE11M) ? true : false)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define FIRST_MACID 1
#else
#define FIRST_MACID 0
#endif
/* @1 ============================================================
* 1 enumrate
* 1 ============================================================
*/
enum phydm_ra_dbg_para {
RADBG_PCR_TH_OFFSET = 0,
RADBG_RTY_PENALTY = 1,
RADBG_N_HIGH = 2,
RADBG_N_LOW = 3,
RADBG_TRATE_UP_TABLE = 4,
RADBG_TRATE_DOWN_TABLE = 5,
RADBG_TRYING_NECESSARY = 6,
RADBG_TDROPING_NECESSARY = 7,
RADBG_RATE_UP_RTY_RATIO = 8,
RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
RADBG_DEBUG_MONITOR1 = 0xc,
RADBG_DEBUG_MONITOR2 = 0xd,
RADBG_DEBUG_MONITOR3 = 0xe,
RADBG_DEBUG_MONITOR4 = 0xf,
RADBG_DEBUG_MONITOR5 = 0x10,
NUM_RA_PARA
};
enum phydm_wireless_mode {
PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
PHYDM_WIRELESS_MODE_A = 0x01,
PHYDM_WIRELESS_MODE_B = 0x02,
PHYDM_WIRELESS_MODE_G = 0x04,
PHYDM_WIRELESS_MODE_AUTO = 0x08,
PHYDM_WIRELESS_MODE_N_24G = 0x10,
PHYDM_WIRELESS_MODE_N_5G = 0x20,
PHYDM_WIRELESS_MODE_AC_5G = 0x40,
PHYDM_WIRELESS_MODE_AC_24G = 0x80,
PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
PHYDM_WIRELESS_MODE_MAX = 0x800,
PHYDM_WIRELESS_MODE_ALL = 0xFFFF
};
enum phydm_rateid_idx {
PHYDM_BGN_40M_2SS = 0,
PHYDM_BGN_40M_1SS = 1,
PHYDM_BGN_20M_2SS = 2,
PHYDM_BGN_20M_1SS = 3,
PHYDM_GN_N2SS = 4,
PHYDM_GN_N1SS = 5,
PHYDM_BG = 6,
PHYDM_G = 7,
PHYDM_B_20M = 8,
PHYDM_ARFR0_AC_2SS = 9,
PHYDM_ARFR1_AC_1SS = 10,
PHYDM_ARFR2_AC_2G_1SS = 11,
PHYDM_ARFR3_AC_2G_2SS = 12,
PHYDM_ARFR4_AC_3SS = 13,
PHYDM_ARFR5_N_3SS = 14,
PHYDM_ARFR7_N_4SS = 15,
PHYDM_ARFR6_AC_4SS = 16
};
/*ARFR4(0x49c/0x4a0) can not be used because FW BT would use.*/
enum phydm_rateid_idx_type_2 {
PHYDM_TYPE2_AC_2SS = 9,
PHYDM_TYPE2_AC_1SS = 10,
PHYDM_TYPE2_MIX_1SS = 11,
PHYDM_TYPE2_MIX_2SS = 12,
PHYDM_TYPE2_ARFR3_AC_2G_2SS = 16, /*0x494/0x498*/
PHYDM_TYPE2_ARFR5_AC_2G_1SS = 18 /*0x4a4/0x4a8*/
};
enum phydm_qam_order {
PHYDM_QAM_CCK = 0,
PHYDM_QAM_BPSK = 1,
PHYDM_QAM_QPSK = 2,
PHYDM_QAM_16QAM = 3,
PHYDM_QAM_64QAM = 4,
PHYDM_QAM_256QAM = 5
};
#if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */
struct _phydm_txstatistic_ {
u32 hw_total_tx;
u32 hw_tx_success;
u32 hw_tx_rty;
u32 hw_tx_drop;
};
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
struct _odm_ra_info_ {
u8 rate_id;
u32 rate_mask;
u32 ra_use_rate;
u8 rate_sgi;
u8 rssi_sta_ra;
u8 pre_rssi_sta_ra;
u8 sgi_enable;
u8 decision_rate;
u8 pre_rate;
u8 highest_rate;
u8 lowest_rate;
u32 nsc_up;
u32 nsc_down;
u16 RTY[5];
u32 TOTAL;
u16 DROP;
u8 active;
u16 rpt_time;
u8 ra_waiting_counter;
u8 ra_pending_counter;
u8 ra_drop_after_down;
#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */
u8 pt_active; /* on or off */
u8 pt_try_state; /* @0 trying state, 1 for decision state */
u8 pt_stage; /* @0~6 */
u8 pt_stop_count; /* Stop PT counter */
u8 pt_pre_rate; /* @if rate change do PT */
u8 pt_pre_rssi; /* @if RSSI change 5% do PT */
u8 pt_mode_ss; /* @decide whitch rate should do PT */
u8 ra_stage; /* @StageRA, decide how many times RA will be done between PT */
u8 pt_smooth_factor;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
u8 rate_down_counter;
u8 rate_up_counter;
u8 rate_direction;
u8 bounding_type;
u8 bounding_counter;
u8 bounding_learning_time;
u8 rate_down_start_time;
#endif
};
#endif
struct ra_table {
#ifdef MU_EX_MACID
u8 mu1_rate[MU_EX_MACID];
#endif
u8 highest_client_tx_order;
u16 highest_client_tx_rate_order;
u8 power_tracking_flag;
u8 ra_th_ofst; /*RA_threshold_offset*/
u8 ra_ofst_direc; /*RA_offset_direction*/
u8 up_ramask_cnt; /*@force update_ra_mask counter*/
u8 up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/
u32 rrsr_val_init; /*0x440*/
u32 rrsr_val_curr; /*0x440*/
boolean dynamic_rrsr_en;
u8 ra_trigger_mode; /*0: pkt RA, 1: TBTT RA*/
u8 ra_tx_cls_th; /*255: auto, xx: in dB*/
#if 0 /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
u8 per_rate_retrylimit_20M[PHY_NUM_RATE_IDX];
u8 per_rate_retrylimit_40M[PHY_NUM_RATE_IDX];
u8 retry_descend_num;
u8 retrylimit_low;
u8 retrylimit_high;
#endif
u8 ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */
void (*record_ra_info)(void *dm_void, u8 macid,
struct cmn_sta_info *sta, u64 ra_mask);
u8 ra_mask_rpt_stamp;
u8 ra_mask_buf[8];
};
struct ra_mask_rpt_trig {
u8 ra_mask_rpt_stamp;
u8 macid;
};
struct ra_mask_rpt {
u8 ra_mask_rpt_stamp;
u8 ra_mask_buf[8];
};
/* @1 ============================================================
* 1 Function Prototype
* 1 ============================================================
*/
boolean phydm_is_cck_rate(void *dm_void, u8 rate);
boolean phydm_is_ofdm_rate(void *dm_void, u8 rate);
boolean phydm_is_ht_rate(void *dm_void, u8 rate);
boolean phydm_is_vht_rate(void *dm_void, u8 rate);
u8 phydm_legacy_rate_2_spec_rate(void *dm_void, u8 rate);
u8 phydm_rate_2_rate_digit(void *dm_void, u8 rate);
u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);
u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);
void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
u32 *_out_len);
void phydm_ra_mask_report_h2c_trigger(void *dm_void,
struct ra_mask_rpt_trig *trig_rpt);
void phydm_ra_mask_report_c2h_result(void *dm_void, struct ra_mask_rpt *rpt);
void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);
void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
void phydm_rrsr_set_register(void *dm_void, u32 rrsr_val);
void phydm_ra_info_watchdog(void *dm_void);
void phydm_rrsr_en(void *dm_void, boolean en_rrsr);
void phydm_ra_info_init(void *dm_void);
void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
u8 ra_th_ofst);
u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
void phydm_update_hal_ra_mask(
void *dm_void,
u32 wireless_mode,
u8 rf_type,
u8 BW,
u8 mimo_ps_enable,
u8 disable_cck_rate,
u32 *ratr_bitmap_msb_in,
u32 *ratr_bitmap_in,
u8 tx_rate_level);
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
u8 phydm_get_plcp(void *dm_void, u16 macid);
#endif
void phydm_refresh_rate_adaptive_mask(void *dm_void);
u8 phydm_get_rx_stream_num(void *dm_void, enum rf_type type);
u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);
void odm_ra_post_action_on_assoc(void *dm);
u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect);
void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx);
void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc);
void phydm_ra_offline(void *dm_void, u8 macid);
void phydm_ra_mask_watchdog(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void odm_refresh_basic_rate_mask(
void *dm_void);
#endif
#ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
void phydm_ra_mode_selection(void *dm_void, u8 mode);
#endif
#endif /*@#ifndef __PHYDMRAINFO_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*************************************************************
* File Name: odm_reg.h
*
* Description:
*
* This file is for general register definition.
*
*
************************************************************/
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
/*@
* Register Definition
*
*/
/* @MAC REG */
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define RF_T_METER_OLD 0x24
#define RF_T_METER_NEW 0x42
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
/* @LTE_COEX */
#define REG_LTECOEX_CTRL 0x07C0
#define REG_LTECOEX_WRITE_DATA 0x07C4
#define REG_LTECOEX_READ_DATA 0x07C8
#define REG_LTECOEX_PATH_CONTROL 0x70
/* @BB REG */
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_6_18 0x830
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
/* RF REG */
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
#define ODM_RF_T_METER 0x24
#define ODM_RF_T_METER_92D 0x42
#define ODM_RF_T_METER_88E 0x42
#define ODM_RF_T_METER_92E 0x42
#define ODM_RF_T_METER_8812 0x42
#define REG_RF_TX_GAIN_OFFSET 0x55
/* @ant Detect Reg */
#define ODM_DPDT 0x300
/* PSD Init */
#define ODM_PSDREG 0x808
/* @92D path Div */
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
/*@
* Bitmap Definition
*/
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
/* TX AGC */
#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR 0xc20
#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR 0xc24
#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR 0xc28
#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR 0xc2c
#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR 0xc30
#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR 0xc34
#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR 0xc38
#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xc3c
#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xc40
#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xc44
#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xc48
#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xc4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR 0xcd8
#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR 0xcdc
#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xce0
#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xce4
#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xce8
#endif
#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR 0xe20
#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR 0xe24
#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR 0xe28
#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR 0xe2c
#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR 0xe30
#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR 0xe34
#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR 0xe38
#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0xe3c
#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0xe40
#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0xe44
#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0xe48
#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0xe4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR 0xed8
#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR 0xedc
#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0xee0
#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0xee4
#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0xee8
#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR 0x1820
#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR 0x1824
#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR 0x1828
#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR 0x182c
#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR 0x1830
#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR 0x1834
#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR 0x1838
#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x183c
#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1840
#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1844
#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1848
#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x184c
#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR 0x18d8
#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR 0x18dc
#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x18e0
#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x18e4
#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x18e8
#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR 0x1a20
#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR 0x1a24
#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR 0x1a28
#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR 0x1a2c
#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR 0x1a30
#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR 0x1a34
#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR 0x1a38
#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR 0x1a3c
#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR 0x1a40
#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR 0x1a44
#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR 0x1a48
#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR 0x1a4c
#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR 0x1ad8
#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR 0x1adc
#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR 0x1ae0
#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR 0x1ae4
#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR 0x1ae8
#endif
#define is_tx_agc_byte0_jaguar 0xff
#define is_tx_agc_byte1_jaguar 0xff00
#define is_tx_agc_byte2_jaguar 0xff0000
#define is_tx_agc_byte3_jaguar 0xff000000
#if defined(CONFIG_WLAN_HAL_8198F) || defined(CONFIG_WLAN_HAL_8822CE) ||\
defined(CONFIG_WLAN_HAL_8814BE) || defined(CONFIG_WLAN_HAL_8812FE) ||\
defined(CONFIG_WLAN_HAL_8197G)
#define REG_TX_AGC_CCK_11_CCK_1_JAGUAR3 0x3a00
#define REG_TX_AGC_OFDM_18_CCK_6_JAGUAR3 0x3a04
#define REG_TX_AGC_OFDM_54_CCK_24_JAGUAR3 0x3a08
#define REG_TX_AGC_MCS3_0_JAGUAR3 0x3a0c
#define REG_TX_AGC_MCS7_4_JAGUAR3 0x3a10
#define REG_TX_AGC_MCS11_8_JAGUAR3 0x3a14
#define REG_TX_AGC_MCS15_12_JAGUAR3 0x3a18
#define REG_TX_AGC_MCS19_16_JAGUAR3 0x3a1c
#define REG_TX_AGC_MCS23_20_JAGUAR3 0x3a20
#define REG_TX_AGC_MCS27_24_JAGUAR3 0x3a24
#define REG_TX_AGC_MCS31_28_JAGUAR3 0x3a28
#define REG_TX_AGC_VHT_Nss1_MCS3_0_JAGUAR3 0x3a2c
#define REG_TX_AGC_VHT_Nss1_MCS7_4_JAGUAR3 0x3a30
#define REG_TX_AGC_VHT_NSS2_MCS1_NSS1_MCS8_JAGUAR3 0x3a34
#define REG_TX_AGC_VHT_Nss2_MCS5_2_JAGUAR3 0x3a38
#define REG_TX_AGC_VHT_Nss2_MCS9_6_JAGUAR3 0x3a3c
#define REG_TX_AGC_VHT_Nss3_MCS3_0_JAGUAR3 0x3a40
#define REG_TX_AGC_VHT_Nss3_MCS7_4_JAGUAR3 0x3a44
#define REG_TX_AGC_VHT_Nss4_MCS1_Nss3_MCS8_JAGUAR3 0x3a48
#define REG_TX_AGC_VHT_Nss4_MCS5_2_JAGUAR3 0x3a4c
#define REG_TX_AGC_VHT_Nss4_MCS9_6_JAGUAR3 0x3a50
#endif
#endif
#define BIT_FA_RESET BIT(0)
#endif

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hal/phydm/phydm_regdefine11ac.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
/* @2 RF REG LIST */
/* @2 BB REG LIST */
/* PAGE 8 */
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
#define ODM_REG_BB_RX_PATH_11AC 0x808
#define ODM_REG_BB_TX_PATH_11AC 0x80c
#define ODM_REG_BB_ATC_11AC 0x860
#define ODM_REG_EDCCA_POWER_CAL 0x8dc
#define ODM_REG_DBG_RPT_11AC 0x8fc
/* PAGE 9 */
#define ODM_REG_EDCCA_DOWN_OPT 0x900
#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
#define odm_adc_trigger_jaguar2 0x95C /*@ADC sample mode*/
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
#define ODM_REG_CCX_PERIOD_11AC 0x990
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
#define ODM_REG_CLM_11AC 0x994
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
#define ODM_REG_NHM_TH8_11AC 0x9a0
#define ODM_REG_NHM_9E8_11AC 0x9e8
#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
/* PAGE A */
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
/* PAGE B */
#define ODM_REG_RST_RPT_11AC 0xB58
/* PAGE C */
#define ODM_REG_TRMUX_11AC 0xC08
#define ODM_REG_IGI_A_11AC 0xC50
/* PAGE E */
#define ODM_REG_IGI_B_11AC 0xE50
#define ODM_REG_ANT_11AC_B 0xE08
/* PAGE F */
#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04
#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c
#define ODM_REG_HT_CRC32_CNT_11AC 0xF10
#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14
#define ODM_REG_OFDM_FA_11AC 0xF48
#define ODM_REG_OFDM_FA_TYPE1_11AC 0xFCC
#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
#define ODM_REG_OFDM_FA_TYPE3_11AC 0xFBC
#define ODM_REG_OFDM_FA_TYPE4_11AC 0xFC0
#define ODM_REG_OFDM_FA_TYPE5_11AC 0xFC4
#define ODM_REG_OFDM_FA_TYPE6_11AC 0xFC8
#define ODM_REG_RPT_11AC 0xfa0
#define ODM_REG_CLM_RESULT_11AC 0xfa4
#define ODM_REG_NHM_CNT_11AC 0xfa8
#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
/* PAGE 18 */
#define ODM_REG_IGI_C_11AC 0x1850
/* PAGE 1A */
#define ODM_REG_IGI_D_11AC 0x1A50
/* PAGE 1D */
#define ODM_REG_IGI_11AC3 0x1D70
/* @2 MAC REG LIST */
#define ODM_REG_RESP_TX_11AC 0x6D8
/* @DIG Related */
#define ODM_BIT_IGI_11AC 0x0000007F
#define ODM_BIT_IGI_B_11AC3 0x00007F00
#define ODM_BIT_IGI_C_11AC3 0x007F0000
#define ODM_BIT_IGI_D_11AC3 0x7F000000
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16)
#define ODM_BIT_BB_RX_PATH_11AC 0xF
#define ODM_BIT_BB_TX_PATH_11AC 0xF
#define ODM_BIT_BB_ATC_11AC BIT(14)
#endif

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hal/phydm/phydm_regdefine11n.h Normal file
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
/* @2 RF REG LIST */
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
#define ODM_REF_RF_DF_11N 0xDF
/* @2 BB REG LIST
* PAGE 8
*/
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
#define ODM_REG_RX_DEFAULT_A_11N 0x858
#define ODM_REG_RX_DEFAULT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_CCX_PERIOD_11N 0x894
#define ODM_REG_NHM_TH9_TH10_11N 0x890
#define ODM_REG_CLM_11N 0x890
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
#define ODM_REG_NHM_TH8_11N 0xe28
#define ODM_REG_CLM_READY_11N 0x8b4
#define ODM_REG_CLM_RESULT_11N 0x8d0
#define ODM_REG_NHM_CNT_11N 0x8d8
/* @For struct acs_info, Jeffery, 2014-12-26 */
#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4
/* PAGE 9 */
#define ODM_REG_BB_CTRL_PAGE9_11N 0x900
#define ODM_REG_DBG_RPT_11N 0x908
#define ODM_REG_BB_TX_PATH_11N 0x90c
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
#define ODM_REG_RX_DFIR_MOD_97F 0x948
#define ODM_REG_SOML_97F 0x998
/* PAGE A */
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_ANT_SEL_11N 0xA04
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
/* PAGE B */
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
#define ODM_REG_RXCK_RFMOD 0xBB0
#define ODM_REG_EDCCA_DCNF_97F 0xBC0
/* PAGE C */
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_BB_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_BB_AGC_SET_2_11N 0xc74
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
/* PAGE D */
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_BB_RX_ANT_11N 0xD04
#define ODM_REG_BB_ATC_11N 0xD2C
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
#define ODM_REG_RPT_11N 0xDF4
/* PAGE E */
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_EDCCA_DCNF_11N 0xE24
#define ODM_REG_TAP_UPD_97F 0xE24
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_PAGE_B1_97F 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
/* PAGE F */
#define ODM_REG_PAGE_F_RST_11N 0xF14
#define ODM_REG_IGI_C_11N 0xF84
#define ODM_REG_IGI_D_11N 0xF88
#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84
#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88
#define ODM_REG_HT_CRC32_CNT_11N 0xF90
#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94
#define ODM_REG_HT_CRC32_CNT_11N_AGG 0xFB8
/* @2 MAC REG LIST */
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
/* @DIG Related */
#define ODM_BIT_IGI_11N 0x0000007F
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9)
#define ODM_BIT_BB_RX_PATH_11N 0xF
#define ODM_BIT_BB_TX_PATH_11N 0xF
#define ODM_BIT_BB_ATC_11N BIT(11)
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*@************************************************************
* include files
************************************************************/
#include "mp_precomp.h"
#include "phydm_precomp.h"
#ifdef PHYDM_SUPPORT_RSSI_MONITOR
void phydm_rssi_monitor_h2c(void *dm_void, u8 macid)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_t = &dm->dm_ra_table;
struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
struct ra_sta_info *ra = NULL;
#ifdef CONFIG_BEAMFORMING
struct bf_cmn_info *bf = NULL;
#endif
u8 h2c[H2C_MAX_LENGTH] = {0};
u8 stbc_en, ldpc_en;
u8 bf_en = 0;
u8 is_rx, is_tx;
if (is_sta_active(sta)) {
ra = &sta->ra_info;
} else {
PHYDM_DBG(dm, DBG_RSSI_MNTR, "[Warning] %s\n", __func__);
return;
}
PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "MACID=%d\n", sta->mac_id);
is_rx = (ra->txrx_state == RX_STATE) ? 1 : 0;
is_tx = (ra->txrx_state == TX_STATE) ? 1 : 0;
stbc_en = (sta->stbc_en) ? 1 : 0;
ldpc_en = (sta->ldpc_en) ? 1 : 0;
#ifdef CONFIG_BEAMFORMING
bf = &sta->bf_info;
if ((bf->ht_beamform_cap & BEAMFORMING_HT_BEAMFORMEE_ENABLE) ||
(bf->vht_beamform_cap & BEAMFORMING_VHT_BEAMFORMEE_ENABLE))
bf_en = 1;
#endif
PHYDM_DBG(dm, DBG_RSSI_MNTR, "RA_th_ofst=(( %s%d ))\n",
((ra_t->ra_ofst_direc) ? "+" : "-"), ra_t->ra_th_ofst);
h2c[0] = sta->mac_id;
h2c[1] = 0;
h2c[2] = sta->rssi_stat.rssi;
h2c[3] = is_rx | (stbc_en << 1) |
((dm->noisy_decision & 0x1) << 2) | (bf_en << 6);
h2c[4] = (ra_t->ra_th_ofst & 0x7f) |
((ra_t->ra_ofst_direc & 0x1) << 7);
h2c[5] = 0;
h2c[6] = ((ra_t->ra_trigger_mode) << 2);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "PHYDM h2c[0x42]=0x%x %x %x %x %x %x %x\n",
h2c[6], h2c[5], h2c[4], h2c[3], h2c[2], h2c[1], h2c[0]);
#if (RTL8188E_SUPPORT)
if (dm->support_ic_type == ODM_RTL8188E)
odm_ra_set_rssi_8188e(dm, sta->mac_id, sta->rssi_stat.rssi);
else
#endif
{
odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, H2C_MAX_LENGTH, h2c);
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta = NULL;
struct rssi_info *rssi_t = NULL;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
sta = dm->phydm_sta_info[macid];
rssi_t = &sta->rssi_stat;
rssi_t->rssi_acc = (init_rssi << RSSI_MA);
rssi_t->rssi = init_rssi;
}
#endif
void phydm_calculate_rssi_min_max(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct cmn_sta_info *sta;
s8 rssi_max_tmp = 0, rssi_min_tmp = 100;
u8 i;
u8 sta_cnt = 0;
if (!dm->is_linked)
return;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
sta = dm->phydm_sta_info[i];
if (is_sta_active(sta)) {
sta_cnt++;
if (sta->rssi_stat.rssi < rssi_min_tmp) {
rssi_min_tmp = sta->rssi_stat.rssi;
dm->rssi_min_macid = i;
}
if (sta->rssi_stat.rssi > rssi_max_tmp) {
rssi_max_tmp = sta->rssi_stat.rssi;
dm->rssi_max_macid = i;
}
/*@[Send RSSI to FW]*/
if (!sta->ra_info.disable_ra)
phydm_rssi_monitor_h2c(dm, i);
if (sta_cnt == dm->number_linked_client)
break;
}
}
dm->pre_rssi_min = dm->rssi_min;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
if (dm->number_linked_client == 0)
return;
#endif
dm->rssi_max = (u8)rssi_max_tmp;
dm->rssi_min = (u8)rssi_min_tmp;
}
void phydm_rssi_monitor_check(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
return;
/*@for AP watchdog period = 1 sec*/
if ((dm->phydm_sys_up_time % 2) == 1)
return;
PHYDM_DBG(dm, DBG_RSSI_MNTR, "%s ======>\n", __func__);
phydm_calculate_rssi_min_max(dm);
PHYDM_DBG(dm, DBG_RSSI_MNTR, "RSSI {max, min} = {%d, %d}\n",
dm->rssi_max, dm->rssi_min);
}
void phydm_rssi_monitor_init(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct ra_table *ra_tab = &dm->dm_ra_table;
dm->pre_rssi_min = 0;
dm->rssi_max = 0;
dm->rssi_min = 0;
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDM_RSSI_MONITOR_H__
#define __PHYDM_RSSI_MONITOR_H__
#define RSSI_MONITOR_VERSION "2.0"
/* @1 ============================================================
* 1 Definition
* 1 ============================================================
*/
/* @1 ============================================================
* 1 structure
* 1 ============================================================
*/
/* @1 ============================================================
* 1 enumeration
* 1 ============================================================
*/
/* @1 ============================================================
* 1 function prototype
* 1 ============================================================
*/
void phydm_rssi_monitor_check(void *dm_void);
void phydm_rssi_monitor_init(void *dm_void);
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
void phydm_sta_rssi_init(void *dm_void, u8 macid, u8 init_rssi);
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMSMTANT_H__
#define __PHYDMSMTANT_H__
/*@#define SMT_ANT_VERSION "1.1"*/ /*@2017.03.13*/
/*@#define SMT_ANT_VERSION "1.2"*/ /*@2017.03.28*/
#define SMT_ANT_VERSION "2.0" /* @Add Cumitek SmtAnt 2017.05.25*/
#define SMTANT_RTK 1
#define SMTANT_HON_BO 2
#define SMTANT_CUMITEK 3
#if (defined(CONFIG_SMART_ANTENNA))
#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
struct smt_ant_cumitek {
u8 tx_ant_idx[2][ODM_ASSOCIATE_ENTRY_NUM]; /*@[pathA~B] [MACID 0~128]*/
u8 rx_default_ant_idx[2]; /*@[pathA~B]*/
};
#endif
#if (defined(CONFIG_HL_SMART_ANTENNA))
struct smt_ant_honbo {
u32 latch_time;
boolean pkt_skip_statistic_en;
u32 fix_beam_pattern_en;
u32 fix_training_num_en;
u32 fix_beam_pattern_codeword;
u32 update_beam_codeword;
u32 ant_num; /*number of "used" smart beam antenna*/
u32 ant_num_total;/*number of "total" smart beam antenna*/
u32 first_train_ant; /*@decide witch antenna to train first*/
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
u32 pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];/*@rssi of each path with a certain beam pattern*/
u8 beam_train_rssi_diff[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
u8 beam_train_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
u32 rfu_codeword_table[4]; /*@2G beam truth table*/
u32 rfu_codeword_table_5g[4]; /*@5G beam truth table*/
u32 beam_patten_num_each_ant;/*@number of beam can be switched in each antenna*/
u32 rx_idle_beam[SUPPORT_RF_PATH_NUM];
u32 pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM];
u32 pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM];
#endif
u32 fast_training_beam_num;/*@current training beam_set index*/
u32 pre_fast_training_beam_num;/*pre training beam_set index*/
u32 rfu_codeword_total_bit_num; /* @total bit number of RFU protocol*/
u32 rfu_each_ant_bit_num; /* @bit number of RFU protocol for each ant*/
u8 per_beam_training_pkt_num;
u8 decision_holding_period;
u32 pre_codeword;
boolean force_update_beam_en;
u32 beacon_counter;
u32 pre_beacon_counter;
u8 pkt_counter; /*@packet number that each beam-set should be colected in training state*/
u8 update_beam_idx; /*@the index announce that the beam can be updated*/
u8 rfu_protocol_type;
u16 rfu_protocol_delay_time;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_WORK_ITEM hl_smart_antenna_workitem;
RT_WORK_ITEM hl_smart_antenna_decision_workitem;
#endif
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
u8 beam_set_avg_rssi_pre[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@avg pre_rssi of each beam set*/
u8 beam_set_train_val_diff[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@rssi of a beam pattern set, ex: a set = {ant1_beam=1, ant2_beam=3}*/
u8 beam_set_train_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@training pkt num of each beam set*/
u32 beam_set_rssi_avg_sum[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@RSSI_sum of avg(pathA,pathB) for each beam-set)*/
u32 beam_path_rssi_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@RSSI_sum of each path for each beam-set)*/
u8 beam_set_avg_evm_2ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
u32 beam_path_evm_2ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B];/*@2SS evm_sum of each path for each beam-set)*/
u32 beam_path_evm_2ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
u8 beam_set_avg_evm_1ss_pre[SUPPORT_BEAM_SET_PATTERN_NUM];
u32 beam_path_evm_1ss_sum[SUPPORT_BEAM_SET_PATTERN_NUM];/*@1SS evm_sum of each path for each beam-set)*/
u32 beam_path_evm_1ss_cnt[SUPPORT_BEAM_SET_PATTERN_NUM];
u32 statistic_pkt_cnt[SUPPORT_BEAM_SET_PATTERN_NUM]; /*@statistic_pkt_cnt for SmtAnt make decision*/
u8 total_beam_set_num; /*@number of beam set can be switched*/
u8 total_beam_set_num_2g;/*@number of beam set can be switched in 2G*/
u8 total_beam_set_num_5g;/*@number of beam set can be switched in 5G*/
u8 rfu_codeword_table_2g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@2G beam truth table*/
u8 rfu_codeword_table_5g[SUPPORT_BEAM_SET_PATTERN_NUM][MAX_PATH_NUM_8822B]; /*@5G beam truth table*/
u8 rx_idle_beam_set_idx; /*the filanl decsion result*/
#endif
};
#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
struct smt_ant {
u8 smt_ant_vendor;
u8 smt_ant_type;
u8 tx_desc_mode; /*@0:3 bit mode, 1:2 bit mode*/
#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
struct smt_ant_cumitek cumi_smtant_table;
#endif
};
#if (defined(CONFIG_CUMITEK_SMART_ANTENNA))
void phydm_cumitek_smt_tx_ant_update(
void *dm_void,
u8 tx_ant_idx_path_a,
u8 tx_ant_idx_path_b,
u32 mac_id);
void phydm_cumitek_smt_rx_default_ant_update(
void *dm_void,
u8 rx_ant_idx_path_a,
u8 rx_ant_idx_path_b);
void phydm_cumitek_smt_ant_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len);
#endif
#if (defined(CONFIG_HL_SMART_ANTENNA))
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_beam_switch_workitem_callback(
void *context);
void phydm_beam_decision_workitem_callback(
void *context);
#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
void phydm_hl_smart_ant_type2_init_8822b(
void *dm_void);
void phydm_update_beam_pattern_type2(
void *dm_void,
u32 codeword,
u32 codeword_length);
void phydm_set_rfu_beam_pattern_type2(
void *dm_void);
void phydm_hl_smt_ant_dbg_type2(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len);
void phydm_process_rssi_for_hb_smtant_type2(
void *dm_void,
void *phy_info_void,
void *pkt_info_void,
u8 rssi_avg);
#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE2))*/
#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))
void phydm_update_beam_pattern(
void *dm_void,
u32 codeword,
u32 codeword_length);
void phydm_set_all_ant_same_beam_num(
void *dm_void);
void phydm_hl_smart_ant_debug(
void *dm_void,
char input[][16],
u32 *_used,
char *output,
u32 *_out_len);
#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA_TYPE1))*/
#endif /*@#if (defined(CONFIG_HL_SMART_ANTENNA))*/
void phydm_smt_ant_init(void *dm_void);
#endif /*@#if (defined(CONFIG_SMART_ANTENNA))*/
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __PHYDMSOML_H__
#define __PHYDMSOML_H__
/*@#define ADAPTIVE_SOML_VERSION "1.0" Byte counter version*/
#define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/
#define PHYDM_ADAPTIVE_SOML_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)
/*@jj add 20170822*/
#define INIT_SOML_TIMMER 0
#define CANCEL_SOML_TIMMER 1
#define RELEASE_SOML_TIMMER 2
#define SOML_RSSI_TH_HIGH 25
#define SOML_RSSI_TH_LOW 20
#define HT_RATE_IDX 16
#define VHT_RATE_IDX 20
#define HT_ORDER_TYPE 3
#define VHT_ORDER_TYPE 4
#define CRC_FAIL 1
#define CRC_OK 0
#if 0
#define CFO_QPSK_TH 20
#define CFO_QAM16_TH 20
#define CFO_QAM64_TH 20
#define CFO_QAM256_TH 20
#define BPSK_QPSK_DIST 20
#define QAM16_DIST 30
#define QAM64_DIST 30
#define QAM256_DIST 20
#endif
#define HT_TYPE 1
#define VHT_TYPE 2
#define SOML_ON 1
#define SOML_OFF 0
#ifdef CONFIG_ADAPTIVE_SOML
struct adaptive_soml {
u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
boolean is_soml_method_enable;
boolean get_stats;
u8 soml_on_off;
u8 soml_state_cnt;
u8 soml_delay_time;
u8 soml_intvl;
u8 soml_train_num;
u8 soml_counter;
u8 soml_period;
u8 soml_select;
u8 soml_last_state;
u8 cfo_qpsk_th;
u8 cfo_qam16_th;
u8 cfo_qam64_th;
u8 cfo_qam256_th;
u8 bpsk_qpsk_dist_th;
u8 qam16_dist_th;
u8 qam64_dist_th;
u8 qam256_dist_th;
u8 cfo_cnt;
s32 cfo_diff_a;
s32 cfo_diff_b;
s32 cfo_diff_sum_a;
s32 cfo_diff_sum_b;
s32 cfo_diff_avg_a;
s32 cfo_diff_avg_b;
u16 ht_cnt[HT_RATE_IDX];
u16 pre_ht_cnt[HT_RATE_IDX];
u16 ht_cnt_on[HT_RATE_IDX];
u16 ht_cnt_off[HT_RATE_IDX];
u16 ht_crc_ok_cnt_on[HT_RATE_IDX];
u16 ht_crc_fail_cnt_on[HT_RATE_IDX];
u16 ht_crc_ok_cnt_off[HT_RATE_IDX];
u16 ht_crc_fail_cnt_off[HT_RATE_IDX];
u16 vht_crc_ok_cnt_on[VHT_RATE_IDX];
u16 vht_crc_fail_cnt_on[VHT_RATE_IDX];
u16 vht_crc_ok_cnt_off[VHT_RATE_IDX];
u16 vht_crc_fail_cnt_off[VHT_RATE_IDX];
u16 vht_cnt[VHT_RATE_IDX];
u16 pre_vht_cnt[VHT_RATE_IDX];
u16 vht_cnt_on[VHT_RATE_IDX];
u16 vht_cnt_off[VHT_RATE_IDX];
u16 num_ht_qam[HT_ORDER_TYPE];
u16 ht_byte[HT_RATE_IDX];
u16 pre_ht_byte[HT_RATE_IDX];
u16 ht_byte_on[HT_RATE_IDX];
u16 ht_byte_off[HT_RATE_IDX];
u16 num_vht_qam[VHT_ORDER_TYPE];
u16 vht_byte[VHT_RATE_IDX];
u16 pre_vht_byte[VHT_RATE_IDX];
u16 vht_byte_on[VHT_RATE_IDX];
u16 vht_byte_off[VHT_RATE_IDX];
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM phydm_adaptive_soml_workitem;
#endif
#endif
struct phydm_timer_list phydm_adaptive_soml_timer;
};
enum qam_order {
BPSK_QPSK = 0,
QAM16 = 1,
QAM64 = 2,
QAM256 = 3
};
void phydm_dynamicsoftmletting(void *dm_void);
void phydm_soml_on_off(void *dm_void, u8 swch);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_adaptive_soml_callback(struct phydm_timer_list *timer);
void phydm_adaptive_soml_workitem_callback(void *context);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
void phydm_adaptive_soml_callback(void *dm_void);
void phydm_adaptive_soml_workitem_callback(void *context);
#else
void phydm_adaptive_soml_callback(void *dm_void);
#endif
void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void);
void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void);
void phydm_soml_reset_rx_rate(void *dm_void);
void phydm_soml_reset_qam(void *dm_void);
void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b);
void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
char *output, u32 *_out_len);
void phydm_soml_statistics(void *dm_void, u8 on_off_state);
void phydm_adsl(void *dm_void);
void phydm_adaptive_soml_reset(void *dm_void);
void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len);
void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length);
void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length);
void phydm_adaptive_soml_timers(void *dm_void, u8 state);
void phydm_adaptive_soml_init(void *dm_void);
void phydm_adaptive_soml(void *dm_void);
void phydm_enable_adaptive_soml(void *dm_void);
void phydm_stop_adaptive_soml(void *dm_void);
void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
u8 period, u8 delay_time);
#endif
void phydm_init_soft_ml_setting(void *dm_void);
#endif /*@#ifndef __PHYDMSOML_H__*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __ODM_TYPES_H__
#define __ODM_TYPES_H__
/*Define Different SW team support*/
#define ODM_AP 0x01 /*BIT(0)*/
#define ODM_CE 0x04 /*BIT(2)*/
#define ODM_WIN 0x08 /*BIT(3)*/
#define ODM_ADSL 0x10
/*BIT(4)*/ /*already combine with ODM_AP, and is nouse now*/
#define ODM_IOT 0x20 /*BIT(5)*/
/*For FW API*/
#define __iram_odm_func__
#define __odm_func__
#define __odm_func_aon__
/*Deifne HW endian support*/
#define ODM_ENDIAN_BIG 0
#define ODM_ENDIAN_LITTLE 1
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&(GET_HAL_DATA(__padapter))->DM_OutSrc))
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define GET_PDM_ODM(__padapter) ((struct dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define GET_PDM_ODM(__padapter) ((struct dm_struct*)(&__padapter->pshare->_dmODM))
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
/* enable PCI & USB HCI at the same time */
#define RT_PCI_USB_INTERFACE 1
#define RT_PCI_INTERFACE RT_PCI_USB_INTERFACE
#define RT_USB_INTERFACE RT_PCI_USB_INTERFACE
#define RT_SDIO_INTERFACE 3
#else
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#endif
#endif
enum hal_status {
HAL_STATUS_SUCCESS,
HAL_STATUS_FAILURE,
#if 0
RT_STATUS_PENDING,
RT_STATUS_RESOURCE,
RT_STATUS_INVALID_CONTEXT,
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,
#endif
};
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define VISTA_USB_RX_REVISE 0
/*
* Declare for ODM spin lock definition temporarily fro compile pass.
*/
enum rt_spinlock_type {
RT_TX_SPINLOCK = 1,
RT_RX_SPINLOCK = 2,
RT_RM_SPINLOCK = 3,
RT_CAM_SPINLOCK = 4,
RT_SCAN_SPINLOCK = 5,
RT_LOG_SPINLOCK = 7,
RT_BW_SPINLOCK = 8,
RT_CHNLOP_SPINLOCK = 9,
RT_RF_OPERATE_SPINLOCK = 10,
RT_INITIAL_SPINLOCK = 11,
RT_RF_STATE_SPINLOCK = 12,
/* For RF state. Added by Bruce, 2007-10-30. */
#if VISTA_USB_RX_REVISE
RT_USBRX_CONTEXT_SPINLOCK = 13,
RT_USBRX_POSTPROC_SPINLOCK = 14,
/* protect data of adapter->IndicateW/ IndicateR */
#endif
/* Shall we define Ndis 6.2 SpinLock Here ? */
RT_PORT_SPINLOCK = 16,
RT_VNIC_SPINLOCK = 17,
RT_HVL_SPINLOCK = 18,
RT_H2C_SPINLOCK = 20,
/* For H2C cmd. Added by tynli. 2009.11.09. */
rt_bt_data_spinlock = 25,
RT_WAPI_OPTION_SPINLOCK = 26,
RT_WAPI_RX_SPINLOCK = 27,
/* add for 92D CCK control issue */
RT_CCK_PAGEA_SPINLOCK = 28,
RT_BUFFER_SPINLOCK = 29,
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
RT_GEN_TEMP_BUF_SPINLOCK = 31,
RT_AWB_SPINLOCK = 32,
RT_FW_PS_SPINLOCK = 33,
RT_HW_TIMER_SPIN_LOCK = 34,
RT_MPT_WI_SPINLOCK = 35,
RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
RT_DBG_SPIN_LOCK = 37,
RT_IQK_SPINLOCK = 38,
RT_PENDED_OID_SPINLOCK = 39,
RT_CHNLLIST_SPINLOCK = 40,
RT_INDIC_SPINLOCK = 41, /* protect indication */
RT_RFD_SPINLOCK = 42,
RT_SYNC_IO_CNT_SPINLOCK = 43,
RT_LAST_SPINLOCK,
};
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define sta_info _RT_WLAN_STA
#define __func__ __FUNCTION__
#define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT
#define MASKH3BYTES 0xffffff00
#define SUCCESS 0
#define FAIL (-1)
#define u8 u1Byte
#define s8 s1Byte
#define u16 u2Byte
#define s16 s2Byte
#define u32 u4Byte
#define s32 s4Byte
#define u64 u8Byte
#define s64 s8Byte
#define phydm_timer_list _RT_TIMER
// for power limit table
enum odm_pw_lmt_regulation_type {
PW_LMT_REGU_FCC = 0,
PW_LMT_REGU_ETSI = 1,
PW_LMT_REGU_MKK = 2,
PW_LMT_REGU_WW13 = 3,
PW_LMT_REGU_IC = 4,
PW_LMT_REGU_KCC = 5,
PW_LMT_REGU_ACMA = 6,
PW_LMT_REGU_CHILE = 7,
PW_LMT_REGU_UKRAINE = 8,
PW_LMT_REGU_MEXICO = 9,
PW_LMT_REGU_CN = 10
};
enum odm_pw_lmt_band_type {
PW_LMT_BAND_2_4G = 0,
PW_LMT_BAND_5G = 1
};
enum odm_pw_lmt_bandwidth_type {
PW_LMT_BW_20M = 0,
PW_LMT_BW_40M = 1,
PW_LMT_BW_80M = 2,
PW_LMT_BW_160M = 3
};
enum odm_pw_lmt_ratesection_type {
PW_LMT_RS_CCK = 0,
PW_LMT_RS_OFDM = 1,
PW_LMT_RS_HT = 2,
PW_LMT_RS_VHT = 3
};
enum odm_pw_lmt_rfpath_type {
PW_LMT_PH_1T = 0,
PW_LMT_PH_2T = 1,
PW_LMT_PH_3T = 2,
PW_LMT_PH_4T = 3
};
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../typedef.h"
#ifdef CONFIG_PCI_HCI
#if defined(CONFIG_RTL_TRIBAND_SUPPORT) && defined(CONFIG_USB_HCI)
#define DEV_BUS_TYPE RT_PCI_USB_INTERFACE
#else
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#endif
#endif
#if (defined(TESTCHIP_SUPPORT))
#define PHYDM_TESTCHIP_SUPPORT 1
#else
#define PHYDM_TESTCHIP_SUPPORT 0
#endif
#define sta_info stat_info
#define boolean bool
#define phydm_timer_list timer_list
#if defined(__ECOS)
#define s64 s8Byte
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
#include <asm/byteorder.h>
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#if defined(__LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#elif defined(__BIG_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#error
#endif
/* define useless flag to avoid compile warning */
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define FPGA_TWO_MAC_VERIFICATION 0
#define RTL8881A_SUPPORT 0
#define PHYDM_TESTCHIP_SUPPORT 0
#define RATE_ADAPTIVE_SUPPORT 0
#define POWER_TRAINING_ACTIVE 0
#define sta_info rtl_sta_info
#define boolean bool
#define phydm_timer_list timer_list
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <drv_types.h>
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#elif defined(CONFIG_SDIO_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#endif
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#elif defined(CONFIG_BIG_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#endif
#define boolean bool
#define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 24, 1, __value)
#define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 8, 25, 1, __value)
#define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc + 28, 29, 1, __value)
/* define useless flag to avoid compile warning */
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define FPGA_TWO_MAC_VERIFICATION 0
#define RTL8881A_SUPPORT 0
#if (defined(TESTCHIP_SUPPORT))
#define PHYDM_TESTCHIP_SUPPORT 1
#else
#define PHYDM_TESTCHIP_SUPPORT 0
#endif
#define phydm_timer_list rtw_timer_list
// for power limit table
enum odm_pw_lmt_regulation_type {
PW_LMT_REGU_FCC = 0,
PW_LMT_REGU_ETSI = 1,
PW_LMT_REGU_MKK = 2,
PW_LMT_REGU_WW13 = 3,
PW_LMT_REGU_IC = 4,
PW_LMT_REGU_KCC = 5,
PW_LMT_REGU_ACMA = 6,
PW_LMT_REGU_CHILE = 7,
PW_LMT_REGU_UKRAINE = 8,
PW_LMT_REGU_MEXICO = 9,
PW_LMT_REGU_CN = 10
};
enum odm_pw_lmt_band_type {
PW_LMT_BAND_2_4G = 0,
PW_LMT_BAND_5G = 1
};
enum odm_pw_lmt_bandwidth_type {
PW_LMT_BW_20M = 0,
PW_LMT_BW_40M = 1,
PW_LMT_BW_80M = 2,
PW_LMT_BW_160M = 3
};
enum odm_pw_lmt_ratesection_type {
PW_LMT_RS_CCK = 0,
PW_LMT_RS_OFDM = 1,
PW_LMT_RS_HT = 2,
PW_LMT_RS_VHT = 3
};
enum odm_pw_lmt_rfpath_type {
PW_LMT_PH_1T = 0,
PW_LMT_PH_2T = 1,
PW_LMT_PH_3T = 2,
PW_LMT_PH_4T = 3
};
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define boolean bool
#define true _TRUE
#define false _FALSE
// for power limit table
enum odm_pw_lmt_regulation_type {
PW_LMT_REGU_NULL = 0,
PW_LMT_REGU_FCC = 1,
PW_LMT_REGU_ETSI = 2,
PW_LMT_REGU_MKK = 3,
PW_LMT_REGU_WW13 = 4
};
enum odm_pw_lmt_band_type {
PW_LMT_BAND_NULL = 0,
PW_LMT_BAND_2_4G = 1,
PW_LMT_BAND_5G = 2
};
enum odm_pw_lmt_bandwidth_type {
PW_LMT_BW_NULL = 0,
PW_LMT_BW_20M = 1,
PW_LMT_BW_40M = 2,
PW_LMT_BW_80M = 3
};
enum odm_pw_lmt_ratesection_type {
PW_LMT_RS_NULL = 0,
PW_LMT_RS_CCK = 1,
PW_LMT_RS_OFDM = 2,
PW_LMT_RS_HT = 3,
PW_LMT_RS_VHT = 4
};
enum odm_pw_lmt_rfpath_type {
PW_LMT_PH_NULL = 0,
PW_LMT_PH_1T = 1,
PW_LMT_PH_2T = 2,
PW_LMT_PH_3T = 3,
PW_LMT_PH_4T = 4
};
#define phydm_timer_list timer_list
#endif
#define READ_NEXT_PAIR(v1, v2, i) do { if (i + 2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i + 1]; } while (0)
#define COND_ELSE 2
#define COND_ENDIF 3
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK7BITS 0x7f
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASK20BITS 0xfffff
#define MASK24BITS 0xffffff
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#define RFREGOFFSETMASK 0xfffff
#define RFREG_MASK 0xfffff
#define MASKH3BYTES 0xffffff00
#define MASKL3BYTES 0x00ffffff
#define MASKBYTE2HIGHNIBBLE 0x00f00000
#define MASKBYTE3LOWNIBBLE 0x0f000000
#define MASKL3BYTES 0x00ffffff
#endif /* __ODM_TYPES_H__ */

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/******************************************************************************
*
* Copyright(c) Semiconductor - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_RA_H
#define __INC_RA_H
/* rate adaptive define */
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
#define DM_RA_RATE_UP 1
#define DM_RA_RATE_DOWN 2
#define AP_USB_SDIO ((DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)))
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
/*
* TX report 2 format in Rx desc
* */
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc, 0, 9)
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc + 16, 0, 32)
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__prx_status_desc) LE_BITS_TO_4BYTE(__prx_status_desc + 20, 0, 32)
#define GET_TX_REPORT_TYPE1_RERTY_0(__paddr) LE_BITS_TO_4BYTE(__paddr, 0, 16)
#define GET_TX_REPORT_TYPE1_RERTY_1(__paddr) LE_BITS_TO_1BYTE(__paddr + 2, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_2(__paddr) LE_BITS_TO_1BYTE(__paddr + 3, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_3(__paddr) LE_BITS_TO_1BYTE(__paddr + 4, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_4(__paddr) LE_BITS_TO_1BYTE(__paddr + 4 + 1, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_0(__paddr) LE_BITS_TO_1BYTE(__paddr + 4 + 2, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_1(__paddr) LE_BITS_TO_1BYTE(__paddr + 4 + 3, 0, 8)
#endif
enum phydm_rateid_idx_88e_e { /*Copy From SD4 _RATR_TABLE_MODE*/
PHYDM_RAID_88E_NGB = 0, /* BGN 40 Mhz 2SS 1SS */
PHYDM_RAID_88E_NG = 1, /* GN or N */
PHYDM_RAID_88E_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */
PHYDM_RAID_88E_N = 3,
PHYDM_RAID_88E_GB = 4,
PHYDM_RAID_88E_G = 5,
PHYDM_RAID_88E_B = 6,
PHYDM_RAID_88E_MC = 7,
PHYDM_RAID_88E_AC_N = 8
};
/* End rate adaptive define */
extern void phydm_tx_stats_rst(struct dm_struct *dm);
void odm_ra_support_init(struct dm_struct *dm);
void odm_ra_info_init_all(struct dm_struct *dm);
int odm_ra_info_init(struct dm_struct *dm, u32 mac_id);
u8 odm_ra_get_sgi_8188e(struct dm_struct *dm, u8 mac_id);
u8 odm_ra_get_decision_rate_8188e(struct dm_struct *dm, u8 mac_id);
u8 odm_ra_get_hw_pwr_status_8188e(struct dm_struct *dm, u8 mac_id);
u8 phydm_get_rate_id_88e(void *dm_void, u8 macid);
void phydm_ra_update_8188e(struct dm_struct *dm, u8 mac_id, u8 rate_id,
u32 rate_mask, u8 sgi_enable);
void odm_ra_set_rssi_8188e(struct dm_struct *dm, u8 mac_id, u8 rssi);
void odm_ra_tx_rpt2_handle_8188e(struct dm_struct *dm, u8 *tx_rpt_buf,
u16 tx_rpt_len, u32 mac_id_valid_entry0,
u32 mac_id_valid_entry1);
void odm_ra_set_tx_rpt_time(struct dm_struct *dm, u16 min_rpt_time);
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* File Name: hal8188ereg.h
*
* Description:
*
* This file is for RTL8188E register definition.
*
*
* ************************************************************ */
#ifndef __HAL_8188E_REG_H__
#define __HAL_8188E_REG_H__
/*
* Register Definition
* */
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8188E 0xc50
#define REG_GPIO_EXT_CTRL 0x0060
#define REG_MCUFWDL_8188E 0x0080
#define REG_FW_DBG_STATUS_8188E 0x0088
#define REG_FW_DBG_CTRL_8188E 0x008F
#define REG_CR_8188E 0x0100
/*
* Bitmap Definition
* */
#define BIT_FA_RESET_8188E BIT(0)
#define REG_ADAPTIVE_DATA_RATE_0 0x2B0
#define REG_DBI_WDATA_8188 0x0348 /* DBI Write data */
#define REG_DBI_RDATA_8188 0x034C /* DBI Read data */
#define REG_DBI_ADDR_8188 0x0350 /* DBI Address */
#define REG_DBI_FLAG_8188 0x0352 /* DBI Read/Write Flag */
#define REG_MDIO_WDATA_8188E 0x0354 /* MDIO for Write PCIE PHY */
#define REG_MDIO_RDATA_8188E 0x0356 /* MDIO for Reads PCIE PHY */
#define REG_MDIO_CTL_8188E 0x0358 /* MDIO for Control */
/* [0-63] */
#define REG_MACID_NO_LINK 0x484 /* No Link register (bit[x] enabled means dropping packets for MACID in HW queue) */
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 3.5.2*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8188E_H
#define __INC_MP_BB_HW_IMG_8188E_H
/******************************************************************************
* agc_tab.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_agc_tab( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_agc_tab(void);
/******************************************************************************
* phy_reg.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_phy_reg( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_phy_reg(void);
/******************************************************************************
* phy_reg_pg.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_phy_reg_pg( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_phy_reg_pg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 3.5.2*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
static boolean
check_positive(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((dm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/
((dm->board_type & BIT(1)) >> 1) << 5 | /* _NGFF*/
((dm->board_type & BIT(5)) >> 5) << 6; /* _TRSWT*/
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u8 cut_version_for_para = (dm->cut_version == ODM_CUT_A) ? 15 : dm->cut_version;
u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type;
u32 driver1 = cut_version_for_para << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
pkg_type_for_para << 12 |
(dm->support_interface & 0x0F) << 8 |
_board_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> %s (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n",
__func__, driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n",
dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Board, Package) = (0x%X, 0x%X)\n", dm->board_type,
dm->package_type);
/*============== value Defined Check ===============*/
/*QFN type [15:12] and cut version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u32 bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
u32 array_mp_8188e_mac_reg[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0x80000002, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000001, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000002, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0xA0000000, 0x00000000,
0x040, 0x00000000,
0xB0000000, 0x00000000,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000001,
0x432, 0x00000002,
0x433, 0x00000004,
0x434, 0x00000005,
0x435, 0x00000006,
0x436, 0x00000007,
0x437, 0x00000008,
0x438, 0x00000000,
0x439, 0x00000000,
0x43A, 0x00000001,
0x43B, 0x00000002,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000006,
0x43F, 0x00000007,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000015,
0x445, 0x000000F0,
0x446, 0x0000000F,
0x447, 0x00000000,
0x458, 0x00000041,
0x459, 0x000000A8,
0x45A, 0x00000072,
0x45B, 0x000000B9,
0x460, 0x00000066,
0x461, 0x00000066,
0x480, 0x00000008,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4D3, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x63C, 0x00000008,
0x63D, 0x00000008,
0x63E, 0x0000000C,
0x63F, 0x0000000C,
0x640, 0x00000040,
0x652, 0x00000020,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
void
odm_read_and_config_mp_8188e_mac_reg(struct dm_struct *dm)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8188e_mac_reg) / sizeof(u32);
u32 *array = array_mp_8188e_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> %s\n", __func__);
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_mac_8188e(dm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8188e_mac_reg(void)
{
return 71;
}
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 3.5.2*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8188E_H
#define __INC_MP_MAC_HW_IMG_8188E_H
/******************************************************************************
* mac_reg.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_mac_reg( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 3.5.2*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8188E_H
#define __INC_MP_RF_HW_IMG_8188E_H
/******************************************************************************
* radioa.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_radioa( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_radioa(void);
/******************************************************************************
* txpowertrack_ap.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_ap( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpowertrack_ap(void);
/******************************************************************************
* txpowertrack_pcie.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_pcie( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpowertrack_pcie(void);
/******************************************************************************
* txpowertrack_pcie_icut.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_pcie_icut(
/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpowertrack_pcie_icut(void);
/******************************************************************************
* txpowertrack_sdio.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_sdio( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpowertrack_sdio(void);
/******************************************************************************
* txpowertrack_sdio_icut.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_sdio_icut(
/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpowertrack_sdio_icut(void);
/******************************************************************************
* txpowertrack_usb.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_usb( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpowertrack_usb(void);
/******************************************************************************
* txpowertrack_usb_icut.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpowertrack_usb_icut(
/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpowertrack_usb_icut(void);
/******************************************************************************
* txpwr_lmt.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpwr_lmt( /* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpwr_lmt(void);
/******************************************************************************
* txpwr_lmt_88ee_m2_for_msi.TXT
******************************************************************************/
void
odm_read_and_config_mp_8188e_txpwr_lmt_88ee_m2_for_msi(
/* tc: Test Chip, mp: mp Chip*/
struct dm_struct *dm);
u32 odm_get_version_mp_8188e_txpwr_lmt_88ee_m2_for_msi(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void odm_config_rf_reg_8188e(struct dm_struct *dm, u32 addr, u32 data,
enum rf_path RF_PATH, u32 reg_addr)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifndef SMP_SYNC
unsigned long x;
#endif
struct rtl8192cd_priv *priv = dm->priv;
#endif
if (addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
SAVE_INT_AND_CLI(x);
odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
RESTORE_INT(x);
#else
odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
#endif
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
void odm_config_rf_radio_a_8188e(struct dm_struct *dm, u32 addr, u32 data)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
addr, data);
}
void odm_config_rf_radio_b_8188e(struct dm_struct *dm, u32 addr, u32 data)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8188e(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
addr, data);
}
void odm_config_mac_8188e(struct dm_struct *dm, u32 addr, u8 data)
{
odm_write_1byte(dm, addr, data);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
addr, data);
}
void odm_config_bb_agc_8188e(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data)
{
odm_set_bb_reg(dm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n",
addr, data);
}
void odm_config_bb_phy_reg_pg_8188e(struct dm_struct *dm, u32 band, u32 rf_path,
u32 tx_num, u32 addr, u32 bitmask, u32 data)
{
if (addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
addr, bitmask, data);
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#endif
}
}
void odm_config_bb_txpwr_lmt_8188e(struct dm_struct *dm, u8 *regulation,
u8 *band, u8 *bandwidth, u8 *rate_section,
u8 *rf_path, u8 *channel, u8 *power_limit)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_set_tx_power_limit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_SetTxPowerLimit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#endif
}
void odm_config_bb_phy_8188e(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data)
{
if (addr == 0xfe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
if (addr == 0xa24)
dm->rf_calibrate_info.rega24 = data;
odm_set_bb_reg(dm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n",
addr, data);
}
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E
#if (RTL8188E_SUPPORT == 1)
void odm_config_rf_reg_8188e(struct dm_struct *dm, u32 addr, u32 data,
enum rf_path RF_PATH, u32 reg_addr);
void odm_config_rf_radio_a_8188e(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_rf_radio_b_8188e(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_mac_8188e(struct dm_struct *dm, u32 addr, u8 data);
void odm_config_bb_agc_8188e(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_phy_reg_pg_8188e(struct dm_struct *dm, u32 band, u32 rf_path,
u32 tx_num, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_phy_8188e(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_txpwr_lmt_8188e(struct dm_struct *dm, u8 *regulation,
u8 *band, u8 *bandwidth, u8 *rate_section,
u8 *rf_path, u8 *channel, u8 *power_limit);
#endif
#endif /* end of SUPPORT */

58
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
s8 phydm_cck_rssi_8188e(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
{
s8 rx_pwr_all = 0;
s8 lna_gain = 0;
/*only use lna0/1/2/3/7*/
s8 lna_gain_table_0[8] = {17, -1, -13, 0, -32, -35, -38, -36};
/*only use lna3 /7*/
s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33};
/*only use lna1/3/5/7*/
s8 lna_gain_table_2[8] = {17, -1, -13, -17, -32, -43, -38, -47};
if (dm->cut_version >= ODM_CUT_I) { /*SMIC*/
if (dm->ext_lna == 0x1) {
switch (dm->type_glna) {
case 0x2: /*eLNA 14dB*/
lna_gain = lna_gain_table_2[lna_idx];
break;
default:
lna_gain = lna_gain_table_0[lna_idx];
break;
}
} else {
lna_gain = lna_gain_table_0[lna_idx];
}
} else { /*TSMC*/
lna_gain = lna_gain_table_1[lna_idx];
}
rx_pwr_all = lna_gain - (2 * vga_idx);
return rx_pwr_all;
}
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __ODM_RTL8188E_H__
#define __ODM_RTL8188E_H__
#if (RTL8188E_SUPPORT == 1)
s8 phydm_cck_rssi_8188e(struct dm_struct *dm, u16 lna_idx, u8 vga_idx);
#endif
#endif

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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
/*RTL8188E PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified.
You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8188E 20171218
#define COMMIT_BY_8188E "RF_Eason"
#define RELEASE_VERSION_8188E 71

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EXTRA_CFLAGS += -I$(src)/hal/phydm
_PHYDM_FILES := hal/phydm/phydm_debug.o \
hal/phydm/phydm_interface.o\
hal/phydm/phydm_phystatus.o\
hal/phydm/phydm_hwconfig.o\
hal/phydm/phydm.o\
hal/phydm/phydm_dig.o\
hal/phydm/phydm_rainfo.o\
hal/phydm/phydm_adaptivity.o\
hal/phydm/phydm_cfotracking.o\
hal/phydm/phydm_noisemonitor.o\
hal/phydm/phydm_beamforming.o\
hal/phydm/phydm_dfs.o\
hal/phydm/txbf/halcomtxbf.o\
hal/phydm/txbf/haltxbfinterface.o\
hal/phydm/txbf/phydm_hal_txbf_api.o\
hal/phydm/phydm_ccx.o\
hal/phydm/phydm_cck_pd.o\
hal/phydm/phydm_rssi_monitor.o\
hal/phydm/phydm_math_lib.o\
hal/phydm/phydm_api.o\
hal/phydm/halrf/halrf.o\
hal/phydm/halrf/halrf_debug.o\
hal/phydm/halrf/halphyrf_ce.o\
hal/phydm/halrf/halrf_powertracking_ce.o\
hal/phydm/halrf/halrf_powertracking.o\
hal/phydm/halrf/halrf_kfree.o
ifeq ($(CONFIG_RTL8188E), y)
RTL871X = rtl8188e
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188e_mac.o\
hal/phydm/$(RTL871X)/halhwimg8188e_bb.o\
hal/phydm/$(RTL871X)/halhwimg8188e_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8188e_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8188e.o\
hal/phydm/$(RTL871X)/hal8188erateadaptive.o\
hal/phydm/$(RTL871X)/phydm_rtl8188e.o
endif
ifeq ($(CONFIG_RTL8192E), y)
RTL871X = rtl8192e
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192e_mac.o\
hal/phydm/$(RTL871X)/halhwimg8192e_bb.o\
hal/phydm/$(RTL871X)/halhwimg8192e_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8192e_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8192e.o\
hal/phydm/$(RTL871X)/phydm_rtl8192e.o
endif
ifeq ($(CONFIG_RTL8812A), y)
RTL871X = rtl8812a
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8812a_mac.o\
hal/phydm/$(RTL871X)/halhwimg8812a_bb.o\
hal/phydm/$(RTL871X)/halhwimg8812a_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_8812a_ce.o\
hal/phydm/$(RTL871X)/phydm_regconfig8812a.o\
hal/phydm/$(RTL871X)/phydm_rtl8812a.o\
hal/phydm/txbf/haltxbfjaguar.o
endif
ifeq ($(CONFIG_RTL8821A), y)
RTL871X = rtl8821a
_PHYDM_FILES += hal/phydm/rtl8821a/halhwimg8821a_mac.o\
hal/phydm/rtl8821a/halhwimg8821a_bb.o\
hal/phydm/rtl8821a/halhwimg8821a_rf.o\
hal/phydm/halrf/rtl8812a/halrf_8812a_ce.o\
hal/phydm/halrf/rtl8821a/halrf_8821a_ce.o\
hal/phydm/rtl8821a/phydm_regconfig8821a.o\
hal/phydm/rtl8821a/phydm_rtl8821a.o\
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.o\
hal/phydm/txbf/haltxbfjaguar.o
endif
ifeq ($(CONFIG_RTL8723B), y)
RTL871X = rtl8723b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8723b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8723b_rf.o\
hal/phydm/$(RTL871X)/halhwimg8723b_mp.o\
hal/phydm/$(RTL871X)/phydm_regconfig8723b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8723b_ce.o\
hal/phydm/$(RTL871X)/phydm_rtl8723b.o
endif
ifeq ($(CONFIG_RTL8814A), y)
RTL871X = rtl8814a
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8814a_bb.o\
hal/phydm/$(RTL871X)/halhwimg8814a_mac.o\
hal/phydm/$(RTL871X)/halhwimg8814a_rf.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8814a.o\
hal/phydm/$(RTL871X)/phydm_regconfig8814a.o\
hal/phydm/halrf/$(RTL871X)/halrf_8814a_ce.o\
hal/phydm/$(RTL871X)/phydm_rtl8814a.o\
hal/phydm/txbf/haltxbf8814a.o
endif
ifeq ($(CONFIG_RTL8723C), y)
RTL871X = rtl8703b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8703b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8703b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8703b_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8703b.o\
hal/phydm/$(RTL871X)/phydm_rtl8703b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8703b.o
endif
ifeq ($(CONFIG_RTL8723D), y)
RTL871X = rtl8723d
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8723d_bb.o\
hal/phydm/$(RTL871X)/halhwimg8723d_mac.o\
hal/phydm/$(RTL871X)/halhwimg8723d_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8723d.o\
hal/phydm/$(RTL871X)/phydm_rtl8723d.o\
hal/phydm/halrf/$(RTL871X)/halrf_8723d.o
endif
ifeq ($(CONFIG_RTL8710B), y)
RTL871X = rtl8710b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8710b_bb.o\
hal/phydm/$(RTL871X)/halhwimg8710b_mac.o\
hal/phydm/$(RTL871X)/halhwimg8710b_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8710b.o\
hal/phydm/$(RTL871X)/phydm_rtl8710b.o\
hal/phydm/halrf/$(RTL871X)/halrf_8710b.o
endif
ifeq ($(CONFIG_RTL8188F), y)
RTL871X = rtl8188f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8188f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8188f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8188f_rf.o\
hal/phydm/$(RTL871X)/phydm_regconfig8188f.o\
hal/phydm/halrf/$(RTL871X)/halrf_8188f.o \
hal/phydm/$(RTL871X)/phydm_rtl8188f.o
endif
ifeq ($(CONFIG_RTL8822B), y)
RTL871X = rtl8822b
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8822b_bb.o \
hal/phydm/$(RTL871X)/halhwimg8822b_mac.o \
hal/phydm/$(RTL871X)/halhwimg8822b_rf.o \
hal/phydm/halrf/$(RTL871X)/halrf_8822b.o \
hal/phydm/$(RTL871X)/phydm_hal_api8822b.o \
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8822b.o \
hal/phydm/halrf/$(RTL871X)/halrf_rfk_init_8822b.o \
hal/phydm/$(RTL871X)/phydm_regconfig8822b.o \
hal/phydm/$(RTL871X)/phydm_rtl8822b.o
_PHYDM_FILES += hal/phydm/txbf/haltxbf8822b.o
endif
ifeq ($(CONFIG_RTL8821C), y)
RTL871X = rtl8821c
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8821c_bb.o \
hal/phydm/$(RTL871X)/halhwimg8821c_mac.o \
hal/phydm/$(RTL871X)/halhwimg8821c_rf.o \
hal/phydm/$(RTL871X)/phydm_hal_api8821c.o \
hal/phydm/$(RTL871X)/phydm_regconfig8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_8821c.o\
hal/phydm/halrf/$(RTL871X)/halrf_iqk_8821c.o
endif
ifeq ($(CONFIG_RTL8192F), y)
RTL871X = rtl8192f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8192f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8192f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8192f_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8192f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8192f.o\
hal/phydm/$(RTL871X)/phydm_rtl8192f.o\
hal/phydm/halrf/$(RTL871X)/halrf_8192f.o
endif
ifeq ($(CONFIG_RTL8198F), y)
RTL871X = rtl8198f
_PHYDM_FILES += hal/phydm/$(RTL871X)/halhwimg8198f_bb.o\
hal/phydm/$(RTL871X)/halhwimg8198f_mac.o\
hal/phydm/$(RTL871X)/halhwimg8198f_rf.o\
hal/phydm/$(RTL871X)/phydm_hal_api8198f.o\
hal/phydm/$(RTL871X)/phydm_regconfig8198f.o
endif